Semiconductor device and power conversion device

Abstract

This semiconductor device is formed using a gallium oxide semiconductor layer (20). A plurality of trenches (5) are provided in a first main face of the gallium oxide semiconductor layer (20). A gate insulation film (6) is provided on the inner surfaces of the trenches (5). A gate electrode (7) is provided on the gate insulation film (6) so as to be embedded in the trenches (5). The primary side surfaces of the trenches (5) are a (010) plane of the gallium oxide semiconductor layer (20).

Description

Semiconductor device and power conversion device

[0001] The present disclosure relates to a semiconductor device and a power conversion device, and more particularly to a semiconductor device made of gallium oxide and a power conversion device to which the same is applied.

[0002] Gallium oxide (Ga ２ O ３ ) has a band gap exceeding that of silicon carbide (SiC) and gallium nitride (GaN), and is an advantageous material for increasing the breakdown voltage and decreasing the resistance of power devices. ２ O ３ is expected to be a material for next-generation power devices.

[0003] On the other hand, in order to manufacture a vertical transistor with excellent power efficiency, it is essential to suppress the punch-through current that flows between the source and drain. In existing power devices, the punch-through current is suppressed by the potential barrier of the pn junction. ２ O ３ In the case where a p-type conductive layer or a layer having a deep acceptor level (pseudo p-layer) capable of forming a desired potential barrier is not obtained, punch-through current is likely to flow.

[0004] Regarding this problem, Patent Document 1 below employs a FinFET (Fin Field-Effect Transistor) structure that physically narrows the current path as a means for suppressing punch-through current. Patent Document 1 also discloses a method for suppressing leakage current by specifying the fin width, donor concentration, electrode work function, etc.

[0005] International Publication No. 2021 / 131891

[0006] Ga ２ O ３ From the above problems, Ga ２ O ３ In semiconductor devices made of such materials, it is difficult to obtain a high On / Off ratio (ratio of current values ​​in a conducting state to that in a cutoff state).

[0007] On the other hand, in FinFETs and trench-gate MOSFETs (hereinafter referred to as "trench MOSFETs") having a similar structure, various channel plane orientations can be selected by adjusting the arrangement angle of an etching mask (hereinafter referred to as "trench mask") when forming a trench in a substrate. ２ O ３ , especially β-type gallium oxide (β-Ga ２ O ３ ) is very sensitive to the channel plane orientation, and it was found that the on / off ratio of the transistor changes significantly depending on the combination of the trench mask placement angle and the type of gate insulating film.

[0008] The present disclosure has been made to solve the above-mentioned problems, and aims to obtain a high On / Off ratio in a semiconductor device using gallium oxide as a material.

[0009] The semiconductor device according to the present disclosure includes a gallium oxide semiconductor layer, a plurality of trenches provided on a first main surface of the gallium oxide semiconductor layer and having a (010) plane of the gallium oxide semiconductor layer as a main side surface, a gate insulating film provided on an inner surface of the trench, and a gate electrode provided on the gate insulating film and embedded in the trench.

[0010] According to the present disclosure, a high On / Off ratio can be obtained in a semiconductor device using gallium oxide as a material.

[0011] The objects, features, aspects, and advantages of the present disclosure will become more apparent from the following detailed description and the accompanying drawings.

[0012] FIG. 1 is a cross-sectional view showing the structure of a unit cell of a semiconductor element in a semiconductor device according to a first embodiment. FIG. 2 is an explanatory diagram of a manufacturing method of a semiconductor device according to a first embodiment. FIG. 3 is an explanatory diagram of a manufacturing method of a semiconductor device according to a first embodiment. FIG. 4 is an explanatory diagram of a manufacturing method of a semiconductor device according to a first embodiment. FIG. 5 is an explanatory diagram of a manufacturing method of a semiconductor device according to a first embodiment. FIG. 6 is an explanatory diagram of a manufacturing method of a semiconductor device according to a first embodiment. FIG. 7 is an explanatory diagram of a manufacturing method of a semiconductor device according to a first embodiment. FIG. 8 is an explanatory diagram of a manufacturing method of a semiconductor device according to a first embodiment. FIG. 9 is an explanatory diagram of a manufacturing method of a semiconductor device according to a first embodiment. FIG. 10 is a diagram showing the relationship between a trench angle and an On / Off ratio obtained in an experiment. FIG. 11 is a cross-sectional view showing the structure of a unit cell of a semiconductor element in a semiconductor device according to a second embodiment. FIG. 12 is a cross-sectional view showing the structure of a unit cell of a semiconductor element in a semiconductor device according to a third embodiment. FIG. 13 is a block diagram showing the configuration of a power conversion system to which a power conversion device according to a fourth embodiment is applied.

[0013] Hereinafter, embodiments of the technology according to the present disclosure will be described with reference to the drawings. The present technology is not limited to the embodiments shown here, and can be modified as appropriate without departing from the spirit of the technology. In addition, in the drawings shown below, the scale of each component or each component may differ from the actual scale in order to facilitate understanding.

[0014] First Embodiment FIG. 1 is a diagram showing the configuration of a semiconductor device according to a first embodiment, and is a cross-sectional view showing the structure of a unit cell of a semiconductor element included in the semiconductor device. A plurality of unit cells shown in FIG. 1 are arranged in an active area of ​​the semiconductor device. In this embodiment, as an example of the semiconductor element, a β-type gallium oxide (β-Ga ２ O ３ 1 shows a vertical trench MOSFET made of SiO 2 .

[0015] The semiconductor device according to the first embodiment is a β-Ga ２ O ３The gallium oxide semiconductor layer 20 is formed using a gallium oxide semiconductor layer 20 consisting of an n-type gallium oxide substrate 1, a first gallium oxide layer 2 provided on the n-type gallium oxide substrate 1, a second gallium oxide layer 3 provided on the first gallium oxide layer 2, and a third gallium oxide layer 4 provided on the second gallium oxide layer 3. The upper surface of the gallium oxide semiconductor layer 20 in FIG. 1 (the upper surface of the third gallium oxide layer 4) is defined as the "first main surface," and the lower surface of the gallium oxide semiconductor layer 20 (the lower surface of the n-type gallium oxide substrate 1) is defined as the "second main surface." Here, the gallium oxide semiconductor layer 20 may be formed by forming epitaxially grown layers on a semiconductor substrate other than the n-type gallium oxide substrate 1 and then separating the semiconductor substrate, and the resulting first gallium oxide layer 2, second gallium oxide layer 3, and third gallium oxide layer 4.

[0016] The n-type gallium oxide substrate 1 is an n-type β-Ga substrate having a (001) plane as its principal surface. ２ O ３ The conductive substrate is made of

[0017] The first gallium oxide layer 2 contains at least one of silicon, chlorine, tin, and germanium, which are n-type dopants, in an amount of 1×10 １６ cm －３ It is added at a moderate concentration.

[0018] The second gallium oxide layer 3 contains 1×10 １８ cm －３ Candidates for acceptor-type impurities include, for example, nitrogen, magnesium, zinc, and phosphorus.

[0019] The third gallium oxide layer 4 contains at least one of silicon, chlorine, tin, and germanium, which are n-type dopants, at a concentration of 5×10 １９ cm －３ It is added at a moderate concentration.

[0020] A plurality of trenches 5 are formed in a stripe pattern on the first main surface of the gallium oxide semiconductor layer 20. That is, each trench 5 extends in parallel with the adjacent trenches 5.

[0021] The main side surface of the trench 5 is the (010) plane. The bottom of the trench 5 reaches the first gallium oxide layer 2. The side surface of the trench 5 is in contact with all of the first gallium oxide layer 2, the second gallium oxide layer 3, and the third gallium oxide layer 4. Here, the main side surface of the trench 5, i.e., the channel surface, being the (010) plane means that the main side surface is a plane that is not deviated from the (010) plane or that is slightly deviated from the (010) plane. Based on the explanation of FIG. 11 described later, a semiconductor device with a high On / Off ratio can be obtained even if the main side surface is deviated from the (010) plane by an angle of 50 degrees or less in the

[010] direction, and particularly even if the main side surface is deviated by an angle of 30 degrees or less in the

[010] direction.

[0022] A gate insulating film 6 is formed on the inner surface of the trench 5. A gate electrode 7 is formed on the gate insulating film 6 so as to be buried in the trench 5. The gate insulating film 6 is made of alumina (Al ２ O ３ The gate electrode 7 is preferably made of polysilicon, and in particular, contains a high concentration p-type (p ＋ It is more preferable that the gate electrode is formed of polysilicon (type).

[0023] An interlayer insulating film 8 is formed on the first main surface of the gallium oxide semiconductor layer 20 so as to cover the gate electrode 7. A source electrode 10 is formed on the interlayer insulating film 8. The gate electrode 7 and the source electrode 10 are electrically isolated from each other by the interlayer insulating film 8.

[0024] A contact hole 9 is formed in the interlayer insulating film 8, reaching the gallium oxide semiconductor layer 20, and the source electrode 10 is electrically connected to the third gallium oxide layer 4 of the gallium oxide semiconductor layer 20 through the contact hole 9. As shown in Figure 1, a recess 12 is formed in the gallium oxide semiconductor layer 20 (third gallium oxide layer 4) at the bottom of the contact hole 9, and the source electrode 10 is connected to the third gallium oxide layer 4 within the recess 12.

[0025] A drain electrode 11 is formed on the second main surface of the gallium oxide semiconductor layer 20. The drain electrode 11 is electrically connected to the n-type gallium oxide substrate 1.

[0026] Next, an example of a method for manufacturing the semiconductor device according to the first embodiment will be described with reference to FIGS.

[0027] First, a conductive n-type gallium oxide substrate 1 having a (001) plane as its principal surface is prepared. Then, as shown in FIG. 2 , a first gallium oxide layer 2 is formed on the n-type gallium oxide substrate 1 using a halide vapor phase epitaxy (HVPE) method, a metal organic chemical vapor deposition (MOCVD) method, a molecular beam epitaxy (MBE) method, or the like. This results in a gallium oxide semiconductor layer 20 consisting of the n-type gallium oxide substrate 1 and the first gallium oxide layer 2. The thickness of the n-type gallium oxide substrate 1 is about 10 μm, and the donor concentration of the n-type gallium oxide substrate 1 is 1×10 １６ cm －３ That's about it.

[0028] Next, an implantation mask is formed on the first main surface of the gallium oxide semiconductor layer 20 (on the upper surface of the first gallium oxide layer 2), and then at least one dopant among dopants that form acceptor levels, such as nitrogen, zinc, phosphorus, and magnesium, is ion-implanted into the gallium oxide semiconductor layer 20. The implantation energy at this time is about 20 keV to 500 keV, and the dose is 1×10 １４ cm －２ To mitigate damage caused by ion implantation, a heated implantation method or a thermal diffusion method may be used.

[0029] After removing the implantation mask, a heat treatment is performed to recover damage caused by the dopant implantation and to activate the dopant. The heat treatment temperature is about 800°C to 1200°C, and the heat treatment atmosphere is nitrogen, oxygen, or a mixture thereof. As a result, a second gallium oxide layer 3 having a depth of about 700 nm is formed on the surface of the first gallium oxide layer 2.

[0030] Subsequently, an implantation mask is formed on the first main surface of the gallium oxide semiconductor layer 20 (on the upper surface of the second gallium oxide layer 3), and then Si (silicon) ions are implanted into the gallium oxide semiconductor layer 20. The implantation energy at this time is about 10 keV to 200 keV, and the dose is 1×10 １５ cm －２After the implantation mask is removed, a heat treatment is performed at a temperature of about 900° C. to recover from damage caused by the ion implantation and to activate the dopant. As a result, a third gallium oxide layer 4 having a depth of about 200 nm is formed on the surface of the second gallium oxide layer 3.

[0031] As a result, as shown in FIG. 3, a gallium oxide semiconductor layer 20 is formed, which is composed of an n-type gallium oxide substrate 1, a first gallium oxide layer 2, a second gallium oxide layer 3, and a third gallium oxide layer 4.

[0032] Next, a stripe-shaped etching mask extending in the

[100] direction of the gallium oxide semiconductor layer 20 is formed on the first principal surface of the gallium oxide semiconductor layer 20, and then the gallium oxide semiconductor layer 20 is dry-etched using an ICP (Inductively Coupled Plasma)-RIE (Reactive Ion Etching) apparatus to form trenches 5 in the gallium oxide semiconductor layer 20, as shown in FIG. 4 . FIG. 5 shows a top view of the gallium oxide semiconductor layer 20 with the trenches 5 formed therein. As shown in FIG. 5 , trenches 5 having (010) planes as their main side surfaces are formed in the gallium oxide semiconductor layer 20. Suitable etching gases include Cl and BCl3. The depth of the trenches 5 is approximately 1 μm. The trenches 5 penetrate the third gallium oxide layer 4 and the second gallium oxide layer 3 to reach the first gallium oxide layer 2.

[0033] The etching mask is removed, and the gallium oxide semiconductor layer 20 is subjected to RCA cleaning. Then, Al is applied to the inner surface of the trench 5. ２ O ３ The gate insulating film 6 is formed on the first main surface of the gallium oxide semiconductor layer 20. ２ O ３ The film may be formed by atomic layer deposition (ALD). The gate insulating film 6 may have a multi-layer structure, for example, SiO ２ , HfO ２ , AlON, AlN, SiN, SiON ２ O ３ It is assumed that the stacked film of these is used as the gate insulating film 6.

[0034] 6, a gate electrode 7 is formed on the gate insulating film 6. The film type of the gate electrode 7 is, for example, a high concentration p-type (p ＋ A polysilicon film of the type (type) is suitable.

[0035] In the trench MOSFET of this embodiment, the second gallium oxide layer 3 doped with acceptor-type impurities serves as a channel portion. By doping the channel portion with acceptor-type impurities, the threshold voltage can be set higher than when the channel portion is composed of only an n-type layer. Furthermore, when the gate electrode 7 is p ＋ When the gate electrode 7 is made of n-type polysilicon, ＋ Compared to a structure using polysilicon, the threshold voltage can be increased by about 1 V. These synergistic effects make the trench MOSFET of this embodiment a device that is resistant to surge voltages.

[0036] Subsequently, the gate electrode 7 and the gate insulating film 6 are etched back using a chlorine-based gas to remove the gate electrode 7 and the gate insulating film 6 on the first main surface of the gallium oxide semiconductor layer 20. As a result, the gate insulating film 6 and the gate electrode 7 embedded in the trench 5 are formed, as shown in FIG.

[0037] 8, an interlayer insulating film 8 is formed on the first main surface of the gallium oxide semiconductor layer 20. The interlayer insulating film 8 is made of SiO.sub.2, which has a large band gap and is less likely to cause leakage current. ２ It is known that the electric field generated at the interface between the semiconductor and the insulating film is affected by the relative dielectric constants of the semiconductor and the insulating film. ２ The dielectric constant of the film is 3.9, which is ２ O ３ Therefore, the interlayer insulating film 8 in contact with the gallium oxide semiconductor layer 20 is made of SiO ２ If the interlayer insulating film 8 is made of a gallium oxide semiconductor layer 20, an electric field nearly three times that of the gallium oxide semiconductor layer 20 will be applied to the interlayer insulating film 8. Therefore, from the viewpoint of breakdown resistance, the relative dielectric constant of the interlayer insulating film 8 is set to SiO ２However, in general, the dielectric constant and the band gap are inversely proportional to each other, and the larger the dielectric constant of a material, the smaller the band gap. Therefore, if the interlayer insulating film 8 is made of a material with a large dielectric constant, it is difficult to ensure a sufficient band offset with respect to the gallium oxide semiconductor layer 20. Therefore, the interlayer insulating film 8 is preferably made of a material with a dielectric constant of SiO ２ The lower layer is a high-k film with a larger band gap than the lower layer, and the SiO ２ A two-layer structure can be used in which a high-k film is placed on the upper layer. This allows for both high breakdown voltage and low leakage current. ２ , HfO ２ , Al ２ O ３ , BaTiO ３ , MgF ２ Possible reasons include:

[0038] 9, contact holes 9 are formed in the interlayer insulating film 8 by selective dry etching using photolithography. The contact holes 9 penetrate the interlayer insulating film 8 and reach the third gallium oxide layer 4. At this time, recesses 12 are formed in the gallium oxide semiconductor layer 20 (third gallium oxide layer 4) exposed at the bottom of the contact holes 9. By roughening the surface of the gallium oxide semiconductor layer 20 by dry etching, the β-Ga ions constituting the gallium oxide semiconductor layer 20 are removed. ２ O ３ Since the donor type defects in the source electrode 10 and the third gallium oxide layer 4 increase and the contact resistance decreases, the ohmic characteristics between the source electrode 10 and the third gallium oxide layer 4 improve.

[0039] Subsequently, as shown in FIG. 10, a source electrode 10 is formed on the interlayer insulating film 8, and a drain electrode 11 is formed on the second main surface of the gallium oxide semiconductor layer 20 (the lower surface of the n-type gallium oxide substrate 1).

[0040] The source electrode 10 is formed by depositing a metal film on the interlayer insulating film 8 using a sputtering device and then patterning the metal film by selective wet etching using photolithography. A Ti / Al laminated structure is suitable as the film type for the source electrode 10. The film thickness of the source electrode 10 is, for example, 20 nm for Ti and 3 μm for Al.

[0041] The drain electrode 11 is formed after removing the film that has spread onto the second main surface of the gallium oxide semiconductor layer 20 using a dry etcher or a grinding / polishing device. The drain electrode 11 is formed by depositing a Ti / Au electrode on the second main surface of the gallium oxide semiconductor layer 20 using a sputtering device or an EB deposition machine.

[0042] Finally, ohmic sintering is carried out to complete the semiconductor device.

[0043] The inventors of the technology according to the present disclosure fabricated vertical trench MOSFETs with different longitudinal angles of the trenches 5 relative to the

[010] direction (hereinafter referred to as "trench angles") and conducted an experiment to determine the relationship between the trench angle and the On / Off ratio. ２ O ３ This was carried out in the case where:

[0044] 11 is a graph showing the experimental results. The horizontal axis of the graph is the trench angle, and the vertical axis of the graph is the normalized On / Off ratio. The normalized On / Off ratio is obtained by adding Al to the gate insulating film 6. ２ O ３ is used, and the On / Off ratio is set to 1 when the longitudinal direction of the trench 5 is oriented in the

[010] direction (i.e., when the trench angle is 0 degrees). When the trench angle is 0 degrees, the longitudinal direction of the trench 5 is oriented in the

[010] direction, and the main side surface of the trench 5 is the (100) plane. When the trench angle is 90 degrees, the longitudinal direction of the trench 5 is oriented in the

[100] direction, and the main side surface of the trench 5 is the (010) plane.

[0045] Al ２ O ３When the gate insulating film 6 is made of a silicon nitride film, the On / Off ratio improves by nearly two orders of magnitude when the longitudinal direction of the trench 5 is oriented in the

[100] direction compared to when the longitudinal direction is oriented in the

[010] direction. Here, even when the trench angle is 40 degrees or more, i.e., the channel surface, which is the side surface of the trench 5, is offset from the (010) plane in the

[010] direction by an angle of 50 degrees or less, a high level of On / Off ratio is obtained. The effect is particularly significant when the trench angle is tilted by 60 degrees or more, i.e., when the channel surface is offset from the (010) plane in the

[010] direction by an angle of 30 degrees or less, or when there is no offset from the (010) plane, as described above. Furthermore, extrapolating the curves in FIG. 11 suggests that when the trench angle is 90 degrees or more, i.e., when the channel surface is offset from the (010) plane by a slight angle opposite to the

[010] direction, the On / Off ratio is unlikely to drop sharply, and a high level of On / Off ratio is obtained.

[0046] Trench arrangement methods can be broadly divided into mesh and stripe types. When using a mesh arrangement, using the (010) plane and the (100) plane, which have a good On / Off ratio, can easily result in large losses. Therefore, the mesh shape and dimensions should be selected so that the area ratio of the (100) plane to the (010) plane is small, in other words, so that the area of ​​the (010) plane is larger than the area of ​​the (100) plane. On the other hand, with a stripe trench arrangement, the (010) plane, which has a good On / Off ratio, can be used preferentially, which has a significant advantage when scaling (miniaturizing) the unit cell.

[0047] Furthermore, even if a planar DI-MOSFET (Double Implanted MOSFET) is fabricated by forming the main surface of the gallium oxide semiconductor layer as a (010) plane, the surface of the channel portion (hereinafter referred to as the "channel surface") can be made a (010) plane. However, it has been reported that a defect layer is formed on the surface of the substrate during activation annealing of the gallium oxide semiconductor layer, reducing the donor concentration at the substrate surface. When the donor concentration at the substrate surface decreases, the extension of the depletion layer in the DI-MOSFET is promoted in the region below the gate electrode, known as the "JFET region," and a potential barrier that cannot be controlled by the gate voltage is generated. This causes an offset in the Id-Vd characteristics of the DI-MOSFET, causing the DI-MOSFET to exhibit diode-like turn-on characteristics.

[0048] On the other hand, in the case of a trench MOSFET, since there is no JFET region, the characteristics do not deteriorate even if the donor concentration on the substrate surface is reduced by activation annealing. In other words, a trench MOSFET with a channel surface (side surface of the gate trench) in the (010) plane can achieve better characteristics than a DI-MOSFET with a channel surface in the (010) plane.

[0049] Second Preferred Embodiment FIG. 12 is a diagram showing the configuration of a semiconductor device according to a second preferred embodiment, and is a cross-sectional view showing the structure of a unit cell of a semiconductor element included in the semiconductor device.

[0050] In the semiconductor device according to the second embodiment, a recess 12 formed in the gallium oxide semiconductor layer 20 at the bottom of the contact hole 9 penetrates the third gallium oxide layer 4 and the second gallium oxide layer 3 and reaches the first gallium oxide layer 2. The other configurations are the same as those of the first embodiment.

[0051] In the semiconductor device according to the second embodiment, the source electrode 10 is connected to the first gallium oxide layer 2 via a Schottky junction. This allows a Schottky barrier diode (SBD) to be built into the MOSFET. Therefore, when the MOSFET is incorporated into an inverter, it is not necessary to provide an external freewheeling diode. This reduces the cost of inverter components.

[0052] Third Preferred Embodiment FIG. 13 is a diagram showing the configuration of a semiconductor device according to a third preferred embodiment, and is a cross-sectional view showing the structure of a unit cell of a semiconductor element included in the semiconductor device.

[0053] In the semiconductor device according to the third embodiment, an intermediate film 13 is interposed between a recess 12 formed in the gallium oxide semiconductor layer 20 at the bottom of the contact hole 9 and the source electrode 10. The other configurations are the same as those of the second embodiment.

[0054] The material of the intermediate film 13 is, for example, TiO2, β-Ga ２ O ３ It is preferable that the band gap of the intermediate film 13 is smaller than that of β-Ga. ２ O ３ If the β-GaAs is smaller than 1000 Ω, no barrier is created in the conduction band, and the forward characteristics of the SBD are not deteriorated. ２ O ３ However, by providing the intermediate film 13 between the gallium oxide semiconductor layer 20 and the source electrode 10, the reaction between the gallium oxide semiconductor layer 20 and the metal film is suppressed, improving temperature stability. Here, the intermediate film 13 may be made of a material having a higher dielectric constant than gallium oxide.

[0055] In this embodiment, an example in which the intermediate film 13 is applied to the semiconductor device of embodiment 2 (FIG. 12) has been shown, but the intermediate film 13 can also be applied to the semiconductor device of embodiment 1 (FIG. 1). In this case, the thickness of the intermediate film 13 may be determined appropriately depending on the material of the source electrode in the MOSFET, the donor species and donor concentration in the source region, etc., but it is preferably about 100 nm or less, particularly about 10 nm or less.

[0056] <Fourth Embodiment> In this embodiment, the semiconductor device according to any one of the above-described first to third embodiments is applied to a power conversion device. Although the application of the semiconductor device according to any one of the first to third embodiments is not limited to a specific power conversion device, the following will describe a case where the semiconductor device according to any one of the first to third embodiments is applied to a three-phase inverter as the fourth embodiment.

[0057] FIG. 14 is a block diagram showing the configuration of a power conversion system to which the power conversion device according to this embodiment is applied.

[0058] The power conversion system shown in Fig. 14 is composed of a power supply 100, a power conversion device 200, and a load 300. The power supply 100 is a DC power supply and supplies DC power to the power conversion device 200. The power supply 100 can be composed of various components, such as a DC system, a solar cell, or a storage battery, or it may be composed of a rectifier circuit connected to an AC system or an AC / DC converter. The power supply 100 may also be composed of a DC / DC converter that converts DC power output from a DC system into a predetermined power.

[0059] The power conversion device 200 is a three-phase inverter connected between the power source 100 and the load 300, and converts DC power supplied from the power source 100 into AC power and supplies the AC power to the load 300. As shown in Fig. 14 , the power conversion device 200 includes a main conversion circuit 201 that converts DC power into AC power and outputs it, a drive circuit 202 that outputs drive signals that drive each switching element of the main conversion circuit 201, and a control circuit 203 that outputs control signals to the drive circuit 202.

[0060] The load 300 is a three-phase electric motor driven by AC power supplied from the power conversion device 200. The load 300 is not limited to a specific application, but is an electric motor mounted on various electrical devices, and is used as an electric motor for, for example, a hybrid vehicle, an electric vehicle, a railroad car, an elevator, or an air conditioning device.

[0061] The power conversion device 200 will be described in detail below. The main conversion circuit 201 includes switching elements and freewheel diodes (not shown). The switching elements convert DC power supplied from the power supply 100 into AC power, which is supplied to the load 300. The main conversion circuit 201 can have a variety of specific circuit configurations. The main conversion circuit 201 according to this embodiment is a two-level, three-phase full-bridge circuit, which can be configured with six switching elements and six freewheel diodes connected in anti-parallel to each switching element. At least one of the switching elements and freewheel diodes of the main conversion circuit 201 is configured with a semiconductor device according to any one of the first to third embodiments. Two of the six switching elements are connected in series to form upper and lower arms, which constitute a respective phase (U phase, V phase, and W phase) of the full-bridge circuit. The output terminals of each upper and lower arm, i.e., the three output terminals of the main conversion circuit 201, are connected to the load 300.

[0062] The drive circuit 202 generates drive signals for driving the switching elements of the main conversion circuit 201 and supplies them to the control electrodes of the switching elements of the main conversion circuit 201. Specifically, in accordance with control signals from a control circuit 203 (described later), the drive circuit 202 outputs to the control electrodes of each switching element a drive signal that turns the switching element on and a drive signal that turns the switching element off. When maintaining a switching element in the on state, the drive signal is a voltage signal (on signal) that is equal to or higher than the threshold voltage of the switching element, and when maintaining a switching element in the off state, the drive signal is a voltage signal (off signal) that is equal to or lower than the threshold voltage of the switching element.

[0063] The control circuit 203 controls the switching elements of the main conversion circuit 201 so that the desired power is supplied to the load 300. Specifically, it calculates the time (on time) that each switching element of the main conversion circuit 201 should be in the on state based on the power to be supplied to the load 300. For example, the main conversion circuit 201 can be controlled by PWM control, which modulates the on time of the switching elements according to the voltage to be output. The control circuit 203 then outputs a control command (control signal) to the drive circuit 202 so that an on signal is output to the switching element that should be in the on state at each time, and an off signal is output to the switching element that should be in the off state at each time. In accordance with this control signal, the drive circuit 202 outputs an on signal or an off signal as a drive signal to the control electrode of each switching element.

[0064] In the power conversion device according to this embodiment, the semiconductor device according to any one of the first to third embodiments is used as the switching element of the main conversion circuit 201, and therefore a high On / Off ratio can be obtained.

[0065] In the present embodiment, an example has been described in which the semiconductor device according to any one of the first to third embodiments is applied to a two-level three-phase inverter, but the application of the semiconductor device according to any one of the first to third embodiments is not limited to this, and the semiconductor device can be applied to various power conversion devices. In the present embodiment, the two-level power conversion device is described, but a three-level or multi-level power conversion device may also be used, and when power is supplied to a single-phase load, the semiconductor device according to any one of the first to third embodiments may be applied to a single-phase inverter. Furthermore, when power is supplied to a DC load or the like, the semiconductor device according to any one of the first to third embodiments can also be applied to a DC / DC converter or an AC / DC converter.

[0066] Furthermore, a power conversion device to which the semiconductor device according to any one of the first to third embodiments is applied is not limited to the case where the load described above is an electric motor, but can also be used, for example, as a power supply device for an electric discharge machine, a laser processing machine, an induction heating cooker, or a contactless power supply system, and can also be used as a power conditioner for a solar power generation system, a power storage system, etc.

[0067] It is possible to freely combine the embodiments, and to modify or omit the embodiments as appropriate.

[0068] The above description is illustrative in all respects, and it is understood that countless variations not illustrated can be envisioned.

[0069] 1 n-type gallium oxide substrate, 2 first gallium oxide layer, 3 second gallium oxide layer, 4 third gallium oxide layer, 5 trench, 6 gate insulating film, 7 gate electrode, 8 interlayer insulating film, 9 contact hole, 10 source electrode, 11 drain electrode, 12 recess, 13 intermediate film, 20 gallium oxide semiconductor layer, 100 power supply, 200 power conversion device, 201 main conversion circuit, 202 drive circuit, 203 control circuit, 300 load.

Claims

1. A semiconductor device comprising: a gallium oxide semiconductor layer; a plurality of trenches provided on a first main surface of the gallium oxide semiconductor layer, the trenches having (010) planes of the gallium oxide semiconductor layer as their main side surfaces; a gate insulating film provided on the inner surface of the trench; and a gate electrode provided on the gate insulating film and embedded in the trench.

2. The semiconductor device according to claim 1, wherein the gate insulating film contains alumina.

3. The semiconductor device according to claim 1 or 2, wherein the gallium oxide semiconductor layer includes: an n-type gallium oxide substrate made of n-type β-gallium oxide having a (001) plane as its principal surface; a first gallium oxide layer provided on the n-type gallium oxide substrate; a second gallium oxide layer provided on the first gallium oxide layer; and a third gallium oxide layer provided on the second gallium oxide layer; and wherein the bottom of the trench reaches the first gallium oxide layer.

4. The semiconductor device according to claim 3, wherein the second gallium oxide layer is doped with an acceptor-type impurity.

5. The semiconductor device according to any one of claims 1 to 4, wherein the gate electrode is made of polysilicon.

6. The semiconductor device according to any one of claims 1 to 5, further comprising: an interlayer insulating film provided on said gallium oxide semiconductor layer; a contact hole provided in said interlayer insulating film and reaching said gallium oxide semiconductor layer; and a source electrode provided on said interlayer insulating film and connected to said gallium oxide semiconductor layer through said contact hole.

7. The semiconductor device according to claim 6, wherein the interlayer insulating film includes a silicon oxide film.

8. The semiconductor device according to claim 7, wherein the interlayer insulating film includes a two-layer structure in which a high-k film having a higher dielectric constant than silicon oxide is formed as a lower layer and the silicon oxide film is formed as an upper layer.

9. The semiconductor device according to any one of claims 6 to 8, wherein a recess is formed in the gallium oxide semiconductor layer at the bottom of the contact hole, and the source electrode is connected to the gallium oxide semiconductor layer within the recess.

10. The semiconductor device according to claim 9, wherein the gallium oxide semiconductor layer includes: an n-type gallium oxide substrate made of n-type β-gallium oxide having a (001) plane as a principal surface; a first gallium oxide layer provided on the n-type gallium oxide substrate; a second gallium oxide layer provided on the first gallium oxide layer; and a third gallium oxide layer provided on the second gallium oxide layer; and wherein the bottom of the recess reaches the first gallium oxide layer.

11. The semiconductor device according to claim 9 or 10, wherein an intermediate film having a band gap smaller than that of gallium oxide is interposed between the recess and the source electrode.

12. A power conversion device comprising: a main conversion circuit having a semiconductor device according to any one of claims 1 to 11, which converts input power and outputs it; a drive circuit which outputs a drive signal to drive said semiconductor device; and a control circuit which outputs a control signal to control said drive circuit to said drive circuit.

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