Complementary carrier mutual-induction semiconductor memory

Abstract

The present invention configures a semiconductor memory cell (that temporarily retains the stored contents even when power is turned off) that has a write / read speed equivalent to an SRAM, and in which complementary carriers present attracted to each other by an electric field in a pair of complementary channel layers facing each other via a separation film are physically or electronically connected to a carrier supply / extraction region and are thereby used as a new storage means capable of static storage. This configuration is compatible with the manufacturing technologies of future LSI generations (2 nm node and beyond) and the FET structures thereof.

Description

Complementary carrier mutual induction semiconductor memory

[0001] The present invention relates to semiconductor memories with improved footprint.

[0002] As shown in Figure 1 (a circuit diagram of a CMOS transistor configuration; see Non-Patent Document 1 for information on early SRAM integrated circuits), a conventional static random access memory (SRAM) cell configured with planar MOS transistors consists of two MOS inverters 11 and 12, their cross-coupled connections 21 and 22, and two write / read n-channel MOS transistors 5 and 6. MOS inverter 11 consists of an n-channel MOS transistor 1 and a p-channel MOS transistor 2, while MOS inverter 12 consists of an n-channel MOS transistor 3 and a p-channel MOS transistor 4. One of the source and drain terminals of write / read n-channel MOS transistor 5 is connected to the output of MOS inverter 11, and one of the source and drain terminals of write / read n-channel MOS transistor 6 is connected to the output of MOS inverter 12. Six transistors are required for one SRAM cell. Therefore, an SRAM cell configured with conventional planar MOS transistors requires an area of ​​6T for the six transistors and a projected area X for the cross-coupled wiring 21 and 22, i.e., 6T+X. When configured with CMOS transistors, a so-called well region 10 is required to accommodate the n-channel MOS transistor, which increases the occupied area accordingly. Note that T refers to the area occupied by one transistor, including the isolation region between adjacent elements.

[0003] To configure an array from this cell, the other of the source and drain of the write / read n-channel MOS transistor 5 is connected to a first digit line 31, the other of the source and drain of the write / read n-channel MOS transistor 6 is connected to a second digit line 32, and the gates of the write / read n-channel MOS transistors 5 and 6 are both connected to a word line 33. The sources of the n-channel MOS transistors 1 and 3 that configure the inverter are connected to a ground potential line (or reference potential line) 34, and the sources of the p-channel MOS transistors 2 and 4 that configure the inverter are connected to a power supply line 35.

[0004] Y. Tarui, Y. Hayashi, et al., a 40ns 144bit n-channel MOS memory, IEEE Jour. Solid-States Circuit, SC-4, 5, pp.271-279 (1969).H. Mertens, et al., nanosheet-based CFET at 48nm gate pitch and middle dielectric isolation, 2023 VLSI symposium, T1_3.

[0005] Special Publication No. 7-7822

[0006] Recently, Dr. Dario Gil of IBM (International Business Machines Corporation, USA) presented his AI (artificial intelligence) chip development policy at SEMICON Japan 2023 (December 13, 2023). High-performance processor chips integrate large arrays of SRAM on the same chip as the logic circuit, and the number of bits increases relative to each generation. Meanwhile, Dr. Thomas Coughlin, president of the Institute of Electrical and Electronics Engineers (IEEE), warned in his 44th IEEE RISM seminar (May 5, 2023) that "SRAM no longer scales with logic's process shrinks." To address this issue, it is necessary to provide SRAM with a smaller footprint as the manufacturing technology advances.

[0007] To achieve this requirement, assuming the use of a gate-all-around (GAA) nano-sheet complementary FET structure (see Non-Patent Document 2), which is expected to be introduced in the 2nm generation or later, a single CMOS inverter can be formed using stacked complementary GAA nano-sheet FETs, i.e., a GAA nano-sheet n-type FET 50 and a GAA nano-sheet p-type FET 60, as shown in Figure 2 (the structure reported in the presentation in Non-Patent Document 2 as a mass production technology for around 2032). Therefore, the projected area of ​​the two inverters, the projected area of ​​the two nano-sheet FETs for the write / read transistors, and the projected area X of the cross-coupled wiring, i.e., the area required for an SRAM cell, is expected to be reduced to 4T + X. Note that this reduction in SRAM area is not described in Non-Patent Document 2 or in the presentation. Figure 2 is a cross-sectional view of the drawing in Non-Patent Document 2, with wiring and other elements omitted for clarity. Reference numeral 100 denotes the substrate, 51 denotes the n-type channel sheet, 61 denotes the p-type channel sheet, 52 and 62 denote the gate insulating film, 56 denotes the gate conductive film, 54 and 55 denote the n-type source or drain, 64 and 65 denote the p-type source or drain, and 70 denotes the isolation insulating film region. 74 and 75 denote contact conductive layers to the n-type source or drain, and 76 and 77 denote contact conductive layers to the p-type source or drain. However, technology capable of reducing the SRAM footprint to 4T+X will only be available up to the 2032 generation mentioned above, and the principles and technology for reducing footprint for the next generation have not yet been determined.

[0008] The present invention has been made in view of these problems, and aims to provide the principles and structure of a semiconductor memory that can reduce the occupied area even further than 4T+X and operate at the same speed as SRAM.

[0009] To achieve the above objective, the present invention first utilizes complementary carriers, which exist in a pair of complementary channel layers facing each other via a separation film and are attracted to each other by an electric field, as a memory means. Note that "complementary carriers" refers to the combination of negatively charged electrons and positively charged holes, as seen from the electrons to the holes and vice versa. This phenomenon has already been disclosed in Patent Document 1, but it does not disclose the operation and device configuration of a semiconductor memory that can reliably realize an SRAM array. Regarding the operation of stored carriers, Patent Document 1 states in column 8, lines 38-44: "The electron-hole pairs continue to exist. In particular, by fabricating the first, second, and third layers of the present invention so that the probability of annihilation due to recombination is reduced, the refresh interval can be made longer than that of conventional dynamic random access memories, allowing for memory use similar to static memories and operation as short-term nonvolatile memories." As is clear from this statement, it does not state that refreshing of the complementary carriers is not necessary while the power is on. In other words, it does not state that SRAM can be reliably realized. The transistor shown in FIG. 1 of Patent Document 1 cannot be used as a memory cell in a memory array as is. (In other words, while stored carriers can be read from the source or drain, it is not possible to read information from a specific cell when the transistors are arranged in an array.) Patent Document 1 also discloses the memory cell configuration shown in FIG. 2 of Patent Document 1 as an example, and this unresolved issue also applies to the memory cell shown in FIG. 2 of Patent Document 1. Specifically, the portion of the channel layer where carriers accumulate, sandwiched between gates 6 and 7 of complementary channel layers 1 and 2, is separated from the source and drain regions 8, 9 and 10, 11 by gates 12 and 13 (the channel region connected to gates 12 and 13 is turned off during the memory period). The amount of electrons and holes stored in channel layers 1 and 2 changes due to recombination of oppositely charged carriers thermally generated. Over a long period of operation, the amount of stored carriers decreases to an equilibrium state at the operating temperature, resulting in loss of memory. The amount of stored carriers changes significantly over time, making the device unusable as an SRAM.

[0010] To solve the above problems, the present invention provides a semiconductor memory cell having a storage portion including a separating film, a pair of complementary channel layers facing each other via the separating film, a first carrier supply and withdrawal region connected to one of the pair of complementary channel layers, and a second carrier supply and withdrawal region connected to the other of the pair of complementary channel layers. This prevents loss of complementary carriers (carriers of a first conductivity type and carriers of a second conductivity type opposite to the first conductivity type, specifically electrons and holes) stored in the complementary channel layers by electrostatic coupling via the separating film. In addition, the present invention provides a semiconductor memory cell further including a third channel layer connected to one of the complementary channel layers directly or via an intermediate carrier supply and withdrawal region for storing and transporting first conductivity type carriers, as a readout portion for carrier charges stored in one of the complementary channel layers, and a third carrier supply and withdrawal region connected to the third channel layer. Furthermore, in the present invention, to form a semiconductor memory array, a semiconductor memory cell is formed from: a first conductive electrode insulated from the one channel layer by a first insulating film and capacitively coupled to the one channel layer; a second conductive electrode insulated from the other channel layer by a second insulating film and capacitively coupled to the other channel layer; and a third conductive electrode insulated from the third channel layer by a third insulating film and capacitively coupled to the third channel layer.Here, the first conductive electrode, which is insulated from and capacitively coupled to the one channel layer by a first insulating film, controls the injection of carriers of the first conductivity type from the first carrier supply and extraction region into the one channel layer or the extraction of carriers from the one channel layer to the first carrier supply and extraction region (the carrier injection and extraction operation is referred to as transport in the present invention), the second conductive electrode, which is insulated from and capacitively coupled to the other channel layer by a second insulating film, controls the injection of carriers of the second conductivity type from the second carrier supply and extraction region into the other channel layer or the extraction of carriers from the other channel layer to the second carrier supply and extraction region, and the third conductive electrode, which is insulated from and capacitively coupled to the third channel layer by a third insulating film, controls the injection or blocking of injection of carriers of the first conductivity type from the first channel layer or from the intermediate carrier supply and extraction region into the third channel layer, thereby controlling the read operation of the semiconductor memory cell. The separating film is a semiconductor or insulating film having an electron barrier that prevents the first conductive type carriers and the second conductive type carriers accumulated in the one channel layer and the other channel layer of the pair of complementary channel layers from being transported to the opposing complementary channel layer. The conductive electrode is formed of a metal film, a highly impurity-concentrated semiconductor film, or the like. If a single film is concerned about chemical reaction with other films that contact it above and below, its surface is covered with a protective film. Here, the side of one channel layer is provided with the first insulating film and the first conductive electrode extended to that side, and the side of the other channel layer is provided with the second insulating film and the second conductive electrode extended to that side, allowing passivation or surface potential control. The first and second carrier supply and extraction regions are provided to replenish carriers lost due to recombination, and one of them is also provided for connection to a digit line of the array described below.

[0011] A semiconductor memory array can be formed by arranging a plurality of semiconductor memory cells according to

[0010] , arranging one or two write word lines, one write digit line, one read word line, and one read digit line for each memory cell of the plurality of semiconductor memory cells, connecting the first carrier supply and draw-out region to a reference potential of the array, connecting the second carrier supply and draw-out region to the write digit line of the array, connecting the first conductive electrode and the second conductive electrode to one or two write word lines of the array, connecting the third carrier supply and draw-out region to the read digit line of the array, and connecting the third conductive electrode to the read word line of the array. In addition, when the first conductive electrode and the second conductive electrode are connected to one write word line, the first conductive electrode and the second conductive electrode can be configured as an integrated conductive electrode having the GAA structure that encases a multilayer structure of the first insulating film / the one channel layer / the separating film / the other channel layer / the second insulating film. Here, word lines and digit lines are conventional names for wiring that intersect horizontally and vertically in a memory array, and the names may be interchanged depending on the application. Examples of combinations and orders of bias application during writing, retaining, and reading of the memory cell or the memory array will be described later.

[0012] The following is one example of a memory cell configuration of the present invention: [Aspect 1] A semiconductor memory cell comprising: a separating film, a pair of complementary channel layers opposed to each other via the separating film, a first carrier supply and withdrawal region connected to one of the pair of complementary channel layers, a second carrier supply and withdrawal region connected to the other of the pair of complementary channel layers, a third channel layer connected to one of the channel layers for storing and transporting carriers of the first conductivity type, and a third carrier supply and withdrawal region connected to the third channel layer, wherein the separating film is a semiconductor or an insulating film having an electron barrier for one channel layer and an electron barrier for the other channel layer, respectively, that prevent first conductivity type carriers and second conductivity type carriers stored in the one channel layer and the other channel layer of the pair of complementary channel layers from flowing to the opposing complementary channel layer. [Aspect 2] The semiconductor memory cell according to Aspect 1, further comprising: an intermediate carrier supply and extraction region disposed between the one channel layer and the third channel layer, connecting the one channel layer and the third channel layer. [Aspect 3] The semiconductor memory cell according to Aspect 1, further comprising: a first conductive electrode insulated from the one channel layer by a first insulating film and capacitively coupled to the one channel layer, a second conductive electrode insulated from the other channel layer by a second insulating film and capacitively coupled to the other channel layer, and a third conductive electrode insulated from the third channel layer by a third insulating film and capacitively coupled to the third channel layer. [Aspect 4] The semiconductor memory cell according to aspect 2, further comprising: a first conductive electrode insulated from the one channel layer by a first insulating film and capacitively coupled to the one channel layer; a second conductive electrode insulated from the other channel layer by a second insulating film and capacitively coupled to the other channel layer; and a third conductive electrode insulated from the third channel layer by a third insulating film and capacitively coupled to the third channel layer.

[0013] Here, the complementary channel layer of the present invention comprises: one channel layer, i.e., a first semiconductor layer capable of storing and transporting carriers of a first conductivity type, and the other channel layer, i.e., a second semiconductor layer capable of storing and transporting carriers of a second conductivity type that is opposite in conductivity to the first conductivity type. Note that the term complementary carriers is used when negatively charged carriers, i.e., electrons, and positively charged carriers, i.e., holes, are used in combination, when viewed from the electrons toward the holes and from the holes toward the electrons. The separation layer of the present invention is a semiconductor or an insulator having a first surface in contact with the first semiconductor layer and a second surface in contact with the second semiconductor layer, a first electron barrier for carriers of the first conductivity type on the first surface to prevent the carriers of the first conductivity type from being transported through the separation layer to the second semiconductor layer, and a second electron barrier for carriers of the second conductivity type on the second surface to prevent the carriers of the second conductivity type from being transported through the separation layer to the first semiconductor layer. The carriers of the first conductivity type and the carriers of the second conductivity type can exist in a state of electrostatic attraction to each other via the separation layer. The first carrier supply and extraction region connected to the first semiconductor layer is one of: a semiconductor region of a first conductivity type, a semiconductor region forming a heterojunction with the first semiconductor layer, or a region forming a Schottky junction with the first semiconductor layer; the second carrier supply and extraction region connected to the second semiconductor layer is one of: a semiconductor region of a second conductivity type, a semiconductor region forming a heterojunction with the second semiconductor layer, or a region forming a Schottky junction with the second semiconductor layer; and the third carrier supply and extraction region is one of: a semiconductor region of a first conductivity type, a semiconductor region forming a heterojunction with the third semiconductor layer, or a region forming a Schottky junction with the third semiconductor layer. The third channel layer is a third semiconductor layer capable of storing and transporting first conductivity type carriers. The intermediate carrier supply and extraction region is one of: a semiconductor region of a first conductivity type; a semiconductor region that forms a heterojunction with both the first semiconductor layer and the third semiconductor layer; and a region that forms a Schottky junction with both the first semiconductor layer and the third semiconductor layer.

[0014] The following is one example of an array configuration of the present invention: [Aspect 5] A semiconductor memory array comprising: an array of semiconductor memory cells according to [Aspect 3]; and, for each memory cell of the plurality of semiconductor memory cells, one write word line of the array, one write digit line of the array, one read word line of the array, and one read digit line of the array; the first carrier supply and draw-out region is connected to a reference potential of the array, the second carrier supply and draw-out region is connected to the write digit line of the array, the first conductive electrode is connected to the write word line of the one array, the second conductive electrode is connected to the write word line of the one array, the third carrier supply and draw-out region is connected to the read digit line of the array, and the third conductive electrode is connected to the read word line of the array. [Aspect 6] A semiconductor memory array comprising: a plurality of semiconductor memory cells according to [Aspect 3]; and for each memory cell of the plurality of semiconductor memory cells, two write word lines of the array, one write digit line of the array, one read word line of the array, and one read digit line of the array; the first carrier supply and draw-out region is connected to a reference potential of the array; the second carrier supply and draw-out region is connected to the write digit line of the array; the first conductive electrode is connected to one write word line of the two write word lines of the array; the second conductive electrode is connected to the other write word line of the two write word lines of the array; the third carrier supply and draw-out region is connected to the read digit line of the array; and the third conductive electrode is connected to the read word line of the array.[Aspect 7] A semiconductor memory array comprising: a plurality of semiconductor memory cells according to [Aspect 4]; and each memory cell of the plurality of semiconductor memory cells is provided with one write word line of the array, one write digit line of the array, one read word line of the array, and one read digit line of the array; the first carrier supply and draw-out region is connected to a reference potential of the array; the second carrier supply and draw-out region is connected to the write digit line of the array; the first conductive electrode is connected to the write word line of the one array; the second conductive electrode is connected to the write word line of the one array; the third carrier supply and draw-out region is connected to the read digit line of the array; and the third conductive electrode is connected to the read word line of the array. [Aspect 8] A semiconductor memory array comprising: a plurality of semiconductor memory cells according to [Aspect 4]; and for each memory cell of the plurality of semiconductor memory cells, two write word lines of the array, one write digit line of the array, one read word line of the array, and one read digit line of the array; the first carrier supply and draw-out region is connected to a reference potential of the array; the second carrier supply and draw-out region is connected to the write digit line of the array; the first conductive electrode is connected to one write word line of the two write word lines of the array; the second conductive electrode is connected to the other write word line of the two write word lines of the array; the third carrier supply and draw-out region is connected to the read digit line of the array; and the third conductive electrode is connected to the read word line of the array.

[0015] An example of memory cell bias during data retention is as follows: The potential of the first conductive electrode is set to a potential between L1 (= the potential of the first carrier supply and extraction region) and (L1 + Vth1), the potential of the second conductive electrode is set to a potential between L2 (= the potential of the second carrier supply and extraction region) and (L2 + Vth2), and the potential of the third control electrode is set to a potential between L1 and (L1 + Vth3). The Vth1, Vth2, and Vth3 are the voltages (threshold voltages) of the first, second, and third conductive electrodes at which carrier charges of the first conductivity type, opposite conductivity type, and first conductivity type begin to be induced in the first, second, and third semiconductor layers, respectively, from a state in which there is no accumulated carrier charge. Here, the voltages Vth1, Vth2, and Vth3 are voltages expressed using the potentials of the first carrier supply and extraction region, the second carrier supply and extraction region, and the intermediate carrier supply and extraction region as starting points. Here, for ease of understanding, the voltages Vth1, Vth2, and Vth3 of the first, second, and third semiconductor layers, and the voltage Vth4 at which carrier charges begin to be induced in a state where there is no accumulated carrier charge in the fourth semiconductor layer described below, are assumed to be enhancement type. When the potential of the first carrier supply and extraction region and the potential of the second carrier supply and extraction region are at a reference potential (usually 0 V), if Vth1 ≧ 0, Vth2 ≦ 0, and Vth3 ≧ 0, when the carriers accumulated in the first semiconductor layer are electrons and the carriers accumulated in the second semiconductor layer are holes, the potential of the first conductive electrode, the potential of the second conductive electrode, and the potential of the third conductive electrode can be set to a reference potential (usually 0 V); and when the carriers accumulated in the first semiconductor layer are holes and the carriers accumulated in the second semiconductor layer are electrons, if Vth1 ≦ 0, Vth2 ≧ 0, and Vth3 ≦ 0, the potential of the first conductive electrode, the potential of the second conductive electrode, and the potential of the third conductive electrode can be set to a reference potential (usually 0 V). Furthermore, in this case, since memory is retained even if the power supply voltage of the memory cell and a memory array described later becomes the reference potential (usually 0 V), memory can be retained at least even if the power supply voltage becomes 0 V due to a power outage or the like. This will make it possible to create a new semiconductor memory in which the stored contents become non-volatile within a certain period of time.

[0016] Examples of write biases for a selected memory cell are: a. When storing complementary carrier charges (when writing "1"), one of the following conditions (1) and (2) is selected. (1) The potential of the first conductive electrode and the second conductive electrode is set to (L1+Vth1+ΔV1). (In this case, the first conductive electrode and the second conductive electrode can be connected to one write word line. Furthermore, the GAA structure can be adopted.) The potential of the second carrier supply and extraction region is set to the potential of the first conductive electrode (L1+Vth1+ΔV1)+ΔV2. The potential of the third conductive electrode is set between L1 and (L1+Vth3). (2) The potential of the first conductive electrode is set to L1+Vth1+ΔV1, and the potential of the second conductive electrode is set to L1+Vth2. The potential of the second carrier supply and extraction region is set to L1+ΔV4. (In this case, the first conductive electrode and the second conductive electrode are connected to different write word lines. Two write word lines are required.) The potential of the third conductive electrode is set between L1 and (L1+Vth3). When the carriers accumulated in the first semiconductor layer are electrons and the carriers accumulated in the second semiconductor layer are holes, it is desirable that ΔV1 is 0.5V to 1.5V, ΔV2 is -Vth2+0.5V to 1.0V, and ΔV4 is 0<ΔV4<-Vth2. When the carriers accumulated in the first semiconductor layer are holes and the carriers accumulated in the second semiconductor layer are electrons, it is desirable that ΔV1 is -0.5V to -1.5V, ΔV2 is -Vth2-0.5V to -1.5V, and ΔV4 is 0>ΔV4>-Vth2. b. When complementary charges are not accumulated (when writing "0"), one of the following conditions (1) and (2) is selected. The potential of the first conductive electrode is set to L1 (= the potential of the first carrier supply and extraction region) -ΔV1, and the potential of the second carrier supply and extraction region is set to the same potential L1 as the potential of the first carrier supply and extraction region. The potential of the second conductive electrode is set to (L1-ΔV1). The potential of the third conductive electrode is set to a potential between L1 (= the potential of the first carrier supply and extraction region) and (L1+Vth3). The potential of the first conductive electrode is set to L1 (= the potential of the first carrier supply and extraction region) -ΔV1, and the potential of the second carrier supply and extraction region is set to the same potential L1 as the potential of the first carrier supply and extraction region.The potential of the second conductive electrode is set to (L1+ΔV1). (In this case, the first conductive electrode and the second conductive electrode are connected to different write word lines. Two write word lines are required.) The potential of the third conductive electrode is set to a potential between L1 (= the potential of the first carrier supply and extraction region) and (L1+Vth3). When the carriers accumulated in the first semiconductor layer are electrons and the carriers accumulated in the second semiconductor layer are holes, the potential of the third conductive electrode is set to a potential between L1 (= the potential of the first carrier supply and extraction region) and (L1+Vth3), and ΔV1 is preferably 0.5V to 1.5V. When the carriers accumulated in the first semiconductor layer are holes and the carriers accumulated in the second semiconductor layer are electrons, ΔV1 is preferably -0.5V to -1.5V. In this case, all cells on one word line are written with "0", so "0" is written first, and then "1" is selectively written to the memory cells that are to be in the "1" state using the method a. above.

[0017] An example of a read bias for a selected memory cell is as follows: The potential of the first conductive electrode is set to a potential between L1 and (L1 + Vth1), and the potential of the second conductive electrode is set to a potential between L2 (= the potential of the second carrier supply and extraction region) and (L2 + Vth2). The potential of the third control electrode is set to L1 (= the potential of the first carrier supply and extraction region) + Vth3 + ΔV3. The potential of the third carrier supply and extraction region is set to L3 + ΔV3. ΔV3 is preferably 0.5 to 1.5 V when the read carriers are electrons, and preferably -0.5 to -1.5 V when the read carriers are holes. Whether or not complementary charges have accumulated can be detected based on whether or not current flows in or out of the third carrier supply and extraction region.

[0018] The present invention further provides the following memory cell configuration: the separating film, the pair of complementary channel layers opposed to each other via the separating film, one channel layer of the pair of complementary channel layers, the first carrier supply and withdrawal region connected to one channel layer of the pair of complementary channel layers, the other channel layer of the pair of complementary channel layers, the third channel layer connected to the one channel layer, the third carrier supply and withdrawal region connected to the third channel layer, a fourth channel layer for storing and transporting carriers of the second conductivity type connected to the other channel layer, a fourth carrier supply and withdrawal region connected to the fourth channel layer, a first conductive electrode insulated from and capacitively coupled to the one channel layer by the first gate insulating film, a second conductive electrode insulated from and capacitively coupled to the other channel layer by the second gate insulating film, and a third conductive electrode insulated from and capacitively coupled to the third channel layer by the third gate insulating film. Furthermore, a semiconductor memory cell is formed by a fourth gate insulating film insulated from the fourth channel layer and a capacitively coupled conductive electrode.

[0019] A memory array can be formed from the plurality of memory cells by arranging a plurality of semiconductor memory cells according to

[0018] , and for each memory cell, two write word lines of the array, one write digit line of the array, one read word line of the array, and one read digit line of the array, connecting the first carrier supply and draw-out region to a reference potential of the array, connecting the fourth carrier supply and draw-out region to the write digit line of the array, connecting the first conductive electrode, the second conductive electrode, and the fourth conductive electrode to the write word line(s) of the array, connecting the third carrier supply and draw-out region to the read digit line of the array, and connecting the third conductive electrode to the read word line of the array. Note that word lines and digit lines are conventional names for wiring that cross horizontally and vertically in the array, and the names may be interchanged depending on the application.

[0020] Other cell configurations of the present invention include the following. [Aspect 9] The memory portion is composed of the separating film, the pair of complementary channel layers opposed to each other via the separating film, one channel layer (for storing and transporting carriers of a first conductivity type) of the pair of complementary channel layers, the other channel layer (for storing and transporting carriers of a second conductivity type) of the pair of complementary channel layers, the first carrier supply and withdrawal region connected to one of the channel layers, a third channel layer (for storing and transporting carriers of the first conductivity type) connected to one of the channel layers, a third carrier supply and withdrawal region connected to the third channel layer, a fourth channel layer (for storing and conducting carriers of the second conductivity type) connected to the other channel layer, and a fourth carrier supply and withdrawal region connected to the fourth channel layer, wherein the third channel layer and the third carrier supply and withdrawal region form a readout portion for reading out carrier charges stored in one of the complementary channel layers, The separating film is a semiconductor or an insulating film having respective electron barriers that prevent carriers stored in one channel layer and the other channel layer of the pair of complementary channel layers from being transported to the opposing channel layer. Aspect 10: The semiconductor memory cell according to aspect 9, further comprising: a first gate insulating film provided on the one channel layer; a first conductive electrode insulated from and capacitively coupled to the one channel layer by the first gate insulating film; a second gate insulating film provided on the other channel layer; a second conductive electrode insulated from and capacitively coupled to the other channel layer by the second gate insulating film; a third gate insulating film provided on the third channel layer; a third conductive electrode insulated from and capacitively coupled to the third channel layer by the third gate insulating film; and a fourth gate insulating film provided on the fourth channel layer; and a fourth conductive electrode insulated from and capacitively coupled to the fourth channel layer by the first gate insulating film.

[0021] Here, the fourth carrier supply and extraction region of the present invention is one of a semiconductor region of a second conductivity type, a semiconductor region that forms a heterojunction with the fourth semiconductor layer, and a region that forms a Schottky junction with the fourth semiconductor layer.

[0022] Other array configurations of the present invention include the following: (4) [Aspect 11] A semiconductor memory array comprising: a plurality of semiconductor memory cells according to Aspect 10; and for each memory cell, three write word lines (first, second, and third) of the array, one write digit line of the array, one read word line of the array, and one read digit line of the array, the first carrier supply and pull-out region being connected to a reference potential of the array, the fourth carrier supply and pull-out region being connected to the write digit line of the array, the first conductive electrode, the second conductive electrode, and the fourth conductive electrode being connected to the first, second, and third write word lines of the array, the third carrier pull-out region being connected to the read digit line of the array, and the third conductive electrode being connected to the read word line of the array.

[0023] An example of the cell bias during memory retention is as follows: the potential of the second carrier supply and extraction region is set to the potential L1 of the first carrier supply and extraction region, the potential of the first conductive electrode is set to a potential between L1 and (L1+Vth1), the potential of the second conductive electrode is set to a potential between L1 and (L1+Vth2), and the potential of the third conductive electrode is set to a potential between L1 and (L1+Vth3).When the potential of the fourth carrier supply and extraction region is the potential of the first carrier supply and extraction region, the potential of the fourth conductive electrode is set to L1+Vth4+ΔV4, and when the potential of the fourth carrier supply and extraction region is L1+Vth4+ΔV4, the potential of the fourth conductive electrode is set to a potential between L1 and (L1+Vth4). When a write voltage is applied to a cell connected to another word line in the array, the potential of the fourth conductive electrode is set to a potential between L1 and (L1 + Vth4) for a certain period of time, including before and after the write voltage application, to prevent malfunction of the memory retention cell. Vth1, Vth2, Vth3, and Vth4 are the voltages of the first, second, third, and fourth conductive electrodes at which first conductivity-type, opposite conductivity-type, first conductivity-type, and opposite conductivity-type carriers begin to be induced in the first, second, third, and fourth semiconductor layers, respectively. When the carriers accumulated in the first semiconductor layer are electrons and the carriers accumulated in the second semiconductor layer are holes, ΔV4 is preferably −0.5 V to −1.5 V. When the carriers accumulated in the first semiconductor layer are holes and the carriers accumulated in the second semiconductor layer are electrons, ΔV4 is preferably 0.5 V to 1.5 V. When the potential L1 of the first carrier supply and extraction region is 0V, if the carriers accumulated in the first semiconductor layer are electrons and the carriers accumulated in the second semiconductor layer are holes, and if Vth1≧0, Vth2≦0, Vth3≧0, Vth4≦0, the potential of the first conductive electrode, the potential of the second conductive electrode, and the potential of the third conductive electrode can be 0V; and if the carriers accumulated in the first semiconductor layer are holes and the carriers accumulated in the second semiconductor layer are electrons, and if Vth1≦0, Vth2≧0, Vth3≦0, Vth4≧0, the potential of the first control electrode, the potential of the second control electrode, and the potential of the third control electrode can be 0V.

[0024] Examples of write biases for a selected cell are: a. When storing complementary charges (when writing "1"), *If the carriers stored in the first semiconductor layer are electrons and the carriers stored in the second semiconductor layer are holes, the potential of the second carrier supply and extraction region is set to the potential L1 of the first carrier supply and extraction region, the potential of the first conductive electrode is set to (L1 + Vth1 + ΔV1), the potential of the second conductive electrode is set to (L1 + Vth2 - ΔV2), the potential of the fourth carrier supply and extraction region is set to the same as L1, and the potential of the fourth conductive electrode is set to (L1 + Vth4 - ΔV2). The potential of the third control electrode is set to a potential between L1 and (L1 + Vth3). It is desirable that ΔV1 be 0.5V to 1.5V and ΔV2 be 0.5V to 1.5V. *When the carriers accumulated in the first semiconductor layer are holes and the carriers accumulated in the second semiconductor layer are electrons, the potential of the first conductive electrode is set to (L1+Vth1-ΔV1), the potential of the second conductive electrode is set to (L1+Vth2+ΔV2), the potential of the fourth carrier supply and extraction region is set to L1, and the potential of the fourth conductive electrode is set to L1+Vth4+ΔV2. The potential of the third control electrode is set to a potential between L1 and (L1+Vth3). b. When complementary charges are not accumulated (when writing "0"), *If the carriers accumulated in the first semiconductor layer are electrons and the carriers accumulated in the second semiconductor layer are holes, the potential of the first conductive electrode is set to a potential between L1 (= the potential of the first carrier supply and extraction region) and L1 + Vth1, the potential of the second conductive electrode is set to a potential between L1 and (L1 + Vth2), and the potential of the fourth conductive electrode is set to L1 + Vth4 - ΔV2. The potential of the fourth carrier supply and extraction region is set to L1 - ΔV2. The potential of the third control electrode is set to a potential between L1 and (L1 + Vth3). ΔV2 is preferably 0.5V to 1.5V. *If the carriers accumulated in the first semiconductor layer are holes and the carriers accumulated in the second semiconductor layer are electrons, in the above potential settings, ΔV2 is preferably -0.5V to -1.5V.

[0025] Examples of read biases for a selected memory cell are: *When the read carriers are electrons, the potential of the first conductive electrode is set to a potential between L1 (= the potential of the first carrier supply and extraction region) and (L1 + Vth1), and the potential of the second conductive electrode is set to a potential between L2 (= the potential of the second carrier supply and extraction region) and (L2 + Vth2). The potential of the fourth carrier supply and extraction region is set to L2, The potential of the fourth conductive electrode is set to a potential between L2 and (L2 + Vth4), and the potential of the third conductive electrode is set to (L1 + Vth3 + ΔV3). The potential of the third carrier supply and extraction region is set to L1 + ΔV3. ΔV3 is preferably 0.5 to 1.5V. *When the readout carriers are holes, the potential of the first conductive electrode is set to a potential between L1 and (L1 + Vth1), the potential of the second conductive electrode is set to a potential between L2 and (L2 + Vth2), the potential of the fourth conductive electrode is set to a potential between L2 and (L2 + Vth4), and the potential of the third conductive electrode is set to (L1 + Vth3 - ΔV3). The potential of the third carrier supply and extraction region is set to L1 - ΔV3. Whether or not complementary charges have accumulated can be detected by whether or not there is current flowing in and out of the third carrier supply and extraction region.

[0026] High-performance processor chips are increasingly integrating large-scale SRAM arrays in addition to logic circuits on the same chip, and with each generation, the integration area of ​​the SRAM portion is increasing relative to the logic circuit portion. Therefore, to ensure the performance of processor chips, an SRAM cell with a smaller footprint (projected area onto the main surface) for the same bit capacity is desired. This invention makes it possible to develop a memory that occupies a small footprint, is capable of high-speed writing and reading similar to SRAM, and retains its stored contents even if the power supply is lost for a certain period of time, contributing to the advancement of future generations of LSIs.

[0027] Fig. 1 is a circuit diagram of an SRAM cell composed of a conventional planar CMOSFET; Fig. 2 is a schematic cross-sectional view of complementary nanosheet GAAFETs; Fig. 3 is a schematic cross-sectional view of Example 1 of a semiconductor memory cell of the present invention; Fig. 4 is a schematic cross-sectional view of Example 2 of a semiconductor memory cell of the present invention; Fig. 5 is a schematic cross-sectional view of Example 3 of a semiconductor memory cell of the present invention;

[0028] An example of a cross-sectional structure of a first embodiment of the memory cell structure of the first aspect is shown in Fig. 3. A first semiconductor layer 101 capable of storing and transporting carriers of a first conductivity type and a second semiconductor layer 102 capable of storing and transporting carriers of a second conductivity type opposite to the first conductivity type are separated by a separation layer 125. The separation layer 125 has a first surface 1251 in contact with the first semiconductor layer 101 and a second surface 1252 in contact with the second semiconductor layer 102, has a first electronic barrier against carriers of the first conductivity type at the first surface 1251 to prevent the carriers of the first conductivity type from being transported through the separation layer 125 to the second semiconductor layer 102, and has a second electronic barrier against carriers of the second conductivity type at the second surface 1252 to prevent the carriers of the second conductivity type from being transported through the separation layer to the first semiconductor layer 101, and is a semiconductor or an insulator having the electronic barriers against the first semiconductor layer and the second semiconductor layer, respectively. The first conductivity type carriers 91 and the second conductivity type carriers 92 can exist in a state of electrostatic attraction to each other via the separation layer. A first carrier supply and extraction region 111 is connected to the first semiconductor layer 101. The first carrier supply and extraction region 111 is one of a first conductivity type semiconductor region, a semiconductor region forming a heterojunction with the first semiconductor layer 101, or a region forming a Schottky junction with the first semiconductor layer 101. A second carrier supply and extraction region 114 is connected to the second semiconductor layer 102. The second carrier supply and extraction region 114 is one of a second conductivity type semiconductor region, a semiconductor region forming a heterojunction with the second semiconductor layer 102, or a region forming a Schottky junction with the second semiconductor layer 102. A third semiconductor layer 103 is connected to the first semiconductor layer 101 via an intermediate carrier supply and extraction region 112. The third semiconductor layer 103 is a semiconductor layer capable of storing and transporting the first conductive type carriers, and is connected to a third carrier supply and extraction region 113 on the side opposite to the intermediate carrier supply and extraction region 112 .The intermediate carrier supply and extraction region 112 is one of a first conductivity type semiconductor region, a semiconductor region forming a heterojunction with the first semiconductor region 101 and the third semiconductor layer 103, or a region forming a Schottky junction with the first semiconductor region 101 and the third semiconductor layer 103. The third carrier supply and extraction region 113 is one of a first conductivity type semiconductor region, a semiconductor region forming a heterojunction with the third semiconductor layer 103, or a region forming a Schottky junction with the third semiconductor layer 103. A first insulating film 121 is provided on a surface 1011 of the first semiconductor layer 101 facing the separation layer 123, and a first conductive film 131 electrostatically coupled to the first semiconductor layer 101 is provided on the surface of the first insulating film 121. A second insulating film 122 is provided on a surface 1022 of the second semiconductor layer 102 facing the separating layer 123, and a second conductive film 132 that is electrostatically coupled to the second semiconductor layer 102 is provided on the surface of the second insulating film 122. A third insulating film 123 is provided on a surface 1031 of the third semiconductor layer 103, and a third conductive film 133 that is electrostatically coupled to the third semiconductor layer 103 is provided on the surface of the third insulating film 123. Although not shown, the first insulating film 121 can be provided on side surfaces of the first semiconductor layer 101 other than the surface 1011, and the first conductive film 131 can be provided on the surface of the first insulating film 121 to provide a passivation effect. A passivation effect can be expected by providing the second insulating film 122 on the side surfaces other than the front surface 1011 of the second semiconductor layer 102 and providing the second conductive film 132 on the surface of the first insulating film 122. A passivation effect can be expected by providing the third insulating film 123 on the side surfaces other than the front surface 1031 of the third semiconductor layer 103 or on the back surface and providing the third conductive film 133 on the surface of the third insulating film 123. The above-mentioned regions and layers can be insulated from the outside by an insulating region 70, and the insulating region 70 can be attached to a substrate as needed.

[0029] By arranging a plurality of semiconductor memory cells described in

[0028] , and for each memory cell, one write word line of the array, one write digit line 152 of the array, one read word line of the array, and one read digit line 153 of the array, connecting the first carrier supply and draw-out region 111 to a reference potential line 150 (usually 0V), connecting the second carrier supply and draw-out region 114 to the write digit line 152, connecting the third carrier supply and draw-out region 113 to the read digit line 153, connecting the first conductive film 131 and the second conductive film 132 to one write word line extending perpendicular to the paper surface, and connecting the third conductive film 133 to a read word line extending perpendicular to the paper surface, a semiconductor memory array can be formed with the memory cells arranged perpendicular to the paper surface and the memory cells arranged left and right in a direction parallel to the paper surface.

[0030] In addition, when the first conductive film 131 and the second conductive film 132 are made of the same material and are connected to each other, the first insulating film 121, the first semiconductor layer 101, the separating layer 123, the second semiconductor layer 102, and the second insulating film 122 can be manufactured using GAA technology as a structure in which the first insulating film 121, the first semiconductor layer 101, the separating layer 123, the second semiconductor layer 102, and the second insulating film 122 are wrapped in the same material. In this case, the first insulating film 121 can be provided on both side surfaces of the surface 1011 of the first semiconductor layer 101, and the second insulating film 122 can be provided on both side surfaces of the surface 1022 of the second semiconductor layer 102 for passivation. The first insulating film 121 and the second insulating film 122 may be made of the same material.

[0031] a plurality of semiconductor memory cells according to

[0028] , and for each memory cell, two (first and second) write word lines of the array, one write digit line 152 of the array, one read word line of the array, and one read digit line 153 of the array; the first carrier supply and draw-out region 111 is connected to a reference potential line 150 (usually 0V); the second carrier supply and draw-out region 114 is connected to the write digit line 152; the third carrier supply and draw-out region 113 is connected to the read digit line 153; the first conductive film 131 and the second conductive film 132 are respectively connected to two first and second write word lines extending in a direction perpendicular to the paper surface; By connecting the third conductive film 133 to the read word line perpendicular to the paper surface, a semiconductor memory array can be formed with the memory cells arranged perpendicular to the paper surface and the memory cells arranged on the left and right in a direction parallel to the paper surface.

[0032] An example of a cross-sectional structure of another embodiment of the memory cell structure of the first aspect is shown in Fig. 4. A first semiconductor layer 101 capable of storing and transporting carriers of a first conductivity type and a second semiconductor layer 102 capable of storing and transporting carriers of a second conductivity type opposite to the first conductivity type are separated by a separation layer 125. The separation layer 125 has a first surface 1251 in contact with the first semiconductor layer 101 and a second surface 1252 in contact with the second semiconductor layer 102, has a first electronic barrier against carriers of the first conductivity type at the first surface 1251 to prevent the carriers of the first conductivity type from being transported through the separation layer 125 to the second semiconductor layer 102, and has a second electronic barrier against carriers of the second conductivity type at the second surface 1252 to prevent the carriers of the second conductivity type from being transported through the separation layer to the first semiconductor layer 101, and is a semiconductor or an insulator having the electronic barriers against the first semiconductor layer and the second semiconductor layer, respectively. The first conductivity type carriers 8 and the second conductivity type carriers 9 can exist in a state of electrostatic attraction to each other via the separation layer. A first carrier supply and extraction region 111 is connected to the first semiconductor layer 101. The first carrier supply and extraction region 111 is one of a first conductivity type semiconductor region, a semiconductor region forming a heterojunction with the first semiconductor layer 101, or a region forming a Schottky junction with the first semiconductor layer 101. A second carrier supply and extraction region 114 is connected to the second semiconductor layer 102. The second carrier supply and extraction region 114 is one of a second conductivity type semiconductor region, a semiconductor region forming a heterojunction with the second semiconductor layer 102, or a region forming a Schottky junction with the second semiconductor layer 102. A third semiconductor layer 103 is connected to the first semiconductor layer 101. The third semiconductor layer 103 is a semiconductor layer capable of storing and transporting first conductivity type carriers, and is connected to a third carrier supply and extraction region 113 on the side opposite to the first carrier supply and extraction region 111. The third carrier supply and extraction region 113 is one of a semiconductor region of the first conductivity type, a semiconductor region that forms a heterojunction with the third semiconductor layer 103, or a region that forms a Schottky junction with the third semiconductor layer 103.A seventh insulating film 127 is provided on a surface 1011 of the first semiconductor layer 101 facing the separating layer 125, and a first conductive film 131 that electrostatically couples to the first semiconductor layer 101 is provided on the surface of the seventh insulating film 127. A second insulating film 122 is provided on a surface 1022 of the second semiconductor layer 102 facing the separating layer 123, and a second conductive film 132 that electrostatically couples to the second semiconductor layer 102 is provided on the surface of the second insulating film 122. The seventh insulating film 127 extends to a surface 1031 of the third semiconductor layer 103, and a third conductive film 133 that electrostatically couples to the third semiconductor layer 103 is provided on the surface of the seventh insulating film 127. The first conductive film and the third conductive film are insulated from each other by an insulating film 129. Although not shown, the seventh insulating film 127 can be extended to the side surfaces of the first semiconductor layer 101 other than the surface 1011, and the first conductive film can be extended thereon to passivate the side surfaces of the first semiconductor layer. The seventh insulating film 127 can be extended to the side surfaces of the third semiconductor layer 103 other than the surface 1031, and the third conductive film 133 can be extended thereon to passivate the side surfaces of the third semiconductor layer. Each of the above regions and layers can be insulated from the outside by an insulating region 70, and the insulating region 70 can be attached to a substrate as needed.

[0033] By arranging a plurality of semiconductor memory cells as described in

[0032] , and for each memory cell, one write word line of the array, one write digit line 152 of the array, one read word line of the array, and one read digit line 153 of the array, connecting the first carrier supply and draw-out region 111 to a reference potential line 150 (usually 0V), connecting the second carrier supply and draw-out region 114 to the write digit line 152, connecting the third carrier supply and draw-out region 113 to the read digit line 153, connecting the first gate conductive film 131 and the second gate conductive film 132 to the write word line extending in a direction perpendicular to the paper surface, and connecting the third conductive film 133 to the read word line perpendicular to the paper surface, a semiconductor memory array can be configured with the semiconductor memory cells arranged perpendicular to the paper surface and the semiconductor memory cells arranged parallel to the paper surface (left and right).

[0034] In addition, when the first conductive film 131 and the second conductive film 132 are made of the same material and are connected, the seventh insulating film 127, the first semiconductor layer 101, the separating layer 123, the second semiconductor layer 102, and the second insulating film 122 can be manufactured using GAA technology as a structure in which the same material is used to encase the seventh insulating film 127, the first semiconductor layer 101, the separating layer 123, the second semiconductor layer 102, and the second insulating film 122 can be extended to both side surfaces of the surface 1011 of the first semiconductor layer 101 and both side surfaces of the surface 1022 of the second semiconductor layer 102 for passivation. The seventh insulating film 127 and the second insulating film 122 may be made of the same material. The seventh insulating film 127 can be extended to both side surfaces of the surface 1031 of the third semiconductor layer 103, and if necessary, the third conductive film 133 can be extended thereon for passivation.

[0035] a plurality of semiconductor memory cells according to

[0032] , and for each memory cell, two (first and second) write word lines of the array, one write digit line 152 of the array, one read word line of the array, and one read digit line 153 of the array; the first carrier supply and draw-out region 111 is connected to a reference potential line 150 (usually 0V); the second carrier supply and draw-out region 114 is connected to the write digit line 152; the third carrier supply and draw-out region 113 is connected to the read digit line 153; the first conductive film 131 and the second conductive film 132 are connected to two first and second write word lines extending in a direction perpendicular to the paper surface; By connecting the third conductive film 133 to a read word line extending perpendicular to the paper surface, a semiconductor memory array can be formed with the memory cells arranged perpendicular to the paper surface and the memory cells arranged on the left and right in a direction parallel to the paper surface.

[0036] a plurality of semiconductor memory cells according to

[0032] , and for each memory cell, one write word line, one write digit line 152, one read word line, and one read digit line 153; connecting the first carrier supply and draw-out region 111 to a reference potential line 150 (usually 0V) of the array; connecting the second carrier supply and draw-out region 114 to the reference potential line 150 of the array; connecting the third carrier supply and draw-out region 113 to the read digit line 153 of the array; connecting the first conductive film 131 to the write word line of the array extending in a direction perpendicular to the paper surface; connecting the second conductive film 132 to the write digit line 152 extending in a direction parallel to the paper surface; and connecting the third conductive film to the read word line of the array extending in a direction perpendicular to the paper surface. A semiconductor memory array can be constructed that is composed of a plurality of semiconductor memory cells described in

[0032] arranged in a direction perpendicular to the paper surface and a plurality of semiconductor memory cells described in

[0032] arranged to the left and right in a direction parallel to the paper surface.

[0037] A cross-sectional structure of one example of the memory cell structure of the second aspect is shown in Fig. 5. A first semiconductor layer 101 capable of storing and transporting carriers of a first conductivity type and a second semiconductor layer 102 capable of storing and transporting carriers of a second conductivity type opposite to the first conductivity type are separated by a separation layer 125. The separation layer 125 is a semiconductor or insulator having a first surface 1251 in contact with the first semiconductor layer 101 and a second surface 1252 in contact with the second semiconductor layer 102, a first electronic barrier for carriers of the first conductivity type at the first surface 1251 to prevent the carriers of the first conductivity type from being transported through the separation layer 125 to the second semiconductor layer 102, and a second electronic barrier for carriers of the second conductivity type at the second surface 1252 to prevent the carriers of the second conductivity type from being transported through the separation layer 125 to the first semiconductor layer 101. The first conductivity type carriers 8 and the second conductivity type carriers 9 can exist in a state of electrostatically attracting each other via the separation layer 125. A first carrier supply and extraction region 111 is connected to the first semiconductor layer 101. The first carrier supply and extraction region 111 is one of a semiconductor region of a first conductivity type, a semiconductor region that forms a heterojunction with the first semiconductor layer 101, or a region that forms a Schottky junction with the first semiconductor layer 101. A third semiconductor layer 103 is connected to the first semiconductor layer 101. The third semiconductor layer is a semiconductor layer that can accumulate and transport the first conductivity type carriers. A third carrier supply and extraction region 113 is connected to the third semiconductor layer 103. The third carrier supply and extraction region 113 is one of a semiconductor region of a first conductivity type, a semiconductor region that forms a heterojunction with the third semiconductor layer 103, or a region that forms a Schottky junction with the third semiconductor layer 103. A sixth semiconductor layer 116 is connected to the fourth semiconductor layer 104. The fourth semiconductor layer is a semiconductor layer that can accumulate and transport carriers of a second conductivity type (opposite conductivity type to the first conductivity type). The sixth carrier supply and extraction region 116 is one of a semiconductor region of the second conductivity type, a semiconductor region that forms a heterojunction with the fourth semiconductor layer 104, or a region that forms a Schottky junction with the fourth semiconductor layer 104.A seventh insulating film 127 is provided on a surface 1011 of the first semiconductor layer 101 opposite to the separating layer 125, and a first (gate) conductive film 131 that is electrostatically coupled to the first semiconductor layer 101 is provided on the surface of the seventh insulating film 127. A sixth insulating film 126 is provided on a surface 1022 of the second semiconductor layer 102 opposite to the separating layer 123, and a second (gate) conductive film 132 that is electrostatically coupled to the second semiconductor layer 102 is provided on the surface of the sixth insulating film 126. The seventh insulating film 127 is provided extending to a surface 1031 of the third semiconductor layer 103 opposite to the separating layer 123, and a third (gate) conductive film 133 that is electrostatically coupled to the third semiconductor layer 103 is provided on the surface of the seventh insulating film 127. The third (gate) conductive film 133 is insulated from the first (gate) conductive film 131 by a ninth insulating film 129. The sixth insulating film 126 extends on a surface 1042 of the fourth semiconductor layer 104 opposite the separation layer 125, and a fourth (gate) conductive film 134 that is electrostatically coupled to the fourth semiconductor layer 104 is provided on the surface of the sixth insulating film 126. The fourth conductive film 134 is insulated from the second (gate) conductive film 132 by an eighth insulating film 128. The above-mentioned regions and layers can be insulated from the outside by an insulating region 70, and the insulating region 70 can be adhered to a substrate as needed.

[0038] A plurality of semiconductor memory cells according to

[0037] are arranged, and for each memory cell, three (first, second, and fourth) write word lines, one write digit line 154, one read word line, and one read digit line 153 are arranged, the first carrier supply and draw-out region 111 is connected to a reference potential line 150 (usually 0 V), the fourth carrier supply and draw-out region 116 is connected to the write digit line 154, and the third carrier supply and draw-out region 113 is connected to the read digit line 153, By connecting the first gate conductive film 131, the second gate conductive film 132, and the fourth gate conductive film 134 to first, second, and fourth write word lines extending perpendicular to the paper surface, respectively, and connecting the third gate conductive film 133 to a read word line extending perpendicular to the paper surface, a semiconductor memory array can be configured with the semiconductor memory cells arranged perpendicular to the paper surface and the memory cells arranged parallel to the paper surface (left and right). Note that when writing to a selected cell is performed and before and after, that is, when the fourth semiconductor layer 104 of the selected cell transports carriers of the second conductivity type, the potential of the unselected write word lines (write word lines connected to the fourth conductive film 134 of the unselected cells) is set to a potential in a direction (negative if the opposite conductivity type carriers are electrons, positive if the opposite conductivity type carriers are holes) that prevents carriers of the second conductivity type from being induced in the fourth semiconductor layer 104, relative to the threshold voltage Vth4 at which carriers of the second conductivity type begin to be induced in the fourth semiconductor layer 104, in order to prevent erroneous writing.

[0039] It is expected that nanosheet FETs will be used as semiconductor memory elements equivalent to small-area SRAMs in high-performance LSIs beyond the 2-nm generation, and that they will also be capable of high-speed writing and reading similar to SRAMs, while retaining their stored contents even if the power supply is lost for a certain period of time.

Claims

1. A semiconductor memory cell comprising: a separating film; a pair of complementary channel layers opposed to each other via the separating film; a first carrier supply and withdrawal region connected to one of the pair of complementary channel layers; a second carrier supply and withdrawal region connected to the other of the pair of complementary channel layers; a third channel layer connected to one of the channel layers for transporting carriers of the first conductivity type; and a third carrier supply and withdrawal region connected to the third channel layer, wherein the separating film is a semiconductor or insulating film having an electron barrier that prevents first conductivity type carriers and second conductivity type carriers accumulated in the one and the other channel layers of the pair of complementary channel layers from being transported to the opposing channel layer.

2. The semiconductor memory cell according to claim 1, further comprising an intermediate carrier supply and extraction region disposed between said one channel layer and said third channel layer, and connecting said one channel layer and said third channel layer.

3. A semiconductor memory cell according to claim 1, comprising: a first conductive electrode insulated from and capacitively coupled to said one channel layer by a first insulating film; a second conductive electrode insulated from and capacitively coupled to said other channel layer by a second insulating film; and a third conductive electrode insulated from and capacitively coupled to said third channel layer by a third insulating film.

4. A semiconductor memory cell according to claim 2, comprising: a first conductive electrode insulated from and capacitively coupled to said one channel layer by a first insulating film; a second conductive electrode insulated from and capacitively coupled to said other channel layer by a second insulating film; and a third conductive electrode insulated from and capacitively coupled to said third channel layer by a third insulating film.

5. A semiconductor memory array comprising a plurality of semiconductor memory cells according to claim 3, wherein for each memory cell: two write word lines of the array; one write digit line of the array; one read word line of the array; and one read digit line of the array; the first carrier supply and draw-out region is connected to a reference potential of the array; the second carrier supply and draw-out region is connected to one write digit line of the array; one each of the first conductive electrode and the second conductive electrode is connected to two write word lines of the array; the third carrier supply and draw-out region is connected to one read digit line of the array; and the third conductive electrode is connected to one read word line of the array.

6. A semiconductor memory array according to claim 5, wherein the two write word lines of the array arranged for each memory cell are one, and the first conductive electrode and the second conductive electrode are connected together to the write word line of the single array.

7. A semiconductor memory array comprising a plurality of semiconductor memory cells according to claim 4, wherein for each memory cell: two write word lines of the array; one write digit line of the array; one read word line of the array; and one read digit line of the array; the first carrier supply and draw-out region is connected to a reference potential of the array; the second carrier supply and draw-out region is connected to the write digit line of the array; the first control electrode and the second control electrode are connected to one write word line of the array in total; the third carrier supply and draw-out region is connected to the read digit line of the array; and the third control electrode is connected to the read word line of the array.

8. A semiconductor memory array according to claim 7, wherein the two write word lines of the array arranged for each memory cell are one, and the first control electrode and the second control electrode are collectively connected to the write word line of the one array.

9. A semiconductor memory array comprising a plurality of semiconductor memory cells according to claim 3, wherein for each memory cell: one write word line of the array; one write digit line of the array; one read word line of the array; and one read digit line of the array; the first carrier supply and extraction region is connected to a reference potential of the array; the second carrier supply and extraction region is connected to a reference potential of the array; one of the first conductive electrode and the second conductive electrode is connected to one write word line of the array and the other is connected to one write digit line of the array; the third carrier extraction region is connected to one read digit line of the array; and the third conductive electrode is connected to one read word line of the array.

10. A semiconductor memory array comprising a plurality of semiconductor memory cells according to claim 4, wherein for each memory cell: one write word line of the array; one write digit line of the array; one read word line of the array; and one read digit line of the array; the first carrier supply and extraction region is connected to a reference potential of the array; the second carrier supply and extraction region is connected to a reference potential of the array; one of the first conductive electrode and the second conductive electrode is connected to one write word line of the array and the other is connected to one write digit line of the array; the third carrier extraction region is connected to one read digit line of the array; and the third conductive electrode is connected to one read word line of the array.

11. A semiconductor device comprising: a separating film; a pair of complementary channel layers opposed to each other via the separating film; a first carrier supply and withdrawal region connected to one of the pair of complementary channel layers; a third channel layer connected to the one channel layer; a third carrier supply and withdrawal region connected to the third channel layer; a fourth channel layer connected to the other of the pair of complementary channel layers; a fourth carrier supply and withdrawal region connected to the fourth channel layer; a first conductive electrode insulated from and capacitively coupled to the one channel layer; a second conductive electrode insulated from and capacitively coupled to the other channel layer; a third conductive electrode insulated from and capacitively coupled to the third channel layer; and a fourth conductive electrode insulated from and capacitively coupled to the fourth channel layer; the separating film is a semiconductor or an insulating film having an electron barrier at an interface between one channel layer and the other channel layer of the pair of complementary channel layers, the electron barrier preventing carriers stored in each of the one channel layer and the other channel layer from being transported to the opposing channel layer.

12. A semiconductor memory array comprising a plurality of semiconductor memory cells according to claim 11, wherein for each memory cell: a total of three write word lines, namely, a first, second and third write word line of the array; one write digit line of the array; one read word line of the array; and one read digit line of the array; the first carrier supply and draw-out region is connected to a reference potential of the array; the fourth carrier supply and draw-out region is connected to the write digit line of the array; the first conductive electrode, the second conductive electrode and the fourth conductive electrode are connected to the first, second and third write word lines of the array, respectively; the third carrier supply and draw-out region is connected to the read digit line of the array; and the third control electrode is connected to the read word line of the array.

13. A semiconductor device comprising at least a first semiconductor layer, a second semiconductor layer, a separating layer, a first carrier supply and extraction region, a second carrier supply and extraction region, an intermediate carrier supply and extraction region, a third semiconductor layer, a third carrier supply and extraction region, a first insulating film, a first conductive film, a second insulating film, a second conductive film, a third insulating film, and a third conductive film, wherein the first semiconductor layer accumulates and transports carriers of a first conductivity type, and the second semiconductor layer accumulates and transports carriers of a second conductivity type, i.e., carriers of an opposite conductivity type to the first conductivity type, the first semiconductor layer and the second semiconductor layer are separated by the separating layer, and the separating layer has a first surface in contact with the first semiconductor layer and a second surface in contact with the second semiconductor layer, the first surface has a first electron barrier against carriers of the first conductivity type, preventing the carriers of the first conductivity type from being transported to the second semiconductor layer through the separation layer; and the second surface has a second electron barrier against carriers of the second conductivity type, preventing the carriers of the second conductivity type from being transported to the first semiconductor layer through the separation layer; the semiconductor or insulator forms the first electron barrier and the second electron barrier for the first semiconductor layer and the second semiconductor layer, respectively; the first conductivity type carriers and the second conductivity type carriers can exist in the first semiconductor layer and the second semiconductor layer in a state where they are electrostatically attracted to each other via the separation layer; the first carrier supply and extraction region is connected to the first semiconductor layer, and the first carrier supply and extraction region is one of a semiconductor region of the first conductivity type, a semiconductor region forming a heterojunction with the first semiconductor layer, and a region forming a Schottky junction with the first semiconductor layer; the second carrier supply and extraction region is connected to the second semiconductor layer, and is one of a semiconductor region of a second conductivity type, a semiconductor region that forms a heterojunction with the second semiconductor layer, or a region that forms a Schottky junction with the second semiconductor layer; the third semiconductor layer is a semiconductor layer that can accumulate and transport the first conductivity type carriers, and is connected to the first semiconductor layer via the intermediate carrier supply and extraction region and is connected to the third carrier supply and extraction region;the intermediate carrier supply and extraction region is one of a semiconductor region of a first conductivity type, or a semiconductor region forming a heterojunction with the first semiconductor layer and the third semiconductor layer, or a region forming a Schottky junction with the first semiconductor layer and the third semiconductor layer; the third carrier supply and extraction region is one of a semiconductor region of a first conductivity type, or a semiconductor region forming a heterojunction with the third semiconductor layer, or a region forming a Schottky junction with the third semiconductor layer; the first insulating film is provided on a surface of the first semiconductor layer facing the separating layer; the first conductive film is provided on a surface of the first insulating film and is electrostatically coupled to the first semiconductor layer; the second insulating film is provided on a surface of the second semiconductor layer facing the separating layer; the second conductive film is provided on a surface of the second insulating film so as to be electrostatically coupled to the second semiconductor layer; and the third insulating film is provided on a surface of the third semiconductor layer. the third conductive film is provided on a surface of the third insulating film so as to be electrostatically coupled to the third semiconductor layer.

14. A semiconductor device comprising at least a first semiconductor layer, a second semiconductor layer, a separating layer, a first carrier supply and extraction region, a second carrier supply and extraction region, a third semiconductor layer, a third carrier supply and extraction region, a seventh insulating film, a first conductive film, a second insulating film, a second conductive film, a ninth insulating film, and a third conductive film, wherein the first semiconductor layer accumulates and transports carriers of a first conductivity type, and the second semiconductor layer accumulates and transports carriers of a second conductivity type, i.e., carriers of an opposite conductivity type to the first conductivity type, the first semiconductor layer and the second semiconductor layer are separated by the separating layer, and the separating layer has a first surface in contact with the first semiconductor layer and a second surface in contact with the second semiconductor layer, and the first surface has a first electron barrier against carriers of the first conductivity type, the first conductive type carriers are prevented from being transported to the second semiconductor layer through the separating layer, and the second surface has a second electronic barrier against the second conductive type carriers; the second surface is a semiconductor or an insulator having the first and second electronic barriers against the first semiconductor layer and the second semiconductor layer, respectively, which prevent the second conductive type carriers from being transported to the first semiconductor layer through the separating layer; the first conductive type carriers and the second conductive type carriers can exist in a state where they are electrostatically attracted to each other via the separating layer; the first carrier supply and extraction region is connected to the first semiconductor layer, and the first carrier supply and extraction region is one of a first conductive type semiconductor region, a semiconductor region forming a heterojunction with the first semiconductor layer, or a region forming a Schottky junction with the first semiconductor layer; the second carrier supply and extraction region is connected to the second semiconductor layer, and the second carrier supply and extraction region is one of a semiconductor region of a second conductivity type, a semiconductor region that forms a heterojunction with the second semiconductor layer, or a region that forms a Schottky junction with the second semiconductor layer; the third semiconductor layer is a semiconductor layer that can accumulate and transport the first conductivity type carriers, and is connected to the first semiconductor layer;the third carrier supply and extraction region is connected to the third semiconductor layer, and the third carrier supply and extraction region is one of a first conductivity type semiconductor region, a semiconductor region forming a heterojunction with the third semiconductor layer, or a region forming a Schottky junction with the third semiconductor layer; the seventh insulating film is provided on the surface of the first semiconductor layer facing the separation layer; the first conductive film is provided on the surface of the seventh insulating film and is electrostatically coupled to the first semiconductor layer; the second insulating film is provided on the surface of the second semiconductor layer facing the separation layer; the second conductive film is provided on the surface of the second insulating film so as to be electrostatically coupled to the second semiconductor layer; the seventh insulating film is provided on the surface of the third semiconductor layer in a state extending from the surface of the first semiconductor layer; and the third conductive film is provided on the surface of the seventh insulating film so as to be electrostatically coupled to the third semiconductor layer; the first conductive film and the third conductive film are insulated from each other by a ninth insulating film.

15. A semiconductor memory array comprising a plurality of semiconductor memory cells according to claim 13, and for each memory cell, two write word lines of the array, one write digit line of the array, one read word line of the array, and one read digit line of the array; the first carrier supply and draw-out region is connected to a reference potential line of the array, the second carrier supply and draw-out region is connected to the write digit line of the array, and the third carrier supply and draw-out region is connected to the read digit line of the array; the first conductive film and the second conductive film are each connected to one of two write word lines of the array extending in a direction perpendicular to the plane of the paper, and the third conductive film is connected to a read word line of the array extending in a direction perpendicular to the plane of the paper; and the semiconductor memory array is characterized in that it is composed of a plurality of the semiconductor memory cells arranged in a direction perpendicular to the plane of the paper and a plurality of the semiconductor memory cells arranged on the left and right of the plane of the paper.

16. A semiconductor memory array comprising a plurality of semiconductor memory cells according to claim 14, and for each memory cell, two write word lines of the array, one write digit line of the array, one read word line of the array, and one read digit line of the array; the first carrier supply and draw-out region is connected to a reference potential line of the array, the second carrier supply and draw-out region is connected to the write digit line of the array, and the third carrier supply and draw-out region is connected to the read digit line of the array; the first conductive film and the second conductive film are each connected to one of two write word lines of the array extended in a direction perpendicular to the plane of the paper, and the third conductive film is extended in a direction perpendicular to the plane of the paper and connected to the read word line of the array; and the semiconductor memory array is characterized in that it is composed of a plurality of the semiconductor memory cells arranged in a direction perpendicular to the plane of the paper and a plurality of the semiconductor memory cells arranged in a left-right direction parallel to the plane of the paper.

17. A semiconductor memory array according to claim 15, wherein the number of write word lines of the array allocated to the memory cells is one, and the first conductive film and the second conductive film are connected to the one write word line of the array.

18. A semiconductor memory array according to claim 16, wherein the number of write word lines of the array allocated to the memory cells is one, and the first conductive film and the second conductive film are connected to the one write word line of the array.

19. A semiconductor memory array comprising a plurality of semiconductor memory cells according to claim 13, and for each memory cell, one write word line of the array, one write digit line of the array, one read word line of the array, and one read digit line of the array; the first carrier supply and draw-out region is connected to a reference potential line of the array, the second carrier supply and draw-out region is connected to a reference potential line of the array, the third carrier supply and draw-out region is connected to a read digit line of the array, the first conductive film is connected to the write word line of the array extending in a direction perpendicular to the plane of the paper, the second conductive film is connected to the one write digit line of the array extending in a direction parallel to the plane of the paper, and the third conductive film is connected to the read word line of the array extending in a direction perpendicular to the plane of the paper; and the semiconductor memory array is composed of a plurality of the semiconductor memory cells arranged in a direction perpendicular to the plane of the paper and a plurality of the semiconductor memory cells arranged in a direction parallel to the plane of the paper.

20. A semiconductor memory array comprising a plurality of semiconductor memory cells according to claim 14, and for each memory cell, one write word line of the array, one write digit line of the array, one read word line of the array, and one read digit line of the array; the first carrier supply and draw-out region is connected to a reference potential line of the array, the second carrier supply and draw-out region is connected to a reference potential line of the array, and the third carrier supply and draw-out region is connected to a read digit line of the array, a first conductive film is connected to the write word line of the array extending in a direction perpendicular to the plane of the paper, a second conductive film is connected to the write digit line of the array extending in a direction parallel to the plane of the paper, and a third conductive film is connected to the read word line of the array extending in a direction perpendicular to the plane of the paper, and a plurality of the semiconductor memory cells arranged in a direction perpendicular to the plane of the paper and a plurality of the semiconductor memory cells arranged on the left and right of the direction parallel to the plane of the paper.

21. A semiconductor device comprising at least a first semiconductor layer capable of storing and transporting carriers of a first conductivity type, a second semiconductor layer capable of storing and transporting carriers of a conductivity type (second conductivity type) opposite to the first conductivity type, a separation film separating the first semiconductor layer and the second semiconductor layer, a first carrier supply and extraction region connected to the first semiconductor layer, a third semiconductor layer connected to the first semiconductor layer on a side facing the first carrier supply and extraction region, a third carrier supply and extraction region connected to the third semiconductor layer on a side facing the first semiconductor layer, a fourth semiconductor layer connected to the second semiconductor layer, a fourth carrier supply and extraction region connected to the fourth semiconductor layer, and a seventh insulating film provided on a surface of the first semiconductor layer facing the separation layer. a first conductive film provided on the surface of the seventh insulating film and electrostatically coupled to the first semiconductor layer; a third conductive film provided on the surface of the seventh insulating film, extending to the surface of the third semiconductor layer, and electrostatically coupled to the third semiconductor layer; a ninth insulating film insulating the third conductive film from the first conductive film; a sixth insulating film provided on the surface of the second semiconductor layer facing the separation layer; a second conductive film provided on the surface of the sixth insulating film and electrostatically coupled to the second semiconductor layer; a fourth conductive film provided on the surface of the sixth insulating film, extending to the surface of the fourth semiconductor layer, and electrostatically coupled to the fourth semiconductor layer; and an eighth insulating film insulating the second conductive film from the fourth conductive film, wherein the separation layer has a first surface in contact with the first semiconductor layer and a second surface in contact with the second semiconductor layer, The first surface has a first electron barrier against carriers of the first conductivity type, preventing carriers of the first conductivity type from being transported through the separation layer to the second semiconductor layer, and the second surface has a second electron barrier against carriers of the second conductivity type, preventing carriers of the second conductivity type from being transported through the separation layer to the first semiconductor layer.a semiconductor or insulator having a second electron barrier, the first conductivity type carriers and the second conductivity type carriers can exist in a state of being electrostatically attracted to each other via the separating layer, the first carrier supply and extraction region is one of a semiconductor region of a first conductivity type, a semiconductor region forming a heterojunction with the first semiconductor layer, and a region forming a Schottky junction with the first semiconductor layer, the third semiconductor layer is a semiconductor layer capable of transporting the first conductivity type carriers, the third carrier supply and extraction region is one of a semiconductor region of a first conductivity type, a semiconductor region forming a heterojunction with the third semiconductor layer, and a region forming a Schottky junction with the third semiconductor layer, the fourth semiconductor layer is a semiconductor layer capable of transporting the second conductivity type carriers, and the fourth carrier supply and extraction region is one of a semiconductor region of a second conductivity type, a semiconductor region forming a heterojunction with the fourth semiconductor layer, and a region forming a Schottky junction with the fourth semiconductor layer.

22. A semiconductor memory array comprising a plurality of semiconductor memory cells according to claim 21, and for each memory cell, three write word lines of the array, one write digit line of the array, one read word line of the array, and one read digit line of the array; connecting the first carrier supply and draw-out region to a reference potential line of the array, connecting the fourth carrier supply and draw-out region to the write digit line of the array, connecting the third carrier supply and draw-out region to the read digit line of the array, connecting the first conductive film, the second conductive film, and the fourth conductive film to each of three write word lines of the array extending in a direction perpendicular to the plane of the paper, and connecting the third gate conductive film to a read word line of the array extending in a direction perpendicular to the plane of the paper, thereby comprising a plurality of the semiconductor memory cells arranged in a direction perpendicular to the plane of the paper and a plurality of the semiconductor memory cells arranged on the left and right sides of the plane of the paper.

Images