Semiconductor device

Abstract

[Problem] To significantly reduce the channel resistance (Rch) of an SiC-MOSFET. [Solution] The present invention provides a semiconductor device which is a planar MOSFET 200 including a MOS structure in which a second SiC epitaxial layer of a first conductivity type is formed between an SiC interface and a gate insulating film, wherein: by increasing the impurity concentration of a body region 23, the channel length Lch can be shortened, which reduces the channel resistance and also allows the punch-through voltage to be increased; by adjusting the concentration Nce and thickness Tce of a channel epitaxial layer 25, Vth can be controlled; and the value of the impurity concentration of the body region 23 and Vth can be designed each independently.

Description

Semiconductor Devices

[0001] The present invention relates to a semiconductor element, and more particularly to a silicon carbide semiconductor element (power semiconductor device) used for high voltage and large current applications. The present invention also relates to a semiconductor device including a silicon carbide semiconductor element.

[0002] Silicon carbide (SiC) is a semiconductor material with a larger band gap and higher hardness than silicon (Si), and is applied to various semiconductor devices such as power elements, environmentally resistant elements, high-temperature operating elements, and high-frequency elements. Among these, its application to power elements such as switching elements and rectifier elements has attracted attention. Power elements using SiC have the advantage of being able to significantly reduce power loss compared to Si power elements. Furthermore, by taking advantage of these characteristics, SiC power elements can realize semiconductor devices that are smaller in size than Si power elements.

[0003] International Publication No. 2015 / 198468

[0004] Metal-insulator-semiconductor field-effect transistors (SiC-MOSFETs) that use SiC materials have the problem of low channel mobility and high channel resistance (Rch). This is primarily due to a high trap density at the interface. The electric field strength of SiC materials is approximately 10 times higher than that of Si, making it possible to reduce the resistance of the MOSFET's drift layer to several hundredths of that of Si. However, because the high Rch results in a high on-resistance (Ron), it is said that the application area of ​​SiC-MOSFETs is limited to power devices of 600 V or higher.

[0005] Research and development to improve channel mobility has been conducted for many years, mainly focusing on improving wafer processes and devising the surface orientation of SiC materials. In addition, a structural innovation has been proposed in which a thin-film SiC epitaxial layer (channel epitaxial layer) is inserted between the SiC and gate insulating film to improve channel mobility. Although improvements have been made over decades, the effective channel mobility (Uef) of SiC is only about 50 cm2 / Vs at the product level, half that of silicon (Si), at 100 cm2 / Vs, and is still insufficient. The problem is that it is difficult to significantly reduce the channel resistance of SiC-MOSFETs.

[0006] An object of the present invention is to significantly reduce the channel resistance (Rch) of a SiC-MOSFET.

[0007] a gate insulating film on the second silicon carbide semiconductor layer; the gate electrode on the gate insulating film; the source electrode in contact with the source region and the body region; and the drain electrode provided on a back surface of the semiconductor substrate. The semiconductor device according to the present invention is a semiconductor device comprising: a semiconductor element including a metal-insulator-semiconductor field effect transistor; and a potential setting unit that sets a potential of the semiconductor element, wherein the potential setting unit comprises a gate electrode, a source electrode, and a drain electrode. The metal-insulator-semiconductor field effect transistor comprises: a semiconductor substrate of a first conductivity type; a first silicon carbide semiconductor layer of the first conductivity type located on a main surface of the semiconductor substrate; a body region of a second conductivity type located in the first silicon carbide semiconductor layer; a source region of the first conductivity type located in the body region; a second silicon carbide semiconductor layer of the first conductivity type formed on the first silicon carbide semiconductor layer and in contact with at least a portion of the body region and the source region;

[0008] In the semiconductor device according to the present invention, it is preferable that the impurity concentration Npw of the body region is adjusted to control the channel length Lch to a predetermined value.

[0009] Furthermore, in the semiconductor device according to the present invention, when the impurity concentration of the second silicon carbide semiconductor layer is Nce and the thickness of the second silicon carbide semiconductor layer is Tce, it is preferable to adjust Nce and / or Tce to set the gate threshold voltage Vth to a predetermined value.

[0010] Furthermore, in the semiconductor device according to the present invention, it is preferable that when the voltage of the drain electrode is Vds and the current flowing through the drain electrode is Id, a saturation current is Idsat, an impurity concentration of the second silicon carbide semiconductor layer is Nce, and a thickness of the second silicon carbide semiconductor layer is Tce, when Idsat is greater than a predetermined value, Npw is increased and / or Tce is shortened and / or Nce is increased and / or a channel length Lch is lengthened to reduce Idsat to the predetermined value, and when Idsat is smaller than the predetermined value, Npw is decreased and / or Tce is lengthened and / or Nce is decreased and / or Lch is shortened to increase Idsat to the predetermined value.

[0011] Furthermore, in the semiconductor device of the present invention, when the channel length Lch is shortened, Lch at which the punch-through voltage Vpt begins to become smaller than a predetermined value is defined as Lchminpt, and when the channel length Lch is shortened, Lch at which the gate threshold voltage Vth begins to drop sharply is defined as Lchminsc, and when Lchminpt is longer than Lchminsc, it is preferable to increase the impurity concentration Npw of the body region and control Lchminpt to a value equal to or less than Lchminsc.

[0012] In the semiconductor device according to the present invention, when the thickness of the second silicon carbide semiconductor layer is defined as Tce, Tce is preferably 8 nm or more.

[0013] In the semiconductor device according to the present invention, when the impurity concentration of the second silicon carbide semiconductor layer is defined as Nce, the Nce is preferably 1e17 cm-3 or more.

[0014] In the semiconductor device according to the present invention, when the thickness of the second silicon carbide semiconductor layer is defined as Tce, Tce is preferably 100 nm or less.

[0015] Furthermore, in the semiconductor device according to the present invention, when the voltage Vgs of the gate electrode is set to 0 V and the voltage Vds of the drain electrode is set to 0 V, the length of the depletion layer of the PN junction between the body region and the source region is set to dbs, the length of the depletion layer of the PN junction between the body region and the first silicon carbide semiconductor layer is set to dbj, and the larger value of dbs and dbj is set to dm, it is preferable that the thickness Tce of the second silicon carbide semiconductor layer is equal to or greater than dm.

[0016] Furthermore, in the semiconductor device according to the present invention, a third silicon carbide semiconductor layer of a second conductivity type is formed between the second silicon carbide semiconductor layer of the first conductivity type and the gate insulating film, and the second silicon carbide semiconductor layer of the first conductivity type has an impurity concentration Ncen, a thickness Tcen, and a fixed charge when depleted Qcen, where Qcen is q*Ncen*Tcen, and the third silicon carbide semiconductor layer of the second conductivity type has an impurity concentration Ncep, a thickness Tcep, and a fixed charge when depleted Qcep, where Qcep is q*Ncep*Tcep, and when Tce is the sum of Tcen and Tcep and Qce is the difference between Qcen and Qcep, Qcen can be expressed as follows: The capacitance is equal to or greater than Qcep, and by adjusting Qce, Tce, Qcen, Ncen, Tcen, Qcep, Ncep and / or Tcep, the gate threshold voltage Vth, punch-through voltage Vpt, Lchminsc, which is the Lch at which the gate threshold voltage Vth begins to drop sharply when the channel length Lch is shortened, Lchminpt, which is the Lch at which the punch-through voltage Vpt begins to become smaller than a predetermined value when the channel length Lch is shortened, and / or the saturation current Idsat, where Id is the current flowing to the drain electrode when the voltage Vds of the drain electrode is increased, can be controlled.

[0017] In the semiconductor device according to the present invention, the impurity concentration Npw of the body region is preferably set to 1e19 cm −3 or more.

[0018] According to the present invention, the channel resistance (Rch) of a SiC-MOSFET can be significantly reduced, and the impurity concentration value of the body region and Vth can be designed independently.

[0019] 1 is a graph showing the relationship between minimum channel length (Lchminsc) and gate threshold voltage (Vth) in an embodiment of the present invention; FIG. 2 is a graph showing the relationship between Vth, Nce, and Tce in an embodiment of the present invention; FIG. 3 is a cross-sectional view of a planar MOSFET of the prior art; FIG. 4 is a cross-sectional view of a planar MOSFET of an embodiment of the present invention; FIG. 5 is a cross-sectional view of a trench MOSFET of an embodiment of the present invention; FIG. 6 is an enlarged cross-sectional view of a PN junction and an insulating film, showing an intersection of the PN junction and the gate insulating film where a high electric field occurs, in an embodiment of the present invention; FIG. 7 is an enlarged cross-sectional view of a PN junction and an insulating film, showing electric field lines, in an embodiment of the present invention; FIG. 8 is an enlarged cross-sectional view of a PN junction and an insulating film, showing a structure to which channel epitaxy is applied, in an embodiment of the present invention; FIG. 9 is a structure to which channel epitaxy composed of two impurity type layers is applied, in an embodiment of the present invention; FIG. 10 is a diagram showing that the slope of the energy band can be made gentle by forming the channel epitaxy as a two-layer structure of an N-type layer and a P-type layer in an embodiment of the present invention; FIG. 11 is a conduction band diagram of a PN junction at a SiC interface in an embodiment of the present invention; FIG. 12 is a diagram showing the relationship between Lchminsc, equivalent channel epitaxy mobility, and Npw in an embodiment of the present invention.

[0020] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following, similar elements in all drawings will be designated by the same reference numerals, and duplicate explanations will be omitted. Furthermore, in the description below, previously described reference numerals will be used as necessary.

[0021] First, a conventional SiC-MOSFET will be described with reference to FIG. 3. It has a generally well-known structure. FIG. 3 shows a vertical planar SiC-MOSFET 100. The semiconductor substrate 1 is an N-type SiC substrate. N-type SiC is formed by epitaxial growth on the semiconductor substrate 1 as a first silicon carbide semiconductor layer 2. This is an N-type drift region for blocking high voltage. For example, in the case of a SiC-MOSFET with a breakdown voltage of 600 V to 1200 V, the impurity in the drift layer is nitrogen, the impurity concentration is 5e15 cm-3 to 5e16 cm-3, and the thickness is 5 um to 12 um.

[0022] A second conductivity type body region 3 is formed above the drift layer by ion implantation. For example, the impurity in the second conductivity type body region 3 is aluminum, and the impurity concentration (Npw) is 1e17 cm-3 to 5e17 cm-3. A first conductivity type source region 4 is formed in the body region 3. The source region 4 is formed by ion implantation using nitrogen as the impurity at a concentration of 1e19 cm-3 to 1e20 cm-3.

[0023] A gate insulating film 6 is formed on the first silicon carbide semiconductor layer 2 and in contact with at least a portion of the body region 3 and the source region 4. The gate insulating film 6 may be formed by thermal oxidation or may be an oxide film formed by a deposition process. A gate electrode 7 is formed on and in contact with the gate insulating film 6. The gate electrode 7 may be made of polysilicon or a metal such as aluminum.

[0024] A source electrode 8 is formed in contact with the surface of the source region 4 and the surface of the body region 3. A drift electrode 9 is formed on the back surface of the semiconductor substrate 1. A JFET region 10 is located between the left and right body regions 3. The source region 4, JFET region 10, and the surface of the body region 3 are in contact with the gate insulating film 6, and this contact surface is the SiC interface of the MOS structure. In the MOSFET, the source region 4 functions as the source, the JFET region 3 functions as the drain, and the interface between the body region 3 functions as the MOS channel. The channel length is shown as Lch in FIG. 3.

[0025] That is, prior art SiC-MOSFET 100 is a semiconductor device comprising a semiconductor element including a metal-insulator-semiconductor field effect transistor and a potential setting unit that sets the potential of the semiconductor element, the potential setting unit comprising a gate electrode 7, a source electrode 8, and a drain electrode 9, and the metal-insulator-semiconductor field effect transistor comprises a semiconductor substrate 1 of a first conductivity type, a first silicon carbide semiconductor layer 2 of the first conductivity type located on a major surface of the semiconductor substrate 1, a body region 3 of a second conductivity type located in the first silicon carbide semiconductor layer 2, and a second silicon carbide semiconductor layer 4 of a second conductivity type located in the body region 3. The semiconductor device includes a source region 4 of one conductivity type, a gate insulating film 6 on the first silicon carbide semiconductor layer 2, a gate electrode 7 on the gate insulating film 6, a source electrode 8 in contact with the source region 4 and the body region 3, and a drain electrode 9 provided on the back surface of the semiconductor substrate 1, and a region of the first silicon carbide semiconductor layer 2 between the two body regions 3 is called a JFET region 10, an impurity concentration of the body region 3 is called a first Npw, and a length from a position of a PN junction formed by the source region 4 and the body region 3 to a position of a PN junction formed by the body region 3 and the JFET region 10 at the interface between the body region 3 and the gate insulating film 6 is called a first Npw. The channel length that is the longest is defined as a first Lch, the gate threshold voltage of the metal-insulator-semiconductor field effect transistor is defined as a first Vth, the voltage of the gate electrode 7 relative to the voltage of the source electrode 8 is defined as Vgs, the voltage of the drain electrode 9 relative to the voltage of the source electrode 8 is defined as Vds, the current flowing through the drain electrode 9 is defined as Id, and when Vgs is set to a voltage higher than Vth so that the metal-insulator-semiconductor field effect transistor is in a conductive state, the saturation current at which Id saturates when Vds is increased is defined as a first Idsat, and when Vgs is set to a voltage lower than Vth so that Id does not flow, As Vds is increased, the depletion layer in the body region 3 extends from the PN junction between the body region 3 and the first silicon carbide semiconductor layer 2 toward the source region 4, and the Vds at which the depletion layer in the body region 3 reaches the source region 4 and Id begins to flow is called the punch-through voltage. This punch-through voltage is defined as the first Vpt, Lch at which the first Vth begins to drop sharply as Lch is shortened is defined as the first Lchminsc, and Lch at which the first Vpt begins to become smaller than a predetermined value as Lch is shortened is defined as the first Lchminpt.Npw is set so that the first Vth becomes a predetermined value.

[0026] (Embodiment 1) Fig. 4 shows a cross-sectional view of a vertical planar SiC-MOSFET 200 to which the present invention is applied. An explanation will be given using Fig. 4. Compared to Fig. 3 of the above-mentioned prior art, the only difference is that a channel epitaxial layer 25, which is a silicon carbide semiconductor layer of the first conductivity type, is formed between the SiC interface and the gate oxide film 26. Other than that, the structure is basically the same.

[0027] The semiconductor substrate 21 is an N-type SiC substrate. N-type SiC is formed by epitaxial growth on the silicon carbide semiconductor substrate 21 as a first semiconductor layer 22. This is an N-type drift region for blocking high voltage. For example, in the case of a SiC-MOSFET with a breakdown voltage of 600 V to 1200 V, the impurity in the drift layer is nitrogen, the impurity concentration is 5e15 cm-3 to 5e16 cm-3, and the thickness is 5 to 12 μm.

[0028] A second conductivity type body region 23 is formed above the drift layer by ion implantation. For example, the impurity in the second conductivity type body region 23 is aluminum, and the impurity concentration (Npw) is 1e18 cm-3 to 1e20 cm-3. A first conductivity type source region 24 is formed in the body region 23. The source region is formed by ion implantation using nitrogen as the impurity at a concentration of 1e19 cm-3 to 1e20 cm-3.

[0029] A channel epitaxial layer 25, which is a silicon carbide semiconductor of a first conductivity type, is formed on the first silicon carbide semiconductor layer 22 and in contact with at least a portion of the body region 23 and the source region 24. The channel epitaxial layer 25 is formed by an epitaxial process. The impurity is nitrogen, the impurity concentration (Nce) is 1e15 cm-3 to 1e20 cm-3, and the thickness (Tce) is 8 nm to 100 nm.

[0030] A gate insulating film 26 is formed on and in contact with the channel epitaxial layer 25. The gate insulating film 26 may be thermally oxidized or may be an oxide film formed by a deposition process. A gate electrode 27 is formed on and in contact with the gate insulating film. The gate electrode 27 may be made of polysilicon or a metal such as aluminum.

[0031] A source electrode 28 is formed in contact with the surface of the source region 24 and the surface of the body region 23. A drift electrode 29 is formed on the back surface of the semiconductor substrate 21. A JFET region 30 is located between the left and right body regions 23. A gate insulating film is formed on the JFET region 30. The source region 24, JFET region 30, and the surfaces of the body region 23 are in contact with the channel epitaxial layer 25. The contact surface between the channel epitaxial layer 25 and the gate insulating film 26 is the SiC interface. In the MOSFET, the source region 24 functions as the source, the JFET region 23 functions as the drain, and the SiC interface located above the body region 23 functions as the MOS channel. The channel length is indicated as Lch in the figure.

[0032] That is, SiC-MOSFET 200 is a semiconductor device comprising a semiconductor element including a metal-insulator-semiconductor field effect transistor and a potential setting unit that sets the potential of the semiconductor element, wherein the potential setting unit comprises gate electrode 27, source electrode 28, and drain electrode 29, and the metal-insulator-semiconductor field effect transistor comprises semiconductor substrate 21 of a first conductivity type, first silicon carbide semiconductor layer 22 of the first conductivity type located on the main surface of semiconductor substrate 21, body region 23 of a second conductivity type located in first silicon carbide semiconductor layer 22, and a gate electrode 29 of a second conductivity type located in body region 23. a second silicon carbide semiconductor layer 25 of the first conductivity type formed on the first silicon carbide semiconductor layer 22 and in contact with at least a part of the body region 23 and the source region 24; a gate insulating film 26 on the second silicon carbide semiconductor layer 25; a gate electrode 27 on the gate insulating film 26; a source electrode 28 in contact with the source region 24 and the body region 23; and a drain electrode 29 provided on the back surface of the semiconductor substrate 21. A region of the first silicon carbide semiconductor layer 22 between the two body regions 23 is referred to as a JFET region 30, and an impurity concentration of the body region 23 is referred to as a is defined as a second Npw, the impurity concentration of the second silicon carbide semiconductor layer 25 is defined as Nce, the thickness of the second silicon carbide semiconductor layer 25 is defined as Tce, the channel length which is the length from the position of the PN junction formed by the source region 24 and the body region 23 at the interface between the body region 23 and the gate insulating film 26 to the position of the PN junction formed by the body region 23 and the JFET region 30 is defined as a second Lch, the gate threshold voltage of the metal-insulator-semiconductor field effect transistor is defined as a second Vth, the voltage of the gate electrode 27 with respect to the voltage of the source electrode 28 as a reference is Vgs, the drain voltage The voltage of drain electrode 29 is Vds, the current flowing through drain electrode 29 is Id, and Vgs is set to a voltage higher than Vth to place the metal-insulator-semiconductor field effect transistor in a conductive state. When Vds is increased, the saturation current at which Id saturates is set to a second Idsat. When Vgs is set to a value equal to or lower than Vth to place Id in a non-flowing state, and Vds is increased, the depletion layer in body region 23 extends from the PN junction between body region 23 and first silicon carbide semiconductor layer 22 toward source region 24, and the depletion layer in body region 23 reaches source region 24,Vds at which Id begins to flow is defined as the punch-through voltage, and this punch-through voltage is defined as the second Vpt, Lch at which the second Vth begins to drop sharply as Lch is shortened is defined as the second Lchminsc, and Lch at which the second Vpt begins to become smaller than the desired value as Lch is shortened is defined as the second Lchminpt, and the second Npw is characterized by being greater than 1e18 cm-3.

[0033] (Problem 1) As described above, there has been a problem in the past in that it is difficult to significantly reduce the channel resistance (Rch) of SiC-MOSFETs. In addition to improving channel mobility, reducing Rch is also possible by shortening the channel length (Lch). Because Rch is proportional to Lch, the shorter Lch is, the more Rch can be reduced. However, shortening Lch causes a short channel effect, which reduces the gate threshold voltage (Vth) of the MOSFET. The short channel effect can be alleviated by increasing the impurity concentration (Npw) of the body region 23, but this also increases Vth. Because Vth must be a desired value, Npw cannot be increased indefinitely.

[0034] The Vth of a SiC-MOSFET is typically between 3V and 5V. Increasing Vth increases Rch. In the case of SiC-MOSFETs, the problem of high Rch makes it desirable to set Vth as small as possible. However, if Vth is lowered too much, there is a risk of malfunction due to noise in the electrical circuit. For this reason, the minimum Vth value is said to be approximately 3V.

[0035] In order to design SiC-MOSFETs to have a low Vth, Npw is set to 1e17cm-3 to 5e18cm-3, and cannot be made any higher. This impurity concentration determines the degree of the short channel effect, and the minimum Lch (Lchminsc) constrained by this is 0.3um. If Lch is made shorter than 0.3um, Vth decreases, and it cannot be made significantly shorter. This is one of the reasons why it is difficult to reduce Rch in SiC-MOSFETs. Thus, there is a problem in that Lchminsc cannot be made significantly shorter. Figure 1 shows how Lchminsc becomes longer when Vth is designed to be low. There is a problem in that Vth and Lchminsc cannot be designed independently.

[0036] (Means for solving problem 1) The second silicon carbide semiconductor layer 25 is a channel epitaxial layer, and the impurity type is a first conductivity type. By increasing Npw of the SiC-MOSFET 200 according to the embodiment of the present invention compared to Npw of the conventional technology, Lchminsc can be shortened. This makes it possible to reduce Rch. Increasing Npw increases Vth of the SiC-MOSFET 200, so Nce and Tce of the channel epitaxial layer 25 are adjusted so that Vth becomes a desired value. Increasing Nce decreases Vth, and thickening Tce decreases Vth. This is shown in FIG. 2. Vth can be controlled by adjusting Nce, Tce, or both.

[0037] When the epitaxial channel 25 is depleted, it becomes a fixed charge near the interface in the MOS structure. The impurity charge (Qce) of the epitaxial channel 25 is Qce = q * Nce * Tce, where q is the elementary charge. The value by which Qce lowers Vth (ΔVth) is approximately ΔVth = Qce / Cox, where Cox is the capacitance between the gate electrode and the body region of the MOS structure. The maximum ΔVTH that can be adjusted by Qce is several tens of volts.

[0038] For example, even if the Npw concentration is 1e20 cm-3, which is the commonly-known maximum impurity concentration of SiC, and the Vth determined by this Npw is several tens of volts, it is possible to control the Vth to a desired value, for example, 3V to 5V, by adjusting Qce. Since the higher Npw, the shorter Lchminsc and the lower Rch can be achieved, it is advisable to set Npw as high as possible. Since Vth increases in this case, Qce can be adjusted to achieve a predetermined Vth value. This has the advantage of significantly shortening Lchminsc and significantly reducing Rch. Furthermore, applying a channel epitaxial layer 25 has the advantage of allowing Vth and Npw to be designed independently. The relationship between Lchminsc and Npw will be explained using the conduction band (Ec) in Figure 9. This shows the Ec of the PN junction between the N-type layer and the P-type body region at the SiC interface. The horizontal axis represents the distance from the PN junction, with 0 representing the PN junction location, the N-layer region to the left of 0, and the body region to the right of 0. The N-type layer is the source region or JFET region. The N-type layer has a region where Ec is a low, constant value, the body region has a region where Ec is a high, constant value, and there is a transition region in between. Lslope in the figure is the length from 0 to the region where Ec is high and constant. Lchminsc is the sum of the Lslope of the PN junction between the source region and the body region and the Lslope of the PN junction between the JFET region and the body region. The higher Npw, the shorter Lslope and therefore the shorter Lchminsc. Figure 10 shows the relationship between Lchminsc and Npw obtained by numerical analysis. Increasing Npw shortens Lchminsc. Lch can be reduced to 0.25 μm or less when Npw is 1e18 cm-3 or more, to 0.2 μm or less when Npw is 1e19 cm-3 or more, and to approximately 0.15 μm when Npw is 1e20 cm-3 or more. This invention enables significant reductions in Rch. Figure 10 also shows the equivalent channel mobility (Uefeq) when Npw is increased. When Lchminsc is shortened to reduce Rch, assuming that Lch is kept constant at 0.3 μm and Uef is increased instead, the Uef value that can achieve an equivalent Rch is defined as Uefeq. The Ron for a conventional MOSFET without channel epitaxy is taken as the reference, with Lch at 0.3 μm and Uef at 50 cm2 / Vs.Since Rch is proportional to Lchminsc / Uef, for example, if Lchminsc is 0.15 um, half of 0.3 um, Uefeq to obtain the same Rch will be doubled to 100 cm2 / Vs. Uefeq is calculated as 50 cm2 / Vs * Lchminsc / 0.3 um. Uefeq can be increased to 60 cm2 / Vs or more when Npw is 1e18 cm-3 or more, and 75 cm2 / Vs or more when Npw is 1e19 cm-3 or more. At 1e20 cm-3, it can be increased to approximately 100 cm2 / Vs, resulting in Uef at the same level as Si, which corresponds to a significant improvement in Uef. Figure 10 was obtained assuming a certain Dit value and is only an example. In reality, the structure must be determined after manufacturing and confirming Vth and Lchminsc.

[0039] Example 1 The shorter Lch is, the more Rch can be reduced. When the short-channel effect restricts the minimum channel length (Lchminsc), Lchminsc can be shortened by increasing Npw. Increasing Npw also increases Vth, so Nce and Tce are adjusted to achieve the desired Vth. The amount of Vth variation is roughly proportional to Qce (= q * Nce * Tce). Increasing Nce decreases Vth, and increasing Tce decreases Vth. Since the Vth of a SiC-MOSFET varies depending on the thickness of the gate insulating film, the material of the gate electrode, the interface trap level density (Dit), and so on, to obtain the desired Vth, it is desirable to use a method in which the difference between the Vth obtained by the actual process and the desired Vth is adjusted by Qce.

[0040] By increasing Npw as much as possible, Lchminsc can be shortened, thereby lowering Rch. For example, Npw is 1e19 cm-3 or more, Tce = 20 to 50 nm, and Nce = 1e16 cm-3 to 1e20 cm-3. Npw may be increased to 1e20 cm-3. Under conditions for obtaining a constant Vth, the thinner Tce is, the higher Nce tends to be, and the thicker Tce is, the lower Nce tends to be. As described above, the embodiment can shorten Lchminsc to reduce Rch and simultaneously obtain a desired Vth. The SiC-MOSFET 200 of the present invention can independently control Lchminsc and Vth, which are limited by the short channel effect.

[0041] (Problem 2) Generally, the higher the drain saturation current (Idsat), the worse the short-circuit resistance. Since the Idsat of a SiC-MOSFET is higher than that of a Si-MOSFET, there is a problem in that the short-circuit resistance is worse than that of a Si-MOSFET.

[0042] (Means for solving problem 2) By applying the channel epitaxial structure of the present invention, Idsat can be reduced and short-circuit resistance can be improved. It is presumed that this is because when Npw is high, the slope of the conduction band at the SiC interface becomes steep, which increases scattering experienced by electrons in the channel, lowering the saturation velocity of electrons and resulting in a decrease in Idsat.

[0043] It is difficult to analytically or by TCAD simulation to show the relationship between Idsat and Npw. Npw must be determined by actually fabricating a device and measuring and confirming it. Idsat can be adjusted by Tce and Nce, and reducing Tce and / or increasing Nce will decrease Idsat.

[0044] Example 2 In the case of a conventional SiC-MOSFET, when Idsat is too high and short circuits are a problem, the structure of Example 1 can be used to improve the situation. When Idsat is higher than a predetermined value, it is advisable to increase Npw. Idsat can also be reduced by either thinning Tce or increasing Nce.

[0045] To obtain a predetermined Idsat, Tce is preferably 20 nm to 50 nm, and Nce is preferably 3e18 cm-3 or more.

[0046] (Problem 3) When Npw is set so that Vth becomes the desired value, the punch-through voltage (Vpt) may be lower than the desired value. In such cases, Lch is lengthened to increase Vpt and achieve the desired value. However, this method has the problem that Rch increases when Lch is lengthened.

[0047] Another method is to adjust the impurity concentration only in the region near the MOS interface rather than the entire body region to set Vth to a predetermined value, and then increase the impurity concentration in the rest of the body region to improve Vpt to a predetermined value. However, this method requires creating two regions in the body region with different impurity concentrations, which complicates the process and increases costs.

[0048] (Means for solving problem 3) SiC-MOSFETs are characterized by their high breakdown voltage, and therefore require a high punch-through voltage (Vpt). When Npw is set so that Vth reaches a desired value, Vpt may end up being lower than the desired value. In this case, Npw is set high to increase Vpt so that the desired value is reached. At this time, Vth also increases, so by adjusting Nce and Tce, the desired Vth can be achieved.

[0049] Furthermore, if Lchminpt, which is determined by the punch-through voltage, is longer than Lchminsc, which is determined by the short channel effect, it is desirable to further increase Npw so that Lchminpt becomes equal to or less than Lchminsc.

[0050] This method eliminates the problem of increased Rch, as it eliminates the need for the method of lengthening Lch, which was a solution used in the prior art. Furthermore, it eliminates the problem of increased process costs, as it does not require dividing the body region into two regions and setting different impurity concentrations. This solves the problem. The present invention can control Lchminpt, which is determined by the constraints of the punch-through effect, by adjusting Npw to be equal to or shorter than Lchminsc, which is determined by the constraints of the short channel effect. This minimizes Lch and reduces Rch. (Example 3) In prior art SiC-MOSFETs, when Lch is set to the value of Lchminsc, a problem sometimes occurs in which Vpt is lower than the desired value. In this example, by increasing Npw, Vpt can be increased, making it easy to set Vpt to the desired value. At the same time, Vth also fluctuates significantly, but the desired Vth can be obtained by adjusting Tce and Nce.

[0051] When the Vpt constraint Lchminpt is longer than Lchminsc, Rch is constrained by Vpt, so it is desirable to further increase Npw so that Lchminpt is the same value as Lchminsc or shorter. This is because Rch can be minimized. In the case of a SiC-MOSFET with a breakdown voltage of 600V to 1200V according to the present invention, Npw should be 1e18cm-3 to 1e20cm-3 to obtain the desired Vpt. When it is desired to reduce Rch, it is desirable to set Npw to 1e19cm-3 or more. In the present invention, when Vpt is lower than the desired value, Npw can be increased to increase Vpt to the desired value.

[0052] (Issue 4) The quality of the gate insulating film in SiC-MOSFETs is poorer than that of Si-MOSFETs, resulting in lower reliability. MOS structures have a point where the gate insulating film intersects with the PN junction, which consists of the source region and body region. A high electric field always exists at the PN junction due to the built-in potential (Vbi). If the impurity concentrations of the P and N layers are 1e20 cm-3 and the SiC Vbi is 2.9 V, then analytically, in the case of an abrupt junction, the electric field at the PN junction is 3.7 MV / cm, which is a very high electric field.

[0053] This high electric field value is the electric field at the PN junction of the parallel plates. At the interface between the PN junction and the gate insulating film, part of this electric field seeps into the inside of the gate insulating film. It is predicted that a few tenths of the electric field of 3.7 MV / cm will enter the gate insulating film, so an electric field of about 1 MV / cm to 2 MV / cm will be applied to the gate insulating film.

[0054] This electric field is always present even when no voltage is applied to the drain or gate. In other words, a high electric field has been applied to the gate insulating film since the MOSFET was manufactured in the wafer process. Although an electric field of 1 MV / cm to 2 MV / cm is lower than the breakdown strength of the gate insulating film, it is thought to increase the failure rate probabilistically. In other words, it is thought to reduce reliability. There is a problem in that a high electric field is always present in the gate insulating film at the intersection region of the PN junction and gate insulating film created in the MOS structure.

[0055] (Solution to Problem 4) First, the conventional problem will be explained using FIGS. 6(a) and 6(b). FIG. 6(a) shows an enlarged cross-sectional view of a source region 41, a body region 42, a gate insulating film 43, an intersection 45, and a gate electrode 44. For example, the source region 41 is an N-type highly doped layer, and the body region 42 is a P-type highly doped layer. The source region 41 and the body region 42 form a PN junction, and a high electric field is generated at this PN junction by Vbi. The intersection of the PN junction and the gate insulating film is shown as intersection 45 in FIG. 6(a).

[0056] 6(b) shows the depletion layer and electric field. The dashed line indicates the boundary between the depletion layer and the non-depletion layer, and the region from the dashed line of the source region 41 to the dashed line of the body region 42 is the depletion layer region. Since the space charge in the depletion layer of the source region 41 is positive and the space charge in the depletion layer of the body region 42 is negative, the electric field lines are directed from the source region 41 to the body region 42. The highest electric field is generated at the PN junction.

[0057] Near the intersection 45, part of the high electric field of this PN junction seeps into the inside of the gate insulating film 43. This state is shown by electric field lines 46 in Figure 6(b). It can be seen that a high electric field is generated within the gate insulating film near the intersection 45. Figure 6(c) shows a structure according to the present invention, to which a channel epitaxial film 47 is applied. A high electric field of the same value as that shown in Figure 6(b) for the conventional structure is generated at the PN junction, but the electric field lines 46 that create the seeping electric field are generated within the channel epitaxial film 47 and do not reach the inside of the gate insulating film 43, so no high electric field is generated.

[0058] The maximum impurity concentration of SiC is generally said to be 1e20 cm-3. When the impurity concentrations of both the P-type layer and the N-type layer are set to 1e20 cm-3 and an abrupt junction impurity profile is used, the length of the depletion layer of the PN junction to which Vbi is applied is approximately 8 nm. If a channel epitaxial layer with a thickness equal to or greater than the length of this depletion layer is used, the electric field reaching the gate insulating film from the PN junction can be significantly reduced. Even if the thickness is less than 8 nm, the electric field reaching the gate insulating film can be reduced to some extent.

[0059] Since an actual PN junction is not an abrupt junction and the impurity concentration changes gradually, the depletion layer length is longer than 8 nm. Therefore, it is necessary to set Tce to a thickness equal to or greater than the depletion layer length determined by the actual impurity concentration. As described above, the electric field created by the PN junction between the body region and the source region was explained using Figure 6. However, since the intersection of the PN junction and the gate insulating film also exists at the PN junction between the body region and the JFET region, it is desirable to set Tce to a thickness equal to or greater than the longer of the depletion layer lengths created by the former and the latter. From the above, the problem of a high electric field occurring in the gate insulating film near the intersection of the PN junction and the gate insulating film can be solved. The present invention significantly reduces the amount of electric field lines that enter the gate insulating film due to the high electric field generated by the built-in potential of the PN junction present in a MOS structure, thereby improving the reliability of the gate oxide film.

[0060] Example 4 When no voltage is applied to the SiC-MOSFET, for example, even when Vgs=0 V and Vds=0 V, a high electric field is always generated in the PN junction inherent in the MOS structure due to Vbi.

[0061] By applying a channel epitaxial layer with a thickness equal to or greater than the length of the depletion layer created by the PN junction, the amount of high electric field generated by the PN junction reaching the gate insulating film can be significantly reduced, and the electric field within the gate insulating film can be significantly reduced or eliminated. This improves the reliability of the gate insulating film. Tce must be 8 nm or greater. Since the depletion layer length of the PN junction depends on the impurity concentration distribution, it is desirable to determine the actual depletion layer length and set Tce to a value equal to or greater than the depletion layer length.

[0062] (Other Measures) There are other ways to solve the problem of high Rch besides the methods mentioned above. One such method is a two-layer channel epitaxial structure, as shown in FIG. 7. FIG. 7 shows a one-dimensional MOS structure consisting of a body region 52, channel epitaxial regions 56a and 56b, a gate insulating film 53, and a gate electrode 54. In the two-layer channel epitaxial region, the layer on the body region 52 side is CEn 56a, and the layer on the gate oxide film side is CEp 56b. CEn 56a is N-type doped, has an impurity concentration of Ncen, a thickness of Tcen, and a fixed charge when depleted of Qcen. CEp 56b is P-type doped, has an impurity concentration of Ncep, a thickness of Tcep, and a fixed charge when depleted of Qcep. Qcen = q * Ncen * Tcen, Qcep = q * Ncep * Tcep, and q is the elementary charge.

[0063] Qce is Qcen-Qcep, and Qcen is set to be larger than Qcep. In other words, Qce is a positive value. As with the case where the channel epitaxial layer has a single layer structure, Vth is lowered by Qce, and the voltage drop is roughly proportional to Qce, so a desired Vth can be obtained by adjusting Qce.

[0064] As mentioned above, inserting a channel epitaxial layer between SiC and the gate insulating film can increase Npw. Because Npw is high, the energy band slope at the interface between the gate insulating film and the body region becomes larger. When the energy band slope becomes larger, electrons in the channel become more susceptible to scattering, reducing the electron mobility and saturation velocity. This increases Rch and decreases Idsat. If the channel epitaxial layer has a two-layer structure consisting of an N-type layer and a P-type layer, the energy band slope can be made gentler.

[0065] This is shown in Figure 8. The two curves in the figure represent the conduction bands. The solid line represents the case where the two-layer channel epitaxial structure of the present invention is applied. The dashed line represents the case where the channel epitaxial structure is a single layer. Compared to the dashed line, the solid line has a steeper slope in the CEn region. This is because Ncen in the two-layer structure is larger than Nce in the single-layer structure. Furthermore, the slope of the solid line is gentler than the dashed line in the CEp region. This is because CEp in the two-layer structure is P-type, while CEp in the single-layer structure is N-type. Since the fixed charges in the single-layer and two-layer channel epitaxial structures are the same, the conduction bands at the interface between the two structures are roughly the same. The slope of the conduction band at the interface of the two-layer structure of the present invention is gentler than that of the single-layer structure. In other words, the two-layer channel epitaxial structure of the present invention reduces electron scattering, improves electron mobility, and reduces Rch. It also improves Idsat.

[0066] (Example 5) The channel epitaxial layer 25 has a two-layer structure. An N-type channel epitaxial layer (CEn layer) is formed on and in contact with the SiC layer. A second P-type channel epitaxial layer (CEp layer) is formed on the CEn layer. The impurity concentration of the CEn layer is Ncen, the thickness is Tcen, and the fixed charge when depleted is Qcen (= q * Ncen * Tcen). The impurity concentration of the CEp layer is Ncep, the thickness is Tcep, and the fixed charge when depleted is Qcep (= q * Ncep * Tcep). The net fixed charge of the CEn layer and CEp layer combined is Qce (= Qcen - Qcep).

[0067] With Qcen > Qcep, the amount of change in Vth caused by the two-layer channel epitaxial layer is roughly proportional to Qce, and increasing Qce decreases Vth. Ncen is 1e17 cm-3 or more, Tcen is 100 nm or less, Ncep is 1e17 cm-3 or more, and Tcen is 100 nm or less. When the desired Vth is 3 to 5 V, for example, Npw is 1e19 cm-3, Ncen is 1.5e18 cm-3 to 6e18 cm-3, Tcen is 15 nm, Ncep is 1e18 cm-3 to 5e18 cm-3, and Tcep is 15 nm.

[0068] Second Embodiment The first embodiment is an example in which the present invention is applied to a planar SiC-MOSFET. Similarly, an example in which the present invention is applied to a trench SiC-MOSFET is shown in Fig. 5. The following description will be given with reference to Fig. 5.

[0069] The semiconductor substrate 31 is an N-type SiC substrate. N-type SiC is epitaxially grown on the semiconductor substrate 31 as a drift layer 32, which is a first silicon carbide semiconductor layer. This is an N-type drift region for blocking high voltage. For example, in the case of a SiC-MOSFET with a breakdown voltage of 600 V to 1200 V, the impurity in the drift layer is nitrogen, with an impurity concentration of 5e15 cm-3 to 5e16 cm-3 and a thickness of 5 to 12 μm.

[0070] A second conductivity type body region 33 is formed above the drift layer by ion implantation. For example, the impurity in the second conductivity type body region 33 is aluminum, and the impurity concentration (Npw) is 1e18 cm-3 to 1e20 cm-3. A first conductivity type source region 34 is formed in the body region 33. The source region is formed by ion implantation using nitrogen as the impurity at a concentration of 1e19 cm-3 to 1e20 cm-3.

[0071] Although detailed processes are omitted, a general method for creating a trench MOS structure can be applied. To form a trench-type MOS structure, a trench is formed by etching. A channel epitaxial layer 35, which is a second silicon carbide semiconductor layer, is formed on the inner sidewalls and bottom surface of the trench by a deposition process. The impurity is nitrogen, the impurity concentration (Nce) is 1e15 cm-3 to 1e20 cm-3, and the thickness (Tce) is 8 nm to 100 nm. A gate insulating film 36 is formed in contact with the surface of the channel epitaxial layer 35. The gate insulating film 36 is formed by a deposition process.

[0072] A gate electrode 37 is formed in contact with the surface of the gate insulating film 26. The gate electrode 37 may be made of polysilicon or a metal such as aluminum. A source electrode 38 is formed in contact with the surfaces of the source region 34 and the body region 33. A drift electrode 39 is formed on the back surface of the semiconductor substrate 31.

[0073] The sidewall surfaces of the trenches in the source region 34 and body region 33 are in contact with the channel epitaxial layer 35, and this contact surface is the SiC interface of the MOS structure. In a MOSFET, the source region 34 is the source, the drift region 32 is the drain, and the contact surface between the channel epitaxial layer 35 and the gate insulating film 26 in the region where the body region 33 and channel epitaxial layer 35 contact is the SiC interface, and this interface functions as the MOS channel. The channel length is shown as Lch in the figure. The trench must be deep enough into the drift layer so that the MOS channel can function.

[0074] Examples 1 to 5 of the first embodiment, which are examples of the planar SiC-MOSFET described above, can be applied as they are to the second embodiment, which is a trench SiC-MOSFET, and therefore a description thereof will be omitted.

[0075] (Other Embodiments) While the present invention has been described using examples in which it is applied to planar and trench SiC-MOSFETs, the present invention is not limited to these and can be applied to power devices having MOSFET elements, such as lateral LDMOSFETs and bipolar devices such as IGBTs. Furthermore, the present invention can also be applied to power devices made of silicon materials, such as MOSFETs and IGBTs, in addition to SiC materials. The present invention can also be applied to superjunction MOSFETs (SJ-MOSFETs) that can significantly reduce the resistance of the MOSFET's drift layer. In particular, in the case of SiC, SJ-MOSFETs can significantly reduce the drift layer resistance, and therefore the Rch occupancy rate in the on-resistance is large, making the need for Rch reduction greater than in conventional MOSFETs. Therefore, applying the present invention is highly effective.

[0076] According to the present invention, when a SiC-MOSFET is mounted in a power conversion device such as a motor drive for an electric vehicle, it is possible to provide a semiconductor element that can reduce energy loss, downsize components, and reduce the cost of SiC materials.

[0077] 1, 21, 31 Semiconductor substrate (N-type SiC substrate), 2, 22, 32 First conductivity type first silicon carbide semiconductor layer (N-type drift layer), 3, 23, 33 Second conductivity type body region 4, 24, 34 First conductivity type source region, 25, 35 First conductivity type second silicon carbide semiconductor layer, 6, 26, 36 Gate insulating film, 7, 27, 37 Gate electrode, 8, 28, 38 Source electrode, 9, 29, 39 Drain electrode, 10, 30 JFET region, 41 Source region, 42, 52 Body region, 43, 53 Gate insulating film, 44, 54 Gate electrode, 45 Intersection of PN junction and gate insulating film, 46 Electric field lines, 47, 56a, 56b Channel epitaxial, 100 Prior art planar MOSFET, 200 Planar MOSFET of the present invention, 300 Trench MOSFET of the present invention, 400 500 Cross-sectional view and electric field lines of the intersection of a PN junction and a gate oxide film of the prior art and the present invention, 501 MOS structure including a channel epitaxial layer made of two impurity types.

Claims

1. A semiconductor device comprising: a semiconductor element including a metal-insulator-semiconductor field effect transistor; and a potential setting unit that sets a potential of the semiconductor element, wherein the potential setting unit comprises: a gate electrode, a source electrode, and a drain electrode; and the metal-insulator-semiconductor field effect transistor comprises: a semiconductor substrate of a first conductivity type; a first silicon carbide semiconductor layer of the first conductivity type located on a main surface of the semiconductor substrate; a body region of a second conductivity type located in the first silicon carbide semiconductor layer; a source region of the first conductivity type located in the body region; a second silicon carbide semiconductor layer of the first conductivity type formed on the first silicon carbide semiconductor layer and in contact with at least a portion of the body region and the source region; a gate insulating film on the second silicon carbide semiconductor layer; the gate electrode on the gate insulating film; the source electrode in contact with the source region and the body region; and the drain electrode provided on a back surface of the semiconductor substrate. The semiconductor device is characterized in that the impurity concentration Npw of the body region is set to 1e18 cm −3 or more.

2. A semiconductor device according to claim 1, wherein the impurity concentration Npw of the body region is adjusted to control the channel length Lch to a predetermined value.

3. A semiconductor device according to claim 1, wherein when the impurity concentration of the second silicon carbide semiconductor layer is Nce and the thickness of the second silicon carbide semiconductor layer is Tce, the Nce and / or Tce is adjusted to set the gate threshold voltage Vth to a predetermined value.

4. A semiconductor device according to claim 1, wherein Idsat represents a saturation current when Vds represents the voltage of the drain electrode and Id represents the current flowing through the drain electrode, Nce represents the impurity concentration of the second silicon carbide semiconductor layer, and Tce represents the thickness of the second silicon carbide semiconductor layer, and when Idsat is greater than a predetermined value, Npw is increased and / or Tce is shortened and / or Nce is increased and / or channel length Lch is lengthened to reduce Idsat to the predetermined value, and when Idsat is smaller than the predetermined value, Npw is decreased and / or Tce is lengthened and / or Nce is decreased and / or Lch is shortened to increase Idsat to the predetermined value.

5. A semiconductor device according to claim 1, wherein when the channel length Lch is shortened, Lch at which the punch-through voltage Vpt begins to become smaller than a predetermined value is defined as Lchminpt, and when the channel length Lch is shortened, Lch at which the gate threshold voltage Vth begins to drop sharply is defined as Lchminsc, and when Lchminpt is longer than Lchminsc, the impurity concentration Npw of the body region is increased to control Lchminpt to a value equal to or less than Lchminsc.

6. A semiconductor device according to claim 1, wherein when the thickness of said second silicon carbide semiconductor layer is Tce, said Tce is 8 nm or more.

7. A semiconductor device according to claim 1, wherein when the impurity concentration of said second silicon carbide semiconductor layer is Nce, said Nce is 1e17 cm-3 or more.

8. A semiconductor device according to claim 1, wherein when the thickness of said second silicon carbide semiconductor layer is Tce, said Tce is 100 nm or less.

9. A semiconductor device according to claim 6, wherein when the voltage Vgs of the gate electrode is set to 0 V and the voltage Vds of the drain electrode is set to 0 V, the length of the depletion layer of the PN junction between the body region and the source region is set to dbs, the length of the depletion layer of the PN junction between the body region and the first silicon carbide semiconductor layer is set to dbj, and the larger of dbs and dbj is set to dm, the thickness Tce of the second silicon carbide semiconductor layer is equal to or greater than dm.

10. A semiconductor device according to claim 1, wherein a third silicon carbide semiconductor layer of a second conductivity type is formed between said second silicon carbide semiconductor layer of a first conductivity type and said gate insulating film, wherein said second silicon carbide semiconductor layer of said first conductivity type has an impurity concentration Ncen, a thickness Tcen and a fixed charge when depleted Qcen, said Qcen being q*Ncen*Tcen, and wherein said third silicon carbide semiconductor layer of said second conductivity type has an impurity concentration Ncep, a thickness Tcep and a fixed charge when depleted Qcep, said Qcep being q*Ncep*Tcep, wherein Tce is the sum of said Tcen and said Tcep and Qce is the difference between said Qcen and said Qcep, and wherein said Qcen is equal to or greater than said Qcep, A semiconductor device characterized in that, by adjusting Qce, Tce, Qcen, Ncen, Tcen, Qcep, Ncep and / or Tcep, the gate threshold voltage Vth, punch-through voltage Vpt, Lchminsc, which is the Lch at which the gate threshold voltage Vth begins to drop sharply when the channel length Lch is shortened, Lchminpt, which is the Lch at which the punch-through voltage Vpt begins to become smaller than a predetermined value when the channel length Lch is shortened, and / or the saturation current Idsat, where Id is the current flowing to the drain electrode when the voltage Vds of the drain electrode is increased.

11. A semiconductor device according to claim 1, wherein the impurity concentration Npw of the body region is set to 1e19 cm-3 or more.

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