Determining parasitic elements of an interconnect of an electronic circuit layout

Abstract

The invention relates to a method for determining parasitic elements of an interconnect of an electronic circuit layout. To facilitate determining the parasitic elements, the method includes determining an interconnect parasitic model from a plurality of interconnect parasitic models of the interconnect based on a comparison between at least one performance indicator associated with each one of the interconnect parasitic models, and determining the parasitic elements of the interconnect based on the determined interconnect parasitic model.

Description

202403132 1 DETERMINING PARASITIC ELEMENTS OF AN INTERCONNECT OF AN ELECTRONIC CIRCUIT LAYOUT TECHNICAL FIELD

[0001] The present disclosure is directed, in general, to electronic design automation (EDA) and, more specifically, to the determination of parasitic elements of an interconnect of an electronic circuit layout. Such electronic design automation systems and parasitic elements determination systems are collectively referred to herein as product systems. BACKGROUND ART

[0002] The development of electronic devices with electronic circuits typically involves many steps known as a design flow. This design flow typically starts with a specification for a new electronic device to be implemented with an electronic circuit, such as a printed circuit board (PCB) or an integrated circuit (IC). The specification of the electronic device can be transformed into an electronic device design, such as a netlist, for example, by a schematic capture tool or by synthesizing a logical design, sometimes referred to as a register transfer level (RTL) description of the electronic device. The netlist may be specified in an Electronic Design Interchange Format (EDIF) or the like, which can describe nets or connectivity between various components or parts in the electronic device design.

[0003] The design flow may continue by verifying functionality of the electronic device design, for example, by simulating, emulating, or prototyping the electronic device design and verifying that the results of the simulation or emulation correspond with an expected output from the electronic device design. The functionality also can be verified by formally verifying with one or more solvers or statically checking the electronic device design for various attributes that may be problematic during operation of the electronic device built utilizing the electronic device design.

[0004] Once the electronic device design has been functionally verified, the design flow may utilize the logical design to generate a layout design for the electronic device. This procedure can be implemented in different ways, but typically, through the use of a layout tool, which can place and interconnect various components or parts into a representation of an electronic circuit. For example, the layout tool implemented in a computing system can present a graphical view of the electronic circuit and allow a designer to utilize the layout tool to place parts from a library onto the electronic circuit in the graphical view.202403132 2

[0005] The layout of the electronic circuit may then physically be verified, e.g. to address functional yield challenges in IC designs. Such a physical verification helps to ensure accurate circuit behavior with precise device parameters, while parasitic extraction tools help to provide accurate and high-performance extraction required for all design styles. In some respects, the present patent disclosure primarily focusses on the physical verification of an electronic circuit layout.

[0006] Currently, there exist product systems and solutions which support determining parasitic elements of an interconnect of an electronic circuit layout. Such product systems may benefit from improvements. SUMMARY OF INVENTION

[0007] Variously disclosed embodiments include methods and computer systems that may be used to facilitate determining parasitic elements of an interconnect of an electronic circuit layout.

[0008] According to a first aspect of the invention, a computer-implemented method for determining parasitic elements of an interconnect of an electronic circuit layout may include: determining an interconnect parasitic model from a plurality of interconnect parasitic models of the interconnect based on a comparison between at least one performance indicator associated with each one of the interconnect parasitic models; and determining the parasitic elements of the interconnect based on the determined interconnect parasitic model.

[0009] According to a second aspect of the invention, a computer system may be arranged and configured to execute the steps of this computer-implemented method according to the first aspect.

[0010] According to a third aspect, a computer program product may include computer program code that, when executed by the computer system according to the second aspect, causes the computer system to carry out the method according to the first aspect.

[0011] According to a fourth aspect, a computer-readable medium may include the computer program product according to the third aspect. By way of example, the described computer-readable medium may be non-transitory and may further be a software component on a storage device.

[0012] The foregoing has outlined rather broadly the technical features of the present disclosure so that those skilled in the art may better understand the detailed description that follows. Additional features and advantages of the disclosure will be described hereinafter202403132 3 that form the subject of the claims. Those skilled in the art will appreciate that they may readily use the conception and the specific embodiments disclosed as a basis for determining parasitic elements of an interconnect of an electronic circuit layout or for carrying out the same purposes of the present disclosure. Those skilled in the art will also realize that such equivalent constructions do not depart from the spirit and scope of the disclosure in its broadest form.

[0013] Also, before undertaking the detailed description below, it should be understood that various definitions for certain words and phrases are provided throughout this patent document and those of ordinary skill in the art will understand that such definitions apply in many, if not most, instances to prior as well as future uses of such defined words and phrases. While some terms may include a wide variety of embodiments, the appended claims may expressly limit these terms to specific embodiments.

[0014] Embodiments will be described below in greater detail. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figs. 1-2 depict a functional block diagram of a first and second example system that facilitate determining parasitic elements of an interconnect of an electronic circuit layout in a product system.

[0016] Figs. 3-7 depict different aspects of various example methodologies that facilitate determining parasitic elements of an interconnect of an electronic circuit layout in a product system, respectively.

[0017] Figs. 8-9 depict a functional block diagram of a third and fourth example system that facilitates determining parasitic elements of an interconnect of an electronic circuit layout in a product system, respectively.

[0018] Figs. 10-11 depict a flow diagram of an example methodology that facilitates determining parasitic elements of an interconnect of an electronic circuit layout in a product system, respectively.

[0019] Fig. 12 depicts a block diagram of a data processing system in which an embodiment can be implemented. DETAILED DESCRIPTION

[0020] Various technologies that pertain to systems and methods for determining parasitic elements of an interconnect of an electronic circuit layout in a product system will now be202403132 4 described with reference to the drawings, where like reference numerals represent like elements throughout. The drawings discussed below, and the various embodiments used to describe the principles of the present disclosure in this patent document are by way of illustration only and should not be construed in any way to limit the scope of the disclosure. Those skilled in the art will understand that the principles of the present disclosure may be implemented in any suitably arranged apparatus. It is to be understood that functionality that is described as being carried out by certain system elements may be performed by multiple elements. Similarly, for instance, an element may be configured to perform functionality that is described as being carried out by multiple elements. The numerous innovative teachings of the present patent document will be described with reference to exemplary non-limiting embodiments.

[0021] With reference to Fig. 1, a functional block diagram of a first example computer system or data processing system 100 is depicted that facilitates determining parasitic elements 124 of an interconnect 122 of an electronic circuit layout 120. The processing system 100 may include an electronic circuit verification (ECV) system 118 which may, in some examples, may include at least one processor 102 that is configured to execute at least one application software component 106 from a memory 104 accessed by the processor 102. The application software component 106 may be configured (i.e., programmed) to cause the processor 102 to carry out various acts and functions described herein. For example, the described application software component 106 may include and / or correspond to one or more components of an application for determining parasitic elements 124 of an interconnect 122 of an electronic circuit layout 120, wherein the application software component 106 may, e.g., be configured to generate and store product data in a data store 108 such as a database.

[0022] By way of example, the ECV system 118 may be cloud-based, internet-based and / or be operated by a provider providing support determining parasitic elements 124 of an inter- connect 122 of an electronic circuit layout 120. In some examples, the user may be located close to the ECV system 118 or remote to the ECV system 118, e.g., anywhere else, e.g., using a mobile device for connecting to the ECV system 118, e.g., via the internet, wherein the mobile device may include an input device 110 and a display device 112. In some examples, the ECV system 118 may be installed and run on a user’s device, such as a computer, laptop, pad, on-premises computing facility, or the like.

[0023] It should be appreciated that determining parasitic elements 124 of an interconnect 122 of an electronic circuit layout 120 may be a challenging and time-consuming process202403132 5 which may require highly skilled engineers with many years of training. For example, advanced knowledge in electronics, physics and other scientific domains may be required, or selections of many options need to be made consciously, each involving many manual steps, which is a long and not efficient process. Further, according to other approaches, determining parasitic elements 124 of the interconnects 122 of more complex electronic circuit layouts 120 may take several days or weeks even on high-performance computers, may lead to wrong determined parasitic elements 124, or may simply not be feasible.

[0024] To enable the enhanced determination of parasitic elements 124 of an interconnect 122 of an electronic circuit layout 120, the described product system or processing system 100 may include at least one input device 110 and at least one display device 112 (such as a display screen). The described processor 102 may be configured to generate a graphical user interface (GUI) 114 through the display device 112. Such a GUI 114 may include GUI elements such as buttons, links, search boxes, lists, text boxes, images, scroll bars usable by a user to provide inputs through the input device 110 that cause determining parasitic elements 124 of an interconnect 122 of an electronic circuit layout 120. By way of example, the GUI 114 may include an ECV user interface (UI) 116 provided to a user.

[0025] In an example embodiment, for determining parasitic elements 124 of an interconnect 122 of an electronic circuit layout 120, the application software component 106 and / or the processor 102 may be configured to determine an interconnect parasitic model 128 from a plurality of interconnect parasitic models 128 of the interconnect 122 based on a comparison between at least one performance indicator 130 associated with each one of the interconnect parasitic models 128.

[0026] Herein, the electronic circuit layout 120 may, e.g., be understood as the above- mentioned layout design for an electronic device obtained after the functional verification step and the completion of the layout step of the above-mentioned design flow. The electronic circuit 152 corresponding to the electronic circuit layout 120 may, by way of example, include an integrated circuit, also known as a microchip, chip or IC, i.e., a small electronic device made up of multiple interconnected electronic components such as transistors, resistors, and capacitors. These components may be etched onto a small piece of semiconductor material, usually silicon. Integrated circuits are used in a wide range of electronic devices, including computers, smartphones, and televisions, to perform various functions such as processing and storing information. They have greatly impacted the field of electronics by enabling device miniaturization and enhanced functionality. In some examples,202403132 6 electronic circuits 152 corresponding to the electronic circuit layout 120 may include a printed circuit board (PCB), also called printed wiring board (PWB), i.e., a medium used to connect or "wire" the above-mentioned components to one another in an electric circuit. In some examples, the electronic circuit 152 and the corresponding electronic circuit layout 120 may include millions or even billions of the mentioned components, e.g., transistors.

[0027] By way of example, the respective interconnect 122 may be understood as a route or metallization layer(s) through which individual components, such as transistors, capacitors, resistors, etc., may electrically be interconnected with wiring on wafer. In some examples, the electronic circuit layout 120 with the plurality of interconnects 122 may include geometric, physical, or material properties of the respective interconnect 122.

[0028] Further, in the context of electrical networks, a parasitic element 124 may, e.g., be understood as a circuit element, such as a resistance R, an inductance L or a capacitance C, that is possessed by an electrical component or an interconnect 122 but which it is not desirable for it to have for its intended purpose. For instance, a resistor is designed to possess resistance, but will also possess unwanted parasitic capacitance. Parasitic elements 124 may, by way of example, be modelled as lumped components in equivalent circuits. Herein, a lumped-element model (also called lumped-parameter model or lumped-component model) is a simplified representation of a physical system or circuit that assumes all components are concentrated at a single point and their behavior can be described by idealized mathematical models. The lumped-element model simplifies the system or circuit behavior description into a topology.

[0029] An interconnect parasitic model 128 may, e.g., be a simplified representation or a model of the parasitic elements 124 of the respective interconnect 122. The interconnect parasitic model 128 of the respective interconnect 122 may, in some examples, be very simple and only take one or more resistances R and one or more capacitances C into account. More complex interconnect parasitic models 128 of the respective interconnect 122 may, e.g., take one or more resistances R, one or more inductances L, and one or more capacitances C into account. Further, the interconnect parasitic model 128 of the respective interconnect 122 may, e.g., be a so-called full-wave model which in many examples, may provide a precise representation or model of the parasitic elements 124 of the respective interconnect 122. For full-wave models, the respective interconnect 122 may be modeled by finite element methods (FEM), wherein the material and the three-dimensional geometry details of the respective interconnect 122 may need to be defined. Herein, the plurality of interconnect parasitic202403132 7 models 128 may, e.g., include at least two interconnect parasitic models 128, e.g., two or three of the above-mentioned models taking resistances R, capacitances C, and optionally inductances L into account or the full-wave model. Further, other suitable interconnect parasitic models 128 may also be used.

[0030] The respective performance indicator 130 associated with each one of the interconnect parasitic models 128 may, e.g., indicate a respective performance 136 of the electronic circuit layout 120 when the respective interconnect 122 is modelled using the respective interconnect parasitic model 128. For example, if a given interconnect 122 is modelled with two different interconnect parasitic models 128-1 & 128-2, then the two corresponding performance indicators 130-1 & 130-2 may indicate the respective performances 136-1 & 136-2 of the electronic circuit layout 120 using the two different interconnect parasitic models 128-1 & 128-2 for this interconnect 122. In some examples, the respective performance 136 of the respective interconnect 122 may be considered.

[0031] In some examples, the performance 136 or performance indicator 130 may include a delay, a gain, a noise, an IR-drop and / or a skew relating to the respective interconnect 122 or the electronic circuit layout 120. Herein, the delay and the noise may, e.g., be a signal delay and a signal noise, respectively. These quantities are explained in more detail below. For example, the noise relating to the electronic circuit layout 120 may be determined based on two or three different interconnect parasitic models 128. Accordingly, two or three different noise values may be determined and be compared as explained below.

[0032] Herein, one interconnect parasitic model 128 of the plurality of interconnect parasitic models 128 may be selected using a comparison of the respective performance indicators 130. In some examples, the interconnect parasitic model 128 with the best agreement of the respective (“modelled”) performance indicator 130 with the corresponding real performance indicator 130 may be selected. Herein, the real performance indicator 130 may relate to a (as far as possible) exact determination of the performance indicator 130 of the respective interconnect 122 or the electronic circuit layout 120, e.g., using a field solver which may calculate electromagnetic parameters by directly solving Maxwell's equations. In further examples, one of the least complex interconnect parasitic models 128 with an acceptable agreement of the respective (“modelled”) performance indicator 130 with the corresponding performance indicator 130 of the most complex interconnect parasitic model 128 may be selected. In these examples, if the less complex interconnect parasitic models 128 do not offer an acceptable agreement of the respective (“modelled”) performance indicator 130 with the202403132 8 corresponding performance indicator 130 of the most complex interconnect parasitic model 128, the most complex interconnect parasitic model 128 may be selected.

[0033] In some examples, the interconnect parasitic model 128 may be selected which offers an acceptable agreement of the respective (“modelled”) performance indicator 130 with the corresponding performance indicator 130 of the most complex interconnect parasitic model 128 or with the corresponding real performance indicator 130 while involving acceptable computational resources, e.g., for the determination of the parasitic elements 124 of the interconnect 122. In these further examples, a reasonable trade-off between an accuracy and computational efforts relating to the interconnect parasitic model 128, respectively, may be an advantageous criterion for the determination of the best-suited interconnect parasitic model 128.

[0034] In some examples, the application software component 106 and / or the processor 102 may further be configured to determine the parasitic elements 124 of the interconnect 122 based on the determined parasitic model 128.

[0035] The determined parasitic model 128 may then be used to, e.g., directly or indirectly, determine the parasitic elements 124 of the interconnect 122. By way of example, the parasitic elements 124 of the interconnect 122 may include one or more resistances R, one or more inductances L, and one or more capacitances C, wherein the respective values of these parasitic elements 124 may be determined based on the determined parasitic model 128. Examples of the determination of the parasitic elements 124 of the interconnect 122 based on the determined parasitic model 128 are provided below.

[0036] In some examples, the application software component 106 and / or the processor 102 may further be configured to: provide the electronic circuit layout 120 including a plurality of interconnects 122; determine at least one characteristic 126 of the respective interconnect 122; assign at least a first interconnect parasitic model 128-1 and a second interconnect parasitic model 128-2 to the respective interconnect 122; determine a respective performance indicator 130-1, 130-2 at least of the first interconnect parasitic model 128-1 and the second interconnect parasitic model 128-2 of the respective interconnect 122 using the respective characteristic 126 of the respective interconnect 122; select one of the at least first interconnect parasitic model 128-1 and second interconnect parasitic model 128-2 for the respective interconnect 122 using the respective performance indicator 130-1, 130-2; and determine the parasitic elements 124 of the respective interconnect 122 using an extractor tool 132 corresponding to the respective, selected interconnect parasitic model 128.202403132 9

[0037] In some examples, providing the electronic circuit layout 120 including the plurality of interconnects 122 may involve that the electronic circuit layout 120 and the plurality of interconnects 122 may be determined by a user or engineer. The electronic circuit layout 120 and the plurality of interconnects 122 may be provided and stored in the data store 108 of the ECV system 118, e.g. by the user using the ECV UI 116 and / or the input device 110. In some examples, the electronic circuit layout 120 and the plurality of interconnects 122 may be received, e.g., via an application programming interface (API) from another data source 108’. Similar approaches may also be used for the provision of the other input information which is explained in more detail below.

[0038] For the determination of the at least one characteristic 126 of the respective interconnect 122, the electronic circuit layout 120 including the plurality of interconnects 122 may be used to extract the respective characteristic 126 of the respective interconnect 122 thereof. The respective characteristic 126 of the respective interconnect 122 may, e.g., include geometric, physical, or material properties of the respective interconnect 122. The geometric properties of the respective interconnect 122 may include the geometric shape of the electric route, e.g., including the length l, width w, and thickness of the respective interconnect 122 and, if the respective interconnect 122 is composed of two or more interconnect parts, the single parts of the respective interconnect 122 making up the respective interconnect 122. The physical properties of the respective interconnect 122 may, e.g., include the electric resistance R or the electric inductance L of the respective interconnect 122. The material properties of the respective interconnect 122 may include the electric, magnetic, or thermal conductivity of the material of which the respective interconnect 122 is made.

[0039] By way of example, the at least one characteristic 126 of the respective interconnect 122 includes enough information on the respective interconnect 122 so that an interconnect parasitic model 128 may be determined which may characterize the parasitic elements 124 of the respective interconnect 122 reasonably well which is explained in more detail below. In some examples, the respective characteristic 126 may be provided and stored in the data store 108 beforehand.

[0040] By way of example, the application software component 106 and / or the processor 102 may further be configured to assign at least a first interconnect parasitic model 128-1 and a second interconnect parasitic model 128-2 to the respective interconnect 122.

[0041] As mentioned above, the respective interconnect parasitic model 128 may, e.g., be a202403132 10 simplified representation or a model of the parasitic elements 124 of the respective inter- connect 122. At least two different interconnect parasitic models 128-1 and 128-2 are assigned to the respective interconnect 122, wherein these at least two interconnect parasitic models 128-1 and 128-2 may have advantages and disadvantages, such as different levels of precision of modeling the real behavior of the respective interconnect 122, and simplicity or complexity of the respective interconnect parasitic model 128 requiring more or less computational resources for the subsequent determination of the parasitic elements 124 of the respective interconnect 122.

[0042] Further, as already mentioned above, the at least first interconnect parasitic model 128-1 and second interconnect parasitic model 128-2 may, e.g., include two or three of the above-mentioned models taking resistances R, capacitances C, and optionally inductances L into account or the full-wave model. Further, other suitable interconnect parasitic models 128 may also be used.

[0043] In further examples, the application software component 106 and / or the processor 102 may further be configured to determine a respective performance indicator 130-1, 130-2 at least of the first interconnect parasitic model 128-1 and the second interconnect parasitic model 128-2 of the respective interconnect 122 using the respective characteristic 126 of the respective interconnect 122.

[0044] For a given interconnect 122, the determined characteristic 126 may, e.g., be used as input to the respective interconnect parasitic model 128-1, 128-2 so that two or more more or less accurate models of the interconnect 122 may be obtained. The different interconnect parasitic models 128-1, 128-2 of the given interconnect 122 may be used as input for a calculation of the respective performance 136-1, 136-2 or the respective performance indicator 130-1, 130-2, which may, e.g., include a delay a gain, a noise, an IR-drop and / or a skew relating to the given interconnect 122 or the electronic circuit layout 120, as already mentioned above.

[0045] In some examples, the application software component 106 and / or the processor 102 may further be configured to select one of the at least first interconnect parasitic model 128-1 and second interconnect parasitic model 128-2 for the respective interconnect 122 using the respective performance indicator 130-1, 130-2.

[0046] The performance indicators 130-1, 130-2 of the given interconnect 122 may, e.g., be compared to each other or to the corresponding real performance indicator 130 to select one of the used interconnect parasitic models 128-1, 128-2. As already mentioned above, one of202403132 11 the least complex interconnect parasitic models 128 with an acceptable agreement of the respective (“modelled”) performance indicator 130 with the corresponding performance indicator 130 of the most complex interconnect parasitic model 128 may be selected, else, i.e., if there is no acceptable agreement, the most complex interconnect parasitic model 128 may be selected. Further, the interconnect parasitic model 128 with the best agreement of the respective (“modelled”) performance indicator 130 with the corresponding real performance indicator 130 may be selected, wherein the real performance indicator 130 may relate to a (as far as possible) exact determination of the performance indicator 130 of the respective interconnect 122 or the electronic circuit layout 120.

[0047] To select one of the interconnect parasitic models 128-1, 128-2, e.g., the above- mentioned reasonable trade-off between an accuracy and computational efforts relating to the interconnect parasitic model 128, respectively, may be used.

[0048] By way of example, the application software component 106 and / or the processor 102 may further be configured to determine the parasitic elements 124 of the respective interconnect 122 using a parasitic extraction tool 132 corresponding to the respective, selected interconnect parasitic model 128.

[0049] While in early integrated circuits the impact of the wiring was negligible, and wires were not considered as electrical elements of the circuit, below the 0.5-micrometre technology node resistance and capacitance of the interconnects 122 started making a significant impact on circuit performance 136. With shrinking process technologies inductance effects of interconnects 122 became important as well.

[0050] Because of this, parasitic extraction tools 132 have been developed and are commercially available from various vendors. For example, the parasitic extraction tools 132 include field solvers and approximate solutions. Field solvers may provide physically accurate solutions through calculating electromagnetic parameters by directly solving Maxwell's equations. Due to high calculation burden, however, field solvers are applicable only to very small designs or to parts of the designs. Approximate solutions with pattern matching techniques may, in some examples, be the only feasible approach to extract parasitics for complete modern integrated circuit designs.

[0051] According to the suggested approach, for a given interconnect 122, a parasitic extraction tool 132 may be used to determine the parasitic elements 124 of the given interconnect 122, wherein this parasitic extraction tool 132 corresponds to the selected interconnect parasitic model 128 for this interconnect 122. Hence, e.g., if the selected202403132 12 interconnect parasitic model 128 is simple and only takes one or more resistances R and one or more capacitances C into account, then a correspondingly simple, approximate solution parasitic extraction tool 132 may be used taking only one or more resistances R and one or more capacitances C into account. Further, e.g., if the selected interconnect parasitic model 128 is more complex and takes one or more resistances R, one or more inductances L, and one or more capacitances C into account, then a correspondingly more complex, approximate solution parasitic extraction tool 132 may be used taking one or more resistances R, one or more inductances L, and one or more capacitances C into account. Also, if the selected interconnect parasitic model 128 is a full-wave model, then a correspondingly sophisticated, approximate solution, full-wave or even field solver parasitic extraction tool 132 may be used taking correspondingly sophisticated effects into account.

[0052] Hence, in some examples, the suggested approach allows to determine the parasitic elements 124 of the respective interconnect 122 with sufficient accuracy while reducing involved computational efforts as far as possible by using a parasitic extraction tool 132 corresponding to the respective, selected interconnect parasitic model 128. Therefore, the suggested approach may, e.g., contribute to ensure accurate circuit behavior with sufficiently precise device parameters, while cleverly using suitably precise and efficient parasitic extraction tools to provide accurate and high-performance extraction required for all design styles.

[0053] By way of example, the application software component 106 and / or the processor 102 may further be configured to providing an application scenario 134 of the electronic circuit layout 120; and to determine the respective performance indicator 136 of the respective interconnect 122 further using the application scenario 136, wherein the application scenario 134 includes a digital application scenario 134 and an analog application scenario 134, and wherein the respective performance 136 includes a delay, a gain, a noise, an IR-drop and / or a skew for the digital application scenario 134 and / or the analog application scenario 134.

[0054] Herein, in some examples, the digital application scenario 134 and an analog application scenario 134 may be understood such that the electronic circuit 152 corresponding to the electronic circuit layout 120 may be used to generate all process digital or an analog signal. An analog signal is, e.g., any continuous-time signal representing some other quantity, i.e., analogous to another quantity. For example, in an analog audio signal, the instantaneous signal voltage varies continuously with the pressure of the sound waves. A202403132 13 digital signal may, e.g., be a discrete time, quantized amplitude signal. In other words, it may be a sampled signal consisting of samples that take on values from a discrete set (a countable set that can be mapped one-to-one to a subset of integers). If that discrete set is finite, the discrete values may be represented with digital words of a finite width. Most commonly, these discrete values may be represented as fixed-point words (either proportional to the waveform values or companded) or floating-point words.

[0055] A delay may, e.g., include a group delay and a phase delay which are two related ways of describing how a signal's frequency components may be delayed in time when passing through a linear time-invariant system, such as a microphone, coaxial cable, amplifier, loudspeaker, telecommunications system, ethernet cable, digital filter, or analog filter. Phase delay describes the time shift of a sinusoidal component (a sine wave in steady state). Group delay describes the time shift of the envelope of a wave packet, a "pack" or "group" of oscillations centered around one frequency that travel together, formed for instance by multiplying (amplitude modulation) a sine wave by an envelope (such as a tapering function). These delays are usually frequency dependent, which means that different frequency components experience different delays. As a result, the signal's waveform experiences distortion as it passes through the system. This distortion can cause problems such as poor fidelity in analog video and analog audio, or a high bit-error rate in a digital bit stream.

[0056] Gain is a measure of the ability of a two-port circuit (often an amplifier) to increase the power or amplitude of a signal from the input to the output port by adding energy converted from some power supply to the signal. A gain may be usually defined as the mean ratio of the signal amplitude or power at the output port to the amplitude or power at the input port and is often expressed using the logarithmic decibel (dB) units ("dB gain"). A gain greater than one (greater than zero dB), that is, amplification, is the defining property of an active component or circuit, while a passive circuit will have a gain of less than one.

[0057] Noise may, e.g., be understood as an unwanted disturbance in an electrical signal.

[0058] An IR-drop relates to a voltage drop across the network or electronic circuit layout 120 which is due to the resistance of the interconnects 122 constituting the network. For example, excessive voltage drops in the power grid may reduce switching speeds and noise margins of circuits and inject noise which might lead to functional failures.

[0059] A skew, esp. a clock skew (sometimes called timing skew), may, e.g., be understood as a phenomenon in synchronous digital circuit systems in which the same sourced clock202403132 14 signal arrives at different components at different times due to gate or, in more advanced semiconductor technology, wire signal propagation delay. The instantaneous difference between the readings of any two clocks is called their skew.

[0060] In some examples, the respective performance 136 includes a delay or an IR-drop for the digital application scenario 134, and a gain, a noise, an IR-drop and / or a skew for the analog application scenario 134.

[0061] For example, if a delay is used as performance indicator 130, the following values may be observed in an electronic circuit layout 120. Modelling a given interconnect 122 of the electronic circuit layout 120 with a simple interconnect parasitic model 128-1 (taking one or more resistances R and one or more capacitances C into account) and using a correspondingly simple, approximate solution parasitic extraction tool 132-1, the overall delay is 5ps. Modelling a given interconnect 122 of the electronic circuit layout 120 with more complex interconnect parasitic model 128-2 (taking one or more resistances R, one or more inductances L, and one or more capacitances C into account) and using a correspondingly more complex, approximate solution parasitic extraction tool 132-2, the overall delay is 5.001ps. Modelling a given interconnect 122 of the electronic circuit layout 120 with a full-wave interconnect parasitic model 128-3 and using a correspondingly sophisticated, full-wave parasitic extraction tool 132-3, the overall delay is 5.005ps.

[0062] In such an example, because of the comparably small differences of the determined overall delay as the performance indicator 130, there may be no need to select a full-wave parasitic extraction tool 132-3, so that the simple, approximate solution parasitic extraction tool 132-1 may be selected.

[0063] By way of example, the respective characteristic 126 of the respective interconnect 122 includes at least one of the route length l, the minimal width w of the metal layers, and the minimal dimensions of the metal layers of the respective interconnect 122, or any combi- nation thereof.

[0064] Herein, the route length l may be the geometrical length of the respective interconnect 122 between the starting point and the end point of the respective interconnect 122. Herein, the respective interconnect 122 may electrically connect two electrical components, such as resistances R, inductances L, capacitances C or transistors, wherein the route length l may then be the geometrical length of the respective interconnect 122 between the two electrical components connected via the respective interconnect 122. The minimal width w of the metal layers of the respective interconnect 122 may, e.g., be the geometric202403132 15 width of the respective interconnect 122 at the narrowest portion of the respective interconnect 122, wherein the minimal width w may, e.g., perpendicular to the direction of the route of the respective interconnect 122 and, e.g., parallel to on wafer on which the respective interconnect 122 is arranged. Further, the minimal dimensions may include the route length l, the minimal width w and / or the thickness of the metal layers of the respective interconnect 122. Cf. Fig. 4 and the corresponding explanations for an illustrative example interconnect 122.

[0065] One or more of these characteristics 126 of the respective interconnect 122 may, e.g., be used as an input to a classifier model in order to estimate an approximate interconnect parasitic model 128 for each interconnect 122.

[0066] In further examples, the electronic circuit layout 120 includes logic elements and / or memory elements, wherein two or more of the interconnects 122 are considered to be a respective interconnect 122 if the two or more of the interconnects 122 include parallel busses connecting the same logic elements and / or the same memory elements.

[0067] Grouping interconnected interconnects 122 into one interconnect 122 for the purposes of the suggested approach may, e.g., contribute to save computational efforts and speed up the determination of the parasitic elements 124 of the respective interconnect 122 of the electronic circuit layout 120.

[0068] In some examples, the respective interconnect parasitic model 128 includes at least one of a RC model 128-1, a RLC model 128-2, and a full-wave model 128-3, wherein the corresponding parasitic extraction tool 132 includes a RC parasitic extraction tool 132-1 for the RC model 128-1, a RLC parasitic extraction tool 132-2 for the RLC model 128-2, or a full-wave parasitic extraction tool 132-3 for the full-wave model 128-3.

[0069] In some examples, the above-mentioned simple interconnect parasitic model 128-1 taking one or more resistances R and one or more capacitances C into account may correspond to the RC model 128-1 which may, in some examples, model the respective interconnect 122 as RC circuit(s) or lumped RC circuit(s). By way of example, the RC model 128-1 may make use of the Pi model or the T model which are named for their shapes and how the resistances R and capacitances C are arranged. Cf. Fig. 6 for an illustration of a simple Pi model with two C / 2 capacitances and one R resistance. A simple T model may have accordingly two R / 2 resistances and one C capacitance. If the RC model 128-1 is selected using the respective performance indicators 130, a RC parasitic extraction tool 132-1 may be used to determine the parasitic elements 124 of the respective interconnect 122.202403132 16

[0070] Further, the above-mentioned more complex interconnect parasitic model 128-2 taking one or more resistances R, one or more inductances L, and one or more capacitances C into account may, e.g., correspond to the RLC model 128-2 which may, in some examples, model the respective interconnect 122 as RLC circuit(s) or lumped RLC circuit(s). In some examples, the RLC model 128-2 may provide a good model for low and intermediate fre- quencies f. If the RLC model 128-2 is selected using the respective performance indicators 130, a RLC parasitic extraction tool 132-2 may be used to determine the parasitic elements 124 of the respective interconnect 122.

[0071] Also, the most accurate interconnect parasitic model 128-3 may, e.g., correspond to the full-wave model 128-3. Herein, the full-wave model 128-3 may, e.g., take so-called S- parameters (scattering parameters) into account which may, e.g., imply how voltages and currents in a transmission line are affected due to a discontinuity of an inserted network into it. E.g., a two-dimensional S-matrix may be established for an electrical component providing a frequency-dependent relationship between the incident, reflected and transmitted waves at each port over a range of frequencies. Hence, the S-parameters may, e.g., provide an amplitude-phase feel in frequency domain rather than transient voltages and currents. If the full-wave model 128-3 is selected using the respective performance indicators 130, a full- wave parasitic extraction tool 132-3 may be used to determine the parasitic elements 124 of the respective interconnect 122.

[0072] By way of example, the application software component 106 and / or the processor 102 may further be configured to determine at least a first modelled performance 136-1 of the electronic circuit layout 120 using the first interconnect parasitic model 128-1 for the respective interconnect 122 and a second modelled performance 136-2 of the electronic circuit layout 120 using the second interconnect parasitic model 128-2 for the respective interconnect 122; and to determine the respective performance indicator 130-1, 130-2 using the first modelled performance 136-1 and the second modelled performance 136-2.

[0073] Referring to the above example of a delay as performance indicator 130, the delay (values) of 5ps according to the simple interconnect parasitic model 128-1 (e.g., the RC model 128-1), 5.001ps according to the more complex interconnect parasitic model 128-2 (e.g., the RLC model 128-2), and 5.005ps according to the full-wave interconnect parasitic model 128-3 (e.g., the full-wave model 128-3) may also be understood, in some examples, as the respective modelled performance 136-1, 136-2, 136-3. These modelled performances 136-1, 136-2, 136-3 may, e.g., be used as an input to derive a slightly different respective202403132 17 performance indicator 130-1, 130-2, 130-3 which may be understood as a respective performance sensitivity:

[0074] In a first delay example, the performance indicators 130 may be defined as the ratio of one of the respective modelled performances 136-1, 136-2, 136-3 to another of the respective modelled performances 136-1, 136-2, 136-3, e.g.: the ratio rRC-RLC of the delay according to the RC model 128-1 to the delay according to the RLC model 128-2 - 5ps / 5.001ps; the ratio rRLC-FWof the delay according to the RLC model 128-2 to the delay according to the full-wave model 128-3 - 5.001ps / 5.005ps; the ratio rRC-FW of the delay according to the RC model 128-1 to the delay according to the full-wave model 128-3 - 5ps / 5.005ps. The respective performance indicators 130 or ratio may, e.g., also be expressed as a relative difference in %, e.g. for the ratio of the delay according to the RC model 128-1 to the delay according to the RLC model 128-2: 100*(5ps - 5.001ps) / 5.001ps. Since the delay determined based on the simple and light-weight RC model 128-1 results only in a relative difference of ca. 0,1% compared to the delay determined based on the full-wave model 128- 3, the simple, approximate solution RC parasitic extraction tool 132-1 may be selected. Generally, in some examples, if the ratios rRC-RLC, rRLC-FW, rRC-FW are all comparably small (e.g., the respective absolute value is <0.01 or 1%), the simple and lightweight RC model 128-1 may be sufficient and may therefore be selected so that the approximate solution RC parasitic extraction tool 132-1 may be used to determine the parasitic elements 124. If the ratios rRC-RLCand rRC-FWare comparably great (e.g., the respective absolute value is >0.01 or 1%) and the ratio rRLC-FWis comparably small (e.g., the absolute value is <0.01 or 1%), the more complex RLC model 128-2 may need to be selected because the RC model 128-1 may not be adequate enough, and the full-wave model 128-3 may not need to be required. Hence, the approximate solution RLC parasitic extraction tool 132-2 may be used to determine the parasitic elements 124. If the ratios rRC-RLC, rRLC-FW, rRC-FW are all comparably great (e.g., the respective absolute value is >0.01 or 1%), the full-wave model 128-3 may need to be selected because the RC model 128-1 and the RLC model 128-2 both may not be adequate enough. Hence, the full-wave parasitic extraction tool 132-2 may be used to determine the parasitic elements 124.

[0075] In a second delay example, the performance indicators 130 may be defined as the ratio of one of the respective modelled performances 136-1, 136-2, 136-3 to the real performance 136r, e.g., determined using a field solver which may calculate electromagnetic parameters by directly solving Maxwell's equations, e.g.: the ratio rRC-real of the delay202403132 18 according to the RC model 128-1 to the real delay (which is assumed to be 5.006ps) - 5ps / 5.006ps; the ratio rRLC-real of the delay according to the RLC model 128-2 to the real delay - 5.001ps / 5.006ps; the ratio rFW-real of the delay according to the full-wave model 128-3 to the real delay - 5.005ps / 5.006ps. The respective performance indicators 130 or ratio may, e.g., also be expressed as a relative difference in %, e.g. for the ratio of the delay according to the RC model 128-1 to the real delay - 100*(5ps - 5.006ps) / 5.006ps. Since the delay determined based on the simple and light-weight RC model 128-1 results only in a relative difference of ca. 0,1% compared to the real delay, the simple, approximate solution RC parasitic extraction tool 132-1 may be selected. Generally, in some examples, if the ratios rRC-real, rRLC-real, rFW-real are all comparably small (e.g., the respective absolute value is <0.01 or 1%), the simple and lightweight RC model 128-1 may be sufficient and may therefore be selected so that the approximate solution RC parasitic extraction tool 132-1 may be used to determine the parasitic elements 124. If the ratio rRC-real is comparably great (e.g., the absolute value is >0.01 or 1%) and the ratios rRLC-real, rFW-realare comparably small (e.g., the respective absolute value is <0.01 or 1%), the more complex RLC model 128-2 may need to be selected because the RC model 128-1 may not be adequate enough and the full-wave model 128-3 may not need to be required. Hence, the approximate solution RLC parasitic extraction tool 132-2 may be used to determine the parasitic elements 124. If the ratios rRC-real, rRLC-real (and maybe even rFW-real) are all comparably great (e.g., the respective absolute value is >0.01 or 1%), the full-wave model 128-3 may need to be selected because the RC model 128-1 and the RLC model 128-2 both may not be adequate enough. Hence, the full-wave parasitic extraction tool 132-2 may be used to determine the parasitic elements 124.

[0076] In some examples, the respective ratio of the modelled performance indicator 130 according to the respective interconnect parasitic model 128 to the performance indicator 130 according to the most complex interconnect parasitic model 128 or the real performance indicator 130r is considered.

[0077] In further examples, one or more of the above-mentioned performance indicators 130 may be used to determine the respective performance indicator 130. If at least two performance indicators 130 are used, a weighting factor may be introduced reflecting a greater importance of one of the performance indicators 130 compared to the other performance indicator(s) 130.

[0078] As already mentioned above, the respective performance 136 and performance indicator 130 may depend on the on the application scenario 134.202403132 19

[0079] In further examples, the interconnect parasitic models 128 are enumerated with respect to increasing complexity, wherein the application software component 106 and / or the processor 102 may further be configured for the respective interconnect to select the least complex interconnect parasitic model 128 which respective performance indicator 130 is within a pre-configurable threshold.

[0080] By way of example, the above-mentioned RC model 128-1 may be the first interconnect parasitic model 128-1 as it is comparably simple and lightweight and only takes one or more resistances R and one or more capacitances C into account. Further, the above- mentioned RLC model 128-2 may be the second interconnect parasitic model 128-2 as it has intermediate complexity and takes one or more resistances R, one or more inductances L, and one or more capacitances C into account. The above-mentioned full-wave model 128-3 may be the third interconnect parasitic model 128-3 as it has advanced complexity. In some examples, only two of these three interconnect parasitic models 128 and / or additional interconnect parasitic models 128 may be used.

[0081] In the context of the above first delay example according to which the performance indicators 130 may be defined as the ratio of one of the respective modelled performances 136-1, 136-2, 136-3 to another of the respective modelled performances 136-1, 136-2, 136-3, the absolute value of 0.01 or 1% for the respective the ratio rRC-RLC, rRLC-FW, rRC-FW may, e.g., be the pre-configurable threshold. Accordingly, in the context of the above second delay example according to which the performance indicators 130 may be defined as the ratio of one of the respective modelled performances 136-1, 136-2, 136-3 to the real performances 136r, the absolute value of 0.01 or 1% for the respective the ratio rRC-real, rRLC-real, rFW-real may, e.g., be the pre-configurable threshold. Herein, in both examples, the pre-configurable threshold may take other values or may be chosen or adapted during the suggested approach: The pre-configurable threshold may, e.g., be also chosen to be 0.002, 0.005, 0.02, 0.05 or any other constructive value which helps to find the above-mentioned reasonable trade-off between an accuracy and computational efforts relating to the respective interconnect parasitic model 128.

[0082] In some examples, if the absolute value of the ratio of the modelled performance indicator 130-1 according to the first (i.e., the simplest) interconnect parasitic model 128-1 to the performance indicator 130 according to the most complex interconnect parasitic model 128 or the real performance indicator 130r is smaller than the pre-configurable threshold, the simplest interconnect parasitic model 128-1 is selected and else, the next interconnect202403132 20 parasitic model 128-2 is tested. If the absolute value of the ratio of the modelled performance indicator 130-2 according to the second (i.e., next more complex) interconnect parasitic model 128-2 to the performance indicator 130 according to the most complex interconnect parasitic model 128 or the real performance indicator 130r is smaller than the pre-configur- able threshold, the second interconnect parasitic model 128-2 is selected and else, the next interconnect parasitic model 128-3 is tested, and so on. The procedure may stop if the most complex interconnect parasitic model 128 has been tested, wherein the most complex inter- connect parasitic model 128 may, in some examples, be selected if the tested less complex interconnect parasitic models 128 were not selected earlier.

[0083] By way of example, the application software component 106 and / or the processor 102 may further be configured to determine the parasitic elements 124 of the electronic circuit layout 120 using the respective parasitic extraction tool 132 corresponding to the respective, selected interconnect parasitic model 128 for the respective interconnect 122.

[0084] The suggested approach to determine the parasitic elements 124 of an individual interconnect 122 using a suitable extraction tool 132 may then be carried out for all the inter- connects 122 of the electronic circuit layout 120. Hence, the parasitic elements 124 of the electronic circuit layout 120 may be determined, wherein in some examples, a reasonable trade-off between the accuracy and the involved computational efforts may be achieved.

[0085] In further examples, the application software component 106 and / or the processor 102 may further be configured to determine a parasitic netlist including the determined parasitic elements 124 of the electronic circuit layout 120.

[0086] Herein, in an EDA or design flow context, a netlist may, e.g., be understood as the electronic circuit layout’s 120 or the corresponding electronic circuit’s 150 list of interconnects 122 which electrically connect the electric components of the electronic circuit layout 120 or the corresponding electronic circuit 152. In some examples, the netlist may further include the electric components of the electronic circuit layout 120 or the corresponding electronic circuit 152. Herein, the parasitic netlist may include the determined parasitic elements 124 of the interconnects 122 and, in some examples, further the components’ parasitic elements 124. In some examples, the mentioned parasitic elements 124 may be connected in the parasitic netlist.

[0087] By way of example, the parasitic netlist may provide an adequate model of the interconnects 122, and optionally of the components, of the electronic circuit layout 120 or the corresponding electronic circuit 152. Herein, the parasitic netlist may be accurate enough202403132 21 and as computationally lightweight as possible.

[0088] In some examples, the application software component 106 and / or the processor 102 may further be configured to determine at least one physical property 138 of the electronic circuit layout 120 using the determined parasitic elements 124 of the respective interconnect 122.

[0089] In some examples, the respective physical property 138 may correspond to the above-mentioned performance indicator 130 which may include to a delay, a gain, a noise, an IR-drop and / or a skew. In other examples, the respective physical property 138 may include a heat dissipation, an indicator of electromagnetic inference (EMI), or a mechanical stress occurring during the operation of the corresponding electronic circuit 152, respectively. Herein, the respective physical property 138 may, e.g., be determined using commercially available simulation tools which may use the determined parasitic elements 124 or the determined parasitic netlist as input to determine the respective physical property 138.

[0090] In some examples, the determination of the respective physical property 138 of the electronic circuit layout 120 using the parasitic elements 124 of the respective interconnect 122 may be understood to be the actual physical verification of the electronic circuit layout 120.

[0091] By way of example, the application software component 106 and / or the processor 102 may further be configured to transmit the electronic circuit layout 120 to an electronic circuit manufacturing machine 150, and optionally to cause the electronic circuit manufacturing machine 150 to manufacture one or more electronic circuits 150 according to the transmitted, electronic circuit layout 120.

[0092] In some examples, the transmission of the electronic circuit layout 120 to an electronic circuit manufacturing machine 150 and optionally, the manufacture of the one or more electronic circuits 150 by the electronic circuit manufacturing machine 150 may only done or triggered, if the determined respective physical property of the electronic circuit layout 120 complies with pre-configurable expectations, e.g., if the respective physical property complies with pre-configurable thresholds, e.g., for a heat dissipation, an indicator of electromagnetic inference (EMI), or a mechanical stress occurring during the operation of the corresponding electronic circuit 152.

[0093] By way of example, the determining parasitic elements 124 may be displayed to a user via the ECV UI 116.

[0094] It should be appreciated that the described the application software component 106202403132 22 and / or the processor 102 may carry out an analogous method of determining parasitic elements 124 of an interconnect 122 of an electronic circuit layout 120. Further, a computer- readable medium 160 which may include a computer program product 162 is shown in Fig. 1, wherein the computer program product 162 may be encoded with executable instructions, that when executed, cause the computer system 100 or and / or the ECV system 118 to carry out the described method.

[0095] Fig. 2 depicts a functional block diagram of second example system 100 that facilitates determining parasitic elements 124 of an interconnect 122 of an electronic circuit layout 120 in a product system.

[0096] An interconnect parasitic model 128 from a plurality of interconnect parasitic models 128 of the interconnect 122 may be determined based on a comparison between at least one performance indicator 130 associated with each one of the interconnect parasitic models 128. The parasitic elements 124 of the interconnect 122 may then be determined based on the determined parasitic model 128. These steps may, e.g., include the provision of the electronic circuit layout 120 including a plurality of interconnects 122. At least one characteristic 126 of the respective interconnect 122 may then be determined, and at least a first interconnect parasitic model 128-1 and a second interconnect parasitic model 128-2 may be assigned to the respective interconnect 122. A respective performance indicator 130-1, 130-2 at least of the first interconnect parasitic model 128-1 and the second interconnect parasitic model 128-2 of the respective interconnect 122 may then be determined using the respective characteristic 126 of the respective interconnect 122. Using the respective performance indicator 130-1, 130-2, one of the at least first interconnect parasitic model 128-1 and second interconnect parasitic model 128-2 may then be selected for the respective interconnect 122. Using an extractor tool 132 corresponding to the respective, selected interconnect parasitic model 128, the parasitic elements 124 of the respective interconnect 122 may be determined.

[0097] Fig. 3 depicts an aspect of a first example methodology that facilitates determining parasitic elements 124 of an interconnect 122 of an electronic circuit layout 120 in a product system.

[0098] An electronic circuit layout 120 including a plurality of interconnects 122 may be provided which is denoted in Fig. 3 with “Circuit schematic” and “Layout”. Then interconnects 122 in the electronic circuit layout 120 may be determined which is denoted with “Split interconnects”. E.g., based on characteristics 126 of the respective interconnect 122 and corresponding performance indicators 130, a “Classifier Model” may be applied to202403132 23 identify the interconnect parasitic model 128 and accordingly the extractor tool 132 which suits best to the respective interconnect 122, e.g., in terms of accuracy and involved computational efforts. Herein, the “RC extractor” 132-1, the “RLC extractor” 132-2, and the “Full-wave extractor” are available for selection, wherein reference is made to the explanations above for related details.

[0099] Fig. 4 depicts an aspect of a second example methodology that facilitates determining parasitic elements 124 of an interconnect 122 of an electronic circuit layout 120 in a product system.

[0100] The interconnect 122 is depicted from above, wherein the interconnect 122 may, e.g., arranged on a wafer. The characteristics 126 of the interconnect 122 may include the length l which is the sum of the interconnect parts with lengths l1, l2, and l3. Further, the charac- teristics 126 of the interconnect 122 may include the width w at the narrowest portion of the interconnect 122. By way of example, the characteristics 126 of the interconnect 122 may include the electrical resistance R of the interconnect 122 which is equal to ρ *l / A, wherein ρ is the material-specific electrical resistivity, l is the above-mentioned length and A is the cross-sectional area of the interconnect 122 (e.g., at the narrowest portion of the interconnect 122). In some examples, the characteristics 126 of the interconnect 122 may include the electrical capacitance C which is proportional to ε *l*w / (distance to ground), wherein ε is the dielectrical permittivity, and l and w are the above-mentioned length and width.

[0101] Fig. 5 depicts an aspect of a third example methodology that facilitates determining parasitic elements 124 of an interconnect 122 of an electronic circuit layout 120 in a product system.

[0102] An interconnect 122 and three interconnect parasitic models 128-1, 128-2, 128-3 may be provided. Then three corresponding performance indicators (“sensitivities”) 130-1, 130-2, 130-3 may be determined for the interconnect 122 using the three interconnect parasitic models 128-1, 128-2, 128-3, wherein, e.g., the characteristics 126 of the interconnect 122 may be used. A “decision maker” may then select the interconnect parasitic model 128 and accordingly the extractor tool 132 which suits best to the respective interconnect 122, e.g., in terms of accuracy and involved computational efforts. Herein, “decision maker” may use respective performance indicators 130-1, 130-2, 130-3 as explained above.

[0103] Fig. 6 depicts an aspect of a fourth example methodology that facilitates determining parasitic elements 124 of an interconnect 122 of an electronic circuit layout 120 in a product202403132 24 system.

[0104] The interconnect 122 may be modelled as a (e.g., lumped) RC interconnect parasitic model 128-1 which, in this example, is a simple Pi model with two C / 2 capacitances and one R resistance.

[0105] Fig. 7 depicts an aspect of a fifth example methodology that facilitates determining parasitic elements 124 of an interconnect 122 of an electronic circuit layout 120 in a product system.

[0106] As depicted in Fig. 7, the impedance Z of a very simplified interconnect 122 or a very simplified interconnect parasitic model 128 may be a function of the frequency f or equivalently of the sinusoidal angular frequency ω (= 2πf). The impedance Z may have the electrical resistance R and the impedance ωL as components, wherein Z = R + j ωL, with j being the imaginary unit.

[0107] As long as the frequency is small (e.g., below the depicted crossover threshold), the impact of the inductance L is negligible and the interconnect 122 may be modeled without the inductance L. In the real world and for real interconnects 122, the threshold may be unknown and may be different from one case to another so that it may, in some examples, be advantageous to determine the mentioned performance indicator 130, such as the above-men- tioned performance sensitivity, to identify the interconnect parasitic model 128 and accordingly the extractor tool 132 which suits best to the respective interconnect 122.

[0108] Fig. 8 depicts a functional block diagram of a third example system 100 that facilitates determining parasitic elements 124 of an interconnect 122 of an electronic circuit layout 120 in a product system.

[0109] An interconnect parasitic model 128 from a plurality of interconnect parasitic models 128 of the interconnect 122 may be determined based on a comparison between at least one performance indicator 130 associated with each one of the interconnect parasitic models 128. The parasitic elements 124 of the interconnect 122 may then be determined based on the determined parasitic model 128. These steps may, e.g., include the provision of the electronic circuit layout 120 including a plurality of interconnects 122. At least one characteristic 126 of the respective interconnect 122 may then be determined, and at least a first interconnect parasitic model 128-1 and a second interconnect parasitic model 128-2 may be assigned to the respective interconnect 122. A respective performance 136-1, 136-2 and a respective performance indicator 130-1, 130-2 at least of the first interconnect parasitic model 128-1 and the second interconnect parasitic model 128-2 of the respective interconnect 122 may then be202403132 25 determined using the respective characteristic 126 of the respective interconnect 122. Using the respective performance indicator 130-1, 130-2, one of the at least first interconnect parasitic model 128-1 and second interconnect parasitic model 128-2 may then be selected for the respective interconnect 122. Using an extractor tool 132 corresponding to the respective, selected interconnect parasitic model 128, the parasitic elements 124 of the respective interconnect 122 may be determined.

[0110] Fig. 9 depicts a functional block diagram of a fourth example system 100 that facilitates determining parasitic elements 124 of an interconnect 122 of an electronic circuit layout 120 in a product system.

[0111] The fourth example system 100 has several similarities with the third example system 100 depicted in Fig. 8 and explained above. Additionally, at least one physical property 138 of the electronic circuit layout 120 may be determined using the parasitic elements 124 of the respective interconnect 122. In some examples, the respective physical property 138 may correspond to the above-mentioned performance indicator 130 which may include to a delay, a gain, a noise, an IR-drop and / or a skew. In other examples, the respective physical property 138 may include a heat dissipation, an indicator of electromagnetic inference (EMI), or a mechanical stress occurring during the operation of the corresponding electronic circuit 152, respectively. Herein, the respective physical property 138 may, e.g., be determined using commercially available simulation tools which may use the determined parasitic elements 124 or the determined parasitic netlist as input to determine the respective physical property 138.

[0112] In some examples, the determination of the respective physical property 138 of the electronic circuit layout 120 using the parasitic elements 124 of the respective interconnect 122 may be understood to be the actual physical verification of the electronic circuit layout 120.

[0113] It should be appreciated that with the advent of 3DIC (3 dimensional integrated circuits) and high-frequency applications like 5G and 6G, the necessity of extracting layout parasitic elements with precision is paramount. There are three main parasitic extraction solvers to model the parasitic elements of an integrated circuit: RC, RLC, and full-wave solvers. To obtain a precise and accurate parasitic elements model for integrated circuits in high frequencies, e.g., a full-wave solver may be used; however, the main problems of full- wave solvers are 1) the extraction runtime and 2) the huge netlist. Current full-wave solvers, while accurate, face challenges such as: a long extraction runtime, and huge and complex202403132 26 netlists, which can exceed the capacity of post-layout simulators and lead to a substantial simulation runtime.

[0114] In general, the parasitic elements of layouts may, e.g., be represented by RC, RLC, or full-wave models. Each type of models has its own layout parasitic extractor. The RC extractors provide the smallest netlist, the lowest post-layout simulation runtime, and the lowest post-layout simulations accuracy compared to the other two models, whereas the full- wave extractors provide the largest netlist, the largest post-layout simulation runtime, and the highest post-layout simulation accuracy. For high-frequency applications, designers use RLC and full-wave solvers to model the parasitic elements of layouts.

[0115] Currently and using other approaches, designers face a lot of challenges to decide the appropriate parasitic model for their layout. They do a lot of manual experiments which consumes a lot of time. Moreover, using full-wave solvers for everything is not favorable most of the time as it consumes a lot of time and generates huge and complex netlists. Also, circuit simulators may not have the capacity to absorb the full-wave netlist for the entire layout. Currently, there is no systematic method that helps layout designers identifying the appropriate parasitic models for each interconnect in a layout.

[0116] The suggested approach may, e.g., offer one or more of the following advantages: The proposed flow may automate a hybrid extraction process. Therefore, the designers may, by way of example, easily extract layout parasitics without any manual intervention. Further, the proposed flow may help in providing very accurate parasitic extraction and post-layout simulation results for 3DIC and high frequency applications. In some examples, the proposed flow may further help in providing: A Small netlist size as compared to the full-wave solver netlist that provides the required post-layout simulation accuracy; and faster parasitic extraction runtime as the flow ensures that the full-wave solver is only executed on the interconnects that are very sensitive to it.

[0117] In some examples, it may be very hard for a designer to decide the appropriate parasitic model manually (RC, RLC, or full-wave), specially for border frequencies. By way of example, the proposed hybrid approach may help designers identifying the appropriate parasitic models in such gray areas. The applications of this flow may, e.g., include 3DIC, RF and microwave circuits, signal integrity analysis, power integrity analysis, and high frequency applications. For example, in 3DIC, the interposer fast serial links and the bridges (parallel busses connecting logic and memory) are examples where it is hard for a user to decide what model to use at high frequency. The proposed flow may ease such decision and202403132 27 helps the user extraction the appropriate parasitic model easily.

[0118] Fig. 10 depicts a flow diagram of an example methodology that facilitates determining parasitic elements of an interconnect of an electronic circuit layout in a product system. The method may start at M02, and the methodology may include several acts carried out through operation of at least one processor.

[0119] These acts may include an act M04 of determining an interconnect parasitic model from a plurality of interconnect parasitic models of the interconnect based on a comparison between at least one performance indicator associated with each one of the interconnect parasitic models; and an act M06 of determining the parasitic elements of the interconnect based on the determined interconnect parasitic model. At M08 the methodology may end.

[0120] It should further be appreciated that the methodology M may include other acts and features discussed previously with respect to the computer-implemented method of determining parasitic elements of an interconnect of an electronic circuit layout.

[0121] Fig. 11 depicts a flow diagram of another example methodology that facilitates determining parasitic elements of an interconnect of an electronic circuit layout in a product system. The method may include the acts M02 to M06 of the example methodology depicted in Fig. 9 and explained above. The methodology M may further include an act M10 of providing the electronic circuit layout including a plurality of interconnects; an act M12 of determining at least one characteristic of the respective interconnect; an act M14 of assigning at least a first interconnect parasitic model and a second interconnect parasitic model to the respective interconnect; an act M16 of determining a respective performance indicator at least of the first interconnect parasitic model and the second interconnect parasitic model of the respective interconnect using the respective characteristic of the respective interconnect; an act M18 of selecting one of the at least first interconnect parasitic model and second intercon- nect parasitic model for the respective interconnect using the respective performance indicator; and an act M20 of determining the parasitic elements of the respective interconnect using a parasitic extraction tool corresponding to the respective, selected interconnect parasitic model. At M22 the methodology may end.

[0122] In some examples, the acts M04 and M18 and the acts M06 and M20 may at least partly overlap.

[0123] Fig. 12 depicts a block diagram of a data processing system 1000 (also referred to as a computer system) in which an embodiment can be implemented, for example, as a portion of a product system, and / or other system operatively configured by software or otherwise to202403132 28 perform the processes as described herein. The data processing system 1000 may comprise, for example, the computer or IT system or data processing system 100 mentioned above. The data processing system depicted comprises at least one processor 1002 (e.g., a CPU) that may be connected to one or more bridges / controllers / buses 1004 (e.g., a north bridge, a south bridge). One of the buses 1004, for example, may comprise one or more I / O buses such as a PCI Express bus. Also connected to various buses in the depicted example may comprise a main memory 1006 (RAM) and a graphics controller 1008. The graphics controller 1008 may be connected to one or more display devices 1010. It should also be noted that in some embodiments one or more controllers (e.g., graphics, south bridge) may be integrated with the CPU (on the same chip or die). Examples of CPU architectures comprise IA-32, x86-64, and ARM processor architectures.

[0124] Other peripherals connected to one or more buses may comprise communication controllers 1012 (Ethernet controllers, WiFi controllers, cellular controllers) operative to connect to a local area network (LAN), Wide Area Network (WAN), a cellular network, and / or other wired or wireless networks 1014 or communication equipment.

[0125] Further components connected to various busses may comprise one or more I / O controllers 1016 such as USB controllers, Bluetooth controllers, and / or dedicated audio controllers (connected to speakers and / or microphones). It should also be appreciated that various peripherals may be connected to the I / O controller(s) (via various ports and connections) comprising input devices 1018 (e.g., keyboard, mouse, pointer, touch screen, touch pad, drawing tablet, trackball, buttons, keypad, game controller, gamepad, camera, microphone, scanners, motion sensing devices that capture motion gestures), output devices 1020 (e.g., printers, speakers) or any other type of device that is operative to provide inputs to or receive outputs from the data processing system. Also, it should be appreciated that many devices referred to as input devices or output devices may both provide inputs and receive outputs of communications with the data processing system. For example, the processor 1002 may be integrated into a housing (such as a tablet) that comprises a touch screen that serves as both an input and display device. Further, it should be appreciated that some input devices (such as a laptop) may comprise a plurality of different types of input devices (e.g., touch screen, touch pad, keyboard). Also, it should be appreciated that other peripheral hardware 1022 connected to the I / O controllers 1016 may comprise any type of device, machine, or component that is configured to communicate with a data processing system.

[0126] Additional components connected to various busses may comprise one or more202403132 29 storage controllers 1024 (e.g., SATA). A storage controller may be connected to a storage device 1026 such as one or more storage drives and / or any associated removable media, which can be any suitable non-transitory machine usable or machine-readable storage medium. Examples comprise nonvolatile devices, volatile devices, read only devices, writable devices, ROMs, EPROMs, magnetic tape storage, floppy disk drives, hard disk drives, solid-state drives (SSDs), flash memory, optical disk drives (CDs, DVDs, Blu-ray), and other known optical, electrical, or magnetic storage devices drives and / or computer media. Also, in some examples, a storage device such as an SSD may be connected directly to an I / O bus 1004 such as a PCI Express bus.

[0127] A data processing system in accordance with an embodiment of the present disclosure may comprise an operating system 1028, software / firmware 1030, and data stores 1032 (that may be stored on a storage device 1026 and / or the memory 1006). Such an operating system may employ a command line interface (CLI) shell and / or a graphical user interface (GUI) shell. The GUI shell permits multiple display windows to be presented in the graphical user interface simultaneously, with each display window providing an interface to a different application or to a different instance of the same application. A cursor or pointer in the graphical user interface may be manipulated by a user through a pointing device such as a mouse or touch screen. The position of the cursor / pointer may be changed and / or an event, such as clicking a mouse button or touching a touch screen, may be generated to actuate a desired response. Examples of operating systems that may be used in a data processing system may comprise Microsoft Windows, Linux, UNIX, iOS, and Android operating systems. Also, examples of data stores comprise data files, data tables, relational database (e.g., Oracle, Microsoft SQL Server), database servers, or any other structure and / or device that is capable of storing data, which is retrievable by a processor.

[0128] The communication controllers 1012 may be connected to the network 1014 (not a part of data processing system 1000), which can be any public or private data processing system network or combination of networks, as known to those of skill in the art, comprising the Internet. Data processing system 1000 can communicate over the network 1014 with one or more other data processing systems such as a server 1034 (also not part of the data pro- cessing system 1000). However, an alternative data processing system may correspond to a plurality of data processing systems implemented as part of a distributed system in which processors associated with several data processing systems may be in communication by way of one or more network connections and may collectively perform tasks described as being202403132 30 performed by a single data processing system. Thus, it is to be understood that when referring to a data processing system, such a system may be implemented across several data processing systems organized in a distributed system in communication with each other via a network.

[0129] Further, the term “controller” means any device, system, or part thereof that controls at least one operation, whether such a device is implemented in hardware, firmware, software, or some combination of at least two of the same. It should be noted that the functionality associated with any particular controller may be centralized or distributed, whether locally or remotely.

[0130] In addition, it should be appreciated that data processing systems may be implemented as virtual machines in a virtual machine architecture or cloud environment. For example, the processor 1002 and associated components may correspond to a virtual machine executing in a virtual machine environment of one or more servers. Examples of virtual machine architectures comprise VMware ESCi, Microsoft Hyper-V, Xen, and KVM.

[0131] Those of ordinary skill in the art will appreciate that the hardware depicted for the data processing system may vary for particular implementations. For example, the data pro- cessing system 1000 in this example may correspond to a computer, workstation, server, PC, notebook computer, tablet, mobile phone, and / or any other type of apparatus / system that is operative to process data and carry out functionality and features described herein associated with the operation of a data processing system, computer, processor, and / or a controller discussed herein. The depicted example is provided for the purpose of explanation only and is not meant to imply architectural limitations with respect to the present disclosure.

[0132] Also, it should be noted that the processor described herein may be located in a server that is remote from the display and input devices described herein. In such an example, the described display device and input device may be comprised in a client device that communicates with the server (and / or a virtual machine executing on the server) through a wired or wireless network (which may comprise the Internet). In some embodiments, such a client device, for example, may execute a remote desktop application or may correspond to a portal device that carries out a remote desktop protocol with the server in order to send inputs from an input device to the server and receive visual information from the server to display through a display device. Examples of such remote desktop protocols comprise Teradici's PCoIP, Microsoft's RDP, and the RFB protocol. In such examples, the processor described herein may correspond to a virtual processor of a virtual machine executing in a physical202403132 31 processor of the server.

[0133] As used herein, the terms “component” and “system” are intended to encompass hardware, software, or a combination of hardware and software. Thus, for example, a system or component may be a process, a process executing on a processor, or a processor. Additionally, a component or system may be localized on a single device or distributed across several devices.

[0134] Also, as used herein a processor corresponds to any electronic device that is configured via hardware circuits, software, and / or firmware to process data. For example, processors described herein may correspond to one or more (or a combination) of a microprocessor, CPU, FPGA, ASIC, or any other integrated circuit (IC) or other type of circuit that is capable of processing data in a data processing system, which may have the form of a controller board, computer, server, mobile phone, and / or any other type of electronic device.

[0135] Those skilled in the art will recognize that, for simplicity and clarity, the full structure and operation of all data processing systems suitable for use with the present disclosure is not being depicted or described herein. Instead, only so much of a data processing system as is unique to the present disclosure or necessary for an understanding of the present disclosure is depicted and described. The remainder of the construction and operation of data processing system 1000 may conform to any of the various current implementations and practices known in the art.

[0136] Also, it should be understood that the words or phrases used herein should be construed broadly, unless expressly limited in some examples. For example, the terms “comprise” and “comprise,” as well as derivatives thereof, mean inclusion without limitation. The singular forms “a”, “an” and “the” are intended to comprise the plural forms as well, unless the context clearly indicates otherwise. Further, the term “and / or” as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. The term “or” is inclusive, meaning and / or, unless the context clearly indicates otherwise. The phrases “associated with” and “associated therewith,” as well as derivatives thereof, may mean to comprise, be comprised within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like.

[0137] Also, although the terms “first”, “second”, “third” and so forth may be used herein to202403132 32 describe various elements, functions, or acts, these elements, functions, or acts should not be limited by these terms. Rather these numeral adjectives are used to distinguish different elements, functions or acts from each other. For example, a first element, function, or act could be termed a second element, function, or act, and, similarly, a second element, function, or act could be termed a first element, function, or act, without departing from the scope of the present disclosure.

[0138] In addition, phrases such as “processor is configured to” carry out one or more functions or processes, may mean the processor is operatively configured to or operably configured to carry out the functions or processes via software, firmware, and / or wired circuits. For example, a processor that is configured to carry out a function / process may correspond to a processor that is executing the software / firmware, which is programmed to cause the processor to carry out the function / process and / or may correspond to a processor that has the software / firmware in a memory or storage device that is available to be executed by the processor to carry out the function / process. It should also be noted that a processor that is “configured to” carry out one or more functions or processes, may also correspond to a processor circuit particularly fabricated or “wired” to carry out the functions or processes (e.g., an ASIC or FPGA design). Further the phrase “at least one” before an element (e.g., a processor) that is configured to carry out more than one function may correspond to one or more elements (e.g., processors) that each carry out the functions and may also correspond to two or more of the elements (e.g., processors) that respectively carry out different ones of the one or more different functions.

[0139] In addition, the term “adjacent to” may provide that: an element is relatively near to but not in contact with a further element; or the element is in contact with the further portion, unless the context clearly indicates otherwise.

[0140] Although an exemplary embodiment of the present disclosure has been described in detail, those skilled in the art will understand that various changes, substitutions, variations, and improvements disclosed herein may be made without departing from the spirit and scope of the disclosure in its broadest form.

[0141] None of the description in the present patent document should be read as implying that any particular element, step, act, or function is an essential element, which must be included in the claim scope: the scope of patented subject matter is defined only by the allowed claims.202403132 33 Reference Signs List 100 processing system 102 processor 104 memory 106 application software component 108 internal data store 110 input device 112 display device 114 graphical user interface (GUI) 116 electronic circuit verification UI 118 electronic circuit verification system 120 electronic circuit layout 122 interconnect 124 parasitic element 126 characteristic 128 parasitic model 130 performance indicator 132 parasitic extraction tool 134 application scenario 136 performance 138 physical property 150 electronic circuit manufacturing machine 152 electronic circuit 160 computer-readable medium 162 computer program product R resistance L inductance C capacitance202403132 34 Z impedance ω sinusoidal angular frequency (2πf, f: frequency) l length w width

Claims

202403132 35 CLAIMS 1. A computer-implemented method for determining parasitic elements of an interconnect of an electronic circuit layout, the computer-method comprising: determining an interconnect parasitic model from a plurality of interconnect parasitic models of the interconnect based on a comparison between at least one performance indicator associated with each one interconnect parasitic model of the plurality of interconnect parasitic models; and determining the parasitic elements of the interconnect based on the determined interconnect parasitic model.

2. The computer-implemented method according to claim 1, further comprising: providing the electronic circuit layout including a plurality of interconnects; determining at least one characteristic of a respective interconnect of the plurality of interconnects; assigning at least a first interconnect parasitic model and a second interconnect parasitic model to the respective interconnect; determining a respective performance indicator at least of the first interconnect parasitic model and the second interconnect parasitic model of the respective interconnect using a respective characteristic of the at least one characteristic of the respective interconnect; selecting one of the at least the first interconnect parasitic model and the second interconnect parasitic model for the respective interconnect using the respective performance indicator; and determining the parasitic elements of the respective interconnect using a parasitic extraction tool corresponding to the respective, selected interconnect parasitic model.

3. The computer-implemented method according to any one of the preceding claims, further comprising: providing an application scenario of the electronic circuit layout; and determining the respective performance indicator of the respective interconnect further using the application scenario,202403132 36 wherein the application scenario includes a digital application scenario and an analog application scenario, and wherein the respective performance indicator includes a delay, a gain, a noise, an IR- drop, a skew, or any combination thereof for the digital application scenario, the analog application scenario, or the digital application scenario and the analog application scenario.

4. The computer-implemented method according to claim 2 or 3, wherein the respective characteristic of the respective interconnect includes a route length, a minimal width of metal layers, minimal dimensions of the metal layers of the respective interconnect, or any combination thereof.

5. The computer-implemented method according to any one of the preceding claims, wherein the electronic circuit layout includes logic elements, memory elements, or the logic elements and the memory elements, and wherein two or more interconnects of the plurality of interconnects are considered to be a respective interconnect when the two or more interconnects include parallel busses connecting the same logic elements, the same memory elements, or the same logic elements and the same memory elements.

6. The computer-implemented method according to any one of the preceding claims, wherein the respective interconnect parasitic model includes an RC model, an RLC model, a full-wave model, or any combination thereof, and wherein the corresponding extractor tool includes an RC extractor tool for the RC model, an RLC extractor tool for the RLC model, or a full-wave extractor tool for the full- wave model.

7. The computer-implemented method according to any one of the preceding claims, further comprising: determining at least a first modelled performance of the electronic circuit layout using the first interconnect parasitic model for the respective interconnect and a second modelled performance of the electronic circuit layout using the second interconnect parasitic model for the respective interconnect; and202403132 37 determining the respective performance indicator using the first modelled performance and the second modelled performance.

8. The computer-implemented method according to any one of the preceding claims, wherein the plurality of interconnect parasitic models are enumerated with respect to increasing complexity, and wherein for the respective interconnect, the method further comprises selecting a least complex interconnect parasitic model which respective performance indicator is within a pre- configurable threshold.

9. The computer-implemented method according to any one of claims 2 to 8, further comprising: determining the parasitic elements of the electronic circuit layout using the respective extractor tool corresponding to the respective, selected interconnect parasitic model for the respective interconnect.

10. The computer-implemented method according to any one of the preceding claims, further comprising: determining a parasitic netlist including the determined parasitic elements of the electronic circuit layout.

11. The computer-implemented method according to any one of the preceding claims, further comprising: determining at least one physical property of the electronic circuit layout using the determined parasitic elements of the respective interconnect.

12. The computer-implemented method according to any of the preceding claims, further comprising: transmitting the electronic circuit layout to an electronic circuit manufacturing machine.

13. A computer system arranged and configured to execute the steps of the computer- implemented method according to any one of the preceding claims.202403132 38 14. A computer program product, including computer program code that, when executed by a computer system, causes the computer system to carry out the method of one of the claims 1 to 12.

15. A computer-readable medium including a computer program product including computer program code that, when executed by a computer system, causes the computer system to carry out the method of one of the claims 1 to 12.

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