Memory and manufacturing method therefor, and electronic device

Abstract

A memory and a manufacturing method therefor, and an electronic device. The memory comprises a first semiconductor structure and a second semiconductor structure coupled to the first semiconductor structure. The first semiconductor structure comprises a plurality of memory arrays arranged in an array and spaced apart from each other; each memory array comprises a plurality of memory cells arranged in an array; each memory cell comprises a vertical transistor extending in a first direction and a capacitor coupled to the vertical transistor; the capacitor comprises a first electrode and a second electrode opposite to each other; and the first electrode is coupled to the vertical transistor. The second semiconductor structure comprises a peripheral circuit and is arranged on the side of the vertical transistor distant from the capacitor in the first direction. The first semiconductor structure further comprises a common electrode electrically connected to second electrodes of the capacitors in the plurality of memory arrays and a common electrode contact plug arranged on the same side of the common electrode as the vertical transistor in the first direction, and the common electrode is coupled to the peripheral circuit by means of the common electrode contact plug.

Description

Memory and manufacturing method thereof, and electronic device Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to a memory, a manufacturing method thereof, and an electronic device. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a type of semiconductor memory. Compared to static memory, DRAM offers advantages such as a simpler structure, lower manufacturing costs, and higher storage density. With technological advancements, DRAM is becoming increasingly popular.

[0003] Current DRAMs typically include multiple memory banks, each of which includes multiple memory arrays. Each memory array shares the same common electrode, and the common electrodes corresponding to different memory arrays are separated from each other, so that other functional devices (typically including passive devices, such as decoupling capacitors, etc.) can be set between adjacent memory arrays. However, such a setting also limits the reduction of memory chip size.

[0004] Summary of the Invention

[0005] According to a first aspect of an embodiment of the present disclosure, there is provided a memory, including:

[0006] A first semiconductor structure includes a plurality of memory arrays arranged in an array and spaced apart from each other, wherein each of the plurality of memory arrays includes a plurality of memory cells arranged in an array, each of the plurality of memory cells includes a vertical transistor extending along a first direction and a capacitor coupled to the vertical transistor, the capacitor including a first electrode and a second electrode opposite to each other, the first electrode coupled to the vertical transistor.

[0007] a second semiconductor structure including a peripheral circuit, bonded to the first semiconductor structure, wherein the second semiconductor structure is disposed on a side of the vertical transistor away from the capacitor in the first direction;

[0008] The first semiconductor structure further includes a common electrode and a common electrode contact plug, the common electrode is electrically connected to the second electrodes of the capacitors in the multiple storage arrays, the common electrode contact plug and the vertical transistor are arranged on the same side of the common electrode in the first direction, and the common electrode is coupled to the peripheral circuit through the common electrode contact plug.

[0009] In some embodiments, the common electrode includes a plurality of first plate-like portions corresponding one-to-one to the plurality of storage arrays and a second plate-like portion connecting the plurality of first plate-like portions, wherein the second plate-like portion is arranged between adjacent storage arrays and is closer to the second semiconductor structure than the plurality of first plate-like portions.

[0010] In some embodiments, an orthographic projection of the common electrode contact plug along the first direction is located within an orthographic projection of the second plate-shaped portion along the first direction.

[0011] In some embodiments, the plurality of first plate-shaped portions and the second plate-shaped portion are integrally formed.

[0012] In some embodiments, an orthographic projection of the common electrode contact plug along the first direction is located in a region defined by four adjacent vertex corners of orthographic projections of four adjacent memory arrays along the first direction.

[0013] In some embodiments, the capacitor further includes a capacitor dielectric layer disposed between the first electrode and the second electrode, the capacitor dielectric layer in the plurality of storage arrays is integrally formed, and the common electrode contact plug penetrates the capacitor dielectric layer and is coupled to the common electrode.

[0014] In some embodiments, the capacitor further includes a capacitor dielectric layer disposed between the first electrode and the second electrode. The capacitor dielectric layer in each storage array is integrally formed, and the capacitor dielectric layers in the multiple storage arrays are separate from each other.

[0015] In some embodiments, the second electrodes in each memory array are integrally formed, and the second electrodes in the plurality of memory arrays are integrally formed or are separate from each other.

[0016] In some embodiments, the second electrodes in the plurality of memory arrays are integrally formed with the common electrode.

[0017] In some embodiments, each of the memory arrays further includes a plurality of word lines extending along a second direction and a plurality of bit lines extending along a third direction; in each of the memory arrays, each of the plurality of word lines is coupled to a row of the vertical transistors arranged along the second direction, and each of the plurality of bit lines is coupled to a column of the vertical transistors arranged along the third direction; the second direction is perpendicular to the first direction, the third direction is perpendicular to the first direction, and the third direction intersects with the second direction.

[0018] In some embodiments, the word lines in adjacent memory arrays are arranged to be spaced apart from each other, and the bit lines in adjacent memory arrays are arranged to be spaced apart from each other.

[0019] In some embodiments, the first semiconductor structure further includes: a plurality of first contact plugs coupled one-to-one with the plurality of word lines in each memory array, each of the plurality of first contact plugs being disposed on a side of the corresponding word line close to the second semiconductor structure; and a plurality of second contact plugs coupled one-to-one with the plurality of bit lines in each memory array, each of the plurality of second contact plugs being disposed on a side of the corresponding bit line close to the second semiconductor structure.

[0020] In some embodiments, the first semiconductor structure further includes a first interconnect layer, which is arranged on a side of the multiple memory arrays close to the second semiconductor structure in the first direction; the second semiconductor structure further includes a second interconnect layer, which is arranged on a side of the peripheral circuit close to the first semiconductor structure in the first direction; the memory further includes a bonding interface arranged between the first interconnect layer and the second interconnect layer.

[0021] In some embodiments, the second semiconductor structure further includes a third interconnect layer, which is disposed on a side of the peripheral circuit away from the first semiconductor structure, and is configured to couple the peripheral circuit with an external circuit.

[0022] According to a second aspect of an embodiment of the present disclosure, a method for preparing a semiconductor structure is provided, comprising:

[0023] A first semiconductor structure is provided, wherein the first semiconductor structure includes a plurality of memory arrays arranged in an array and spaced apart from each other, each memory array in the plurality of memory arrays includes a plurality of memory cells arranged in an array, each memory cell in the plurality of memory cells includes a vertical transistor extending along a first direction and a capacitor coupled to the vertical transistor, the capacitor including a first electrode and a second electrode opposite to each other, the first electrode being coupled to the vertical transistor, the first semiconductor structure further including a common electrode and a common electrode contact plug, the common electrode being electrically connected to the second electrode of the capacitors in the plurality of memory arrays, the common electrode contact plug and the vertical transistor being disposed on the same side of the common electrode in the first direction;

[0024] providing a second semiconductor structure, wherein the second semiconductor structure includes a peripheral circuit;

[0025] The first semiconductor structure and the second semiconductor structure are bonded to each other so that the common electrode is coupled to the peripheral circuit through the common electrode contact plug, wherein the second semiconductor structure is disposed on a side of the vertical transistor away from the capacitor in the first direction.

[0026] According to a third aspect of an embodiment of the present disclosure, there is provided an electronic device, including:

[0027] processor; and

[0028] The memory provided by any embodiment of the present disclosure is coupled to the processor.

[0029] In an embodiment of the present disclosure, multiple memory arrays share the same common electrode. Accordingly, other functional devices (for example, decoupling capacitors, etc.) can be arranged on the periphery of the multiple memory arrays, thereby reducing the spacing between adjacent memory arrays. Overall, the size of the first semiconductor structure can be reduced, which is beneficial to reducing the chip size of the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] FIG1 is a schematic diagram of a cross-sectional structure of a memory provided by some embodiments of the present disclosure;

[0031] FIG2 is a schematic diagram illustrating the arrangement of multiple storage arrays in a memory provided by some embodiments of the present disclosure;

[0032] FIG3 a is a schematic diagram of a cross-sectional structure of a memory provided by some embodiments of the present disclosure, taken along line A1A2 in FIG2 ;

[0033] FIG3 b is a schematic diagram of a cross-sectional structure of a memory provided by some embodiments of the present disclosure, taken along line B1B2 in FIG2 ;

[0034] FIG4 is a schematic diagram of a planar structure of an interconnection line provided by some embodiments of the present disclosure;

[0035] FIG5 a is a schematic diagram of a partial cross-sectional structure of a memory provided by other embodiments of the present disclosure, taken along line A1A2 in FIG2 ;

[0036] FIG5 b is a schematic diagram of a partial cross-sectional structure of a memory provided by other embodiments of the present disclosure, taken along line B1B2 in FIG2 ;

[0037] FIG6 a is a schematic diagram of a partial cross-sectional structure of a memory provided by still other embodiments of the present disclosure, taken along line A1A2 in FIG2 ;

[0038] FIG6 b is a schematic diagram of a partial cross-sectional structure of a memory provided by still other embodiments of the present disclosure, taken along line B1B2 in FIG2 ;

[0039] FIG7 is a schematic flow chart of a method for manufacturing a memory device according to some embodiments of the present disclosure;

[0040] FIG8 is a schematic block diagram of the structure of an electronic device provided in some embodiments of the present disclosure. DETAILED DESCRIPTION

[0041] The technical solutions of the present disclosure will be further described in detail below with reference to the accompanying drawings and examples. Although the accompanying drawings illustrate exemplary implementations of the present disclosure, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0042] The following paragraphs describe the present disclosure in more detail by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become more apparent from the following description and claims. It should be noted that the drawings are highly simplified and not to exact scale, and are intended solely to facilitate and clearly illustrate the embodiments of the present disclosure.

[0043] It will be understood that the meanings of “on,” “over,” and “over” throughout this disclosure should be interpreted in the broadest manner, such that “on” not only means being “on” something with no intervening features or layers (i.e., directly on something), but also includes being “on” something with intervening features or layers.

[0044] In the embodiments of the present disclosure, the terms "first," "second," "third," etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0045] In the embodiments of the present disclosure, the term "layer" refers to a portion of a material including an area having a thickness. A layer may extend over the entirety of a lower or upper structure, or may have an extent that is smaller than the extent of the lower or upper structure. In addition, a layer may be an area of ​​a homogeneous or inhomogeneous continuous structure having a thickness that is smaller than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be between any horizontal faces at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.

[0046] In the embodiments of the present disclosure, the term "coupling" refers to two (or more) conductive structures being operably connected to each other. Depending on actual needs, it may include but is not limited to the following situations: 1) the two conductive structures are directly electrically connected; 2) the two conductive structures are indirectly electrically connected (through other conductive structures); 3) although the two conductive structures are not electrically connected (for example, an insulating layer is provided between the two), one of the two conductive structures can control the electrical properties of the other of the two conductive structures in response to an electrical signal, for example, the gate (or word line) is coupled with the active area (or channel area).

[0047] It should be noted that the technical solutions and technical features described in the embodiments of the present disclosure can be arbitrarily combined without conflict.

[0048] At least some embodiments of the present disclosure provide a memory. The memory includes a first semiconductor structure and a second semiconductor structure coupled to the first semiconductor structure. The first semiconductor structure includes a plurality of memory arrays arranged in an array and spaced apart from each other. Each memory array in the plurality of memory arrays includes a plurality of memory cells arranged in an array. Each memory cell in the plurality of memory cells includes a vertical transistor extending along a first direction and a capacitor coupled to the vertical transistor. The capacitor includes a first electrode and a second electrode opposing each other, the first electrode coupled to the vertical transistor. The second semiconductor structure includes peripheral circuitry. The second semiconductor structure is disposed on a side of the vertical transistor in the first direction away from the capacitor. The first semiconductor structure also includes a common electrode and a common electrode contact plug. The common electrode is electrically connected to the second electrode of the capacitor in the plurality of memory arrays. The common electrode contact plug and the vertical transistor are disposed on the same side of the common electrode in the first direction. The common electrode is coupled to the peripheral circuitry via the common electrode contact plug. In embodiments of the present disclosure, the plurality of memory arrays share the same common electrode. Accordingly, other functional devices (e.g., decoupling capacitors, etc.) can be disposed on the periphery of the plurality of memory arrays, thereby reducing the spacing between adjacent memory arrays and, overall, reducing the size of the first semiconductor structure, thereby facilitating a reduction in the chip size of the memory.

[0049] Figure 1 is a schematic diagram of the cross-sectional structure of a memory provided in some embodiments of the present disclosure; Figure 2 is a schematic diagram of the arrangement of multiple memory arrays in a memory provided in some embodiments of the present disclosure; Figure 3a is a schematic diagram of the cross-sectional structure of the memory provided in some embodiments of the present disclosure taken along the A1A2 line in Figure 2; Figure 3b is a schematic diagram of the cross-sectional structure of the memory provided in some embodiments of the present disclosure taken along the B1B2 line in Figure 2.

[0050] For example, as shown in Figures 1, 2, 3a, and 3b, the memory 10 may include a first semiconductor structure 100 and a second semiconductor structure 200. The first semiconductor structure 100 may include a plurality of memory arrays 105 arranged in an array and spaced apart from each other, and the second semiconductor structure 200 may include a peripheral circuit 205. The first semiconductor structure 100 and the second semiconductor structure 200 may be bonded to each other via a bonding interface 300, so that the plurality of memory arrays 105 are respectively coupled to the peripheral circuit 205.

[0051] For example, as shown in Figures 2, 3a, and 3b, each memory array 105 may include a plurality of memory cells arranged in an array, each memory cell including a vertical transistor 110 extending along a first direction Z and a capacitor 120 coupled to the vertical transistor 110. The second semiconductor structure 200 may be disposed on a side of the vertical transistor 110 away from the capacitor 120 in the first direction Z.

[0052] It should be noted that the number of memory arrays in the accompanying drawings is exemplary and is not limited in the embodiments of the present disclosure. For example, in some examples, the memory 10 may include m×n memory arrays 105, where m represents the number of memory arrays 105 in the row direction (e.g., the second direction X hereinafter), and n represents the number of memory arrays 105 in the column direction (e.g., the third direction Y hereinafter), and for example, both m and n are positive integers greater than or equal to 2. Figure 2 shows a case where both m and n are 2.

[0053] For example, in some examples, as shown in FIG2 , FIG3 a , and FIG3 b , vertical transistor 110 includes an active pillar 111 extending along a first direction Z, a gate 112 covering the sidewalls of active pillar 111, and a gate dielectric layer 113 located between active pillar 111 and gate 112. For example, the material of active pillar 111 may include any suitable semiconductor material, such as silicon, germanium, gallium arsenide, or an oxide semiconductor material. For example, oxide semiconductor materials may include, but are not limited to, indium gallium zinc oxide (IGZO), indium gallium oxide (IGO), or indium zinc oxide (IZO). For example, the material of gate 112 may include any suitable conductive material, such as titanium nitride (TiN), tantalum nitride (TaN), tungsten, metal silicide, doped polysilicon, or any combination thereof. For example, the material of gate dielectric layer 113 may include any suitable dielectric material, such as silicon oxide, silicon nitride, a high-K dielectric material, or any combination thereof. For example, high-K dielectric materials may include, but are not limited to, hafnium oxide (HfO 2 ) and zirconium oxide (ZrO 2 ). It should be noted that the vertical transistor 110 in the drawings is exemplary, and the embodiments of the present disclosure do not limit the structure of the vertical transistor 110. For example, the vertical transistor 110 can be a gate-all-around (GAA) transistor (as shown in the drawings), or a single-side gate transistor, a double-side (e.g., opposite-side) gate transistor, or a triple-side gate transistor.

[0054] For example, as shown in Figures 3a and 3b, the capacitor 120 includes a first electrode 121 and a second electrode 122 facing each other, and a capacitor dielectric layer 123 disposed between the first electrode 121 and the second electrode 122. For example, the materials of the first electrode 121 and the second electrode 122 include any suitable conductive material, such as titanium nitride (TiN), tantalum nitride (TaN), tungsten, metal silicide, doped polysilicon, or any combination thereof. For example, the material of the capacitor dielectric layer 123 includes any suitable dielectric material, such as silicon oxide, silicon nitride, a high-K dielectric material, or any combination thereof; for example, the material of the capacitor dielectric layer 123 may also include a dielectric material having ferroelectric or antiferroelectric properties, such as ferroelectric hafnium oxide, ferroelectric hafnium zirconium oxide, or the like; that is, the capacitor 120 may be a ferroelectric capacitor.

[0055] For example, in some examples, as shown in Figures 3a and 3b, the first electrode 121 can be coupled to the vertical transistor 110 through the contact pad 115. For example, the first electrode 121 is coupled to the first source and drain of the vertical transistor 110. For example, the material of the contact pad 115 may include any suitable conductive material, such as titanium nitride (TiN), tantalum nitride (TaN), tungsten, metal silicide, doped polysilicon, or any combination thereof, etc. For example, the shape and structure of the contact pad 115 can be set as needed to match the arrangement of the multiple capacitors 120 in the memory array 105 (such as a square arrangement or a hexagonal close packing, etc.). It should be noted that in other examples, the contact pad 115 can be omitted, that is, the first electrode 121 can be directly coupled to the vertical transistor 110.

[0056] For example, as shown in Figures 2, 3a, and 3b, the first semiconductor structure 100 further includes a common electrode 124 and a common electrode contact plug 150. The common electrode 124 is electrically connected to the second electrodes 122 of the capacitors 120 in the plurality of memory arrays 105. That is, the plurality of memory arrays 105 share the same common electrode 100. The common electrode contact plug 150 and the vertical transistor 105 are disposed on the same side of the common electrode 124 in the first direction Z. The common electrode 124 is coupled to the peripheral circuit 205 (e.g., the ground terminal of the peripheral circuit 205) through the common electrode contact plug 150.

[0057] It should be noted that in related art memories, each memory array shares the same common electrode, and the common electrodes corresponding to different memory arrays are separated from each other, so that other functional devices (usually including passive devices, such as decoupling capacitors, etc.) can be arranged between adjacent memory arrays; however, such an arrangement limits the reduction of memory chip size. In the embodiment of the present disclosure, multiple memory arrays 105 share the same common electrode 100, and other functional devices (such as decoupling capacitors, etc.) can be arranged around the periphery of the multiple memory arrays 105, thereby reducing the spacing between adjacent memory arrays 105. Overall, the size of the first semiconductor structure 100 can be reduced, which in turn helps reduce the chip size of the memory 10.

[0058] For example, the material of the common electrode 124 may include any suitable conductive material, such as titanium nitride (TiN), tantalum nitride (TaN), tungsten, doped polysilicon, silicon germanium (SiGe), or any combination thereof, etc. For example, the material of the common electrode contact plug 150 may include any suitable conductive material, such as titanium nitride (TiN), tantalum nitride (TaN), tungsten, cobalt, metal silicide, or any combination thereof, etc.

[0059] For example, in some examples, as shown in Figures 3a and 3b , the second electrode 122 in each memory array 105 and the capacitor dielectric layer 123 in each memory array 105 are integrally formed. Furthermore, the second electrodes 122 in multiple memory arrays 105 and the capacitor dielectric layer 123 in multiple memory arrays 105 are integrally formed, thereby simplifying the manufacturing process of the first semiconductor structure 100. In other words, the second electrode 122 and the capacitor dielectric layer 123 can be shared by multiple memory arrays 105. In this case, as shown in Figures 3a and 3b , one end of the common electrode contact plug 150 penetrates the shared capacitor dielectric layer 123 to contact and connect with the shared second electrode 122, thereby achieving electrical connection between the common electrode contact plug 150 and the common electrode 124. It is understood that, based on the embodiments shown in Figures 3a and 3b , one end of the common electrode contact plug 150 can further penetrate the shared second electrode 122 to directly contact and connect with the common electrode 124. It is also understandable that in some examples, the second electrodes 122 in multiple memory arrays 105 may be separate from each other, so that one end of the common electrode contact plug 150 may pass through the shared capacitor dielectric layer 123 and directly contact and connect with the common electrode 124 .

[0060] For example, in some examples, as shown in Figures 3a and 3b, the common electrode 124 may include a plurality of first plate-shaped portions 124a corresponding one-to-one to the plurality of memory arrays 105 and a second plate-shaped portion 124b connecting the plurality of first plate-shaped portions 124a; the second plate-shaped portion 124b is disposed between adjacent memory arrays 105, and the second plate-shaped portion 124b is closer to the second semiconductor structure 200 than the plurality of first plate-shaped portions 124. For example, the orthographic projection of the second plate-shaped portion 124b along the first direction Z may be in a grid shape. It should be noted that in this disclosure, an orthographic projection along a certain direction refers to an orthographic projection within a virtual plane perpendicular to the direction.

[0061] For example, in some examples, as shown in Figures 3a and 3b, the common electrode 124 may also include an extension portion 124c extending along the first direction Z, the extension portion 124c is arranged on the side wall of the first electrode 121 and is connected to the corresponding first plate-shaped portion 124a, and the first plate-shaped portion 124a is connected to the second plate-shaped portion 124b through the extension portion 124c.

[0062] For example, in some examples, as shown in Figures 3a and 3b, a recess 124R is formed in the common electrode 124, the first plate-shaped portion 124a is located on both sides of the opening of the recess 124R, the second plate-shaped portion 124b is located at the bottom of the recess 124R, and the partially extended portion 124c is located on the sidewalls of the recess 124R. For example, in some examples, the first semiconductor structure may further include a planarization layer (not shown) disposed on a side of the common electrode 124 away from the second semiconductor structure 200 and filling the recess 124R.

[0063] For example, in some examples, as shown in Figures 3a and 3b, the plurality of first plate-shaped portions 124a, the second plate-shaped portions 124b, and the extension portion 124c can be integrally formed. For example, in some examples, as shown in Figures 2, 3a, and 3b, the orthographic projection of the common electrode along the first direction Z can be a closed figure (e.g., without a cavity and / or gap therein).

[0064] For example, in some examples, as shown in Figures 3a and 3b, the orthographic projection of the common electrode contact plug 150 along the first direction Z can be located within the orthographic projection of the second plate-shaped portion 124b along the first direction. That is, the common electrode contact plug 150 is coupled to the second plate-shaped portion 124b to achieve coupling with the common electrode 124, thereby shortening the transmission path of the common electrode contact plug 150 and reducing the transmission resistance of the common electrode contact plug 150. For example, in some examples, the first semiconductor structure 100 may include a plurality of common electrode contact plugs 150, wherein the orthographic projection of at least one common electrode contact plug 150 along the first direction Z is located within the orthographic projection of the second plate-shaped portion 124b along the first direction.

[0065] For example, as shown in Figures 2, 3a, and 3b, each memory array 105 may further include a plurality of word lines 130 extending along a second direction X and a plurality of bit lines 140 extending along a third direction Y. In each memory array 105, each word line 130 is coupled to a row of vertical transistors 110 arranged along the second direction X. For example, the word line 130 is coupled to the gate of the vertical transistor 110, or the gate of the vertical transistor 110 is part of the word line 130. Each bit line 140 is coupled to a column of vertical transistors 110 arranged along the third direction Y. For example, the bit line 140 is coupled to the second source and drain of the vertical transistor. For example, the second direction X is perpendicular to the first direction Z, and the third direction Y is perpendicular to the first direction Z. For example, the third direction Y intersects the second direction X. For example, the third direction Y may be perpendicular to the second direction X. It should be noted that in this disclosure, the definitions of row and column are relative and can be interchanged.

[0066] For example, the material of the word line 130 may include any suitable conductive material, such as titanium nitride (TiN), tantalum nitride (TaN), tungsten, metal silicide, doped polysilicon, or any combination thereof, etc. For example, the material of the bit line 140 may include any suitable conductive material, such as titanium nitride (TiN), tantalum nitride (TaN), tungsten, metal silicide, doped polysilicon, or any combination thereof, etc.

[0067] For example, as shown in Figures 2, 3a, and 3b, in each memory array 105, multiple word lines 130 may be arranged at intervals along the third direction Y, and multiple bit lines 140 may be arranged at intervals along the second direction X. The word lines 130 in adjacent memory arrays 105 may be arranged at intervals from each other, and the bit lines 140 in adjacent memory arrays 105 may be arranged at intervals from each other. In other words, two word lines 130 in adjacent memory arrays 105 that are located on the same straight line (e.g., a straight line extending along the second direction X) can each be independently controlled, and two bit lines 140 in adjacent memory arrays 105 that are located on the same straight line (e.g., a straight line extending along the third direction Y) can each be independently controlled.

[0068] 3a and 3b , the bit line 140 may be coupled to the vertical transistor via a bit line contact plug 116. The bit line contact plug 116 may be made of any suitable conductive material, such as titanium nitride (TiN), tantalum nitride (TaN), tungsten, metal silicide, doped polysilicon, or any combination thereof.

[0069] For example, as shown in Figures 2, 3a, and 3b, the first semiconductor structure may further include a plurality of first contact plugs 160 coupled in a one-to-one correspondence with the plurality of word lines 130 in each memory array 105, and a plurality of second contact plugs 170 coupled in a one-to-one correspondence with the plurality of bit lines 140 in each memory array 105. Each first contact plug 160 is disposed on a side of a corresponding word line 130 that is adjacent to the second semiconductor structure 200, and each second contact plug 170 is disposed on a side of a corresponding bit line 140 that is adjacent to the second semiconductor structure 200.

[0070] For example, in some examples, as shown in FIG2 , FIG3 a , and FIG3 b , in each memory array 105 , the first end of the odd-numbered word line 130 (e.g., the left end in FIG2 ) is coupled to the corresponding first contact plug 160, and the second end of the even-numbered word line 130 (e.g., the right end in FIG2 ) is coupled to the corresponding first contact plug 160; the first end of the odd-numbered bit line 140 (e.g., the lower end in FIG2 ) is coupled to the corresponding second contact plug 170, and the second end of the even-numbered bit line 140 (e.g., the upper end in FIG2 ) is coupled to the corresponding second contact plug 170. Thus, during the manufacturing process, the process window of the first contact plug 160 and the second contact plug 170 can be increased.

[0071] For example, in some examples, the first contact plug 160 , the second contact plug 170 , and the common electrode contact plug 150 may be formed simultaneously, that is, the three may have substantially the same structure and material composition.

[0072] For example, in some examples, as shown in FIG2 , FIG3 a , and FIG3 b , the orthographic projection of the common electrode contact plug 150 along the first direction Z is located in a region defined by four adjacent vertex corners of the orthographic projections of four adjacent memory arrays 105 along the first direction Z. Thus, the common electrode contact plug 150 can be configured to have a larger cross-sectional area, which helps to reduce the transmission resistance of the common electrode contact plug 150 .

[0073] For example, in some examples, as shown in Figures 2, 3a and 3b, the area of ​​the orthographic projection of the common electrode contact plug 150 along the first direction Z can be larger than the area of ​​the orthographic projection of the first contact plug 160 along the first direction Z, and can also be larger than the area of ​​the orthographic projection of the second contact plug 170 along the first direction Z.

[0074] For example, in some examples, as shown in Figures 3a and 3b, the first semiconductor structure 100 may further include a first interconnect layer 180, which is disposed on a side of the plurality of memory arrays 105 that is proximate to the second semiconductor structure 200 in the first direction Z. The second semiconductor structure 200 may further include a second interconnect layer 220, which is disposed on a side of the peripheral circuit 205 that is proximate to the first semiconductor structure in the first direction Z. The memory 10 may further include a bonding interface 300 disposed between the first interconnect layer 180 and the second interconnect layer 220. For example, the first interconnect layer 180 and the second interconnect layer 220 are bonded via the bonding interface 300 to achieve bonding between the first semiconductor structure 100 and the second semiconductor structure 200. For example, hybrid bonding technology may be used to achieve the above bonding.

[0075] For example, in some examples, as shown in Figures 3a and 3b, the first interconnect layer 180 may include multiple levels of first interconnect lines 181, first interconnect vias 182 disposed between adjacent levels of the first interconnect lines 181, and multiple first bonding pads 183. Similarly, the second interconnect layer 220 may include multiple levels of second interconnect lines 221, second interconnect vias 222 disposed between adjacent levels of the second interconnect lines 221, and multiple second bonding pads 223. The multiple first bonding pads 183 and the multiple second bonding pads 223 are bonded to each other via the bonding interface 300. For example, each of the common electrode contact plug 150, the first contact plug 160, and the second contact plug 170 is coupled to the peripheral circuit 205 via the first interconnect line 181, the first interconnect via 182, the first bonding pad 183, the second bonding pad 223, the second interconnect via 222, and the second interconnect line 221.

[0076] For example, in some examples, as shown in Figures 3a and 3b, the second semiconductor structure 200 may include a semiconductor substrate 201, and the peripheral circuit 205 may include a plurality of transistors 210 at least partially disposed in the semiconductor substrate 201, for implementing the structure and function of control circuits such as a word line driver (e.g., a sub-word line driver) and a sense amplifier (SA). For example, as shown in Figures 3a and 3b, the transistor 210 may include an active region 211 located in the substrate, a gate 212 disposed on the active region 211, and a gate dielectric layer 213 located between the active region 211 and the gate 212. The semiconductor substrate 201 may include a trench isolation structure 207 defining each active region 211. For example, the material of the semiconductor substrate 201 may include any suitable semiconductor material, such as silicon, germanium, gallium arsenide, an oxide semiconductor material, etc. For example, the material of the gate 212 may include any suitable conductive material, such as titanium nitride (TiN), tantalum nitride (TaN), tungsten, metal silicide, doped polysilicon, or any combination thereof, etc. For example, the material of the gate dielectric layer 213 may include any suitable dielectric material, such as silicon oxide, silicon nitride, a high-K dielectric material, or any combination thereof. It should be noted that the transistor 210 in the drawings is exemplary, and the embodiments of the present disclosure do not limit the structure of the transistor 210. For example, the transistor 210 may be a planar transistor (as shown in the drawings) or a fin-type transistor (FinFET).

[0077] For example, in some examples, as shown in FIG. 3 a and FIG. 3 b , the second semiconductor structure may further include a plurality of third contact plugs 230 disposed between the peripheral circuit 205 and the second interconnect layer 220 for achieving coupling between the peripheral circuit 205 and the second interconnect layer 220 .

[0078] For example, in some examples, as shown in Figures 3a and 3b, the second semiconductor structure 200 may further include a third interconnect layer 280. The third interconnect layer 280 is disposed on a side of the peripheral circuit 205 away from the first semiconductor structure 100. The third interconnect layer 280 is used to couple the peripheral circuit 205 with an external circuit. For example, as shown in Figures 3a and 3b, the peripheral circuit 205 and the second interconnect layer 220 are disposed on a first side (e.g., the front side) of the semiconductor substrate 201, and the third interconnect layer 280 is disposed on a second side (e.g., the back side) of the semiconductor substrate 201.

[0079] For example, in some examples, as shown in FIG. 3 a and FIG. 3 b , the third interconnect layer 280 may include multiple levels of third interconnect lines 281 , third interconnect vias 282 disposed between adjacent levels of the third interconnect lines 281 , and multiple lead pads 283 .

[0080] For example, in some examples, as shown in Figures 3a and 3b, the second semiconductor structure may further include a plurality of fourth contact plugs 250 penetrating the semiconductor substrate 201 to achieve coupling between the second interconnect layer 220 and the third interconnect layer 280. It will be appreciated that an isolation layer (not shown) may be provided between the fourth contact plugs 250 and the semiconductor substrate 201 to achieve electrical insulation between the fourth contact plugs 250 and the semiconductor substrate 201.

[0081] For example, in some examples, as shown in Figures 3a and 3b, the peripheral circuit 205 is coupled to the external circuit through the third contact plug 230, the second interconnection layer 220 (for example, the second interconnection line 221 therein, or the second interconnection line 221 and the second interconnection via 222 therein), the fourth contact plug 250, and the third interconnection layer 280 (for example, the third interconnection line 281, the third interconnection via 282 and the lead-out pad 283 therein).

[0082] FIG4 is a schematic diagram of a planar structure of an interconnect provided by some embodiments of the present disclosure. For example, as shown in FIG4 , a first interconnect 181 is coupled to a first contact plug 160 (or a second contact plug 170) and a first interconnect via 182 located on either side thereof, respectively. The width of the first interconnect 181 has a local maximum at the junction with the first contact plug 160 (or the second contact plug 170) and the first interconnect via 182, thereby facilitating increased contact area and reduced contact resistance. As shown in FIG4 , the first interconnect 181 extends along a third direction E1. The width of the first interconnect 181 refers to the dimension of the first interconnect 181 in a third direction E2 perpendicular to the third direction E1. The local maximum refers to the width of the first interconnect 181 at a certain segment being greater than the width at other adjacent segments (which may not be all of the remaining segments, for example, may be portions of segments on either side of the segment). For example, the third direction E1 and the fourth direction E2 are both parallel to the plane defined by the second direction X and the third direction Y. The third direction E1 may be parallel to the second direction X or the third direction Y, or may intersect both. It should be noted that although FIG4 uses the first interconnect line 181, the first contact plug 160 (or the second contact plug 170), and the first interconnect via 182 as an example, the remaining interconnect lines and the contact plugs / interconnect vias on both sides thereof may also be arranged with reference to FIG4.

[0083] In the present disclosure, the interconnect layers (e.g., first interconnect layer 180, second interconnect layer 220, and third interconnect layer 280) may include one or more interlayer dielectric layers, and interconnect lines (e.g., first interconnect line 181, second interconnect line 221, and third interconnect line 281), interconnect vias (e.g., first interconnect via 182, second interconnect via 222, and third interconnect via 282), pads (e.g., first bonding pad 183, second bonding pad 223, and lead pad 283), etc. may be formed in the one or more interlayer dielectric layers. For example, the materials of the interconnect lines and interconnect vias may include any suitable conductive material, such as titanium nitride (TiN), tantalum nitride (TaN), tungsten, aluminum, cobalt, copper, metal silicide, doped polysilicon, or any combination thereof. For example, the material of the pads may include any suitable conductive material, including, but not limited to, copper. The materials of the interlayer dielectric layers may include, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-K dielectric materials, or any combination thereof, etc.

[0084] It should be noted that the structure of the capacitor 120 in the drawings of the present disclosure is exemplary, and the embodiments of the present disclosure do not limit the structure of the capacitor 120, as long as the arrangement of the first electrode 121, the second electrode 122 and the capacitor dielectric layer 123 can form the capacitor 120. For example, the first electrode 121 can be columnar (as shown in the drawings), or it can be plate-shaped or U-shaped, or it can be any other suitable shape; the second electrode 122 conformally covers the sidewalls and / or top surface of the first electrode 121, and the capacitor dielectric layer 123 is located between the first electrode 121 and the second electrode 122. For example, in some examples, in the first semiconductor structure 100, one or more support layers for supporting the first electrode can be provided, and the support layer is in a grid shape, and the capacitor dielectric layer 123 and the second electrode 122 can partially cover the support layer.

[0085] Figure 5a is a schematic diagram of a partial cross-sectional structure of a memory provided by other embodiments of the present disclosure, taken along line A1A2 in Figure 2 . Figure 5b is a schematic diagram of a partial cross-sectional structure of a memory provided by other embodiments of the present disclosure, taken along line B1B2 in Figure 2 . It should be noted that, compared to Figures 3a and 3b , for the sake of simplicity, Figures 5a and 5b only illustrate a portion of the structure of the memory. Structures not shown in Figures 5a and 5b may refer to the corresponding structures in Figures 3a and 3b .

[0086] The main difference between the memory device in the embodiment shown in Figures 5a and 5b and the memory device in the embodiment shown in Figures 3a and 3b is that, in the embodiment shown in Figures 5a and 5b, the second electrode 122 in each memory array 105 is integrally formed, and the capacitor dielectric layer 123 in each memory array 105 is integrally formed. Furthermore, the second electrodes 122 in multiple memory arrays 105 are integrally formed, but the capacitor dielectric layers 123 in multiple memory arrays 105 are separate. In this case, as shown in Figures 5a and 5b, one end of the common electrode contact plug 150 can directly contact and connect with the shared second electrode 122 without penetrating the capacitor dielectric layer 123. It is understood that, based on the embodiment shown in Figures 5a and 5b, one end of the common electrode contact plug 150 can penetrate the shared second electrode 122 to directly contact and connect with the common electrode 124. It is also understood that, in some examples, the second electrodes 122 in multiple memory arrays 105 can be separate, so that one end of the common electrode contact plug 150 can directly contact and connect with the common electrode 124.

[0087] The remaining structural features of the memory in the embodiment shown in FIG. 5 a and FIG. 5 b may refer to the related description of FIG. 3 a and FIG. 3 b above, and will not be repeated here.

[0088] Figure 6a is a schematic diagram of a partial cross-sectional structure of a memory device according to further embodiments of the present disclosure, taken along line A1A2 in Figure 2 . Figure 6b is a schematic diagram of a partial cross-sectional structure of a memory device according to further embodiments of the present disclosure, taken along line B1B2 in Figure 2 . It should be noted that, similar to Figures 5a and 5b , for the sake of simplicity, Figures 6a and 6b only illustrate a portion of the memory device structure. For structures not shown in Figures 6a and 6b , reference can be made to the corresponding structures in Figures 3a and 3b .

[0089] The main difference between the memory in the embodiment shown in Figures 6a and 6b and the memory in the embodiment shown in Figures 5a and 5b is that in the memory in the embodiment shown in Figures 6a and 6b, the second electrode 122 and the common electrode 124 are integrally formed, thereby simplifying the process steps. In other words, the second electrode 122 and the common electrode 124 form an integral structure, and the two are not strictly distinguished or are both considered to be part of the overall structure. For example, in some examples, the second electrode 122 and the common electrode 124 in the embodiment shown in Figures 3a and 3b can also be regarded as an integral structure, that is, the overall structure can be a multi-layer structure, and does not necessarily have to be a single-layer structure.

[0090] The remaining structural features of the memory in the embodiment shown in FIG. 6 a and FIG. 6 b may refer to the related description of FIG. 3 a and FIG. 3 b , and will not be repeated here.

[0091] For example, in some embodiments, the memory 10 may include multiple memory banks, each of which includes multiple memory arrays (i.e., multiple memory arrays 105). The multiple memory arrays in each memory bank share the same common electrode (i.e., common electrode 124), i.e., each memory bank corresponds to a common electrode; the common electrodes corresponding to different memory banks are separate. For example, passive devices may be provided between adjacent memory banks; for example, passive devices include, but are not limited to, decoupling capacitors.

[0092] For example, the memory 10 may be a dynamic random access memory (DRAM) or a ferroelectric random access memory (Fe-RAM), but is not limited thereto.

[0093] It should be noted that, for the sake of clarity and conciseness, most of the insulating layers and / or dielectric layers in the first semiconductor structure and the second semiconductor structure are omitted in the drawings, for example, the filling layer and support layer mentioned above are omitted.

[0094] At least some embodiments of the present disclosure further provide a method for manufacturing a memory device, which can be used to manufacture the memory device described in the aforementioned embodiments. FIG. 7 is a flow chart illustrating a method for manufacturing a memory device provided in some embodiments of the present disclosure. For example, as shown in FIG. 7 , the method may include the following steps S100 to S300 .

[0095] S100: Provide a first semiconductor structure, wherein the first semiconductor structure includes a plurality of memory arrays arranged in an array and spaced apart from each other, each memory array in the plurality of memory arrays includes a plurality of memory cells arranged in an array, each memory cell in the plurality of memory cells includes a vertical transistor extending along a first direction and a capacitor coupled to the vertical transistor, the capacitor includes a first electrode and a second electrode opposite to each other, the first electrode is coupled to the vertical transistor, the first semiconductor structure further includes a common electrode and a common electrode contact plug, the common electrode is electrically connected to the second electrode of the capacitor in the plurality of memory arrays, and the common electrode contact plug and the vertical transistor are arranged on the same side of the common electrode in the first direction.

[0096] For example, in some examples, taking the first semiconductor structure 100 shown in Figures 2, 3a and 3b as an example, providing the first semiconductor structure may include: forming a vertical transistor 110, a word line 130, a contact pad 115, a capacitor 120 and a common electrode 124 on a first surface (such as the front surface) of a substrate; thinning or removing the substrate from a second surface (such as the back surface) of the substrate, and forming a bit line 140, a common electrode contact plug 150, a first contact plug 160, a second contact plug 170, and a first interconnection layer 180.

[0097] S200: providing a second semiconductor structure, wherein the second semiconductor structure includes a peripheral circuit.

[0098] For example, in some examples, taking the second semiconductor structure 200 shown in Figures 2, 3a and 3b as an example, providing the second semiconductor structure may include: forming a peripheral circuit 205 (as shown in the transistor 210 in the figure), a third contact plug 230 and a second interconnect layer 220 on a first surface (such as the front surface) of a semiconductor substrate 201; thinning the semiconductor substrate 201 from the second surface (such as the back surface) of the semiconductor substrate 201, and forming a fourth contact plug 250 and a third interconnect layer 280.

[0099] S300: Bonding the first semiconductor structure to the second semiconductor structure so that the common electrode is coupled to the peripheral circuit through the common electrode contact plug, wherein the second semiconductor structure is arranged on a side of the vertical transistor away from the capacitor in the first direction.

[0100] For example, a hybrid bonding technique may be used to bond the first semiconductor structure to the second semiconductor structure.

[0101] For example, in some examples, taking the memory 10 shown in Figures 2, 3a and 3b as an example, bonding the first semiconductor structure 100 to the second semiconductor structure 200 may include: bonding the first interconnect layer 180 and the second interconnect layer 220 to achieve bonding between the first semiconductor structure 100 and the second semiconductor structure 200, wherein the bonding interface 300 is located between the first interconnect layer 180 and the second interconnect layer 220.

[0102] It should be noted that one or more steps of the above-mentioned manufacturing method may include multiple sub-steps, and these sub-steps may be executed sequentially or in parallel according to actual needs; in addition, according to actual needs, the sub-steps in different steps may be executed sequentially, in parallel or alternately.

[0103] For example, in some embodiments, a first semiconductor structure may be provided first; then, an initial second semiconductor structure may be provided, i.e., a peripheral circuit 205 (as shown by the transistor 210 in the figure), a third contact plug 230, and a second interconnection layer 220 may be formed on a first surface (e.g., the front surface) of a semiconductor substrate 201; the first semiconductor structure may be bonded to the initial second semiconductor structure; finally, the semiconductor substrate 201 of the initial second semiconductor structure may be thinned from the second surface (e.g., the back surface) of the semiconductor substrate 201, and a fourth contact plug 250 and a third interconnection layer 280 may be formed.

[0104] For more details and technical effects of the manufacturing method provided by the embodiments of the present disclosure, reference can be made to the relevant description in the above-mentioned memory embodiments, which will not be repeated here.

[0105] At least some embodiments of the present disclosure further provide an electronic device. FIG8 is a block diagram of the structure of an electronic device provided by some embodiments of the present disclosure. As shown in FIG8 , the electronic device 1 includes a processor 20 and the memory 10 of the aforementioned embodiment, wherein the memory 10 is coupled to the processor 20.

[0106] For example, the processor 20 may include, but is not limited to, a central processing unit (CPU), a graphics processing unit (GPU), etc. The memory 10 may be configured to store data to be processed by the processor 20 and / or data processed by the processor.

[0107] For example, the electronic device 1 includes but is not limited to mobile phones, tablet computers, smart bracelets, wearable electronic devices, virtual reality devices, augmented reality devices, vehicle-mounted devices, servers, workstations, etc.

[0108] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A memory (10), comprising: A first semiconductor structure (100) includes a plurality of memory arrays (105) arranged in an array and spaced apart from each other, wherein each of the plurality of memory arrays includes a plurality of memory cells arranged in an array, each of the plurality of memory cells includes a vertical transistor (110) extending along a first direction (Z) and a capacitor (120) coupled to the vertical transistor, the capacitor including a first electrode (121) and a second electrode (122) opposite to each other, the first electrode being coupled to the vertical transistor. a second semiconductor structure (200), comprising a peripheral circuit (205), bonded to the first semiconductor structure, wherein the second semiconductor structure is arranged on a side of the vertical transistor away from the capacitor in the first direction; The first semiconductor structure further includes a common electrode (124) and a common electrode contact plug (150), wherein the common electrode is electrically connected to the second electrodes of the capacitors in the plurality of storage arrays, the common electrode contact plug and the vertical transistor are arranged on the same side of the common electrode in the first direction, and the common electrode is coupled to the peripheral circuit through the common electrode contact plug.

2. The memory according to claim 1, wherein The common electrode includes a plurality of first plate-shaped portions (124a) corresponding one-to-one to the plurality of storage arrays and a second plate-shaped portion (124b) connected to the plurality of first plate-shaped portions, wherein the second plate-shaped portion is arranged between adjacent storage arrays and is closer to the second semiconductor structure than the plurality of first plate-shaped portions.

3. The memory according to claim 2, wherein An orthographic projection of the common electrode contact plug along the first direction is located within an orthographic projection of the second plate-shaped portion along the first direction.

4. The memory according to claim 2 or 3, wherein: The common electrode further includes an extension portion (124c) extending along the first direction, the extension portion is arranged on the side wall of the first electrode and connected to the corresponding first plate-shaped portion, and the first plate-shaped portion is connected to the second plate-shaped portion through the extension portion.

5. The memory according to claim 2 or 3, wherein: The plurality of first plate-shaped portions and the second plate-shaped portion are integrally formed.

6. The memory according to any one of claims 1 to 5, wherein: The orthographic projection of the common electrode contact plug along the first direction is located in a region defined by four adjacent vertex corners of the orthographic projections of four adjacent memory arrays along the first direction.

7. The memory according to any one of claims 1 to 6, wherein: The capacitor further comprises a capacitor dielectric layer (123) arranged between the first electrode and the second electrode. The capacitor dielectric layers in the plurality of storage arrays are integrally formed. The common electrode contact plug penetrates the capacitor dielectric layer and is coupled to the common electrode.

8. The memory according to any one of claims 1 to 6, wherein: The capacitor further includes a capacitor dielectric layer disposed between the first electrode and the second electrode. The capacitor dielectric layer in each storage array is integrally formed, and the capacitor dielectric layers in the multiple storage arrays are separate from each other.

9. The memory according to any one of claims 1 to 8, wherein: The second electrodes in each memory array are integrally formed, and the second electrodes in the plurality of memory arrays are integrally formed or separated from each other.

10. The memory according to any one of claims 1 to 8, wherein: The second electrodes in the plurality of storage arrays are integrally formed with the common electrode.

11. The memory according to any one of claims 1 to 10, wherein: Each memory array further includes a plurality of word lines (130) extending along a second direction (X) and a plurality of bit lines (140) extending along a third direction (Y). In each of the memory arrays, each of the plurality of word lines is coupled to a row of the vertical transistors arranged along the second direction, and each of the plurality of bit lines is coupled to a column of the vertical transistors arranged along the third direction. The second direction is perpendicular to the first direction, the third direction is perpendicular to the first direction, and the third direction intersects with the second direction.

12. The memory according to claim 11, wherein The word lines in adjacent memory arrays are arranged at intervals from each other, and the bit lines in adjacent memory arrays are arranged at intervals from each other.

13. The memory according to claim 11 or 12, wherein: The first semiconductor structure further includes: a plurality of first contact plugs (160) coupled to the plurality of word lines in each memory array in a one-to-one correspondence, each of the plurality of first contact plugs being arranged on a side of the corresponding word line close to the second semiconductor structure; A plurality of second contact plugs (170) are coupled one-to-one with the plurality of bit lines in each memory array, and each second contact plug in the plurality of second contact plugs is arranged on a side of the corresponding bit line close to the second semiconductor structure.

14. The memory according to any one of claims 1 to 13, wherein: The first semiconductor structure further comprises a first interconnection layer (180), the first interconnection layer being arranged on a side of the plurality of memory arrays close to the second semiconductor structure in the first direction; The second semiconductor structure further comprises a second interconnect layer (220), which is arranged on the peripheral circuit a side of the road close to the first semiconductor structure in the first direction; The memory further includes a bonding interface (300) disposed between the first interconnect layer and the second interconnect layer.

15. The memory according to any one of claims 1 to 14, wherein: The second semiconductor structure further comprises a third interconnection layer (280), which is arranged on a side of the peripheral circuit away from the first semiconductor structure, and is used for coupling the peripheral circuit with an external circuit.

16. An electronic device (1), comprising: Processor (20); as well as The memory (10) according to any one of claims 1 to 13, wherein the memory is coupled to the processor.

17. A method for manufacturing a memory, comprising: A first semiconductor structure is provided, wherein the first semiconductor structure includes a plurality of memory arrays arranged in an array and spaced apart from each other, each memory array in the plurality of memory arrays includes a plurality of memory cells arranged in an array, each memory cell in the plurality of memory cells includes a vertical transistor extending along a first direction and a capacitor coupled to the vertical transistor, the capacitor including a first electrode and a second electrode opposite to each other, the first electrode being coupled to the vertical transistor, the first semiconductor structure further including a common electrode and a common electrode contact plug, the common electrode being electrically connected to the second electrode of the capacitors in the plurality of memory arrays, the common electrode contact plug and the vertical transistor being disposed on the same side of the common electrode in the first direction; Providing a second semiconductor structure, wherein the second semiconductor structure includes a peripheral circuit; The first semiconductor structure and the second semiconductor structure are bonded to each other so that the common electrode is coupled to the peripheral circuit through the common electrode contact plug, wherein the second semiconductor structure is disposed on a side of the vertical transistor away from the capacitor in the first direction.

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