Storage device, and semiconductor structure and manufacturing method therefor

Abstract

Disclosed are a semiconductor structure and a manufacturing method therefor. The semiconductor structure comprises: a substrate, wherein the substrate comprises a plurality of active structures arranged at intervals in a first direction and a second direction, each active structure comprises a first active portion and a second active portion, the substrate has a first surface, and the second active portion extends towards the first surface along the first active portion, and has a first end surface in the direction facing the first surface; contact structures, wherein the contact structures are located on the first end surfaces of the second active portions; and a barrier layer, which is located on the first surface and covers parts of the side walls of the second active portions and parts of the side walls of the contact structures.

Description

Memory device, semiconductor structure and manufacturing method thereof

[0001] Cross-references

[0002] This disclosure claims priority to Chinese patent application number 202410398933.4, filed on April 3, 2024, entitled “Memory device, semiconductor structure and manufacturing method thereof”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The embodiments of the present disclosure relate to the field of semiconductors, and in particular to a memory device, a semiconductor structure, and a method thereof. Background Art

[0004] Memory is a component used to store programs and various data. Random Access Memory (RAM) commonly used in computer systems can be divided into two types: Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM). DRAM is a commonly used semiconductor memory device in computers, consisting of many repeated memory cells.

[0005] A memory cell typically includes a capacitor and a transistor. The drain of the transistor is connected to a bit line structure, and the source is connected to a capacitor. The capacitor includes a capacitor contact structure and a capacitor. The word line structure of the memory cell can control the opening or closing of the channel region of the transistor, thereby reading the data information stored in the capacitor through the bit line structure, or writing the data information into the capacitor for storage through the bit line structure.

[0006] With the rapid development of semiconductor manufacturing technology, semiconductor devices are developing towards higher component density and higher integration. The semiconductor process nodes are continuously decreasing in accordance with the development trend of Moore's Law. It is currently necessary to propose a new memory device, semiconductor structure and its manufacturing method. Summary of the Invention

[0007] According to some embodiments of the present disclosure, one aspect of the present disclosure provides a semiconductor structure, including:

[0008] A substrate comprising a plurality of active structures spaced apart along a first direction and a second direction, wherein the active structures comprise a first active portion and a second active portion;

[0009] The substrate includes a first surface, the second active portion extends along the first active portion toward the first surface, and has a first end surface in a direction toward the first surface;

[0010] a contact structure, the contact structure being located on the first end surface of the second active portion;

[0011] A barrier layer is located on the first surface and covers a portion of a sidewall of the second active portion and a portion of a sidewall of the contact structure.

[0012] In some embodiments, the barrier layer includes a first barrier layer and a second barrier layer, the first barrier layer covers a portion of the side wall of the second active portion and a portion of the side wall of the contact structure, the second barrier layer covers a portion of the first barrier layer, and the etching selectivity ratio of the first barrier layer and the second barrier layer is different.

[0013] In some embodiments, the semiconductor structure further includes a plurality of capacitor structures, which are disposed on the substrate and electrically connected to the active structure through the contact structure.

[0014] In some embodiments, the capacitor structure includes a support layer and a dielectric layer on the support layer, and the support layer is disposed on the second barrier layer.

[0015] In some embodiments, a distance between top surfaces of the support layers of adjacent capacitor structures is greater than a width of the contact structure along the first direction.

[0016] In some embodiments, the support layer and the first barrier layer have different etching selectivities.

[0017] In some embodiments, the support layer and the second barrier layer are made of the same material.

[0018] In some embodiments, the substrate further includes: a second surface, the second end surface of the first active portion being exposed to the second surface of the substrate; a word line, the word line being arranged around the active structure and partially overlapping with the first active portion; a bit line, the bit line being located on the second surface of the substrate, the bit line being electrically connected to the active structure through the second end surface of the first active portion; and a bonding layer, the bonding layer being located on the second surface and connected to the word line, the bit line and the capacitor structure through a bonding structure.

[0019] According to some embodiments of the present disclosure, on the other hand, embodiments of the present disclosure further provide a method for manufacturing a semiconductor structure, comprising: providing a substrate; forming a plurality of active structures arranged at intervals along a first direction and a second direction in the substrate, the active structure comprising a first active portion and a second active portion; the substrate comprising a first surface, the second active portion extending along the first active portion toward the first surface and exposed to the first surface; forming a barrier layer circumferentially around the second active portion, the barrier layer being located on the first surface and exposing the first end face of the second active portion; forming a contact structure, the contact structure being located at the first end face of the second active portion, the barrier layer covering a portion of the side wall of the second active portion and a portion of the side wall of the contact structure.

[0020] In some embodiments, the process steps for forming a plurality of active structures spaced apart along a first direction and a second direction in the substrate include: providing a base; etching the base to form a plurality of through holes spaced apart along a first direction and a second direction and an initial active structure adjacent to the through holes; filling a portion of the through holes to form an isolation layer, wherein the isolation layer exposes a portion of the initial active structure; forming a protective layer, wherein the protective layer covers the initial active structure exposed by the isolation layer; using the protective layer as a mask, etching away a portion of the isolation layer and a portion of the initial active structure to form a first trench, wherein the remaining portion of the isolation layer and a portion of the initial active structure constitute the isolation structure and the active structure, respectively.

[0021] In some embodiments, a barrier layer is formed circumferentially around the second active portion, the barrier layer being located on the first surface and exposing the first end face of the second active portion. The process steps include: depositing a gate oxide layer in the first trench, the gate oxide layer covering a portion of the sidewalls of the active structure; forming a gate conductive layer on the surface of the isolation structure and the side faces of the gate oxide layer, the gate oxide layer and the gate conductive layer together forming a word line, the surface of the word line is flush with the bottom surface of the protective layer, and the sidewalls of the protective layer and the surface of the word line together forming a second trench; filling the second trench to form an insulating layer, the insulating layer covering the word line, etching back the insulating layer until the second active portion is exposed, the second active portion and the insulating layer together forming a third trench; forming a barrier layer in the third trench, the barrier layer including a first barrier layer and a second barrier layer, the first barrier layer covering a portion of the sidewalls of the second active portion and a portion of the contact structure, the second barrier layer covering a portion of the first barrier layer, the first barrier layer and the second barrier layer having different etching selectivities; etching the barrier layer to expose the first end face of the second active portion.

[0022] In some embodiments, the process steps for forming a contact structure, wherein the contact structure is located on the first end surface of the second active portion, include: depositing a metal layer, wherein the metal layer covers the barrier layer and the first end surface of the second active portion; performing high-temperature treatment on the metal layer, and removing the metal layer covering the barrier layer, and retaining the metal layer on the first end surface to form the contact structure.

[0023] In some embodiments, the method further includes: forming a capacitor structure, the capacitor structure including a support layer and a dielectric layer formed on the support layer, the support layer being formed on the second barrier layer, and the spacing between the top surfaces of the support layers of adjacent capacitor structures is greater than the width of the contact structure along the first direction; forming a bit line, the substrate further including a second surface, the bit line being formed on the second surface of the substrate, the second end surface of the first active portion being exposed to the second surface, and the bit line being electrically connected to the active structure through the second end surface of the first active portion; forming a bonding layer, the bonding layer being located on the second surface and connected to the word line, the bit line and the capacitor structure through a bonding structure.

[0024] In some embodiments, the supporting layer and the first barrier layer have different etching selectivities, or the supporting layer and the second barrier layer are made of the same material.

[0025] According to some embodiments of the present disclosure, a third aspect of the embodiments of the present disclosure further provides a storage device, which is formed by bonding the semiconductor structure and the bonding wafer; the bonding wafer includes a control circuit and a bonding interface, and the storage device is bonded to the bonding interface of the bonding wafer through the bonding layer of the semiconductor structure.

[0026] The technical solution provided by the embodiments of the present disclosure has at least the following advantages: a plurality of active structures are arranged at intervals along the first direction and the second direction on the substrate, and a contact structure is provided on the first end face of the second active portion. By providing a blocking layer on the side walls of part of the second active portion and part of the contact structure, the subsequent process of forming the capacitor structure can be prevented from affecting the active structure, and a short circuit between the capacitor structure and the active structure can be avoided. In addition, by providing the blocking layer, the difficulty of the process of forming the capacitor structure is reduced, thereby improving the yield of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0028] FIG1 is a schematic diagram of a semiconductor structure in an embodiment of the present disclosure.

[0029] FIG. 2 is a top view of the semiconductor structure shown in FIG. 1 .

[0030] FIG3 is a flowchart of a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure.

[0031] 4 to 14 are schematic structural diagrams along the AA′ direction of the semiconductor structure corresponding to each step of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure.

[0032] FIG. 15 is a schematic diagram of a semiconductor structure including a capacitor structure along the AA′ direction according to an embodiment of the present disclosure.

[0033] 16-17 are structural schematic diagrams along the AA′ direction corresponding to the step of forming a bit line in a semiconductor structure manufacturing method provided by an embodiment of the present disclosure.

[0034] FIG18 is a top view of the structural schematic diagram corresponding to FIG17 after the bit lines are formed.

[0035] FIG19 is a schematic diagram of a semiconductor structure including a bonding layer along the AA′ direction according to an embodiment of the present disclosure.

[0036] FIG. 20 is a schematic diagram showing the process steps for forming a memory device by bonding. DETAILED DESCRIPTION

[0037] The following describes various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present disclosure to facilitate a better understanding of the present disclosure. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can still be implemented.

[0038] The present disclosure does not limit the type of transistors. The vertical gate-all-around (VGAA) transistor will be used as an example for introduction below. The vertical gate-all-around transistor can be applied to logic devices and driving transistors of memory devices such as DRAM (Dynamic Random Access Memory) and MRAM (Magnetic Random Access Memory), but the present disclosure is not limited to this. The memory includes a plurality of memory cells distributed in an array, each memory cell includes a vertical gate-all-around transistor, a capacitor contact structure connected to the source of the vertical gate-all-around transistor, a word line connected to the gate, and a bit line connected to the drain. The capacitor contact structure and the capacitor structure are formed on the substrate in sequence. In the vertical gate-all-around transistor, it is difficult to realize the process of forming a capacitor structure with a certain height in a direction perpendicular to the substrate and electrically connecting it to the transistor through the capacitor contact structure. In particular, due to the small size of the capacitor contact structure, when the capacitor structure is formed, it is easy to cause the transistor and the capacitor structure to be short-circuited.

[0039] In order to solve the above technical problems, an embodiment of the present disclosure provides a semiconductor structure, which will be described below with reference to the accompanying drawings.

[0040] FIG1 is a schematic diagram of a semiconductor structure according to an embodiment of the present disclosure; FIG2 is a top view of the semiconductor structure shown in FIG1 . Referring to FIG1 and FIG2 , the semiconductor structure 10 provided by the embodiment of the present disclosure includes: a substrate 100 including a plurality of active structures 107 spaced apart along a first direction X and a second direction Y, the active structures 107 including a first active portion 1072 and a second active portion 1071; the substrate 100 including a first surface S1, the second active portion 1071 extending along the first active portion 1072 toward the first surface S1 and having a first end surface L1 in a direction toward the first surface S1; a contact structure 115 located at the first end surface L1 of the second active portion 1071; and a barrier layer 113 located on the first surface S1 and covering a portion of the sidewalls of the second active portion 1071 and a portion of the sidewalls of the contact structure 115. These structures will be described in detail below with reference to the accompanying drawings.

[0041] Continuing with reference to Figures 1 and 2, the substrate 100 includes a plurality of active structures 107 spaced apart along a first direction X and a second direction Y. The first direction X and the second direction Y may be the row direction and the column direction, respectively, within a plane parallel to the substrate 100 as shown in Figure 1. The third direction Z may be the direction from the top surface of the substrate 100 to the bottom surface of the substrate 100 as shown in Figure 1. The X, Y, and Z directions are mutually perpendicular. The substrate 100 may further include a base 101. Exemplarily, a first surface S1 is a plane of the substrate 100 extending along the first direction X and the second direction Y and facing away from the base 101. The second active portion 1071 extends along the first active portion 1072 toward the first surface S1 and has a first end surface L1 in a direction toward the first surface S1. That is, the first surface S1 exposes the first end surface L1 of the second active portion 1071. The first end surface L1 of the second active portion 1071 may be a source or a drain.

[0042] The contact structure 115 is located on the first end surface L1 of the second active portion 1071. The multiple contact structures 115 correspond to the multiple active structures 107 arranged at intervals along the first direction X and the second direction Y. Each contact structure 115 is electrically connected to the active structure 107 through the first end surface L1 of the second active portion 1071, that is, the source or drain.

[0043] 1 , barrier layer 113 is located on first surface S1 and covers a portion of the sidewalls of second active portion 1071 and a portion of the sidewalls of contact structure 115. Providing barrier layer 113 on a portion of the sidewalls of second active portion 1071 and a portion of the sidewalls of contact structure 115 prevents subsequent processes for forming the capacitor structure from affecting active structure 107, thereby preventing short circuits between the capacitor structure and active structure 107.

[0044] In some embodiments, the barrier layer 113 may include a first barrier layer 1131 and a second barrier layer 1132, wherein the first barrier layer 1131 covers a portion of the sidewall of the second active portion 1071 and a portion of the sidewall of the contact structure 115, and the second barrier layer 1132 covers a portion of the first barrier layer 1131. For example, the top surfaces of the first barrier layer 1131 and the second barrier layer 1132 may be flush, which helps ensure that the contact structure 115 is accurately formed on the first end surface L1 of the second active portion 1071.

[0045] In some embodiments, as shown in Figure 11, the contact structure 115 also covers a portion of the top surface of the first barrier layer 1131. The contact structure 115 extends in a direction parallel to the second barrier layer 1132 and covers a portion of the top surface of the first barrier layer 1131, effectively increasing the surface area of ​​the contact structure 115. After the capacitor structure is subsequently formed, the contact area between the capacitor structure and the contact structure 115 can be effectively increased, which is beneficial to reducing the contact resistance.

[0046] In some embodiments, the etching selectivity ratios of the first barrier layer 1131 and the second barrier layer 1132 are different. For example, the material of the first barrier layer 1131 may be silicon oxide, and the material of the second barrier layer 1132 may be silicon nitride. The two materials are different, and the selectivity ratios are different during the etching process. During the subsequent capacitor process, the first barrier layer 1131 can be completely retained, thereby effectively preventing the substrate 100 from being over-etched, resulting in a short circuit between the capacitor structure and the active structure 107.

[0047] In some embodiments, referring to Figures 14 and 15, the semiconductor structure 10 further includes a plurality of capacitor structures 117, which are disposed on the substrate 100 and electrically connected to the active structure 107 via the contact structure 115. The capacitor structures 117 include a lower electrode 1172 and an upper electrode 1174. Each capacitor structure 117 is electrically connected to the active structure 107 via the lower electrode 1172. The lower electrode 1172 and the upper electrode 1174 may be made of the same material, and the material of both the lower electrode 1172 and the upper electrode 1174 may be at least one of platinum nickel, titanium, tantalum, cobalt, polysilicon, copper, tungsten, tantalum nitride, titanium nitride, or ruthenium. In other embodiments, the material of the lower electrode layer and the material of the upper electrode layer may also be different.

[0048] Capacitor structure 117 further includes a support layer 1171 and a dielectric layer 1173 located on support layer 1171. In some embodiments, dielectric layer 1173 may be made of a high dielectric constant material such as silicon oxide, tantalum oxide, hafnium oxide, zirconium oxide, niobium oxide, titanium oxide, barium oxide, strontium oxide, yttrium oxide, lanthanum oxide, praseodymium oxide, or barium strontium titanate. Support layer 1171 is disposed on second barrier layer 1132. The material of support layer 1171 may be at least one of silicon nitride or silicon carbonitride. The high hardness of support layer 1171 facilitates supporting capacitor structure 117 and prevents collapse of capacitor structure 117. In some embodiments, the etching selectivity ratio of the supporting layer 1171 and the first barrier layer 1131 is different, or the material of the supporting layer 1171 and the second barrier layer 1132 is the same. When etching the supporting layer to form the capacitor structure 117, the first barrier layer 1131 can be ensured not to be etched, thereby ensuring that the substrate 100 is not over-etched, and further avoiding short circuit between the capacitor structure 117 and the active structure 107.

[0049] In some embodiments, referring to Figures 11 and 13, the spacing d2 between the top surfaces of the support layers 1171 of adjacent capacitor structures 117 can be greater than the width d1 of the contact structure 115 along the first direction, thereby ensuring that the contact structure 115 can be fully exposed to the support layer and ensuring the contact area between the lower electrode 1172 and the contact structure 115.

[0050] In some embodiments, referring to Figure 16, the substrate 100 may further include: a second surface S2, the second end surface L2 of the first active portion 1072 is exposed to the second surface S2; a word line 109, the word line 109 is arranged around the active structure 107, and partially overlaps with the first active portion 1072; a bit line 118, the bit line 118 is located on the second surface S2 of the substrate 100, and the bit line 118 is electrically connected to the active structure 107 through the second end surface L2 of the first active portion 1072; a bonding layer L3, the bonding layer L3 is located on the second surface S2, and is connected to the word line 109, the bit line 118 and the capacitor structure 117 through the bonding structure 120, which will be specifically explained in conjunction with the drawings.

[0051] As shown in FIG16 , the substrate 100 further includes a second surface S2, and the second end surface L2 of the first active portion 1072 is exposed to the second surface S2. For example, the active structure 107 includes a source, a drain, and a channel region. The source or the drain may be located at the second end surface L2 of the first active portion 1072 facing the second surface S2 and the first end surface L1 of the second active portion 1071 facing the first surface S1, respectively. The channel region is located between the source and the drain.

[0052] Continuing with reference to Figures 15 and 16, substrate 100 may further include a plurality of discrete word lines 109, each extending along a second direction Y. Word lines 109 include: a gate oxide layer 1091, which is disposed circumferentially within the channel region of active structure 107 and covers the sidewall surfaces of the channel region of active structure 107; and a gate conductive layer 1092, which is disposed surrounding the channel region and located on the corresponding sidewall surfaces of gate oxide layer 1091 within the channel region. The channel region is disposed between the source and drain of active structure 107. For each word line 109, word line 109 surrounds the channel region of at least one active structure 107 and partially overlaps with first active portion 1072. Exemplarily, gate conductive layer 1092 may be made of at least one metal or metal compound such as tungsten or titanium nitride, and gate oxide layer 1091 may be made of silicon oxide.

[0053] In some embodiments, as shown in Figures 16 and 17, a plurality of discrete bit lines 118 are further disposed on the second surface S2 of the substrate 100. Each bit line 118 extends along a first direction X. The bit lines 118 are formed from a conductive layer. Exemplarily, the conductive layer may include a metal or metal compound, such as at least one of cobalt, nickel, molybdenum, titanium, tungsten, tantalum, or platinum, or at least one of cobalt silicide, nickel silicide, molybdenum silicide, titanium silicide, tungsten silicide, tantalum silicide, or platinum silicide. The second end surface L2 of the first active portion 1072 may be a source or drain. Each bit line 118 is electrically connected to the active structure 107 via the first end surface L2 of the first active portion 1072, i.e., the source or drain. Figure 18 is a top view of the semiconductor structure after the bit lines 118 are formed. As shown in Figure 18, the bit lines BL, i.e., the bit lines 118, are spaced apart along the first direction X, and the word lines WL, i.e., the word lines 109, are spaced apart along the second direction Y.

[0054] In some embodiments, as shown in FIG16 , the bonding layer L3 is located on the second surface S2 of the substrate 100 and is connected to the word lines 109, the bit lines 118, and the capacitor structure 117 via a bonding structure 120. Referring to FIG19 , the bonding structure 120 is composed of a metal wiring layer 1201, a barrier layer 1202, an insulating layer 1203, and a passivation layer 124. The metal wiring layer 1201 on the surface of the bonding layer L3 serves as a bonding pad, which can be used to bond to a bonding wafer when a memory device is subsequently formed.

[0055] In summary, by providing a barrier layer 113 on the sidewalls of part of the second active portion 1071 and part of the sidewalls of the contact structure 115 , the subsequent process of forming the capacitor structure can be prevented from affecting the active structure 107 and a short circuit between the capacitor structure and the active structure 107 can be avoided. In addition, by setting the barrier layer 113 to include a first barrier layer 1131 and a second barrier layer 1132, the first barrier layer 1131 covers a portion of the side wall of the second active portion 1071 and a portion of the side wall of the contact structure 115, the second barrier layer 1132 covers a portion of the first barrier layer 1131, and the top surfaces of the first barrier layer 1131 and the second barrier layer 1132 are flush, which is conducive to ensuring that the contact structure 115 is accurately formed on the first end surface L1 of the second active portion 1071; and the etching selectivity ratios of the first barrier layer 1131 and the second barrier layer 1132 are different. Therefore, when performing the subsequent capacitor process, the first barrier layer 1131 can be completely retained, thereby ensuring that the substrate 100 is not over-etched, and avoiding short circuit between the capacitor structure 117 and the active structure 107.

[0056] Accordingly, another embodiment of the present invention provides a method for manufacturing a semiconductor structure, which can be used to form the above-mentioned semiconductor structure.

[0057] Figure 3 is a step flow chart of a semiconductor structure manufacturing method provided by an embodiment of the present disclosure, and Figures 4-14 and 16-19 are schematic diagrams of the cross-sectional structures along the AA' direction corresponding to each step in the semiconductor structure manufacturing method provided by another embodiment of the present disclosure. The manufacturing method of the semiconductor structure provided by this embodiment will be described in detail in conjunction with the accompanying drawings. The parts that are the same as or corresponding to the above embodiments will not be described in detail below.

[0058] Step S100 provides a substrate 100;

[0059] In step S200, a plurality of active structures 107 are formed in the substrate 100 and arranged in a first direction X and a second direction Y. The active structures 107 include a first active portion 1072 and a second active portion 1071. The substrate 100 includes a first surface S1. The second active portion 1071 extends along the first active portion 1072 toward the first surface S1 and is exposed to the first surface S1.

[0060] In some embodiments, referring to Figures 4-6, a substrate 101 is provided, wherein the material of the substrate 101 can be single crystal silicon (Si), single crystal germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); it can also be silicon on insulator (SOI), germanium on insulator (GOI); or it can also be other materials, such as III-V Group compounds such as gallium arsenide.

[0061] The substrate 101 is etched to form a plurality of through-holes 104 spaced apart along a first direction X and a second direction Y, and an initial active structure 103 adjacent to the through-holes 104. The initial active structure 103 includes a source / drain region, a channel region, and a source / drain region sequentially arranged along a third direction Z. The source region, the channel region, and the drain region are doped with the same ion type, for example, all N-type or P-type dopant ions. A portion of the through-holes 104 is filled to form an isolation layer 102, which exposes a portion of the initial active structure 103. The isolation layer 102 may be made of an insulating material, such as silicon oxide.

[0062] A protective layer 105 is formed, and the protective layer 105 covers the initial active structure 103 exposed by the isolation layer 102; using the protective layer 105 as a mask, a portion of the isolation layer 102 and a portion of the initial active structure 103 are etched away to form a first trench 108, and the remaining portion of the initial active structure 103 constitutes an active structure 107, and the remaining isolation layer 102 constitutes an isolation structure 106. As shown in FIG6 , during the etching process, the formation of the protective layer 105 ensures that the end face and a portion of the side wall of the initial active structure 103 are not etched, thereby ensuring the integrity of the active structure 107.

[0063] In step S300 , a barrier layer 113 is formed circumferentially around the second active portion 1071 . The barrier layer 113 is located on the first surface S1 and exposes the first end surface L1 of the second active portion 1071 .

[0064] In some embodiments, referring to Figures 6-9 , after forming the active structure 107, a gate oxide layer 1091 may be deposited within the first trench 108 and then patterned to form a gate oxide layer 1091 covering a portion of the sidewalls of the active structure 107. The gate oxide layer 1091 may be a high-K dielectric layer, such as silicon oxide, to improve the performance of the semiconductor structure. In other embodiments of the present disclosure, the gate oxide layer 1091 may also be formed directly on the side surfaces of the active structure 107.

[0065] A gate conductive layer 1092 is formed on the surface of the isolation structure 106 facing away from the substrate 101 and on the side of the gate oxide layer 1091. The gate oxide layer 1091 and the gate conductive layer 1092 together constitute a word line 109. The surface of the word line 109 is flush with the bottom surface of the protective layer 105. The sidewall of the protective layer 105 and the surface of the word line 109 together constitute a second trench 110. The surface of the word line 109 is the surface facing away from the substrate 101, and the bottom surface of the protective layer 105 is the bottom surface facing the substrate 101.

[0066] Specifically, a gate conductive layer 1092 is formed on the surface of the isolation structure 106 facing away from the substrate 101 and on the side of the gate oxide layer 1091 by a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, or a metal organic chemical vapor deposition (MOCVD) process. The material of the gate conductive layer 1092 can be polysilicon, TiN, TaN, Al, W, Cu, etc. The gate conductive layer 1092 can be flush with the channel region of the active structure 107 and extend along the second direction Y.

[0067] Second trench 110 is filled to form insulating layer 111. Insulating layer 111 covers word line 109. Insulating layer 111 is then etched back until second active portion 1071 is exposed. Second active portion 1071 and insulating layer 111 together form third trench 112. The insulating layer may be made of silicon nitride. Base 101, isolation structure 106, word line 109, active structure 107, and insulating layer 111 together form substrate 100, as shown in FIG8 .

[0068] A barrier layer 113 is formed in the third trench 112. The barrier layer 113 may include a first barrier layer 1131 and a second barrier layer 1132. The barrier layer 113 is etched to expose the first end surface L1 of the second active portion 1071. The first end surface L1 may be the source or drain of the active structure 107. The remaining barrier layer 113 covers a portion of the sidewall of the active structure 107. That is, the first barrier layer 1131 covers a portion of the sidewall of the second active portion 1071, and the second barrier layer 1132 covers a portion of the first barrier layer 1131. The first barrier layer 1131 and the second barrier layer 1132 have different etching selectivities. For example, the material of the first barrier layer 1131 may be silicon oxide, and the material of the second barrier layer 1132 may be silicon nitride. The selectivity of silicon oxide to silicon nitride is 1:20.

[0069] In step S400 , a contact structure 115 is formed. The contact structure 115 is located on the first end surface L1 of the second active portion 1071 . The barrier layer 113 covers a portion of the sidewall of the second active portion 1071 and a portion of the sidewall of the contact structure 115 .

[0070] Specifically, in some embodiments, referring to Figures 10 and 11 , a metal layer 114 is first deposited. The metal layer 114 covers the barrier layer 113 and the first end surface L1 of the second active portion 1071. For example, a sputtering process can be used to form the metal on the surface of the first end surface L1 of the second active portion 1071. The metal layer 114 is then subjected to a high-temperature treatment. During the high-temperature annealing process, a metal silicide can form on the first end surface L1 of the second active portion 1071 due to a diffusion effect. The metal layer 114 covering the barrier layer 113 is then removed, leaving the metal layer 114 on the first end surface L1 to form the contact structure 115. After forming the contact structure 115, the metal layer 114 on the barrier layer 113 is further removed. The metal silicide can be at least one of cobalt silicide, nickel silicide, platinum silicide, or nickel platinum silicide.

[0071] As shown in the dotted line portion in FIG11 , when removing the metal layer 114 covering the barrier layer 113, only the metal layer 114 on the second barrier layer 1132 can be removed. The contact structure 115 finally formed can cover a portion of the top surface of the first barrier layer 1131. The contact structure 115 extends in a direction parallel to the second barrier layer 1132 and covers a portion of the top surface of the first barrier layer 1131, thereby effectively increasing the surface area of ​​the contact structure 115. After the capacitor structure 117 is subsequently formed, the contact area between the capacitor structure 117 and the contact structure 115 can be effectively increased, thereby facilitating reduction of contact resistance.

[0072] In some embodiments, as shown in Figures 11 to 15, the method for manufacturing the semiconductor structure 10 further includes forming a capacitor structure 117. The capacitor structure 117 includes a support layer 1171 and a dielectric layer 1173 formed on the support layer 1171, and the support layer 1171 is formed on the second barrier layer 1132. Exemplarily, the support layer 1171 and the sacrificial layer 117 are sequentially deposited on the contact structure 115 and the barrier layer 113, and the sacrificial layer 117 is formed on the support layer 1171. The deposition process includes but is not limited to CVD, PVD, ALD or MOCVD process; part of the sacrificial layer 117 and part of the support layer 118 are etched step by step to expose the contact structure 115. After etching, the sacrificial layer 117 and the support layer 1171 are arranged at intervals along the first direction X and the second direction Y. The etching process may include at least one of photolithography, wet etching or dry etching. The material of the sacrificial layer 117 may be low-k dielectric, borosilicate, borophosphosilicate glass, tetraethyl silicate, silicon oxide, etc., and the material of the supporting layer 1171 may be silicon nitride.

[0073] During the formation of the capacitor structure 117, when the support layer 1171 is etched downward along the third direction Z to expose the contact structure 115, the barrier layer 113 covers the substrate 100 and can effectively block further etching of the substrate 100 by the etchant during the etching process, thereby preventing the active structure 107 from being exposed to the substrate 100. In some embodiments, the support layer 1171 and the first barrier layer 1131 have different etching selectivities, or the support layer and the second barrier layer 1132 are made of the same material, for example, both are silicon nitride. After etching, the support layer 1171 is located on the second barrier layer 1132. Since the etching selectivity of the first barrier layer 1131 and the second barrier layer 1132 is different, the etching selectivity of the support layer 1171 and the first barrier layer 1131 is different, or the material of the support layer 1171 and the second barrier layer 1132 is the same, when the support layer 1171 is etched to expose the contact structure 115, the first barrier layer 1131 can be completely retained to prevent the substrate 100 from being over-etched, thereby protecting the active structure 107 from being exposed to the substrate 100, and further preventing the capacitor structure 117 and the active structure 107 from being short-circuited.

[0074] A lower electrode 1172 is deposited in the trench formed by the etched support layer 1171, the sacrificial layer 117, and the contact structure 115. The bottom of the lower electrode 1172 is electrically connected to the active structure 107 via the contact structure 115. A metal such as NiPt, Ti, Ta, W, Co, Ru, Cu, TaN, TiN, or polysilicon is formed as the lower electrode 1172 through a process such as CVD, PVD, ALD, or MOCVD. The sacrificial layer 117 is removed to expose at least the upper surface of the lower electrode 1172 facing away from the substrate 101. In this step, the surface of the support layer 1171 facing away from the substrate 101 is also exposed.

[0075] A dielectric layer 1173 is formed on the surface of the lower electrode 1172. In this step, the dielectric layer 1173 can be formed using a process such as CVD, PVD, ALD, or MOCVD. The dielectric layer 1173 not only covers the upper surface of the lower electrode 1172 but also covers the surface of the support layer 1171. The dielectric layer 1173 can be a high-K dielectric material.

[0076] An upper electrode 1174 is formed on the surface of the dielectric layer 1173. In this step, a metal such as NiPt, Ti, Ta, W, Co, Ru, Cu, TaN, TiN, or polysilicon is deposited on the surface of the dielectric layer 1173 as the upper electrode 1174, which covers the dielectric layer 1173. The support layer 1171, the lower electrode 1172, the dielectric layer 1173, and the upper electrode 1174 together constitute the capacitor structure 117. The spacing d2 between the top surfaces of the support layers 1171 of adjacent capacitor structures 117 is greater than the width d1 of the contact structure 115 along the first direction, thereby ensuring that the contact structure 115 is fully exposed to the support layer 1171 and the contact area between the lower electrode 1172 and the contact structure 115 is ensured.

[0077] As shown in Figures 14-19, the method for fabricating the semiconductor structure 10 further includes forming a bit line 118. The substrate 100 may further include a second surface S2. The bit line 118 is formed on the second surface S2 of the substrate 100 and extends along a first direction X. A plurality of bit lines 118 are spaced apart along a second direction Y. The second end surface L2 of the first active portion 1072 is exposed at the second surface S2. The bit line 118 is electrically connected to the active structure 107 via the second end surface L2 of the first active portion 1072. Exemplarily, the isolation structure 106 of the substrate 100 is etched along a third direction Z to expose the second end surface L2 of the first active portion 1072. The second end surface L2 of the first active portion is silicided to form the bit line 118. For example, metal ion deposition and high-temperature annealing are performed on the second end surface L2 of the first active portion to form the bit line 118. This metal silicide can be at least one of cobalt silicide, nickel silicide, platinum silicide, or nickel platinum silicide. As shown in FIG. 19 , in some embodiments, air gaps 120 may be formed at ends of the isolation structures 106 adjacent to the bit lines 118 and facing the second surface S2 to reduce coupling capacitance between adjacent bit lines 118 .

[0078] As shown in FIG19 , the method for manufacturing the semiconductor structure 10 further includes forming a bonding layer L3, which is located on the second surface S2 of the substrate 100 and is connected to the word line 109, the bit line 118, and the capacitor structure 117 through a bonding structure 120. For example, a barrier layer 122, a metal wiring layer 121, an insulating layer 124, and a passivation layer 124 are sequentially deposited on the second surface S2 of the substrate 100. The barrier layer 122, the metal wiring layer 121, the insulating layer 124, and the passivation layer 124 together constitute a bonding structure 120. The metal wiring layer 121 on the surface of the bonding layer L3 serves as a bonding pad, which can be used to bond to a bonding wafer when a memory device is subsequently formed.

[0079] This embodiment also provides a storage device, which is formed by bonding a semiconductor structure 10 and a bonding wafer 20. As shown in Figures 19 and 20, the bonding wafer 20 includes a control circuit and a bonding interface. The storage device is bonded to the bonding interface of the bonding wafer 20 through the bonding layer L3 of the semiconductor structure 10.

[0080] Those skilled in the art will appreciate that the above-described embodiments are specific examples for implementing the present disclosure, and in actual applications, various changes may be made to them in form and detail without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the embodiments of the present disclosure. Therefore, the scope of protection of the embodiments of the present disclosure shall be based on the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that include: A substrate (100), the substrate (100) comprising a plurality of active structures (107) spaced apart along a first direction (X) and a second direction (Y), the active structure (107) comprising a first active portion (1072) and a second active portion (1071); The substrate (100) includes a first surface (S1), the second active portion (1071) extends along the first active portion (1072) toward the first surface (S1), and has a first end surface (L1) in a direction toward the first surface (S1); a contact structure (115), the contact structure (115) being located on the first end surface (L1) of the second active portion (1071); A barrier layer (113) is located on the first surface (S1) and covers a portion of the sidewall of the second active portion (1071) and a portion of the sidewall of the contact structure (115).

2. The semiconductor structure according to claim 1, wherein: The barrier layer (113) includes a first barrier layer (1131) and a second barrier layer (1132), wherein the first barrier layer (1131) covers a portion of the side wall of the second active portion (1071) and a portion of the side wall of the contact structure (115), and the second barrier layer (1132) covers a portion of the first barrier layer (1131), and the first barrier layer (1131) and the second barrier layer (1132) have different etching selectivities.

3. The semiconductor structure according to claim 2, wherein: It also includes a plurality of capacitor structures (117), wherein the capacitor structures (117) are arranged on the substrate (100) and are electrically connected to the active structure (107) through the contact structure (115).

4. The semiconductor structure according to claim 3, wherein: The capacitor structure (117) comprises a support layer (1171) and a dielectric layer (1173) located on the support layer (1171), and the support layer (1171) is arranged on the second barrier layer (1132).

5. The semiconductor structure according to claim 4, wherein: The spacing between the top surfaces of the support layers (1171) of adjacent capacitor structures (117) is greater than the width of the contact structure (115) along the first direction. The semiconductor structure according to claim 4 , wherein: The support layer (1171) and the first barrier layer (1131) have different etching selectivities.

7. The semiconductor structure according to claim 4, wherein: The supporting layer (1171) is made of the same material as the second barrier layer (1132).

8. The semiconductor structure according to claim 3, wherein: The substrate (100) further comprises: a second surface (S2), wherein a second end surface (L2) of the first active portion (1072) is exposed to the second surface (S2) of the substrate (100); a word line (109), the word line (109) being arranged around the active structure (107) and partially overlapping with the first active portion (1072); a bit line (118), the bit line (118) being located on the second surface (S2) of the substrate (100), the bit line (118) being electrically connected to the active structure (107) through the second end surface (L2) of the first active portion (1072); A bonding layer (L3), the bonding layer (L3) is located on the second surface (S2) and is connected to the word line (109), the bit line (118) and the capacitor structure (117) through a bonding structure (120).

9. A method for manufacturing a semiconductor structure, characterized in that: include: providing a substrate (100); A plurality of active structures (107) are formed in the substrate (100) and are arranged at intervals along a first direction (X) and a second direction (Y), wherein the active structure (107) includes a first active portion (1072) and a second active portion (1071); The (100) includes a first surface (S1), and the second active portion (1071) extends along the first active portion (1072) toward the first surface (S1) and is exposed to the first surface (S1); forming a barrier layer (113) circumferentially around the second active portion (1071), wherein the barrier layer (113) is located on the first surface (S1) and exposes the first end surface (L1) of the second active portion (1071); A contact structure (115) is formed, wherein the contact structure (115) is located on the first end surface (L1) of the second active portion (1071), and the barrier layer (113) covers a portion of the side wall of the second active portion (1071) and a portion of the side wall of the contact structure (115).

10. The method for manufacturing a semiconductor structure according to claim 9, wherein: The process steps of forming a plurality of active structures (107) spaced apart along a first direction (X) and a second direction (Y) in the substrate (100) include: providing a substrate (101); Etching the substrate (101) to form a plurality of through holes (104) spaced apart along a first direction (X) and a second direction (Y) and an initial active structure (103) adjacent to the through holes (104); Filling a portion of the through hole (104) to form an isolation layer (102), wherein the isolation layer (102) exposes a portion of the initial active structure (103); A protective layer (105) is formed, wherein the protective layer (105) covers the initial active structure (103) exposed by the isolation layer (102); and a portion of the isolation layer (102) and a portion of the initial active structure (103) are etched away using the protective layer (105) as a mask to form a first trench (108), with the remaining portion of the isolation layer (102) and the remaining portion of the initial active structure (103) constituting the isolation structure (106) and the active structure (107), respectively.

11. The method for manufacturing a semiconductor structure according to claim 10, wherein: The process steps of forming a barrier layer (113) circumferentially around the second active portion (1071), wherein the barrier layer (113) is located on the first surface (S1) and exposes the first end surface (L1) of the second active portion (1071) include: Depositing a gate oxide layer (1091) in the first trench (108), wherein the gate oxide layer (1091) covers a portion of the sidewall of the active structure (107); A gate conductive layer (1092) is formed on the surface of the isolation structure (106) and on the side of the gate oxide layer (1091); the gate oxide layer (1091) and the gate conductive layer (1092) together constitute a word line (109); the surface of the word line (109) is flush with the bottom surface of the protection layer (105); and the sidewall of the protection layer (105) and the surface of the word line (109) together constitute a second trench (110); Filling the second trench (110) to form an insulating layer (111), the insulating layer (111) covering the word line (109), etching back the insulating layer (111) until the second active portion (1071) is exposed, the second active portion (1071) and the insulating layer (111) together forming a third trench (112); forming a barrier layer (113) in the third trench (112), the barrier layer (113) comprising a first barrier layer (1131) and a second barrier layer (1132), the first barrier layer (1131) covering a portion of the second active portion (1071) and a portion of the sidewall of the contact structure (115), the second barrier layer (1132) covering a portion of the first barrier layer (1131), and the first barrier layer (1131) and the second barrier layer (1132) having different etching selectivities; The barrier layer (113) is etched to expose the first end surface (L1) of the second active portion (1071).

12. The method for manufacturing a semiconductor structure according to claim 9, wherein: The process steps of forming a contact structure (115), wherein the contact structure (115) is located on the first end surface (L1) of the second active portion (1071), include: depositing a metal layer (114), wherein the metal layer (114) covers the barrier layer (113) and the first end surface (L1) of the second active portion (1071); The metal layer (114) is subjected to high-temperature treatment, and the metal layer (114) covering the barrier layer is removed, while the metal layer (114) on the first end surface is retained to form the contact structure (115).

13. The method for manufacturing a semiconductor structure according to claim 11, wherein: The method further comprises: forming a capacitor structure (117), the capacitor structure (117) comprising a support layer (1171) and a dielectric layer (1173) formed on the support layer (1171), the support layer (1171) being formed on the second barrier layer (1132), and a distance between top surfaces of the support layers (1171) of adjacent capacitor structures (117) being greater than a width of the contact structure (115) along a first direction (X); forming a bit line (118), the substrate (100) further comprising a second surface (S2), the bit line (118) being formed on the second surface (S2) of the substrate (100), the second end surface (L2) of the first active portion (1072) being exposed to the second surface (S2), and the bit line (118) being electrically connected to the active structure (103) via the second end surface (L2) of the first active portion (1072); A bonding layer (L3) is formed, the bonding layer (L3) being located on the second surface (S2) and connected to the word line (109), the bit line (118) and the capacitor structure (117) through a bonding structure (120).

14. The method for manufacturing a semiconductor structure according to claim 13, wherein: The support layer (1171) and the first barrier layer (1131) have different etching selectivities, or the support layer (1171) and the second barrier layer (1132) are made of the same material.

15. A memory device, characterized in that: The semiconductor structure according to any one of claims 1 to 8 is bonded to a bonding wafer (20); The bonding wafer (20) comprises a control circuit and a bonding interface, and the storage device is formed by bonding the bonding layer (L3) of the semiconductor structure to the bonding interface of the bonding wafer (20).

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