Manufacturing method for topcon battery having back se structure

Abstract

The present invention provides a manufacturing method for a TOPCon battery having a back SE structure. The method comprises forming a high-concentration thick-Poly structure in a metal region of an SE structure, and forming a low-concentration thin-Poly structure in a non-metal region. The present invention ensures both the thickness difference and the concentration difference of the structure manufactured by the present method; and the high-concentration thick-Poly metal region ensures contact performance of slurry, and the low-concentration thin-Poly structure in the non-metal region can reduce parasitic absorption and free carrier absorption, thus improving the short-circuit current.

Description

A method for manufacturing a back-side SE structure TOPCon battery Technical Field

[0001] The present invention relates to the field of photovoltaic technology, and in particular to a method for manufacturing a back-side SE structure TOPCon cell. Background Art

[0002] As the current mainstream battery, TOPCon batteries have been deployed by most manufacturers. According to statistics from professional institutions, as of 2023, the planned production capacity of domestic companies has reached 224GW, and will gradually replace PERC batteries in the future.

[0003] The existing TOPCon structure adopts a tunneling oxide structure on the back, that is, an ultra-thin tunneling oxide layer and a doped polysilicon layer are deposited on the back. The chemical passivation and multi-carrier tunneling effect of silicon oxide, as well as the field passivation of the doped polysilicon layer, are used to greatly reduce the surface recombination on the back and improve the conversion efficiency of the battery.

[0004] Although the TOPCon structure has very good passivation, the introduced doped polysilicon has very serious parasitic absorption of light. According to experimental data, the doped polysilicon on the back side can cause an absorption of about 0.004mA / cm² / nm. While 30nm of doped polysilicon can already meet the existing passivation requirements, it is limited by the current back side slurry. When the thickness is less than 80nm, the back side polysilicon layer will experience slurry burn-through, thus affecting the electrical performance. Summary of the Invention

[0005] The purpose of the present invention is to provide a method for manufacturing a back-side SE structure TOPCon battery. By forming high surface concentration + thick poly and low surface concentration + thin poly areas on the back side, this structure solves the slurry sintering problem in the metal area, while reducing the poly thickness and concentration in the non-metallic area, reducing parasitic absorption and free carrier absorption, and increasing the short-circuit current of the battery, thereby improving the battery conversion efficiency.

[0006] To achieve the above objectives, the present invention provides the following technical solutions:.

[0007] In a first aspect, the present invention provides a method for manufacturing a back-side SE structure TOPCon battery, comprising the following steps:

[0008] S1. Select an N-type silicon wafer and perform texturing on a texturing machine;

[0009] S2, diffusing boron on the silicon wafer after texturing;

[0010] S3, after the boron diffusion is completed, the BSG on the back and edge of the silicon wafer is removed, and then the back is alkaline polished while retaining the BSG on the front;

[0011] S4, depositing the following layers on the back side of the alkali-polished silicon wafer from bottom to top: a tunneling oxide layer, an intrinsic poly layer, an intermediate oxide layer, and a phosphorus-doped poly layer, wherein the thickness of the intrinsic poly layer is less than that of the phosphorus-doped poly layer;

[0012] S5, generating a patterned silicon oxide mask on the surface of the deposited silicon wafer;

[0013] S6. The silicon wafer with the silicon oxide mask is subjected to alkaline etching. In the area protected by the silicon oxide, the film layer below will not be corroded, while the area without silicon oxide protection will be corroded by the alkali in the alkaline solution. However, due to the presence of the intermediate oxide layer, the alkali will slow down or even stop the corrosion at the interface and will not continue to corrode the poly layer below. Therefore, there will be an etching time difference, which greatly increases the corrosion window and forms structures with different thicknesses, namely, phosphorus-doped poly layer + intrinsic poly layer, and a separate intrinsic poly layer area. At the same time, the silicon oxide in the protected area is removed in the subsequent HF bath;

[0014] S7. The etched silicon wafer is subjected to a high-temperature phosphorus diffusion process to crystallize and phosphorus diffuse the intrinsic poly layer on the back side and the phosphorus-doped poly layer at the same time. Since there is a phosphorus-doped poly layer in the protected area, in addition to the doping source introduced during the high-temperature phosphorus diffusion, it itself also serves as a doping source. The unprotected area has only one intrinsic poly layer and can only be doped by phosphorus diffusion, thus forming a staggered distribution of thick poly + high doping and thin poly + low doping;

[0015] S8, performing PSG etching on the front side of the silicon wafer after phosphorus diffusion, and then performing a de-coating process on the silicon wafer to remove the doped polysilicon layer coated on the front side;

[0016] S9, coating the silicon wafer after de-coating with silicon nitride + aluminum oxide on the front side, and coating the silicon nitride on the back side;

[0017] S10. Use screen printing to print silver-aluminum paste on the front side of the coated silicon wafer and silver paste on the back side to make a back-side SE structure TOPCon solar cell.

[0018] Preferably, in step S1, the silicon wafer parameters used are: thickness 160-180 um, resistivity 0.5-1.0 mΩ*cm; the texturing parameters are: reflectivity controlled at 9-11%, and weight loss controlled at 0.2-1 g.

[0019] Preferably, in step S2, the process parameters are: boron diffusion deposition temperature is 900-1050°C, diffusion time is 3h30min, and sheet resistance is 80-200ohm / sq.

[0020] Preferably, in step S4, a phosphorus-containing gas needs to be introduced into the phosphorus-doped poly layer during deposition to perform phosphorus doping to form an in-situ doped layer, and the thickness of the intrinsic poly layer is less than the thickness of the phosphorus-doped poly layer. More preferably, the phosphorus-containing gas is phosphine. The specific steps of step S4 are: in LPCVD, first pass 10000-100000sccm of oxygen, use normal pressure oxidation method, temperature 500-600℃, time 300-900s, first deposit a layer of ultra-thin tunneling oxide with a thickness of 1-2nm; then pass 300-2000sccm of silane, deposition temperature 550-650℃, deposition time 10-500s, pressure 200-500mTorr, and deposit a layer of 10-50 nm intrinsic poly layer; then 10000-100000sccm of oxygen is introduced to react with the previously deposited intrinsic poly layer to form a 1-2nm intermediate oxide layer; then 300-2000sccm of silane and 100-1000sccm of phosphine are introduced, the deposition temperature is 550-650℃, the deposition time is 500-1500s, the pressure is 200-500mTorr, and a 50-100nm in-situ phosphorus-doped poly layer is deposited.

[0021] Preferably, in step S5, the silicon oxide mask is formed by laser irradiation and heating, wherein the specific process is: coating a layer of TEOS solution on the surface of the silicon wafer, forming a thin film after drying, heating the surface of the film by laser, and the thin film in the heated area reacts to generate silicon oxide, wherein the laser is an infrared laser with a power of 5-30W, a repetition frequency of 120000KHZ, and a speed of 10000-40000mm / s.

[0022] Preferably, in step S9, the thicknesses of the front silicon nitride and aluminum oxide coatings are 70-90 nm and 3-10 nm respectively, and the thickness of the back silicon nitride coating is 80-90 nm.

[0023] In a second aspect, the present invention also provides a back-side SE structure TOPCon battery manufactured using the method described above.

[0024] Compared with the prior art, the present invention has the following beneficial effects: the method of the present invention realizes an SE structure with a high-concentration + thick poly metal area and a low-concentration + thin poly non-metal area on the back side by forming a protective layer for reverse etching of the metal area through mask + laser. This structure reduces parasitic absorption while meeting the sintering requirements of the thick poly on the back side. Compared with the traditional back-side Topcon passivation structure, the SE structure of the present invention adopts a high-concentration + thick poly structure in the metal area and a low-concentration + thin poly structure in the non-metal area, which not only ensures the thickness difference but also satisfies the concentration difference. The high-concentration metal area ensures the contact performance of the slurry, and the low-concentration and thin poly in the non-metal area can also reduce free carrier absorption and parasitic absorption, thereby improving the short-circuit current. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] FIG1 is a schematic diagram of a back-side SE structure TOPCon cell structure prepared by the method of the present invention.

[0026] In the figure: 1: front silicon nitride; 2: aluminum oxide; 3: P-type emitter; 4: N-type substrate; 5: tunneling oxide layer; 6: first phosphorus-doped poly layer; 7: middle oxide layer; 8: second phosphorus-doped poly layer; 9: back silicon nitride; 10: back electrode; 11: front electrode. DETAILED DESCRIPTION

[0027] The present invention aims to resolve the conflicting requirements of reducing the thickness of the back-side passivation structure of the cell while simultaneously meeting the requirements of reducing parasitic absorption and resisting burn-through. In an exemplary embodiment, our technical solution is to adopt an "SE" structure on the back side of the TOPCon cell. That is, a double-layer poly structure is deposited on the back side, and then a patterned area is formed by mask coating and laser heating. Then, a lightly and heavily doped structure is formed by reverse etching, forming the structure shown in Figure 1: the heavily doped area (metal area) is a tunneling oxide layer + a first phosphorus-doped poly layer + an intermediate oxide layer + a second phosphorus-doped poly layer, while the lightly doped area (non-metal area) is a tunneling oxide layer + a first phosphorus-doped poly layer, where the thickness of the first phosphorus-doped poly layer is less than that of the second phosphorus-doped poly layer, and the second phosphorus-doped poly layer is deposited by in-situ doping deposition.

[0028] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0029] In the description of the present invention, it should be noted that the terms "upper," "lower," "inner," "outer," "front end," "rear end," "both ends," "one end," "the other end," and the like, which indicate positions or relationships, are used solely to facilitate description and simplify the present invention. They are not intended to indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation, and therefore should not be construed as limiting the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0030] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "provided with," "connected," etc., should be understood in a broad sense. For example, "connected" may refer to a fixed connection, a detachable connection, or an integral connection; it may refer to a mechanical connection or an electrical connection; it may refer to a direct connection or an indirect connection through an intermediate medium; it may refer to internal communication between two components. Those skilled in the art will be able to understand the specific meanings of the above terms in the present invention based on the specific circumstances. Example

[0031] In an exemplary embodiment, a method for preparing a rear-side SE structure TOPCon cell is as follows.

[0032] Step 1: Select an N-type silicon wafer with a thickness of 160-180um and a resistivity of 0.5-1.0mΩ*cm. Then, use a tank-type alkaline texturing process to control the reflectivity at 9-11% and the weight loss at 0.2-1g.

[0033] Step 2: Diffusion of boron is performed on the silicon wafers after step 1 in a back-to-back manner, with a deposition temperature of 900-1050° C., a diffusion time of 3 h 30 min, and a sheet resistance of 80-200 ohm / sq.

[0034] Step 3: Use chain HF to remove BSG on the back and edge of the silicon wafer after step 2, and then polish the back using tank alkaline polishing while retaining BSG on the front.

[0035] Step 4: Use LPCVD to deposit a tunnel oxide layer and multiple amorphous silicon layers on the back of the silicon wafer after step 3. First, pass 10,000-100,000 sccm of oxygen and use atmospheric pressure oxidation at a temperature of 500-600°C for 300-900 seconds to deposit an ultra-thin tunnel oxide layer with a thickness of 1-2nm; then pass 300-2000 sccm of silane at a deposition temperature of 550-650°C for 10-500 seconds at a pressure of 200-500mTorr. Deposit a 10-50nm intrinsic poly layer; then introduce 10,000-100,000sccm of oxygen to react with the previously deposited intrinsic poly layer to form a 1-2nm intermediate oxide layer, and then introduce 300-2000sccm of silane and 100-1000sccm of phosphine. The deposition temperature is 550-650℃, the deposition time is 500-1500s, and the pressure is 200-500mTorr to deposit a 50-100nm in-situ phosphorus-doped poly layer.

[0036] Step 5: Coat the surface of the silicon wafer after step 4 with a layer of TEOS (tetraethoxysilane) solution, and form a thin film after drying. Use laser to heat the surface of the film. The film in the heated area will react to generate silicon oxide. The laser is an infrared laser with a power of 5-30W, a repetition frequency of 120,000KHZ, and a speed of 10,000-40,000mm / s. Since it only acts on the thin film, no additional laser damage will be caused to the poly below the film.

[0037] Step 6. Etch the silicon wafer after step 5 using a tank-type alkaline polishing machine. The laser area is protected by silicon oxide, and the poly layer below will not be corroded. The non-laser area will be corroded by alkali in the alkaline solution because it has no silicon oxide protection. However, due to the presence of the intermediate oxide layer, the alkali will slow down or even stop the corrosion at the interface and will not continue to corrode the poly layer below, greatly increasing the corrosion window and forming structures with different thicknesses. At the same time, the silicon oxide in the laser area is removed in the subsequent HF tank.

[0038] Step 7: The silicon wafer after step 6 is subjected to a high-temperature phosphorus expansion process using a phosphorus expansion tube to dope and crystallize the intrinsic poly layer and phosphorus-doped poly layer on the back. Since there is an in-situ doped poly layer in the laser area, during the high-temperature phosphorus expansion, in addition to the phosphorus oxychloride introduced into the furnace tube, it can also be used as a doping source. After alkali etching, the non-laser area has only one intrinsic poly layer, which can only be doped by phosphorus expansion. Therefore, a staggered distribution of thick poly + high doping and thin poly + low doping can be formed.

[0039] Step 8: After the silicon wafer is processed in step 7, the PSG formed on the front side is etched using chain HF, and then the silicon wafer is subjected to a de-plating process to remove the doped polysilicon layer plated on the front side.

[0040] Step 9: Coat the front side of the silicon wafer after step 8 with silicon nitride and aluminum oxide, with thicknesses of 70-90nm and 3-10nm respectively; and coat the back side with silicon nitride, with a thickness of 80-90nm;

[0041] Step 10: Use screen printing to print silver-aluminum paste on the front side of the silicon wafer after step 9, and silver paste on the back side.

[0042] Anything not described in detail in the present invention is a well-known technology to those skilled in the art. It should be understood that the specific details in the above steps are only for illustration, and these technical details can be easily replaced after understanding the principles of the present invention. Therefore, the above specific step details should not limit the scope of protection of the present invention, and the final scope of protection should be based on the claims. For example, in a specific embodiment, the method for forming a mask on a silicon wafer is by laser heating, but people in the industry can easily think of using other methods to form a mask based on the principles of the present method, such as coating, printing, etching, deposition, etc., as long as it can achieve the formation of a silicon oxide mask on the silicon wafer to protect the underlying poly layer, so these alternative methods should also be protected.

[0043] Finally, it should be noted that the above specific implementation methods are only used to illustrate the technical solutions of the present invention and are not limiting. Although the present invention has been described in detail with reference to the embodiments, those skilled in the art should understand that the technical solutions of the present invention can be modified and replaced with equivalents without departing from the spirit and scope of the technical solutions of the present invention, which should all be included in the scope of the claims of the present invention.

Claims

1. A method for manufacturing a back-side SE structure TOPCon battery, characterized in that: The method comprises the following steps: S1. Select an N-type silicon wafer and perform texturing on it; S2, diffusing boron into the silicon wafer after texturing; S3, after the boron diffusion is completed, the BSG on the back and edge of the silicon wafer is removed, and then the back is alkaline polished, while the BSG on the front is retained; S4. Depositing the following layers on the back side of the alkali-polished silicon wafer from bottom to top: a tunneling oxide layer, an intrinsic poly layer, an intermediate oxide layer, and a phosphorus-doped poly layer. During the deposition of the phosphorus-doped poly layer, a phosphorus-containing gas is introduced to perform phosphorus doping to form an in-situ doped layer. The thickness of the intrinsic poly layer is smaller than that of the phosphorus-doped poly layer. S5, generating a patterned silicon oxide mask on the surface of the deposited silicon wafer; S6. The silicon wafer with the silicon oxide mask is subjected to alkaline etching. In the area protected by silicon oxide, the film layer below will not be corroded, while the area without silicon oxide protection will be corroded by the alkali in the alkaline solution. However, due to the presence of the intermediate oxide layer, the alkali will slow down or even stop the corrosion at the interface and will not continue to corrode the poly below. Therefore, there will be an etching time difference, which greatly increases the corrosion window and forms structures with different thicknesses, namely, phosphorus-doped poly layer + intrinsic poly layer, and a separate intrinsic poly layer area. At the same time, the silicon oxide in the protected area is removed in the subsequent HF bath; S7. The etched silicon wafer is subjected to a high-temperature phosphorus diffusion process to crystallize and phosphorus diffuse the intrinsic poly layer on the back side and the phosphorus-doped poly layer at the same time. Since there is a phosphorus-doped poly layer in the protected area, in addition to the doping source introduced during the high-temperature phosphorus diffusion, it itself also serves as a doping source. The unprotected area has only one intrinsic poly layer and can only be doped by phosphorus diffusion, thus forming a staggered distribution of thick poly + high doping and thin poly + low doping; S8, performing PSG etching on the front side of the silicon wafer after phosphorus diffusion, and then performing a de-coating process on the silicon wafer to remove the doped polysilicon layer coated on the front side; S9, coating the silicon wafer after de-coating with silicon nitride + aluminum oxide on the front side, and coating the silicon nitride on the back side; S10. Use screen printing to print silver-aluminum paste on the front side of the coated silicon wafer and silver paste on the back side to make a back-side SE structure TOPCon solar cell.

2. The method for manufacturing a back-side SE structure TOPCon battery according to claim 1, wherein: In step S1 , the silicon wafer parameters used are: thickness 160-180 μm, resistivity 0.5-1.0 mΩ*cm; the texturing parameters are: reflectivity controlled at 9-11%, and weight loss controlled at 0.2-1 g.

3. The method for manufacturing a back-side SE structure TOPCon battery according to claim 1, wherein: In step S2 , the process parameters are: boron diffusion deposition temperature of 900-1050° C., diffusion time of 3 h 30 min, and sheet resistance of 80-200 ohm / sq.

4. The method for manufacturing a back-side SE structure TOPCon battery according to claim 1, wherein: In step S4, the phosphorus-containing gas is phosphine.

5. The method for manufacturing a back-side SE structure TOPCon battery according to claim 4, wherein: The specific steps of step S4 are as follows: in LPCVD, first pass 10000-100000sccm of oxygen, use atmospheric pressure oxidation method, temperature 500-600℃, time 300-900s, first deposit a layer of ultra-thin tunneling oxide with a thickness of 1-2nm; then pass 300-2000sccm of silane, deposition temperature 550-650℃, deposition time 10-500s, pressure 200-500mTorr, deposit a layer of 10-50nm intrinsic poly layer, which is an intrinsic poly layer; then 10000-100000sccm of oxygen is introduced to react with the previously deposited intrinsic poly layer to form a 1-2nm intermediate oxide layer; then 300-2000sccm of silane and 100-1000sccm of phosphine are introduced, the deposition temperature is 550-650℃, the deposition time is 500-1500s, the pressure is 200-500mTorr, and a 50-100nm phosphorus-doped poly layer is deposited, that is, the phosphorus-doped poly layer.

6. The method for manufacturing a back-side SE structure TOPCon battery according to claim 1, wherein: In step S5, the silicon oxide mask is formed by laser irradiation and heating, wherein the specific process is: a layer of TEOS solution is coated on the surface of the silicon wafer, and a thin film is formed after drying, and the surface of the thin film is heated by laser, and the thin film in the heated area reacts to generate silicon oxide, wherein the laser is an infrared laser with a power of 5-30W, a repetition frequency of 120,000KHZ, and a speed of 10,000-40,000mm / s.

7. The method for manufacturing a back-side SE structure TOPCon battery according to claim 1, wherein: In step S9, the thicknesses of the front silicon nitride and aluminum oxide coatings are 70-90 nm and 3-10 nm respectively, and the thickness of the back silicon nitride coating is 80-90 nm.

8. A back-side SE structure TOPCon battery, manufactured by the method according to any one of claims 1 to 7.

Images