Arithmetic device and tensor update method

Abstract

This arithmetic device is configured so as to comprise a contraction unit (1) that expresses a tensor of rank L (where L is an integer equal to or greater than 2) as the product of a plurality of minor tensors, each of which has a smaller number of elements than the number of elements in the tensor of rank L, and performs a contraction process on the plurality of minor tensors to acquire factor information present among the plurality of minor tensors.

Description

Arithmetic device and tensor update method

[0001] The present disclosure relates to a computing device and a tensor update method.

[0002] There is a computing device that expresses an L-th order tensor (L is an integer equal to or greater than 2) as the product of multiple tensors (hereinafter referred to as "small tensors") having fewer elements than the number of elements of the L-th order tensor, and performs a contraction process on a tensor group including the multiple small tensors to incorporate factor information. As an example of such a computing device, Non-Patent Document 1 discloses a computing device that performs a contraction process in which all factor information that exists other than between two small tensors included in a tensor group is moved to between the two small tensors, and then the factor information that exists between the two small tensors is incorporated into the two small tensors.

[0003] U. Schollwock, "The density-matrix renormalization group in the age of matrix product states," posted August 20, 2010, arXiv:1008.3477v2

[0004] The arithmetic device disclosed in Non-Patent Document 1 has a problem in that it takes a long arithmetic processing time to move all factor information that exists other than between the two small tensors included in the tensor group to between the two small tensors before performing the contraction processing.

[0005] The present disclosure has been made to solve the above-mentioned problems, and aims to obtain a calculation device that can reduce calculation processing time compared to the calculation device disclosed in Non-Patent Document 1.

[0006] The arithmetic device according to the present disclosure is equipped with a contraction unit that represents an L-th order (L is an integer equal to or greater than 2) tensor as a product of multiple small tensors, which are tensors having fewer elements than the number of elements of the L-th order tensor, and performs a contraction process on the multiple small tensors to incorporate factor information present between the multiple small tensors.

[0007] According to the present disclosure, it is possible to reduce the calculation processing time compared to the calculation device disclosed in Non-Patent Document 1.

[0008] FIG. 5A is a configuration diagram showing a calculation device according to a first embodiment; FIG. 5B is a hardware configuration diagram showing hardware of the calculation device according to the first embodiment; FIG. 5C is a hardware configuration diagram of a computer when the calculation device is realized by software, firmware, or the like; and FIG. 5D is a flowchart showing a tensor update method, which is a processing procedure of the calculation device. FIG. 5A shows a matrix a ｊ，ｋ and matrix a ｉ，ｋ FIG. 5B is an explanatory diagram showing the tensor a ｉ，ｊ，ｋ 5C is an explanatory diagram showing the tensor M ｉ，ｊ σｉ，σｉ＋１12. An explanatory diagram showing an L-th-order tensor expressed as the product of multiple small tensors. An explanatory diagram showing an example in which the number of elements of a tensor is reduced by increasing the rank of the tensor. An explanatory diagram showing conventional contraction processing disclosed in Non-Patent Document 1. An explanatory diagram showing contraction processing, decomposition processing, and approximation processing in the arithmetic device shown in FIG. 1. A configuration diagram showing the inside of the contraction unit 1. A flowchart showing the processing procedure of the contraction unit 1. A configuration diagram showing a arithmetic device according to a second embodiment. A hardware configuration diagram showing the hardware of the arithmetic device according to the second embodiment. A flowchart showing a tensor updating method, which is the processing procedure of the arithmetic device according to the second embodiment. An explanatory diagram showing contraction processing, decomposition processing, approximation processing, and rearrangement processing in the arithmetic device shown in FIG. 12. An explanatory diagram showing a specific example of rearrangement processing by the rearrangement unit 4. An explanatory diagram showing an example in which multiple pieces of factor information exist between multiple small tensors. An explanatory diagram showing factor information after movement. A flowchart showing contraction processing by the contraction unit 1 in the arithmetic device according to a fourth embodiment.

[0033] Fig. 20A is an explanatory diagram showing an example of the configuration of a switching target, and Fig. 20B is an explanatory diagram showing an example of a user interface for setting. Fig. 22A is an explanatory diagram showing an example of a product of small tensors having a one-dimensional shape, Fig. 22B is an explanatory diagram showing an example of a product of small tensors having a two-dimensional, two-row shape, Fig. 22C is an explanatory diagram showing an example of a product of small tensors having a two-dimensional, two-column shape, and Fig. 22D is an explanatory diagram showing an example of a product with a large two-dimensional row or column.

[0009] In order to explain the present disclosure in more detail, embodiments of the present disclosure will be described below with reference to the accompanying drawings.

[0010] Embodiment 1. Fig. 1 is a configuration diagram showing a calculation device according to embodiment 1. Fig. 2 is a hardware configuration diagram showing the hardware of the calculation device according to embodiment 1. The calculation device shown in Fig. 1 includes a reduction unit 1, a decomposition unit 2, and an approximation unit 3.

[0011] The contraction unit 1 is realized, for example, by a contraction circuit 11 shown in FIG. 2 . The contraction unit 1 expresses an L-th order tensor (L is an integer equal to or greater than two) as a product of multiple sub-tensors, which are tensors having fewer elements than the L-th order tensor. The contraction unit 1 performs a contraction process on the multiple sub-tensors, incorporating factor information present between the multiple sub-tensors. The factor information may be, for example, a factor matrix in matrix form, or a numerical value or numerical sequence in which elements close to zero in a matrix are omitted. The factor information is information obtained when converting each L-th order tensor into, for example, a basis transformation matrix, and includes, for example, information representing a quantum state. Among the multiple factor information, factor information present closer to the tensor of the operator has a greater impact on the accuracy of the calculation. The contraction unit 1 outputs the contraction results from the contraction process to the decomposition unit 2.

[0012] Here, the contraction unit 1 performs a contraction process for a plurality of small tensors, incorporating factor information present between the plurality of small tensors. However, this is merely an example, and the contraction unit 1 may also perform a contraction process for a plurality of small tensors, incorporating factor information present between the plurality of small tensors and operators for the plurality of small tensors. In the following explanation, it is assumed that the contraction unit 1 performs a contraction process for incorporating factor information and operators.

[0013] The decomposition unit 2 is realized by, for example, the decomposition circuit 12 shown in Fig. 2. The decomposition unit 2 obtains the contraction result from the contraction process from the contraction unit 1. The decomposition unit 2 performs a decomposition process on the contraction result and outputs a tensor group including a plurality of small tensors and factor information to the approximation unit 3.

[0014] The approximation unit 3 is realized by, for example, the approximation circuit 13 shown in Fig. 2. The approximation unit 3 acquires a tensor group including a plurality of small tensors and factor information from the decomposition unit 2. The approximation unit 3 performs approximation processing on the factor information included in the tensor group.

[0015] 1, it is assumed that each of the components of the arithmetic device, that is, a reduction unit 1, a decomposition unit 2, and an approximation unit 3, is realized by dedicated hardware as shown in Fig. 2. That is, it is assumed that the arithmetic device is realized by a reduction circuit 11, a decomposition circuit 12, and an approximation circuit 13. Each of the reduction circuit 11, the decomposition circuit 12, and the approximation circuit 13 corresponds to, for example, a single circuit, a composite circuit, a programmed processor, a parallel programmed processor, an ASIC (Application Specific Integrated Circuit), an FPGA (Field-Programmable Gate Array), or a combination thereof.

[0016] The components of the arithmetic unit are not limited to those realized by dedicated hardware, and the arithmetic unit may be realized by software, firmware, or a combination of software and firmware. The software or firmware is stored in the memory of a computer as a program. A computer refers to hardware that executes a program, and includes, for example, a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), a central processing unit, a processing unit, an arithmetic unit, a microprocessor, a microcomputer, a processor, or a DSP (Digital Signal Processor).

[0017] 3 is a hardware configuration diagram of a computer when the arithmetic unit is realized by software, firmware, etc. When the arithmetic unit is realized by software, firmware, etc., a program for causing the computer to execute the respective processing procedures of the contraction unit 1, decomposition unit 2, and approximation unit 3 is stored in memory 21. Then, a processor 22 of the computer executes the program stored in memory 21.

[0018] 2 shows an example in which each of the components of the arithmetic device is realized by dedicated hardware, while Fig. 3 shows an example in which the arithmetic device is realized by software, firmware, etc. However, this is merely an example, and some of the components in the arithmetic device may be realized by dedicated hardware, and the remaining components may be realized by software, firmware, etc.

[0019] Next, the operation of the arithmetic unit shown in Fig. 1 will be described. Fig. 4 is a flowchart showing a tensor updating method, which is a processing procedure of the arithmetic unit. Fig. 5A shows a case where the L-th order tensor is a second-order tensor, and the matrix a ｊ，ｋ and matrix a ｉ，ｋ The matrix a ｊ，ｋ The number of elements of D ｊ D ｋ and the matrix a ｉ，ｋ The number of elements of D ｉ D ｋ FIG. 5B shows that the L-th order tensor is a third-order tensor, and the third-order tensor is a tensor a ｉ，ｊ，ｋ The tensor a ｉ，ｊ，ｋ The number of elements of D ｉ D ｊ D ｋ FIG. 5C shows that the L-th order tensor is a fourth-order tensor, and the tensor M ｉ，ｊ σｉ，σｉ＋１ This shows:

[0020] Fig. 10 is a block diagram showing the inside of the contraction unit 1. As shown in Fig. 10, the contraction unit 1 includes a tensor acquisition unit 31, a tensor representation unit 32, and a contraction processing unit 33. Fig. 11 is a flowchart showing the processing procedure of the contraction unit 1. The tensor acquisition unit 31 of the contraction unit 1 acquires M subscripts σ as shown in the upper diagram of Fig. 6. ｍ An L-th order tensor Φ having m=1, . . . , M is acquired (step ST11 in FIG. 11 ). M is an integer equal to or greater than 2. The tensor Φ is, for example, a tensor having a subscript σ ｍ When the degrees of freedom of each are 2, 2 MThe tensor representation unit 32 of the contraction unit 1 converts the L-th order tensor Φ into a plurality of small tensors T ｉ (Step ST12 in FIG. 11 ), where i=1, ..., I, and I is an integer equal to or greater than 2. The small tensor T ｉ has a constant number of elements. The number of elements is 2 M FIG. 6 is an explanatory diagram showing an L-th order tensor expressed as a product of multiple small tensors.

[0021] The techniques disclosed herein can be used by transforming a first-order tensor into a second-order or higher-order tensor. Figure 7 is an explanatory diagram showing an example in which the number of elements of a tensor is reduced by increasing the rank of the tensor. In the example of Figure 7, the number of elements, D ｉ is 10000, the number of elements is D ａ , D ｂ is 100, the number of elements is D ｃ When σ is 5, the tensor on the far right in the figure is expressed as the product of two small tensors. The number of elements of the tensor on the far right in the figure is 1000, which is fewer than the number of elements of the tensor on the far left. In Figure 7, the number of elements of a tensor is reduced by increasing the rank of the tensor. However, this is merely an example, and the number of elements of a tensor may also be reduced by decreasing the rank of the tensor. Since reducing the number of elements of a tensor by decreasing the rank of a tensor is a well-known technique, a detailed description thereof will be omitted. The example in Figure 7 shows an L-order tensor expressed as the product of two small tensors. However, this is merely an example, and an L-order tensor may also be expressed as the product of three or more small tensors.

[0022] The contraction processing unit 33 of the contraction unit 1 performs a contraction process on a plurality of small tensors, incorporating factor information present between the plurality of small tensors and operators for the plurality of small tensors (step ST1 in FIG. 4 and step ST13 in FIG. 11). The contraction processing unit 33 outputs the contraction results from the contraction process to the decomposition unit 2.

[0023] FIG. 8 is an explanatory diagram showing a conventional contraction process disclosed in Non-Patent Document 1. In the conventional contraction process, the leftmost factor information is moved one position to the right, thereby moving the leftmost factor information between two small tensors. In the conventional contraction process, all factor information to the right of the two small tensors is moved, thereby moving all factor information between the two small tensors. For example, the rightmost factor information is moved five positions to the left, thereby moving it between the two small tensors. The process of moving factor information itself is a well-known technique, so a detailed description will be omitted. The conventional contraction process requires a calculation processing time associated with moving this factor information. In the example of FIG. 8, after this factor information is moved, a contraction process is performed to incorporate all factor information and operators into the two small tensors.

[0024] FIG. 9 is an explanatory diagram showing the contraction process, decomposition process, and approximation process in the arithmetic device shown in FIG. 1 . In the arithmetic device shown in FIG. 1 , the contraction processing unit 33 of the contraction unit 1 does not move factor information as in conventional contraction processes. Factor information other than factor information originally present between two small tensors has less impact on calculation accuracy the further it is between the two small tensors. In other words, selectively incorporating factor information present between the two small tensors into two small tensors enables efficient calculation. Therefore, in the contraction process by the contraction processing unit 33, factor information present between multiple small tensors is selectively incorporated into two small tensors.

[0025] The small tensor on the left side included in the tensor group to be contracted shown in FIG. ｉ，ｋ’ σ’ｌ , the right-hand small tensor included in the tensor group to be contracted is b' ｋ’，ｊσ’ｌ＋１ , the factor information existing between the two small tensors is s' ｋ’ , the operator is M σ’ｌ，σ’ｌ＋１ σｌ，σｌ＋１ If so, the contraction result M ｉ，ｊ σｌ，σｌ＋１ is expressed as the following equation (1): l is a variable indicating the number of dimensions.

[0026] Here, an example is shown in which an operator, which is an operation performed on a tensor, is expressed as a fourth-order tensor, and the operation of applying the operator is expressed by a multiply-and-accumulate operation. However, this is just one example, and there are cases where the order of the operator is different from fourth order, for example. There are also cases where the operation of applying the operator is expressed in the form of a linear equation.

[0027] The decomposition unit 2 receives the reduction result M ｉ，ｊ σｌ，σｌ＋１ Here, the reduction process is expressed by a sum-of-products operation. However, this is only an example, and it is preferable to use a method that satisfies the axioms of a commutative semiring, and is not limited to a sum-of-products operation. The decomposition unit 2 obtains the reduction result M ｉ，ｊ σｌ，σｌ＋１ The decomposition process is performed on the contraction result M ｉ，ｊ σｌ，σｌ＋１ Examples of decomposition processing for x include singular value decomposition, QR decomposition, and QLP decomposition. A tensor group including two small tensors and factor information is obtained by the decomposition processing. The tensor group including the two small tensors and factor information is expressed as in the following equation (2). The decomposition unit 2 outputs the tensor group including the two small tensors and factor information to the approximation unit 3.

[0028] In formula (2), a ｉ，ｋ σｌ is the left-hand sub-tensor, and b ｋ，ｊ σｌ＋１ is the right-hand sub-tensor, and s ｋ is the factor information existing between two small tensors.

[0029] The approximation unit 3 acquires a tensor group including two small tensors and factor information from the decomposition unit 2. The approximation unit 3 performs approximation processing on the factor information included in the tensor group (step ST3 in FIG. 4 ). An example of approximation processing on the factor information is a process of deleting singular values ​​close to 0 from among the singular values ​​of the factor matrix indicating the factor information. When the number of singular values ​​of the factor matrix indicating the factor information included in the tensor group is D′, if the number of singular values ​​of the factor matrix is ​​set to D (D<D′) by deleting the singular values ​​close to 0, the tensor group after approximation processing is expressed as shown in the following formula (3).

[0030]

[0031] In the first embodiment described above, a tensor of order L (L is an integer equal to or greater than 2) is expressed as a product of multiple sub-tensors, each of which has fewer elements than the L-order tensor, and the arithmetic device is configured to include a contraction unit 1 that performs a contraction process on the multiple sub-tensors, incorporating factor information present between the multiple sub-tensors. Therefore, the arithmetic device can reduce the arithmetic processing time compared to the arithmetic device disclosed in Non-Patent Document 1.

[0032] Furthermore, in the first embodiment, the arithmetic device is configured to include an approximation unit 3 that performs approximation processing on the factor information included in the tensor group output from the decomposition unit 2. Therefore, the arithmetic device can reduce the size of the factor information included in the tensor group.

[0033] Embodiment 2 In embodiment 2, a calculation device including a rearrangement unit 4 that rearranges adjacent factor information, which is factor information adjacent to each small tensor, among factor information other than factor information existing between a plurality of small tensors, for a tensor group after approximation processing by the approximation unit 3 will be described.

[0034] Fig. 12 is a configuration diagram showing a calculation device according to embodiment 2. In Fig. 12, the same reference numerals as in Fig. 1 indicate the same or corresponding parts, and detailed description thereof will be omitted. Fig. 13 is a hardware configuration diagram showing the hardware of the calculation device according to embodiment 2. In Fig. 13, the same reference numerals as in Fig. 2 indicate the same or corresponding parts, and detailed description thereof will be omitted. The calculation device shown in Fig. 12 includes a contraction unit 1, a decomposition unit 2, an approximation unit 3, and a rearrangement unit 4.

[0035] The rearrangement unit 4 is realized by, for example, the rearrangement circuit 14 shown in Fig. 13. The rearrangement unit 4 acquires the tensor set after the approximation process from the approximation unit 3. The rearrangement unit 4 rearranges, for the tensor set, adjacent factor information, which is factor information adjacent to each small tensor, among factor information other than that existing between a plurality of small tensors.

[0036] 12, it is assumed that each of the components of the arithmetic device, that is, the contraction unit 1, the decomposition unit 2, the approximation unit 3, and the rearrangement unit 4, is realized by dedicated hardware as shown in Fig. 13. That is, it is assumed that the arithmetic device is realized by a contraction circuit 11, a decomposition circuit 12, an approximation circuit 13, and a rearrangement circuit 14. Each of the contraction circuit 11, the decomposition circuit 12, the approximation circuit 13, and the rearrangement circuit 14 corresponds to, for example, a single circuit, a composite circuit, a programmed processor, a parallel programmed processor, an ASIC, an FPGA, or a combination thereof.

[0037] The components of the arithmetic unit are not limited to those realized by dedicated hardware, and the arithmetic unit may be realized by software, firmware, or a combination of software and firmware. When the arithmetic unit is realized by software or firmware, a program for causing a computer to execute the respective processing procedures of the contraction unit 1, decomposition unit 2, approximation unit 3, and rearrangement unit 4 is stored in memory 21 shown in Fig. 3. Then, processor 22 shown in Fig. 3 executes the program stored in memory 21.

[0038] 13 shows an example in which each of the components of the arithmetic device is realized by dedicated hardware, while Fig. 3 shows an example in which the arithmetic device is realized by software, firmware, etc. However, this is merely an example, and some of the components in the arithmetic device may be realized by dedicated hardware, and the remaining components may be realized by software, firmware, etc.

[0039] Next, the operation of the arithmetic device shown in FIG. 12 will be described. However, since the arithmetic device is the same as that shown in FIG. 1 except for the rearrangement unit 4, only the operation of the rearrangement unit 4 will be described here. FIG. 14 is a flowchart showing a tensor update method, which is a processing procedure of the arithmetic device according to embodiment 2. FIG. 15 is an explanatory diagram showing the contraction process, decomposition process, approximation process, and rearrangement process in the arithmetic device shown in FIG. 12. For example, the rearrangement unit 4 stores neighboring factor information before the contraction process is performed by the contraction unit 1. As shown in FIG. 15, the neighboring factor information is factor information adjacent to each small tensor among factor information other than factor information existing between multiple small tensors. The rearrangement unit 4 obtains the tensor set after the approximation process from the approximation unit 3. As shown in FIG. 15, the rearrangement unit 4 rearranges the neighboring factor information for the tensor set (step ST4 in FIG. 14).

[0040] The rearrangement process of the rearrangement unit 4 will be specifically described below. Fig. 16 is an explanatory diagram showing a specific example of the rearrangement process by the rearrangement unit 4. Fig. 16 shows a case where neighboring factor information S １ The rearrangement unit 4 rearranges the tensor T ２ On the other hand, the neighboring factor information S １ and factor information S ２ However, even after the contraction, S １, T ２, The rearrangement unit 4 then performs a decomposition process such as QR decomposition on the contraction result to obtain the factor information S'. １ Next, the rearrangement unit 4 obtains the small tensor T on the right side of the figure, out of the two small tensors included in the tensor group after the approximation process.１ On the other hand, the factor information S' １ The inverse matrix S' of the matrix １ －１ By performing the above process, the rearrangement unit 4 multiplies the neighboring factor information S １ can be rearranged.

[0041] In the second embodiment described above, the arithmetic device shown in Fig. 12 is configured to include a rearrangement unit 4 that rearranges adjacent factor information, which is factor information adjacent to each small tensor, among factor information other than factor information existing between a plurality of small tensors, for a tensor group after approximation processing by the approximation unit 3. Therefore, the arithmetic device shown in Fig. 12 can shorten the arithmetic processing time more than the arithmetic device disclosed in Non-Patent Document 1, and can also improve the arithmetic accuracy more than the arithmetic device shown in Fig. 1.

[0042] In the arithmetic device shown in Fig. 12, the rearrangement unit 4 rearranges the neighboring factor information for the tensor group. When rearranging the neighboring factor information, the rearrangement unit 4 may adjust the value of the neighboring factor information. １ If a matrix containing small singular values ​​contains a singular value, the matrix may become numerically unstable. Therefore, it is necessary to remove the bond dimension of the tensor or to use the neighbor factor information S １ The inverse matrix S' of the matrix １ －１ By approximating the singular values ​​contained in to 0, a numerically stable operation becomes possible.

[0043] Third Embodiment In the third embodiment, a calculation device will be described in which the contraction unit 1 performs a contraction process on a plurality of small tensors, incorporating a plurality of pieces of factor information present between the plurality of small tensors.

[0044] The configuration of the arithmetic device according to the third embodiment is the same as the configuration of the arithmetic device according to the first embodiment or the configuration of the arithmetic device according to the second embodiment. Therefore, the configuration diagram showing the arithmetic device according to the third embodiment is FIG. 1 or FIG. 12 . FIG. 17 is an explanatory diagram showing an example in which multiple pieces of factor information exist between multiple small tensors. In the example of FIG. 17 , four pieces of factor information exist between two small tensors. In the example of FIG. 17 , the contraction unit 1 moves the first piece of factor information from the right three spaces to the left, the second piece of factor information from the right two spaces to the left, and the third piece of factor information from the right one space to the left. The process of moving factor information itself is a well-known technique, so a detailed description will be omitted. As a result, the four pieces of factor information exist between two adjacent small tensors, as shown in FIG. 18 . FIG. 18 is an explanatory diagram showing the factor information after the moves. The contraction unit 1 performs a contraction process on two small tensors to incorporate the four pieces of factor information existing between the two small tensors.

[0045] In the third embodiment described above, the arithmetic device is configured so that the contraction unit 1 performs contraction processing on a plurality of small tensors, incorporating a plurality of pieces of factor information present between the plurality of small tensors. Therefore, the arithmetic device can perform contraction processing on a plurality of small tensors even when a plurality of pieces of factor information exists between the plurality of small tensors.

[0046] Fourth Embodiment In the fourth embodiment, a description will be given of a calculation device in which a reduction unit 1 performs a reduction process on a plurality of small tensors, incorporating factor information present between the plurality of small tensors, only when priority is given to calculation processing time over calculation accuracy.

[0047] The configuration of the arithmetic device according to the fourth embodiment is the same as the configuration of the arithmetic device according to the first embodiment or the configuration of the arithmetic device according to the second embodiment. Therefore, the configuration diagram showing the arithmetic device according to the fourth embodiment is Fig. 1 or Fig. 12. Fig. 19 is a flowchart showing the reduction processing of the reduction unit 1 in the arithmetic device according to the fourth embodiment.

[0048] Next, the operation of the arithmetic device according to embodiment 4 will be described. However, since the operation other than that of the reduction unit 1 is the same as that of the arithmetic device according to embodiment 1, only the operation of the reduction unit 1 will be described here. The user can set the arithmetic device to prioritize calculation processing time over calculation accuracy, or to prioritize calculation accuracy over calculation processing time.

[0049] FIG. 20A is an explanatory diagram showing an example of a configuration to be switched. FIG. 20B is an explanatory diagram showing an example of a user interface for settings. Calculations using tensor networks are compiled into a library, and calculations can be switched according to user specifications. Parameters for switching between the configuration on the left side of FIG. 20A (emphasis on calculation accuracy) and the configuration on the right side of the figure (emphasis on speed: priority on calculation processing time) include, for example, whether to prioritize calculation speed, whether to use all operators, and whether to execute all swaps. Swaps are performed by using the physical index σ ｉ The swap is usually performed continuously, and it may be preferable to perform all swaps to achieve high accuracy. In the user interface shown in FIG. 20B , for example, the range of tensor updates, the range of small tensors representing the L-th order tensors, the numbers of small tensors representing the L-th order tensors, the number of factor information to be used for the update, etc. can be set. In the example of FIG. 20B , the number of factor information to be used for the update among the factor information present to the left of the second small tensor from the left in the figure, and the number of factor information to be used for the update among the factor information present to the right of the third small tensor from the left in the figure can be set. A variable value may be set by changing the number of required factor information according to the number of small tensors representing the L-th order tensors. Although not shown in FIG. 20 , the number of swaps to be used for the update may be set. If an increase in the speed of calculations is expected, the user may configure the calculation device. For example, predictions by AI (Artificial Intelligence) may be used to predict the expected increase in calculation speed.

[0050] If the reduction unit 1 is set to prioritize calculation time over calculation accuracy (step ST21 in FIG. 19 : YES), it performs a reduction process on the multiple small tensors to incorporate factor information present between the multiple small tensors (step ST22 in FIG. 19 ), similar to the calculation devices of Embodiments 1 to 3. If the reduction unit 1 is set to prioritize calculation accuracy over calculation time (step ST21 in FIG. 19 : NO), it performs a reduction process on the multiple small tensors to incorporate all factor information that has a connection relationship with each small tensor (step ST23 in FIG. 19 ), similar to the calculation device of Non-Patent Document 1.

[0051] In the above-described fourth embodiment, the arithmetic device is configured so that, when the reduction unit 1 prioritizes calculation processing time over calculation accuracy, it performs a reduction process for multiple small tensors that incorporates factor information present between the multiple small tensors, and, when the arithmetic accuracy is prioritized over calculation processing time, it performs a reduction process for multiple small tensors that incorporates all factor information that has a connection relationship with each of the multiple small tensors. Therefore, the arithmetic device can perform a reduction process that prioritizes either calculation accuracy or calculation processing time.

[0052] In the arithmetic device according to the fourth embodiment, if a setting is made to prioritize arithmetic processing time over arithmetic accuracy, the contraction unit 1 performs a contraction process for multiple small tensors, incorporating factor information present between the multiple small tensors. However, this is merely an example, and even if a setting is made to prioritize arithmetic processing time over arithmetic accuracy, the contraction unit 1 may perform a contraction process for multiple small tensors, incorporating factor information present between the multiple small tensors, only if a faster arithmetic processing time can be expected. A case in which a faster arithmetic processing time can be expected is, for example, when the number of times factor information is moved is equal to or greater than a threshold.

[0053] Fifth Embodiment In the fifth embodiment, a calculation device will be described in which, when there are a plurality of tensors to be contracted, each containing a plurality of small tensors, the contraction unit 1 performs contraction processing on the plurality of tensors to be contracted in parallel.

[0054] The configuration of the arithmetic device according to the fifth embodiment is the same as the configuration of the arithmetic device according to the first embodiment or the configuration of the arithmetic device according to the second embodiment. Therefore, the configuration diagram showing the arithmetic device according to the fifth embodiment is FIG. 1 or FIG. 12.

[0055] FIG. 21 is an explanatory diagram showing an example of multiple tensors to be contracted for which contraction processing is performed in parallel. FIG. 21A shows four tensors to be contracted, and FIG. 21B shows two tensors to be contracted. In the example of FIG. 21A, the contraction unit 1 performs contraction processing on four tensors to be contracted in parallel. In the example of FIG. 21B, the contraction unit 1 performs contraction processing on two tensors to be contracted in parallel. The contraction processing performed by the arithmetic device according to embodiment 5 for each tensor to be contracted is similar to the contraction processing performed by the arithmetic devices according to embodiments 1 to 4. When performing contraction processing on multiple tensors to be contracted, the arithmetic device according to embodiment 5 performs multiple contraction processing in parallel.

[0056] In the fifth embodiment described above, the arithmetic device according to the third embodiment is configured so that there are a plurality of tensors to be contracted, each of which includes a plurality of small tensors, and the contraction unit 1 performs the contraction process on the plurality of tensors to be contracted in parallel. Therefore, the arithmetic device according to the third embodiment can achieve faster arithmetic processing time than the arithmetic device according to the first embodiment.

[0057] In the first to fifth embodiments, an example is shown in which the shape of the product of small tensors is one-dimensional, as shown in FIG. 22A . However, this is merely an example, and the shape of the product of small tensors can also be applied to a two-dimensional, two-row shape as shown in FIG. 22B . The shape of the product of small tensors can also be applied to a two-dimensional, two-column shape as shown in FIG. 22C . The shape of the product of small tensors can also be applied to a shape with a large two-dimensional row or column as shown in FIG. 22D . When the shape of the product of small tensors is one-dimensional or a two-dimensional, two-row shape, the same path can be repeatedly taken during swapping, allowing for efficient updating of factor information. For example, when updating consecutive intervals using multiple long-distance operators, if an update path can be selected, it is particularly effective to select the update path toward the longer one. If the longer one is two rows, an update path toward the rows is selected, and if the longer one is two columns, an update path toward the columns is selected. This allows the update information of the factor information from the previous operator to be reflected in the next operator, resulting in more accurate calculations.

[0058] FIG. 22A is an explanatory diagram showing an example in which the shape of a product of small tensors is a one-dimensional shape. FIG. 22B is an explanatory diagram showing an example in which the shape of a product of small tensors is a two-dimensional, two-row shape. FIG. 22C is an explanatory diagram showing an example in which the shape of a product of small tensors is a two-dimensional, two-column shape. FIG. 22D is an explanatory diagram showing an example in which the two-dimensional rows or columns are large. However, the shape of a product of small tensors may be a combination of one-row and two-row shapes in part, or a product of small tensors that includes three or more rows in part. When the shape of a product of small tensors is two-dimensional, the shape of the product of small tensors is not limited to a two-dimensional rectangle, but may be, for example, a polygon, a bond intersection, or an N-dimensional solid shape.

[0059] In addition, the present disclosure allows for free combination of the respective embodiments, modification of any of the components of the respective embodiments, or omission of any of the components of the respective embodiments.

[0060] The present disclosure is suitable for a computing device and a tensor update method.

[0061] REFERENCE SIGNS LIST 1 Contraction unit, 2 Decomposition unit, 3 Approximation unit, 4 Rearrangement unit, 11 Contraction circuit, 12 Decomposition circuit, 13 Approximation circuit, 14 Rearrangement circuit, 21 Memory, 22 Processor, 31 Tensor acquisition unit, 32 Tensor representation unit, 33 Contraction processing unit.

Claims

1. A computing device having a contraction unit that expresses an L-th order (L is an integer greater than or equal to 2) tensor as a product of multiple small tensors, which are tensors having fewer elements than the number of elements of the L-th order tensor, and performs a contraction process on the multiple small tensors to incorporate factor information present between the multiple small tensors.

2. The arithmetic device according to claim 1, characterized in that the contraction unit performs a contraction process on the plurality of small tensors by incorporating factor information existing between the plurality of small tensors and an operator for the plurality of small tensors.

3. The arithmetic device according to claim 2, further comprising a decomposition unit that performs decomposition processing on the reduction result of the reduction processing of said reduction unit, and outputs a tensor group including a plurality of small tensors and factor information.

4. The arithmetic device according to claim 3, further comprising an approximation unit that performs approximation processing of factor information included in the tensor group output from said decomposition unit.

5. The arithmetic device according to claim 4, further comprising a rearrangement unit that rearranges adjacent factor information, which is factor information adjacent to each small tensor, among factor information other than that existing between the plurality of small tensors, for the tensor group after approximation processing by the approximation unit.

6. The arithmetic device according to claim 1, wherein the contraction unit performs a contraction process on the plurality of small tensors, incorporating information on a plurality of factors existing between the plurality of small tensors.

7. The arithmetic device according to claim 1, characterized in that the contraction unit performs a contraction process on the plurality of small tensors to incorporate factor information present between the plurality of small tensors when priority is given to calculation processing time over calculation accuracy, and performs a contraction process on the plurality of small tensors to incorporate all factor information that has a connection relationship with each of the small tensors when priority is given to calculation accuracy over calculation processing time.

8. The arithmetic device according to claim 1, characterized in that there are a plurality of tensors to be contracted, each of which includes a plurality of small tensors, and the contraction unit performs the contraction process on the plurality of tensors to be contracted in parallel.

9. The arithmetic unit according to claim 1, wherein the shape of the product of said small tensors is one-dimensional, two-dimensional with two rows, or two-dimensional with two columns.

10. A tensor updating method in which a contraction unit represents an L-th order (L is an integer equal to or greater than 2) tensor as a product of multiple small tensors, each of which has a number of elements fewer than the number of elements of the L-th order tensor, and performs a contraction process on the multiple small tensors to incorporate factor information present between the multiple small tensors.

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