Image sensor and imaging device

Abstract

The present invention improves performance in an image sensor that performs HDR synthesis.　This image sensor is provided with a pixel circuit, an analog-to-digital converter, a determination unit, and a characteristic control unit. The pixel circuit generates a pixel signal. The analog-to-digital converter subjects the pixel signal to analog-to-digital conversion processing. The determination unit determines whether or not the illuminance is higher than a prescribed threshold on the basis of the output of the analog-to-digital converter, and outputs a determination result. The characteristic control unit controls the characteristics of the analog-to-digital converter on the basis of the determination result.

Description

Image sensor and imaging device

[0001] The present technology relates to an image sensor, and more particularly to an image sensor that combines a plurality of pixel signals, and an imaging device.

[0002] High-Dynamic-Range (HDR) synthesis has been used in imaging devices and the like to expand the dynamic range. For example, an image sensor has been proposed in which pixel sensitivity is variable, pixel signals at high sensitivity and pixel signals at low sensitivity are read out in sequence for each pixel, and the pixel signals are HDR-synthesized (see, for example, Patent Document 1).

[0003] Japanese Patent Application Laid-Open No. 2017-175345

[0004] The conventional technology described above achieves HDR compositing by varying the sensitivity of pixels, without using long and short exposures. However, with the conventional technology described above, it is difficult to improve various aspects of performance, such as increasing speed, reducing noise, and reducing power consumption.

[0005] This technology was developed in light of these circumstances, and aims to improve the performance of image sensors that perform HDR synthesis.

[0006] The present technology has been made to solve the above-mentioned problems, and a first aspect thereof is an image sensor including a pixel circuit that generates a pixel signal, an analog-to-digital converter that performs analog-to-digital conversion processing on the pixel signal, a determination unit that determines whether or not illuminance is higher than a predetermined threshold based on an output of the analog-to-digital converter and outputs the determination result, and a characteristics control unit that controls characteristics of the analog-to-digital converter based on the determination result, thereby providing an effect of improving performance of the image sensor.

[0007] In this first aspect, the analog-to-digital converter may include a tail current source that supplies a tail current, and the characteristic may include a value of the tail current, thereby providing an effect that the value of the tail current switches depending on illuminance.

[0008] In this first aspect, the analog-to-digital converter may include a load MOS (Metal-Oxide-Semiconductor) current source connected to a vertical signal line that transmits a pixel signal, and the characteristic may include a value of a load MOS current generated by the load MOS current source, thereby providing an effect that the value of the load MOS current switches depending on illuminance.

[0009] In addition, in this first aspect, the pixel signals may include first and second pixel signals, the analog-to-digital converter may convert the first pixel signal into a first digital signal with a resolution higher than a predetermined value, and the second pixel signal into a second digital signal with a resolution not exceeding the predetermined value, and the determination unit may determine whether the illuminance is higher than the threshold value based on the output corresponding to the first pixel signal. This brings about an effect of improving image quality.

[0010] In this first aspect, the characteristic control unit may further control the charge-voltage conversion efficiency of the pixel circuit based on the determination result, thereby providing an effect of switching the charge-voltage conversion efficiency according to illuminance.

[0011] In this first aspect, the characteristics control unit may stop the analog-to-digital converter when the illuminance does not exceed the threshold value, thereby achieving an effect of reducing power consumption.

[0012] In this first aspect, the characteristic may be an analog gain of the analog-to-digital converter, thereby providing an effect that the analog gain is switched in accordance with the illuminance.

[0013] Also, in this first aspect, the analog-to-digital converter may include a comparator that compares the pixel signal with a predetermined reference signal and outputs a comparison result, and a counter that counts a count value over a period until the comparison result is inverted, and the determination unit determines whether the illuminance is higher than the threshold based on the comparison result. This provides an effect of switching characteristics based on the comparison result of the comparator. Note that the counter is not necessarily required. It is determined whether the comparator is inverted when an enable timing signal corresponding to the threshold is reached. The characteristics are switched based on this comparison result.

[0014] In addition, in this first aspect, the analog-to-digital converter may include a comparator that compares the pixel signal with a predetermined reference signal and outputs a comparison result, and a counter that counts a count value over a period until the comparison result is inverted, and the determination unit may determine whether the illuminance is higher than the threshold value based on the count value. This brings about the effect of switching the characteristics based on the count value.

[0015] In the first aspect, the level of the pixel signal may include first and second reset levels when the pixel circuit is initialized and first and second signal levels according to an amount of exposure, thereby enabling a CDS (Correlated Double Sampling) process to be performed.

[0016] In addition, in this first aspect, the analog-to-digital converter may convert the first reset level, the first signal level, the second signal level, and the second reset level into a digital signal in this order, and the determination unit may determine whether the illuminance is higher than the threshold value based on the output within a readout period of the first signal level. This brings about an effect of realizing PDDP readout.

[0017] In addition, in this first aspect, the analog-to-digital converter may convert the first signal level, the first reset level, the second signal level, and the second reset level into digital signals in this order, and the determination unit may determine whether the illuminance is higher than the threshold value based on the output within a readout period of the first reset level. This brings about an effect of realizing DPDP readout.

[0018] In addition, in this first aspect, the analog-to-digital converter may convert the first reset level, the second reset level, the first signal level, and the second signal level into digital signals in this order, and the determination unit may determine whether the illuminance is higher than the threshold value based on the output within a readout period of the second reset level. This brings about an effect of realizing PPDD readout.

[0019] In addition, in this first aspect, the pixel circuit may include a first photoelectric conversion element, a transfer transistor that transfers charge from the first photoelectric conversion element to a floating diffusion layer, a reset transistor that initializes the floating diffusion layer, and an FD gain transistor that controls charge-to-voltage conversion efficiency, thereby producing an effect of generating a pixel signal.

[0020] In addition, in this first aspect, the pixel circuit may further include a second photoelectric conversion element having a sensitivity different from that of the first photoelectric conversion element, thereby producing an effect that pixel signals of two pixels having different sensitivities are generated.

[0021] A second aspect of the present technology is an image sensor including a pixel circuit that generates a pixel signal, an analog-to-digital converter that sequentially performs analog-to-digital conversion processing on the pixel signal, and a characteristics control unit that controls charge-to-voltage conversion efficiency of the pixel circuit based on an output of the analog-to-digital converter, thereby improving the performance of the image sensor.

[0022] A second aspect of the present technology is an imaging device including a pixel circuit that generates a pixel signal, an analog-to-digital converter that performs analog-to-digital conversion processing on the pixel signal, a determination unit that determines whether or not illuminance is higher than a predetermined threshold based on an output of the analog-to-digital converter and outputs the determination result, a characteristics control unit that controls characteristics of the analog-to-digital converter based on the determination result, and an image processing unit that processes the digital signal from the analog-to-digital converter. This brings about an effect of improving performance of the imaging device.

[0023] 1 is a block diagram showing an example of a configuration of an imaging device according to a first embodiment of the present technology. FIG. 2 is a diagram showing an example of a stacked structure of an image sensor according to the first embodiment of the present technology. FIG. 3 is a block diagram showing an example of a configuration of an image sensor according to the first embodiment of the present technology. FIG. 4 is a circuit diagram showing an example of a configuration of a pixel block according to the first embodiment of the present technology. FIG. 5 is a block diagram showing an example of a configuration of a column readout circuit unit and a column signal processing unit according to the first embodiment of the present technology. FIG. 6 is a circuit diagram showing an example of a configuration of a determination unit according to the first embodiment of the present technology. FIG. 7 is a timing chart showing an example of an operation of the determination unit when reading out in the order of a reset level and a signal level according to the first embodiment of the present technology. FIG. 8 is a timing chart showing an example of an operation of the determination unit when reading out in the order of a signal level and a reset level according to the first embodiment of the present technology. FIG. 9 is a diagram showing an example of an operation of a characteristic control unit according to the first embodiment of the present technology. FIG. 10 is a circuit diagram showing an example of a configuration of a load MOS current source according to the first embodiment of the present technology. FIG. 11 is a circuit diagram showing an example of a configuration of a comparator according to the first embodiment of the present technology. FIG. 12 is a timing chart showing an example of an operation of an image sensor at the start of exposure according to the first embodiment of the present technology. FIG. 13 is a timing chart showing an example of an operation of an image sensor when reading out in the order of PDDP starting from a pixel with low illuminance according to the first embodiment of the present technology. 1 is a timing chart showing an example of an operation of an image sensor when reading out pixels from a pixel with a low illuminance in the order of PDDP according to the first embodiment of the present technology. FIG. 2 is a timing chart showing an example of an operation of an image sensor when reading out pixels from a pixel with a low illuminance in the order of DPDP according to the first embodiment of the present technology. FIG. 3 is a flowchart showing an example of an operation of an image sensor when reading out pixels from a pixel with a high illuminance in the order of DPDP according to the first embodiment of the present technology. FIG. 4 is a timing chart showing an example of an operation of an image sensor when reading out pixels from a pixel with a low illuminance in the order of PDDP according to a modified example of the first embodiment of the present technology. FIG. 5 is a timing chart showing an example of an operation of an image sensor when reading out pixels from a pixel with a low illuminance in the order of PDDP according to a modified example of the first embodiment of the present technology.1 is a block diagram showing an example of a configuration of a pixel and a column signal processing unit according to a second embodiment of the present technology. FIG. 2 is a diagram showing an example of an operation of a characteristic control unit according to the second embodiment of the present technology. FIG. 3 is a timing chart showing an example of an operation of an image sensor when reading out pixels starting from low illuminance in the order of PPDD according to the second embodiment of the present technology. FIG. 4 is a timing chart showing an example of an operation of an image sensor when reading out pixels starting from high illuminance in the order of PPDD according to the second embodiment of the present technology. FIG. 5 is a timing chart showing an example of an operation of an image sensor when reading out pixels starting from low illuminance in the order of PDDP according to the second embodiment of the present technology. FIG. 6 is a timing chart showing an example of an operation of an image sensor when reading out pixels starting from high illuminance in the order of PDDP according to the second embodiment of the present technology. FIG. 7 is a block diagram showing an example of a configuration of a pixel and a column signal processing unit according to a first modified example of the second embodiment of the present technology. FIG. 8 is a circuit diagram showing an example of a configuration of a counter according to the first modified example of the second embodiment of the present technology. FIG. 9 is a diagram showing an example of an operation of a characteristic control unit and an output control unit according to the first modified example of the second embodiment of the present technology. FIG. 10 is a timing chart showing an example of an operation of an image sensor when reading out pixels starting from low illuminance in the order of PPDD according to the first modified example of the second embodiment of the present technology. 10 is a timing chart showing an example of operation of an image sensor when reading out in the order of PPDD starting from pixels with high illuminance in a first modified example of a second embodiment of the present technology. 11 is a timing chart showing an example of operation of an image sensor when reading out in the order of PDDP starting from pixels with low illuminance in a first modified example of a second embodiment of the present technology. 12 is a timing chart showing an example of operation of an image sensor when reading out in the order of PDDP starting from pixels with high illuminance in a first modified example of a second embodiment of the present technology. 13 is a block diagram showing an example of a configuration of a pixel block and a column signal processing unit in a second modified example of a second embodiment of the present technology. 14 is a timing chart showing an example of operation of an image sensor when reading out from pixels with low illuminance in a comparative example. 15 is a timing chart showing an example of operation of an image sensor when reading out from pixels with high illuminance in a comparative example.10 is a timing chart showing an example of operation of an image sensor when reading out pixels with low illuminance in the order of DPDP according to a second modified example of the second embodiment of the present technology. FIG. 11 is a timing chart showing an example of operation of an image sensor when reading out pixels with high illuminance in the order of DPDP according to a second modified example of the second embodiment of the present technology. FIG. 12 is a block diagram showing an example of a configuration of a column signal processing unit according to a third embodiment of the present technology. FIG. 13 is a diagram showing an example of operation of a characteristic control unit according to the third embodiment of the present technology. FIG. 14 is a timing chart showing an example of operation of an image sensor when reading out pixels with low illuminance in the order of PPDD according to the third embodiment of the present technology. FIG. 15 is a timing chart showing an example of operation of an image sensor when reading out pixels with high illuminance in the order of PPDD according to the third embodiment of the present technology. FIG. 16 is a timing chart showing an example of operation of an image sensor when reading out pixels with low illuminance in the order of PDDP according to the third embodiment of the present technology. FIG. 17 is a timing chart showing an example of operation of an image sensor when reading out pixels with high illuminance in the order of PDDP according to the third embodiment of the present technology. FIG. 18 is a block diagram showing an example of a configuration of a column signal processing unit according to a first modified example of the third embodiment of the present technology. 10 is a timing chart showing an example of an operation of an image sensor when reading out in the order of PPDD starting from a pixel with low illuminance in the first modified example of the third embodiment of the present technology. FIG. 11 is a timing chart showing an example of an operation of an image sensor when reading out in the order of PPDD starting from a pixel with high illuminance in the first modified example of the third embodiment of the present technology. FIG. 12 is a timing chart showing an example of an operation of an image sensor when reading out in the order of PDDP starting from a pixel with low illuminance in the first modified example of the third embodiment of the present technology. FIG. 13 is a timing chart showing an example of an operation of an image sensor when reading out in the order of PDDP starting from a pixel with high illuminance in the first modified example of the third embodiment of the present technology. FIG. 14 is a diagram showing an example of a readout operation of an image sensor in a second modified example of the third embodiment of the present technology and a comparative example. FIG. 15 is a timing chart showing an example of an operation of an image sensor when reading out from a pixel with low illuminance in the second modified example of the third embodiment of the present technology.10 is a timing chart showing an example of operation of an image sensor when reading from a pixel with high illuminance in a second modified example of the third embodiment of the present technology. A diagram showing an example of readout operation of an image sensor in another example of the second modified example of the third embodiment of the present technology and a comparative example. A timing chart showing an example of operation of an image sensor when it is determined that the illuminance is high and reading is performed at a pixel with lower conversion efficiency in another example of the second modified example of the third embodiment of the present technology. A timing chart showing an example of operation of an image sensor when it is determined that the illuminance is low and reading is performed at a pixel with higher conversion efficiency in another example of the second modified example of the third embodiment of the present technology. A block diagram showing an example of a configuration of a column signal processing unit in a fourth embodiment of the present technology. A block diagram showing an example of a configuration of a data latch in the fourth embodiment of the present technology. A diagram showing an example of operation of a determination unit in the fourth embodiment of the present technology. A timing chart showing an example of operation of an image sensor at the time of determination in the fourth embodiment of the present technology. A circuit diagram showing an example of a configuration of a pixel block in which transfer transistors are reduced in a fifth embodiment of the present technology. A circuit diagram showing an example of a configuration of a pixel block in which FD (Floating Diffusion) gain transistors are reduced in a fifth embodiment of the present technology. Fig. 10 is a circuit diagram showing a configuration example of a pixel block to which a transfer transistor is added according to a fifth embodiment of the present technology. Fig. 11 is a circuit diagram showing a configuration example of a pixel block to which a transfer transistor is added and an FC gain transistor is removed according to the fifth embodiment of the present technology. Fig. 12 is a circuit diagram showing a configuration example of a pixel block to which a transfer transistor is added and an FD gain transistor is removed according to the fifth embodiment of the present technology. Fig. 13 is a circuit diagram showing a configuration example of a pixel to which a capacitor and a transfer transistor are added according to a sixth embodiment of the present technology. Fig. 14 is a circuit diagram showing a configuration example of a pixel to which a capacitor is added according to the sixth embodiment of the present technology. Fig. 15 is a circuit diagram showing a configuration example of a pixel to which an FC gain transistor and a capacitor are added and an FD gain transistor is removed according to the sixth embodiment of the present technology.Fig. 14 is a circuit diagram showing an example configuration of a pixel to which an FC gain transistor, a capacitor, and an overflow gate transistor are added according to a sixth embodiment of the present technology. Fig. 15 is a circuit diagram showing an example configuration of a pixel to which a capacitor and an overflow gate transistor are added according to the sixth embodiment of the present technology. Fig. 16 is a circuit diagram showing an example configuration of a pixel to which an FC gain transistor, a capacitor, and an overflow gate transistor are added and an FD gain transistor is removed according to the sixth embodiment of the present technology. Fig. 17 is a block diagram showing an example of a schematic configuration of a vehicle control system. Fig. 18 is an explanatory diagram showing an example of installation positions of an outside-vehicle information detection unit and an imaging unit.

[0024] Hereinafter, modes for carrying out the present technology (hereinafter referred to as embodiments) will be described. The description will be made in the following order: 1. First embodiment (an example of controlling current based on a comparison result) 2. Second embodiment (an example of controlling charge-voltage conversion efficiency based on a comparison result) 3. Third embodiment (an example of controlling analog gain based on a comparison result) 4. Fourth embodiment (an example of controlling current based on a digital signal) 5. Fifth embodiment (an example of changing the circuit of a pixel block and controlling current based on a comparison result) 6. Sixth embodiment (an example of changing the circuit of a pixel and controlling current based on a comparison result) 7. Example of application to a moving body

[0025] 1 is a block diagram showing an example of the configuration of an imaging device 100 according to a first embodiment of the present technology. The imaging device 100 is a device for capturing image data, and includes an optical unit 110, an image sensor 200, and a DSP (Digital Signal Processing) circuit 120. The imaging device 100 further includes a display unit 130, an operation unit 140, a bus 150, a frame memory 160, a storage unit 170, and a power supply unit 180. The imaging device 100 is expected to be a camera mounted on a smartphone, an in-vehicle camera, or the like.

[0026] The optical unit 110 collects light from a subject and guides it to the image sensor 200. The image sensor 200 generates image data by photoelectric conversion. The image sensor 200 supplies the generated image data to the DSP circuit 120 via a signal line 209.

[0027] The DSP circuit 120 performs predetermined signal processing on the image data, and outputs the processed image data to a frame memory 160 or the like via a bus 150.

[0028] The display unit 130 displays image data. For example, a liquid crystal panel or an organic EL (Electro Luminescence) panel is assumed as the display unit 130. The operation unit 140 generates an operation signal in accordance with a user's operation.

[0029] The bus 150 is a common path for the optical unit 110, image sensor 200, DSP circuit 120, display unit 130, operation unit 140, frame memory 160, storage unit 170, and power supply unit 180 to exchange data with one another.

[0030] The frame memory 160 holds image data. The storage unit 170 stores various data such as image data. The power supply unit 180 supplies power to the image sensor 200, the DSP circuit 120, the display unit 130, and the like.

[0031] 2 is a diagram showing an example of a stacked structure of an image sensor 200 according to the first embodiment of the present technology. The image sensor 200 includes a circuit chip 202 and a pixel chip 201 stacked on the circuit chip 202. These chips are electrically connected via connecting portions such as vias. Note that, in addition to vias, they can also be connected by Cu-Cu bonding or bumps.

[0032] 3 is a block diagram showing an example of the configuration of the image sensor 200 according to the first embodiment of the present technology. The image sensor 200 includes a vertical drive unit 211, a system control unit 212, a DAC (Digital to Analog Converter) 213, a pixel array unit 214, a column readout circuit unit 255, a column signal processing unit 300, a horizontal drive unit 215, and an image processing unit 216. In the pixel array unit 214, a plurality of pixels are arranged in a two-dimensional lattice pattern.

[0033] The pixel array unit 214 is divided into a plurality of pixel blocks 220. For example, two pixels are arranged vertically in each pixel block 220. Note that two pixels may also be arranged horizontally within each pixel block 220.

[0034] Furthermore, the pixel array unit 214 is disposed, for example, on the pixel chip 201, and the remaining circuits are disposed on the circuit chip 202. Note that the circuits disposed on each chip are not limited to those exemplified in the figure.

[0035] The vertical drive section 211 sequentially selects and drives rows of pixel blocks 220 in the pixel array section 214 .

[0036] The system control unit 212 controls the operation timing of the vertical drive unit 211, the DAC 213, the column signal processing unit 300, and the horizontal drive unit 215 in synchronization with the vertical synchronization signal.

[0037] The DAC 213 generates a sawtooth ramp signal and supplies it to the column signal processing unit 300. Inside the column readout circuit unit 255, a load MOS current source (not shown) is arranged.

[0038] The column signal processing unit 300 performs AD (Analog to Digital) conversion processing on pixel signals for each column of the pixel block 220. The column signal processing unit 300 outputs the converted digital signals to the image processing unit 216 under the control of the horizontal driving unit 215.

[0039] The horizontal driving section 215 controls the column signal processing section 300 to output digital signals in sequence.

[0040] The image processing unit 216 performs various processes such as CDS processing and HDR synthesis on the digital signals from the column signal processing unit 300. The image processing unit 216 supplies image data (in other words, frames) in which the processed signals are arranged to the DSP circuit 120.

[0041] It should be noted that the DSP circuit 120 can also perform HDR synthesis instead of the image processing unit 216 .

[0042] 4 is a circuit diagram showing an example of the configuration of a pixel block 220 according to the first embodiment of the present technology. The pixel block 220 includes a photoelectric conversion element 221, a transfer transistor 222, a reset transistor 223, a capacitor 224, floating diffusion layers 225 and 227, and an FD gain transistor 226. The pixel block 220 further includes an amplification transistor 228, a selection transistor 229, an FC gain transistor 230, a capacitor 231, a charge accumulation unit 232, and a photoelectric conversion element 233. Each transistor in the pixel block 220 is, for example, an nMOS (n-channel Metal Oxide Semiconductor) transistor.

[0043] The photoelectric conversion elements 221 and 233 generate electric charges by photoelectric conversion. However, the sensitivity of the photoelectric conversion element 221 is higher than the sensitivity of the photoelectric conversion element 233. The cathode of the photoelectric conversion element 233 is connected to the charge accumulation unit 232.

[0044] The transfer transistor 222 transfers charges from the photoelectric conversion element 221 to the floating diffusion layer 227 in accordance with a drive signal TGL from the vertical drive unit 211 .

[0045] The reset transistor 223 extracts electric charges from the floating diffusion layer 227 and the like in accordance with a drive signal RST from the vertical drive unit 211 to initialize the pixel block 220 .

[0046] The capacitor 224 is inserted between the power supply voltage FD_Vdd and the floating diffusion layer 225. The floating diffusion layers 225 and 227 store electric charges and generate a voltage according to the amount of the electric charges.

[0047] The FD gain transistor 226 is a transistor for controlling charge-voltage conversion efficiency. The FD gain transistor 226 opens and closes the path between the floating diffusion layer 225 and the floating diffusion layer 227 in accordance with a drive signal FDG from the vertical drive unit 211. When the FD gain transistor 226 is in the open state, the charge-voltage conversion efficiency of the pixel block 220 is higher than when it is in the closed state.

[0048] The amplifier transistor 228 forms a source follower circuit and outputs from its drain a voltage corresponding to a voltage input to its gate. The gate of the amplifier transistor 228 is connected to the floating diffusion layer 227.

[0049] The selection transistor 229 outputs the analog signal of the voltage from the amplification transistor 228 as a pixel signal Ain to a vertical signal line VSL in accordance with a drive signal SEL from the vertical drive unit 211. The vertical signal line VSL is wired for each column of the pixel block 220, and the pixel signal Ain is supplied to the column signal processing unit 300 via this signal line.

[0050] The FC gain transistor 230 transfers charges from the charge storage section 232 to the floating diffusion layer 225 in accordance with a drive signal FCG from the vertical drive section 211. The capacitor 231 is inserted between the power supply voltage FC_Vdd and the charge storage section 232.

[0051] The level of the pixel signal Vin when initialized by the reset transistor 223 is hereinafter referred to as the "reset level." This reset level is also called the P-phase level. The level of the pixel signal Vin according to the amount of exposure during charge transfer is hereinafter referred to as the "signal level." This signal level is also called the D-phase level.

[0052] With the circuit configuration illustrated in the figure, the pixel block 220 functions as two adjacent pixels. The circuit within the pixel block 220 is an example of a pixel circuit as defined in the claims.

[0053] [Configuration Example of Column Signal Processing Unit] FIG. 5 is a block diagram showing a configuration example of the column readout circuit unit 255 and the column signal processing unit 300 according to the first embodiment of the present technology.

[0054] A load MOS current source 260 is arranged for each vertical signal line VSL in the column readout circuit unit 255. The power supply side of the load MOS current source 260 is connected to the corresponding vertical signal line VSL, and generates a load MOS current ILM. This load MOS current ILM is variable, and its value can be controlled by a control signal LMSEL.

[0055] Furthermore, a column circuit 310 is arranged for each vertical signal line VSL in the column signal processing unit 300. Each column circuit 310 includes a selector 321, capacitors 322, 323, and 324, a comparator 350, auto-zero switches 325 and 326, a counter 380, a determination unit 330, and a characteristics control unit 340.

[0056] The circuit consisting of the load MOS current source 260 , the selector 321 , the capacitors 322 , 323 and 324 , the comparator 350 , the auto-zero switches 325 and 326 and the counter 380 functions as the ADC 320 .

[0057] The capacitor 322 is inserted between the DAC 213 and the inverting input terminal (−) of the comparator 350. The capacitor 323 is inserted between the selector 321 and the non-inverting input terminal (+) of the comparator 350. The capacitor 324 is inserted between the vertical signal line VSL and the non-inverting input terminal (+) of the comparator 350.

[0058] The selector 321 selects either the ground voltage or the vertical signal line VSL in accordance with a control signal ATT from the system control unit 212, and connects the selected voltage to one end of the capacitor 323. For example, when the control signal ATT is at a low level, the selector 321 selects the ground voltage, and when the control signal ATT is at a high level, the selector 321 selects the vertical signal line VSL.

[0059] When the vertical signal line VSL is selected by the selector 321, the capacitors 323 and 324 are connected in parallel, and the capacitance connected to the comparator 350 is larger than when they are not connected in parallel. This increases the amount of attenuation of the pixel signal Ain, and accordingly reduces the analog gain of the input signal of the ADC 320 (i.e., the pixel signal Ain).

[0060] The comparator 350 compares the pixel signal Ain from the vertical signal line VSL with the ramp signal Rmp from the DAC 213. The comparator 350 outputs a comparison result VCO to the counter 380 and the determination unit 330.

[0061] The auto-zero switches 325 and 326 open and close the path between the input terminal and output terminal of the comparator 350 in accordance with a control signal AZP from the system control unit 212. For example, when the control signal AZP is at a high level, the auto-zero switches 325 and 326 are controlled to a closed state.

[0062] The counter 380 counts the count value over a period until the comparison result VCO is inverted. The counter 380 holds a digital signal Dout indicating the count value and outputs it to the image processing unit 216 under the control of the horizontal driving unit 215.

[0063] The judgment unit 330 judges whether the illuminance of the incident light on the pixel block 220 is higher than a predetermined threshold value based on the output of the ADC 320 (comparison result VCO in the same figure), and outputs a flag F indicating the judgment result to the characteristic control unit 340.

[0064] The characteristics control unit 340 controls the characteristics of the ADC 320 based on the determination result (i.e., flag F) of the determination unit 330. For example, at least one of the value of the load MOS current ILM and the value of the tail current in the comparator 350 is controlled as a characteristic of the ADC 320. The load MOS current ILM is controlled by a control signal LMSEL, and the value of the tail current is controlled by a control signal CMSEL.

[0065] 6 is a circuit diagram showing an example of the configuration of the determination unit 330 according to the first embodiment of the present technology. The determination unit 330 includes a latch circuit 331 and an OR (logical sum) gate 332.

[0066] The OR gate 332 receives the reset signal LARST and the enable signal LAEN from the system control unit 212. The OR gate 332 outputs the logical sum of the reset signal LARST and the enable signal LAEN to the clock terminal CK of the latch circuit 331.

[0067] The latch circuit 331 holds the comparison result VCO from the comparator 350. The comparison result VCO is input to an input terminal D of the latch circuit 331. When the input signal to the clock terminal CK is at a high level, the latch circuit 331 updates and outputs the held value based on the comparison result VCO, and when the input signal to the clock terminal CK is at a low level, the latch circuit 331 fixes the output (in other words, latches). The latch circuit 331 outputs the held value as a flag F from an output terminal Q to the characteristics control unit 340, and outputs an inverted value of the held value as an inversion flag xF from an output terminal xQ.

[0068] 7 is a timing chart showing an example of the operation of the determination unit 330 when reading out the reset level and the signal level in this order according to the first embodiment of the present technology. In the figure, "a" shows the timing chart when the illuminance is low, and "b" shows the timing chart when the illuminance is high. The dotted curves in "a" and "b" in the figure indicate the level of the vertical signal line VSL. The same applies to the subsequent timing charts.

[0069] As shown in the diagram (a), the system control unit 212 supplies a high-level reset signal LARST over a pulse period from timing T11, immediately before the readout of signal level D0. At this time, the comparison result VCO is low, and the value held in the latch circuit 331 is initialized to low. Furthermore, the level of the vertical signal line VSL drops to signal level D0. The higher the illuminance, the greater the amount of drop.

[0070] Then, at timing T12 immediately after timing T11, the level of the ramp signal Rmp rises to its maximum value, and the comparison result VCO becomes high. The level of the ramp signal Rmp at this time corresponds to the dark state.

[0071] Then, the ramp signal Rmp decreases over time, and at timing T13 while it is decreasing, the ramp signal Rmp falls below signal level D0, causing the comparison result VCO to invert to low level. From timing T14 after timing T13, the system control unit 212 supplies a high-level enable signal LAEN over a pulse period. The level of the ramp signal Rmp at this time corresponds to the threshold value used for illuminance determination. The higher the threshold value, the longer the time period from timing T13 to timing T14 is set.

[0072] When the illuminance is equal to or lower than the threshold, the comparison result VCO at timing T14 is low. The latch circuit 331 updates the held value to low and latches the output when the pulse period has elapsed. Immediately after timing T14, the control signal LMSEL is updated based on the flag output by the latch circuit 331.

[0073] On the other hand, when the illuminance is higher than the threshold as illustrated in b in the figure, the amount of drop in the vertical signal line VSL is large, so the comparison result VCO is not inverted at timing T14 and remains at high level.

[0074] As shown in a and b in the figure, the comparison result VCO at timing T14 according to the threshold value indicates whether the illuminance of the incident light is higher than the threshold value.

[0075] Although the image sensor 200 reads out the signal level and then the reset level, it is also possible to read out the signal level and then the reset level.

[0076] 8 is a timing chart showing an example of the operation of the determination unit 330 when reading out the signal level and the reset level in this order according to the first embodiment of the present technology. In the figure, "a" shows the timing chart when the illuminance is low, and "b" shows the timing chart when the illuminance is high.

[0077] As shown in the diagram, the system control unit 212 supplies a high-level reset signal LARST for a pulse period from timing T11 immediately before the readout of the signal level D0. At this time, the comparison result VCO is low, and the value held by the latch circuit 331 is initialized to low.

[0078] Then, the level of the vertical signal line rises to the reset level P0 just before timing T12. The higher the illuminance, the greater the amount of rise. At timing T12, the level of the ramp signal Rmp rises to its maximum value, and the comparison result VCO becomes high level.

[0079] Then, the ramp signal Rmp decreases over time, and at timing T14 during the decrease, the ramp signal Rmp becomes equal to or lower than the signal level D0, and the comparison result VCO is inverted to the low level. The level of the ramp signal Rmp at this time corresponds to the dark state.

[0080] At timing T13, which is prior to timing T14, the system control unit 212 supplies a pulse of the enable signal LAEN. The level of the ramp signal Rmp at this time corresponds to the threshold value used for illuminance determination.

[0081] When the illuminance is equal to or lower than the threshold, the comparison result VCO at timing T13 is high. The latch circuit 331 updates the held value to high and latches the output when the pulse period has elapsed. Immediately after timing T13, the control signal LMSEL is updated based on the flag output by the latch circuit 331.

[0082] On the other hand, as illustrated in b in the figure, when the illuminance is higher than the threshold, the amount of rise in the vertical signal line VSL is large, so that the comparison result VCO is inverted at timing T13 and becomes low level.

[0083] As shown in a and b in the figure, the driving method of reading out the signal level and the reset level in that order is called DDS (Double Data Sampling). In this DDS, the logic of the comparison result VCO is opposite to that in the case of FIG.

[0084] 9 is a diagram illustrating an example of the operation of the characteristics control unit 340 according to the first embodiment of the present technology. The characteristics control unit 340 receives the flag F from the determination unit 330 and the control signal Ctl from the system control unit 212.

[0085] Before the timing for determining the illuminance, a high-level control signal Ctl is input. In this case, the characteristics control unit 340 controls the load MOS current to ICM0 and the tail current to ICM0 regardless of the value of the flag F.

[0086] After the timing for determining the illuminance, a low-level control signal Ctl is input. Furthermore, when the reset level and signal level are read out in this order, flag F becomes low when the illuminance is equal to or lower than the threshold, and becomes high when the illuminance is higher than the threshold. Furthermore, when the signal level and reset level are read out in this order, flag F becomes high when the illuminance is equal to or lower than the threshold, and becomes low when the illuminance is higher than the threshold.

[0087] When the control signal Ctl is at a low level and the flag F is at a value indicating low illuminance (such as a low level), the characteristics control section 340 controls the load MOS current to ICM1 ​​and the tail current to ICM1.

[0088] When the control signal Ctl is at a low level and the flag F is at a value indicating high illuminance (such as a high level), the characteristics control section 340 controls the load MOS current to ICM2 and the tail current to ICM2.

[0089] Here, the following relational expression is established among ILM0, ILM1, and ILM2: ILM0>ILM2>ILM1 (Expression 1)

[0090] Furthermore, the following relational expression holds between ICM0, ICM1, and ICM2: ICM0>ICM2>ICM1 (Equation 2)

[0091] Although the characteristics control section 340 switches both the load MOS current and the tail current in accordance with the illuminance, it is also possible to switch only one of them.

[0092] 10 is a circuit diagram showing an example of the configuration of a load MOS current source 260 according to the first embodiment of the present technology. The load MOS current source 260 includes nMOS transistors 261 to 265 and a capacitor 266.

[0093] The nMOS transistors 261, 263, and 265 are connected in series to the vertical signal line VSL. A predetermined bias voltage is applied to the gate of the nMOS transistor 261.

[0094] The nMOS transistors 262 and 264 are connected in series to the connection node of the nMOS transistors 261 and 263 .

[0095] The characteristics control section 340 supplies a two-bit control signal LMSEL, one bit of which is input to the gate of the nMOS transistor 262 and the other bit is input to the gate of the nMOS transistor 263 .

[0096] A predetermined voltage held in a capacitor 266 is applied to the gates of the nMOS transistors 264 and 265 .

[0097] With the circuit configuration illustrated in the figure, the load MOS current is controlled to one of ILM0, ILM1 and ILM2.

[0098] 11 is a circuit diagram showing an example of the configuration of a comparator 350 according to the first embodiment of the present technology. The comparator 350 includes pMOS (n-channel MOS) transistors 351 to 362, capacitors 363 and 364, nMOS transistors 365 and 366, a tail current source 370, and amplifiers 376 and 377.

[0099] The pMOS transistors 351, 352, 353, and 356 are connected in series to the power supply voltage. The pMOS transistors 354 and 355 are connected in series between the power supply voltage and the connection node of the pMOS transistors 353 and 356. A predetermined bias voltage is applied to the gates of the pMOS transistors 351, 352, and 354.

[0100] The characteristics control section 340 supplies a two-bit control signal SFSEL, one bit of which is input to the gate of the pMOS transistor 353 and the other bit is input to the gate of the pMOS transistor 355 .

[0101] The ramp signal Rmp is input to the gate of the pMOS transistor 356 via the capacitor 322 .

[0102] The pMOS transistors 357 and 358 are connected in parallel to the power supply voltage, and the gate of the pMOS transistor 357 is connected to its own drain and to the gate of the pMOS transistor 358 .

[0103] The nMOS transistor 365 is inserted between the pMOS transistor 357 and the tail current source 370 , and the nMOS transistor 366 is inserted between the pMOS transistor 358 and the tail current source 370 .

[0104] The pMOS transistors 359 and 361 are connected in series between the drain of the pMOS transistor 357 and the gate of the nMOS transistor 365. A predetermined bias voltage is applied to the gates of the pMOS transistors 359 and 361.

[0105] The pMOS transistors 360 and 362 are connected in series between the drain of the pMOS transistor 358 and the gate of the nMOS transistor 366. A predetermined bias voltage is applied to the gates of the pMOS transistors 360 and 362.

[0106] The capacitor 363 is inserted between the connection node of the pMOS transistors 353 and 356 and the gate of the nMOS transistor 365. The pixel signal Ain is input to the gate of the nMOS transistor 366 via a capacitor 364.

[0107] The tail current source 370 supplies a tail current ICM. The tail current source 370 includes nMOS transistors 371 to 374. The nMOS transistors 371 and 372 are connected in series to a common node that is a node to which the nMOS transistors 365 and 366 are commonly connected. The nMOS transistors 373 and 374 are also connected in series to the common node.

[0108] The characteristics control section 340 supplies a 2-bit control signal CMSEL, one bit of which is input to the gate of the nMOS transistor 371, and the remaining bit is input to the gate of the nMOS transistor 373. A predetermined bias voltage is applied to the gates of the nMOS transistors 372 and 374.

[0109] The amplifier 376 amplifies the voltage of the connection node between the pMOS transistor 358 and the nMOS transistor 366 and outputs the amplified voltage to the amplifier 377. The amplifier 377 amplifies the voltage from the amplifier 376 and outputs the comparison result as VCO.

[0110] With the circuit configuration illustrated in the figure, the tail current is controlled to one of ICM0, ICM1, and ICM2. Furthermore, the control signal SFSEL switches the current of the source follower on the lamp side in response to the switching of the tail current.

[0111] 12 is a timing chart showing an example of the operation of the image sensor 200 at the start of exposure according to the first embodiment of the present technology. A horizontal synchronization signal XHS obtained by multiplying the vertical synchronization signal is input to the vertical drive unit 211. The vertical drive unit 211 sequentially selects rows of the pixel block 220 in synchronization with the horizontal synchronization signal XHS and starts exposure. This control method in which the exposure timing differs for each row is called a rolling shutter method.

[0112] During the period of the horizontal synchronization signal XHS from timing T1 to T8, the vertical drive unit 211 sets the drive signal SEL to low level, and supplies the drive signals RST and FDG at high level during the period from timing T2 to T7.

[0113] Furthermore, the vertical drive section 211 supplies a high-level drive signal TGL during the period from timing T3 to T4, and supplies a high-level drive signal FCG during the period from timing T5 to T6.

[0114] Exposure is initiated row by row in sequence according to the control illustrated in the figure. Then, at the end of the exposure period, the column signal processing unit 300 AD converts (in other words, reads) the pixel signals of the two pixels with different sensitivities. The reset level (P-phase level) and signal level (D-phase level) of the pixel signal with the higher sensitivity are set to, for example, "P0" and "D0." The reset level and signal level of the pixel signal with the lower sensitivity are set to, for example, "P1" and "D1."

[0115] These levels are read out in the order P0, D0, D1, P1, or D0, P0, D1, P1, the former being called the "PDDP" order and the latter being called the "DPDP" order.

[0116] The reset levels P0 and P1 are examples of the first and second reset levels set forth in the claims, and the signal levels D0 and D1 are examples of the first and second signal levels set forth in the claims.

[0117] FIG. 13 is a timing chart showing an example of the operation of the image sensor 200 when reading out pixels in the order of PDDP starting from the pixel with the lowest illuminance according to the first embodiment of the present technology.

[0118] The readout period for a certain row is assumed to be from timing T11 to T16. The vertical drive unit 211 supplies a high-level drive signal SEL during the period from timing T11 to T16, and supplies a high-level drive signal RST throughout the pulse period from timing T11. The system control unit 212 also supplies a high-level control signal AZP throughout the pulse period from timing T11. This control generates a reset level P0, which is then AD converted.

[0119] The vertical drive unit 211 supplies a high-level drive signal TGL over a pulse period from timing T12 after the change of the reset level P0. By this control, a signal level D0 is generated and is AD converted.

[0120] Based on the comparison result at timing T13 during the readout period of the signal level D0, the aforementioned determination unit 330 determines whether the illuminance is higher than the threshold. In the figure, the period during which the ramp signal Rmp continues to decrease corresponds to the readout period. Furthermore, when the illuminance is equal to or lower than the threshold, the amount of decrease in the signal level D0 is relatively small.

[0121] In the figure, the end of the read period is set as the timing T13 for determination, but as described above, this timing is set according to the threshold value and is not limited to the end. The same applies to the subsequent timing charts.

[0122] The characteristics control unit 340 switches the load MOS current and tail current based on the result of the illuminance determination. In the figure, since the illuminance is low, the load MOS current and tail current are switched from ILM0 and ICM0 to ILM1 and ICM1.

[0123] The system control section 212 then sets the control signal ATT to high level, and immediately thereafter supplies a pulse of the control signal AZP, generating a signal level D1 which is then AD converted.

[0124] The vertical drive unit 211 supplies the drive signal RST over the pulse period from timing T15 after the conversion of the signal level D1. By this control, a reset level P1 is generated and AD converted.

[0125] Furthermore, in the CDS processing, the image processing unit 216 performs processing to obtain the difference between the reset level P0 and the signal level D0 as a net pixel signal, and processing to obtain the difference between the reset level P1 and the signal level D1 as a net pixel signal. The image processing unit 216 performs HDR synthesis to synthesize these pixel signals.

[0126] The slope of the ramp signal Rmp when reading out P0, D0, D1, and P1 is the same, and the resolution of the ADC 320 when converting each level is the same.

[0127] FIG. 14 is a timing chart showing an example of the operation of the image sensor 200 when reading out pixels in the order of PDDP starting from the pixel with the highest illuminance according to the first embodiment of the present technology.

[0128] When the illumination is higher than the threshold, the amount of reduction in the signal level D0 is relatively large, in which case the load MOS current and tail current are switched from ILM0 and ICM0 to ILM2 and ICM2.

[0129] 13 and 14, the column signal processing unit 300 reads out pixel signals of two pixels with different sensitivities for each pixel, so that the downstream image processing unit 216 can perform HDR synthesis of these pixel signals to expand the dynamic range.

[0130] Furthermore, the characteristics control unit 340 switches the values ​​of the load MOS current and tail current at the time of low sensitivity from ILM0 and ICM0 to ILM1 and ICM1, or ILM2 and ICM2. According to Equations 1 and 2, the currents become smaller by switching, and therefore power consumption can be reduced compared to when no switching is performed at the time of low sensitivity.

[0131] Furthermore, the characteristics control unit 340 switches the values ​​of the load MOS current and tail current to ILM1 and ICM1 ​​when the illuminance is low, and to ILM2 and ICM2 when the illuminance is high. According to Equations 1 and 2, ILM1 and ICM1 ​​are smaller than ILM2 and ICM2, and therefore power consumption can be reduced compared to when there is no switching when the illuminance is low.

[0132] Furthermore, the load MOS current and tail current at the time of conversion of each of the reset level P0 and signal level D0, which are paired in the CDS processing, are the same values ​​(ILM0 and ICM0). Similarly, the load MOS current and tail current at the time of conversion of each of the reset level P1 and signal level D1, which are paired in the CDS processing, are also the same values ​​(ILM1 and ICM1, or ILM2 and ICM2). Therefore, errors at the time of the CDS processing can be suppressed.

[0133] 15 and 16, the signals can also be read out in the order of DPDP. In this case, the signals are converted in the order of signal level D0, reset level P0, signal level D1, and reset level P1. Based on the comparison result at timing T13 within the readout period of reset level P0, the aforementioned determination unit 330 determines whether the illuminance is higher than the threshold value.

[0134] 17 is a flowchart showing an example of the operation of the image sensor 200 according to the first embodiment of the present technology. This operation is started, for example, when a predetermined application for capturing image data is executed. The same figure also shows a flow when reading out in the order of PDDP.

[0135] The image sensor 200 selects a row to be read (step S901), initializes the load MOS current and tail current to ILM0 and ICM0 (step S902), reads the reset level P0 (step S903), and then reads the signal level D0 (step S904).

[0136] The image sensor 200 determines whether the illuminance of each pixel in a row is higher than a threshold (step S905). If the illuminance is equal to or lower than the threshold (step S905: No), the image sensor 200 switches the load MOS current and tail current of that pixel to ILM1 and ICM1 ​​(step S906). On the other hand, if the illuminance is higher than the threshold (step S905: Yes), the image sensor 200 switches the load MOS current and tail current of that pixel to ILM2 and ICM2 (step S907).

[0137] Steps S905 to S907 are executed in parallel for each pixel block 220 in a row. In the figure, the processing of one pixel block 220 is described.

[0138] Then, the image sensor 200 reads out the signal level D1 (step S908), and then reads out the reset level P1 (step S909).

[0139] The image sensor 200 determines whether or not reading of all rows has been completed (step S910). If there are rows that have not been read (step S901: No), the image sensor 200 repeatedly executes step S901 and subsequent steps. If reading of all rows has been completed (step S910: Yes), the image sensor 200 performs image processing such as CDS processing and HDR composition (step S911), and ends the operation for capturing an image.

[0140] When multiple sets of image data are captured consecutively, the image sensor 200 repeatedly executes steps S901 to S911 in synchronization with a vertical synchronization signal.

[0141] As described above, according to the first embodiment of the present technology, the characteristics control unit 340 controls the load MOS current and the tail current of the ADC 320 based on the determination result of the illuminance, thereby making it possible to reduce power consumption.

[0142] Furthermore, the load MOS current and tail current during conversion of the reset level and signal level, which are paired in the CDS process, are controlled to the same value, thereby making it possible to suppress errors during the CDS process.

[0143] In the first embodiment described above, the resolution of the ADC 320 is constant, but this configuration may not be able to sufficiently suppress degradation of image quality due to horizontal stripe noise (in other words, streaking). The image sensor 200 in this modification of the first embodiment differs from the first embodiment in that the resolution of the ADC 320 is changed.

[0144] FIG. 18 is a timing chart showing an example of the operation of the image sensor when reading out pixels in the order of PDDP starting from the pixel with the lowest illuminance in the modification of the first embodiment of the present technology.

[0145] FIG. 19 is a timing chart showing an example of the operation of the image sensor when reading out pixels in the order of PDDP starting from the pixel with the highest illuminance according to the modification of the first embodiment of the present technology.

[0146] 18 and 19 , the system control unit 212 sets the resolution of the ADC 320 when reading out the higher sensitivity signals P0 and D0 to be higher than the resolution when reading out the lower sensitivity signals D1 and P1. The resolution can be switched, for example, by controlling the analog gain of the comparator 350. To increase the resolution, the analog gain can be increased.

[0147] Streaking is more likely to occur when the characteristics control unit 340 reduces currents such as the load MOS current. On the other hand, the criteria for streaking are more relaxed as the resolution of the ADC 320 becomes lower. Therefore, by reducing currents such as the load MOS current when reading out low-sensitivity pixel signals and lowering the resolution of the ADC 320 at that time, streaking can be made less noticeable and image quality can be improved.

[0148] The resolution of the ADC 320 can be changed in the same way when reading out in the order of DPDP.

[0149] In this way, according to the modified example of the first embodiment of the present technology, the resolution of the ADC 320 is lowered when the characteristic control unit 340 reduces the load MOS current, etc., so that the effect of streaking can be suppressed and image quality can be improved.

[0150] 2. Second Embodiment In the first embodiment described above, the illuminance determination result was used to control the current, but this configuration makes it difficult to achieve higher resolution image data or further reduce power consumption. The image sensor 200 in this second embodiment differs from the first embodiment in that it controls the charge-voltage conversion efficiency of the pixels based on the illuminance determination result.

[0151] 20 is a block diagram showing a configuration example of the pixel 240 and the column signal processing unit 300 according to the second embodiment of the present technology. In the second embodiment, the pixel array unit 214 has a plurality of pixels 240 arranged in a two-dimensional lattice pattern.

[0152] The pixel 240 includes a photoelectric conversion element 241 , a transfer transistor 242 , a reset transistor 243 , a capacitor 244 , floating diffusion layers 245 and 247 , an FD gain transistor 246 , an amplification transistor 248 , and a selection transistor 249 .

[0153] The photoelectric conversion element 241 generates electric charges through photoelectric conversion. The transfer transistor 242 transfers electric charges from the photoelectric conversion element 241 to the floating diffusion layer 247 in accordance with a drive signal TGL. The reset transistor 243 initializes the pixel 240 in accordance with a drive signal RST.

[0154] The capacitor 244 is inserted between the power supply voltage FD_Vdd and the floating diffusion layer 245. The floating diffusion layers 245 and 247 store electric charges and generate a voltage according to the amount of the electric charges.

[0155] The FD gain transistor 246 is a transistor for controlling charge-voltage conversion efficiency. The amplification transistor 248 forms a source follower circuit and outputs from its drain a voltage corresponding to a voltage input to its gate. The selection transistor 249 outputs an analog signal of the voltage from the amplification transistor 248 as a pixel signal Ain to the vertical signal line VSL in accordance with a drive signal SEL.

[0156] Furthermore, the characteristic control unit 340 of the second embodiment differs from that of the first embodiment in that it controls the charge-voltage conversion efficiency of the pixel 240 by the drive signal FDG based on the flag F from the determination unit 330 .

[0157] The circuit in the pixel 240 is an example of a pixel circuit described in the claims.

[0158] 21 is a diagram showing an example of the operation of the characteristics control unit 340 according to the second embodiment of the present technology. The characteristics control unit 340 receives a 2-bit control signal Ctl and a flag F as input.

[0159] When the control signal Ctrl is binary "00" or "11" and the flag F is a value indicating low illuminance (such as a low level), the characteristics control unit 340 sets the drive signal FDG to a low level. This increases the charge-voltage conversion efficiency of the pixel 240 above a predetermined value. This conversion efficiency is hereinafter referred to as "HCG."

[0160] When the control signal Ctl is binary "00" or "11" and the flag F is a value indicating high illuminance (such as a high level), the characteristics control unit 340 sets the drive signal FDG to a high level. This causes the charge-voltage conversion efficiency of the pixel 240 to become lower than a predetermined value. This conversion efficiency is hereinafter referred to as "LCG."

[0161] Furthermore, when the control signal Ctl is "01" in binary, the characteristics control unit 340 forcibly sets the drive signal FDG to a low level regardless of the flag F. When the control signal Ctl is "10" in binary, the characteristics control unit 340 forcibly sets the drive signal FDG to a high level regardless of the flag F.

[0162] FIG. 22 is a timing chart showing an example of the operation of the image sensor when reading out pixels in the order of PPDD starting from the pixel with the lowest illuminance according to the second embodiment of the present technology.

[0163] The vertical drive unit 211 supplies a high-level drive signal SEL during the period from timing T11 to T16, and supplies a high-level drive signal RST throughout the pulse period from timing T11. The system control unit 212 also controls the characteristics control unit 340 to supply a high-level drive signal FDG during the period from timing T11 to timing T12. This control generates a reset level P0 with a low charge-to-voltage conversion efficiency (LCG), which is then AD-converted.

[0164] After timing T13, the drive signal FDG goes low, so that the reset level P1 is generated with high charge-voltage conversion efficiency (HCG) and is AD converted.

[0165] The vertical drive unit 211 supplies a high-level drive signal TGL over a pulse period from timing T13 after the change of the reset level P1. By this control, a signal level D1 is generated in the HCG and is AD converted.

[0166] Based on the comparison result at timing T15 within the readout period of signal level D1, the determination unit 330 determines whether the illuminance is higher than the threshold. If the illuminance is equal to or lower than the threshold, the characteristics control unit 340 keeps the drive signal FDG at a low level. As a result, the signal level D1 generated by the HCG is read out during the period from timing T15 to T16. The level generated by the HCG the first time is designated D1_1, and the level generated by the HCG the second time is designated D1_2.

[0167] The image processing unit 216 at the subsequent stage calculates the average value of the signal levels D1_1 and D1_2, and calculates the difference between this average value and the reset level P1. This averaging of the signal levels reduces noise, making it possible to obtain image data with higher resolution than in the first embodiment. Note that the reset level P0 is not used in the CDS processing and is discarded.

[0168] FIG. 23 is a timing chart showing an example of the operation of the image sensor 200 when reading out pixels in the order of PPDD starting from the pixel with the highest illuminance according to the second embodiment of the present technology.

[0169] If it is determined based on the comparison result at timing T15 that the illuminance is higher than the threshold, the characteristics control unit 340 controls the drive signal FDG to a high level. As a result, the signal level D0 generated by the LCG is read out during the period from timing T15 to T16. In this case, the image processing unit 216 performs CDS processing to determine the difference between the reset level P0 and the signal level D0. Note that the reset level P1 and the signal level D1 are not used in the CDS processing and are discarded.

[0170] As shown in FIGS. 22 and 23, when the reset level P0, the reset level P1, the signal level D1, and the signal level (D1 or D0) are read out in this order, this order is referred to as "PPDD."

[0171] As shown in FIGS. 24 and 25, the data can also be read in the order of the PDDPs.

[0172] FIG. 24 is a timing chart showing an example of the operation of the image sensor 200 when reading out pixels in the order of PDDP starting from the pixel with the lowest illuminance according to the second embodiment of the present technology.

[0173] The column signal processing unit 300 sequentially reads out the reset level P0 and the signal level D0 generated by the HCG.

[0174] Based on the comparison result at timing T13 within the readout period of signal level D0, the determination unit 330 determines whether the illuminance is higher than the threshold. If the illuminance is equal to or lower than the threshold, the characteristics control unit 340 keeps the drive signal FDG at a low level. As a result, the reset level P0 and signal level D0 generated by the HCG are read out during the period from timing T14 to T16. The levels generated by the HCG the first time are designated P0_1 and D0_1, and the levels generated by the HCG the second time are designated D0_2 and P0_2.

[0175] The image processing unit 216 at the subsequent stage calculates the average value of the reset levels P0_1 and P0_2 and the average value of the signal levels D1_1 and D1_2, and calculates the difference therebetween.

[0176] FIG. 25 is a timing chart showing an example of the operation of the image sensor 200 when reading out pixels in the order of PDDP starting from the pixel with the highest illuminance according to the second embodiment of the present technology.

[0177] First, the column signal processing unit 300 sequentially reads out the reset level P0 and the signal level D0 generated by the HCG.

[0178] Based on the comparison result at timing T13 during the readout period of signal level D0, the determination unit 330 determines whether the illuminance is higher than the threshold. If the illuminance is higher than the threshold, the characteristics control unit 340 controls the drive signal FDG to a high level. As a result, the reset level P1 and signal level D1 generated by the LCG are read out during the period from timing T14 to T16. The downstream image processing unit 216 performs CDS processing to determine the difference between the reset level P1 and the signal level D1. Note that the reset level P0 and signal level D0 are discarded.

[0179] The characteristics control section 340 can control the charge-voltage conversion efficiency in accordance with the illuminance, and can also control the current such as the load MOS current in accordance with the illuminance.

[0180] As described above, according to the second embodiment of the present technology, the characteristics control unit 340 controls the charge-voltage conversion efficiency of the pixel 240 based on the illuminance determination result, thereby enabling image data to have higher definition.

[0181] [First Modification] In the second embodiment described above, the charge-voltage conversion efficiency is controlled in accordance with the illuminance to increase the resolution of the image data, but power consumption can also be reduced. The image sensor 200 in this first modification of the second embodiment differs from the second embodiment in that the charge-voltage conversion efficiency is controlled in accordance with the illuminance, and the ADC 320 is stopped in accordance with the illuminance.

[0182] 26 is a block diagram showing a configuration example of a pixel 240 and a column signal processing unit 300 in a first modified example of the second embodiment of the present technology. The characteristic control unit 340 in the first modified example of the second embodiment differs from the second embodiment in that it controls charge-voltage conversion efficiency based on a flag F and stops the ADC 320 by an enable signal CTEN when the illuminance is equal to or lower than a threshold.

[0183] 27 is a circuit diagram showing an example of a configuration of a counter 380 according to a first modified example of the second embodiment of the present technology. The counter 380 includes a delay unit 381, an output control unit 382, ​​a Gray code latch 383, a binary code conversion unit 384, an adder 385, a metastable mask circuit 386, a binary counter 388, and a data latch 390.

[0184] The delay unit 381 delays the comparison result VCO from the comparator 350 for a predetermined time. The delay unit 381 supplies the delayed signal to the output control unit 382 as a delayed signal dVCO.

[0185] The output control unit 382 receives the comparison result VCO, delay signal dVCO, and enable signal CTEN from the comparator 350, delay unit 381, and characteristics control unit 340. The output control unit 382 generates a control signal CMout based on these signals and supplies it to the Gray code latch 383.

[0186] The gray code latch 383 receives the gray code from the gray code generation unit 400 and the control signal CMout.

[0187] The gray code generator 400 generates a 5-bit gray code over the pixel signal readout period. This gray code is increased or decreased in synchronization with a predetermined clock signal and is used in common for all columns.

[0188] The Gray code latch 383 holds the Gray code in accordance with the control signal CMout. The Gray code latch 383 supplies the held code to a binary code conversion unit 384. The clock signal of the most significant bit of the code from the Gray code latch 383 is supplied to a metastable mask circuit 386.

[0189] The binary code converter 384 converts the 5-bit Gray code into a binary code and supplies it to the adder 385 .

[0190] The adder 385 adds the 7-bit upper bit string to the 5-bit binary code to generate a 14-bit binary code, which is supplied to the multiplexer 387. The logical values ​​of all bits in the upper bit string are "0".

[0191] The metastable mask circuit 386 supplies a carry signal. Outside of a predetermined mask period, the metastable mask circuit 386 supplies the clock signal from the Gray code latch 383 as a carry signal to the multiplexer 387. This carry signal is used to carry the least significant bit of the seven most significant bits of the binary counter 388. However, measures to prevent metastable states are required for the carry signal. Here, metastable states refer to, for example, when the timing of the edge of the carry signal and the inversion of the comparison result VCO are close, a carry does not occur on the Gray code side but does occur on the binary code side, resulting in data skipping. By setting a mask period based on the timing of the inversion of the comparison result VCO, the metastable mask circuit 386 can prevent metastable states.

[0192] The multiplexer 387 selects either the binary code from the adder 385 or the carry signal from the metastable mask circuit 386 under the control of the system control unit 212 and supplies the selected signal to the binary counter 388 .

[0193] The binary counter 388 counts the 14-bit binary code BIN and supplies it to the data latch 390. The data latch 390 holds the binary code BIN and outputs it as a digital signal Dout under the control of the horizontal drive unit 215.

[0194] 28 is a diagram showing an example of the operation of the characteristics control unit 340 and the output control unit 382 in the first modified example of the second embodiment of the present technology. In the figure, "a" shows an example of the operation of the characteristics control unit 340, and "b" shows an example of the operation of the output control unit 382.

[0195] As illustrated in FIG. 10A, when controlling the drive signal FDG in accordance with the flag F, the characteristics control section 340 also controls the enable signal CTEN in accordance with the flag F.

[0196] For example, if the control signal Ctl is "00" or "11" in binary and the flag F is a value indicating low illuminance (such as a low level), the characteristics control unit 340 sets the enable signal CTEN to a value indicating disable (such as a low level). If the control signal Ctl is "00" or "11" in binary and the flag F is a value indicating high illuminance (such as a high level), the characteristics control unit 340 sets the enable signal CTEN to a value indicating enable (such as a high level).

[0197] Furthermore, when the control signal Ctl is "10" or "01" in binary, the enable signal CTEN is controlled to a high level.

[0198] As illustrated in b in the same figure, when the enable signal CTEN is at a disable value, the output control unit 382 sets the control signal CMout to a value indicating count stop (such as a low level) regardless of whether an inversion has occurred.

[0199] When the enable signal CTEN is at the enable value and the comparison result VCO is equal to the delay signal dVCO, the output control section 382 sets the control signal CMout to a value (such as a high level) that indicates continuation of counting.

[0200] When the enable signal CTEN is at the enable value and the comparison result shows that VCO is different from the delay signal dVCO (that is, inversion occurs), the output control section 382 sets the control signal CMout to a low level.

[0201] FIG. 29 is a timing chart showing an example of the operation of the image sensor when reading out pixels in PPDD order starting from the pixel with the lowest illuminance in the first modified example of the second embodiment of the present technology.

[0202] In the first modification of the second embodiment, as in the second embodiment, the reset level P0 generated by the LCG, the reset level P1 generated by the HCG, and the signal level D1 generated by the HCG are read out in sequence. The gray period of the ADC 320 in the figure indicates the period during which counting continues. At the start of this period, the Gray code and binary code are initialized. Furthermore, the output of the data latch 390 is latched at the timing when the comparison result VCO is inverted.

[0203] Based on the comparison result at timing T15 within the readout period of signal level D1, the determination unit 330 determines whether the illuminance is higher than the threshold. If the illuminance is equal to or lower than the threshold, the characteristics control unit 340 keeps the drive signal FDG at a low level. Furthermore, the characteristics control unit 340 switches the enable signal CTEN from an enable value to a disable value. This control stops the ADC 320 from counting.

[0204] Furthermore, the image processing unit 216 performs CDS processing to obtain the difference between the reset level P1 and the signal level D1.

[0205] FIG. 30 is a timing chart showing an example of the operation of the image sensor when reading out pixels in PPDD order starting from the pixel with the highest illuminance according to the first modified example of the second embodiment of the present technology.

[0206] If the illuminance is higher than the threshold value, the characteristic control unit 340 keeps the enable signal CTEN at the enable value, so that the signal level D0 is further read out.

[0207] Furthermore, the image processing unit 216 performs CDS processing to obtain the difference between the reset level P0 and the signal level D0.

[0208] 29 and 30, the characteristics control unit 340 stops the ADC 320 when the illuminance is equal to or lower than a threshold value, thereby reducing power consumption compared to the second embodiment.

[0209] 31 and 32, the signals may be read out in the order of PDDP. In this case, if the illuminance is equal to or lower than the threshold at timing T13, the characteristics control unit 340 stops the ADC 320 thereafter.

[0210] As described above, according to the first modified example of the second embodiment of the present technology, the characteristics control unit 340 stops the ADC 320 when the illuminance is equal to or lower than the threshold value, thereby reducing power consumption.

[0211] [Second Modification] In the second embodiment described above, the charge-voltage conversion efficiency of the pixel 240 is controlled, but instead, it is also possible to control the charge-voltage conversion efficiency of the pixel block 220 of the first embodiment. The image sensor 200 in this second embodiment differs from the second embodiment in that the charge-voltage conversion efficiency of the pixel block 220 is controlled based on the result of illuminance determination.

[0212] FIG. 33 is a block diagram showing an example of the configuration of the pixel block 220 and the column signal processing unit 300 in the second modified example of the second embodiment of the present technology.

[0213] In the second modification of the second embodiment, the circuit configuration of the pixel block 220 is the same as that of the first embodiment, except that a drive signal FDG from the characteristics control unit 340 is input to the gate of the FD gain transistor 226.

[0214] The characteristic control unit 340 reduces the charge-voltage conversion efficiency of the pixel block 220 below a predetermined value, and the ADC 320 reads out the reset level and signal level of the pixel signal of the pixel with the higher sensitivity of the two pixels in the pixel block 220. This pixel signal is designated "PD2LCG," and its reset level and signal level are designated "P0" and "D0."

[0215] The determination unit 330 then determines whether the illuminance is higher than the threshold value within the readout period of D0. Based on the determination result, the characteristics control unit 340 controls the charge-voltage conversion efficiency, and the ADC 320 reads out the reset level and signal level of the pixel signal of the pixel with the lower sensitivity of the two pixels. This pixel signal is designated "PD1." Furthermore, PD1 with a high charge-voltage conversion efficiency is designated "PD1HCG," and its reset level and signal level are designated "P1" and "D1." On the other hand, PD1 with a low charge-voltage conversion efficiency is designated "PD1LCG," and its reset level and signal level are designated "P2" and "D2."

[0216] That is, after PD2LCG (P0 and D0) is read out, PD1HCG (P1 and D1) or PD1LCG (P2 and D2) is read out depending on the illuminance.

[0217] Here, an image sensor that sequentially reads out PD2LCG, PD1HCG, and PD1LCG without determining whether the illuminance is higher than a threshold value is assumed as a comparative example.

[0218] 34 and 35 show an example of the operation of the image sensor when reading out pixels in the comparative example. Fig. 34 shows a timing chart when reading out pixels with low illuminance, and Fig. 35 shows a timing chart when reading out pixels with high illuminance.

[0219] As illustrated in FIGS. 34 and 35, the image sensor of the comparative example reads out pixel signals in the order of PD2LCG, PD1HCG, and PD1LCG, regardless of the illuminance.

[0220] 36 is a timing chart showing an example of the operation of the image sensor when reading out DPDPs in order from pixels with low illuminance in the second modification of the second embodiment of the present technology. During the period from timing T11 to T14, the ADC 320 reads out PD2LCGs of high-sensitivity pixels. Based on the comparison result VCO at timing T14, the determination unit 330 determines whether the illuminance is higher than the threshold value.

[0221] If the illuminance is equal to or lower than the threshold, the characteristics control unit 340 sets the drive signal FDG to low level after timing T14, thereby switching to the HCG with higher charge-voltage conversion efficiency and reading out PD1HCG of the low-sensitivity pixel.

[0222] 37 is a timing chart showing an example of the operation of the image sensor when reading out pixels in order from the pixel with the highest illuminance to the pixel with the lowest illuminance in the second modification of the second embodiment of the present technology. Control up to timing T14 is the same as that in FIG.

[0223] If the illuminance is equal to or lower than the threshold, the characteristics control unit 340 sets the drive signal FDG to high level after timing T14, thereby switching to the LCG with the lower charge-voltage conversion efficiency and reading out PD1LCG of the low-sensitivity pixel.

[0224] 34 to 37, by reading out PD1HCG or PD1LCG according to the illuminance after reading out PD2LCG, the readout speed becomes faster than in the comparative example in which PD2LCG, PD1HCG, and PD1LCG are read out in sequence, thereby making it possible to improve the frame rate.

[0225] As described above, according to the second modified example of the second embodiment of the present technology, after reading out PD2LCG, the charge-voltage conversion efficiency is controlled according to the illuminance, and PD1HCG or PD1LCG is read out, thereby enabling the frame rate to be improved compared to the comparative example.

[0226] 3. Third Embodiment In the second embodiment described above, the illuminance determination result was used to control the current, but this configuration makes it difficult to increase the resolution of image data and further reduce power consumption. The image sensor 200 in this third embodiment differs from the first embodiment in that the analog gain of the ADC 320 is controlled based on the illuminance determination result.

[0227] 38 is a block diagram showing a configuration example of a column signal processing unit 300 according to the third embodiment of the present technology. The characteristics control unit 340 according to the third embodiment differs from the first embodiment in that it controls the analog gain of the ADC 320 using a control signal ATT based on the determination result of the illuminance.

[0228] FIG. 39 is a diagram showing an example of the operation of the characteristic control unit 340 according to the third embodiment of the present technology.

[0229] When the control signal Ctl is "00" or "11" in binary and the flag F is a value indicating low illuminance (such as a low level), the characteristics control unit 340 sets the control signal ATT to a low level. This causes the analog gain of the ADC 320 (attenuation gain in the figure) to be higher than a predetermined value. This gain is hereinafter referred to as high gain or "HG."

[0230] When the control signal Ctl is "00" or "11" in binary and the flag F is a value indicating high illuminance (such as a high level), the characteristics control unit 340 sets the control signal ATT to a high level. This causes the analog gain of the ADC 320 to become lower than a predetermined value. This gain is hereinafter referred to as low gain or "LG."

[0231] Furthermore, when the control signal Ctl is "01" in binary, the characteristics control unit 340 forcibly sets the control signal ATT to low level regardless of the flag F. When the control signal Ctl is "10" in binary, the characteristics control unit 340 forcibly sets the control signal ATT to high level regardless of the flag F.

[0232] FIG. 40 is a timing chart showing an example of the operation of the image sensor when reading out pixels in the order of PPDD starting from the pixel with the lowest illuminance according to the third embodiment of the present technology.

[0233] The system control section 212 controls the characteristics control section 340 to supply a high-level control signal ATT from timing T11 to timing T12. During this period, the reset level P0 is AD converted at low gain (LG).

[0234] After timing T13, the control signal ATT goes low, so that the reset level P1 and the signal level D1 are AD converted in this order at high gain (HG).

[0235] Based on the comparison result at timing T15 within the readout period of signal level D1, the determination unit 330 determines whether the illuminance is higher than the threshold. If the illuminance is equal to or lower than the threshold, the characteristics control unit 340 keeps the control signal ATT at a low level. As a result, signal level D1 is read out at high gain during the period from timing T15 to T16. The level read out at high gain the first time is designated D1_1, and the level read out at high gain the second time is designated D1_2.

[0236] The image processing unit 216 at the subsequent stage calculates the average value of the signal levels D1_1 and D1_2, and calculates the difference between this average value and the reset level P1. This averaging of the signal levels reduces noise, and it is possible to obtain image data with higher resolution than in the first embodiment.

[0237] FIG. 41 is a timing chart showing an example of the operation of the image sensor when reading out PPDDs in order from pixels with higher illuminance according to the third embodiment of the present technology.

[0238] If it is determined based on the comparison result at timing T15 that the illuminance is higher than the threshold, the characteristics control unit 340 controls the control signal ATT to a high level. As a result, the signal level D0 is read out at a low gain during the period from timing T15 to T16. In this case, the image processing unit 216 performs CDS processing to determine the difference between the reset level P0 and the signal level D0.

[0239] As shown in FIGS. 42 and 43, the data can also be read in the order of the PDDPs.

[0240] FIG. 42 is a timing chart showing an example of the operation of the image sensor 200 when reading out pixels in the order of PDDP starting from the pixel with the lowest illuminance according to the third embodiment of the present technology.

[0241] The column signal processing unit 300 sequentially reads out the reset level P0 and the signal level D0 with high gain.

[0242] Based on the comparison result at timing T13 within the readout period of signal level D0, the determination unit 330 determines whether the illuminance is higher than the threshold. If the illuminance is equal to or lower than the threshold, the characteristics control unit 340 keeps the control signal ATT at a low level. As a result, the signal level D0 and reset level D0 are read out at high gain during the period from timing T14 to T16. The levels read out at high gain the first time are designated P0_1 and D0_1, and the levels read out at high gain the second time are designated D0_2 and P0_2.

[0243] The image processing unit 216 at the subsequent stage calculates the average value of the reset levels P0_1 and P0_2 and the average value of the signal levels D0_1 and D0_2, and calculates the difference therebetween.

[0244] FIG. 43 is a timing chart showing an example of the operation of the image sensor 200 when reading out pixels in the order of PDDP starting from the pixel with the highest illuminance according to the third embodiment of the present technology.

[0245] The column signal processing unit 300 sequentially reads out the reset level P0 and the signal level D0 with high gain.

[0246] Based on the comparison result at timing T13 within the readout period of signal level D0, the determination unit 330 determines whether the illuminance is higher than the threshold. If the illuminance is higher than the threshold, the characteristics control unit 340 controls the control signal ATT to a high level. As a result, the signal level D1 and reset level P1 are read out at low gain during the period from timing T14 to T16. The image processing unit 216 at the downstream stage performs CDS processing to determine the difference between the reset level P1 and the signal level D1.

[0247] It should be noted that while the analog gain is controlled in accordance with the illuminance, it is also possible to control the current such as the load MOS current and the charge-voltage conversion efficiency in accordance with the illuminance.

[0248] As described above, according to the third embodiment of the present technology, the characteristics control unit 340 controls the analog gain of the ADC 320 based on the determination result of the illuminance, and therefore, it is possible to increase the definition of the image data.

[0249] [First Modification] In the third embodiment described above, the analog gain is controlled in accordance with the illuminance to increase the resolution of the image data, but power consumption can also be reduced. Image sensor 200 in this first modification of the third embodiment differs from the third embodiment in that it controls the analog gain in accordance with the illuminance and stops ADC 320 in accordance with the illuminance.

[0250] 44 is a block diagram showing a configuration example of a column signal processing unit 300 in a modification of the third embodiment of the present technology. The characteristic control unit 340 in the first modification of the third embodiment differs from the third embodiment in that it controls charge-voltage conversion efficiency based on a flag F and stops the ADC 320 by an enable signal CTEN when the illuminance is equal to or lower than a threshold.

[0251] The method of controlling the enable signal CTEN in the first modification of the third embodiment is similar to that illustrated in FIG.

[0252] FIG. 45 is a timing chart showing an example of the operation of the image sensor when reading out pixels in PPDD order starting from the pixel with the lowest illuminance according to the first modified example of the third embodiment of the present technology.

[0253] In the first modification of the third embodiment, as in the third embodiment, the reset level P0 is read out with a low gain, and the reset level P1 and the signal level D1 are read out with a high gain.

[0254] Based on the comparison result at timing T15 within the readout period of signal level D1, the determination unit 330 determines whether the illuminance is higher than the threshold. If the illuminance is equal to or lower than the threshold, the characteristics control unit 340 keeps the control signal ATT at a low level. Furthermore, the characteristics control unit 340 switches the enable signal CTEN from an enable value to a disable value, thereby stopping the ADC 320.

[0255] Furthermore, the image processing unit 216 performs CDS processing to obtain the difference between the reset level P1 and the signal level D1.

[0256] FIG. 46 is a timing chart showing an example of the operation of the image sensor when reading out pixels in PPDD order starting from the pixel with the highest illuminance according to the first modified example of the third embodiment of the present technology.

[0257] If the illuminance is higher than the threshold value, the characteristic control unit 340 keeps the enable signal CTEN at the enable value, so that the signal level D0 is further read out.

[0258] Furthermore, the image processing unit 216 performs CDS processing to obtain the difference between the reset level P0 and the signal level D0.

[0259] 45 and 46, the characteristics control unit 340 stops the ADC 320 when the illuminance is equal to or lower than a threshold value, thereby reducing power consumption compared to the third embodiment.

[0260] It should be noted that the data may be read out in the order of PDDP, as illustrated in Figures 47 and 48. In this case, if the illuminance is equal to or lower than the threshold at timing T13, the characteristics control section 340 stops the ADC 320 thereafter.

[0261] As described above, according to the first modified example of the third embodiment of the present technology, the characteristics control unit 340 stops the ADC 320 when the illuminance is equal to or lower than the threshold value, thereby reducing power consumption.

[0262] [Second Modification] In the third embodiment described above, the analog gain is controlled in accordance with the illuminance to increase the resolution of the image data, but it is preferable to further increase the readout speed. Image sensor 200 in this second modification of the third embodiment differs from the third embodiment in that the readout order is changed based on the illuminance determination result.

[0263] 49 is a diagram showing an example of a read operation of the image sensor 200 in the second modified example of the third embodiment of the present technology and a comparative example. In the drawing, "a" shows the read operation in the second modified example of the third embodiment, and "b" shows the read operation in the comparative example.

[0264] The pixel signal of the pixel with the higher sensitivity of the two pixels is designated PD2, and the pixel signal of the pixel with the lower sensitivity is designated PD1. PD2 read out at low gain is designated PD2LG. PD1 read out at low gain is designated PD1LG, and PD1 read out at high gain is designated PD1HG.

[0265] As shown in the diagram a, the ADC 320 in the second modification of the third embodiment converts PD2LG by the DDS method within the period from timing T21 to T22. Then, based on the comparison result at timing T22, the determination unit 330 determines whether the illuminance is higher than the threshold value.

[0266] When the illuminance is equal to or lower than the threshold, the ADC 320 converts the reset level (P phase) of PD1LG during the period from timing T22 to T23. Then, during the period from timing T23 to T24, the ADC 320 converts the reset level and signal level of PD1HG, in that order. The period from timing T24 to T25 is set as a waiting time to match the pixels with high illuminance. Next, during the period from timing T25 to T26, the ADC 320 converts the signal level (D phase) of PD1LG. In this way, when the illuminance is high, the levels are read out in the order of PPDD from timing T22 onwards.

[0267] On the other hand, if the illuminance is higher than the threshold, the period from timing T22 to T23 is set as a waiting time. Then, during the period from timing T23 to T24, the ADC 320 converts the reset level and signal level of PD1LG in that order. Next, during the period from timing T24 to T26, the ADC 320 converts PD1LG using the DDS method. In this way, when the illuminance is high, the levels are read out in the order of PDDP from timing T22 onwards.

[0268] As illustrated in b in the figure, in the comparative example, the ADC 320 converts PD2LG by the DDS method within the period from timing T21 to T22.

[0269] The illuminance is not determined, and the ADC 320 converts the reset level (P phase) of PD1LG during the period from timing T22 to T23. Then, during the period from timing T23 to T24, the ADC 320 converts the reset level and signal level of PD1HG, in that order. Next, during the period from timing T24 to T25, the ADC 320 converts the signal level (D phase) of PD1LG. Then, during the period from timing T25 to T27, the ADC 320 converts PD1HG using the DDS method.

[0270] As shown in a and b in the figure, by switching the analog gain according to the illuminance and switching the readout order to either PPDD or PDDP, the readout speed can be increased compared to the comparative example in which the readout order is not switched. In the examples of a and b in the figure, the readout time for the reset level and signal level of the pixel signal of one pixel is T ＡＤ Then, the readout time for each row is 0.5×T ＡＤ can be shortened by just

[0271] FIG. 50 is a timing chart showing an example of the operation of the image sensor when reading out from a pixel with low illuminance in the second modified example of the third embodiment of the present technology.

[0272] During the period from timing T21 to T22, the ADC 320 converts the signal level D0 of the PD2LG, and then converts the reset level P0. Then, based on the comparison result at timing T22, the determination unit 330 determines whether the illuminance is higher than the threshold value.

[0273] When the illuminance is equal to or lower than the threshold, the ADC 320 converts the reset level P1 of PD1LG during the period from timing T22 to T23. Then, the ADC 320 converts the reset level P2 of PD1HG during the period from timing T23 to T24, and then converts the signal level D2.

[0274] After the waiting time from timing T24 to T25 has elapsed, the ADC 320 converts the signal level D1 of PD1LG during the period from timing T25 to T26. In this way, when the illuminance is high, the levels are read out in the order of P1, P2, D2, and D1 from timing T22 onwards.

[0275] FIG. 51 is a timing chart showing an example of the operation of the image sensor when reading out from a pixel with high illuminance in the second modified example of the third embodiment of the present technology.

[0276] If the illuminance is higher than the threshold, after the waiting time from timing T22 to T23 has elapsed, the ADC 320 converts the reset level P2 of PD1HG and then converts the signal level D2 within the period from timing T23 to T24.

[0277] Then, during the period from timing T24 to T26, the ADC 320 converts the signal level D1 of PD1LG, and then converts the reset level P1. In this way, when the illuminance is high, the levels are read out in the order of P2, D2, D1, and P1 from timing T22 onwards.

[0278] The image sensor 200 can also perform the control of a in Fig. 52 instead of the control of a in Fig. 49. Between timings T20 and T21, it is determined whether the illuminance is higher than the threshold value.

[0279] If the illuminance is determined to be higher than the threshold, the ADC 320 converts the reset level of PD1LG during the period from timing T21 to T22. Then, the ADC 320 converts PD1HG using the CDS method during the period from timing T22 to T23. Then, the ADC 320 converts the signal level of PD1LG during the period from timing T23 to T24. The period from timing T24 to T25 is set as a waiting time. Then, the ADC 320 converts PD2LG using the DDS method during the period from timing T25 to T26.

[0280] On the other hand, if the illuminance is determined to be equal to or lower than the threshold, the period from timing T21 to T22 is set as a waiting time. Then, the ADC 320 converts PD1LG using the CDS method during the period from timing T22 to T23. Then, the ADC 320 converts PD1LG using the DDS method during the period from timing T23 to T25, and converts PD2LG using the DDS method during the period from timing T25 to T26.

[0281] In contrast, as illustrated in b in the same figure, in the comparative example, illuminance is not determined, and the ADC 320 converts the reset level of PD1LG during the period from timing T21 to T22. Then, the ADC 320 converts PD2HG using the CDS method during the period from timing T22 to T23. Then, the ADC 320 converts the signal level of PD1LG during the period from timing T23 to T24. Then, the ADC 320 converts PD1LG using the DDS method during the period from timing T24 to T25, and converts PD2LG using the DDS method during the period from timing T25 to T27.

[0282] As shown in a and b in the figure, even in the control in a, the read time for each row is set to 0.5×T ＡＤ can be shortened by just

[0283] Fig. 53 is a timing chart showing an example of the operation of the image sensor when high illuminance is determined in the control of a in Fig. 52 and readout is performed using the pixel with lower conversion efficiency. During the period from timing T20 to T21, it is determined whether the illuminance is higher than the threshold value.

[0284] If the illuminance is determined to be higher than the threshold, the ADC 320 converts the reset level P0 of PD1LG during the period from timing T21 to T22. Then, the ADC 320 converts the reset level P1 of PD1HG during the period from timing T22 to T23, and then converts the signal level D0. Then, the ADC 320 converts the signal level D1 of PD1LG during the period from timing T23 to T24. The period from timing T24 to T25 is set as a waiting time. Then, the ADC 320 converts the signal level D2 of PD2LG during the period from timing T25 to T26, and then converts the reset level P2.

[0285] Fig. 54 is a timing chart showing an example of the operation of the image sensor when low illuminance is determined in the control of a in Fig. 52 and readout is performed using the pixel with higher conversion efficiency. During the period from timing T20 to T21, it is determined whether the illuminance is higher than the threshold value.

[0286] If the illuminance is determined to be equal to or lower than the threshold, the period from timing T21 to T22 is set as a waiting time. Then, the ADC 320 converts the reset level P0 of PD1LG during the period from timing T22 to T23, and then converts the signal level D0. Then, the ADC 320 converts the signal level D1 of PD1LG during the period from timing T23 to T25, and then converts the reset level P1. Then, the ADC 320 converts the signal level D2 of PD2LG during the period from timing T25 to T26, and then converts the reset level P2.

[0287] In addition, the image sensor 200 may further include a reference signal generating circuit in the column signal processing unit 300 that generates a reference signal for determining brightness, as described in FIG. 2 of Japanese Patent Application Laid-Open No. 2022-025515.

[0288] As described above, according to the second modified example of the third embodiment of the present technology, the characteristic control unit 340 switches the analog gain (such as the attenuation gain) according to the illuminance, and the ADC 320 switches the readout order, thereby increasing the readout speed.

[0289] 4. Fourth Embodiment In the first embodiment described above, the determination unit 330 determines whether or not the illuminance is higher than the threshold value based on the comparison result VCO of the comparator 350. However, this is not limiting. The determination unit 330 in this fourth embodiment differs from the first embodiment in that it determines whether or not the illuminance is higher than the threshold value based on a digital signal Dout indicating the count value of the counter 380.

[0290] 55 is a block diagram showing an example configuration of a column signal processing unit 300 according to the fourth embodiment of the present technology. The determining unit 330 according to the fourth embodiment receives the most significant digits of the digital signal Dout, an enable signal CALEN from the system control unit 212 or the like, and the most significant digits of the threshold value TH.

[0291] For example, the data size of Dout is 14 bits, and Dout[12:13] consisting of the 12th and 13th bits is input to the determination unit 330. Similarly, the threshold is 14 bits, and TH[1:0] consisting of the 12th and 13th bits of the threshold is input to the determination unit 330. Note that the logical values ​​of the 0th to 11th bits of the threshold TH are all "0".

[0292] When enabled by the enable signal CALEN, the determination unit 330 compares Dout[12:13] with TH[1:0] to determine whether the digital signal Dout is higher than the threshold value TH.

[0293] The characteristic control section 340 controls the load MOS current and the tail current based on the determination result of the determination section 330 .

[0294] The fourth embodiment can also be applied to the modified version of the first embodiment. The fourth embodiment can also be applied to both the second embodiment and its first and second modified versions. In this case, the charge-voltage conversion efficiency is controlled based on the determination result of the determination unit 330. The fourth embodiment can also be applied to the third embodiment and its first and second modified versions. In this case, the analog gain is controlled based on the determination result of the determination unit 330.

[0295] 56 is a block diagram showing a configuration example of a data latch 390 according to the fourth embodiment of the present technology. A predetermined number of latch circuits 391 are arranged in the data latch 390. If the data size of the digital signal Dout is 14 bits, 14 latch circuits 391 are arranged.

[0296] The nth bit of the binary code BIN from the preceding binary counter 388 and the nth bit of the drive signal LSEL from the horizontal drive unit 215 are input to the nth bit latch circuit 391. Here, n is an integer from 0 to 13. The latch circuit 391 updates the held value using the binary code in accordance with the drive signal LSEL and latches the output. Each bit of the digital signal Dout from the data latch 390 is output to the image processing unit 216. Of these, the most significant digits Dout

[12] and Dout

[13] are also output to the determination unit 330.

[0297] 57 is a diagram illustrating an example of the operation of the determination unit 330 according to the fourth embodiment of the present technology. For example, when set to enable, the enable signal CALEN is controlled to a high level, and when set to disable, the enable signal CALEN is controlled to a low level.

[0298] As illustrated in a in the same figure, when the enable signal CALEN is at a high level (enabled) and Dout[12:13] is greater than TH[1:0], the judgment unit 330 judges that the illuminance is higher than the threshold and sets flag F to a high level.

[0299] Furthermore, when the enable signal CALEN is at a high level (enabled) and Dout[12:13] is equal to or lower than TH[1:0], the determining unit 330 determines that the illuminance is equal to or lower than the threshold value, and sets the flag F to a low level.

[0300] Furthermore, when the enable signal CALEN is at a low level (disabled), the determination unit 330 latches the flag F regardless of Dout[12:13].

[0301] The determination unit 330 can also determine the illuminance by performing a logical operation on Dout[12:13]. For example, as illustrated in FIG. 1B, the determination unit 330 determines whether Dout

[12] and Dout

[13] are both at a high level when the enable signal LAEN is at a high level (enabled). If Dout

[12] and Dout

[13] are both at a high level, the determination unit 330 sets flag F to a high level; otherwise, the determination unit 330 sets flag F to a low level.

[0302] Furthermore, although the most significant two bits of Dout are input to the determining unit 330, the number of most significant bits input to the determining unit 330 is not limited to two bits.

[0303] 58 is a timing chart showing an example of the operation of the image sensor 200 during determination according to the fourth embodiment of the present technology. For example, a signal level D0 is read out during a readout period from timing T11 to T12. Immediately after timing T12, the horizontal drive unit 215 transmits a pulse of the drive signal LSEL, and the system control unit 212 transmits a pulse of the enable signal LAEN. This control causes the binary code to be captured and latched as Dout in the data latch 390. Furthermore, the flag F is updated and latched in the determination unit 330.

[0304] As described above, according to the fourth embodiment of the present technology, the determining unit 330 determines the illuminance based on the digital signal Dout, so that it is not necessary to input the comparison result VCO to the determining unit 330 .

[0305] 5. Fifth Embodiment In the first embodiment described above, pixel signals are generated by the pixel block 220 illustrated in Fig. 4, but the circuit configuration of the pixel block 220 is not limited to that illustrated in Fig. 4. The image sensor 200 in this fifth embodiment differs from the first embodiment in that the circuit configuration of the pixel block 220 is changed.

[0306] 59 is a circuit diagram showing a configuration example of a pixel block 220 according to a fifth embodiment of the present technology. The pixel block 220 according to the fifth embodiment differs from the pixel block 220 according to the first embodiment in that the FC gain transistor 230 is eliminated. This enables the circuit scale of the pixel block 220 to be reduced.

[0307] As shown in FIG. 60, the FD gain transistor 226 can be omitted.

[0308] 61, a transfer transistor 234 can be added. The transfer transistor 234 transfers charges from the photoelectric conversion element 233 to the charge accumulation section 232 in accordance with a drive signal TGS from the vertical drive section 211.

[0309] Also, as shown in FIG. 62, it is possible to add a transfer transistor 234 and remove the FC gain transistor 230.

[0310] Also, as shown in FIG. 63, it is possible to add a transfer transistor 234 and remove the FD gain transistor 226 .

[0311] Moreover, the pixel blocks 220 in FIGS. 59 to 63 can be applied to the first to fourth embodiments and their respective modifications.

[0312] However, it should be noted that the pixel block 220 in FIGS. 57 and 60, which does not have the FD gain transistor 226, cannot be applied to the second embodiment, which controls the charge-voltage conversion efficiency.

[0313] As described above, according to the fifth embodiment of the present technology, the circuit configuration of the pixel block 220 is changed, and therefore, when the number of transistors is reduced, the circuit scale of the pixel block 220 can be reduced.

[0314] 6. Sixth Embodiment In the second embodiment described above, pixel signals are generated by the pixels 240 illustrated in Fig. 20, but the circuit configuration of the pixels 240 is not limited to that illustrated in Fig. 20. The image sensor 200 in this sixth embodiment differs from the second embodiment in that the circuit configuration of the pixels 240 is changed.

[0315] 64 is a circuit diagram showing a configuration example of a pixel 240 according to a sixth embodiment of the present technology. The pixel 240 according to the sixth embodiment differs from the second embodiment in that an FC gain transistor 250 and a capacitor 251 are added. The FC gain transistor 250 opens and closes a path between a floating diffusion layer 245 and the capacitor 251 in accordance with a drive signal FCG from a vertical drive unit 211. This circuit configuration makes it possible to control the charge-voltage conversion efficiency in three stages.

[0316] As shown in FIG. 65, it is also possible to add only a capacitor 251.

[0317] 66 , it is also possible to add an FC gain transistor 250 and a capacitor 251 and eliminate the FD gain transistor 246. In this case, the characteristics control section 340 controls the charge-voltage conversion efficiency by turning the FC gain transistor 250 on and off.

[0318] 67 , it is also possible to add an FC gain transistor 250, a capacitor 251, and an overflow gate transistor 252. The overflow gate transistor 252 opens and closes a path between the connection node of the FC gain transistor 250 and the capacitor 251 and the photoelectric conversion element 241 in accordance with a drive signal OFG from the vertical drive unit 211.

[0319] Also, as shown in FIG. 68, a capacitor 251 and an overflow gate transistor 252 can be added.

[0320] 69 , it is also possible to add an FC gain transistor 250, a capacitor 251, and an overflow gate transistor 252, and to eliminate the FD gain transistor 246. In this case, the characteristics control unit 340 controls the charge-voltage conversion efficiency by turning the FC gain transistor 250 on and off.

[0321] The pixel 240 shown in FIGS. 64 to 69 can be applied to the first to fourth embodiments and their respective modifications.

[0322] As described above, according to the sixth embodiment of the present technology, the circuit configuration of the pixel 240 is changed, so that when the FC gain transistor 250 is added, the charge-voltage conversion efficiency can be controlled in three stages.

[0323] 7. Application Examples to Mobile Bodies The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0324] FIG. 70 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology of the present disclosure can be applied.

[0325] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 70, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (Interface) 12053.

[0326] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0327] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0328] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0329] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0330] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0331] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, vehicle lane departure warning, etc.

[0332] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0333] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0334] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle of information. In the example of Fig. 70, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0335] FIG. 71 is a diagram showing an example of the installation position of the imaging unit 12031.

[0336] In FIG. 71, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0337] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided on the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0338] 71 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0339] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0340] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the closest three-dimensional object on the path of the vehicle 12100 that is traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation.

[0341] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0342] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0343] An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the imaging unit 12031 of the above-described configuration. Specifically, the imaging device 100 of FIG. 1 can be applied to the imaging unit 12031. By applying the technology according to the present disclosure to the imaging unit 12031, various performance improvements can be achieved, such as increased speed, reduced noise, and reduced power consumption.

[0344] Note that the above-described embodiment shows an example for realizing the present technology, and the matters in the embodiment and the matters specifying the invention in the claims correspond to each other. Similarly, the matters specifying the invention in the claims and the matters in the embodiment of the present technology having the same name correspond to each other. However, the present technology is not limited to the embodiment, and can be realized by applying various modifications to the embodiment within the scope of the gist thereof.

[0345] The effects described in this specification are merely examples and are not limiting, and other effects may also be obtained.

[0346] The present technology may also be configured as follows: (1) An image sensor comprising: a pixel circuit that generates a pixel signal; an analog-to-digital converter that performs analog-to-digital conversion processing on the pixel signal; a determination unit that determines whether illuminance is higher than a predetermined threshold based on an output of the analog-to-digital converter and outputs a determination result; and a characteristic control unit that controls characteristics of the analog-to-digital converter based on the determination result. (2) The image sensor according to (1), wherein the analog-to-digital converter includes a tail current source that supplies a tail current, and the characteristic includes a value of the tail current. (3) The image sensor according to (1) or (2), wherein the analog-to-digital converter includes a load MOS current source connected to a vertical signal line that transmits a pixel signal, and the characteristic includes a value of a load MOS current generated by the load MOS current source. (4) The image sensor according to any one of (1) to (3), wherein the pixel signals include first and second pixel signals, the analog-to-digital converter converts the first pixel signal into a first digital signal with a resolution higher than a predetermined value and converts the second pixel signal into a second digital signal with a resolution not exceeding the predetermined value, and the determination unit determines whether the illuminance is higher than the threshold value based on the output corresponding to the first pixel signal. (5) The image sensor according to any one of (1) to (4), wherein the characteristic control unit further controls the charge-voltage conversion efficiency of the pixel circuit based on the determination result. (6) The image sensor according to (5), wherein the characteristic control unit stops the analog-to-digital converter when the illuminance does not exceed the threshold. (7) The image sensor according to any one of (1) to (6), wherein the characteristic is an analog gain of the analog-to-digital converter. (8) The image sensor described in any one of (1) to (7), wherein the analog-to-digital converter comprises: a comparator that compares the pixel signal with a predetermined reference signal and outputs a comparison result; and a counter that counts a count value over a period until the comparison result is inverted; and the determination unit determines whether the illuminance is higher than the threshold value based on the comparison result.(9) The image sensor according to any one of (1) to (8), wherein the analog-to-digital converter comprises: a comparator that compares the pixel signal with a predetermined reference signal and outputs a comparison result; and a counter that counts a count value over a period until the comparison result is inverted, and the determination unit determines whether the illuminance is higher than the threshold value based on the count value. (10) The image sensor according to any one of (1) to (9), wherein the level of the pixel signal includes first and second reset levels when the pixel circuit is initialized and first and second signal levels according to an amount of exposure. (11) The image sensor according to (10), wherein the analog-to-digital converter converts the first reset level, the first signal level, the second signal level, and the second reset level into a digital signal in this order, and the determination unit determines whether the illuminance is higher than the threshold value based on the output within a readout period of the first signal level. (12) The image sensor according to (10), wherein the analog-to-digital converter converts into digital signals in the order of the first signal level, the first reset level, the second signal level, and the second reset level, and the determination unit determines whether the illuminance is higher than the threshold based on the output within a readout period of the first reset level. (13) The image sensor according to (10), wherein the analog-to-digital converter converts into digital signals in the order of the first reset level, the second reset level, the first signal level, and the second signal level, and the determination unit determines whether the illuminance is higher than the threshold based on the output within a readout period of the second reset level. (14) The image sensor according to any of (1) to (13), wherein the pixel circuit includes: a first photoelectric conversion element; a transfer transistor that transfers charge from the first photoelectric conversion element to a floating diffusion layer; a reset transistor that initializes the floating diffusion layer; and an FD gain transistor that controls charge-to-voltage conversion efficiency. (15) The image sensor according to (14), wherein the pixel circuit further includes a second photoelectric conversion element having a different sensitivity from the first photoelectric conversion element.(16) An image sensor comprising: a pixel circuit that generates a pixel signal; an analog-to-digital converter that performs analog-to-digital conversion processing on the pixel signal in sequence; and a characteristics control unit that controls charge-to-voltage conversion efficiency of the pixel circuit based on an output of the analog-to-digital converter. (17) An imaging device comprising: a pixel circuit that generates a pixel signal; an analog-to-digital converter that performs analog-to-digital conversion processing on the pixel signal; a determination unit that determines whether illuminance is higher than a predetermined threshold based on the output of the analog-to-digital converter and outputs the determination result; a characteristics control unit that controls characteristics of the analog-to-digital converter based on the determination result; and an image processing unit that processes a digital signal from the analog-to-digital converter.

[0347] 100 Imaging device 110 Optical unit 120 DSP circuit 130 Display unit 140 Operation unit 150 Bus 160 Frame memory 170 Storage unit 180 Power supply unit 200 Image sensor 201 Pixel chip 202 Circuit chip 211 Vertical drive unit 212 System control unit 213 DAC 214 Pixel array unit 215 Horizontal drive unit 216 Image processing unit 220 Pixel block 221, 233, 241 Photoelectric conversion element 222, 234, 242 Transfer transistor 223, 243 Reset transistor 224, 231, 244, 251, 266, 322 to 324, 363, 364 Capacitor 225, 227, 245, 247 Floating diffusion layer 226, 246 FD gain transistor 228, 248 Amplifying transistor 229, 249 Selecting transistor 230, 250 FC gain transistor 232 Charge storage unit 240 Pixel 252 Overflow gate transistor 255 Column readout circuit unit 260 Load MOS current source 261 to 265, 365, 366, 371 to 374 nMOS transistor 300 Column signal processing unit 310 Column circuit 320 ADC 321 Selector 325, 326 Auto-zero switch 330 Determination unit 331, 391 Latch circuit 332 OR (logical sum) gate 340 Characteristics control unit 350 Comparator 351 to 362 pMOS transistor 370 Tail current source 376, 377 Amplifier 380 Counter 381 Delay unit 382 Output control unit 383 Gray code latch 384 Binary code conversion unit 385 Adder 386 Metastable mask circuit 387 Multiplexer 388 Binary counter 390 Data latch 400 Gray code generation unit 12031 Imaging unit

Claims

1. An image sensor comprising: a pixel circuit that generates a pixel signal; an analog-to-digital converter that performs analog-to-digital conversion processing on the pixel signal; a determination unit that determines whether or not illuminance is higher than a predetermined threshold based on the output of the analog-to-digital converter and outputs the determination result; and a characteristics control unit that controls the characteristics of the analog-to-digital converter based on the determination result.

2. The image sensor according to claim 1, wherein the analog-to-digital converter includes a tail current source that supplies a tail current, and the characteristic includes a value of the tail current.

3. The image sensor according to claim 1, wherein the analog-to-digital converter includes a load MOS (Metal-Oxide-Semiconductor) current source connected to a vertical signal line that transmits a pixel signal, and the characteristic includes a value of a load MOS current generated by the load MOS current source.

4. The image sensor according to claim 1, wherein the pixel signals include first and second pixel signals, the analog-to-digital converter converts the first pixel signal into a first digital signal with a resolution higher than a predetermined value and converts the second pixel signal into a second digital signal with a resolution not exceeding the predetermined value, and the determination unit determines whether the illuminance is higher than the threshold value based on the output corresponding to the first pixel signal.

5. The image sensor according to claim 1, wherein the characteristic control section further controls the charge-voltage conversion efficiency of the pixel circuit based on the determination result.

6. The image sensor according to claim 5, wherein the characteristic control section stops the analog-to-digital converter when the illuminance does not exceed the threshold value.

7. The image sensor according to claim 1, wherein the characteristic is the analog gain of the analog-to-digital converter.

8. The image sensor according to claim 1, wherein the analog-to-digital converter comprises: a comparator that compares the pixel signal with a predetermined reference signal and outputs a comparison result; and a counter that counts a count value over a period until the comparison result is inverted; and the determination unit determines whether the illuminance is higher than the threshold value based on the comparison result.

9. The image sensor according to claim 1, wherein the analog-to-digital converter comprises: a comparator that compares the pixel signal with a predetermined reference signal and outputs a comparison result; and a counter that counts a count value over a period until the comparison result is inverted; and the determination unit determines whether the illuminance is higher than the threshold value based on the count value.

10. The image sensor according to claim 1, wherein the levels of the pixel signals include first and second reset levels when the pixel circuit is initialized, and first and second signal levels according to the amount of exposure.

11. The image sensor according to claim 10, wherein the analog-to-digital converter converts the first reset level, the first signal level, the second signal level, and the second reset level into a digital signal in that order, and the determination unit determines whether the illuminance is higher than the threshold value based on the output during a readout period of the first signal level.

12. The image sensor according to claim 10, wherein the analog-to-digital converter converts the first signal level, the first reset level, the second signal level, and the second reset level into a digital signal in that order, and the determination unit determines whether the illuminance is higher than the threshold value based on the output during a readout period of the first reset level.

13. The image sensor according to claim 10, wherein the analog-to-digital converter converts the first reset level, the second reset level, the first signal level, and the second signal level into a digital signal in that order, and the determination unit determines whether the illuminance is higher than the threshold value based on the output during a readout period of the second reset level.

14. The image sensor according to claim 1, wherein the pixel circuit comprises: a first photoelectric conversion element; a transfer transistor that transfers charge from the first photoelectric conversion element to a floating diffusion layer; a reset transistor that initializes the floating diffusion layer; and an FD (Floating Diffusion) gain transistor that controls charge-to-voltage conversion efficiency.

15. The image sensor according to claim 14, wherein the pixel circuit further comprises a second photoelectric conversion element having a different sensitivity from that of the first photoelectric conversion element.

16. An image sensor comprising: a pixel circuit that generates a pixel signal; an analog-to-digital converter that sequentially performs analog-to-digital conversion processing on the pixel signal; and a characteristics control unit that controls the charge-to-voltage conversion efficiency of the pixel circuit based on the output of the analog-to-digital converter.

17. An imaging device comprising: a pixel circuit that generates a pixel signal; an analog-to-digital converter that performs analog-to-digital conversion processing on the pixel signal; a determination unit that determines whether or not illuminance is higher than a predetermined threshold based on the output of the analog-to-digital converter and outputs the determination result; a characteristics control unit that controls the characteristics of the analog-to-digital converter based on the determination result; and an image processing unit that processes the digital signal from the analog-to-digital converter.

Images