Capacitor bank, oscillator, and phase synchronization circuit

Abstract

The present invention improves capacitor resolution while suppressing an increase in the number of components of a capacitor bank.　This capacitor bank comprises a plurality of metal oxide metal (MOM) unit capacitors that differ from each other in capacitance value and a switch that selectively connects the MOM unit capacitors in parallel. The plurality of MOM unit capacitors have N capacitance values (where N is an integer of not less than 2) that differ from each other. The ratio of the capacitance values of the MOM unit capacitors may be set to 2M (where M is an integer from 1 to N). The MOM unit capacitors include two MOM unit capacitors that have equal capacitance values. The switch may be provided with a field effect transistor that connects the two MOM unit capacitors in series.

Description

Capacitor banks, oscillators and phase-locked circuits

[0001] The present technology relates to a capacitor bank, an oscillator, and a phase-locked loop circuit. More specifically, the present technology relates to a capacitor bank, an oscillator, and a phase-locked loop circuit provided with a plurality of MOM (Metal Oxide Metal) unit capacitors having different capacitance values.

[0002] In oscillators, a capacitor bank composed of MOM unit capacitors is sometimes used to adjust the oscillation frequency. For example, a technology has been disclosed in which multiple capacitors are connected in parallel and switches are connected in series to each of the capacitors (see, for example, Patent Document 1).

[0003] JP 2011-10368 A

[0004] However, in the above-mentioned conventional technology, a capacitance bank is formed based on a parallel connection of multiple MOM unit capacitors with the same capacitance value. Therefore, in order to improve the capacitance resolution of the capacitance bank, it is necessary to reduce the capacitance values ​​of all MOM unit capacitors in the capacitance bank, which may lead to an increase in the number of components in the capacitance bank.

[0005] This technology was developed in light of these circumstances, and aims to improve capacitance resolution while suppressing an increase in the number of components in a capacitor bank.

[0006] The present technology has been made to solve the above-mentioned problems, and a first aspect thereof is a capacitance bank including a plurality of MOM (Metal Oxide Metal) unit capacitors having different capacitance values ​​and a switch for selectively connecting the MOM unit capacitors in parallel, thereby improving the capacitance resolution of the capacitance bank by reducing the capacitance values ​​of some of the MOM unit capacitors in the capacitance bank.

[0007] In the first aspect, the plurality of MOM unit capacitors have N (N is an integer of 2 or more) capacitance values ​​different from one another, and the ratio of the capacitance values ​​of the MOM unit capacitors is 2 Ｍ (M is an integer between 1 and N). This brings about the effect of equalizing the amount of change in the capacitance value of the MOM capacitor bank.

[0008] In the first aspect, the MOM unit capacitor may include two MOM unit capacitors having the same capacitance value, and the switch may include a field effect transistor that connects the two MOM unit capacitors in series. This provides the effect of ensuring symmetry of the MOM unit capacitors in differential operation while selectively connecting the MOM unit capacitors in parallel.

[0009] In the first aspect, the ratio of the capacitance values ​​of the MOM unit capacitors having different capacitance values ​​may be equal to the ratio of W / L (W is gate width, L is gate length) of the field effect transistors assigned to the MOM unit capacitors having different capacitance values. This allows the ratio of the capacitance values ​​of the MOM unit capacitors, including the parasitic capacitance of the field effect transistor, to be 2. Ｍ This has the effect of setting the

[0010] In the first aspect, a binary control code for selectively connecting the MOM unit capacitors in parallel may be assigned to each of the two MOM unit capacitors and the field effect transistor as a unit, whereby the capacitance value of the MOM capacitor bank is set to 2 or less based on the E (E is an integer of 3 or more) bits of the binary control code. Ｅ This brings about the effect of being changed in stages.

[0011] In the first aspect, the circuit may further include a dummy capacitor that matches the capacitance values ​​of the MOM unit capacitors having different capacitance values, thereby ensuring layout consistency of the MOM unit capacitors having different capacitance values.

[0012] In addition, in the first aspect, a MOS (Metal Oxide Semiconductor) capacitor bank having a finer capacitance resolution than the MOM unit capacitor may be further provided, thereby providing an effect of reducing variations in capacitance value of the MOM unit capacitor and increasing the resolution of the capacitor bank.

[0013] A second aspect of the present invention is an oscillator including an inductor, a MOM capacitor bank capable of selectively connecting multiple MOM unit capacitors having different capacitance values ​​in parallel, and a negative resistance connected to the MOM capacitor bank, thereby improving the accuracy of adjusting the oscillation frequency of the oscillator while suppressing an increase in the number of components in the MOM capacitor bank.

[0014] A third aspect of the present invention is a phase locked loop circuit including an oscillator that generates a clock signal based on an oscillation operation, a phase comparator that compares the phase of the clock signal with the phase of a reference clock, and a loop filter that applies a control signal to the oscillator according to a difference signal output from the phase comparator, the oscillator including a capacitor bank that can selectively connect in parallel a plurality of MOM unit capacitors having different capacitance values. This provides the effect of improving the frequency accuracy of the clock signal generated by the phase locked loop circuit while suppressing an increase in the number of components in the MOM capacitor bank.

[0015] In addition, in the third aspect, the circuit may further include a MOS capacitor bank having a capacitance resolution finer than that of the MOM unit capacitor, and the frequency coverage range of the MOS capacitor bank may cover 1 LSB or more of the frequency adjustable by the MOM capacitor bank. This allows a plurality of MOM unit capacitors having different capacitance values ​​to be selectively connected in parallel, while absorbing variations in the capacitance values ​​of the MOM capacitor bank.

[0016] FIG. 1 is a diagram illustrating a configuration example of an oscillator according to a first embodiment. FIG. 2 is a diagram illustrating a configuration example of an MOM capacitor bank according to the first embodiment. FIG. 3 is a diagram illustrating an example of switching of the MOM capacitor bank according to the first embodiment. FIG. 4 is a diagram illustrating the relationship between the MOM control code, capacitance value, and Q value according to the first embodiment. FIG. 5 is a diagram illustrating the relationship between the MOM control code and capacitance resolution according to the first embodiment. FIG. 6 is a diagram illustrating variations of the MOM capacitor bank according to the second embodiment. FIG. 7 is a diagram illustrating a configuration example of the MOM capacitor bank according to the third embodiment. FIG. 8 is a diagram illustrating a configuration example of an oscillator to which the MOM capacitor bank according to the fourth embodiment is applied. FIG. 9 is a diagram illustrating the relationship between PLL operation and the MOM control code and the MOS control code according to the fourth embodiment. FIG. 10 is a diagram illustrating a configuration example of an oscillator to which the MOM capacitor bank according to the fifth embodiment is applied. FIG. 11 is a block diagram illustrating a schematic configuration example of a vehicle control system. FIG. 12 is an explanatory diagram illustrating an example of the installation position of an imaging unit.

[0017] Hereinafter, modes for implementing the present technology (hereinafter referred to as embodiments) will be described. The description will be made in the following order: 1. First embodiment (an example in which an oscillator is provided with a MOM capacitance bank capable of selectively connecting in parallel a plurality of MOM unit capacitances having different capacitance values) 2. Second embodiment (an example of a variation of a MOM capacitance bank capable of selectively connecting in parallel a plurality of MOM unit capacitances having different capacitance values) 3. Third embodiment (an example in which a MOM capacitance bank capable of selectively connecting in parallel a plurality of MOM unit capacitances having different capacitance values ​​is provided with a dummy capacitance) 4. Fourth embodiment (an example in which an oscillator provided with a MOM capacitance bank capable of selectively connecting in parallel a plurality of MOM unit capacitances having different capacitance values ​​is applied to a PLL (Phase Locked Loop) circuit) 5. Fifth embodiment (an example in which an oscillator provided with a MOM capacitance bank capable of selectively connecting in parallel a plurality of MOM unit capacitances having different capacitance values ​​is applied to an ADPLL (All Digital PLL) circuit) 6. Application example to a mobile body

[0018] 1. First Embodiment FIG. 1 is a diagram showing an example of the configuration of an oscillator according to a first embodiment.

[0019] In the figure, an LC oscillator generates an oscillation signal SO based on the resonance between an inductor L and a metal oxide metal (MOM) capacitor bank BM. The LC oscillator includes an inductor L, a MOM capacitor bank BM, a metal oxide semiconductor (MOS) capacitor bank BS, field effect transistors M11 and M12, and a variable resistor VR. The field effect transistors M11 and M12 are N-channel field effect transistors. The MOM capacitor bank BM can be configured by sandwiching a dielectric between metals. The MOS capacitor bank BS can be configured based on a PN junction formed in a semiconductor.

[0020] The inductor L, the MOM capacitor bank BM, and the MOS capacitor bank BS are connected in parallel. The drains of the field-effect transistors M11 and M12 are connected to both ends of the MOM capacitor bank BM. The drain of the field-effect transistor M11 is connected to the gate of the field-effect transistor M12, and the drain of the field-effect transistor M12 is connected to the gate of the field-effect transistor M11. The sources of the field-effect transistors M11 and M12 are connected to ground potential via a variable resistor VR. The field-effect transistors M11 and M12 can operate as negative resistors. The resistance value of the variable resistor VR is changed based on a current adjustment code IDC. The center tap of the inductor L is connected to the power supply potential VDD.

[0021] The MOM capacitor bank BM switches the capacitance value connected to the LC oscillator based on the MOM binary control code BMC. The MOM capacitor bank BM includes a plurality of switching capacitors S1, S2, ..., each having a different capacitance value of the MOM unit capacitor.

[0022] The switching capacitance S1 includes MOM unit capacitances CA1 and CB1 and a field-effect transistor M1. The MOM unit capacitances CA1 and CB1 can be connected in series to each other via the field-effect transistor M1. When the field-effect transistor M1 is turned on, the series connection of the MOM unit capacitances CA1 and CB1 is selectively connected in parallel to the inductor L. When the field-effect transistor M1 is turned off, the series connection of the MOM unit capacitances CA1 and CB1 is selectively disconnected from the inductor L.

[0023] The switching capacitor S2 includes MOM unit capacitors CA2 and CB2 and a field-effect transistor M2. The MOM unit capacitors CA2 and CB2 can be connected in series to each other via the field-effect transistor M2. When the field-effect transistor M2 is turned on, the series connection of the MOM unit capacitors CA2 and CB2 is selectively connected in parallel to the inductor L. When the field-effect transistor M2 is turned off, the series connection of the MOM unit capacitors CA2 and CB2 is disconnected from the inductor L. At this time, a MOM binary control code BMC is input to the gates of the field-effect transistors M1 and M2 via inverters IV1 and IV2, respectively. The capacitance value of the MOM capacitor bank BM added to the LC oscillator can be discretely changed based on the MOM binary control code BMC.

[0024] The capacitance values ​​of the MOM unit capacitors CA1 and CB1 are set equal to each other. The capacitance values ​​of the MOM unit capacitors CA2 and CB2 are set equal to each other. The capacitance values ​​of the MOM unit capacitors CA1 and CB1 are set different from the capacitance values ​​of the MOM unit capacitors CA2 and CB2. For example, the capacitance values ​​of the MOM unit capacitors CA2 and CB2 can be set to twice the capacitance values ​​of the MOM unit capacitors CA1 and CB1.

[0025] The ratio of W / L (W is the gate width, L is the gate length) of each field effect transistor M1, M2 can be set equal to the ratio of the capacitance value of the MOM unit capacitors CA1, CB1 to the capacitance value of the MOM unit capacitors CA2, CB2. For example, if the capacitance values ​​of the MOM unit capacitors CA2, CB2 are twice the capacitance values ​​of the MOM unit capacitors CA1, CB1, the W / L of the field effect transistor M2 can be set to twice the W / L of the field effect transistor M1.

[0026] The MOS capacitor bank BS switches the capacitance value connected to the LC oscillator based on the MOS binary control code BSC. At this time, the MOS capacitor bank BS can set the capacitance value more precisely than the MOM capacitor bank BM. The MOS capacitor bank BS includes a switching capacitor W1.

[0027] The switching capacitor W1 includes field-effect transistors M3 and M4. The sources and drains of the field-effect transistors M3 and M4 are shorted. At this time, a MOS binary control code BSC is input to the sources and drains of the field-effect transistors M3 and M4. The gate of the field-effect transistor M3 is connected to the drain of the field-effect transistor M11, and the gate of the field-effect transistor M4 is connected to the drain of the field-effect transistor M12.

[0028] Here, the field-effect transistors M1 and M2 are turned on and off based on the MOM binary control code BMC, and the capacitance value of the MOM capacitor bank BM connected in parallel to the LC oscillator is changed, thereby compensating for variations in the oscillation frequency of the oscillation signal SO due to manufacturing, voltage, and temperature variations (PVT) of the LC oscillator.

[0029] 2 is a diagram showing an example of the configuration of a MOM capacitor bank according to the first embodiment. Note that the diagram shows an example in which the capacitance value of the MOM capacitor bank can be switched based on a 5-bit MOM binary control code BMC.

[0030] In the figure, when a 5-bit MOM binary control code BMC is assigned to the MOM capacity bank, the MOM capacity bank can switch its capacity value over 32 levels. In this case, the MOM capacity bank can be divided into five switching units K1 to K5. The switching unit K1 can be assigned a 0.5 unit capacity. The switching unit K2 can be assigned a 1 unit capacity. The switching unit K3 can be assigned a 2 unit capacity. The switching unit K4 can be assigned a 4 unit capacity. The switching unit K5 can be assigned a 8 unit capacity.

[0031] Here, the switching unit K1 can be configured with one switching capacitor S1. The switching unit K2 can be configured with one switching capacitor S2. The switching unit K3 can be configured with two switching capacitors S2 connected in parallel. The switching unit K4 can be configured with four switching capacitors S2 connected in parallel. The switching unit K5 can be configured with eight switching capacitors S2 connected in parallel. In this case, in the switching capacitor S1, for example, the capacitance values ​​of the MOM unit capacitors CA1 and CB1 are set to C ０ and the W / L of the field effect transistor M1 can be set to 1. In the switching capacitor S2, for example, the capacitance values ​​of the MOM unit capacitors CA2 and CB2 can be set to 2C ０ and the W / L of the field effect transistor M2 can be set to 2.

[0032] In each of the switching units K3 to K5, unit capacitors are connected to both sides of the switch, and the switching capacitors S1 and S2, each having a unit capacitor connected in series via the switch, are selectively connected in parallel to the LC oscillator, thereby ensuring symmetry of the MOM unit capacitors in the differential of the LC oscillator.

[0033] 3 is a diagram showing an example of switching of the MOM capacitance bank according to the first embodiment. In the figure, for the capacitance values ​​of each switching unit K1 to K5, the white outline indicates that the capacitance values ​​of the switching units K1 to K5 are disabled, and the gray hatched indicates that the capacitance values ​​of the switching units K1 to K5 are enabled.

[0034] In the figure, a MOM binary control code BMC is assigned corresponding to a MOM control code BOC. Here, switching unit K1 is switched based on the value of bit position 0 of the MOM binary control code BMC. Switching unit K2 is switched based on the value of bit position 1 of the MOM binary control code BMC. Switching unit K3 is switched based on the value of bit position 2 of the MOM binary control code BMC. Switching unit K4 is switched based on the value of bit position 3 of the MOM binary control code BMC. Switching unit K5 is switched based on the value of bit position 4 of the MOM binary control code BMC. Then, by switching the MOM capacitor bank according to the values ​​of the five bit positions of the MOM binary control code BMC, the capacity value of the MOM capacitor bank can be switched over 32 levels.

[0035] 4 is a diagram showing the relationship between the MOM control code, capacitance value, and Q value according to the first embodiment, where a and c in the figure show examples in which the MOM capacitor bank is configured based on the same unit capacitance, and b in the figure shows an example in which the MOM capacitor bank is configured based on two different unit capacitances.

[0036] In FIG. 10A, in the 4-bit configuration, the capacitance value Cap of the MOM capacitor bank can be switched over 16 levels.

[0037] In the figure, in the 4.5-bit configuration, the capacitance value Cap of the MOM capacitor bank is switched over 32 steps. The off-capacitance Coff of the MOM capacitor bank is about 5 fF larger than that of the 4-bit configuration. The Q value is the same as that of the 4-bit configuration.

[0038] In the figure, in the 5-bit configuration, the capacitance value Cap of the MOM capacitor bank is switched over 32 steps. The off-capacitance Coff of the MOM capacitor bank is about 40 fF larger than that of the 4-bit configuration. The Q factor is reduced by up to about 20%.

[0039] FIG. 5 is a diagram showing the relationship between the MOM control code and the capacitance resolution according to the first embodiment.

[0040] In FIG. 10A, in the 4-bit configuration, the amount of change in capacitance ΔC≈16 fF / LSB.

[0041] In the figure, b, in the 4.5-bit configuration, the change in capacitance value ΔC is ≈ 8 fF / LSB, and the capacitance resolution is improved by a factor of 2. However, although a step occurs due to a systematic mismatch between the 1-bit and 0.5-bit cells, this step is small enough to be tolerable and does not pose a practical problem.

[0042] In the diagram, in the case of c, a 5-bit configuration does not produce a step due to systematic mismatch, but there is a trade-off between an increase in parasitic capacitance and a decrease in the Q value.

[0043] As described above, in the first embodiment, an oscillator is provided with a MOM capacitor bank that allows selective parallel connection of MOM unit capacitors CA1, CB1, CA2, and CB2. This allows the capacitance values ​​of some of the MOM unit capacitors CA1 and CB1 in the capacitor bank to be smaller than the capacitance values ​​of the MOM unit capacitors CA2 and CB2, thereby improving the capacitance resolution of the capacitor bank. This reduces wiring congestion, increases in layout area, and increases in switch on-resistance compared to a capacitor bank configured based on parallel connections of multiple MOM unit capacitors with equal capacitance values. As a result, the capacitance resolution of the capacitor bank can be improved while suppressing increases in parasitic capacitance and decreases in the Q factor, thereby improving the phase noise and jitter characteristics of the LC oscillator and increasing the maximum oscillation frequency.

[0044] Furthermore, the ratio of the capacitance values ​​of the MOM unit capacitors CA1, CB1, CA2, and CB2 is made equal to the W / L ratios of the field-effect transistors M1 and M2 assigned to the MOM unit capacitors CA1, CB1, CA2, and CB2, respectively. This makes it possible to set the ratio of the capacitance values ​​of the MOM unit capacitors CA1, CB1, CA2, and CB2, including the parasitic capacitances of the field-effect transistors M1 and M2, and reduces variations in the oscillation frequency of the oscillation signal SO caused by the parasitic capacitances of the field-effect transistors M1 and M2.

[0045] 2. Second Embodiment In the first embodiment described above, an oscillator is provided with a MOM capacitance bank that can selectively connect MOM unit capacitances CA1, CB1, CA2, and CB2 in parallel. In this second embodiment, a variety of MOM capacitance banks are provided that can selectively connect multiple MOM unit capacitances having different capacitance values ​​in parallel.

[0046] 6 is a diagram showing variations of the MOM capacitor bank according to the second embodiment, in which variations of a 5-bit MOM capacitor bank are shown.

[0047] In the figure, an E (E is an integer equal to or greater than 3) binary bit MOM capacitor bank has E-2 variations, for example, a 5-bit MOM capacitor bank has 3 variations.

[0048] In variation 1, two different unit capacitances C １ , C ２ The MOM capacitor bank is configured as follows. ２ = 2C １ It can be said that:

[0049] In variation 2, three different unit capacitances C １ From C ３ The MOM capacitor bank is configured as follows. ３ = 4C １ , C ２ = 2C １ It can be said that:

[0050] In variation 3, four different unit capacitances C １ From C ４ The MOM capacitor bank is configured as follows. ４ = 8C １ , C ３ = 4C １ , C ２ = 2C １ It can be said that:

[0051] In this way, in the second embodiment described above, a variety of MOM capacitor banks are provided that allow a plurality of MOM unit capacitors having different capacitance values ​​to be selectively connected in parallel, thereby improving the resolution of the MOM capacitor bank and increasing the degree of freedom in design.

[0052] Here, in the variation of the MOM capacitor bank, the MOM unit capacitors can have N different capacitance values ​​(N is an integer equal to or greater than 2). In this case, the ratio of the capacitance values ​​of the MOM unit capacitors is 2. Ｍ (M is an integer between 1 and N) This makes it possible to equalize the amount of change in capacitance value of the MOM capacitor bank.

[0053] 3. Third Embodiment In the first embodiment described above, an oscillator is provided with a MOM capacitance bank that can selectively connect MOM unit capacitances CA1, CB1, CA2, and CB2 in parallel. In this third embodiment, a dummy capacitance is provided in a MOM capacitance bank that can selectively connect a plurality of MOM unit capacitances having different capacitance values ​​in parallel.

[0054] FIG. 7 is a diagram illustrating an example of the configuration of a MOM capacitor bank according to the third embodiment.

[0055] In the figure, the switching capacitor S2 is used at bit positions 1 to 4, and the switching capacitor S1 is used at bit position 0. Here, in order to make the capacitance value of the switching capacitor S2 twice the capacitance value of the switching capacitor S1, the capacitance value C ０ The capacitances EA2 and EC2 are connected in parallel to form the MOM unit capacitance CA2, and the capacitance value C ０ The capacitances EB2 and ED2 can be connected in parallel to form the MOM unit capacitance CB2.

[0056] At this time, in the switching capacitor S2, spaces corresponding to the capacitances EB2 and ED2 are added to the switching capacitor S1, causing a layout mismatch between the switching capacitors S1 and S2. For this reason, dummy capacitances DA1 and DA2 corresponding to the spaces of the capacitances EB2 and ED2 of the switching capacitor S2 are added to the switching capacitor S1. The dummy capacitances DA1 and DA2 are electrically disconnected from the MOM capacitor bank and do not contribute to the capacitance value of the MOM capacitor bank. At this time, both terminals of each of the dummy capacitances DA1 and DA2 may be connected to ground potential.

[0057] In this way, in the third embodiment described above, dummy capacitances DA1 and DA2 are provided in the MOM capacitance bank that can selectively connect the MOM unit capacitances CA1, CB1, CA2, and CB2 in parallel, thereby improving the layout consistency of the MOM unit capacitances CA1, CB1, CA2, and CB2 that have different capacitance values.

[0058] 4. Fourth Embodiment In the first embodiment described above, an oscillator is provided with a MOM capacitor bank that can selectively connect MOM unit capacitors CA1, CB1, CA2, and CB2 in parallel. In this fourth embodiment, an oscillator provided with a MOM capacitor bank that can selectively connect MOM unit capacitors CA1, CB1, CA2, and CB2 in parallel is applied to a PLL circuit.

[0059] 8 is a diagram showing an example of the configuration of an oscillator to which a MOM capacitor bank according to the fourth embodiment is applied, in which a PLL (Phase Locked Loop) circuit is taken as an example of a phase locked loop circuit.

[0060] In the figure, a PLL circuit generates a clock signal CLK based on a PLL loop. The phase locked loop circuit includes an oscillator 103, a phase comparator 101, a loop filter 102, and a frequency divider 104. Note that the frequency divider 104 may be omitted.

[0061] The oscillator 103 generates a clock signal CLK based on an oscillation operation. At this time, the clock signal CLK generated by the oscillator 103 is fed back to the phase comparator 101 via the frequency divider 104. The oscillator 103 includes a MOM capacitor bank that can selectively connect multiple MOM unit capacitors having different capacitance values ​​in parallel. The oscillator 103 may be the LC oscillator of the first embodiment described above. The MOM capacitor bank may have any of the configurations of the first to third embodiments described above. Here, the frequency coverage range of the MOS capacitor bank can cover 1 LSB of the frequency adjustable by the MOM capacitor bank.

[0062] The phase comparator 101 compares the phase of the reference clock REF with the phase of the clock signal CLK, and controls the oscillation frequency of the oscillator 103 so that the phase of the reference clock REF matches the phase of the clock signal CLK.

[0063] The loop filter 102 applies a control signal corresponding to the differential signal output from the phase comparator 101 to the oscillator 103 .

[0064] The frequency divider 104 divides the frequency of the clock signal CLK generated by the oscillator 103 and feeds the divided signal back to the phase comparator 101 .

[0065] 9 is a diagram showing the relationship between PLL operation and the MOM control code and MOS control code according to the fourth embodiment. In the diagram, "a" indicates the frequency convergence process of the PLL circuit. In the diagram, "b" indicates the update process of the MOM control code during the frequency convergence process of the PLL circuit. In the diagram, "c" indicates the update process of the MOS control code during the frequency convergence process of the PLL circuit.

[0066] In FIG. 10A, the PLL circuit generates a clock signal CLK based on the PLL loop so as to approach the target frequency TGF.

[0067] When the PLL circuit is started (time t0), the oscillator 103 can be operated based on the adjustment of the capacitance value of the MOM capacitor bank (B1), as shown in b in the figure. At this time, the capacitance value of the MOS capacitor bank is fixed. Adjusting the capacitance value of the MOM capacitor bank generates a frequency error EBF of 1 LSB or less of the MOM capacitor bank. However, even when using a MOM capacitor bank that can selectively connect multiple MOM unit capacitors with different capacitance values ​​in parallel, it is possible to approach the target frequency TGF as long as there is no missing code.

[0068] Next, when the frequency of the PLL circuit reaches a frequency error EBF of the MOM capacitor bank that is less than 1 LSB (time t1), the oscillator 103 can be operated based on the adjustment of the capacitance value of the MOS capacitor bank (B2), as shown at c in the figure. At this time, the capacitance value of the MOM capacitor bank is fixed. Here, if the frequency coverage range of the MOS capacitor bank covers 1 LSB of the MOM capacitor bank, manufacturing variations in the MOM capacitor bank can be absorbed. Note that the MOS capacitor bank may have a frequency coverage range of 1 LSB or more of the MOM capacitance to include a margin for frequency drift after frequency locking.

[0069] In this way, in the fourth embodiment described above, oscillator 103 provided with a MOM capacitor bank that can selectively connect MOM unit capacitors CA1, CB1, CA2, and CB2 in parallel is applied to a PLL circuit, thereby making it possible to improve the frequency accuracy of clock signal CLK generated by the PLL circuit while suppressing an increase in the number of components in the MOM capacitor bank.

[0070] 5. Fifth Embodiment In the above-described fourth embodiment, an oscillator provided with a MOM capacitance bank that can selectively connect MOM unit capacitances CA1, CB1, CA2, and CB2 in parallel is applied to a PLL circuit. In this fifth embodiment, an oscillator provided with a MOM capacitance bank that can selectively connect MOM unit capacitances CA1, CB1, CA2, and CB2 in parallel is applied to an ADPLL circuit.

[0071] 10 is a diagram showing an example of the configuration of an oscillator to which a MOM capacitor bank according to the fifth embodiment is applied, in which an ADPLL (All Digital PLL) circuit is taken as an example of a phase locked loop circuit.

[0072] In the figure, the ADPLL forms a feedback loop based on phase synchronization and outputs a clock signal CLK. The clock signal CLK can be determined based on a reference clock REF and a frequency command word (FCW) parameter. The ADPLL includes an accumulator 211, an adder 212, a loop filter 213, an oscillator 214, a frequency divider 215, a counter 216, and a time-to-digital converter (TDC) 217. The frequency divider 215 is optional.

[0073] The accumulator 211 sets a count-up value for each cycle of the reference clock RCK based on the FCW parameter and outputs the count-up value to the adder 212. The FCW parameter can specify the ratio of the frequency of the clock signal CLK to the frequency of the reference clock REF. The FCW parameter can be provided from outside the ADPLL.

[0074] The adder 212 subtracts the output of the counter 216 and the output of the TDC 217 from the output of the accumulator 211, and outputs the result to the loop filter 213. The output of the adder 212 can indicate the phase error between the reference clock REF and the clock signal CLK.

[0075] The loop filter 213 band-limits the input to the oscillator 214 to reduce the effect of quantization error. The gain of the loop filter 213 can be adjusted based on the calibration of the ADPLL.

[0076] The oscillator 214 generates a clock signal CLK based on an oscillation operation. The oscillator 214 can change its oscillation frequency based on an oscillator tuning word. The oscillator 214 includes a MOM capacitor bank that can selectively connect multiple MOM unit capacitors having different capacitance values ​​in parallel. The oscillator 214 may be the LC oscillator of the first embodiment described above. The MOM capacitor bank may have any of the configurations of the first to third embodiments described above.

[0077] The frequency divider 215 divides the frequency of the clock signal CLK generated by the oscillator 214 and feeds the divided signal back to the counter 216 and the TDC 217 .

[0078] The counter 216 counts up for each clock of the clock signal CLK and outputs the count to the adder 212. At this time, the counter 216 can detect the phase in units of one cycle of the clock signal CLK.

[0079] The TDC 217 detects the time difference between the reference clock RCK and the clock signal CLK, digitizes it, and outputs it to the adder 212. At this time, the ADPLL can operate the phase locked loop so that the phase error approaches 0. The TDC 217 may be a delay line TDC.

[0080] In this way, in the fifth embodiment described above, oscillator 103 provided with a MOM capacitor bank that can selectively connect MOM unit capacitors CA1, CB1, CA2, and CB2 in parallel is applied to an ADPLL circuit, thereby making it possible to improve the frequency accuracy of clock signal CLK generated by the ADPLL circuit while suppressing an increase in the number of components in the MOM capacitor bank.

[0081] 6. Application Examples to Mobile Bodies The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0082] FIG. 11 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0083] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 11, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (interface) 12053.

[0084] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0085] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0086] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0087] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0088] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0089] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, vehicle lane departure warning, etc.

[0090] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0091] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0092] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle of information. In the example of Fig. 11, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0093] FIG. 12 is a diagram showing an example of the installation position of the imaging unit 12031.

[0094] In FIG. 12, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0095] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided on the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0096] 12 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0097] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0098] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which runs autonomously without relying on driver operation.

[0099] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0100] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0101] The above describes an example of a vehicle control system to which the technology according to the present disclosure can be applied. The technology according to the present disclosure can be applied to the drivetrain control unit 12010, the body system control unit 12020, the outside-vehicle information detection unit 12030, the inside-vehicle information detection unit 12040, the integrated control unit 12050, and the image capture unit 12031 among the above-described configurations. Specifically, for example, the oscillator according to the first embodiment described above can be applied to the drivetrain control unit 12010, the body system control unit 12020, the outside-vehicle information detection unit 12030, the inside-vehicle information detection unit 12040, the integrated control unit 12050, and the image capture unit 12031. By applying the technology according to the present disclosure to the vehicle control system 12000, it is possible to improve the accuracy of the oscillation frequency while suppressing an increase in the number of oscillator components.

[0102] Note that the above-described embodiment shows an example for realizing the present technology, and the matters in the embodiment and the matters specifying the invention in the claims correspond to each other. Similarly, the matters specifying the invention in the claims and the matters in the embodiment of the present technology with the same title correspond to each other. However, the present technology is not limited to the embodiment, and can be realized by applying various modifications to the embodiment within the scope of the gist. Furthermore, the effects described in this specification are merely examples and are not limited, and other effects may also be present.

[0103] The present technology can also be configured as follows: (1) A capacitor bank including a plurality of MOM (Metal Oxide Metal) unit capacitors having different capacitance values, and a switch for selectively connecting the MOM unit capacitors in parallel. (2) The plurality of MOM unit capacitors have N (N is an integer of 2 or more) different capacitance values, and the ratio of the capacitance values ​​of the MOM unit capacitors is 2. Ｍ(M is an integer from 1 to N). The capacitance bank according to (1), wherein the MOM unit capacitance includes two MOM unit capacitances having equal capacitance values, and the switch includes a field-effect transistor that connects the two MOM unit capacitances in series. (4) The capacitance bank according to (3), wherein a ratio of the capacitance values ​​of the MOM unit capacitances that are different from each other is equal to a ratio of W / L (W is a gate width, L is a gate length) of the field-effect transistors that are assigned to the MOM unit capacitances that are different from each other. (5) The capacitance bank according to (3) or (4), wherein a binary control code that selectively connects the MOM unit capacitances in parallel is assigned to the two MOM unit capacitances and the field-effect transistor as a unit. (6) The capacitance bank according to any of (1) to (5), further including a dummy capacitance that matches the capacitance values ​​of the MOM unit capacitances that are different from each other. (7) The capacitance bank according to any one of (1) to (6), further comprising a MOS (Metal Oxide Semiconductor) capacitance bank having a capacitance resolution finer than that of the MOM unit capacitance. (8) An oscillator comprising: an inductor; a MOM capacitance bank capable of selectively connecting in parallel a plurality of MOM unit capacitances having different capacitance values; and a negative resistance connected to the MOM capacitance bank. (9) A phase locked loop circuit comprising: an oscillator that generates a clock signal based on an oscillation operation; a phase comparator that compares the phase of the clock signal with the phase of a reference clock; and a loop filter that applies to the oscillator a control signal corresponding to a difference signal output from the phase comparator, wherein the oscillator comprises a capacitance bank that can selectively connect in parallel a plurality of MOM unit capacitances having different capacitance values. (10) The phase locked loop circuit according to (9), further comprising a MOS capacitance bank having a capacitance resolution finer than that of the MOM unit capacitance, wherein the frequency coverage range of the MOS capacitance bank covers 1 LSB or more of the frequencies adjustable by the MOM capacitance bank.

[0104] M1 to M4, M11, M12 Field effect transistors VR Variable resistor L Inductor BM MOM capacitance bank BS MOS capacitance bank S1, S2 Switching capacitance CA1, CB1, CA2, CB2 MOM unit capacitance IV1, IV2 Inverter

Claims

1. A capacitance bank comprising: a plurality of MOM (Metal Oxide Metal) unit capacitors having different capacitance values; and a switch for selectively connecting the MOM unit capacitors in parallel.

2. The plurality of MOM unit capacitors have N (N is an integer of 2 or more) different capacitance values, and the ratio of the capacitance values ​​of the MOM unit capacitors is 2 Ｍ The capacitor bank of claim 1 , wherein M is set to an integer from 1 to N.

3. The capacitance bank according to claim 1, wherein the MOM unit capacitance comprises two MOM unit capacitances having the same capacitance value, and the switch comprises a field effect transistor that connects the two MOM unit capacitances in series.

4. The capacitance bank according to claim 3, wherein the ratio of the capacitance values ​​of the MOM unit capacitors having different capacitance values ​​is equal to the ratio of W / L (W is gate width, L is gate length) of the field effect transistors assigned to the MOM unit capacitors having different capacitance values.

5. The capacitor bank according to claim 3, wherein a binary control code for selectively connecting the MOM unit capacitors in parallel is assigned to each of the two MOM unit capacitors and the field effect transistor.

6. The capacitor bank according to claim 1, further comprising a dummy capacitor for matching the capacitance values ​​of the MOM unit capacitors having different capacitance values.

7. The capacitor bank according to claim 1, further comprising a MOS (Metal Oxide Semiconductor) capacitor bank having a capacitance resolution finer than that of the MOM unit capacitor.

8. An oscillator comprising: an inductor; a MOM capacitance bank capable of selectively connecting in parallel a plurality of MOM unit capacitances having different capacitance values; and a negative resistance connected to the MOM capacitance bank.

9. A phase locked loop circuit comprising: an oscillator that generates a clock signal based on oscillation; a phase comparator that compares the phase of the clock signal with the phase of a reference clock; and a loop filter that applies a control signal to the oscillator according to the difference signal output from the phase comparator, wherein the oscillator comprises a MOM capacitor bank that can selectively connect in parallel a plurality of MOM unit capacitors having different capacitance values.

10. The phase locked loop circuit according to claim 9, further comprising a MOS capacitor bank having a capacitance resolution finer than that of the MOM unit capacitor, wherein the frequency coverage range of the MOS capacitor bank covers 1 LSB or more of the frequency adjustable by the MOM capacitor bank.

Images