Semiconductor device and method for producing semiconductor device

Abstract

The purpose of the present invention is to suppress reduction in flatness of at least one side surface of a semiconductor substrate.　A semiconductor device according to the present disclosure comprises a semiconductor chip including a semiconductor substrate having a plurality of side surfaces, wherein each of the plurality of side surfaces has a plurality of uneven regions, the semiconductor substrate is an off substrate, and at least one side surface of the plurality of side surfaces is a crystal surface of the semiconductor substrate. With the semiconductor device according to the present disclosure, a decrease in flatness of at least one side surface of the semiconductor substrate can be suppressed.

Description

Semiconductor device and manufacturing method thereof

[0001] The technology according to the present disclosure (hereinafter also referred to as "the technology") relates to a semiconductor device and a method for manufacturing the semiconductor device.

[0002] 2. Description of the Related Art Conventionally, semiconductor devices have been known that include a semiconductor chip including a semiconductor substrate having a plurality of side surfaces (see, for example, Patent Documents 1 and 2).

[0003] For example, in the semiconductor device described in Patent Documents 1 and 2, a plurality of semiconductor elements are formed collectively on a semiconductor wafer, and then the semiconductor wafer is divided into a plurality of chip-shaped semiconductor elements (semiconductor chips) by stealth dicing. Each side surface of the semiconductor substrate of the divided semiconductor chip has an uneven region as a modified layer.

[0004] JP 2017-38066 A JP 2004-260083 A

[0005] For example, in the semiconductor devices described in Patent Documents 1 and 2, there is room for improvement in terms of suppressing a decrease in flatness of at least one side surface of the semiconductor substrate.

[0006] Therefore, a main object of the present technology is to suppress a decrease in flatness of at least one side surface of a semiconductor substrate.

[0007] The present technology provides a semiconductor device comprising: a semiconductor chip including a semiconductor substrate having a plurality of side surfaces, each of the plurality of side surfaces having a plurality of uneven regions; the semiconductor substrate being an off-substrate; and at least one of the plurality of side surfaces being a crystal plane of the semiconductor substrate. Each of the plurality of side surfaces may be a crystal plane of the semiconductor substrate. The crystal plane may be a cleavage plane. The off-direction of the semiconductor substrate may be non-perpendicular to the side surface that is the crystal plane. The plurality of side surfaces may include a side surface that is not a crystal plane. The off-angle of the semiconductor substrate may be 0.1° or more and 15° or less. The side surface that is the crystal plane may be inclined with respect to a normal to the semiconductor substrate. The inclination angle of the side surface that is the crystal plane with respect to the normal may be 0.1° or more and 15° or less. The plurality of uneven regions may be two-dimensionally arranged along the side surface that is the crystal plane. The side surface, which is the crystal plane, may have an orthogonal side perpendicular to a normal to the semiconductor substrate and an inclined side inclined with respect to the normal, and a plurality of groups of uneven regions, each group including at least two of the uneven regions aligned in a direction parallel to the inclined side, may be aligned in a direction parallel to the orthogonal side. The shape of the side surface, which is the crystal plane, may be a parallelogram. The shape of the side surface that is not a crystal plane may be a parallelogram. The shape of the main surface of the semiconductor substrate may be a parallelogram. The semiconductor substrate may include a compound semiconductor. The semiconductor substrate may include any of GaAs, Si, Ge, SiC, GaP, and InP. The semiconductor chip may include a light emitting unit and / or a light receiving unit provided on the semiconductor substrate. The semiconductor chip may include the light emitting unit, and the light emitting unit may include a light emitting layer arranged on one surface side of the semiconductor substrate and emit light to the other surface side of the semiconductor substrate. The present technology also provides a method for manufacturing a semiconductor device, including the steps of: forming a plurality of semiconductor elements on a semiconductor wafer having an off-angle; irradiating a laser beam onto regions between the semiconductor elements of the semiconductor wafer to form a plurality of modified layers along a crystal plane of the semiconductor wafer; and singulating the plurality of semiconductor elements.The method for manufacturing a semiconductor device may further include, before the step of forming the plurality of modified layers, forming dicing streets in regions between the semiconductor elements of the semiconductor wafer, and in the step of forming the plurality of modified layers, the laser beam may be scanned along the dicing streets. In the step of forming the dicing streets, the dicing streets may be formed so as to describe a parallelogram in a plan view that surrounds the regions where the semiconductor elements are to be formed.

[0008] 8 is a schematic perspective view of a semiconductor device according to an embodiment of the present technology; FIG. 9 is a schematic plan view of the semiconductor device of FIG. 1; FIG. 3A is a schematic side view (part 1) of the semiconductor device of FIG. 1; FIG. 3B is a schematic side view (part 2) of the semiconductor device of FIG. 1; FIG. 10 is a partial cross-sectional view (part 1) of the semiconductor device of FIG. 1; FIG. 11 is a partial cross-sectional view (part 2) of the semiconductor device of FIG. 1; FIG. 12 is a diagram for explaining cleavage planes, which are side surfaces of a semiconductor substrate of the semiconductor device of FIG. 1; FIG. 13 is a diagram for explaining an off-substrate; FIG. 14 is a schematic cross-sectional view of a state in which the semiconductor device of FIG. 1 is mounted on a mounting substrate; FIG. 15 is a partial enlarged cross-sectional view (part 1) of FIG. 8; FIG. 16 is a partial enlarged cross-sectional view (part 2) of FIG. 8; FIG. 17 is a partial enlarged cross-sectional view (part 3) of FIG. 8; FIG. 18 is a flowchart for explaining an example of a manufacturing method of a semiconductor device according to an embodiment of the present technology; FIG. 19 is a flowchart for explaining a semiconductor element forming process; 28A is a partial enlarged plan view of the semiconductor wafer device during a laser irradiation step. FIG. 28B is a partial enlarged view of FIG. 28A. FIG. 29A is a schematic cross-sectional view (part 1) of the semiconductor wafer device during a laser irradiation step. FIG. 29B is a schematic cross-sectional view (part 1) of the semiconductor wafer device during an expand step. FIG. 30A is a schematic cross-sectional view (part 2) of the semiconductor wafer device during a laser irradiation step. FIG. 30B is a schematic cross-sectional view (part 2) of the semiconductor wafer device during an expand step. FIG. 28B is a schematic cross-sectional view (part 2) of the semiconductor wafer device during an expand step. FIG. 28A is a flowchart for explaining a semiconductor chip mounting process. Schematic cross-sectional views of the semiconductor chip mounting process. Schematic cross-sectional views of the semiconductor chip mounting process. 1A and 1B are schematic cross-sectional views of a semiconductor chip mounting process;47A and 47B are schematic cross-sectional views of a semiconductor chip mounting process; FIG. 47B are schematic cross-sectional views of a semiconductor chip mounting process; FIG. 47C are schematic cross-sectional views of a semiconductor chip mounting process; FIG. 47D is a schematic plan view of a semiconductor device according to Modification 1 of an embodiment of the present technology; FIG. 40A is a schematic side view (part 1) of the semiconductor device of FIG. 39; FIG. 40B is a schematic side view (part 2) of the semiconductor device of FIG. 39; FIG. 47E is a schematic plan view of a semiconductor device according to Modification 2 of an embodiment of the present technology; FIG. 42A is a schematic side view (part 1) of the semiconductor device of FIG. 41; FIG. 42B is a schematic side view (part 2) of the semiconductor device of FIG. 41; FIG. 51B is a partial enlarged plan view of the semiconductor wafer device of the comparative example during a laser irradiation process. FIG. 51A is a partial enlarged view of the semiconductor wafer device of the comparative example during a laser irradiation process. FIG. 51B is a partial enlarged view of FIG. 51A. FIG. 51B is a schematic side view of the semiconductor wafer device of the comparative example during a laser irradiation process. FIG. 51C is a diagram for explaining a defect caused by blade dicing. FIG. 51D is a diagram illustrating an example of an application of a surface-emitting laser device according to a first example of an embodiment of the present technology to a distance measurement device. FIG. 51E is a block diagram illustrating an example of a schematic configuration of a vehicle control system. FIG. 51F is an explanatory diagram illustrating an example of an installation position of a distance measurement device.

[0009] Preferred embodiments of the present technology will be described in detail below with reference to the accompanying drawings. Note that in this specification and the drawings, components having substantially the same functional configurations are denoted by the same reference numerals, and redundant description will be omitted. The embodiments described below are representative embodiments of the present technology, and the scope of the present technology should not be interpreted narrowly. Even when it is described in this specification that the semiconductor device and the semiconductor device manufacturing method according to the present technology each achieve multiple effects, it is sufficient that the semiconductor device and the semiconductor device manufacturing method according to the present technology each achieve at least one effect. The effects described in this specification are merely examples and are not limiting, and other effects may also be achieved.

[0010] The description will be made in the following order: 0. Introduction 1. Semiconductor device according to one embodiment of the present technology 2. Semiconductor device according to modified example 1 of one embodiment of the present technology 3. Semiconductor device according to modified example 2 of one embodiment of the present technology 4. Semiconductor device according to modified example 3 of one embodiment of the present technology 5. Modified example 1 of semiconductor chip of semiconductor device according to one embodiment of the present technology 6. Modified example 2 of semiconductor chip of semiconductor device according to one embodiment of the present technology 7. Modified example 3 of semiconductor chip of semiconductor device according to one embodiment of the present technology 8. Semiconductor device according to modified example 4 of one embodiment of the present technology 9. Semiconductor device according to modified example 5 of one embodiment of the present technology 10. Other modified examples of the present technology 11. Application example to electronic device 12. Example of application of surface-emitting laser to distance measurement device 13. Example of mounting distance measurement device on a moving body

[0011] <0. Introduction>

[0012] In recent years, stealth dicing (SD) has been attracting attention as a dicing method that is less susceptible to chipping and cracking.

[0013] In conventional stealth dicing, multiple modified layers (concave and recessed regions) were formed in a direction perpendicular to the front and back surfaces of the wafer to separate multiple elements (e.g., semiconductor elements) formed collectively on the wafer into chips so that the substrate (e.g., semiconductor substrate) of each chip (e.g., semiconductor chip) would be a rectangular parallelepiped.

[0014] However, even when a wafer has an off-angle where the crystal plane is tilted, if multiple modified layers are formed in a direction perpendicular to the front and back surfaces of the wafer, the alignment direction of the modified layers will be misaligned with the extension direction of cracks originating from the modified layers, resulting in the formation of irregularities other than the modified layers on the side surface of the chip substrate, or the meandering cut line, resulting in a decrease in flatness of the side surface of the substrate. This decrease in flatness leads to the generation of dust and chip cracks or chipping during element separation.

[0015] To address this problem, patent documents 1 and 2 have been proposed.

[0016] In Patent Document 1 (JP 2017-38066 A), multiple SD modified layers (uneven regions) are formed on the cleanly cleavable surface (slope) of a hexagonal substrate. However, in reality, even on the cleanly cleavable surface, unevenness other than the modified layers is formed, and the cut line is meandering. In other words, Patent Document 1 leaves room for improvement in terms of suppressing a decrease in flatness on at least one side of the substrate.

[0017] In Patent Document 2 (JP 2004-260083 A), the substrate side surface (SD cut surface) is inclined by utilizing the substrate's off-angle. However, because only one modified layer (uneven region) is formed in the thickness direction of the substrate, element division is difficult, and unevenness other than the modified layer is formed, or the cut line is meandering. In other words, Patent Document 2 leaves room for improvement in terms of suppressing a decrease in flatness of at least one side surface of the substrate.

[0018] Therefore, after extensive research, the inventors have succeeded in suppressing the decrease in flatness of at least one side surface of a semiconductor substrate by forming a plurality of uneven regions (modified layers) on the crystal surface of the semiconductor substrate, which is a novel finding of the inventors.

[0019] The inventors have developed a semiconductor device according to the present technology as a semiconductor device that embodies this new finding. The semiconductor device according to the present technology can suppress a decrease in flatness of at least one side surface of a semiconductor substrate. This makes it possible to suppress the generation of dust and chip cracks and chipping during element separation.

[0020] Hereinafter, an embodiment of a semiconductor device according to the present technology will be described in detail with reference to the drawings. In the following, in Figures 3A and 3B etc., the upper side will be referred to as "upper" and the lower side will be referred to as "lower" as appropriate.

[0021] 1. Semiconductor device according to an embodiment of the present technology Fig. 1 is a schematic perspective view of a semiconductor device 10 according to an embodiment of the present technology. Fig. 2 is a schematic plan view of the semiconductor device of Fig. 1. Fig. 3A is a schematic side view (part 1) of the semiconductor device 10 of Fig. 1. Fig. 3B is a schematic side view (part 2) of the semiconductor device 10 of Fig. 1. Fig. 4 is a partial cross-sectional view (part 1) of the semiconductor device 10 of Fig. 1. Fig. 5 is a partial cross-sectional view (part 2) of the semiconductor device 10 of Fig. 1.

[0022] <Configuration of Semiconductor Device> (Overall Configuration of Semiconductor Device)

[0023] As shown in FIG. 1 , a semiconductor device 10 according to an embodiment of the present technology includes a semiconductor chip SC. Here, a "semiconductor chip" refers to a chip-shaped semiconductor element. A "semiconductor element" refers to an element that is mainly composed of semiconductors and may also include conductors and insulators. Hereinafter, the "semiconductor chip SC" may also be simply referred to as a "chip," and the "semiconductor element" may also be simply referred to as an "element."

[0024] The semiconductor chip SC is a surface-emitting laser array chip as an example of a chip-shaped semiconductor element, and includes a plurality of (e.g., 63) vertical cavity surface-emitting lasers (VCSELs) arranged two-dimensionally (e.g., in a matrix arrangement, a staggered arrangement, or the like).

[0025] The semiconductor chip SC includes a semiconductor substrate 15, a plurality of surface-emitting laser resonators 100 (light-emitting units) arranged two-dimensionally (e.g., in a matrix or staggered pattern) on the semiconductor substrate 15, and pedestals 120A, 120B arranged on one side and the other side of a resonator arrangement region RPA in which the plurality of resonators 100 are arranged. The plurality of surface-emitting lasers share the semiconductor substrate 15. As an example, each surface-emitting laser is a back-emitting surface-emitting laser. That is, each surface-emitting laser emits laser light toward the back side of the semiconductor substrate 15 (the side opposite the resonator 100). Hereinafter, two pedestals facing each other are provided, but at least one pedestal surrounding the resonator arrangement region RPA may also be provided. Hereinafter, when there is no need to distinguish between the pedestals 120A, 120B, they will be collectively referred to as the "pedestal 120."

[0026] As an example, a semiconductor device 10 including a semiconductor chip SC is flip-chip mounted on a mounting substrate 20 (see FIG. 8 ). Flip-chip mounting is also called "junction-down mounting" or "face-down mounting." As an example, each surface-emitting laser of the semiconductor chip SC is driven by a driver (drive circuit). In FIG. 8 , the mounting substrate 20 is a drive substrate having a driver (drive circuit), but it may also be a wiring substrate connected to the driver (drive circuit). The semiconductor device 10 may include the mounting substrate 20 as a component in addition to the semiconductor chip SC.

[0027] Fig. 4 is a cross-sectional view of a portion of the semiconductor device 10 including two adjacent resonators 100. Fig. 5 is a cross-sectional view of a portion of the semiconductor device 10 including adjacent resonators 100 and a pedestal 120. The resonators 100 and the pedestal 120 have substantially the same layered structure.

[0028] 4 and 5 , the resonator 100 and the pedestal 120 have, for example, a layered structure disposed on a semiconductor substrate 15. In this layered structure, a first contact layer 101, a first semiconductor multilayer reflector 102, a first cladding layer 104, a light-emitting layer 105, a second cladding layer 106, a second semiconductor multilayer reflector 107, and a second contact layer 108 are layered in this order. An oxide constriction layer 103 is disposed within the first semiconductor multilayer reflector 102 of the resonator 100. The peripheral portion of the layer of the first semiconductor multilayer reflector 102 of the pedestal 120 corresponding to the oxide constriction layer 103 is an oxidized region 103′. Here, each resonator 100 and each pedestal 120 shares the first contact layer 101.

[0029] The first and second cladding layers 104 and 106 have different conductivity types. The resonator 100 has a double heterostructure in which the light-emitting layer 105 is sandwiched in the stacking direction (vertical direction, perpendicular to the surface) between the first and second cladding layers 104 and 106 of different conductivity types, and holes and electrons can undergo radiative recombination (radiative recombination) in the light-emitting layer 105.

[0030] The length of the resonator 100 is, for example, an integer multiple of half the wavelength (λ / 2) of the standing wave generated within the resonator 100, where λ is the emission wavelength of the surface-emitting laser.

[0031] Both the resonator 100 and the pedestal 120 have a mesa. Hereinafter, the mesa of the resonator 100 will also be referred to as the "light-emitting mesa LM." The mesa of the pedestal 120 will also be referred to as the "dummy mesa DM." Here, the light-emitting mesa LM and the dummy mesa DM are both configured as at least a part of the above-mentioned laminated structure (here, the part of the above-mentioned laminated structure excluding the part below the first contact layer 101).

[0032] As an example, the light emitting mesa LM and the dummy mesa DM each have a height of several μm to several tens of μm (for example, about 3 to 10 μm). It is preferable that the difference in height between the light emitting mesa LM and the dummy mesa DM is as small as possible. The shape of the light emitting mesa LM in a planar view is circular here (see FIG. 2), but it may also be elliptical or a polygonal shape such as a square, rectangle, hexagon, or octagon.

[0033] The light emitting mesa LM and the dummy mesa DM are covered with an insulating film 109. The insulating film 109 is made of a dielectric material such as SiO, SiN, or SiON. The insulating film 109 is provided with a first contact hole CH1 that exposes the top of the light emitting mesa LM (more specifically, the second contact layer 108 of the light emitting mesa LM), a second contact hole CH2 that exposes the top of the dummy mesa DM (more specifically, the second contact layer 108 of the dummy mesa DM), and a third contact hole CH3 that exposes a portion of the first contact layer 101 between the light emitting mesa LM and the dummy mesa DM.

[0034] A cathode electrode 110 is provided in the first contact hole CH1 so as to be in contact with the top of the light emitting mesa LM (more specifically, the second contact layer 108 of the light emitting mesa LM). The cathode electrode 110 is made of, for example, Au / Ni / AuGe.

[0035] As shown in FIG. 5, the anode electrode 111 is provided in the second contact hole CH2 so as to be in contact with the top of the dummy mesa DM (more specifically, the top of the second contact layer 108 of the dummy mesa DM).

[0036] An intermediate electrode 112 is provided in the third contact hole CH3 so as to be in contact with the first contact layer 101. The intermediate electrode 112 is a common electrode provided in common to the plurality of resonators 100. The intermediate electrode 112 is made of, for example, Au / Pt / Ti.

[0037] The anode electrode 111 and the intermediate electrode 112 are connected via an anode wiring 113 (connecting layer). The anode wiring 113 is made of, for example, conductive plating. The conductive plating is made of, for example, Au, Ag, Cu, or the like.

[0038] As is clear from the above description, the semiconductor device 10 has an electrode layout in which the anode is common to the plurality of resonators 100 and the cathodes are independent, and each resonator 100 can be driven independently by a driver.

[0039] (Semiconductor Substrate) The semiconductor substrate 15 is made of, for example, a compound semiconductor, such as a semi-insulating (SI) GaAs substrate (SI-GaAs substrate). The semi-insulating semiconductor substrate 15 has little light absorption and is suitable for a back-emitting VCSEL.

[0040] (First Contact Layer) The first contact layer 101 is a semiconductor layer with high carrier conductivity and low resistance. For example, it is made of a p-GaAs layer doped with a high concentration of p-type impurities. Examples of the p-type impurities (dopants) include Zn, Mg, Be, and C. The contact layer is also called a "current injection layer." A lateral current path is formed within the first contact layer 101 of the resonator 100. (First Semiconductor Multilayer Reflector) The first semiconductor multilayer reflector 102 is, for example, a semiconductor multilayer reflector doped with p-type impurities, and has low light absorption, high reflectivity, and electrical conductivity. The semiconductor multilayer reflector has a structure in which multiple types (for example, two types) of semiconductor layers (e.g., p-AlGaAs layers) with different refractive indices are alternately stacked with an optical thickness equal to one-quarter of the emission wavelength λ. Examples of the p-type impurities (dopants) include Zn, Mg, Be, and C.

[0041] (Oxidized Narrowing Layer) The oxidized narrowing layer 103 has a non-oxidized region 103a and an oxidized region 103b surrounding the non-oxidized region 103a. The non-oxidized region 103a is made of a compound semiconductor (e.g., AlGaAs, AlAs, etc.). The oxidized region 103b is made of an insulator (e.g., Al x O y The oxidized region 103b has a higher resistance and a lower refractive index than the non-oxidized region 103a, so that the non-oxidized region 103a functions as a current / light passing region, and the oxidized region 103b functions as a current / light confinement region. The oxidized confinement layer 103 is preferably disposed at or near a node of a standing wave generated within the resonator 100.

[0042] (First Cladding Layer) The first cladding layer 104 is made of, for example, p-AlGaAs. The cladding layer is also called a "spacer layer." (Light-Emitting Layer) The light-emitting layer 105 is made of, for example, a compound semiconductor having a band gap energy smaller than those of the first and second cladding layers 104 and 106. The light-emitting layer 105 is made of, for example, a GaAs-based compound semiconductor (e.g., GaAs, AlGaAs, GaInAs, GaInAsN, etc.). The light-emitting layer 105 may have any of a quantum well structure, a strained quantum well structure, a multiple quantum well structure, a quantum wire structure, and a quantum dot structure. The light-emitting layer 105 is also called an "active layer." The light-emitting layer 105 has a light-emitting region, which is a region into which current is injected (current injection region) and which emits light. The light-emitting region is a region defined by the oxidized region 103b of the oxidized constriction layer 103 and corresponds to the non-oxidized region 103a. The light-emitting layer 105 is preferably disposed at or near the antinode of a standing wave generated within the resonator 100. (Second Cladding Layer) The second cladding layer 106 is made of n-AlGaAs, for example. The cladding layer is also called a "spacer layer."

[0043] (Second Semiconductor Multilayer Reflector) The second semiconductor multilayer reflector 107 is, for example, a semiconductor multilayer reflector doped with n-type impurities, and has low light absorption, high reflectivity, and electrical conductivity. The semiconductor multilayer reflector has a structure in which multiple types (for example, two types) of semiconductor layers (for example, n-AlGaAs layers) with different refractive indices are alternately stacked with an optical thickness of ¼ the emission wavelength λ. Examples of the n-type impurity (dopant) include Si, Se, and Ge. The second semiconductor multilayer reflector 107 is set to have a slightly higher reflectivity than the first semiconductor multilayer reflector 102.

[0044] (Second Contact Layer) The second contact layer 108 is a semiconductor layer with high carrier conductivity and low resistance, and is made of, for example, an n-GaAs layer doped with a high concentration of n-type impurities. Examples of the n-type impurities (dopants) include Si, Se, and Ge. The contact layer is also called a "current injection layer."

[0045] (Details of semiconductor substrate)

[0046] The semiconductor substrate 15 is an SI-GaAs substrate as described above, and is an off-substrate (tilted substrate).

[0047] As an example, the semiconductor substrate 15 is an off-substrate whose main surfaces (front and back surfaces) are tilted (off-angled) from the (100) plane by an off-angle θ in the

[110] direction (see FIG. 7 ). The off-angle θ is preferably, for example, 0.1° or more and 15° or less. Here, the off-angle θ is set to 2°. The thickness of the semiconductor substrate 15 is, for example, 100 μm.

[0048] 1 to 3B, the semiconductor substrate 15 is, for example, a semiconductor substrate having an outer shape like a shear-deformed rectangular parallelepiped, and has a plurality of (for example, four) side surfaces (for example, two side surfaces 15a, 15a facing each other, and two side surfaces 15b, 15b facing each other), a first main surface 15c (front surface) on which the resonator 100 and the pedestal 120 are provided, and a second main surface 15d (rear surface) facing the first main surface 15c. In this specification, the first main surface 15c and the second main surface 15d facing each other will be collectively referred to as the "main surfaces" as appropriate.

[0049] The first main surface 15c and the second main surface 15d are, for example, flat surfaces parallel to each other. At least one side surface (here, all side surfaces) of the multiple (for example, four) side surfaces 15a, 15a, 15b, 15b is a crystal plane of the semiconductor substrate 15. For example, each of the two side surfaces 15a, 15a is a crystal plane parallel to the (011) plane. For example, each of the two side surfaces 15b, 15b is a crystal plane parallel to the (01-1) plane.

[0050] Each side surface that is a crystal plane is preferably a cleavage plane. The shape of each side surface that is a crystal plane is, for example, a parallelogram. More specifically, the shape of each side surface that is a crystal plane is, for example, a parallelogram whose interior angles are not right angles.

[0051] The off-direction of the semiconductor substrate 15 and each side surface, which is a crystal plane, are non-perpendicular (see FIG. 6 ). Here, the angle formed between the off-direction of the semiconductor substrate 15 and each side surface, which is a crystal plane, is 45° or 135°, but is not limited thereto. The angle may be 0° or greater but less than 90°, or greater than 90° but less than 180°. The angle formed between the off-direction of the semiconductor substrate 15 and each side surface, which is a crystal plane, may be, for example, 5° or 95°, 10° or 100°, 15° or 105°, 20° or 110°, 25° or 115°, 30° or 120°, 35° or 125°, 40° or 130°, 50° or 140°, 55° or 145°, 60° or 150°, 75° or 165°, 80° or 170°, or 85° or 175°.

[0052] 3A and 3B , each side surface, which is a crystal plane, is inclined at an inclination angle φ (<90°) with respect to the normal NL of the semiconductor substrate 15. The inclination angle φ is preferably, for example, not less than 0.1° and not more than 15°. Here, the inclination angle φ is set to 1.4°.

[0053] The shape of each of the front and back surfaces (first main surface 15c and second main surface 15d) of the semiconductor substrate 15 is a parallelogram. More specifically, the shape of each of the front and back surfaces (first main surface 15c and second main surface 15d) of the semiconductor substrate 15 is a parallelogram whose interior angles are not right angles.

[0054] Each of the side surfaces 15 a, 15 b has a plurality of uneven areas UEA (Uneven Areas). Each uneven area UEA is an area where unevenness is continuous. As an example, each uneven area UEA is a modified layer SDL formed by stealth dicing.

[0055] A plurality of uneven regions UEA are arranged (more specifically, arranged two-dimensionally) along each side surface, which is a crystal plane. Each side surface, which is a crystal plane, has an orthogonal side OS that is perpendicular to the normal line NL of the semiconductor substrate 15 and an inclined side SS that is inclined with respect to the normal line NL. A plurality of (e.g., two) uneven region groups, each including at least two (e.g., two) uneven regions UEA aligned in a direction parallel to the inclined side SS, are aligned in a direction parallel to the orthogonal side OS.

[0056] Here, two uneven regions UEA are formed side by side in a direction parallel to the inclined side SS, but this is not limited to this, and three or more uneven regions UEA may be formed side by side in a direction parallel to the inclined side SS.

[0057] 8 is a cross-sectional view of the semiconductor device 10 of FIG. 1 mounted on a mounting substrate 20. As shown in FIG. 8 as an example, the mounting substrate 20 includes a semiconductor substrate 21 (e.g., a Si substrate, a Ge substrate, or the like) on which a driver is provided, and a wiring layer 22 stacked on the semiconductor substrate 21 and bonded to the semiconductor device 10.

[0058] As an example, the driver has an NMOS transistor that turns on and off the power supply to each surface-emitting laser of the semiconductor device 10. The NMOS transistor is electrically connected to the semiconductor device 10 via the wiring layer 22 and the bump. Note that the driver may have a PMOS transistor instead of the NMOS transistor.

[0059] The wiring layer 22 is bonded to each resonator 100 via first bumps BP1, and is also bonded to the pedestal 120 via a plurality of second bumps BP2.

[0060] As an example, the wiring layer 22 includes an insulating layer 22b, a plurality of metal layers 22a provided in the insulating layer 22b, a plurality of connection pads 22c, and a plurality of connection pads 22d. The plurality of metal layers 22a electrically connect the NMOS driver in the semiconductor substrate 21 to the plurality of connection pads 22d. The plurality of connection pads 22d are provided exposed on the surface (upper layer) of the insulating layer 22b at positions facing the semiconductor device 10. The plurality of connection pads 22d include a connection pad 22d (cathode terminal) connected to the resonator 100 (specifically, the cathode electrode 110) via a first bump BP1 and a connection pad 22d (anode terminal) connected to the pedestal portion 120 (specifically, the anode electrode 111) via a second bump BP2. The plurality of connection pads 22c are provided on the surface (upper layer) of the insulating layer 22b, exposed at positions not facing the semiconductor device 10, and are electrically connected to a controller (control device) via bonding wires, for example. Note that the electrical connection between the semiconductor device 10 and the mounting substrate 20 is not limited to that shown in FIG.

[0061] Fig. 9 is a partially enlarged cross-sectional view (part 1) of Fig. 8, which is an enlarged cross-sectional view showing the part surrounded by the dashed line in Fig. 8. Fig. 10 is a partially enlarged cross-sectional view (part 2) of Fig. 8, which is an enlarged cross-sectional view showing the part surrounded by the two-dot chain line in Fig. 8. Fig. 11 is a partially enlarged cross-sectional view (part 3) of Fig. 8, which is an enlarged cross-sectional view showing the part surrounded by the dashed line in Fig. 8.

[0062] As shown in FIGS. 9 and 11, in the semiconductor device 10, the cathode electrode 110 provided on the top of the light emitting mesa LM is joined to the mounting substrate 20 via a first bump BP1.

[0063] As shown in FIGS. 10 and 11, in the semiconductor device 10, the anode electrode 111 provided on the top of the dummy mesa DM is joined to the mounting substrate 20 via a plurality of second bumps BP2.

[0064] (bump)

[0065] As an example, each of the first bump BP1 and the second bump BP2 includes a material that is resistant to being crushed by pressure.Furthermore, as an example, the first bump BP1 and the second bump BP2 are made of the same conductive material.

[0066] The conductive material constituting the first bump BP1 and the second bump BP2 is preferably a conductive material that can be transitioned from a softened state (relatively soft state) to a hardened state (relatively hard state) during bump bonding. Specifically, the conductive material includes a material that is resistant to being crushed by pressure.

[0067] More specifically, the conductive material may be, for example, a metal particle paste. The metal particle paste can be gradually transformed from a softened state to a hardened state by applying pressure. Furthermore, the metal paste can be solidified by sintering. Examples of the metal particle paste include Au particle paste, Ag particle paste, and Cu particle paste.

[0068] The metal particle paste is preferably a metal nanopaste containing metal nanoparticles, in which metal particles containing metal nanoparticles with a particle size of less than 1 μm are dispersed in a resin binder. Examples of such metal nanopastes include Au nanopaste, Ag nanopaste, and Cu nanopaste.

[0069] The conductive material may be, for example, an alloy paste. The alloy paste may be, for example, a solder paste (cream solder). Solder paste has a property (thixotropy) in which the viscosity decreases (becomes softened) when stirred and returns to its original state (hardened) when left standing. Specific examples of solder paste include Sn—Ag-based, Sn—Au-based, and Sn—Cu-based pastes.

[0070] As an example, it is preferable that the difference in the arrangement density (area density) of the first bumps BP1 and the second bumps BP2 within the surface be as small as possible (ideally 0). This makes it possible to make the load applied to the semiconductor device 10 uniform within the surface when the semiconductor device 10 is mounted on the mounting substrate 20 (when the bumps are bonded), and ultimately makes it possible to suppress deformation of the semiconductor device 10.

[0071] <Operation of Surface Light-Emitting Device> The operation of the semiconductor device 10 will now be described. When the driver's NMOS transistor is turned ON, current from the anode side of the driver flows into the first contact layer 101 of each resonator 100 via the second bump BP2, the anode electrode 111, the anode wiring 113, and the intermediate electrode 112. The current passing through the first contact layer 101 passes through the first semiconductor multilayer film reflector 102, is constricted by the oxide constriction layer 103, and is injected into the light-emitting layer 105 via the first cladding layer 104. At this time, the light-emitting layer 105 emits light, and the light travels back and forth between the first and second semiconductor multilayer film reflectors 102 and 107 while being constricted by the oxide constriction layer 103 and amplified by the light-emitting layer 105. When oscillation conditions are satisfied, the light is emitted as laser light to the back side (second main surface) of the semiconductor substrate 15. The current injected into the light-emitting layer 105 flows out to the cathode side of the driver via the second cladding layer 106, the second semiconductor multilayer reflector 107, the second contact layer 108, the cathode electrode 110, and the first bump BP1 in this order.

[0072] <Method for Manufacturing Semiconductor Device> Hereinafter, the overall flow of an example of a method for manufacturing the semiconductor device 10 will be described with reference to the flowchart of FIG.

[0073] In step S1, a semiconductor element formation process is carried out. In the semiconductor formation process, a semiconductor manufacturing method using semiconductor manufacturing equipment is used to simultaneously form a plurality of surface-emitting laser arrays (semiconductor elements) on a single semiconductor wafer (e.g., an SI-GaAs off-substrate having a diameter of 6 inches and a thickness of 675 μm; hereinafter, for convenience, referred to as the "semiconductor substrate 15," "wafer," or "substrate"), which is the base material of the semiconductor substrate 15. Details of the semiconductor element formation process will be described later.

[0074] In step S2, a dicing process is performed. In the dicing process, a series of multiple surface-emitting laser arrays are separated from each other by stealth dicing to obtain chip-shaped surface-emitting laser arrays (surface-emitting laser array chips). The dicing process will be described in detail later.

[0075] In step S3, a semiconductor chip mounting process is performed, in which the surface-emitting laser array chip is mounted on the mounting substrate 20. The details of the semiconductor chip mounting process will be described later.

[0076] (Step S1: Semiconductor Element Formation Processing) Hereinafter, the semiconductor element formation processing will be described in detail with reference to the flowchart of FIG.

[0077] In the first step S1-1, a stacked body L is produced (see FIG. 14 ). Specifically, the stacked body L is produced by stacking, in this order, a first contact layer 101, a first semiconductor multilayer reflector 102 having an oxidized layer 103S (e.g., an AlGaAs layer, an AlAs layer, or the like) serving as a material for the oxide constriction layer 103 disposed therein, a first cladding layer 104, a light-emitting layer 105, a second cladding layer 106, a second semiconductor multilayer reflector 107, and a second contact layer 108 on a semiconductor substrate 15 serving as a growth substrate by an epitaxial crystal growth method such as MOCVD (Metal Organic Chemical Vapor Deposition). In this case, as raw materials for the compound semiconductor, for example, methyl-based organometallic gases such as trimethylaluminum (TMAl), trimethylgallium (TMGa), and trimethylindium (TMIn), and arsine (AsH) gas are used, as raw materials for the donor impurities, for example, disilane (SiH), and as raw materials for the acceptor impurities, for example, carbon tetrabromide (CBr).

[0078] In the next step S1-2, a first mesa M1 that will become the light-emitting mesa LM and a second mesa M2 that will become the dummy mesa DM are formed (see FIGS. 15 and 16 ). Specifically, a resist pattern that covers the areas on the stack where the first and second mesas M1 and M2 will be formed is formed by photolithography, and the stack is then etched by dry etching or wet etching using the resist pattern as a mask. The etching is performed, for example, until the bottom of the etching reaches the inside of the first contact layer 101. As a result, the first and second mesas M1 and M2 are formed. The resist pattern is then removed. An etching stop layer (e.g., an InGaP layer) may be disposed between the first contact layer 101 and the first semiconductor multilayer film reflector 102.

[0079] In the next step S1-3, an oxidized constriction layer 103 is formed (see FIGS. 17 and 18). Specifically, the first mesa M1 (see FIG. 15) is exposed to a high-temperature water vapor atmosphere, and the oxidized layer 103S is selectively oxidized for a predetermined distance from the side. As a result, an oxidized constriction layer 103 is formed in the first mesa M1, with a non-oxidized region 103a surrounded by an oxidized region 103b, thereby generating a light-emitting mesa LM (see FIG. 17). A layer in which a non-oxidized region is surrounded by an oxidized region 103' is also formed in the second mesa M2, thereby generating a dummy mesa DM (see FIG. 18).

[0080] In the next step S1-4, the insulating film 109 is formed (see FIGS. 19 and 20). Specifically, the insulating film 109 is formed on the entire surface by, for example, sputtering or vacuum deposition.

[0081] In the next step S1-5, first to third contact holes CH1, CH2, and CH3 are formed (see FIGS. 21 and 22). Specifically, for example, by photolithography and etching, the insulating film 109 on the top of the light emitting mesa LM, the insulating film 109 on the top of the dummy mesa DM, and the insulating film 109 on the first contact layer 101 between the light emitting mesa LM and the dummy mesa DM are removed to form the first to third contact holes CH1, CH2, and CH3.

[0082] In the next step S1-6, the cathode electrode 110, the anode electrode 111, and the intermediate electrode 112 are formed (see FIGS. 23 and 24). Specifically, for example, by lift-off, the cathode electrode 110 is formed in the first contact hole CH1, the anode electrode 111 is formed in the second contact hole CH2, and the intermediate electrode 112 is formed in the third contact hole CH3. At this time, for example, sputtering, vacuum deposition, or the like is used to form the electrode material films.

[0083] In the final step S1-7, the anode wiring 113 is formed (see FIG. 25). Specifically, the anode wiring 113 is formed, for example, by plating, so that one end contacts the intermediate electrode 112, the middle portion is formed on the side surface of the dummy mesa DM via the insulating film 109, and the other end contacts the anode electrode 111. Prior to plating, it is preferable to form a seed layer in advance in the area to be plated. The thickness of the anode wiring 113 is preferably set to a thickness (for example, about 2 μm) that can sufficiently prevent voltage drop.

[0084] After this, the wafer is annealed, the back surface of the wafer is polished using a back glider or CMP (Chemical Mechanical Polisher) device to thin the wafer (to about 100 μm, for example), and the back surface of the wafer is anti-reflective coated, and multiple surface-emitting laser arrays are formed in a single, continuous array on one wafer.

[0085] (Step S2: Dicing Process) The dicing process will be described in detail below with reference to the flowchart of FIG.

[0086] In the first step S2-1, dicing streets are formed on a semiconductor wafer SW (SI-GaAs off-substrate) on which multiple surface-emitting laser arrays are formed (see FIG. 27). Specifically, dicing streets DS for dividing the semiconductor wafer SW into multiple surface-emitting laser arrays are formed by photolithography and etching. More specifically, the dicing streets DS are formed on the semiconductor wafer SW so as to describe a parallelogram (here, a parallelogram with non-right angles) that surrounds the area where the surface-emitting laser arrays are formed in a plan view. That is, in this step, oblique exposure feed (oblique shot feed) is performed using a stepper (a step-and-repeat projection exposure apparatus) so that dicing lines in the shape of a parallelogram lattice are formed, as shown in FIG. 27.

[0087] To further clarify, the dicing streets DS are formed by etching the surface (first main surface) of the semiconductor wafer SW using the stealth dicing method, so that the insulating film and the compound semiconductor layer of the resonator 100 do not remain on the surface, resulting in a flat surface that exposes the surface of the semiconductor wafer SW. The width of the dicing streets DS is set to 40% or more of the cut thickness, which is the laser incidence width for stealth dicing. Here, the substrate thickness is 100 μm, and the height difference from the substrate surface to the dicing street surface is 8 μm, so the cut thickness is 92 μm (= 100 μm - 8 μm), and the width of the dicing streets DS is set to 40 μm so that it is 36.8 μm or more. The dicing streets DS are formed on a GaAs off-substrate that is off-axis by 2° from the (100) plane in the

[110] direction, so that the four substrate side surfaces after dicing are two side surfaces parallel to the (011) plane and two side surfaces parallel to the (01-1) plane, resulting in a parallelogram. For this reason, the mask pattern used in photolithography has a parallelogram lattice shape, and the shot feed in stepper exposure is also sent diagonally so as to maintain the parallelogram even when spanning across shots. Note that, if the off-angle θ of the semiconductor wafer SW is, for example, 2°, the interior angle of the parallelogram changes from a right angle by only about 0.04°, but when processing the wafer, the cut line deviates by about 45 μm from one end of the wafer to the other, so it is preferable that the stepper shot shape of the mask pattern is a parallelogram, and that the shot feed in stepper exposure is also sent diagonally so as to maintain the parallelogram even when spanning across shots.

[0088] In the next step S2-2, the back surface of the semiconductor wafer SW is attached to a dicing tape DT. Specifically, the semiconductor wafer SW is mounted on a tape frame via the dicing tape DT with the back surface facing the dicing tape DT.

[0089] In the next step S2-3 (laser irradiation step), a laser beam is scanned along the dicing streets DS. Specifically, the laser beam is irradiated onto the regions between the surface-emitting laser arrays 10′ of the semiconductor wafer SW while being focus-controlled, to form a plurality of modified layers SDL (uneven regions UEA) along the crystal planes (preferably cleavage planes) of the semiconductor wafer SW (see FIG. 28A).

[0090] Specifically, in stealth dicing, the laser focal position for forming the modified layer SDL (uneven region UEA) is offset taking into account the off-angle and orientation of the semiconductor wafer SW so that the semiconductor wafer SW is divided at the center of the dicing street DS. Here, the modified layer SDL is formed at two locations on the backside and frontside of the wafer in the wafer thickness direction along the (011) and (01-1) planes, which are the cleavage planes of the GaAs off-substrate. Therefore, the offset amounts from the center of the dicing street DS are different ( FIGS. 29A and 30A ). When the modified layer SDL is formed at depths of 65 μm and 35 μm from the dicing street DS on the front side of the wafer, the surface on which the modified layer SDL is formed is not perpendicular to the front and back sides of the wafer but is tilted at an angle of 1.4°. Therefore, the offset amounts from the center of the dicing street DS are 1.6 μm and 0.9 μm, respectively. Therefore, the laser focal position is offset and laser irradiation is performed. The depth position, number, and laser power of the modified layer SDL may be set in a combination that causes cracks to penetrate to the back side of the wafer after stealth dicing and does not cause ablation on the front and back sides of the wafer, and are not limited to those described here. In the above focus control, the focus of the laser light is controlled at two depth positions, but for example, if the wafer is thinner, it may be positioned at one depth position, or if the wafer is thicker, it may be controlled at three or more depth positions.

[0091] In the surface-emitting laser array subjected to the laser irradiation process as described above, the modified layers SDL are arranged two-dimensionally along the crystal plane (preferably the cleavage plane), and cracks originating from each of the modified layers SDL formed so as to be aligned along the crystal plane (preferably the cleavage plane) extend along the crystal plane (e.g., the cleavage plane), thereby preventing the formation of irregularities other than the modified layers SDL (uneven regions UEA) (see Figures 28B, 29A, and 30A). This makes it possible to obtain high-quality surface-emitting laser array chips that are less susceptible to dust generation during element separation after stealth dicing and have less meandering cut lines. Furthermore, because the cut lines are less meandering, surface-emitting laser array chips with high flexural strength can be obtained.

[0092] In the next step S2-4 (chip division step), the surface-emitting laser array chips are divided (singled) by expanding. Specifically, by expanding the dicing tape DT, the surface-emitting laser arrays are divided along cracks that penetrate through to the rear surface of the wafer, thereby obtaining multiple surface-emitting laser array chips (see FIGS. 29B and 30B).

[0093] (Step S3: Semiconductor Chip Mounting Process) The semiconductor chip mounting process will be described in detail below with reference to the flowchart of FIG.

[0094] In the first step S3-1, the surface (the surface on the resonator 100 side) of the semiconductor chip SC (surface-emitting laser array chip) on the dicing tape DT is picked up (suction-held) by the first collet Co1 of the flip-chip bonder (see Figures 32 and 33).

[0095] In the next step S3-2, the first collet Co1 holding the semiconductor chip SC is turned over (see FIG. 34).

[0096] In the next step S3-3, the back surface (surface on the semiconductor substrate 15 side) of the semiconductor chip SC is picked up (suction-held) by the second collet Co2 of the flip-chip bonder (see FIGS. 35 and 36).

[0097] In the final step S3-4, the semiconductor chip SC is mounted on the mounting substrate 20 (flip-chip mounting).

[0098] Specifically, first, first bumps BP1 in a softened state are attached to each cathode terminal of the mounting substrate 20, and multiple second bumps BP2 in a softened state are attached to each anode terminal. The arrangement density (area density) and size of each bump may be set so that the spacing between the semiconductor chip SC and the mounting substrate 20 is roughly constant across the surface and so that the difference in the amount of crushing of the bumps when a predetermined pressure is applied to the bumps is small. Here, each bump contains a conductive material that is resistant to crushing when pressure is applied. For example, if each bump is made of solder paste, it is pre-mixed in a hardened state to soften it.

[0099] Next, the semiconductor chip SC held by the second collet Co2 is aligned with the mounting substrate 20 so that the cathode electrode 110 faces the first bump BP1 and the anode electrode 111 faces the multiple second bumps BP2 (see FIG. 37). Then, pressure bonding is performed in a high-temperature environment (see FIG. 38). At this time, the entire semiconductor chip SC is uniformly pressed against the mounting substrate 20 with a predetermined pressure, bonding the cathode electrode 110 to the cathode terminal of the mounting substrate 20 via the first bump BP1 and bonding the anode electrode 111 to the anode terminal of the mounting substrate 20 via the multiple second bumps BP2. As each bump is crushed, it gradually transitions from a softened state to a hardened state, dispersing stress on the semiconductor chip SC from the initial to middle stages of bonding and suppressing chip breakage. From the middle to final stages of bonding, each bump becomes relatively hard, resulting in sufficient bonding strength (bonding rigidity).

[0100] Next, each bump is solidified. Specifically, for example, if each bump is a metal particle paste, it may be solidified by sintering it by heating under pressure, or by sintering it in a heating furnace (by reflow). For example, if each bump is a solder paste, it is solidified by leaving it for a predetermined time after the end of stirring.

[0101] After the bump bonding, an underfill may be injected (preferably filled) into the gap between the semiconductor chip SC and the mounting substrate 20 in order to protect the bonding portion from foreign matter and the like and to improve the bonding strength.

[0102] In this embodiment, since the surface-emitting laser array chip as the semiconductor chip SC has a back-emitting VCSEL, the quality of the back surface of the semiconductor chip SC (the surface on the semiconductor substrate 15 side, hereinafter also referred to as the "chip back surface"), which is the emission surface, is important. If dust adhesion, scratches, meandering cut lines, etc. are present on the back surface of the semiconductor chip SC, there is a risk of characteristic defects, chip cracks, chip chipping, etc., and therefore the suppression of dust generation and meandering cut lines by this technology is very effective.

[0103] To further elaborate, for example, in step S3-3 above, when the semiconductor chip SC is mounted on the mounting substrate 20 with its front surface (the surface facing the resonator 100) facing downward, the collet adsorbs the back surface of the chip. Therefore, if dust adheres to the back surface of the chip, the dust is transferred to and accumulates on the collet, causing problems such as the chip being contaminated or damaged during subsequent chip mounting. Furthermore, since the back surface of the chip is pressed during chip mounting, accumulated dust or meandering of the cut line can cause the chip to crack or chip. Therefore, applying this technology to a back-emitting VCSEL can reduce contamination and scratches on the back surface of the chip, as well as chip cracking and chipping, thereby improving yield. Furthermore, if dust adheres to the back surface of the chip, there is a concern that the area in which dust accumulates may expand due to variations in the relative position between the collet and the chip caused by repeated chip mounting.

[0104] <Effects of the Semiconductor Device and the Method for Manufacturing the Semiconductor Device> Hereinafter, the effects of the semiconductor device 10 and the method for manufacturing the semiconductor device 10 will be described.

[0105] The semiconductor device 10 comprises a semiconductor chip SC including a semiconductor substrate 15 having a plurality of side surfaces, each of the plurality of side surfaces 15a, 15b having a plurality of uneven areas UEA, the semiconductor substrate 15 being an off-substrate, and at least one of the plurality of side surfaces 15a, 15b being a crystal plane of the semiconductor substrate 15.

[0106] In the semiconductor device 10, at least one side surface of the semiconductor substrate 15 is a crystal plane having a plurality of uneven regions UEA (modified layers SDL). In this case, since the plurality of uneven regions UEA are arranged along the side surface, which is a crystal plane, cracks C originating from each uneven region UEA (each modified layer SDL) extend along the side surface during element separation, i.e., the extension direction of the cracks C does not deviate from the direction along the side surface.

[0107] As a result, the semiconductor device 10 can provide a semiconductor device that can suppress a decrease in flatness of at least one side surface of the semiconductor substrate 15 .

[0108] That is, the semiconductor device 10 can suppress meandering of the cut line, generation of dust, chip cracking, and chip chipping during element separation. By suppressing meandering of the cut line, chips with high flexural strength can be obtained. Suppressing dust generation, chip cracking, and chip chipping contributes to improving yield.

[0109] 51A, 51B, and 52, multiple modified layers SDL are formed along a direction perpendicular to the front and back surfaces of the wafer having an off-angle, so that cracks C originating from each modified layer SDL extend along the crystal plane rather than along a side surface that is not a crystal plane (a surface perpendicular to the front and back surfaces of the wafer), i.e., the extension direction of the cracks C deviates from the direction along the side surface. For this reason, in the semiconductor device of the comparative example, it is difficult to suppress a decrease in the flatness of at least one side surface of the semiconductor substrate of the semiconductor chip (a semiconductor element SE' separated into individual pieces).

[0110] Each of the plurality of side surfaces 15a, 15b is preferably a crystal plane of the semiconductor substrate 15. This makes it possible to suppress a decrease in the flatness of each of the plurality of side surfaces 15a, 15b.

[0111] The crystal plane is preferably a cleavage plane, which increases the cleavage property of the crystal plane, thereby reliably preventing a decrease in the flatness of the side surface that is the crystal plane.

[0112] It is preferable that the off-direction of the semiconductor substrate 15 and the side surface which is the crystal plane are non-perpendicular to each other, so that the side surface which is the crystal plane can be used as a cleavage plane, and deterioration in the flatness of the side surface can be reliably suppressed.

[0113] Additionally, when the off-direction of the semiconductor substrate 15 is not perpendicular to any of the side surfaces of the semiconductor substrate 15, the shape of the main surface of the semiconductor substrate 15 becomes a parallelogram, and the stealth dicing effect of the present technology along the cleavable crystal plane is maximized.

[0114] The off-angle of the semiconductor substrate 15 is preferably 0.1° to 15°, both inclusive, so that the semiconductor chip SC can have necessary and sufficient characteristics (for example, polarization controllability).

[0115] The side surface, which is the crystal plane, is preferably inclined with respect to the normal NL of the semiconductor substrate 15 .

[0116] The inclination angle of the side surface, which is the crystal plane, with respect to the normal NL of the semiconductor substrate 15 is preferably 0.1° or more and 15° or less.

[0117] It is preferable that the plurality of concave-convex regions UEA are two-dimensionally arranged along the side surface that is the crystal plane, thereby allowing the extension direction of cracks originating from each of the plurality of concave-convex regions UEA to be aligned with the crystal plane (preferably the cleavage plane), and thus making it possible to sufficiently suppress a decrease in the flatness of the side surface that is the crystal plane.

[0118] The side surface, which is the crystal plane, preferably has an orthogonal side OS perpendicular to the normal line NL and an inclined side SS inclined with respect to the normal line NL, and a plurality of groups of uneven regions, each including at least two uneven regions UEA aligned in a direction parallel to the inclined side SS, are aligned in a direction parallel to the orthogonal side OS. This makes it possible to easily and accurately divide the chips.

[0119] In other words, the side surface, which is the crystal plane, preferably has an orthogonal side OS perpendicular to the normal line NL and an inclined side SS inclined with respect to the normal line NL, and a group of concave-convex regions, each of which includes a plurality of concave-convex regions UEA aligned in a direction parallel to the orthogonal side OS, are preferably aligned in a direction parallel to the inclined side SS. This makes it possible to easily and accurately divide the chips.

[0120] The shape of the side surface, which is a crystal face, is preferably a parallelogram, and more preferably a parallelogram with no right-angled interior angles.

[0121] The shape of the main surface of the semiconductor substrate 15 is preferably a parallelogram, and more preferably a parallelogram whose interior angles are not right angles.

[0122] The semiconductor substrate 15 preferably contains a compound semiconductor (for example, GaAs), which increases the cleavage of the crystal plane, thereby reliably preventing a decrease in the flatness of the side surface, which is the crystal plane.

[0123] The semiconductor chip SC includes a plurality of resonators 100 as light emitting sections provided on the semiconductor substrate 15. This makes it possible to improve the yield and realize a surface emitting laser array chip with high flexural strength.

[0124] The semiconductor chip SC includes a plurality of resonators 100 as light-emitting sections, and each resonator 100 includes a light-emitting layer 105 arranged on one surface (front side) of the semiconductor substrate 15, and emits light to the other surface (back side) of the semiconductor substrate 15. This improves yield and realizes a back-emitting surface-emitting laser array chip with high flexural strength.

[0125] The manufacturing method of the semiconductor device 10 includes the steps of forming a plurality of semiconductor elements (e.g., surface-emitting laser array chips) on a semiconductor wafer SW, irradiating laser light onto areas between the semiconductor elements (e.g., surface-emitting laser arrays) of the semiconductor wafer SW to form a plurality of modified layers SDL along the crystal planes of the semiconductor wafer SW, and singulating the plurality of semiconductor elements.

[0126] According to the method for manufacturing the semiconductor device 10, it is possible to manufacture the semiconductor device 10 in which a decrease in flatness of at least one side surface of the semiconductor substrate 15 can be suppressed.

[0127] The manufacturing method for the semiconductor device 10 further includes a step of forming dicing streets DS in areas between semiconductor elements of the semiconductor wafer SW before the step of forming the multiple modified layers SDL, and in the step of forming the multiple modified layers SDL, laser light is scanned along the dicing streets DS.

[0128] In the step of forming the dicing streets DS, the dicing streets DS are formed so as to describe a parallelogram (for example, a parallelogram with no right angles) that surrounds the region where the semiconductor elements are to be formed in plan view. This allows at least one side surface (for example, all side surfaces) of the semiconductor substrate 15 of the semiconductor chip, which is the individual semiconductor element, to be a crystal plane (preferably a cleavage plane).

[0129] In the above-mentioned singulation process, it is preferable to divide the semiconductor elements by expanding. This makes it possible to obtain chips with cut surfaces (substrate sides) that are free of irregularities caused by chip collisions, etc., compared to when elements are divided by breaking, for example. This further reduces the generation of dust during element division.

[0130] On the other hand, for example, as shown in Figure 53, when the semiconductor chip after the laser irradiation process is divided by breaking using a dicing blade DB, the wafer of the semiconductor chip attached to the dicing tape DT may crack from below starting from the modified layer SDL, and the upper ends of the chips may collide with each other, generating dust.

[0131] In the above embodiment, a GaAs off-substrate is used for the semiconductor substrate 15, but the same effect can be obtained with an off-substrate made of Si, Ge, or other cleavable crystal. Since the higher the cleavability of the crystal, the greater the effect, when the semiconductor substrate 15 is an off-substrate made of a compound semiconductor such as SiC, GaP, or InP in addition to GaAs, a significant effect of suppressing the decrease in flatness of the substrate side surface can be obtained.

[0132] That is, in the present technology, various semiconductor crystals (e.g., hexagonal crystal, cubic crystal, etc.) can be used as the material of the semiconductor substrate. In addition to forming a semiconductor element by growing a semiconductor layer (epitaxial layer) lattice-matched to the semiconductor substrate 15 on the semiconductor substrate 15 as in the above embodiment, a buffer layer may be disposed between the semiconductor substrate 15 and the epitaxial layer in order to suppress misfit dislocations or to accommodate lattice mismatch, or the semiconductor substrate 15 and the semiconductor element may be bonded by heterogeneous material bonding (e.g., room temperature bonding).

[0133] 39 is a schematic plan view of a semiconductor device 10-1 according to a first modification of an embodiment of the present technology. Fig. 40A is a schematic side view (part 1) of the semiconductor device 10-1 of Fig. 39. Fig. 40B is a schematic side view (part 2) of the semiconductor device 10-1 of Fig. 39.

[0134] As shown in Figures 39 to 40B, the semiconductor device 10-1 has a configuration generally similar to that of the semiconductor device 10 according to the above embodiment, except that the shape of each of the first main surface 15c and the second main surface 15d of the semiconductor substrate 15 is a parallelogram (more specifically, a rectangle), and the shape of each of the two opposing side surfaces 15b, 15b is a rectangle.

[0135] In the semiconductor device 10-1, each of the two opposing side surfaces 15a, 15a (here, the side surfaces that are not crystal planes) of the semiconductor substrate 15 has a parallelogram shape with no right angles inside (see FIG. 40A).

[0136] In the semiconductor device 10-1, the off-direction of the semiconductor substrate 15 is perpendicular to each of two opposing side surfaces 15a, 15a of the semiconductor substrate 15, which are not crystal planes.

[0137] In the semiconductor device 10-1, the off-direction of the semiconductor substrate 15 is non-perpendicular to each of two opposing side surfaces 15b, 15b, which are crystal planes (preferably cleavage planes) of the semiconductor substrate 15.

[0138] In the semiconductor device 10-1, two opposing side surfaces 15b, 15b, which are crystal planes (preferably cleavage planes) of the semiconductor substrate 15, are inclined in the same direction with respect to the normal NL of the semiconductor substrate 15 by an inclination angle φ (for example, 0.1° to 15°).

[0139] In the semiconductor device 10-1, two opposing side surfaces 15a, 15a of the semiconductor substrate 15, which are not crystal planes, are parallel to the normal NL of the semiconductor substrate 15.

[0140] In the semiconductor device 10-1, on each of the two opposing side surfaces 15 b, 15 b, a plurality of uneven regions UEA are two-dimensionally arranged along the side surfaces, which are crystal planes. More specifically, in the semiconductor device 10-1, on each of the two opposing side surfaces 15 b, 15 b, an uneven region group including a plurality of (for example, two) uneven regions UEA aligned in the thickness direction of the semiconductor substrate 15 is aligned in a direction parallel to the front and back surfaces of the semiconductor substrate 15.

[0141] In the semiconductor device 10-1, on each of the two opposing side surfaces 15 a, 15 a, a plurality of uneven regions UEA are two-dimensionally arranged along a side surface that is not a crystal plane. More specifically, each of the two opposing side surfaces 15 a, 15 a has an orthogonal side that is perpendicular to the normal line NL of the semiconductor substrate 15 and an inclined side that is inclined with respect to the normal line NL, and a plurality of uneven region groups including a plurality of (for example, two) uneven regions UEA aligned in a direction parallel to the inclined side are aligned in a direction parallel to the orthogonal side.

[0142] The semiconductor device 10-1 can be manufactured by a method generally similar to the method for manufacturing the semiconductor device 10 according to the above embodiment. However, in the method for manufacturing the semiconductor device 10-1, in the step of forming the dicing streets DS, the dicing streets DS are formed so as to describe a rectangle that surrounds the region in which the semiconductor element is formed in plan view.

[0143] Although the semiconductor device 10-1 has room for improvement in suppressing the decrease in flatness of the two side surfaces 15 a, 15 a, it can achieve substantially the same effects as the semiconductor device 10 according to the above embodiment. Note that in the semiconductor device 10-1, the shape of the main surface of the semiconductor substrate 15 may be square.

[0144] 41 is a schematic plan view of a semiconductor device 10-2 according to a second modification of an embodiment of the present technology. Fig. 42A is a schematic side view (part 1) of the semiconductor device 10-2 in Fig. 41. Fig. 42B is a schematic side view (part 2) of the semiconductor device 10-2 in Fig. 41.

[0145] As shown in Figures 41 to 42B, the semiconductor device 10-2 has a configuration generally similar to that of the semiconductor device 10 according to the above embodiment, except that the shape of each of the first main surface 15c and the second main surface 15d of the semiconductor substrate 15 is a parallelogram (more specifically, a rectangle), and the shape of each of the two opposing side surfaces 15a, 15a is a rectangle.

[0146] In the semiconductor device 10-2, each of the two opposing side surfaces 15b, 15b (here, the side surfaces that are not crystal planes) of the semiconductor substrate 15 has a parallelogram shape with no right angles inside.

[0147] In the semiconductor device 10-2, the off-direction of the semiconductor substrate 15 is perpendicular to each of two opposing side surfaces 15b, 15b of the semiconductor substrate 15, which are not crystal planes.

[0148] In the semiconductor device 10-2, the off-direction of the semiconductor substrate 15 is non-perpendicular to each of two opposing side surfaces 15a, 15a, which are crystal planes (preferably cleavage planes) of the semiconductor substrate 15.

[0149] In the semiconductor device 10-2, two opposing side surfaces 15a, 15a, which are crystal planes (preferably cleavage planes) of the semiconductor substrate 15, are inclined in the same direction with respect to the normal NL of the semiconductor substrate 15 by an inclination angle φ (for example, 0.1° to 15°).

[0150] In the semiconductor device 10-2, two opposing side surfaces 15b, 15b of the semiconductor substrate 15, which are not crystal planes, are parallel to the normal NL of the semiconductor substrate 15.

[0151] In the semiconductor device 10-2, on each of the two opposing side surfaces 15 a, 15 a, a plurality of concave-convex regions UEA are two-dimensionally arranged along the side surfaces, which are crystal planes. More specifically, in the semiconductor device 10-2, on each of the two opposing side surfaces 15 a, 15 a, a group of concave-convex regions including a plurality of (for example, two) concave-convex regions UEA aligned in the thickness direction of the semiconductor substrate 15 is aligned in a direction parallel to the front and back surfaces of the semiconductor substrate 15.

[0152] In the semiconductor device 10-2, on each of the two opposing side surfaces 15 b, 15 b, a plurality of uneven regions UEA are two-dimensionally arranged along a side surface that is not a crystal plane. More specifically, each of the two opposing side surfaces 15 b, 15 b may have an orthogonal side that is perpendicular to the normal line NL of the semiconductor substrate 15 and an inclined side that is inclined with respect to the normal line NL, and a plurality of uneven region groups including a plurality of (for example, two) uneven regions UEA aligned in a direction parallel to the inclined side may be aligned in a direction parallel to the orthogonal side.

[0153] The semiconductor device 10-2 can be manufactured by a method generally similar to the method for manufacturing the semiconductor device 10 according to the above embodiment. However, in the method for manufacturing the semiconductor device 10-2, in the step of forming the dicing streets DS, the dicing streets DS are formed so as to describe a rectangle that surrounds the region in which the semiconductor element is formed in plan view.

[0154] Although the semiconductor device 10-2 has room for improvement in suppressing the decrease in flatness of the two side surfaces 15b, 15b, it can achieve substantially the same effects as the semiconductor device 10 according to the above embodiment. Note that in the semiconductor device 10-2, the shape of the main surface of the semiconductor substrate 15 may be square.

[0155] 4. Semiconductor Device According to Modification 3 of Embodiment of the Present Technology FIG. 43 is a schematic perspective view of a semiconductor device 10-3 according to Modification 3 of the embodiment of the present technology.

[0156] The semiconductor device 10-3 has a configuration generally similar to that of the semiconductor device 10 according to the above embodiment, except that a silicon off-substrate is used as the semiconductor substrate 15 and a light receiving unit 200 is added. The semiconductor device 10-3 is capable of receiving light emitted from the resonator 100 as a light emitting unit and reflected by an object at the light receiving unit 200, and can constitute a light receiving and emitting device (at least a part of a distance measuring device). The distance measuring device can include a mounting board on which the semiconductor device 10-3 is mounted, and on which a TOF (Time of Flight) calculation circuit is provided in addition to or instead of a driver (drive circuit).

[0157] When a III-V compound semiconductor is grown on a silicon off-substrate, it is possible to suppress the occurrence of crystal defects such as dislocations. A buffer layer having a lattice constant between that of Si and that of GaAs may be provided between the silicon off-substrate as the semiconductor substrate 15 and the resonator 100.

[0158] As an example, the light receiving unit 200 is provided in the semiconductor substrate 15 with its light receiving surface exposed in a region around the emission region on the back surface (the surface opposite to the resonator 100 side) of the semiconductor substrate 15. The light receiving unit 200 has at least one light receiving element (e.g., a photodiode (PD), an avalanche photodiode (APD), etc.). The light receiving unit 200 may have a condenser lens in front of the light receiving element.

[0159] The semiconductor device 10-3 can provide a light emitting and receiving device that can achieve the same effects as the semiconductor device 10 according to the above embodiment. Note that in the semiconductor device 10-3, a Ge off-substrate may be used as the semiconductor substrate 15 instead of the Si off-substrate.

[0160] 5. First Modification of Semiconductor Chip of Semiconductor Device According to One Embodiment of the Present Technology FIG. 44 is a partial cross-sectional view of a first modification of the semiconductor chip of the semiconductor device according to one embodiment of the present technology.

[0161] As shown in FIG. 44, the semiconductor chip according to the first modification has the same configuration as the semiconductor device 10 according to the above embodiment, except that the surface-emitting laser array chip as the semiconductor chip has a surface-emitting surface-emitting laser.

[0162] In the semiconductor chip according to the first modification, the cavity 100-1 of the surface-emitting laser uses, as the cathode electrode 110, a circumferential (e.g., ring-shaped) electrode that surrounds the non-oxidized region 103a of the oxidized constriction layer 103 in a plan view. Here, the reflectance of the first semiconductor multilayer film reflector 102 is set slightly higher than the reflectance of the second semiconductor multilayer film reflector 107.

[0163] The semiconductor chip according to the first modification can provide a surface-emitting surface-emitting laser array that can achieve the same effects as the semiconductor device 10 according to the above embodiment.

[0164] 6. Modification 2 of Semiconductor Chip of Semiconductor Device According to One Embodiment of the Present Technology FIG. 45 is a partial cross-sectional view of Modification 2 of the semiconductor chip of the semiconductor device according to one embodiment of the present technology.

[0165] The semiconductor chip according to the second modification has the same configuration as the semiconductor device 10 according to the above embodiment, except that it has a plurality of back-emitting light-emitting diodes shown in FIG.

[0166] In the semiconductor chip according to the second modification, the light emitting portion 100-2 of the light emitting diode does not have the first semiconductor multilayer film reflector 102.

[0167] In the semiconductor chip according to variant example 2, the light emitted upward from the light-emitting layer 105 and reflected by the second semiconductor multilayer film reflector 107 and the light emitted downward from the light-emitting layer 105 are combined and emitted to the back side of the semiconductor substrate 15.

[0168] According to the semiconductor device of the second modification, it is possible to provide a back-emitting light-emitting diode array that exhibits the same effects as the semiconductor device 10 according to the above embodiment.

[0169] 7. Third Modification of Semiconductor Chip of Semiconductor Device According to One Embodiment of the Present Technology FIG. 46 is a partial cross-sectional view of a third modification of the semiconductor chip of the semiconductor device according to one embodiment of the present technology.

[0170] The semiconductor chip according to the third modification has the same configuration as the semiconductor chip according to the first modification shown in FIG. 44, except that it has a plurality of surface-emitting light-emitting diodes shown in FIG.

[0171] In the semiconductor chip according to the third modification, the light emitting portion 100-3 of the light emitting diode does not have the first semiconductor multilayer film reflector 102.

[0172] In the semiconductor chip according to variant example 3, the combined light of the light emitted upward from the light-emitting layer 105 and the light emitted downward from the light-emitting layer 105 and reflected by the first semiconductor multilayer film reflector 102 is emitted to the top side of the light-emitting mesa LM.

[0173] According to the semiconductor device of the third modification, it is possible to provide a surface-emitting light-emitting diode array that exhibits the same effects as the semiconductor device 10 according to the above embodiment.

[0174] 47 is a schematic perspective view of a semiconductor device 10-4 according to Modification 4 of an embodiment of the present technology. Fig. 48 is a diagram showing a partial cross-sectional configuration example 1 of the semiconductor device 10-4 of Fig. 47.

[0175] The semiconductor device 10-4 has the same configuration as the semiconductor device 10 according to the above embodiment, except that the semiconductor chip is a surface-emitting laser array chip having a mesare-less structure.

[0176] In the surface-emitting laser of the semiconductor device 10-4, a plurality of trenches T are provided on the upper surface of each resonator 100-4 so as to surround the oxidized constriction layer 103. Here, the bottom surface of each trench T coincides with the upper surface of the first contact layer 101 or is located within the first contact layer 101. Each trench T has the function of exposing the side surface of the oxidized layer 103S, which is the material of the oxidized constriction layer 103, during the oxidation process, and also functions as a groove for drawing out the anode electrode 111.

[0177] The side surfaces and the periphery of the opening of the trench T are covered with an insulating film 109. A first portion (bottom portion) of an anode electrode 111 that is circumferential (e.g., ring-shaped) in a plan view contacts the bottom surface of the trench T, a second portion (middle portion) extends in the depth direction of the trench T, and a third portion (top portion) is provided around the opening of the trench T via the insulating film 109. In a narrow sense, the term "trench" means a "groove," but in a broad sense it also includes a "hole," a "recess," a "dent," etc.

[0178] In the surface-emitting laser of the semiconductor device 10-4, a cathode electrode 110 is provided on the upper surface of the resonator 100-4 (specifically, on the upper surface of the second contact layer 108) so as to be surrounded by an anode electrode 111.

[0179] According to the semiconductor device of the fourth modification, it is possible to provide a surface-emitting laser array chip having a back-side emission type mesare-less structure that exhibits the same effects as the semiconductor device 10 according to the above embodiment.

[0180] 49, which is a partial cross-sectional view of a second example of the semiconductor device 10-4 of FIG. 47, an ion implantation region IIA may be provided instead of the insulating film 109. The ion species used in the ion implantation region IIA may be, for example, H + , B + etc.

[0181] 9. Semiconductor Device According to Modification 5 of Embodiment of the Present Technology FIG. 50 is a schematic perspective view of a semiconductor device 10-5 according to Modification 5 of the embodiment of the present technology.

[0182] 50, the semiconductor device 10-5 has a configuration generally similar to that of the semiconductor device 10 according to the above embodiment, except that a silicon off-substrate is used as the semiconductor substrate 15, and the semiconductor device 10-5 does not have a light-emitting portion but has a light-receiving portion 300. The semiconductor device 10-5 is capable of receiving light from an object (subject) with the light-receiving portion 300, and can constitute a light-receiving device (for example, a part of a distance measuring device). The light-receiving device is a mounting substrate on which the semiconductor device 10-5 is mounted, and can include a mounting substrate on which a TOF (Time of Flight) calculation circuit is provided.

[0183] As an example, the light receiving unit 300 is provided in the semiconductor substrate 15 with its light receiving surface exposed on the first main surface 15c (front surface) of the semiconductor substrate 15. The light receiving unit 300 has at least one light receiving element (e.g., a photodiode (PD), an avalanche photodiode (APD), etc.). The light receiving unit 300 may have a condenser lens in front of the light receiving element.

[0184] The semiconductor device 10-5 can provide a light receiving device that can obtain the same effects as the semiconductor device 10 according to the above embodiment. Note that in the semiconductor device 10-5, a Ge off-substrate may be used as the semiconductor substrate 15 instead of the Si off-substrate.

[0185] 10. Other Modifications of the Present Technology The present technology is not limited to the above-described embodiment and modifications, and can be modified as appropriate.

[0186] In the above embodiment and each modification, the multiple side surfaces of the semiconductor substrate 15 may include side surfaces that are not crystal planes in addition to side surfaces that are crystal planes (preferably cleavage planes).

[0187] The shape of the main surface of the semiconductor substrate 15 may be a polygon other than a parallelogram.

[0188] In the above-described embodiment and each modification, the semiconductor chip of the semiconductor device according to the present technology may be an edge-emitting laser chip. In this case, it is preferable to use highly flat regions other than the concave-convex regions UEA of the two opposing side surfaces, which are crystal planes (preferably cleavage planes), as cavity end faces (reflecting surfaces).

[0189] In the above-described embodiment and some of the modifications (modifications having a light-emitting portion), the semiconductor chip may have a single light-emitting portion provided on the semiconductor substrate 15 .

[0190] In the above-described embodiment and some of the modifications (modifications having a light-emitting portion), the semiconductor chip may not have at least one of the first and second contact layers 101 and 108 .

[0191] In the above-described embodiment and some of the modified examples (modified examples having a light emitting section), the resonators are arranged two-dimensionally, but the resonators may be arranged one-dimensionally.

[0192] For example, current confinement in the light-emitting section is not limited to that achieved by the oxide confinement layer 103. For example, current confinement may be achieved by an ion-implanted region, QWI that confines carriers by creating a bandgap energy difference between the inside and outside of the aperture through Ga vacancy diffusion, a tunnel junction, a buried tunnel junction, or the like. Multiple current confinement structures may also be used in combination. For example, the non-oxidized region 103a of the oxide confinement layer 103 may be surrounded by an ion-implanted region.

[0193] The light emitting portion used in the semiconductor device according to the present technology can be made of a material that emits light at any wavelength within the wavelength range of 200 to 2000 nm.

[0194] The light receiving portion used in the semiconductor device according to the present technology can be made of a material that is sensitive to any wavelength included in the wavelength band of 200 to 2000 nm.

[0195] The light-emitting portion used in the semiconductor device according to the present technology is not limited to a semiconductor multilayer film reflector, and may in fact have a reflector made of one or a combination of two or more types selected from semiconductors, dielectrics, and metals.

[0196] In the above-described embodiment and some of its modifications (modifications having a light-emitting portion), the conductivity types (p-type and n-type) of the first and second semiconductor structures sandwiching the light-emitting layer may be reversed. In this case, the positional relationship between the anode electrode and the cathode electrode must also be reversed.

[0197] Parts of the configurations of the above-described embodiment and each modification may be combined within a range that does not contradict each other.

[0198] The material, thickness, width, shape, size, etc. of each component of the semiconductor chip of the above embodiment and each modification can be changed as appropriate within the range in which the semiconductor chip functions.

[0199] 11. Application Examples to Electronic Devices The technology according to the present disclosure (the present technology) can be applied to various products (electronic devices). For example, the technology according to the present disclosure may be realized as a device mounted on any type of moving body such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot, or on a low-power device (for example, a smartphone, a smartwatch, a tablet, a mouse, a laptop computer, etc.).

[0200] A semiconductor device according to the present technology that has a light-emitting portion can also be applied as a light source for devices that form or display images using light (e.g., printers, copiers, projectors, head-mounted displays, head-up displays, etc.).

[0201] 12. Example of Application of Semiconductor Device to Distance Measuring Device An application example of the semiconductor device 10 according to the above embodiment will be described below.

[0202] 54 illustrates an example of a schematic configuration of a distance measurement device 1000 (distance measuring device) including a semiconductor device 10, as an example of an electronic device according to the present technology. The distance measurement device 1000 measures the distance to a subject S by a TOF (Time Of Flight) method. The distance measurement device 1000 includes the semiconductor device 10. The distance measurement device 1000 includes, for example, the semiconductor device 10, a light receiving device 125, lenses 128 and 138, a signal processing unit 145, a control unit 155, a display unit 165, and a storage unit 175.

[0203] The light receiving device 125 receives light emitted from the semiconductor device 10 and reflected by the specimen S (object). That is, the light receiving device 125 detects the light reflected by the specimen S. The lens 128 is a lens, such as a collimating lens, for converting the light emitted from the semiconductor device 10 into parallel light. The lens 138 is a lens, such as a condensing lens, for collecting the light reflected by the specimen S and guiding it to the light receiving device 125.

[0204] The signal processing unit 145 is a circuit for generating a signal corresponding to the difference between the signal input from the light receiving device 125 and the reference signal input from the control unit 155. The control unit 155 is configured to include, for example, a time-to-digital converter (TDC). The reference signal may be a signal input from the control unit 155 or an output signal from a detection unit that directly detects the output of the semiconductor device 10. The control unit 155 is, for example, a processor that controls the semiconductor device 10, the light receiving device 125, the signal processing unit 145, the display unit 165, and the storage unit 175. The control unit 155 is a circuit that measures the distance to the subject S based on the signal generated by the signal processing unit 145. The control unit 155 generates a video signal for displaying information about the distance to the subject S and outputs it to the display unit 165. The display unit 165 displays the information about the distance to the subject S based on the video signal input from the control unit 155. The control unit 155 stores the information about the distance to the subject S in the storage unit 175.

[0205] In this application example, instead of the semiconductor device 10, any one of the semiconductor devices 10-1, 10-2, 10-3, 10-4, and 10-5 can be applied to the distance measurement device 1000.

[0206] 13. Example in which distance measuring device is mounted on a moving body> FIG. 55 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a moving body control system to which the technology according to the present disclosure can be applied.

[0207] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 55, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (interface) 12053.

[0208] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0209] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0210] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, a distance measurement device 12031 is connected to the outside-vehicle information detection unit 12030. The distance measurement device 12031 includes the above-described distance measurement device 1000. The outside-vehicle information detection unit 12030 causes the distance measurement device 12031 to measure the distance to an object outside the vehicle (subject S) and acquires the distance data obtained thereby. The outside-vehicle information detection unit 12030 may perform object detection processing for people, cars, obstacles, signs, etc. based on the acquired distance data.

[0211] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0212] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane departure warning, etc.

[0213] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0214] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0215] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying information to vehicle occupants or the outside of the vehicle. In the example of Fig. 55, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0216] FIG. 56 is a diagram showing an example of the installation position of the distance measurement device 12031.

[0217] In FIG. 56, a vehicle 12100 has distance measurement devices 12101, 12102, 12103, 12104, and 12105 as a distance measurement device 12031.

[0218] Distance measuring devices 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of vehicle 12100. Distance measuring device 12101 provided on the front nose and distance measuring device 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire data ahead of vehicle 12100. Distance measuring devices 12102 and 12103 provided on the side mirrors mainly acquire data on the sides of vehicle 12100. Distance measuring device 12104 provided on the rear bumper or back door mainly acquires data behind vehicle 12100. The forward data acquired by distance measuring devices 12101 and 12105 is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, etc.

[0219] 56 shows an example of the detection ranges of the distance measuring devices 12101 to 12104. Detection range 12111 indicates the detection range of the distance measuring device 12101 provided on the front nose, detection ranges 12112 and 12113 indicate the detection ranges of the distance measuring devices 12102 and 12103 provided on the side mirrors, respectively, and detection range 12114 indicates the detection range of the distance measuring device 12104 provided on the rear bumper or back door.

[0220] For example, based on the distance data obtained from the distance measuring devices 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the detection ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which runs autonomously without relying on driver operation.

[0221] For example, based on the distance data obtained from the distance measuring devices 12101 to 12104, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0222] The above describes an example of a mobile object control system to which the technology according to the present disclosure can be applied. The technology according to the present disclosure can be applied to the distance measurement device 12031 of the above-described configuration.

[0223] The present technology can also be configured as follows. (1) A semiconductor device comprising: a semiconductor chip including a semiconductor substrate having a plurality of side surfaces, each of the plurality of side surfaces having a plurality of uneven regions, the semiconductor substrate being an off-axis substrate, and at least one of the plurality of side surfaces being a crystal plane of the semiconductor substrate. (2) The semiconductor device according to (1), in which each of the plurality of side surfaces is a crystal plane of the semiconductor substrate. (3) The semiconductor device according to (1) or (2), in which the crystal plane is a cleavage plane. (4) The semiconductor device according to any one of (1) to (3), in which an off-axis direction of the semiconductor substrate and the side surface being the crystal plane are non-perpendicular. (5) The semiconductor device according to any one of (1) to (4), in which the plurality of side surfaces include a side surface that is not the crystal plane. (6) The semiconductor device according to any one of (1) to (5), in which an off-axis angle of the semiconductor substrate is 0.1° or more and 15° or less. (7) The semiconductor device according to any one of (1) to (6), wherein the side surface, which is the crystal plane, is inclined with respect to the normal to the semiconductor substrate. (8) The semiconductor device according to (7), wherein the inclination angle of the side surface, which is the crystal plane, with respect to the normal is 0.1° or more and 15° or less. (9) The semiconductor device according to any one of (1) to (8), wherein the plurality of uneven regions are arranged two-dimensionally along the side surface, which is the crystal plane. (10) The semiconductor device according to any one of (1) to (9), wherein the side surface, which is the crystal plane, has an orthogonal side perpendicular to the normal to the semiconductor substrate and an inclined side inclined with respect to the normal, and wherein a plurality of uneven region groups, each including at least two of the uneven regions arranged in a direction parallel to the inclined side, are arranged in a direction parallel to the orthogonal side. (11) The semiconductor device according to any one of (1) to (10), wherein the shape of the side surface, which is the crystal plane, is a parallelogram. (12) The semiconductor device according to any one of (1) to (11), wherein the shape of the side surface that is not a crystal plane is a parallelogram. (13) The semiconductor device according to any one of (1) to (12), wherein the shape of the main surface of the semiconductor substrate is a parallelogram. (14) The semiconductor device according to any one of (1) to (13), wherein the semiconductor substrate includes a compound semiconductor.(15) The semiconductor device according to any one of (1) to (14), wherein the semiconductor substrate includes any one of GaAs, Si, Ge, SiC, GaP, and InP. (16) The semiconductor device according to any one of (1) to (15), wherein the semiconductor chip includes a light emitting portion and / or a light receiving portion provided on the semiconductor substrate. (17) The semiconductor device according to (16), wherein the semiconductor chip includes the light emitting portion, and the light emitting portion includes a light emitting layer disposed on one surface of the semiconductor substrate and emits light to the other surface of the semiconductor substrate. (18) The semiconductor device according to any one of (1) to (17), further including a mounting substrate on which the semiconductor chip is mounted. (19) An electronic device including a semiconductor chip including a semiconductor substrate having a plurality of side surfaces, wherein each of the plurality of side surfaces has a plurality of uneven regions, the semiconductor substrate is an off-substrate, and at least one of the plurality of side surfaces is a crystal plane of the semiconductor substrate. (20) A method for manufacturing a semiconductor device, comprising: forming a plurality of semiconductor elements on a semiconductor wafer having an off-angle; irradiating regions of the semiconductor wafer between the semiconductor elements with laser light to form a plurality of modified layers along a crystal plane of the semiconductor wafer; and singulating the plurality of semiconductor elements. (21) The method for manufacturing a semiconductor device according to (20), further comprising, before the step of forming the plurality of modified layers, forming dicing streets in the regions of the semiconductor wafer between the semiconductor elements, wherein the step of forming the plurality of modified layers involves scanning the laser light along the dicing streets. (22) The method for manufacturing a semiconductor device according to (21), wherein, in the step of forming the dicing streets, the dicing streets are formed so as to describe a parallelogram that surrounds the regions where the semiconductor elements are formed in a plan view. (23) The method for manufacturing a semiconductor device according to any one of (20) to (22), wherein, in the step of singulating, the plurality of semiconductor elements are divided by expanding.

[0224] 10, 10-1, 10-2, 10-3, 10-4, 10-5: semiconductor device 15: semiconductor substrate 15a, 15b: side surface 20: mounting substrate 100: resonator (light emitting portion) 200, 300: light receiving portion 105: light emitting layer SC: semiconductor chip SW: semiconductor wafer UEA: uneven area SDL: modified layer θ: off angle φ: tilt angle OS: orthogonal side SS: tilted side DS: dicing street

Claims

1. A semiconductor device comprising: a semiconductor chip including a semiconductor substrate having a plurality of side surfaces, each of the plurality of side surfaces having a plurality of uneven regions, the semiconductor substrate being an off-substrate, and at least one of the plurality of side surfaces being a crystal plane of the semiconductor substrate.

2. The semiconductor device according to claim 1, wherein each of said plurality of side surfaces is a crystal plane of said semiconductor substrate.

3. The semiconductor device according to claim 1, wherein the crystal plane is a cleavage plane.

4. The semiconductor device according to claim 1, wherein the off-direction of the semiconductor substrate and the side surface which is the crystal plane are non-perpendicular to each other.

5. The semiconductor device according to claim 1, wherein said plurality of side surfaces include a side surface that is not a crystal plane.

6. The semiconductor device according to claim 1, wherein the off-angle of the semiconductor substrate is 0.1° or more and 15° or less.

7. The semiconductor device according to claim 1, wherein the side surface, which is the crystal plane, is inclined with respect to the normal to the semiconductor substrate.

8. The semiconductor device according to claim 7, wherein the side surface, which is the crystal plane, has an inclination angle with respect to the normal line of 0.1° or more and 15° or less.

9. The semiconductor device according to claim 1, wherein said plurality of uneven regions are arranged two-dimensionally along said side surface which is said crystal plane.

10. The semiconductor device according to claim 1, wherein the side surface, which is the crystal plane, has an orthogonal side perpendicular to a normal to the semiconductor substrate and an inclined side inclined with respect to the normal, and wherein a plurality of groups of uneven regions, each group including at least two of the uneven regions aligned in a direction parallel to the inclined side, are aligned in a direction parallel to the orthogonal side.

11. The semiconductor device according to claim 1, wherein the shape of the side surface that is the crystal plane is a parallelogram.

12. The semiconductor device according to claim 5, wherein the shape of the side surface that is not a crystal plane is a parallelogram.

13. The semiconductor device according to claim 1, wherein the shape of the main surface of the semiconductor substrate is a parallelogram.

14. The semiconductor device according to claim 1, wherein the semiconductor substrate includes a compound semiconductor.

15. The semiconductor device according to claim 1, wherein the semiconductor substrate includes any one of GaAs, Si, Ge, SiC, GaP, and InP.

16. The semiconductor device according to claim 1, wherein the semiconductor chip includes a light emitting portion and / or a light receiving portion provided on the semiconductor substrate.

17. The semiconductor device according to claim 16, wherein the semiconductor chip includes the light emitting portion, and the light emitting portion includes a light emitting layer disposed on one surface side of the semiconductor substrate and emits light to the other surface side of the semiconductor substrate.

18. A method for manufacturing a semiconductor device, comprising: a step of forming a plurality of semiconductor elements on a semiconductor wafer having an off-angle; a step of irradiating a laser beam onto an area between the semiconductor elements of the semiconductor wafer to form a plurality of modified layers along a crystal plane of the semiconductor wafer; and a step of singulating the plurality of semiconductor elements.

19. The method for manufacturing a semiconductor device according to claim 18, further comprising the step of forming dicing streets in regions between the semiconductor elements of the semiconductor wafer before the step of forming the plurality of modified layers, wherein in the step of forming the plurality of modified layers, the laser light is scanned along the dicing streets.

20. The method for manufacturing a semiconductor device according to claim 19, wherein in the step of forming the dicing streets, the dicing streets are formed so as to describe a parallelogram that surrounds the region in which the semiconductor element is to be formed in plan view.

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