Semiconductor storage device and method for manufacturing semiconductor storage device

Abstract

Provided is a semiconductor storage device with which it is possible, in an MRAM, to reduce the circuit area and achieve high density. A semiconductor storage device 1000 comprises a memory cell array 10 in which a plurality of memory cells 100 are arranged in a matrix. Each memory cell 100 includes a topological antiferromagnetic body to which data can be written by spin inflow caused by a write current, a first electrode provided so as to supply the write current to the topological antiferromagnetic body, and a switch element SW00 for opening and closing a write current supply path leading to the topological antiferromagnetic body. The topological antiferromagnetic body exhibits an abnormal Hall effect due to a write current in a prescribed direction. Data is read by detecting a difference in potential resulting from the abnormal Hall effect.

Description

Semiconductor memory device and method of manufacturing the same

[0001] The present invention relates to a semiconductor memory device and a method for manufacturing the same.

[0002] (Background of magnetic random access memory)

[0003] A nonvolatile memory device using a magnetoresistive effect element (MRAM: Magnetic Random Access Memory or Magnetoresistive Random Access Memory) is attracting attention for its application to next-generation logic integrated circuits.

[0004] As an example of such an MRAM configuration, a spin transfer torque (STT) MRAM is known (see Patent Documents 1 and 2).

[0005] STT-MRAM is a type of non-volatile memory that retains information even when the power is turned off. It is expected to be used in a wide range of applications, including AI (artificial intelligence), IoT (Internet of Things), and automotive applications.

[0006] In STT-MRAM, data is rewritten by passing a current through a memory element called a magnetic tunnel junction (MTJ) element. Conventionally, an MTJ element has a structure in which two ferromagnetic layers sandwich a tunnel insulating film. The resistance to the current passing through this ferromagnetic layer / tunnel insulating film / ferromagnetic layer is small when the magnetic field directions of the two ferromagnetic layers are parallel, and large when they are antiparallel. This phenomenon is called the tunnel magnetoresistance effect. STT-MRAM operates on the principle of reversing the magnetization direction of the MTJ element using the torque action of electron spin.

[0007] One direction for the development of STT-MRAM is to replace cache memory embedded in microprocessors, for example. Current cache memory uses volatile memory (SRAM: Static Random Access Memory). Replacing this with non-volatile STT-MRAM will enable the power supply to be cut off more frequently. As a result, power consumption can be significantly reduced.

[0008] On the other hand, another direction in the development of STT-MRAM is to aim at partially replacing DRAM (Dynamic Random Access Memory).

[0009] In this situation, antiferromagnetic materials are attracting attention as a replacement for ferromagnetic materials in MRAM, in the hope of further improving device performance. Antiferromagnetic materials have the following advantages: (i) they do not produce stray magnetic fields, allowing for high-density devices with simple structures, (ii) their spin resonance frequency is higher at THz than that of ferromagnetic materials (GHz), enabling higher speeds, and (iii) they offer greater freedom in material selection.

[0010] However, because antiferromagnets do not have spontaneous magnetization, it is generally difficult to detect and control the spontaneous response resulting from the spin structure.

[0011] In contrast, the topological antiferromagnetic metal Mn ３ Sn is being actively researched as a candidate material for nonvolatile memory that will lead to the realization of terahertz electronic devices.

[0012] Mn ３ Sn is an antiferromagnetic material in which a non-collinear spin structure, called the inverse 120-degree structure, appears at temperatures as high as 430 K. This antiferromagnetic spin structure exhibits a macroscopic broken time-reversal symmetry even in a zero-magnetization state, similar to the case of ferromagnetic order. This is due to the strongly ordered spin structure (cluster magnetic octupole) in which six spins, each consisting of three sublattices, are arranged in a two-layer kagome lattice.

[0013] Here, a "topological antiferromagnet" is a Weyl semimetal that exhibits a topological semimetal state in which the interior is semimetallic and the surface is metallic.

[0014] For example, it has been demonstrated that in Weyl antiferromagnets, information can be stored by the direction of a virtual magnetic field, i.e., the distribution of Weyl particles in momentum space, instead of by magnetization.

[0015] JP 2013-214768 A JP 2012-164754 A

[0016] https: / / www.issp.u-tokyo.ac.jp / maincontents / news2.html?pid=10521

[0017] However, conventional STT-MRAMs impose large voltages across the device's tunnel oxide during programming, resulting in a continuous trade-off between data retention, programming endurance, and programming speed.

[0018] Given this background, in MRAM, when the MTJ element is miniaturized through integration, it is possible to reduce the write current itself, but at present it cannot be said that sufficient consideration has been given to the circuit configuration for high integration.

[0019] The present invention has been made to solve the above-mentioned problems, and has an object to provide a semiconductor memory device in an MRAM that can reduce the circuit area and increase the density.

[0020] Another object of the present invention is to provide a method for writing and reading data in an MRAM, which is a semiconductor memory device that allows a reduction in circuit area.

[0021] Another object of the present invention is to provide a method for manufacturing an MRAM, which is a semiconductor memory device that can reduce the circuit area.

[0022] (Item 1) According to one aspect of the present invention, there is provided a semiconductor memory device comprising a plurality of memory cells, each of the memory cells including an electrode extending in a first direction and a second direction, and a memory layer provided at a portion of the electrode where the first direction and the second direction intersect, the memory layer including a non-collinear antiferromagnetic material, the electrode having a first node and a second node provided at both ends of the electrode in the first direction, respectively, for supplying a write current and a read current to the electrode, and a third node and a fourth node provided at both ends of the electrode in the second direction, respectively, for detecting a Hall voltage generated in the memory layer when the read current is flowing, and the read current is smaller than the write current.

[0023] (Item 2) Preferably, the semiconductor memory device of item 1 further includes a first write wiring and a second write wiring, and each of the memory cells further includes a first switch element provided between the first write wiring and the first node for selectively conducting the write current and the read current, and a second switch element provided between the second write wiring and the second node for selectively conducting the write current and the read current, and further includes a data write circuit that writes data of different values ​​into the memory layer by changing the direction of the write current flowing between the first node and the second node.

[0024] (Item 3) Preferably, the semiconductor memory device of item 2 further includes a first read wiring and a second read wiring, and each of the memory cells further includes a third switch element provided between the first read wiring and the third node and selectively turned on when the read current is conducted, and a fourth switch element provided between the second read wiring and the fourth node and selectively turned on when the read current is conducted, and the semiconductor memory device further includes a current supply circuit for supplying a current between the first node and the second node, and a potential difference detection circuit for detecting a potential difference between the third node and the fourth node, and further includes a read circuit for reading the data written to the memory layer by the current supply circuit supplying the read current between the first node and the second node and the potential difference detection circuit detecting a potential difference between the third node and the fourth node when the read current is flowing.

[0025] (Item 4) Preferably, in the semiconductor memory device of item 3, the potential difference detection circuit includes a multi-stage potential difference amplifier circuit.

[0026] (Item 5) Preferably, in the semiconductor memory device according to any one of items 1 to 4, the plurality of memory cells are arranged in a matrix.

[0027] (Item 6) Preferably, in the semiconductor memory device of item 1, the plurality of memory cells are arranged in a matrix, and the semiconductor memory device further includes a first write wiring and a second write wiring commonly connected to the second node of the plurality of memory cells arranged in a column direction, and each of the memory cells further includes a first switch element provided between the first write wiring and the first node for selectively conducting the write current and the read current, and further includes a current supply circuit that writes data of different values ​​to the memory layer by changing the direction of the write current flowing between the first node and the second node.

[0028] (Item 7) Preferably, the semiconductor memory device of item 6 further includes a first read wiring and a second read wiring commonly connected to the third node of a plurality of the memory cells arranged in a row direction, each of the memory cells further including a fourth switch element provided between the first read wiring and the fourth node and selectively brought into a conductive state when the read current is conducted, the semiconductor memory device further includes a potential difference detection circuit that detects a potential difference between the third node and the fourth node, and the current supply circuit further includes a read circuit that, when performing a read operation of data written to the memory layer, supplies the read current between the first node and the second node, and, when the read current is flowing, detects a potential difference between the third node and the fourth node, thereby reading the data written to the memory layer.

[0029] (Item 8) Preferably, the semiconductor memory device of item 1 further comprises a current supply circuit for supplying a current between the first node and the second node, and a potential difference detection circuit for detecting a potential difference between the third node and the fourth node, and further comprises a read circuit for reading the data written in the memory layer when performing a read operation of data written in the memory layer, the current supply circuit supplies the read current between the first node and the second node, and the potential difference detection circuit detects a potential difference between the third node and the fourth node when the read current is flowing, thereby reading the data written in the memory layer, and the plurality of memory cells are arranged in a matrix, and the electrodes of the memory cells adjacent in a row direction are integrally formed.

[0030] (Item 9) Preferably, in the semiconductor memory device of item 8, the potential difference detection circuit includes an integration circuit that integrates the detected potential difference.

[0031] (Item 10) Preferably, in the semiconductor memory device of item 8, the potential difference detection circuit includes a plurality of sample and hold circuits that hold data read out for each column, and each of the plurality of sample and hold circuits holds a potential when the stored data is read out and a reference potential that is read out after writing complementary data during a period when a column is selected and the data is read out, and includes an amplifier circuit that amplifies the stored data by comparing the potential when the stored data is read out with the reference potential based on the data held in the plurality of sample and hold circuits.

[0032] (Item 11) Preferably, the semiconductor memory device according to item 8 further comprises shunt wiring for shunting between the memory cells with respect to the electrodes of the memory cells adjacent in the row direction.

[0033] According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor memory device, the semiconductor memory device comprising a plurality of memory cells, each of the memory cells comprising an electrode extending in a first direction and a second direction, and a memory layer provided at a portion of the electrode where the first direction and the second direction intersect, the memory layer including a non-collinear antiferromagnetic material, the electrode having a first node and a second node provided at both ends of the electrode in the first direction, respectively, for supplying a write current and a read current to the memory layer, and a third node and a fourth node provided at both ends of the electrode in the second direction, respectively, for detecting a Hall voltage generated in the memory layer when the read current is flowing, the method comprising the steps of: forming a circuit on a semiconductor substrate; and forming, on a substrate, a write switching element for opening and closing a conduction path of a write current to the memory layer, a read switching element for opening and closing a read path of a read voltage from the memory layer, as well as a write wiring for supplying the write current and a read wiring that serves as a read path of the read voltage, and forming a planarized insulating film layer on the write switching element, the read switching element, the write wiring, and the read wiring, and further comprising a post-processing step of forming the memory layer after the pre-processing step, the post-processing step including a step of forming an electrode (LEL) on the uppermost insulating film layer, the electrode (LEL) extending in a first direction and a second direction, and a step of forming the memory layer (110) provided in a portion of the electrode (LEL) and including a non-collinear antiferromagnetic material.

[0034] (Item 13) In the method for manufacturing a semiconductor memory device according to item 12, the electrode and the memory layer are preferably formed by processing them with different resist patterns.

[0035] (Item 14) Preferably, in the method for manufacturing a semiconductor memory device according to item 12, the electrode and the memory layer are formed by processing using the same resist pattern.

[0036] (Item 15) Preferably, in the method of manufacturing a semiconductor memory device according to item 12, one surface of the wiring located below the electrode contacts one surface of the electrode.

[0037] According to the configuration of the semiconductor memory device of the present invention, in the STT-MRAM, it is possible to reduce the circuit area and increase the density.

[0038] 13 is a conceptual diagram showing a configuration of a magnetic tunnel junction element constituting a memory cell. FIG. 14 is a conceptual diagram for explaining control relating to writing data to a Hall effect memory cell according to a first embodiment. FIG. 15 is a conceptual diagram for explaining control relating to writing data to a Hall element memory cell according to a first embodiment. FIG. 16 is a conceptual diagram showing control relating to reading data from a Hall element memory cell according to a first embodiment. FIG. 17 is a conceptual diagram showing control relating to reading data from a Hall element memory cell according to a first embodiment. FIG. 18 is a diagram showing an example of a circuit configuration of an amplifier. FIG. 19 is a diagram showing another example of a circuit configuration of an amplifier. FIG. 19 is a diagram showing another example of a circuit configuration of an amplifier. FIG. 19 is a diagram showing an example of the structure and operation of a memory cell array of Hall element memory cells according to the present embodiment. FIG. 20 is a diagram showing an example of the structure and operation of a memory cell array of Hall element memory cells according to a second modification of the first embodiment. FIG. 21 is a diagram showing the structure and operation of a Hall element memory cell array according to a second modification of the first embodiment. FIG. 22 is a diagram for explaining operations of a first read amplifier, an integrating circuit, and a second read amplifier shown in FIG. 22. FIG. 23 is a plan view of a Hall element memory cell. 14A ; FIG. 14B is a cross-sectional view of a Hall element memory cell taken along the cross section AA′ of FIG. 14A ; FIG. 14C is a cross-sectional view of a state in which a buried contact is formed between a lower electrode and an uppermost wiring layer after a multi-layer wiring process; FIG. 14D is a cross-sectional view of a state in which a lower electrode layer is formed after forming the buried contact; FIG. 14E is a cross-sectional view of a state in which a resist layer is formed for patterning the lower electrode layer; FIG. 14F is a cross-sectional view of a state in which the lower electrode layer is patterned by etching using the resist layer; FIG. 14G is a cross-sectional view of a state in which a resist layer is formed for patterning the data storage layer; FIG. 14H is a cross-sectional view of a Hall element memory cell taken along the cross section AA′ of FIG. 23A ; FIG. 14H is a cross-sectional view of a Hall element memory cell; FIG. 14H is a cross-sectional view of a Hall element memory cell taken along the cross section AA′ of FIG. 24A ;

[0039] Preferred embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. In this specification and drawings, components having substantially the same functional configurations are designated by the same reference numerals, and redundant description will be omitted.

[0040] [Embodiment 1] A Hall element memory cell 100 according to this embodiment will be described with reference to FIG. 1 . FIG. 1 is a schematic diagram of the Hall element memory cell 100 according to this embodiment. As shown in FIG. 1 , the cell 100 of the Hall element memory (also referred to as a Hall effect memory) includes a lower electrode LEL and a data storage layer 110. In this specification, the Hall element memory cell 100 may be referred to as a memory cell 100. The data storage layer 110 corresponds to an example of a "storage layer." The lower electrode LEL corresponds to an example of an "electrode."

[0041] The bottom electrode LEL extends in a first direction D1 and a second direction D2. The first direction D1 and the second direction D2 intersect. The bottom electrode LEL has, for example, four nodes T below the data storage layer 110. The four nodes T include a first node T1, a second node T2, a third node T3, and a fourth node T4. The first node T1 and the second node T2 are provided at both ends of the bottom electrode LEL in the first direction D1, respectively. The third node (T3) and the fourth node (T4) are provided at both ends of the bottom electrode LEL in the second direction D2, respectively.

[0042] The data storage layer 110 is provided at a portion where the first direction and the second direction of the bottom electrode LEL intersect. In this embodiment, the data storage layer 110 is provided between a first node T1 and a second node T2. The data storage layer 110 is provided between a third node T4 and a fourth node T4. The data storage layer 110 includes a non-collinear antiferromagnetic material as described below.

[0043] Contacts are provided below the nodes T of the lower electrodes LEL. The contacts are connected to the outside of the memory cell 100 via wiring. For example, the contacts can be connected to another wiring layer.

[0044] The first node T1 and the second node T2 are nodes T for supplying a write current to the bottom electrode LEL for writing data to the data storage layer 110. For example, the first node T1 and the second node T2 are connected to an external power supply. By making the potential of the first node T1 higher than the potential of the second node T2, a current flows from the first node T1 to the second node T2. If the value of this current is greater than a predetermined threshold, spins are flowed into the data storage layer. This forms a memory orientation in the data storage layer 110 (i.e., memory is written).

[0045] Furthermore, for example, when a read current flows from the first node T1 to the second node T2, a potential difference occurs in the bottom electrode in a direction perpendicular to the current direction. Here, a potential difference occurs from the third node T3 to the fourth node T4, causing a current to flow. This is based on the so-called Hall effect. In this specification, the potential difference between the third node T3 and the fourth node T4 based on the Hall effect may be referred to as a "Hall voltage." In this manner, the first node T1 and the second node T2 are nodes T for supplying a read current for data to the data storage layer 110 to the bottom electrode LEL. The third node T3 and the fourth node T4 are nodes T for detecting the Hall voltage generated in the data storage layer 110 when a read current flows.

[0046] The material used for the data storage layer 110 is, for example, Mn ３ The material can be an antiferromagnetic material such as X (X = Sn, Ge, etc.). These antiferromagnetic materials have a non-collinear chiral spin structure, for example, called a kagome surface. By using such materials, the Hall effect can be generated without the need for an external magnetic field (the so-called anomalous Hall effect). This technology enables drive control (e.g., writing and reading) at the first node T1, the second node T2, and the third node T3 and the fourth node T4.

[0047] 2 and 3 are conceptual diagrams for explaining control relating to writing data to the Hall element memory cell 100 according to the first embodiment.

[0048] An example of control relating to writing data to the Hall element memory cell 100 according to the first embodiment will be described with reference to Figures 2 and 3. Figures 2 and 3 are diagrams showing an example of a circuit of the Hall element memory cell 100 and an example of control relating to writing.

[0049] The semiconductor memory device includes a Hall element memory cell 100, a data write circuit 190, and a data read circuit as shown in FIG. 2. However, FIG. 2 illustrates only one Hall element memory cell 100. In reality, a plurality of such Hall element memory cells 100 are arranged in a matrix. Each Hall element memory cell 100 is selected by activating the potential of a write enable wiring WE (word line) in the row direction. Read wirings RL1 and RL2 are arranged in the column direction and selected by activating the potential of a read enable wiring RE. The potential of the write enable wiring (word line) WE is controlled by a row selection circuit (not shown) in response to an externally applied address signal, and the potential of the read enable wiring RE is controlled by a column selection circuit (not shown). 2 , the semiconductor memory device 1000 includes a memory cell 100, a first write line WL1, a second write line WL2, a first read line RL1, a second read line RL2, a write enable line WE, a read enable line RE, a data write circuit 190, an amplifier AMP, and a resistor R1. As described above, the data write circuit 190 includes current supply circuits 191 and 192. As described above, the arrangement of the multiple memory cells 100, i.e., the memory cell array, will be described later with reference to FIG. 9 . In this embodiment, the potential supplied from the current supply circuit 190, as described later, is controlled and switched by the data write circuit. The Hall element memory cell 100 further includes a first switch element (TR1), a second switch element (TR2), a third switch element TR3, and a fourth switch element TR4 in addition to the lower electrode LEL and the data storage layer 110. The amplifier AMP corresponds to an example of a "potential difference detection circuit."

[0050] The first switch element TR1 is provided between the first write line WL1 and the first node T1. The first switch element TR1 selectively conducts a write current and a read current. In this embodiment, the first switch element TR1 is a transistor. A write enable line WE is connected to the gate of the first switch element TR1.

[0051] The second switch element TR2 is provided between the second write line WL2 and the second node T2. The second switch element TR2 selectively conducts a write current and a read current. In this embodiment, the second switch element TR2 is a transistor. The gate of the second switch element TR2 is connected to the write enable line WE.

[0052] The third switch element TR3 is provided between the first read line RL1 and the third node T3. The third switch element TR3 is selectively turned on when the read current is conducted.

[0053] The fourth switch element TR4 is provided between the second read line RL2 and the fourth node T4, and is selectively turned on when the read current is conducted.

[0054] The amplifier AMP detects the potential difference between the third node T3 and the fourth node T4. More specifically, the amplifier AMP amplifies the potential difference between the third node T3 and the fourth node T4.

[0055] (Data Write Operation) The data write circuit 190 writes data of different values ​​to the data storage layer 110 by changing the direction of the write current flowing between the first node T1 and the second node T2. The data write circuit 190 includes a first data write circuit 191 and a second data write circuit 192. The first data write circuit 191 switches the potential of the first write wiring WL1. More specifically, the first data write circuit 191 switches the potential of the first write wiring WL1 to one of the Vdd level, the GND level, and the Vdd (I-small) level. The potential of the Vdd (I-small) level is lower than the potential of the Vdd level. The second data write circuit 192 switches the potential of the second write wiring WL2. More specifically, the second data write circuit 192 switches the potential of the second write wiring WL2 between the Vdd level and the GND level.

[0056] In controlling writing, the write enable line WE is activated to connect the first node T1 and the second node T2 to the power supply. The read enable line RE is inactivated. The spin direction of the data memory layer 110 can be reversed by passing a write current through the bottom electrode LEL in a direction from the first node T1 to the second node T2, or in a direction from the second node T2 to the first node T1. More specifically, for example, as shown in FIG. 2 , when writing data “0” to the data memory layer 110, a write current is passed in a direction from the first node T1 to the second node T2. When writing data “1” to the data memory layer 110, a write current is passed in a direction from the second node T2 to the first node T1.

[0057] The current value in the write control is set to be larger than the read current in the read control, which will be described later. In other words, the read current is smaller than the write current. If the current value in the read control is set so that the data in the data storage layer 110 is not destroyed during reading, there is no need to perform write control again. For this reason, the amount of current from the power supply (Vdd) during reading is referred to as Vdd(I-small) here to distinguish it from the amount of current during writing. The setting of the amount of current from Vdd and Vdd(I-small) varies depending on the type of material of the data storage layer 110, but it is preferable to set it so that at least (amount of current from Vdd) > (amount of current from Vdd(I-small)). As shown in FIGS. 2 and 3 , by varying the magnitude of the potential difference between the first node T1 and the second node T2, the direction of current flow can be controlled and the spin direction of the data storage layer 110 can be set.

[0058] 3 , when writing data “0” to the data storage layer 110, the first data write circuit 191 switches the potential of the first write line WL1 to the Vdd level. The second data write circuit 192 switches the potential of the second write line WL2 to the GND level. Therefore, a write current flows from the first node T1 to the second node T2. As a result, the spin direction of the data storage layer is set, and data “0” is written to the data storage layer 110.

[0059] 3, when writing data "1" to the data storage layer 110, the first data write circuit 191 switches the potential of the second write line WL2 to the GND level. The second data write circuit 192 switches the potential of the second write line WL2 to the Vdd level. Therefore, a write current flows from the second node T2 to the first node T1. As a result, the spin direction of the data storage layer is set, and data "1" is written to the data storage layer 110.

[0060] As described above, the semiconductor memory device 1000 includes the data write circuit 190. The data write circuit 190 writes data of different values ​​into the memory layer (data memory layer 110) by changing the direction of the write current flowing between the first node T1 and the second node T2. Therefore, by controlling the direction of the write current, data of different values ​​can be easily written.

[0061] (Data Read Operation) FIGS. 4 and 5 are conceptual diagrams showing control relating to reading data from the Hall element memory cell 100 according to the first embodiment.

[0062] An example of control relating to data read from the Hall element memory cell 100 according to the first embodiment will be described with reference to Figures 4 and 5. Figures 4 and 5 are diagrams showing an example of a circuit of the Hall element memory cell 100 and an example of control relating to read. Figures 4 and 5 correspond to the spin directions in the data storage layers shown in Figures 2 and 3, respectively.

[0063] The current supply circuit 190 supplies a read current between the first node T1 and the second node T2, which is smaller than the current during a write operation, as described above. When performing a read operation of data written to the data storage layer 110, the current supply circuit 190 supplies a read current between the first node T1 and the second node T2. The current supply circuit 190 includes a first current supply circuit 191 and a second current supply circuit 192. The first current supply circuit 191 switches the potential of the first write wiring WL1. More specifically, the first current supply circuit 191 switches the potential of the first write wiring WL1 between the GND level and the Vdd(I-small) level. In this embodiment, when performing a read operation of data written to the data storage layer 110, the first current supply circuit 191 switches the potential of the first write wiring WL1 to the Vdd(I-small) level, as shown in FIGS. 4 and 5 . The second current supply circuit 192 switches the potential of the second write wiring WL2. More specifically, the second current supply circuit 192 switches the potential of the second write wiring WL2 between the Vdd level and the GND level. In this embodiment, when performing a read operation of data written in the data memory layer 110, the second current supply circuit 192 switches the potential of the second write wiring WL2 to the GND level, as shown in FIGS. 4 and 5 .

[0064] Read control is performed by activating the read enable line RE and connecting the first node T1 and the second node T2 to Vdd (I-small) or GND. The direction of the read current can be one-way, from the first node T1 to the second node T2, but the direction of the current is not particularly limited. At this time, a potential difference occurs between the third node T3 and the fourth node T4 depending on the magnitude of the current. The magnitude of the potential difference depends on the magnitude of the current. This potential difference also causes a current to flow externally between the third node T3 and the fourth node T4 (here, through resistor R1). Reading is possible by amplifying this potential difference (±AmV) with an amplifier AMP.

[0065] As shown in FIG. 4 , when data "0" is written to the data memory layer 110, the first current supply circuit 191 switches the potential of the first write wiring WL1 to the Vdd (I-small) level when performing a read operation of the data written to the data memory layer 110. Therefore, a read current flows from the first node T1 to the second node T2. As a result, the potential of the third node T3 becomes ½ Vdd + AmV, and the potential of the fourth node T4 becomes ½ Vdd - AmV. In other words, when data "0" is written to the data memory layer 110, the voltage of the third node T3 is higher than the voltage of the fourth node T4. By amplifying this potential difference (± AmV) with the amplifier AMP, the data "0" written to the data memory layer 110 can be read.

[0066] As shown in FIG. 5 , when data "1" is written to the data storage layer 110 and a read operation of the data written to the data storage layer 110 is performed, the first current supply circuit 191 switches the potential of the first write wiring WL1 to the Vdd (I-small) level. Therefore, a read current flows from the first node T1 to the second node T2. As a result, the potential of the third node T3 becomes ½ Vdd-AmV, and the potential of the fourth node T4 becomes ½ Vdd+AmV. This potential difference causes a current to flow externally between the third node T3 and the fourth node T4 (here, through resistor R1). When data "1" is written to the data storage layer 110, a current flows in the opposite direction to the read current shown in FIG. 4 . In other words, when data "1" is written to the data storage layer 110, the voltage of the third node T3 is lower than the voltage of the fourth node T4. By amplifying this potential difference (±AmV) with the amplifier AMP, the data "1" written in the data storage layer 110 can be read.

[0067] In this way, the potential difference between the third node T3 and the fourth node T4 is complementary when data "0" is written in the data memory layer 110 and when data "1" is written in the data memory layer 110. Therefore, when a read current is flowing, the amplifier AMP detects the potential difference between the third node T3 and the fourth node T4, thereby reading the data written in the data memory layer 110.

[0068] Furthermore, when a read current is flowing, the read circuit reads data written in the memory layer (data memory layer 110) by detecting the potential difference between the third node T3 and the fourth node T4 using a potential difference detection circuit (amplifier AMP). Therefore, the data written in the memory layer (data memory layer 110) can be read with high accuracy.

[0069] As mentioned above, the read current is set smaller than the write current, but the potential difference also depends on the read current. Therefore, it is desirable to set the potential difference within the range that can be amplified by the amplifier AMP and to set the read current and write current to satisfy this. When the read enable wiring RE is activated during read, the third node T3 and the fourth node T4 for reading the memory cell 100 are shorted by the resistor R1, causing a current to flow in a loop. This generates a potential difference between the third node T3 and the fourth node T4, which is amplified by the amplifier AMP, enabling readout. At this time, a current path is formed between the third node T3 and the fourth node T4, causing complementary potential differences to be generated. This eliminates the need for a new reference potential for comparison during amplification by the amplifier AMP, and reduces the circuit configuration of the read amplifier AMP. This reduces the circuit area, enabling higher density. It also increases the margin, leading to faster readout.

[0070] (Configuration 1 of Amplifier Circuit) Fig. 6 is a diagram showing an example of the circuit configuration of the amplifier AMP. An example of the amplifier AMP will be described with reference to Fig. 6 .

[0071] As shown in FIG. 6 , the amplifier AMP includes transistors ATR1, ATR2, ATR3, ATR4, and ATR5. Transistors ATR1, ATR2, and ATR3 are PMOS transistors. Transistors ATR4 and ATR5 are NMOS transistors. The gate of transistor ATR1 is connected to the selection signal line / SE. The gate of transistor ATR2 is connected to a fourth node T4. The gate of transistor ATR3 is connected to a third node T3. The gate of transistor ATR4 is connected to the drain of transistor ATR3 and the drain of transistor ATR5. The gate of transistor ATR5 is connected to the drain of transistor ATR2 and the drain of transistor ATR4. NMOS transistors ATR4 and ATR5 are connected so as to be cross-coupled.

[0072] 4 and 5 , the potential difference between the third node T3 and the fourth node T4 is complementary when data "0" is written to the data memory layer 110 and when data "1" is written to the data memory layer 110. For example, when a read operation of data written to the data memory layer 110 is performed on a memory cell 100 in which data "0" is written to the data memory layer 110, the potential of the third node T3 is ½ Vdd + 15 mV, and the potential of the fourth node T4 is ½ Vdd - 15 mV. On the other hand, when a read operation of data written to the data memory layer 110 is performed on a memory cell 100 in which data "1" is written to the data memory layer 110, the potential of the third node T3 is ½ Vdd - 15 mV, and the potential of the fourth node T4 is ½ Vdd + 15 mV. As described above, in the example shown in FIG. 6, during a data read operation of the data storage layer 110, a potential difference of 30 mV occurs depending on the data written in the memory cell 100.

[0073] The amplifier AMP amplifies the potential difference between the third node T3 and the fourth node T4. When the selection signal line / SE is activated, the difference in current corresponding to the potential of the fourth node T4 input to the gate of the PMOS transistor ATR2 and the third node T3 input to the gate of the PMOS transistor ATR3 is amplified by the cross-coupled NMOS transistors ATR4 and ATR5, and the result is output.

[0074] (Configuration 2 of Amplifier Circuit) FIG. 7 is a diagram showing another example of the circuit configuration of the amplifier AMP.

[0075] Another example of the amplifier AMP will be described with reference to Fig. 7. Description of parts that overlap with the circuit configuration described with reference to Fig. 6 will be omitted.

[0076] 4 and 5 , the potential difference between the third node T3 and the fourth node T4 is complementary when data "0" is written to the data memory layer 110 and when data "1" is written to the data memory layer 110. For example, when a read operation of data written to the data memory layer 110 is performed on a memory cell 100 in which data "0" is written to the data memory layer 110, the potential of the third node T3 is GND+15 mV and the potential of the fourth node T4 is GND−15 mV. On the other hand, when a read operation of data written to the data memory layer 110 is performed on a memory cell 100 in which data "1" is written to the data memory layer 110, the potential of the third node T3 is GND−15 mV and the potential of the fourth node T4 is GND+15 mV. As described above, in the example shown in FIG. 6, during a data read operation of the data storage layer 110, a potential difference of 30 mV occurs depending on the data written in the memory cell 100.

[0077] 7 includes a multi-stage potential difference amplifier circuit. In this embodiment, the amplifier AMP includes two stages of potential difference amplifier circuits (potential difference amplifier circuit AMP1 and potential difference amplifier circuit AMP2). The potential difference amplifier circuit AMP1 and the potential difference amplifier circuit AMP2 are connected in series. The potential difference amplifier circuit AMP2 is disposed in a subsequent stage of the potential difference amplifier circuit.

[0078] The potential difference amplifier circuit AMP1 amplifies the potential difference between the third node T3 and the fourth node T4. The potential difference amplifier circuit AMP1 includes transistors ATR6, ATR7, ATR8, ATR9, current sources IS1 and IS2. The transistors ATR6, ATR7, and ATR8 are PMOS transistors. The transistor ATR9 is an NMOS transistor. The gate of the transistor ATR6 is connected to the fourth node T4. The gate of the transistor ATR7 is connected to the third node T3. The gate of the transistor ATR8 is connected to the selection signal line / SE. The gate of the transistor ATR9 is connected to the selection signal line SE. The current source IS1 is connected in series between the transistors ATR6 and ATR9. The current source IS2 is connected in series between the transistors ATR7 and ATR9.

[0079] The potential difference amplifier circuit AMP1 amplifies the potential difference between the third node T3 and the fourth node T4. When the selection signal line / SE and the selection signal line SE are activated, the current source IS1 and the current source IS2 amplify the difference in current corresponding to the potential of the fourth node T4 input to the gate of the PMOS transistor ATR6 and the potential of the third node T3 input to the gate of the PMOS transistor ATR7, and output the amplified current to the potential difference amplifier circuit AMP2.

[0080] The potential difference amplifier circuit AMP2 has the same configuration as the amplifier AMP described with reference to Fig. 6. The potential difference amplifier circuit AMP2 further amplifies the potential difference amplified by the potential difference amplifier circuit AMP1. The potential difference amplifier circuit AMP2 outputs the amplified result.

[0081] The amplifier AMP is configured to include a multi-stage potential difference amplifier circuit (two stages in FIG. 7), thereby making it possible to further increase the amplification factor.

[0082] (Configuration 3 of Amplifier Circuit) Another example of the amplifier AMP will be described with reference to Fig. 8. Description of parts that overlap with the circuit configuration described with reference to Fig. 6 will be omitted. Fig. 8 is a diagram showing another example of the circuit configuration of the amplifier AMP.

[0083] As shown in FIG. 8, the semiconductor memory device 1000 further includes a current source IS3 and a current source IS4.

[0084] The current source IS3 is connected to the third node T3. The read enable line RE is connected to the current source IS3. When the potential of the read enable line RE is activated, the current source IS3 is activated.

[0085] The current source IS4 is connected to the fourth node T4. The read enable line RE is connected to the current source IS4. When the potential of the read enable line RE is activated, the current source IS4 is activated.

[0086] 8, when the potential of the read enable line RE is activated during a read operation, the current source IS3 is activated, and the potential of the third node T3 becomes ½Vdd+α+15 mV. Here, +α is the potential based on the current source IS3. In other words, the potential increases by α of the potential based on the current source IS3.

[0087] As explained with reference to Figures 4 and 5, when data "0" is written in the data memory layer 110 and when data "1" is written in the data memory layer 110, the potential difference between the third node T3 and the fourth node T4 is complementary.

[0088] For example, when a memory cell 100 in which data "0" is written performs a read operation of the data written in the data memory layer 110, the potential of the third node T3 becomes ½ Vdd + α + 15 mV. Here, + α is the potential based on the current source IS3. As shown in FIG. 4 , when reading data "0" written in the data memory layer 110, a current flows in the direction into the third node T3. In other words, this is the same direction as the current flowed by the current source IS3. Therefore, the current source IS3 functions to increase the potential difference of the memory cell 100.

[0089] Furthermore, when a read operation of data written in the data memory layer 110 is performed on a memory cell 100 in which data "0" is written, the potential of the fourth node T4 becomes ½Vdd-α-15 mV. Here, -α is the potential based on the current source IS4. As shown in FIG. 4, when reading data "0" written in the data memory layer 110, a current flows in the direction that flows out of the fourth node T4. In other words, this is the same direction as the current flowed by the current source IS4.

[0090] As described above, when reading data "0" written in the data memory layer 110, the potential of the third node T3 becomes ½ Vdd + α + 15 mV, and the potential of the fourth node T4 becomes ½ Vdd - α - 15 mV. Therefore, the potential difference of the fourth node T4 becomes +2α + 30 mV.

[0091] On the other hand, when a read operation of data written in the data memory layer 110 is performed on a memory cell 100 in which data "1" is written, the potential of the third node T3 becomes ½Vdd-α-15 mV. Here, -α is the potential based on the current source IS3. As shown in FIG. 5 , when reading data "0" written in the data memory layer 110, a current flows in a direction that causes the current to flow out of the third node T3. In other words, the direction is opposite to the direction of the current flowed by the current source IS3.

[0092] Furthermore, when a read operation of data written in the data memory layer 110 is performed on a memory cell 100 in which data "1" is written, the potential of the fourth node T4 becomes ½ Vdd + α + 15 mV. Here, -α is the potential based on the current source IS4. As shown in FIG. 4 , when reading data "0" written in the data memory layer 110, a current flows in a direction that flows into the fourth node T4. In other words, the direction is opposite to the direction of the current flowed by the current source IS4.

[0093] As described above, when reading data "1" written in the data storage layer 110, the potential of the third node T3 becomes ½ Vdd-α-15 mV, and the potential of the fourth node T4 becomes ½ Vdd+α+15 mV. Therefore, the potential difference at the fourth node T4 becomes −2α-30 mV.

[0094] As described with reference to FIG. 8 , the semiconductor memory device 1000 further includes a current source IS3 and a current source IS4. The current source IS3 is connected to a third node T3. The current source IS4 is connected to a fourth node T4. Therefore, when performing a read operation of data written to the data storage layer 110, a potential difference based on the current source IS3 is added to the potential of the third node T3. Furthermore, a potential difference based on the current source IS4 is added to the potential of the fourth node T4. Therefore, the potential difference between the third node T3 and the fourth node T4 can be increased. As a result, the data written to the data storage layer 110 can be read satisfactorily using the amplifier AMP while suppressing an increase in the read current.

[0095] (Configuration of Semiconductor Memory Device 1000) The configuration of the semiconductor memory device 1000 according to this embodiment will be described with reference to Fig. 9. Fig. 9 is a diagram showing an example of the structure and operation of the memory cell array 10 of the Hall element memory cell 100 according to this embodiment. Fig. 9 shows only a portion of the memory cells, and although in reality many more memory cells and corresponding signal lines are arranged in both the row direction and the column direction, they are not shown in Fig. 9.

[0096] 9, a semiconductor memory device 1000 includes a memory cell array 10, a data write circuit 1003, and a data read circuit 1002. The memory cell array 10 includes a plurality of memory cells 100 arranged in a matrix.

[0097] Data write circuit 1003 includes a write row decoder 1010 and a write column decoder 1030. In a data write operation, write row decoder 1010 selects a row to which data is to be written, and write column decoder 1030 selects a column to which data is to be written.

[0098] The following describes the operation in which a memory cell 100 (enclosed within the dotted line frame in FIG. 9) is selected, data is written, and data is read.

[0099] When writing data, the write row decoder 1010 activates the potential of the write enable line, thereby rendering transistors TR001 and TR002 conductive. The write column decoder 1030 selects a column. At this time, one end of the memory cell is connected to a reference power supply (shown as an inverted triangle in the figure, with a potential of, for example, ½ Vdd) via transistor TR001. The write column decoder 1030 also renders transistor WTR01 conductive, thereby selecting write source line WSL0. Depending on the data to be written, the other end of the memory cell is connected to either the power supply potential Vdd or the ground potential GND via transistors WTR01 and TR002. The direction of the write current is selected depending on the data to be written. The write column decoder 1030 renders transistor STR12 conductive, thereby rendering the unselected write source line WSL1 at the reference power supply level, and thus no write current flows through the unselected memory cells.

[0100] During data read, the write row decoder 1010 and write column decoder 1030 select rows and columns, similar to the data write operation. The write row decoder 1010 activates the potential of the write enable line, thereby turning on transistors TR001 and TR002. The write column decoder 1030 turns on transistor WTR01, causing a current to flow through write source line WSL0 of the selected memory cell. At this time, the current flowing through write source line WSL0 is smaller (less than half) than during write. Here, the gate potential of the write source driver (transistor WTR01) controlled by the write column decoder 1030 is lower than during data write, thereby connecting write source line WSL0 to the power supply potential Vdd while reducing the current driving capability of the write source driver. Note that a circuit for lowering the gate potential of the write source driver is not shown, but a general circuit may be used.

[0101] The read circuit 1002 includes a read row decoder 1020 and a read column decoder 1040. During data read, a current flows through the read source line RSL0 selected by the read row decoder 1020. The read row decoder 1020 turns on transistor RTR0 to create a path for current to flow through the read source line RSL0 of the selected memory cell. This current flows through the memory cell, and the current flowing through the memory cell selected by the read column decoder 1040 turning on transistors TR003 and TR004 is sent to read amplifier RA0, where it is compared with a reference voltage (Vref), and a result according to the comparison is output.

[0102] In this example, a transistor for selection processing is placed at each of the four terminals of the memory cell, and there are two transistors in the same current flow. Therefore, in order to reduce the resistance value that occurs in the current path, it is desirable to increase the gate width of the transistors when the same current is flowing.

[0103] First Modification of First Embodiment FIG. 10 is a diagram showing the structure and operation of a memory array 10 of Hall element memory cells 100 according to a first modification of the first embodiment.

[0104] Here, too, the memory cell array 10 is configured by arranging memory cells 100 (inside the dotted line frame) in row and column directions.

[0105] The difference from the configuration in Figure 9 is that, while in Figure 9 a transistor for selection processing is arranged at each of the four terminals of memory cell 100, in Figure 10 one transistor for selection processing is provided in the path for supplying current and one transistor for selection processing is provided in the path for detecting Hall voltage.

[0106] 9, the write source lines (write source lines WSL0, WSL1) are connected to the second node T2 via the second switching elements (transistor TR002, transistor TR012, transistor TR102, transistor TR112) of each memory cell 100, but in Fig. 10, the write source lines (write source lines WSL0, WSL1) are connected directly to the second node T2 without going through a transistor. In other words, the semiconductor memory device 1000 shown in Fig. 10 includes write source lines (write source lines WSL0, WSL1) that are commonly connected to the second nodes T2 of a plurality of memory cells 100 arranged in the column direction.

[0107] 9, the read source lines (read source lines RSL0, RSL1) are connected to the third node T via the third switching elements (transistor TR003, transistor TR013, transistor TR103, transistor TR113) of each memory cell 100, but in Fig. 10, the read source lines (read source lines RSL0, RSL1) are connected directly to the third node T3 without going through a transistor. In other words, the semiconductor memory device 1000 shown in Fig. 10 includes read source lines (read source lines RSL0, RSL01) commonly connected to the third nodes T3 of a plurality of memory cells 100 arranged in the row direction.

[0108] Write circuit 1003 includes a write row decoder 1010 and a write column decoder 1030. When writing data, write row decoder 1010 selects a row to which data is to be written, and write column decoder 1030 selects a column to which data is to be written.

[0109] The read circuit 1002 includes a read row decoder 1020 and a read column decoder 1040. When reading data, the write row decoder 1010 and the write column decoder 1030 also operate in cooperation. When reading data, the read row decoder 1020 selects the row from which data is to be read, and the read column decoder 1040 selects the column from which data is to be read.

[0110] The following description will be made of the operation in which the memory cell 100 in FIG. 10 (enclosed within the dotted line frame in FIG. 10) is selected, data is written, and data is read.

[0111] When writing data, the write row decoder 1010 activates the potential of the write enable line, thereby turning on transistor TR001. A column is selected by the write column decoder 1030. At this time, one end of the memory cell is connected to a reference power supply (shown as an inverted triangle in the figure, with a potential of, for example, 1 / 2 Vdd) via transistor TR001. The write column decoder 1030 also turns on transistor WTR01, thereby selecting write source line WSL0. Depending on the data to be written, the other end of the memory cell is connected via transistor WTR01 to either power supply potential Vdd or ground potential GND. The direction of the write current is selected depending on the data to be written. As in FIG. 9, the unselected write source line WSL1 is at the reference power supply level.

[0112] During data read, the write row decoder 1010 and write column decoder 1030 select rows and columns in the same way as during data write operations. The write row decoder 1010 activates the potential of the write enable line, causing transistor TR001 to become conductive. The write column decoder 1030 then causes transistor WTR01 to become conductive, causing a current to flow through write source line WSL0 of the selected memory cell. At this time, the current flowing through write source line WSL0 is smaller (half or less) than during write, as in FIG. 9 .

[0113] When reading data, a current flows through the read source line RSL0 selected by the read row decoder 1020. The read row decoder 1020 turns on the transistor RTR0 to create a path for the current to flow through the read source line RSL0 of the selected memory cell. This current flows through the memory cell, and the current flowing through the memory cell selected by the read column decoder 1040 turning on the transistor TR004 is sent to the read amplifier RA0, where it is compared with a reference voltage (Vref), and a result according to the comparison is output.

[0114] 10, the semiconductor memory device 1000 includes second write lines (write source lines WSL0, WSL1) commonly connected to the second nodes T2 of the memory cells 100 arranged in the column direction. Therefore, the second write lines (write source lines WSL0, WSL1) are directly connected to the second nodes T2 without passing through a transistor. This reduces the area of ​​the memory cell array 10.

[0115] The semiconductor memory device 1000 also includes first read wirings (read source lines RSL0 and RSL01) commonly connected to the second nodes T3 of the memory cells 100 arranged in the row direction. Therefore, the first read wirings (read source lines RSL0 and RSL01) are directly connected to the third node T3 without passing through a transistor. This reduces the area of ​​the memory cell array 10.

[0116] 11, the amplifier AMPa includes a first read amplifier RA01, a second read amplifier RA02, and a sample hold SH0. The amplifier AMPb includes a first read amplifier RA11, a second read amplifier RA12, and a sample hold SH1. The second read amplifier RA02 and the second read amplifier RA12 correspond to an example of an "amplification circuit."

[0117] The sample and hold circuits SH0 and SH1 hold the potentials read out three times for each column, as described below. The sample and hold circuit SH0 is provided between the first read amplifier RA01 and the second read amplifier RA02. The sample and hold circuit SH1 is provided between the first read amplifier RA11 and the second read amplifier RA12.

[0118] The second read amplifier RA02 amplifies the data held by the sample and hold circuit SH0 based on three corresponding read potentials (the potential when the stored data is read and the potentials read after writing the complementary data) during the period when a column is selected and data is read. The second read amplifier RA12 amplifies the stored data by comparing the potential when the stored data is read with the potential (reference potential) read after writing the complementary data, based on the data held by the sample and hold circuit SH1.

[0119] In the second modification, the array selection and write and read operations are characterized by high-precision write and read operations using small signals.

[0120] The specific operation is as follows: 1) Write desired data to a selected memory cell.

[0121] In the subsequent read operation, the following processes are performed: 2) Read from the selected memory cell and hold the read potential 3) Write and read "1" data to the selected memory cell and hold the read potential 4) Write and read "0" data to the selected memory cell and hold the read potential 5) Determine the read data of 2) by comparing the potentials of 3) with those of 4) and 5) 6) Write back the data read in 5) to the selected memory cell

[0122] As shown in FIG. 11 , the memory cell array 10 is configured by arranging memory cells 100 (within the dotted line frame) in a row and column direction. However, in Modification 2, the read terminals of each memory cell are connected in series by lower wiring within the same row. Specifically, the lower electrodes LEL of memory cells adjacent in the row direction are integrally formed. Note that the semiconductor memory device 1000 may be configured such that shunt wirings L0 and L1 are further provided for the lower electrodes LEL of memory cells 100 adjacent in the row direction. The shunt wirings L0 and L1 shunt between the memory cells 100. With the above configuration, there are no transistors in the read direction within the area equivalent to one memory cell, and the area of ​​the memory cell array 10 is reduced.

[0123] In a data write operation, the write row decoder 1010 selects a row to which data is to be written, and the write column decoder 1030 selects a column to which data is to be written.

[0124] The following describes the operation in which a memory cell 100 (enclosed within the dotted line frame in FIG. 9) is selected, data is written, and data is read.

[0125] When writing data, the write row decoder 1010 activates the potential of the write enable line, thereby turning on the transistors TR0011 and TR0021. The write column decoder 1030 activates the potential of the write enable line, thereby turning on the transistors TR0012 and TR0022.

[0126] As described above, memory cells are selected by the write row decoder 1010 and the write column decoder 1030. At this time, one end of the memory cell is connected to the reference power supply (shown as an inverted triangle in the figure, with a potential of, for example, 1 / 2 Vdd) via transistors TR0011 and TR0012. Furthermore, the write column decoder 1030 places transistor WTR01 in a conductive state, thereby selecting write source line WSL0. Depending on the data to be written, the other end of the memory cell is connected to either the power supply potential Vdd or the ground potential GND via transistors TR0021, TR0022, and WTR01. The direction of the write current is selected depending on the data to be written. Note that, as in FIG. 9, the unselected write source line WSL1 is at the reference power supply level.

[0127] When reading data, the write row decoder 1010 and the write column decoder 1030 select rows and columns in the same manner as when writing data. When the write row decoder 1010 and the write column decoder 1030 activate the potential of the write enable line, the transistors TR0011, TR0021, TR0012, and TR0022 are rendered conductive.

[0128] Write column decoder 1030 turns on transistor WTR01, causing a current to flow through write source line WSL0 of the selected memory cell. At this time, the current flowing through write source line WSL0 is smaller (half or less) than during writing, as in FIG. 9 .

[0129] During data read, a current flows through the serially connected lower wirings selected by the read row decoder 1020. The read row decoder 1020 turns on the transistor RTR0 to create a path for the current to flow through the serially connected lower wirings of the selected memory cell. This current flows within the memory cell, and then flows serially between memory cells in the row direction. The current that flows through the memory cell selected by the write row decoder 1010 and the write column decoder 1030 is sent to the first read amplifier RA01. The potential difference generated by the current that flows through the memory cell is amplified by the first read amplifier RA01. This value is stored in the sample-and-hold circuit SH0 preceding the second read amplifier RA02. Here, three potential level information (the initial potential read by a normal read operation, the potential resulting from the read after writing data "1" to the selected memory cell, and the potential resulting from the read after writing data "0" to the selected memory cell) is stored in the sample-and-hold circuit SH0. The second read amplifier RA02 determines whether the potential resulting from the initial readout as described above is closer to the potential after writing "1" data or the potential after writing "0" data, and determines whether the initially stored data is "0" or "1".

[0130] After that, the determined data is written back in the same manner as in the data write operation, and the read data is restored to the selected memory cell.

[0131] With the above configuration, even when data is read in the row direction via a path that is higher resistance than the source wiring and is the lower electrodes connected in series, write and read operations can be performed with high precision using small signals, as described above.

[0132] [Third Modification of First Embodiment] FIG. 12 is a diagram showing the structure and operation of a Hall element memory cell array 10 according to a third modification of the first embodiment.

[0133] The third modification is also characterized in that the array selection, write and read operations are high-precision write and read operations using small signals.

[0134] The configuration differs from that of the second modification of the first embodiment shown in FIG. 11 in the following points.

[0135] That is, in the configuration shown in Fig. 12, integrating circuits SB0 and SB1 are provided instead of the sample-and-hold circuits SH0 and SH1 shown in Fig. 11. As shown in Fig. 12, the amplifier AMPa includes a first read amplifier RA01, a second read amplifier RA02, and an integrating circuit SB0. The amplifier AMPb includes a first read amplifier RA11, a second read amplifier RA12, and an integrating circuit SB1. The integrating circuits SB0 and SB1 integrate the detected potential difference.

[0136] 11, information on three potential levels (the initial potential read by a normal read operation, the potential resulting from the read after writing data "1" to the selected memory cell, and the potential resulting from the read after writing data "0" to the selected memory cell) is stored in the integrating circuit SB0, and for example, the second read amplifier RA02 compares these potentials to determine the data stored in the selected memory cell. In contrast, the configuration of FIG. 12 is configured to enable highly accurate data reading by integrating the output from the first read amplifier in an integrating circuit.

[0137] In other respects, the configuration in FIG. 12 is similar to the configuration in FIG. 11, and therefore description thereof will not be repeated.

[0138] 13A and 13B are diagrams for explaining the operations of the first read amplifiers RA01 and RA11, the integrating circuits SB0 and SB1, and the second read amplifiers RA02 and RA12 shown in FIG.

[0139] 13A, after the potential RE of the enable line is activated, while a read current is flowing through the first node T1 and the second node T2, the first read amplifier RA01 amplifies the potential difference generated between the third node T3 and the fourth node T4. While the potential RE of the enable line is active, the integrating circuit SB0 integrates this amplified potential difference, thereby amplifying the signal, and the second read amplifier RA02 outputs, for example, read data "0".

[0140] In FIG. 13B, the stored data is the opposite of that in FIG. 13A, so the output of the integrating circuit is also the opposite, and the output of the second read amplifier RA02 is also the opposite.

[0141] (Structure and Manufacturing Method of Hall Element Memory Cell) Next, an example of a manufacturing method of the Hall element memory cell according to this embodiment will be described.

[0142] In the conventional manufacturing of MRAMs and the like, memory cells are formed between wiring processes. Therefore, the memory cells are susceptible to the heat treatments in the remaining wiring processes. Therefore, in the embodiment described above, the memory cells are formed after the final wiring process.

[0143] This makes it possible to avoid the influence of heat treatment in the wiring process.

[0144] 14A and 14B are diagrams showing an example of the configuration of a Hall element memory: Fig. 14A is a plan view of a Hall element memory cell, and Fig. 14B is a cross-sectional view of the Hall element memory cell taken along the line AA' in Fig. 14A.

[0145] As shown in FIG. 14A, a data storage layer 110 is provided on a bottom electrode LEL that extends from a first node T and to a second node T2.

[0146] As shown in FIG. 14B, the configuration of the data storage layer 110 is not particularly limited. For example, the data storage layer 110 may be made of a topological antiferromagnetic material such as Mn ３ The shape of Sn is set back with respect to the shape of the lower electrode LEL.

[0147] In addition, the multilayer wiring layers 120 and 140 are connected by buried contacts 130 and 150. Hereinafter, as a pre-process, a write switching element (write transistor (not shown)) for opening and closing a conduction path of a write current to the data storage layer and a read switching element (read transistor (not shown)) for opening and closing a read path of a read voltage from the data storage layer are formed on a semiconductor substrate (e.g., a Si substrate), and then a write wiring for supplying a write current and a read wiring serving as a read path of a read voltage are formed as layers in either of the multilayer wiring layers 120 and 140. Furthermore, as shown in FIG. 14B , a planarized insulating film layer is formed on these write transistors, read transistors, write wiring, and read wiring. After this pre-process, a post-process for forming a data storage layer is performed. In the post-process, as described below, a lower electrode LEL extending in a first direction and a second direction is formed on the planarized insulating film layer. Subsequently, the data storage layer 110 is formed on the lower electrode LEL and includes a non-collinear antiferromagnetic material. The lower electrode LEL and the uppermost wiring layer 120 are connected by buried contacts T1 and T2.

[0148] In the post-process, the structure shown in FIG. 14B is obtained by, for example, three lithographic processes after a multilayer wiring and a planarized insulating film are formed.

[0149] Such a process will be described below.

[0150] FIG. 15 is a cross-sectional view in which buried contacts T1 and T2 are formed between the lower electrode LEL and the uppermost wiring layer 120 after the multi-layer wiring process.

[0151] 15, after the multi-layer wiring is formed, buried contacts T1 and T2, which are connection channels from the uppermost contact metal to the lower electrode LEL, are formed by a first lithography process. As the buried contacts, for example, a metal layer such as Ta can be used.

[0152] FIG. 16 is a cross-sectional view showing a state in which the lower electrode layer is formed after the buried contacts T1 and T2 are formed.

[0153] As shown in FIG. 16, the lower electrode layer can be formed by sputtering tungsten, for example.

[0154] FIG. 17 is a cross-sectional view in which a resist layer RES for patterning the lower electrode layer is formed.

[0155] As shown in FIG. 17, a pattern is formed by the resist RES so that the lower electrode has a planar structure as shown in FIG. 14A, leaving behind the regions where the first node T1 and the second node T2 are connected.

[0156] FIG. 18 is a cross-sectional view showing the lower electrode layer patterned by etching using a resist layer RES.

[0157] As the etching method, for example, the well-known reactive ion etching (RIE) method can be used.

[0158] FIG. 19 is a cross-sectional view in which the resist is removed after etching the lower electrode layer.

[0159] The resist can be removed by, for example, a well-known ashing method.

[0160] FIG. 20 is a cross-sectional view showing the state in which the data storage layer 110 is formed after the lower electrode layer is patterned.

[0161] As shown in FIG. 20, the data storage layer 110 is made of, for example, Mn ３ The Sn layer can be formed by a sputtering method or the like.

[0162] FIG. 21 is a cross-sectional view in which a resist layer RES for patterning the data storage layer 110 is formed.

[0163] FIG. 22 is a cross-sectional view of the data storage layer 110 patterned by etching using the resist layer RES.

[0164] As shown in FIGS. 18 and 22, the lower electrode LEL and the data storage layer 110 are formed by processing them with different resist patterns.

[0165] 23A and 23B are diagrams showing another example of the configuration of a Hall element memory, where Fig. 23A is a plan view of the Hall element memory cell and Fig. 23B is a cross-sectional view of the Hall element memory cell taken along the line AA' in Fig. 23A.

[0166] For the Hall element memory shown in FIGS. 23A and 23B, Mn ３ The shape of the Sn layer is the same as or approximately similar to the shape of the lower electrode. For example, the lower electrode LEL and the data storage layer 110 are formed by processing using the same resist pattern. In addition, the lower electrode and the multilayer wiring layer are connected by a buried contact. This structure is obtained by processing using two lithography processes.

[0167] The first step is to process the channel from the top contact metal to the tungsten (bottom electrode), and the second step is to process the Mn ３ This is patterning of a laminated structure of Sn layer and tungsten.

[0168] 24A and 24B are diagrams showing another example of the configuration of a Hall element memory, where Fig. 24A is a plan view of the Hall element memory cell and Fig. 24B is a cross-sectional view of the Hall element memory cell taken along the line AA' in Fig. 24A.

[0169] For the Hall element memory shown in FIGS. 24A and 24B, Mn ３ The shape of the Sn layer is the same as or substantially similar to the shape of the lower electrode. For example, the lower electrode LEL and the data storage layer 110 are formed by processing using the same resist pattern.

[0170] Furthermore, the lower electrode and the wiring layer are in direct contact, not through a contact. In other words, one side of the wiring (multi-layer wiring layer 120) located below the lower electrode 120 is in contact with one side of the lower electrode LEL. This structure can be obtained by processing with one lithography. This processing is performed using Mn ３ The laminated structure of the Sn layer and the lower electrode layer (tungsten layer) is simply patterned.

[0171] Therefore, the Hall element memory cell can be formed by a simpler process.

[0172] Finally, while various embodiments of the present disclosure have been described, they are presented by way of example and are not intended to limit the scope of the invention. The novel embodiments may be embodied in various other forms, and various omissions, substitutions, and modifications may be made without departing from the spirit of the invention. Such embodiments and modifications are within the scope and spirit of the invention, and are also within the scope of the inventions and their equivalents as defined in the claims.

[0173] AMP amplifier, RL1, RL2 read wiring, WL1, WL2 write wiring, RE read enable wiring, WE write enable wiring, TR1, TR2, TR3, TR4 switch element, LEL lower electrode, 10 memory cell array, 100 memory cell, 110 data storage layer, T1 first node, T2 second node, T3 third node, T4 fourth node, 190 data write circuit, 191, 192 current supply circuit, 1000 semiconductor memory device, 1002 read circuit, 1003 write circuit, 1010 write row decoder, 1020 read row decoder, 1030 write column decoder, 1040 read column decoder.

Claims

1. A semiconductor memory device comprising a plurality of memory cells, each of the memory cells comprising: an electrode extending in a first direction and a second direction; and a memory layer provided at a portion of the electrode where the first direction and the second direction intersect, the memory layer including a non-collinear antiferromagnetic material, wherein the electrode has: a first node and a second node provided at both ends of the electrode in the first direction, respectively, for supplying a write current and a read current to the electrode for writing data to the memory layer; and a third node and a fourth node provided at both ends of the electrode in the second direction, respectively, for detecting a Hall voltage generated in the memory layer when the read current is flowing, wherein the read current is smaller than the write current.

2. The semiconductor memory device according to claim 1, further comprising: a first write wiring; and a second write wiring; and each of the memory cells further comprising: a first switch element provided between the first write wiring and the first node for selectively conducting the write current and the read current; and a second switch element provided between the second write wiring and the second node for selectively conducting the write current and the read current; and a data write circuit for writing data of different values ​​into the memory layer by changing the direction of the write current flowing between the first node and the second node.

3. The semiconductor memory device further comprises a first read wiring and a second read wiring, and each of the memory cells further comprises: a third switch element provided between the first read wiring and the third node, and selectively brought into a conductive state when the read current is conducted; and a fourth switch element provided between the second read wiring and the fourth node, and selectively brought into a conductive state when the read current is conducted; the semiconductor memory device further comprises: a current supply circuit for supplying a current between the first node and the second node; and a potential difference detection circuit for detecting a potential difference between the third node and the fourth node; and when performing a read operation of data written in the memory layer, the current supply circuit supplies the read current between the first node and the second node, 3. The semiconductor memory device according to claim 2, further comprising a read circuit that reads data written to said memory layer by detecting a potential difference between said third node and said fourth node with said potential difference detection circuit when said read current is flowing.

4. The semiconductor memory device according to claim 3, wherein said potential difference detection circuit includes a multi-stage potential difference amplifier circuit.

5. The semiconductor memory device according to any one of claims 1 to 4, wherein the plurality of memory cells are arranged in a matrix.

6. The semiconductor memory device according to claim 1, wherein the plurality of memory cells are arranged in a matrix, the semiconductor memory device further comprises: a first write wiring; and a second write wiring commonly connected to the second node of the plurality of memory cells arranged in the column direction, each of the memory cells further comprising: a first switch element provided between the first write wiring and the first node for selectively conducting the write current and the read current, and a current supply circuit for writing data of different values ​​into the memory layer by changing the direction of the write current flowing between the first node and the second node.

7. The semiconductor memory device according to claim 6, further comprising: a first read wiring and a second read wiring commonly connected to the third node of a plurality of the memory cells arranged in the row direction; each of the memory cells further comprising: a fourth switch element provided between the first read wiring and the fourth node and selectively brought into a conductive state when the read current is conducted; the semiconductor memory device further comprising: a potential difference detection circuit that detects a potential difference between the third node and the fourth node; the current supply circuit, when performing a read operation of data written in the memory layer, supplies the read current between the first node and the second node; and a read circuit that reads the data written in the memory layer by the potential difference detection circuit detecting the potential difference between the third node and the fourth node when the read current is flowing.

8. The semiconductor memory device according to claim 1, further comprising: a current supply circuit for supplying a current between the first node and the second node; and a potential difference detection circuit for detecting a potential difference between the third node and the fourth node; wherein, when performing a read operation of data written in the memory layer, the current supply circuit supplies the read current between the first node and the second node; and wherein, when the read current is flowing, the potential difference detection circuit detects the potential difference between the third node and the fourth node, thereby reading the data written in the memory layer; wherein the plurality of memory cells are arranged in a matrix, and the electrodes of the memory cells adjacent in the row direction are integrally formed.

9. The semiconductor memory device according to claim 8, wherein said potential difference detection circuit includes an integration circuit that integrates the detected potential difference.

10. The semiconductor memory device according to claim 8, wherein the potential difference detection circuit includes a plurality of sample and hold circuits that hold data read out for each column, each of the plurality of sample and hold circuits holding a potential when the stored data is read out and a reference potential that is read out after writing complementary data during a period when a column is selected and the data is read out, and an amplifier circuit that amplifies the stored data by comparing the potential when the stored data is read out with the reference potential based on the data held in the plurality of sample and hold circuits.

11. The semiconductor memory device according to claim 8, further comprising shunt wiring for shunting between said memory cells with respect to said electrodes of said memory cells adjacent in the row direction.

12. A method for manufacturing a semiconductor memory device, the semiconductor memory device comprising: a plurality of memory cells, each of the memory cells comprising: an electrode extending in a first direction and a second direction; and a memory layer provided at a portion of the electrode where the first direction and the second direction intersect, the memory layer including a non-collinear antiferromagnetic material; the electrode having: a first node and a second node provided at both ends of the electrode in the first direction, respectively, for supplying a write current and a read current to the electrode for writing data to the memory layer; and a third node and a fourth node provided at both ends of the electrode in the second direction, respectively, for detecting a Hall voltage generated in the memory layer when the read current is flowing; and a pre-processing step of forming a circuit on a semiconductor substrate, the pre-processing step comprising: a step of forming, on the semiconductor substrate, a write switching element for opening and closing a conduction path of a write current to the memory layer, a read switching element for opening and closing a read path of a read voltage from the memory layer, as well as a write wiring for supplying the write current and a read wiring that serves as the read path of the read voltage; and a step of forming a planarized insulating film layer on the write switching element, the read switching element, the write wiring, and the read wiring, wherein the method further comprises a post-processing step of forming the memory layer after the pre-processing step, the post-processing step including: forming electrodes on the uppermost insulating film layer, the electrodes extending in a first direction and a second direction; and forming the memory layer, the electrodes being provided in portions of the electrodes, and including a non-collinear antiferromagnetic material.

13. The method for manufacturing a semiconductor memory device according to claim 12, wherein the electrode and the memory layer are formed by processing them with different resist patterns.

14. The method for manufacturing a semiconductor memory device according to claim 12, wherein the electrode and the memory layer are formed by processing using the same resist pattern.

15. The method for manufacturing a semiconductor memory device according to claim 12, wherein one surface of the wiring located below the electrode is in contact with one surface of the electrode.

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