Apparatus and method for supporting movement of image data in display

Abstract

Disclosed are an apparatus and a method for supporting movement of image data in a display. A display device may comprise: a controller for controlling data writing, light-emitting element driving, and data movement; and a plurality of pixels including a pixel-embedded memory for storing image data represented by a multi-bit value. Each of the plurality of pixels can store image data in the pixel-embedded memory in a data write time period, and shift the image data stored in the pixel-embedded memory to one adjacent pixel among upper, lower, left, and right pixels on the basis of a control signal inputted from the controller in a data movement time period.

Description

Device and method for supporting movement of image data within a display

[0001] The technical field relates to digital display systems, and to devices and methods that support the movement of image data within a display.

[0002] A display device may include a plurality of display pixels. The display pixels may be arranged in MxN rows and columns. Each display pixel may include one or more light-emitting elements, and may typically be composed of three light-emitting elements (R, G, B). Here, the three light-emitting elements may be referred to as sub-pixels.

[0003] Display devices can be applied to a wide range of applications, from small mobile devices to large outdoor displays. In particular, displays are increasingly being utilized in diverse fields, including various vehicle devices, augmented reality (AR), and virtual reality (VR) devices.

[0004] Therefore, improvements in various characteristics such as various areas, various shapes, high resolution, process time, manufacturing cost, high reliability, and fast response speed are still required.

[0005] Additionally, drive circuit control may be required considering the power consumption of the display device, and a method for supporting the movement of image data within the display may be required depending on the application being displayed.

[0006] The technical problem of the present invention is to provide a digital display system capable of supporting movement of image data within a display through embodiments.

[0007] A display device according to one embodiment includes a plurality of pixels having a controller for controlling data writing, light-emitting element driving, and data movement, and a pixel built-in memory for storing image data expressed as a multi-bit value, wherein each of the plurality of pixels stores image data in the pixel built-in memory during a data writing time period, and shifts the image data stored in the pixel built-in memory to one of the adjacent pixels up, down, left, and right based on a control signal input from the controller during a data movement time period.

[0008] It may include a first dummy shift register for retrieving 1-bit data stored in the built-in memory of an adjacent pixel, n-bit shift registers for storing n-bit image data, and a second dummy shift register for retrieving 1-bit data stored in the n-bit shift registers.

[0009] The first dummy shift register operates to retrieve 1-bit data stored in the built-in memory of an adjacent pixel at the first clock of the data movement time interval, the second dummy shift register operates to retrieve 1-bit data stored in the n-bit shift registers at the second clock of the data movement time interval, and each of the n-bit shift registers can shift 1-bit data from the third clock of the data movement time interval.

[0010] The first dummy shift register and the second dummy shift register may include a reset switch for resetting the register after shifting of image data.

[0011] At this time, image data shift between left and right adjacent pixels connected to the same column line can be performed during n+1 line times.

[0012] At this time, the image data shift between the upper and lower adjacent pixels includes an image data shift from a first pixel of a first column line to a second pixel of a second column line, and the first pixel can perform a shift by 1 bit in the order of a first dummy shift register, a second dummy shift register, and n-bits shift registers of the first pixel in a clock cycle of the first column line, and the second pixel can perform a shift by 1 bit in the order of a first dummy shift register, a second dummy shift register, and n-bits shift registers of the second pixel in a clock cycle of the second line delayed by 1 line time from the clock cycle of the first column line.

[0013] A method for supporting data movement of a display device according to one embodiment includes the steps of storing image data expressed as a multi-bit value in a pixel built-in memory of each of a plurality of pixels during a data writing time period, receiving a control signal for controlling data movement during a data movement time period, and shifting the image data stored in the pixel built-in memory to one of the adjacent pixels above, below, left, and right based on the control signal.

[0014] A pixel of a display device according to one embodiment of the present invention includes a light-emitting element and a pixel circuit connected to the light-emitting element, and the pixel circuit includes a path control unit that selects a connection path with an adjacent pixel based on a control signal input from a controller, and a pixel built-in memory that stores image data expressed as a multi-bit value in a data writing time section and shifts the image data through the connection path with the adjacent pixel in a data moving time section.

[0015] The above path control unit may include a first path control unit that selects a receiving path for image data based on the type of the control signal, and a second path control unit that selects an output path for image data based on the type of the control signal.

[0016] The types of the above control signals may include an up_control (M_UP) that executes image data movement to an upper adjacent pixel, a down_control (M_DN) that executes image data movement to a lower adjacent pixel, a left_control (M_LE) that executes image data movement to a left adjacent pixel, and a right_control (M_RI) that executes image data movement to a right adjacent pixel.

[0017] The first path control unit may select a connection path with a lower adjacent pixel for receiving data when receiving the up control (M_UP), select a connection path with an upper adjacent pixel when receiving the down control (M_DN), select a connection path with a right adjacent pixel when receiving the left control (M_LE), and select a connection path with a left adjacent pixel when receiving the right control (M_RI).

[0018] The second path section may select a connection path with an upper adjacent pixel for shifting data when receiving the up control (M_UP), select a connection path with a lower adjacent pixel when receiving the down control (M_DN), select a connection path with a left adjacent pixel when receiving the left control (M_LE), and select a connection path with a right adjacent pixel when receiving the right control (M_RI).

[0019] A display device according to another embodiment of the present invention includes a plurality of pixels having a controller for controlling data writing, driving of light-emitting elements and data movement, and a pixel built-in memory for storing image data expressed as a multi-bit value, and at least one of the plurality of pixels includes a plurality of output pins (Pins) for outputting image data stored in the pixel built-in memory to an adjacent pixel based on a control signal input from the controller during a data movement time period, and a plurality of input pins for receiving image data from an adjacent pixel.

[0020] The above plurality of output pins may include an up output pin (DO_U) for outputting image data to an upper adjacent pixel, a down output pin (DO_D) for outputting image data to a lower adjacent pixel, a left output pin (DO_L) for outputting image data to a left adjacent pixel, and a right output pin (DO_R) for outputting image data to a right adjacent pixel.

[0021] The above plurality of input pins may include a down input pin (DI_D) that receives image data from an upper adjacent pixel, an up input pin (DI_U) that receives image data from a lower adjacent pixel, a right input pin (DI_R) that receives image data from a left adjacent pixel, and a left input pin (DI_L) that receives image data from a right adjacent pixel.

[0022] A display device according to another embodiment of the present invention includes a controller for controlling data writing, light-emitting element driving, and data movement, and a first pixel and a second pixel, wherein the first pixel and the second pixel include a pixel built-in memory for storing image data expressed as a multi-bit value, and the pixel built-in memory includes a first dummy shift register for retrieving 1-bit data stored in the built-in memory of an adjacent pixel, n-bit shift registers for storing n-bit image data, and a second dummy shift register for retrieving 1-bit data stored in the n-bit shift registers in the data movement time section.

[0023] If the first pixel and the second pixel are pixels connected to the same column line, image data shift between the left and right adjacent pixels can be performed during n+1 line times.

[0024] When the first pixel is a pixel connected to a first column line, the second pixel is a pixel connected to a second column line, and image data is shifted from the first pixel to the second pixel, the first pixel may shift by 1 bit in the order of a first dummy shift register, a second dummy shift register, and n-bits shift registers of the first pixel in a clock cycle of the first column line, and the second pixel may shift by 1 bit in the order of a first dummy shift register, a second dummy shift register, and n-bits shift registers of the second pixel in a clock cycle of a second line that is delayed by 1 line time from the clock cycle of the first column line.

[0025] Embodiments of the present invention can support movement of image data within a display without power consumption or time loss.

[0026] In addition, by supporting movement of image data within a display through embodiments of the present invention, the usability of applications to which the display device is applied can be increased.

[0027] FIG. 1 illustrates a configuration of a display device including pixels according to one embodiment of the present invention.

[0028] Figure 2 is a drawing for explaining an example of movement of an image displayed within a display.

[0029] FIG. 3 is a drawing for explaining a display driving method for moving image data according to an embodiment of the present invention.

[0030] FIG. 4 is a drawing for explaining pixels and pixel arrays of a display device according to one embodiment of the present invention.

[0031] FIG. 5 is a drawing for explaining a schematic configuration of a pixel circuit provided in each of the plurality of pixels illustrated in FIG. 4.

[0032] FIG. 6 is a drawing for explaining the specific configuration of a pixel circuit provided in each of the plurality of pixels illustrated in FIG. 4.

[0033] Fig. 7 is a drawing for explaining a clock connected to the pixel built-in memory shown in Fig. 6.

[0034] FIG. 8 is a drawing for explaining the configuration and operation of the shift register shown in FIGS. 6 and 7.

[0035] FIG. 9 is a drawing showing an example of the configuration of the pixel built-in memory shown in FIGS. 6 and 7.

[0036] FIGS. 10 to 12 are drawings for explaining the operation timing of a display device according to an embodiment of the present invention.

[0037] FIG. 13 and FIG. 14 are drawings for explaining the operation timing for image movement according to an embodiment of the present invention.

[0038] FIG. 15 is a drawing showing examples of specific clocks of CYCLE1 and CYCLE 2 shown in FIG. 13.

[0039] Fig. 16 shows an example of a pixel array of a display device according to an embodiment of the present invention.

[0040] FIG. 17 and FIG. 18 are drawings for explaining an example in which image data moves to the right pixel in the pixel array shown in FIG. 16.

[0041] Figures 19 to 21 are drawings for explaining an example in which image data moves to the lower pixel in the pixel array shown in Figure 16.

[0042] Figures 22 to 24 are drawings for explaining an example in which image data moves to the upper pixel in the pixel array shown in Figure 16.

[0043] Structural or functional descriptions are merely illustrative for the purpose of explaining embodiments according to the concept of the present invention, and embodiments according to the concept of the present invention may be implemented in various forms and are not limited to the embodiments described herein.

[0044] Embodiments according to the concept of the present invention may have various modifications and take various forms, and thus, embodiments are illustrated in the drawings and described in detail in this specification. However, this is not intended to limit embodiments according to the concept of the present invention to specific disclosed forms, but rather includes modifications, equivalents, or alternatives that fall within the spirit and technical scope of the present invention.

[0045] While terms such as "first" or "second" may be used to describe various components, these components should not be limited by these terms. These terms are intended solely to distinguish one component from another. For example, a first component may be referred to as a "second component," and similarly, a second component may also be referred to as a "first component," without departing from the scope of the invention.

[0046] When a component is referred to as being "connected" or "connected" to another component, it should be understood that it may be directly connected or connected to that other component, but that there may be other components in between. Conversely, when a component is referred to as being "directly connected" or "directly connected" to another component, it should be understood that there are no other components in between. Expressions that describe relationships between components, such as "between," "immediately between," or "directly adjacent to," should be interpreted similarly.

[0047] The terminology used herein is for the purpose of describing specific embodiments only and is not intended to limit the present invention. The singular expressions include plural expressions unless the context clearly indicates otherwise. In this specification, it should be understood that the terms "comprises" or "has" are intended to specify the presence of a described feature, number, step, operation, component, part, or combination thereof, but do not preclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0048] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and will not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0049]

[0050] Hereinafter, embodiments will be described in detail with reference to the attached drawings. However, the scope of the patent application is not limited or restricted by these embodiments. The same reference numerals provided in each drawing represent the same components.

[0051]

[0052] FIG. 1 illustrates a configuration of a display device including pixels according to one embodiment of the present invention.

[0053] Referring to FIG. 1, a display device (100) may include a display panel (110), a scan driving circuit (120), a data driving circuit (130), and a control unit (140). In this specification, the 'scan driving circuit (120)' may be referred to as a row driving circuit, and the data driving circuit (130) may be referred to as a column driving circuit.

[0054] The display panel (110) may include a plurality of pixels (PX). In one embodiment, the plurality of pixels (PX) may be configured by arranging M * N (M and N are natural numbers) pixels in the form of a matrix, but the manner in which the plurality of pixels (PX) are arranged may be arranged in various patterns, such as a zigzag shape, according to other embodiments.

[0055] Each of the plurality of pixels (PX) may include one or more light-emitting elements (lighting elements or luminous elements). In one embodiment, the light-emitting elements may be light-emitting diodes (LEDs). The light-emitting diodes may be micro LEDs having a size of 80 μm or less.

[0056] Each pixel (PX) may include a pixel driving circuit that drives a light-emitting element included in the pixel, i.e., a sub-pixel.

[0057] The display panel (110) may include one or more scan lines (SL1 to SLm) arranged in a row direction and one or more data lines (DL1 to DLn) arranged in a column direction. Each pixel (PX) may be connected to one scan line (SLk) and one data line (DLk). One or more scan lines (SL1 to SLm) may be connected to a scan driving circuit (120), and one or more data lines (DL1 to DLn) may be connected to a data driving circuit (130).

[0058] The scan driving circuit (120) can output a signal (hereinafter, a low signal) that causes one or more pixels connected to one or more scan lines (SL1 to SLm) to be driven.

[0059] The data driving circuit (130) can output a signal related to gradation (hereinafter, column signal) to each pixel through one or more data lines (DL1 to DLn). That is, the column signal can correspond to a bit value of image data.

[0060]

[0061] Figure 2 is a drawing for explaining an example of movement of an image displayed within a display.

[0062] Referring to FIG. 2, the application can operate in a first state (210) in which an object image (201) is displayed in the central portion of the display (200).

[0063] If a user is in close proximity to the display (200), the user may perceive the object image (201) in a distorted form depending on the movement of the eye's focus. To reduce the phenomenon of perceiving the object image (201) in a distorted form, the position of the object image (201) may need to be changed according to the eye's focus. In other words, to reduce the distortion of image recognition, the display device may need to move the image within the display.

[0064] Here, the movement of the image may include at least one of a second state (220) that moves the object image (201) upward, a third state (230) that moves the object image (201) downward, a fourth state (240) that moves the object image (201) to the right, and a fifth state (250) that moves the object image (201) to the left.

[0065] Image movement according to conventional techniques may require continuous updating of image data stored in a pixel array for image movement. For example, to change from a first state (210) to a second state (220), the image data of all pixels must be updated per unit time. Therefore, image movement according to conventional techniques may increase power consumption and data movement. Furthermore, image movement according to conventional techniques may have the problem of requiring that a specific operation be repeated within a short period of time.

[0066] In embodiments of the present invention, the movement of an image can be expressed as the movement of image data from a display driving perspective. A display device according to an embodiment of the present invention may include a pixel-embedded memory for each pixel. A display device according to an embodiment of the present invention may move image data stored in the pixel-embedded memory to an adjacent pixel. Accordingly, a display device according to an embodiment of the present invention may move image data to any one of the adjacent pixels above, below, left, and right within the display.

[0067]

[0068] FIG. 3 is a drawing for explaining a display driving method for moving image data according to an embodiment of the present invention.

[0069] Reference numeral 310 of FIG. 3 represents an example in which the movement of image data is performed in accordance with the driving order of the column lines, and reference numeral 330 of FIG. 3 represents an example in which the movement of image data is performed at once regardless of the driving order of the column lines.

[0070] The method illustrated in reference numeral 310 may be configured in the following order: an image data writing or image data storage time section (311), a light-emitting element driving time section (313), a data movement time section (315), a light-emitting element driving time section (317), a data movement time section (319), and a light-emitting element driving time section (321).

[0071] Here, data movement between adjacent pixels in the data movement time interval (315) can be sequentially performed for each column line. Therefore, the method illustrated by reference numeral 310 can reduce loss and power consumption in the display ON interval compared to the method illustrated by reference numeral 330.

[0072] The method illustrated by reference numeral 330 is a method in which data movement is performed simultaneously on all column lines rather than sequentially on each column line during the data movement time intervals (340, 350). In this case, loss intervals (331, 333, 337, 339) due to display on may occur. Therefore, the method illustrated by reference numeral 330 may result in increased power consumption compared to the method illustrated by reference numeral 310.

[0073]

[0074] FIG. 4 is a drawing for explaining pixels and pixel arrays of a display device according to one embodiment of the present invention.

[0075] Referring to FIG. 4, the display device (400) includes a controller (not shown) and pixels (410).

[0076] At this time, the controller may be provided in any one of the display panel (110), scan driving circuit (120), data driving circuit (130), and control unit (140) illustrated in Fig. 1. The controller may control data writing, light-emitting element driving, and data movement.

[0077] For example, a particular region (410) of the pixel array may include a plurality of pixels (411, 413, 417, 415, 417, 419).

[0078] Each of the plurality of pixels (411, 413, 417, 415, 417, 419) may have an embedded pixel memory that stores image data expressed as a multi-bit value.

[0079] At this time, the image data may be n-bit image data applied through a column line during the data write time period. In addition, the image data may be expressed as a multi-bit value composed of the MSB (Most Significant Bit) and the LSB (Least Significant Bit).

[0080] The pixel memory can store at least 1 bit of data. The pixel memory can be implemented with a memory having less than n bits, depending on the driving frequency. The pixel memory can include a shift register. The pixel memory can be implemented with one or more transistors. The pixel memory can be implemented with random access memory (RAM), such as SRAM or DRAM.

[0081] The pixel (411) may include a plurality of output pins (Pins) for outputting image data stored in the pixel built-in memory to adjacent pixels based on a control signal input from the controller during a data movement time period, and a plurality of input pins for receiving image data from adjacent pixels.

[0082] Below, multiple output pins and multiple input pins are described using pixel (411) as an example.

[0083] The plurality of output pins may include an up output pin (DO_U) that outputs image data to an upper adjacent pixel (413), a down output pin (DO_D) that outputs image data to a lower adjacent pixel (415), a left output pin (DO_L) that outputs image data to a left adjacent pixel (417), and a right output pin (DO_R) that outputs image data to a right adjacent pixel (419).

[0084] The multiple input pins may include a down input pin (DI_D) that receives image data from an upper adjacent pixel (413), an up input pin (DI_U) that receives image data from a lower adjacent pixel (), a right input pin (DI_R) that receives image data from a left adjacent pixel, and a left input pin (DI_L) that receives image data from a right adjacent pixel.

[0085] The up output pin (DO_U) of the pixel (411) can be connected to the up input pin (DI_U) of the upper adjacent pixel (413). The down input pin (DI_D) of the pixel (411) can be connected to the down output pin (DO_D) of the upper adjacent pixel (413).

[0086] In this way, a pixel according to an embodiment of the present invention may include interfaces for exchanging image data with adjacent pixels.

[0087] Each of the plurality of pixels (411, 413, 417, 415, 417, 419) can store image data in the pixel built-in memory during the data writing time period, and shift the image data stored in the pixel built-in memory to one of the adjacent pixels up, down, left, or right based on a control signal input from the controller during the data movement time period.

[0088] In other words, each of the plurality of pixels (411, 413, 417, 415, 417, 419) stores image data expressed as a multi-bit value in the pixel built-in memory of each of the plurality of pixels during the data writing time period, receives a control signal for controlling data movement during the data movement time period, and can shift the image data stored in the pixel built-in memory to one of the adjacent pixels above, below, left, and right based on the control signal.

[0089]

[0090] FIG. 5 is a drawing for explaining a schematic configuration of a pixel circuit provided in each of the plurality of pixels illustrated in FIG. 4.

[0091] The pixel circuit (500) can be connected to a light emitting element.

[0092] Referring to FIG. 5, the pixel circuit (500) includes a path control unit (510) and a pixel built-in memory (520). The pixel circuit (500) may further include a pixel driver unit (530) for driving a light-emitting element.

[0093] The path control unit (510) selects a connection path with adjacent pixels based on a control signal input from the controller.

[0094] The path control unit (510) may include a first path control unit that selects a receiving path for image data based on the type of the control signal and a second path control unit that selects an output path for image data based on the type of the control signal.

[0095] The pixel built-in memory (520) stores image data expressed as a multi-bit value in the data writing time section, and shifts the image data through a connection path with the adjacent pixels in the data movement time section.

[0096]

[0097] FIG. 6 is a drawing for explaining the specific configuration of a pixel circuit provided in each of the plurality of pixels illustrated in FIG. 4.

[0098] Referring to FIG. 6, the pixel circuit (600) includes a first path control unit (610), a pixel built-in memory (620), and a second path control unit (630). The pixel circuit (600) may further include a pixel driver unit (640) for driving a light-emitting element.

[0099] The first path control unit (610) selects a receiving path for image data based on the type of control signal. The second path control unit (630) selects an output path for image data based on the type of control signal.

[0100] The types of control signals for controlling image data movement may include an up_control (M_UP) that executes image data movement to an upper adjacent pixel, a down_control (M_DN) that executes image data movement to a lower adjacent pixel, a left_control (M_LE) that executes image data movement to a left adjacent pixel, and a right_control (M_RI) that executes image data movement to a right adjacent pixel.

[0101] In the control signal (Control) illustrated in Fig. 6, M_DW is a command for writing data to the pixel built-in memory during the data write time period. Therefore, when the first path control unit (610) receives M_DW, it can select a path for receiving data through the data line.

[0102] In the control signal (Control) illustrated in Fig. 6, M_PWM represents a command for driving the light-emitting element during the light-emitting element driving time period.

[0103] When the first path control unit (610) receives an up control (M_UP), it can select the DI_U pin, which is a connection path with a lower adjacent pixel for receiving data. At this time, the up control (M_UP) can be input to the first path control unit (610) and the second path control unit (630) simultaneously. When the second path control unit (630) receives an up control (M_UP), it can select the DO_U pin, which is a connection path with an upper adjacent pixel.

[0104] When the first path control unit (610) receives a down_control (M_DN), it can select the DI_D pin, which is a connection path with an upper adjacent pixel for receiving data. At this time, the down_control (M_DN) can be input to the first path control unit (610) and the second path control unit (630) simultaneously. When the second path control unit (630) receives the down_control (M_DN), it can select the DO_D pin, which is a connection path with a lower adjacent pixel.

[0105] When the first path control unit (610) receives the left control (M_LE), it can select the DI_L pin, which is a connection path with the right adjacent pixel for receiving data. At this time, the left control (M_LE) can be input to the first path control unit (610) and the second path control unit (630) simultaneously. When the second path control unit (630) receives the left control (M_LE), it can select the DO_L pin, which is a connection path with the left adjacent pixel.

[0106] When the first path control unit (610) receives the light control (M_RI), it can select the DI_R pin, which is a connection path with the left adjacent pixel for receiving data. At this time, the light control (M_RI) can be input to the first path control unit (610) and the second path control unit (630) simultaneously. When the second path control unit (630) receives the light control (M_RI), it can select the DO_R pin, which is a connection path with the right adjacent pixel.

[0107] The pixel built-in memory (620) may include a first dummy shift register D1, n-bit shift registers M1, M2,,,M(n) and a second dummy shift register D2.

[0108] D1 is a shift register for retrieving 1-bit data stored in the built-in memory of adjacent pixels. M1, M2,,,M(n) are shift registers that store n-bits of image data, respectively. D2 is a shift register for retrieving 1-bit data stored in n-bit shift registers, and is specifically a shift register for retrieving 1-bit data stored in M(n).

[0109]

[0110] Fig. 7 is a drawing for explaining a clock connected to the pixel built-in memory shown in Fig. 6.

[0111] Referring to FIG. 7, shift registers D1, M1, M2,,,M(n-1), M(n) and D2 can operate by receiving clocks CK_D1, CK_M1, CK_M2, CK_M(n-1), CK_M(n), CK_D2, respectively.

[0112] The specific timing reference diagrams of the clocks CK_D1, CK_M1, CK_M2, CK_M(n-1), CK_M(n), and CK_D2 for operating the shift registers will be explained through FIGS. 10 to 15.

[0113]

[0114] FIG. 8 is a drawing for explaining the configuration and operation of the shift register shown in FIGS. 6 and 7.

[0115] Referring to FIG. 8, the shift register (810) may be a memory having a latch structure to minimize the pixel size. The memory having a latch structure may include a memory structure for data storage and a switch (811) for reset.

[0116] Meanwhile, in FIGS. 6 and 7, D1, M1, M2,,,M(n) may have different structures. For example, D1 may include a switch (811) for reset as shown in FIG. 8, and M1, M2,,,M(n) may have a structure that does not include a switch (811) for reset.

[0117] Referring to exemplary timing (820) for the operation of the shift register (810), the shift register (810) can perform a data shift in a section (821) in which the clock CLK_D1 is activated, and the shift register (810) can perform a reset to erase the remaining data in a section (823) in which the clock CLK_RST is activated.

[0118]

[0119] FIG. 9 is a drawing showing an example of the configuration of the pixel built-in memory shown in FIGS. 6 and 7.

[0120] Referring to FIG. 9, D1 and D2 may have the same structure as the structure illustrated in FIG. 8.

[0121] More specifically, D1 may include a reset switch (911) for resetting the register after movement of image data. D2 may include a reset switch (941) for resetting the register after movement of image data.

[0122] Here, the reset switch (911) can operate to reset data after the writing operation of image data in the data writing section is completed.

[0123] M1, M2,,,M(n) may simply be a latch-structured memory for storing data. In other words, unlike D1 or D2, M1, M2,,,M(n) may have a structure that does not include a reset switch.

[0124]

[0125] FIGS. 10 to 12 are drawings for explaining the operation timing of a display device according to an embodiment of the present invention.

[0126] The pixel circuit structure of Fig. 6 may be referred to for a description of the timing operation.

[0127] Referring to Fig. 10, 'PIXEL DATA WRITE MODE' indicates a data writing time interval, and 'PIXEL DRIVING MODE' indicates a light-emitting element driving time interval. The data writing time interval may be, for example, the image data storage time interval (311) of Fig. 3.

[0128] The data write time interval may include n clock cycles (Cycle1, Cycle2, Cycle3,,,Cycle(n-1), Cycle(n)) to sequentially write n-bits of data data1, data2, data 3,,,data(n-1), data(n) to the pixel built-in memory.

[0129] In the activation section of the control signal M-DW, the CKD1 clock for the operation of the first dummy shift register D1 can be activated first. Afterwards, the CKn, CKn-1, CK3, CK2, CK1 clocks for the operation of M(n), M(n-1),,,M3),,, M3, M2, M1 in the order of proximity to the output terminal are activated.

[0130] Since the second dummy shift register D2 does not operate during the data write time interval, CKD2 may not be activated.

[0131] At the timing when data writing is completed, RST_D1 is activated and the reset switch of D1 can be operated.

[0132] The clock M_PWM for driving the light-emitting element can be activated at the timing when PIXEL DATA WRITE MODE ends.

[0133] The driving time section of the light-emitting element may be, for example, the light-emitting element driving time section (313) of FIG. 3.

[0134] Referring to Fig. 11, the driving of the light-emitting element may include a section (1101) for driving data 1, a section (1103) for driving data 2, a section (1105) for driving data 3, and a section (1107) for driving data (n). Here, data 1 may be MSB and data (n) may be LSB.

[0135] Referring to FIG. 12, 'PIXEL DATA SHIFT MODE' indicates a data movement time interval. The data movement time interval may be, for example, the data movement time interval (315) illustrated in FIG. 3.

[0136] A data movement time interval may include n clock cycles (Cycle1, Cycle2, Cycle3,,,Cycle(n-1), Cycle(n)) and a hold interval (1201). The number of clock cycles required may vary depending on the movement direction of the image data, and the hold interval (1201) may be required to execute data movement for each column line.

[0137] In Fig. 12, M_UP, DN, LE, and RI represent the types of control signals described through Fig. 6, and are signals for controlling the movement direction of image data.

[0138] When the CKD 1 clock is activated, the first dummy shift register performs an operation to retrieve 1-bit data stored in the built-in memory of the adjacent pixel. In other words, it can be expressed as 'the first dummy shift register operates to retrieve 1-bit data stored in the built-in memory of the adjacent pixel at the first clock of the data movement time interval.'

[0139] After the CKD 1 clock, the CKD 2 clock can be activated, and the second dummy shift register can perform an operation to retrieve the image data stored in M(n). In other words, it can be expressed as 'the second dummy shift register operates to retrieve 1-bit data stored in n-bit shift registers in the second clock of the data movement time section.'

[0140] After the CKD 2 clock, the clocks for the operation of each of the n-bit shift registers can be activated. The clock activation order follows the order of the CKn, CKn-1, CK3, CK2, and CK1 clocks. Therefore, it can be expressed that 'each of the n-bit shift registers shifts 1-bit data starting from the third clock of the data movement time interval.'

[0141] At the timing when data movement ends, RST_D1 and RST_D2 are activated, and the reset switches of D1 and D2 can operate.

[0142] After data transfer is complete, the clock M_PWM for driving the light-emitting element can be activated at the timing when PIXEL DATA SHIFT MODE ends.

[0143] The 'PIXEL DRIVING MODE' illustrated in Fig. 12 can be executed in the same manner as the 'PIXEL DRIVING MODE' illustrated in Fig. 10.

[0144]

[0145] FIG. 13 and FIG. 14 are drawings for explaining the operation timing for image movement according to an embodiment of the present invention.

[0146] Referring to Fig. 13, Shift 1 to Shift 8 represent the movement of continuous image data. Image shift, i.e., image data movement, can occur at each Frame Time. In Fig. 13, 'Display' after image shift represents the operating time section of the light source element.

[0147] Since image data movement can proceed on a column-line-by-column basis, the image data movement time interval (1310) from the perspective of the entire pixel array can include a delay of one line time '1H' per column line. Here, the line time represents a time interval of the same length as one clock cycle.

[0148] Figure 14 shows the specific clock cycles per column line and the Control PIN timing for controlling the pin connection of the pixels. In Figure 14, 'DISPLAY' indicates the driving of the light-emitting element after data transfer.

[0149] If the number of bits of image data is n, shifting of image data between left and right adjacent pixels connected to the same column line can be performed during (n+1)H, which is n+1 line times. For example, the number of clock cycles required to shift 3-bit image data to the left or right adjacent pixel may be 4.

[0150] Meanwhile, the up control (M_UP) that performs image data movement to the upper adjacent pixel and the down control (M_DN) that performs image data movement to the lower adjacent pixel may require different numbers of clock cycles than the left and right movements.

[0151] For example, when a first pixel is a pixel connected to a first column line (LINE1), a second pixel is a pixel connected to a second column line (LINE2), and image data is shifted from the first pixel to the second pixel, the first pixel can perform a shift by 1 bit in the order of the first dummy shift register, the second dummy shift register, and the n-bits shift registers of the first pixel in the clock cycle CYC1 to CYC(n) of LINE1.

[0152] At this time, the second pixel can perform a shift by 1 bit in the order of the first dummy shift register, the second dummy shift register, and the n-bits shift registers of the second pixel in the clock cycle CYC1 to CYC(n) of LINE2, which is delayed by 1 line time from the clock cycle of LINE1.

[0153]

[0154] FIG. 15 is a drawing showing examples of specific clocks of CYCLE1 and CYCLE 2 shown in FIG. 13.

[0155] Referring to FIG. 15, the activation order of the clock can be determined according to the operation order of each shift register of the pixel built-in memory.

[0156] Therefore, the CK_D1 clock can be activated first, and then the CK_D2 clock can be activated, and the second dummy shift register can perform an operation of retrieving the image data stored in M(n).

[0157] After the CK_D2 clock, clocks for the operation of each n-bit shift register can be activated. The clock activation order follows the order of CK_M(n), CK_M(n-1),,,CK_M2, CK_M1 clocks. Therefore, the pixel internal memory operates in the order of D1, D2, M(n) ~ M1.

[0158]

[0159] Fig. 16 shows an example of a pixel array of a display device according to an embodiment of the present invention.

[0160] Figure 16 shows an example of a 4x4 pixel array, which may be a portion of the entire pixel array. Line n, Line n+1, Line n+2, and Line n+3 represent column lines, respectively.

[0161] PIXEL 1, PIXEL 5, PIXEL 9 and PIXEL 13 are connected to column line Line n.

[0162] Pixels PIXEL 2, PIXEL 6, PIXEL 10 and PIXEL 14 located below Line n are connected to Line n+1.

[0163] Pixels PIXEL 3, PIXEL 7, PIXEL 11 and PIXEL 15 located below Line n+1 are connected to Line n+2.

[0164] Pixels PIXEL 4, PIXEL 8, PIXEL 12 and PIXEL 16 located below Line n+2 are connected to Line n+3.

[0165]

[0166] FIG. 17 and FIG. 18 are drawings for explaining an example in which image data moves to the right pixel in the pixel array shown in FIG. 16.

[0167] The examples shown in FIGS. 17 and 18 represent the movement of image data of PIXEL 1, PIXEL 5, PIXEL 9, and PIXEL 13 connected to Line n. Here, the image data is assumed to be 3 bits. However, in order to distinguish the data stored in each pixel in the data writing time section, the data stored in PIXEL 1 is expressed as '11', '12', and '13', the data stored in PIXEL 5 is expressed as '51', '52', and '53', the data stored in PIXEL 9 is expressed as '91', '92', and '93', and the data stored in PIXEL 13 is expressed as '131', '132', and '133'.

[0168] Figure 17 shows the operation of each pixel in the first clock cycle cycle1.

[0169] In the first clock cycle cycle1, D1 of each pixel operates first.

[0170] For example, D1 of PIXEL 5 retrieves data '0' stored in D2 of PIXEL 1, which is the left adjacent pixel. In other words, data '0' stored in D2 of PIXEL 1 is shifted to D1 of PIXEL 5.

[0171] D2 of each pixel retrieves the data stored in M3 of each pixel when CK_D2 is activated. For example, D2 of PIXEL 5 retrieves the data '53' stored in M3.

[0172] Figure 18 shows the entire data movement operation from cycle 1 to cycle 4.

[0173] When the data movement operation from cycle 1 to cycle 4 is completed, PIXEL 1 leaves '0' corresponding to dummy data in all shift registers.

[0174] '11', '12', '13' shifted to the right adjacent pixel in PIXEL 1 are stored in the pixel internal memory of PIXEL 5. '51', '52', '53' shifted to the right adjacent pixel in PIXEL 5 are stored in the pixel internal memory of PIXEL 9. '91', '52', '53' shifted to the right adjacent pixel in PIXEL 9 are stored in the pixel internal memory of PIXEL 13.

[0175] Referring to Figure 18, the pixels erase a kind of garbage data remaining in D1 and D2 by executing a reset at the reset timing.

[0176] For example, D1 of PIXEL 5 maintains the dummy data state '0' by deleting data '11' through reset. D1 of PIXEL 9 maintains the dummy data state '0' by deleting data '51' through reset. D1 of PIXEL 13 maintains the dummy data state '0' by deleting data '91' through reset.

[0177]

[0178] Figures 19 to 21 are drawings for explaining an example in which image data moves to the lower pixel in the pixel array shown in Figure 16.

[0179] The examples shown in Figures 19 to 21 illustrate a case where image data is shifted to PIXEL 1 connected to Line n, PIXEL 2 connected to Line n+1, PIXEL connected to Line n+2, and PIXEL 4 connected to Line n+3.

[0180] Figure 19 shows the pixel built-in memory operation of each pixel in cycle 1 of Line n.

[0181] The data image shift operation according to an embodiment of the present invention can be sequentially executed line by line with a time difference of one line time. Therefore, in cycle 1 of line n, pixels of other lines do not operate, and only the built-in memory of PIXEL 1 performs a shift operation.

[0182] Figure 20 shows image data movement executed over four clock cycles.

[0183] In Fig. 20, cycle2 corresponds to cycle 1 (pixel2 cycle1) delayed by 1H from the perspective of Line n+1. Therefore, the pixel internal memories of PIXEL 1 and PIXEL 2 each perform shift operations. For example, D1 of PIXEL 2 can retrieve data '13' stored in D2 of the upper adjacent pixel when the CK_D1 clock is activated.

[0184] In the fourth clock cycle, cycle 4, PIXEL 1 remains in a hold state in which there is no clock input and no shift operation is performed. At this time, PIXEL 2, PIXEL 3, and PIXEL 4 each perform a shift operation.

[0185] Figure 21 shows an operation executed after the operation illustrated in Figure 20.

[0186] In the fifth clock cycle, cycle 5, PIXEL 2 remains in a hold state in which there is no clock input and no shift operation is performed. At this time, PIXEL 3 and PIXEL 4 each perform a shift operation.

[0187] In the sixth clock cycle, cycle 6, PIXEL 2 can execute a reset operation to initialize D1 and D2. At this time, PIXEL 3 maintains the hold state, and PIXEL 4 executes a shift operation.

[0188] In cycle 7, PIXEL 3 executes a reset operation, and PIXEL 4 maintains the hold state. Then, in cycle 8, PIXEL 4 can execute a reset operation to initialize D1 and D2.

[0189] Referring to FIG. 21, image data '11', '12', '13' shifted from PIXEL 1 are stored in PIXEL 2, '21', '22', '23' are stored in PIXEL 3, and '31', '32', '33' are stored in PIXEL 4.

[0190]

[0191] Figures 22 to 24 are drawings for explaining an example in which image data moves to the upper pixel in the pixel array shown in Figure 16.

[0192] The examples shown in Figures 22 to 24 illustrate a case where image data is shifted to PIXEL 4 connected to Line n+3, PIXEL 3 connected to Line n+2, PIXEL 2 connected to Line n+1, and PIXEL 1 connected to Line n.

[0193] In other words, the examples shown in FIGS. 22 to 24 represent a case where an up_control (M_UP) is performed to move image data from PIXEL 4, PIXEL 3, PIXEL 2, and PIXEL 1 to the upper adjacent pixel.

[0194] Figure 22 shows the pixel built-in memory operation of each pixel in cycle 1 of Line n.

[0195] When the driving order for each line is maintained as shown in reference numeral 310 in FIG. 3, even in the case of up control (M_UP), the operation of the column line is performed from the top.

[0196] Therefore, in cycle 1, the pixels connected to Line n, D1, D2, M3, M2, and M1 of PIXEL 1 are operated in that order. At this time, pixels connected to lines other than Line n do not operate.

[0197] Figure 23 shows the image data movement that is executed over four clock cycles.

[0198] In Fig. 23, cycle2 corresponds to cycle 1 (pixel2 cycle1) delayed by 1H from the perspective of Line n+1. Therefore, the pixel internal memories of PIXEL 1 and PIXEL 2 each perform shift operations. For example, D1 of PIXEL 2 can retrieve data '0' stored in D2 of the lower adjacent pixel PIXEL 2 when the CK_D1 clock is activated.

[0199] Referring to FIG. 23, up_control (M_UP) can be performed sequentially line by line over four clock cycles.

[0200] Figure 24 shows an operation executed after the operation illustrated in Figure 23.

[0201] For example, in the fifth clock cycle, cycle 5, image data '21', '22', and '23' are stored in M1, M2, and M3 of PIXEL 1, respectively.

[0202] Afterwards, in cycle 6, D1 and D2 of PIXEL 1 perform a reset operation.

[0203] Afterwards, sequentially in cycle 7, D1 and D2 of PIXEL 2 perform a reset operation.

[0204] In cycle 8, D1 and D2 of PIXEL 3 perform a reset operation.

[0205] When the execution of up_control (M_UP) is completed, the shifted image data '21', '22', '23' from PIXEL 2 are stored in PIXEL 1, '31', '32', '33' are stored in PIXEL 2, and '41', '42', '43' are stored in PIXEL 3.

[0206]

[0207] The devices described above may be implemented as hardware components, software components, and / or a combination of hardware components and software components. For example, the devices and components described in the embodiments may be implemented using one or more general-purpose computers or special-purpose computers, such as, for example, a processor, a controller, an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable array (FPA), a programmable logic unit (PLU), a microprocessor, or any other device capable of executing instructions and responding to them. The processing device may execute an operating system (OS) and one or more software applications running on the operating system. The processing device may also access, store, manipulate, process, and generate data in response to the execution of the software. For ease of understanding, the processing device is sometimes described as being used alone; however, one of ordinary skill in the art will recognize that the processing device may include multiple processing elements and / or multiple types of processing elements. For example, a processing unit may include multiple processors, or a processor and a controller. Other processing configurations, such as parallel processors, are also possible.

[0208] Software may include a computer program, code, instructions, or a combination of one or more of these, which may configure a processing device to perform a desired operation or may, independently or collectively, command the processing device. The software and / or data may be permanently or temporarily embodied in any type of machine, component, physical device, virtual equipment, computer storage medium or device, or transmitted signal wave, for interpretation by the processing device or for providing instructions or data to the processing device. The software may also be distributed over networked computer systems and stored or executed in a distributed manner. The software and data may be stored on one or more computer-readable recording media.

[0209] The method according to the embodiment may be implemented in the form of program commands that can be executed through various computer means and recorded on a computer-readable medium. The computer-readable medium may include program commands, data files, data structures, etc., alone or in combination. The program commands recorded on the medium may be those specially designed and configured for the embodiment or may be those known and available to those skilled in the art of computer software. Examples of the computer-readable recording medium include magnetic media such as hard disks, floppy disks, and magnetic tapes, optical media such as CD-ROMs and DVDs, magneto-optical media such as floptical disks, and hardware devices specially configured to store and execute program commands, such as ROMs, RAMs, and flash memories. Examples of the program commands include not only machine language codes generated by a compiler, but also high-level language codes that can be executed by a computer using an interpreter, etc. The hardware devices described above may be configured to operate as one or more software modules to perform the operations of the embodiment, and vice versa.

[0210] Although the embodiments described above have been described with limited drawings, those skilled in the art will recognize that various modifications and variations can be made based on the above description. For example, appropriate results can still be achieved even if the described techniques are performed in a different order than described, and / or components of the described systems, structures, devices, circuits, etc. are combined or combined in a different manner than described, or are replaced or substituted with other components or equivalents.

[0211] Therefore, other implementations, other embodiments, and equivalents to the claims also fall within the scope of the claims described below.

Claims

1. A controller that controls data writing, light-emitting element operation, and data movement; and It comprises a plurality of pixels having a pixel memory that stores image data expressed as multi-bit values, Each of the plurality of pixels stores image data in the pixel built-in memory during the data writing time period, and shifts the image data stored in the pixel built-in memory to one of the adjacent pixels above, below, left, or right based on a control signal input from the controller during the data movement time period. Display device.

2. In paragraph 1, The above pixel built-in memory is A first dummy shift register for retrieving 1-bit data stored in the built-in memory of an adjacent pixel, n-bit shift registers for storing n-bit image data, and a second dummy shift register for retrieving 1-bit data stored in the n-bit shift registers. Display device.

3. In paragraph 2, The above first dummy shift register operates to retrieve 1-bit data stored in the built-in memory of an adjacent pixel at the first clock of the data movement time interval, The second dummy shift register operates to retrieve 1-bit data stored in the n-bit shift registers at the second clock of the data movement time interval, Each of the above n-bit shift registers shifts 1 bit of data from the third clock of the data movement time interval. Display device.

4. In paragraph 2, The first dummy shift register and the second dummy shift register include a reset switch for resetting the register after movement of image data. Display device.

5. In paragraph 2, Image data shift between left and right adjacent pixels connected to the same column line is performed during n+1 line times. Display device.

6. In paragraph 5, The image data shift between the upper and lower adjacent pixels includes the image data shift from the first pixel of the first column line to the second pixel of the second column line, The first pixel performs a shift by 1 bit in the order of the first dummy shift register, the second dummy shift register, and the n-bit shift registers of the first pixel in the clock cycle of the first column line, The second pixel performs a shift by 1 bit in the order of the first dummy shift register, the second dummy shift register, and the n-bits shift registers of the second pixel in the clock cycle of the second line delayed by 1 line time from the clock cycle of the first column line. Display device.

7. A step of storing image data expressed as a multi-bit value in the pixel built-in memory of each of a plurality of pixels during a data writing time interval; A step of receiving a control signal for controlling data movement during a data movement time interval; and Based on the control signal, the step of shifting the image data stored in the pixel built-in memory to one of the adjacent pixels above, below, left, and right A method for supporting data movement on a display device.

8. Light-emitting element; and Includes a pixel circuit connected to the above light emitting element. The above pixel circuit A path control unit that selects a connection path with adjacent pixels based on a control signal input from the controller; and A pixel embedded memory that stores image data expressed as a multi-bit value in a data writing time interval and shifts the image data through a connection path with the adjacent pixels in a data moving time interval. Pixels of a display device.

9. In paragraph 8, The above path control unit A first path control unit that selects a receiving path for image data based on the type of the control signal; and A second path control unit that selects an output path of image data based on the type of the control signal. Pixels of a display device.

10. In paragraph 9, The types of the above control signals include up_control (M_UP) that executes image data movement to the upper adjacent pixel, down_control (M_DN) that executes image data movement to the lower adjacent pixel, left_control (M_LE) that executes image data movement to the left adjacent pixel, and right_control (M_RI) that executes image data movement to the right adjacent pixel. Pixels of a display device.

11. In paragraph 10, The above first path control unit When the above up control (M_UP) is received, a connection path with a lower adjacent pixel for receiving data is selected, when the above down control (M_DN) is received, a connection path with an upper adjacent pixel is selected, when the above left control (M_LE) is received, a connection path with a right adjacent pixel is selected, and when the above right control (M_RI) is received, a connection path with a left adjacent pixel is selected. Pixels of a display device.

12. In paragraph 10, The above second path section When the above up_control (M_UP) is received, a connection path with an upper adjacent pixel for shifting data is selected, when the above down_control (M_DN) is received, a connection path with a lower adjacent pixel is selected, when the above left_control (M_LE) is received, a connection path with a left adjacent pixel is selected, and when the above right_control (M_RI) is received, a connection path with a right adjacent pixel is selected. Pixels of a display device.

13. In paragraph 8, The above pixel built-in memory is A first dummy shift register for retrieving 1-bit data stored in the built-in memory of an adjacent pixel, n-bit shift registers for storing n-bit image data, and a second dummy shift register for retrieving 1-bit data stored in the n-bit shift registers. Pixels of a display device.

14. In paragraph 13, The above first dummy shift register operates to retrieve 1-bit data stored in the built-in memory of an adjacent pixel at the first clock of the data movement time interval, The second dummy shift register operates to retrieve 1-bit data stored in the N-bit shift registers at the second clock of the data movement time interval, Each of the above N-bit shift registers shifts 1 bit of data from the third clock of the data movement time interval. Pixels of a display device.

15. In paragraph 13, The first dummy shift register and the second dummy shift register include a reset switch for resetting the register after movement of image data. Pixels of a display device.

16. A controller that controls data writing, light-emitting element operation, and data movement; and It comprises a plurality of pixels having a pixel memory that stores image data expressed as multi-bit values, At least one of the plurality of pixels includes a plurality of output pins (Pins) for outputting image data stored in the pixel built-in memory to an adjacent pixel based on a control signal input from the controller during a data movement time interval, and a plurality of input pins for receiving image data from the adjacent pixel. Display device.

17. In paragraph 16, The above multiple output pins It includes an up output pin (DO_U) that outputs image data to the upper adjacent pixel, a down output pin (DO_D) that outputs image data to the lower adjacent pixel, a left output pin (DO_L) that outputs image data to the left adjacent pixel, and a right output pin (DO_R) that outputs image data to the right adjacent pixel. The above multiple input pins It includes a down input pin (DI_D) that receives image data from the upper adjacent pixel, an up input pin (DI_U) that receives image data from the lower adjacent pixel, a right input pin (DI_R) that receives image data from the left adjacent pixel, and a left input pin (DI_L) that receives image data from the right adjacent pixel. Display device.

18. A controller that controls data writing, light-emitting element operation, and data movement; and Contains a first pixel and a second pixel, The first pixel and the second pixel include a pixel memory that stores image data expressed as a multi-bit value, The pixel built-in memory includes a first dummy shift register for retrieving 1-bit data stored in the built-in memory of an adjacent pixel, n-bit shift registers for storing n-bit image data, and a second dummy shift register for retrieving 1-bit data stored in the n-bit shift registers during the data movement time interval. Display device.

19. In paragraph 18, If the first pixel and the second pixel are pixels connected to the same column line, the image data shift between the left and right adjacent pixels is performed for n+1 line times. Display device.

20. In paragraph 18, When the first pixel is a pixel connected to the first column line, the second pixel is a pixel connected to the second column line, and image data is shifted from the first pixel to the second pixel, The first pixel performs a shift by 1 bit in the order of the first dummy shift register, the second dummy shift register, and the n-bit shift registers of the first pixel in the clock cycle of the first column line, The second pixel performs a shift by 1 bit in the order of the first dummy shift register, the second dummy shift register, and the n-bits shift registers of the second pixel in the clock cycle of the second line delayed by 1 line time from the clock cycle of the first column line. Display device.

Images