Pixel driving circuit and driving method therefor, and display apparatus

Abstract

A pixel driving circuit and a driving method therefor, and a display apparatus. The pixel driving circuit comprises: a first control sub-circuit, which is configured to provide a signal to a first node (N1) under the control of signals of at least one scanning signal terminal, at least one input signal terminal and a third node (N3); second control sub-circuits, which are configured to provide a signal of a first power supply terminal (ELVDD) to a second node (N2) and provide a signal of the third node (N3) to a fourth node (N4) respectively under the control of signals of a first light emission signal terminal (EM1) and a second light emission signal terminal (EM2); and a third control sub-circuit, which is configured to provide a signal of an initial signal terminal (INIT) to the second node (N2) under the control of a signal of a third scanning signal terminal (G3).

Description

Pixel driving circuit and driving method thereof, and display device TECHNICAL FIELD

[0001] The present document relates to, but is not limited to, the technical field of display, in particular to a pixel driving circuit and driving method thereof, and display device. BACKGROUND

[0002] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diodes (QLED) are active light-emitting display devices, which have the advantages of self-luminous, wide viewing angle, high contrast, low power consumption, extremely high response speed, light and thin, bendable, and low cost. With the continuous development of display technology, the display device with OLED or QLED as light-emitting device and controlled by Thin Film Transistor (TFT) has become the mainstream product in the current display field.

[0003] SUMMARY

[0004] The following is a summary of the subject matter of the detailed description herein. This summary is not intended to limit the scope of the claims.

[0005] In a first aspect, the present disclosure provides a pixel driving circuit, comprising: a driving sub-circuit, a first control sub-circuit, a second control sub-circuit, and a third control sub-circuit;

[0006] The first control sub-circuit is electrically connected with at least one scan signal terminal, at least one input signal terminal, a first node, and a third node respectively, and is configured to provide a signal to the first node under the control of signals of the at least one scan signal terminal, the at least one input signal terminal, and the third node;

[0007] The second control sub-circuit is electrically connected with a first light-emitting signal terminal, a second light-emitting signal terminal, a first power supply terminal, a second node, a third node, and a fourth node respectively, and is configured to provide a signal of the first power supply terminal to the second node and a signal of the third node to the fourth node under the control of signals of the first light-emitting signal terminal and the second light-emitting signal terminal;

[0008] The third control sub-circuit is electrically connected with a third scan signal terminal, the second node, and an initial signal terminal respectively, and is configured to provide a signal of the initial signal terminal to the second node under the control of a signal of the third scan signal terminal;

[0009] The driving sub-circuit is electrically connected with the first node, the second node, and the third node respectively, and is configured to provide a driving signal to the third node under the control of signals of the first node and the second node.

[0010] In an example embodiment, the at least one scan signal terminal includes a first scan signal terminal and a second scan signal terminal, and the at least one input signal terminal includes a data signal terminal and a reference signal terminal.

[0011] The first control sub-circuit is configured to provide a signal of the data signal terminal or the reference signal terminal to the first node under control of signals of the first scan signal terminal and the second scan signal terminal, and store a voltage difference of signals of the first node and the third node.

[0012] In an example embodiment, the first control sub-circuit includes a data write sub-circuit, an initialization sub-circuit, and a first storage sub-circuit.

[0013] The data write sub-circuit is electrically connected to the first scan signal terminal, the data signal terminal, and the first node respectively, and is configured to provide a signal of the data signal terminal to the first node under control of a signal of the first scan signal terminal.

[0014] The initialization sub-circuit is electrically connected to the second scan signal terminal, the reference signal terminal, and the first node respectively, and is configured to provide a signal of the reference signal terminal to the first node under control of a signal of the second scan signal terminal.

[0015] The first storage sub-circuit is electrically connected to the first node and the third node respectively, and is configured to store a voltage difference of signals of the first node and the third node.

[0016] In an example embodiment, the data write sub-circuit includes a first transistor, the initialization sub-circuit includes a second transistor, and the first storage sub-circuit includes a first capacitor.

[0017] The control electrode of the first transistor is electrically connected to the first scan signal terminal, the first electrode of the first transistor is electrically connected to the data signal terminal, and the second electrode of the first transistor is electrically connected to the first node.

[0018] The control electrode of the second transistor is electrically connected to the second scan signal terminal, the first electrode of the second transistor is electrically connected to the reference signal terminal, and the second electrode of the second transistor is electrically connected to the first node.

[0019] The first end of the first capacitor is electrically connected to the first node, and the second end of the first capacitor is electrically connected to the third node.

[0020] In an example embodiment, the at least one scan signal terminal includes a first scan signal terminal, and the at least one input signal terminal includes a control signal terminal, the control signal terminal being the data signal terminal at least part of the time and being the reference signal terminal at least part of the time.

[0021] The first control sub-circuit is configured to provide a signal of the control signal terminal to the first node under control of a signal of the first scan signal terminal, and store a voltage difference of signals of the first node and the third node.

[0022] In an example embodiment, the first control sub-circuit comprises a node control sub-circuit and a first storage sub-circuit.

[0023] The node control sub-circuit is electrically connected with the first scan signal terminal, the control signal terminal and the first node respectively, and is configured to provide a signal of the control signal terminal to the first node under control of a signal of the first scan signal terminal.

[0024] The first storage sub-circuit is electrically connected with the first node and the third node respectively, and is configured to store a voltage difference of signals of the first node and the third node.

[0025] In an example embodiment, the node control sub-circuit comprises a first transistor, and the first storage sub-circuit comprises a first capacitor.

[0026] The control electrode of the first transistor is electrically connected with the first scan signal terminal, the first electrode of the first transistor is electrically connected with the control signal terminal, and the second electrode of the first transistor is electrically connected with the first node.

[0027] The first end of the first capacitor is electrically connected with the first node, and the second end of the first capacitor is electrically connected with the third node.

[0028] In an example embodiment, the first control sub-circuit is further electrically connected with a constant voltage signal terminal, and further comprises a second storage sub-circuit.

[0029] The second storage sub-circuit is electrically connected with the constant voltage signal terminal and the third node respectively, and is configured to store a voltage difference of signals of the constant voltage signal terminal and the third node.

[0030] In an example embodiment, the second storage sub-circuit comprises a second capacitor.

[0031] The first end of the second capacitor is electrically connected with the constant voltage signal terminal, and the second end of the second capacitor is electrically connected with the third node.

[0032] In an example embodiment, the drive sub-circuit comprises a third transistor, and the second control sub-circuit comprises a fifth transistor and a sixth transistor.

[0033] The control electrode of the third transistor is electrically connected with the first node, the first electrode of the third transistor is electrically connected with the second node, and the second electrode of the third transistor is electrically connected with the third node.

[0034] The control electrode of the fifth transistor is electrically connected with the first light-emitting signal end, the first electrode of the fifth transistor is electrically connected with the first power supply end, and the second electrode of the fifth transistor is electrically connected with the second node;

[0035] The control electrode of the sixth transistor is electrically connected with the second light-emitting signal end, the first electrode of the sixth transistor is electrically connected with the third node, and the second electrode of the sixth transistor is electrically connected with the fourth node.

[0036] In an exemplary embodiment, the third control sub-circuit comprises a fourth transistor;

[0037] The control electrode of the fourth transistor is electrically connected with the third scan signal end, the first electrode of the fourth transistor is electrically connected with the initial signal end, and the second electrode of the fourth transistor is electrically connected with the second node.

[0038] In an exemplary embodiment, the first control sub-circuit comprises a first transistor, a second transistor and a first capacitor, or comprises a first transistor, a second transistor, a first capacitor and a second capacitor, the second control sub-circuit comprises a fifth transistor and a sixth transistor, the third control sub-circuit comprises a fourth transistor, and the driving transistor comprises a third transistor;

[0039] The control electrode of the first transistor is electrically connected with the first scan signal end, the first electrode of the first transistor is electrically connected with the data signal end, and the second electrode of the first transistor is electrically connected with the first node;

[0040] The control electrode of the second transistor is electrically connected with the second scan signal end, the first electrode of the second transistor is electrically connected with the reference signal end, and the second electrode of the second transistor is electrically connected with the first node;

[0041] The control electrode of the third transistor is electrically connected with the first node, the first electrode of the third transistor is electrically connected with the second node, and the second electrode of the third transistor is electrically connected with the third node;

[0042] The control electrode of the fourth transistor is electrically connected with the third scan signal end, the first electrode of the fourth transistor is electrically connected with the initial signal end, and the second electrode of the fourth transistor is electrically connected with the second node.

[0043] The control electrode of the fifth transistor is electrically connected with the first light-emitting signal end, the first electrode of the fifth transistor is electrically connected with the first power supply end, and the second electrode of the fifth transistor is electrically connected with the second node;

[0044] The control electrode of the sixth transistor is electrically connected with the second light-emitting signal end, the first electrode of the sixth transistor is electrically connected with the third node, and the second electrode of the sixth transistor is electrically connected with the fourth node.

[0045] The first end of the first capacitor is electrically connected with the first node, and the second end of the first capacitor is electrically connected with the third node.

[0046] A first end of the second capacitor is electrically connected with the constant voltage signal end, and a second end of the second capacitor is electrically connected with the third node.

[0047] In an example embodiment, the first control sub-circuit comprises a first transistor and a first capacitor, or comprises a first transistor, a first capacitor and a second capacitor, the second control sub-circuit comprises a fifth transistor and a sixth transistor, the third control sub-circuit comprises a fourth transistor, and the driving transistor comprises a third transistor.

[0048] A control electrode of the first transistor is electrically connected with the first scan signal end, a first electrode of the first transistor is electrically connected with the control signal end, and a second electrode of the first transistor is electrically connected with the first node.

[0049] A control electrode of the third transistor is electrically connected with the first node, a first electrode of the third transistor is electrically connected with the second node, and a second electrode of the third transistor is electrically connected with the third node.

[0050] A control electrode of the fourth transistor is electrically connected with the third scan signal end, a first electrode of the fourth transistor is electrically connected with the initial signal end, and a second electrode of the fourth transistor is electrically connected with the second node.

[0051] A control electrode of the fifth transistor is electrically connected with the first light-emitting signal end, a first electrode of the fifth transistor is electrically connected with the first power supply end, and a second electrode of the fifth transistor is electrically connected with the second node.

[0052] A control electrode of the sixth transistor is electrically connected with the second light-emitting signal end, a first electrode of the sixth transistor is electrically connected with the third node, and a second electrode of the sixth transistor is electrically connected with the fourth node.

[0053] A first end of the first capacitor is electrically connected with the first node, and a second end of the first capacitor is electrically connected with the third node.

[0054] A first end of the second capacitor is electrically connected with the constant voltage signal end, and a second end of the second capacitor is electrically connected with the third node.

[0055] In an example embodiment, the pixel driving circuit is electrically connected with a light-emitting device, and the light-emitting device is respectively electrically connected with the fourth node and the second power supply end.

[0056] The constant voltage signal end is the same signal end as one of the reference signal end, the initial signal end, the first power supply end and the second power supply end.

[0057] In a second aspect, the disclosure also provides a display device comprising the pixel driving circuit.

[0058] In an example embodiment, the at least one scan signal end comprises a first scan signal end and a second scan signal end.

[0059] The display device further comprises a first data unit, a second data unit, a third data unit, a fourth data unit and a fifth data unit, the first data unit is electrically connected with the first scanning signal terminal and is configured to provide a signal to the first scanning signal terminal, the second data unit is electrically connected with the second scanning signal terminal and is configured to provide a signal to the second scanning signal terminal, the third data unit is electrically connected with the third scanning signal terminal and is configured to provide a signal to the third scanning signal terminal, the fourth data unit is electrically connected with the first light-emitting signal terminal and is configured to provide a signal to the first light-emitting signal terminal, and the fifth data unit is electrically connected with the second light-emitting signal terminal and is configured to provide a signal to the second light-emitting signal terminal;

[0060] The time when the first data unit provides the effective level signal to the first scanning signal terminal does not overlap with the time when the second data unit provides the effective level signal to the second scanning signal terminal and the time when the third data unit provides the effective level signal to the third scanning signal terminal, and the time when the second data unit provides the effective level signal to the second scanning signal terminal at least partially overlaps with the time when the third data unit provides the effective level signal to the third scanning signal terminal;

[0061] The at least part of the time when the fourth data unit provides the effective level signal to the first light-emitting signal terminal and the at least part of the time when the fifth data unit provides the effective level signal to the second light-emitting signal terminal at least partially overlap with the time when the second data unit provides the effective level signal to the second scanning signal terminal.

[0062] In an exemplary embodiment, the time when the fourth data unit provides the effective level signal to the first light-emitting signal terminal comprises a first time and a second time, and the time when the fifth data unit provides the effective level signal to the second light-emitting signal terminal comprises a third time and a fourth time;

[0063] The first time occurs before the second time, the third time occurs before the fourth time, the third time occurs before the first time, and the second time and the fourth time at least partially overlap;

[0064] The time when the third data unit provides the effective level signal to the third scanning signal terminal, the first time and the third time are located in the time when the second data unit provides the effective level signal to the second scanning signal terminal, the time when the third data unit provides the effective level signal to the third scanning signal terminal at least partially overlaps with the third time and does not overlap with the first time;

[0065] The time when the first data unit provides the effective level signal to the first scanning signal terminal is located between the first time and the second time.

[0066] In the exemplary embodiments, in the state that the first time lasts for K*H, the third scan signal terminal connected with the nth row of pixel driving circuit is the same as the first scan signal terminal connected with the n+K+1th row of pixel driving circuit, H is the time for driving one row of pixel driving circuit, K is a positive integer greater than or equal to 1, n is a positive integer greater than or equal to 1 and less than M-K, and M is the total number of rows of pixel driving circuit.

[0067] In the exemplary embodiments, the at least one scan signal terminal comprises a first scan signal terminal;

[0068] The display device further comprises a first data unit, a third data unit, a fourth data unit and a fifth data unit, the first data unit is electrically connected with the first scan signal terminal and configured to provide a signal to the first scan signal terminal, the third data unit is electrically connected with the third scan signal terminal and configured to provide a signal to the third scan signal terminal, the fourth data unit is electrically connected with the first light-emitting signal terminal and configured to provide a signal to the first light-emitting signal terminal, and the fifth data unit is electrically connected with the second light-emitting signal terminal and configured to provide a signal to the second light-emitting signal terminal.

[0069] The time when the first data unit provides an effective level signal to the first scan signal terminal at least partially overlaps with the time when the third data unit provides an effective level signal to the third scan signal terminal, the time when the fourth data unit provides an effective level signal to the first light-emitting signal terminal, and the time when the fifth data unit provides an effective level signal to the second light-emitting signal terminal, the time when the third data unit provides an effective level signal to the third scan signal terminal at least partially overlaps with the time when the fifth data unit provides an effective level signal to the second light-emitting signal terminal, and at least part of the time when the fourth data unit provides an effective level signal to the first light-emitting signal terminal does not overlap with at least part of the time when the fifth data unit provides an effective level signal to the second light-emitting signal terminal.

[0070] In the exemplary embodiments, the time when the first data unit provides an effective level signal to the first scan signal terminal comprises a fifth time, a plurality of interval-arranged sixth times and a seventh time, the time when the fourth data unit provides an effective level signal to the first light-emitting signal terminal comprises an eighth time and a plurality of interval-arranged sixth times, and the time when the fifth data unit provides an effective level signal to the second light-emitting signal terminal comprises a ninth time and a tenth time.

[0071] The fifth time occurs before the first sixth time and has an interval with the first sixth time, the seventh time occurs after the last sixth time and has an interval with the last sixth time, the eighth time and the tenth time occur after the seventh time, and the ninth time occurs before the tenth time.

[0072] The ninth time at least partially overlaps with the fifth time, the eighth time at least partially overlaps with the tenth time, and the time at which the third data unit provides the valid level signal to the third scan signal end at least partially overlaps with the fifth time and the ninth time, respectively.

[0073] In an example embodiment, further comprising: a sixth data unit, the sixth data unit being electrically connected with the control signal end and being configured to provide a signal to the control signal end.

[0074] The sixth data unit is configured to provide a reference signal to the control signal end at the fifth time, the sixth time, the time between the last sixth time and the seventh time, the part of the time at the eighth time, and the part of the time at the tenth time, and to provide a data signal to the control signal end at the time between the fifth time and the first sixth time, between adjacent sixth times, the seventh time, at least part of the time at the eighth time, and at least part of the time at the tenth time, wherein the reference signal is a signal of the reference signal end and the data signal is a signal of the data signal end.

[0075] In an example embodiment, further comprising: a plurality of signal lines; and the pixel driving circuits are electrically connected with the first scan signal end, the second scan signal end, the third scan signal end, the reference signal end, the initial signal end, and the data signal end, respectively, and at least one pixel driving circuit comprises: a fourth transistor and a fifth transistor.

[0076] The display device comprises: a plurality of pixel driving circuit groups, and the plurality of pixel driving circuit groups comprise: at least two pixel driving circuits located in at least one row.

[0077] The first scan signal ends connected by the pixel driving circuits in the same pixel driving circuit group are connected to the same signal line, the second scan signal ends connected by the pixel driving circuits in the same pixel driving circuit group are connected to the same signal line, the third scan signal ends connected by the pixel driving circuits in the same pixel driving circuit group are connected to the same signal line, the reference signal ends connected by the pixel driving circuits in the same pixel driving circuit group are connected to the same signal line, and the initial signal ends connected by the pixel driving circuits in the same pixel driving circuit group are connected to the same signal line.

[0078] The fourth transistor in at least two pixel driving circuits in the same pixel driving circuit group is the same transistor, or the fifth transistor in at least two pixel driving circuits in the same pixel driving circuit group is the same transistor, or the fourth transistor in at least two pixel driving circuits in the same pixel driving circuit group is the same transistor, and the fifth transistor in at least two pixel driving circuits in the same pixel driving circuit group is the same transistor.

[0079] In an example embodiment, further comprising: a plurality of signal lines; the pixel driving circuits are electrically connected with a first scan signal end, a third scan signal end, an initial signal end and a control signal end respectively, and at least one pixel driving circuit comprises: a fourth transistor and a fifth transistor;

[0080] The display device comprises: a plurality of pixel driving circuit groups, and the plurality of pixel driving circuit groups comprise: at least two pixel driving circuits in at least one row;

[0081] The first scan signal ends connected by the pixel driving circuits in the same pixel driving circuit group are connected with the same signal line, the third scan signal ends connected by the pixel driving circuits in the same pixel driving circuit group are connected with the same signal line, and the initial signal ends connected by the pixel driving circuits in the same pixel driving circuit group are connected with the same signal line;

[0082] The fourth transistor in at least two pixel driving circuits in the same pixel driving circuit group is the same transistor, or the fifth transistor in at least two pixel driving circuits in the same pixel driving circuit group is the same transistor, or the fourth transistor in at least two pixel driving circuits in the same pixel driving circuit group is the same transistor, and the fifth transistor in at least two pixel driving circuits in the same pixel driving circuit group is the same transistor.

[0083] In a third aspect, the present disclosure further provides a driving method of a pixel driving circuit, configured to drive the pixel driving circuit, the method comprising:

[0084] The first control sub-circuit provides a signal to the first node under the control of signals at the at least one scan signal end, the at least one input signal end and the third node;

[0085] The second control sub-circuit provides a signal of the first power supply end to the second node and a signal of the third node to the fourth node under the control of signals at the first light-emitting signal end and the second light-emitting signal end;

[0086] The third control sub-circuit provides a signal of the initial signal end to the second node under the control of a signal at the third scan signal end;

[0087] The driving sub-circuit provides a driving signal to the third node under the control of signals of the first node and the second node.

[0088] Other aspects can become apparent from the following detailed description when read in conjunction with the drawings.

[0089] SUMMARY

[0090] The accompanying drawings are included to provide a further understanding of the present technology, and constitute a part of this specification. The drawings illustrate embodiments of the present technology and, together with the description, serve to explain the principles of the present technology. The drawings are not intended to be to scale.

[0091] FIG. 1 is a structural schematic diagram of a pixel driving circuit according to an embodiment of the present disclosure;

[0092] FIG. 2 is a structural schematic diagram of a pixel driving circuit according to another embodiment of the present disclosure;

[0093] FIG. 3 is a structural schematic diagram of a first control sub-circuit in the pixel driving circuit according to the embodiment of FIG. 1;

[0094] FIG. 4 is an equivalent circuit diagram of the first control sub-circuit according to the embodiment of FIG. 3;

[0095] FIG. 5 is a structural schematic diagram of a first control sub-circuit in the pixel driving circuit according to the embodiment of FIG. 2;

[0096] FIG. 6 is an equivalent circuit diagram of the first control sub-circuit according to the embodiment of FIG. 5;

[0097] FIG. 7 is a structural schematic diagram of a first control sub-circuit in the pixel driving circuit according to the embodiment of FIG. 1;

[0098] FIG. 8 is a structural schematic diagram of a first control sub-circuit in the pixel driving circuit according to the embodiment of FIG. 2;

[0099] FIG. 9 is an equivalent circuit diagram of a second storage sub-circuit according to the embodiment of FIG. 7;

[0100] FIG. 10 is an equivalent circuit diagram of a second storage sub-circuit according to the embodiment of FIG. 8;

[0101] FIG. 11 is an equivalent circuit diagram of a driving sub-circuit, a second control sub-circuit and a third control sub-circuit;

[0102] FIG. 12 is an equivalent circuit diagram of a pixel driving circuit;

[0103] FIG. 13 is an equivalent circuit diagram of another pixel driving circuit;

[0104] FIG. 14 is a driving timing diagram of the pixel driving circuit according to the embodiment of FIG. 12;

[0105] FIG. 15 is a driving timing diagram of the pixel driving circuit according to the embodiment of FIG. 13;

[0106] Fig. 16 is an equivalent circuit diagram of a pixel drive circuit group 1;

[0107] Fig. 17 is an equivalent circuit diagram of a pixel drive circuit group 2;

[0108] Fig. 18 is an equivalent circuit diagram of a pixel drive circuit group 3;

[0109] Fig. 19 is an equivalent circuit diagram of a pixel drive circuit group 4;

[0110] Fig. 20 is an equivalent circuit diagram of a pixel drive circuit group 5;

[0111] Fig. 21 is an equivalent circuit diagram of a pixel drive circuit group 6.

[0112] Detailed description

[0113] In order to make the objects, technical solutions and advantages of the present disclosure clearer, below the embodiments of the present disclosure will be described in detail with reference to the drawings. Note that the embodiments can be implemented in multiple different forms. It can be easily understood by those skilled in the art that the manners and contents can be changed into various forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. The embodiments in the present disclosure and the features in the embodiments can be combined with each other arbitrarily without conflict.

[0114] The proportions of the drawings in the present disclosure can be used as a reference in the actual process, but are not limited thereto. For example, the width-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are also not limited to the number shown in the drawings. The drawings described in the present disclosure are only schematic structural diagrams, and one embodiment of the present disclosure is not limited to the shapes or values shown in the drawings.

[0115] The ordinal numbers "first", "second", "third" and the like in the present specification are set in order to avoid confusion of the constituent elements, and are not intended to be limited in terms of quantity.

[0116] In this specification, terms of "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicating the positional or directional relationship of components are used to describe the positional relationship of components with reference to the drawings for the convenience of explanation and simplification of the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be construed as limiting on the present disclosure. The positional relationship of components is appropriately changed according to the direction in which each component is described. Therefore, it is not limited to the words described in the specification, and can be appropriately changed according to the situation.

[0117] In this specification, unless explicitly defined and limited otherwise, the terms "mount", "connected", "connected" should be broadly understood. For example, it can be fixedly connected, or detachably connected, or integrally connected; it can be mechanically connected, or electrically connected; it can be directly connected, or indirectly connected through an intermediate piece, or communication inside two elements. For those skilled in the art, the specific meaning of the above terms in the present disclosure can be understood according to the specific circumstances.

[0118] In this specification, a transistor refers to an element including at least a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to a region through which current mainly flows.

[0119] In this specification, the first electrode can be a drain electrode, and the second electrode can be a source electrode, or the first electrode can be a source electrode, and the second electrode can be a drain electrode. In the case of using a transistor with opposite polarity or in the case of changing the direction of current in the circuit operation, the functions of "source electrode" and "drain electrode" are sometimes exchanged with each other. Therefore, in this specification, "source electrode" and "drain electrode" can be exchanged with each other, and "source terminal" and "drain terminal" can be exchanged with each other.

[0120] In this specification, "electrically connected" includes the case where components are connected together through an element having some electrical action. The element having some electrical action is not particularly limited as long as it can transmit and receive an electrical signal between the components to be connected. Examples of the element having some electrical action include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, and another element having various functions.

[0121] In this specification, "parallel" means a state where an angle formed by two straight lines is -10° or more and 10° or less, and thus, an angle of -5° or more and 5° or less is also included. In addition, "perpendicular" means a state where an angle formed by two straight lines is 80° or more and 100° or less, and thus, a state where an angle of 85° or more and 95° or less is also included.

[0122] In this specification, "film" and "layer" can be interchanged with each other. For example, "a conductive layer" can be sometimes interchanged with "a conductive film". Similarly, "an insulating film" can be sometimes interchanged with "an insulating layer".

[0123] In this specification, a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon is not necessarily strict, and can be an approximate triangle, an approximate rectangle, an approximate trapezoid, an approximate pentagon, or an approximate hexagon. There can be some small deformation due to a tolerance, a rounded corner, a curved side, or the like.

[0124] With the development of OLED display technology, oxide process is often applied in OLED display products due to high uniformity. The compensation process of pixel driving circuit made by oxide process occurs with the data writing process, which makes the compensation time of pixel driving circuit shorter and reduces the reliability of pixel driving circuit.

[0125] FIG. 1 is a structural schematic diagram of a pixel driving circuit according to an embodiment of the present disclosure, and FIG. 2 is another structural schematic diagram of the pixel driving circuit according to an embodiment of the present disclosure. As shown in FIG. 1 and FIG. 2, the pixel driving circuit according to an embodiment of the present disclosure can include a driving sub-circuit, a first control sub-circuit, a second control sub-circuit, and a third control sub-circuit. The first control sub-circuit is electrically connected to at least one scan signal terminal, at least one input signal terminal, a first node N1, and a third node N3, respectively, and is configured to provide a signal to the first node N1 under the control of signals of the at least one scan signal terminal, the at least one input signal terminal, and the third node N3. The second control sub-circuit is electrically connected to a first emission signal terminal EM1, a second emission signal terminal EM2, a first power supply terminal ELVDD, a second node N2, the third node N3, and a fourth node N4, respectively, and is configured to provide a signal of the first power supply terminal ELVDD to the second node N2 and a signal of the third node N3 to the fourth node N4 under the control of signals of the first emission signal terminal EM1 and the second emission signal terminal EM2. The third control sub-circuit is electrically connected to a third scan signal terminal G3, the second node N2, and an initial signal terminal INIT, respectively, and is configured to provide a signal of the initial signal terminal INIT to the second node N2 under the control of a signal of the third scan signal terminal G3. The driving sub-circuit is electrically connected to the first node N1, the second node N2, and the third node N3, respectively, and is configured to provide a driving signal to the third node N3 under the control of signals of the first node N1 and the second node N2. FIG. 1 is described by taking an example in which the at least one scan signal terminal includes a first scan signal terminal G1 and a second scan signal terminal G2, and the at least one input signal terminal includes a data signal terminal DATA and a reference signal terminal REF, and FIG. 2 is described by taking an example in which the at least one scan signal terminal includes the first scan signal terminal G1, and the at least one input signal terminal includes a control signal terminal CON.

[0126] In an example embodiment, the control signal terminal CON is the data signal terminal DATA at least part of the time and is the reference signal terminal REF at least part of the time.

[0127] In an example embodiment, the signal of the reference signal terminal can have a voltage of 0 V.

[0128] In an example embodiment, the first power supply terminal ELVDD can continuously provide a high-level signal, and the signal of the first power supply terminal ELVDD is a direct current signal.

[0129] In an example embodiment, the pixel driving circuit is configured to drive a light emitting device EL to emit light. As shown in FIG. 1 and FIG. 2, the light emitting device EL is electrically connected to the fourth node N4 and a second power supply terminal ELVSS, respectively.

[0130] In an example embodiment, the second power terminal ELVSS can continuously provide a low-level signal, and the signal of the second power terminal ELVSS is a direct current signal.

[0131] In an example embodiment, the light emitting device EL can include a first electrode (anode), an organic emitting layer, and a second electrode (cathode) stacked. Illustratively, the anode of the light emitting device EL is electrically connected to the third node N3, and the cathode of the light emitting device EL is electrically connected to the second power terminal ELVSS.

[0132] In an example embodiment, the light emitting device EL can include a current driving type device, and can employ a current type light emitting diode, such as a Micro Light Emitting Diode (Micro LED) or a Mini Light Emitting Diode (Mini LED) or an Organic Light Emitting Diode (OLED) or a Quantum Light Emitting Diode (QLED). The typical size (e.g. length) of a Micro LED can be less than 100 μm, such as 10 μm to 50 μm. The typical size (e.g. length) of a Mini LED can be about 100 μm to 300 μm, such as 120 μm to 260 μm.

[0133] In an example embodiment, the organic emitting layer can include a Hole Injection Layer (HIL), a Hole Transport Layer (HTL), an Electron Block Layer (EBL), an Emitting Layer (EML), a Hole Block Layer (HBL), an Electron Transport Layer (ETL), and an Electron Injection Layer (EIL) stacked. In an example embodiment, the HIL of all sub-pixels can be a common layer connected together, the EIL of all sub-pixels can be a common layer connected together, the HTL of all sub-pixels can be a common layer connected together, the ETL of all sub-pixels can be a common layer connected together, the HBL of all sub-pixels can be a common layer connected together, the EML of adjacent sub-pixels can have a small amount of overlap, or can be isolated, and the EBL of adjacent sub-pixels can have a small amount of overlap, or can be isolated.

[0134] The pixel driving circuit provided by the present disclosure can make the compensation process of the pixel driving circuit independent of the data writing process, prolong the compensation time of the pixel driving circuit, and thus improve the reliability of the pixel driving circuit through the cooperation of the first control sub-circuit, the second control sub-circuit and the third control sub-circuit.

[0135] FIG. 3 is a structural schematic diagram of the first control sub-circuit in the pixel driving circuit provided by FIG. 1. As shown in FIG. 3, when the at least one scan signal end includes a first scan signal end G1 and a second scan signal end G2, and the at least one input signal end includes a data signal end DATA and a reference signal end REF, the first control sub-circuit is configured to provide the signal of the data signal end DATA or the reference signal end REF to a first node N1 under the control of the signals of the first scan signal end G1 and the second scan signal end G2, and store the voltage difference of the signals of the first node N1 and a third node N3.

[0136] As shown in FIG. 3, in an exemplary embodiment, the first control sub-circuit can include a data writing sub-circuit, an initialization sub-circuit and a first storage sub-circuit. The data writing sub-circuit is electrically connected with the first scan signal end G1, the data signal end DATA and the first node N1 respectively, and is configured to provide the signal of the data signal end DATA to the first node N1 under the control of the signal of the first scan signal end G1; the initialization sub-circuit is electrically connected with the second scan signal end G2, the reference signal end REF and the first node N1 respectively, and is configured to provide the signal of the reference signal end REF to the first node N1 under the control of the signal of the second scan signal end G2; and the first storage sub-circuit is electrically connected with the first node N1 and the third node N3 respectively, and is configured to store the voltage difference of the signals of the first node N1 and the third node N3.

[0137] FIG. 4 is an equivalent circuit diagram of the first control sub-circuit provided by FIG. 3. As shown in FIG. 4, in an exemplary embodiment, the data writing sub-circuit can include a first transistor T1. The control electrode of the first transistor T1 is electrically connected with the first scan signal end G1, the first electrode of the first transistor T1 is electrically connected with the data signal end DATA, and the second electrode of the first transistor T1 is electrically connected with the first node N1. The first transistor T1 can be referred to as a data writing transistor.

[0138] As shown in FIG. 4, in an exemplary embodiment, the initialization sub-circuit includes a second transistor T2. The control electrode of the second transistor T2 is electrically connected with the second scan signal end G2, the first electrode of the second transistor T2 is electrically connected with the reference signal end REF, and the second electrode of the second transistor T2 is electrically connected with the first node N1. The second transistor T2 can be referred to as an initialization transistor.

[0139] As shown in FIG. 4, in an example embodiment, the first storage sub-circuit includes a first capacitor C1. Wherein a first terminal of the first capacitor C1 is electrically connected with the first node N1, and a second terminal of the first capacitor C1 is electrically connected with the third node N3.

[0140] Only one example structure of the data writing sub-circuit, the initialization sub-circuit and the first storage sub-circuit is shown in FIG. 4, and it is easy for those skilled in the art to understand that the implementation of the data writing sub-circuit, the initialization sub-circuit and the first storage sub-circuit is not limited thereto.

[0141] FIG. 5 is a structural schematic diagram of the first control sub-circuit in the pixel driving circuit provided in FIG. 2. As shown in FIG. 5, in an example embodiment, when the at least one scan signal end includes a first scan signal end G1, and the at least one input signal end includes a control signal end CON, the first control sub-circuit is configured to provide the signal of the control signal end CON to the first node N1 under the control of the signal of the first scan signal end G1, and store the voltage difference of the signals of the first node N1 and the third node N3.

[0142] As shown in FIG. 5, in an example embodiment, the first control sub-circuit can include a node control sub-circuit and a first storage sub-circuit. Wherein the node control sub-circuit is electrically connected with the first scan signal end G1, the control signal end CON and the first node N1 respectively, and is configured to provide the signal of the control signal end to the first node N1 under the control of the signal of the first scan signal end G1; and the first storage sub-circuit is electrically connected with the first node N1 and the third node N3 respectively, and is configured to store the voltage difference of the signals of the first node N1 and the third node N3.

[0143] FIG. 6 is an equivalent circuit diagram of the first control sub-circuit provided in FIG. 5. As shown in FIG. 6, in an example embodiment, the node control sub-circuit can include a first transistor T1. Wherein a control electrode of the first transistor T1 is electrically connected with the first scan signal end G1, a first electrode of the first transistor T1 is electrically connected with the control signal end CON, and a second electrode of the first transistor T1 is electrically connected with the first node N1.

[0144] As shown in FIG. 6, in an example embodiment, the first storage sub-circuit can include a first capacitor C1. Wherein a first terminal of the first capacitor C1 is electrically connected with the first node N1, and a second terminal of the first capacitor C1 is electrically connected with the third node N3.

[0145] Only one example structure of the node control sub-circuit and the first storage sub-circuit is shown in FIG. 6, and it is easy for those skilled in the art to understand that the implementation of the node control sub-circuit and the first storage sub-circuit is not limited thereto.

[0146] In an example embodiment, the first control sub-circuit is further electrically connected with a constant voltage signal end.

[0147] FIG. 7 is a schematic diagram of a second structure of the first control sub-circuit of the pixel driving circuit provided in FIG. 1, and FIG. 8 is a schematic diagram of a second structure of the first control sub-circuit of the pixel driving circuit provided in FIG. 2. As shown in FIG. 7 and FIG. 8, the first control sub-circuit can further include a second storage sub-circuit. The second storage sub-circuit is electrically connected with the constant voltage signal terminal V0 and the third node N3 respectively, and is configured to store the voltage difference of the signals of the constant voltage signal terminal V0 and the third node N3.

[0148] In an example embodiment, FIG. 9 is an equivalent circuit diagram of the second storage sub-circuit provided in FIG. 7, and FIG. 10 is an equivalent circuit diagram of the second storage sub-circuit provided in FIG. 8. As shown in FIG. 9 and FIG. 10, the second storage sub-circuit can include a second capacitor C2. Wherein, a first end of the second capacitor C2 is electrically connected with the constant voltage signal terminal V0, and a second end of the second capacitor C2 is electrically connected with the third node N3.

[0149] Only one example structure of the second storage sub-circuit is shown in FIG. 8 and FIG. 9, and it is easy for those skilled in the art to understand that the implementation of the second storage sub-circuit is not limited thereto.

[0150] In an example embodiment, FIG. 11 is an equivalent circuit diagram of the driving sub-circuit, the second control sub-circuit and the third control sub-circuit. As shown in FIG. 11, the driving sub-circuit can include a third transistor T3. Wherein, a control electrode of the third transistor T3 is electrically connected with the first node N1, a first electrode of the third transistor T3 is electrically connected with the second node N2, and a second electrode of the third transistor T3 is electrically connected with the third node N3. The third transistor T3 can be referred to as a driving transistor.

[0151] As shown in FIG. 11, in an example embodiment, the second control sub-circuit includes a fifth transistor T5 and a sixth transistor T6. Wherein, a control electrode of the fifth transistor T5 is electrically connected with the first light-emitting signal terminal EM1, a first electrode of the fifth transistor T5 is electrically connected with the first power supply terminal ELVDD, and a second electrode of the fifth transistor T5 is electrically connected with the second node N2; a control electrode of the sixth transistor T6 is electrically connected with the second light-emitting signal terminal EM2, a first electrode of the sixth transistor T6 is electrically connected with the third node N3, and a second electrode of the sixth transistor T6 is electrically connected with the fourth node N4.

[0152] As shown in FIG. 11, in an example embodiment, the third control sub-circuit can include a fourth transistor T4. Wherein, a control electrode of the fourth transistor T4 is electrically connected with the third scanning signal terminal G3, a first electrode of the fourth transistor T4 is electrically connected with the initial signal terminal INIT, and a second electrode of the fourth transistor T4 is electrically connected with the second node N2.

[0153] It is easy for those skilled in the art to understand that the implementation of the driving sub-circuit, the second control sub-circuit and the third control sub-circuit is not limited to the above.

[0154] FIG. 12 is an equivalent circuit diagram of a pixel driving circuit. As shown in FIG. 12, in an exemplary embodiment, the first control sub-circuit includes a first transistor T1, a second transistor T2, a first capacitor C1 and a second capacitor C2, the second control sub-circuit includes a fifth transistor T5 and a sixth transistor T6, the third control sub-circuit includes a fourth transistor T4, and the driving transistor includes a third transistor T3. Wherein, the control electrode of the first transistor T1 is electrically connected with a first scan signal terminal G1, the first electrode of the first transistor T1 is electrically connected with a data signal terminal DATA, and the second electrode of the first transistor T1 is electrically connected with a first node N1; the control electrode of the second transistor T2 is electrically connected with a second scan signal terminal G2, the first electrode of the second transistor T2 is electrically connected with a reference signal terminal REF, and the second electrode of the second transistor T2 is electrically connected with the first node N1; the control electrode of the third transistor T3 is electrically connected with the first node N1, the first electrode of the third transistor T3 is electrically connected with a second node N2, and the second electrode of the third transistor T3 is electrically connected with a third node N3; the control electrode of the fourth transistor T4 is electrically connected with a third scan signal terminal G3, the first electrode of the fourth transistor T4 is electrically connected with an initial signal terminal INIT, and the second electrode of the fourth transistor T4 is electrically connected with the second node N2; the control electrode of the fifth transistor T5 is electrically connected with a first emission signal terminal EM1, the first electrode of the fifth transistor T5 is electrically connected with a first power supply terminal ELVDD, and the second electrode of the fifth transistor T5 is electrically connected with the second node N2; the control electrode of the sixth transistor T6 is electrically connected with a second emission signal terminal EM2, the first electrode of the sixth transistor T6 is electrically connected with the third node N3, and the second electrode of the sixth transistor T6 is electrically connected with a fourth node N4; the first end of the first capacitor C1 is electrically connected with the first node N1, and the second end of the first capacitor C1 is electrically connected with the third node N3; the first end of the second capacitor C2 is electrically connected with a constant voltage signal terminal V0, and the second end of the second capacitor C2 is electrically connected with the third node N3.

[0155] FIG. 13 is an equivalent circuit diagram of another pixel driving circuit. As shown in FIG. 13, in an example embodiment, the first control sub-circuit includes a first transistor T1, a first capacitor C1 and a second capacitor C2, the second control sub-circuit includes a fifth transistor T5 and a sixth transistor T6, the third control sub-circuit includes a fourth transistor T4, and the driving transistor includes a third transistor T3. The control electrode of the first transistor T1 is electrically connected with a first scan signal terminal G1, the first electrode of the first transistor T1 is electrically connected with a control signal terminal CON, and the second electrode of the first transistor T1 is electrically connected with a first node N1. The control electrode of the third transistor T3 is electrically connected with the first node N1, the first electrode of the third transistor T3 is electrically connected with a second node N2, and the second electrode of the third transistor T3 is electrically connected with a third node N3. The control electrode of the fourth transistor T4 is electrically connected with a third scan signal terminal G3, the first electrode of the fourth transistor T4 is electrically connected with an initial signal terminal INIT, and the second electrode of the fourth transistor T4 is electrically connected with the second node N2. The control electrode of the fifth transistor T5 is electrically connected with a first emission signal terminal EM1, the first electrode of the fifth transistor T5 is electrically connected with a first power supply terminal ELVDD, and the second electrode of the fifth transistor T5 is electrically connected with the second node N2. The control electrode of the sixth transistor T6 is electrically connected with a second emission signal terminal EM2, the first electrode of the sixth transistor T6 is electrically connected with the third node N3, and the second electrode of the sixth transistor T6 is electrically connected with a fourth node N4. The first terminal of the first capacitor C1 is electrically connected with the first node N1, and the second terminal of the first capacitor C1 is electrically connected with the third node N3. The first terminal of the second capacitor C2 is electrically connected with a constant voltage signal terminal V0, and the second terminal of the second capacitor C2 is electrically connected with the third node N3.

[0156] In an example embodiment, the pixel driving circuit can be arranged in a display device, and the display device can include a plurality of sub-pixels, at least one of which includes the pixel driving circuit. At least one of the sub-pixels is provided with a pixel opening, and the pixel openings of different color sub-pixels are different. Since the pixel openings of different color sub-pixels are different, the intrinsic capacitances of the light emitting devices EL of different color sub-pixels are also different.

[0157] The arrangement of the second capacitor C2 and the sixth transistor T6 in the present disclosure can avoid the use of the intrinsic capacitance (i.e. the parasitic capacitance) of the light emitting device EL, which can ensure that at least one pixel driving circuit in the display device is completely consistent. Therefore, the pixel design precision and the control gray scale precision of the display device using the pixel driving circuit provided by the embodiments of the present disclosure are high, and the pixel design precision and the control gray scale precision can be ensured even if the pixel openings of different sub-pixels are not the same.

[0158] In an exemplary embodiment, the voltage value of the signal of the constant voltage signal terminal V0 is constant. Exemplarily, the constant voltage signal terminal V0 can be the same signal terminal as one of the reference signal terminal REF, the initial signal terminal INIT, the first power supply terminal ELVDD and the second power supply terminal ELVSS, or the constant voltage signal terminal V0 can be different from any one of the reference signal terminal REF, the initial signal terminal INIT, the first power supply terminal ELVDD and the second power supply terminal ELVSS. When the constant voltage signal terminal V0 is different from any one of the reference signal terminal REF, the initial signal terminal INIT, the first power supply terminal ELVDD and the second power supply terminal ELVSS, the mutual influence of any one of the reference signal terminal REF, the initial signal terminal INIT, the first power supply terminal ELVDD and the second power supply terminal ELVSS caused by voltage drop and the like can be reduced, and the reliability of the pixel driving circuit can be improved.

[0159] According to the characteristic of the transistor, the transistor can be divided into an N-type transistor and a P-type transistor. When the transistor is a P-type transistor, the on voltage is a low voltage (for example, 0V, -5V, -10V or other suitable voltage), and the off voltage is a high voltage (for example, 5V, 10V or other suitable voltage). When the transistor is an N-type transistor, the on voltage is a high voltage (for example, 5V, 10V or other suitable voltage), and the off voltage is a low voltage (for example, 0V, -5V, -10V or other suitable voltage).

[0160] In an exemplary embodiment, the N-type transistor can be an oxide thin film transistor. The active layer of the oxide thin film transistor adopts an oxide semiconductor. The oxide thin film transistor has the advantages of low leakage current, uniform film formation, good transistor hysteresis characteristics and low manufacturing cost.

[0161] In an exemplary embodiment, the P-type transistor can be a low-temperature polysilicon transistor. The low-temperature polysilicon transistor has the advantages of high mobility and fast charging.

[0162] In an exemplary embodiment, in the pixel driving circuit provided in FIG. 12, the third transistor T3 can be an N-type transistor, and at least one of the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 can be an N-type transistor or a P-type transistor.

[0163] In an exemplary embodiment, in the pixel driving circuit provided in FIG. 13, the third transistor T3 can be an N-type transistor, and at least one of the first transistor T1, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 can be an N-type transistor or a P-type transistor.

[0164] In the example embodiment, when the pixel driving circuit includes P-type transistors and N-type transistors, i.e., low-temperature polysilicon transistors and oxide transistors are integrated on one display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate, the advantages of both can be utilized, low-frequency driving can be achieved, power consumption can be reduced, and display quality can be improved.

[0165] FIG. 14 is a driving timing diagram of the pixel driving circuit provided in FIG. 12. FIG. 14 is described by taking an example in which all the transistors in the pixel driving circuit are N-type transistors.

[0166] As shown in FIG. 14, in the example embodiment, the time during which the signal at the first scan signal terminal G1 is an effective level signal does not overlap with the time during which the signal at the second scan signal terminal G2 is an effective level signal and the time during which the signal at the third scan signal terminal G3 is an effective level signal, and the time during which the signal at the second scan signal terminal G2 is an effective level signal at least partially overlaps with the time during which the signal at the third scan signal terminal G3 is an effective level signal.

[0167] As shown in FIG. 14, in the example embodiment, the time during which the signal at the first emission signal terminal EM1 is an effective level signal at least partially overlaps with the time during which the signal at the second emission signal terminal EM2 is an effective level signal and the time during which the signal at the second scan signal terminal G2 is an effective level signal.

[0168] As shown in FIG. 14, in the example embodiment, the time during which the signal at the first emission signal terminal EM1 is an effective level signal includes a first time t1 and a second time t2, and the first time t1 occurs before the second time t2.

[0169] As shown in FIG. 14, in the example embodiment, the time during which the signal at the second emission signal terminal EM2 is an effective level signal includes a third time t3 and a fourth time t4, and the third time t3 occurs before the fourth time t4 and the third time t3 occurs before the first time t1.

[0170] As shown in FIG. 14, in the example embodiment, the second time t2 and the fourth time t4 at least partially overlap. For example, the second time t2 can coincide with the fourth time t4.

[0171] As shown in FIG. 14, in the example embodiment, the time during which the signal at the third scan signal terminal G3 is an effective level signal, the first time t1, and the third time t3 are located within the time during which the signal at the second scan signal terminal G2 is an effective level signal.

[0172] As shown in FIG. 14, the signal of the third scan signal terminal G3 is at least partially overlapped with the third time t3 and not overlapped with the first time t1. Exemplarily, the time when the signal of the third scan signal terminal G3 is at the active level can be within the third time t3.

[0173] As shown in FIG. 14, in the exemplary embodiment, the time when the signal of the first scan signal terminal G1 is at the active level is between the first time t1 and the second time t2.

[0174] In the exemplary embodiment, in the state that the first time lasts for K*H, the third scan signal terminal G3 connected to the nth row of pixel driving circuit is the same as the first scan signal terminal G1 connected to the nth+K+1 row of pixel driving circuit, H is the time for driving one row of pixel driving circuit, K is a positive integer greater than or equal to 1, n is a positive integer greater than or equal to 1 and less than M-K, and M is the total number of rows of pixel driving circuit. The third scan signal terminal G3 connected to the nth row of pixel driving circuit is the same as the first scan signal terminal G1 connected to the nth+K+1 row of pixel driving circuit, i.e., the signals of the third scan signal terminal G3 connected to the nth row of pixel driving circuit and the first scan signal terminal G1 connected to the nth+K+1 row of pixel driving circuit are the same. The time for compensation of the nth row of pixel driving circuit can be reserved to ensure the normal operation of the nth row of pixel driving circuit.

[0175] In the exemplary embodiment, the display device in which the pixel driving circuit is located further comprises at least one driving circuit located in the non-display area. Since the third scan signal terminal G3 connected to the nth row of pixel driving circuit can be the same as the first scan signal terminal G1 connected to the nth+K+1 row of pixel driving circuit, the driving circuit for providing the signal to the first scan signal terminal connected to the pixel driving circuit can be the same as the driving circuit for providing the signal to the third scan signal terminal connected to the driving circuit. The third scan signal terminal G3 connected to the nth row of pixel driving circuit being the same as the first scan signal terminal G1 connected to the nth+K+1 row of pixel driving circuit can reduce the number of driving circuits located in the non-display area, and thus the narrow frame of the display device can be achieved.

[0176] The working process of the pixel driving circuit exemplified by FIG. 12 is described below to illustrate the exemplary embodiments of the present disclosure. As shown in FIG. 14, the working process of the pixel driving circuit provided by FIG. 12 is as follows:

[0177] In the first stage P1, the signals of the first scan signal terminal G1 and the first light-emitting signal terminal EM1 are low level signals, and the signals of the second scan signal terminal G2, the third scan signal terminal G3 and the second light-emitting signal terminal EM2 are high level signals. The second transistor T2, the fourth transistor T4 and the sixth transistor T6 are turned on, and the first transistor T1 and the fifth transistor T5 are turned off.

[0178] The second transistor T2 is turned on, and the signal of the reference signal terminal REF is written to the first node N1, so that the first node N1 is initialized and the charge of the first node N1 is cleared. The fourth transistor T4 is turned on, and the signal of the initial signal terminal INIT is written to the second node N2, so that the second node N2 is initialized and the charge of the second node N2 is cleared. The third transistor T3 is turned on, and the second node N2 and the third node N3 are connected, so that the signal of the second node N2 is written to the third node N3 and the third node N3 is initialized. The sixth transistor T6 is turned on, so that the fourth node N4 and the third node N3 are connected, and the signal of the third node N3 is written to the fourth node N4 and the fourth node N4 is initialized.

[0179] In this stage, the voltage value of the signal of the first node N1 satisfies V N1 =Vref, the voltage value of the signal of the second node N2 satisfies V N2 =Vinit, the voltage value of the signal of the third node N3 satisfies V N3 =Vinit, and the voltage value of the signal of the fourth node N4 satisfies V N4 =Vinit, where Vref is the voltage value of the signal of the reference signal terminal REF, and Vinit is the voltage value of the signal of the initial signal terminal INIT.

[0180] In the second stage P2, the signals of the first scan signal terminal G1, the third scan signal terminal G3 and the second light-emitting signal terminal EM2 are low level signals, and the signals of the second scan signal terminal G2 and the first light-emitting signal terminal EM1 are high level signals. The second transistor T2 and the fifth transistor T5 are turned on, and the first transistor T1, the fourth transistor T4 and the sixth transistor T6 are turned off.

[0181] The second transistor T2 is turned on, and the signal of the reference signal terminal REF is continuously written to the first node N1, so that the first node N1 is initialized and the charge of the first node N1 is cleared. The fifth transistor T5 is turned on, and the signal of the first power supply terminal ELVDD is written to the third node N3 through the turned-on fifth transistor T5, the second node N2 and the turned-on third transistor T3, until the voltage value of the signal of the third node N3 satisfies V N3 =Vref-Vth. Since the sixth transistor T6 is turned off, the fourth node N4 keeps the signal of the previous stage.

[0182] In this phase, the voltage value of the signal of the first node N1 satisfies V N1 =Vref, the voltage value of the signal of the second node N2 satisfies V N2 =Vdd, the voltage value of the signal of the third node N3 satisfies V N3 =Vref-Vth, and the voltage value of the signal of the fourth node N4 satisfies V N4 =Vinit, wherein Vdd is the voltage value of the signal of the first power supply end ELVDD.

[0183] In the third phase P3, a data writing phase, the signal of the first scan signal end G1 is a high level signal, and the signals of the second scan signal end G2, the third scan signal end G3, the first light emitting signal end EM1 and the second light emitting signal end EM2 are low level signals. The first transistor T1 is turned on, and the second transistor T2, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 are turned off.

[0184] The turning on of the first transistor T1 causes the data voltage of the data signal end DATA to be written into the first node N1. Due to the jump of the signal of the first node N1, the signal of the third node N3 also jumps under the action of the first capacitor C1. The voltage value of the signal of the third node N3 satisfies V N3 =Vref-Vth+α(Vdata-Vref), 0<α<1, α=C1 / (C1+C2), C1 is the capacitance value of the first capacitor C1, and C2 is the capacitance value of the second capacitor C2.

[0185] In the fourth phase P4, a light emitting phase, the signals of the first light emitting signal end EM1 and the second light emitting signal end EM2 are high level signals, and the signals of the first scan signal end G1, the second scan signal end G2 and the third scan signal end G3 are low level signals. The fifth transistor T5 and the sixth transistor T6 are turned on, and the first transistor T1, the second transistor T2 and the fourth transistor T4 are turned off.

[0186] The turning on of the fifth transistor T5 and the sixth transistor T6 causes the power supply voltage output by the first power supply end ELVDD to provide a driving current to the first electrode of the light emitting device EL through the turned-on fifth transistor T5, the turned-on third transistor T3 and the turned-on sixth transistor T6, so as to drive the light emitting device EL to emit light.

[0187] In the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (a driving transistor) of each pixel driving circuit is determined by the voltage difference between the gate electrode and the second electrode thereof. Since the voltage of the signal of the first node N1 satisfies V N1 =Vdata, the voltage value of the signal of the third node N3 satisfies V N3 =Vref-Vth+α(Vdata-Vinit)

[0188] Thus the driving current I of the third transistor T3 is: I=K*(Vgs-Vth) 2 =K*[Vdata-Vref+Vth-α(Vdata-Vref)-Vth] 2 =K*[(1-α)(Vdata-Vref)] 2

[0189] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current of the light emitting device EL, K is a constant related to process and design, and Vgs is the voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0190] As can be seen from the derivation of the above current formula, in the light emitting stage, the driving current of the third transistor T3 of each pixel driving circuit is not affected by the threshold voltage of the third transistor T3, thereby eliminating the influence of the threshold voltage of the third transistor T3 on the driving current, and ensuring the uniformity of the display brightness of the display product and improving the display effect of the entire display product.

[0191] FIG. 15 is a driving timing diagram of the pixel driving circuit provided in FIG. 13. As shown in FIG. 15, the pixel driving circuit is taken as an example in which all the transistors are N-type transistors.

[0192] As shown in FIG. 15, in the exemplary embodiment, the time when the signal of the first scan signal terminal G1 is an effective level signal at least partially overlaps with the time when the signal of the third scan signal terminal G3 is an effective level signal, the time when the signal of the first emission signal terminal EM1 is an effective level signal and the time when the signal of the second emission signal terminal EM2 is an effective level signal.

[0193] As shown in FIG. 15, in the exemplary embodiment, the time when the signal of the third scan signal terminal G3 is an effective level signal at least partially overlaps with the time when the signal of the second emission signal terminal EM2 is an effective level signal.

[0194] As shown in FIG. 15, in the exemplary embodiment, the time when the signal of the first emission signal terminal EM1 is an effective level signal at least partially overlaps with the time when the signal of the second emission signal terminal EM2 is an effective level signal.

[0195] As shown in FIG. 15, in an exemplary embodiment, the time during which the signal of the first scan signal terminal G1 is an active level signal includes the fifth time t5, a plurality of interval arranged sixth times t6, and a seventh time t7, the time during which the signal of the first light emitting signal terminal EM1 is an active level signal includes an eighth time t8 and a plurality of interval arranged sixth times t6, and the time during which the signal of the second light emitting signal terminal EM2 is an active level signal is a ninth time t9 and a tenth time t10. The fifth time t5 occurs before the first sixth time t6 and there is an interval between the fifth time t5 and the first sixth time t6, the seventh time t7 occurs after the last sixth time t6 and there is an interval between the seventh time t7 and the last sixth time t6, the eighth time t8 and the tenth time t10 occur after the seventh time t7, and the ninth time t9 occurs before the tenth time t10.

[0196] As shown in FIG. 15, in an exemplary embodiment, the ninth time t9 at least partially overlaps with the fifth time t5. Exemplarily, the ninth time t9 coincides with the fifth time t5.

[0197] As shown in FIG. 15, in an exemplary embodiment, the eighth time t8 at least partially overlaps with the tenth time t10. Exemplarily, the eighth time t8 coincides with the tenth time t10.

[0198] As shown in FIG. 15, in an exemplary embodiment, the time during which the signal of the third scan signal terminal G3 is an active level signal at least partially overlaps with the fifth time t5 and the ninth time t9 respectively. Exemplarily, the time during which the signal of the third scan signal terminal G3 is an active level signal, at least two of the fifth time t5 and the ninth time t9 coincide.

[0199] As shown in FIG. 15, the signal of the control signal terminal CON is a reference signal at the fifth time t5, the sixth time t6, the time between the last sixth time t6 and the seventh time t7, at least part of the time of the eighth time t8, and at least part of the time of the tenth time t10, wherein the reference signal is the signal of the reference signal terminal REF.

[0200] As shown in FIG. 15, the signal of the control signal terminal CON is a data signal at the time between the fifth time t5 and the first sixth time t6, between adjacent sixth times t6, the seventh time t7, at least part of the time of the eighth time t8, and at least part of the time of the tenth time t10, wherein the data signal is the signal of the data signal terminal DATA.

[0201] The working process of the pixel driving circuit exemplified by FIG. 13 is described below. As shown in FIG. 15, the working process of the pixel driving circuit provided by FIG. 13 can include:

[0202] In the first stage S1, the signals of the first scan signal terminal G1, the third scan signal terminal G3 and the second emitting signal terminal EM2 are high level signals, the signal of the first emitting signal terminal EM1 is a low level signal, and the signal of the control signal terminal CON is written into the signal of the reference signal terminal. The first transistor T1, the fourth transistor T4 and the sixth transistor T6 are turned on, and the fifth transistor T5 is turned off.

[0203] The first transistor T1 is turned on, and the signal of the control signal terminal CON is written into the first node N1 to initialize the first node N1 and clear the charge of the first node N1. The fourth transistor T4 is turned on, and the signal of the initial signal terminal INIT is written into the second node N2 to initialize the second node N2 and clear the charge of the second node N2. The third transistor T3 is turned on, the second node N2 is connected with the third node N3, and the signal of the second node N2 is written into the third node N3 to initialize the third node N3. The sixth transistor T6 is turned on to make the fourth node N4 and the third node N3 communicate, and the signal of the third node N3 is written into the fourth node N4 to initialize the fourth node N4.

[0204] In this stage, the voltage value of the signal of the first node N1 satisfies V N1 =Vref, the voltage value of the signal of the second node N2 satisfies V N2 =Vinit, the voltage value of the signal of the third node N3 satisfies V N3 =Vinit, the voltage value of the signal of the fourth node N4 satisfies V N4 =Vinit, Vref is the voltage value of the signal of the reference signal terminal, and Vinit is the voltage value of the signal of the initial signal terminal INIT.

[0205] In the second stage S2, the signals of the second emitting signal terminal EM2 and the third scan signal terminal G3 are low level signals, and the fourth transistor T4 and the sixth transistor T6 are turned off.

[0206] The second stage S2 includes a plurality of first sub-stages S21 and a plurality of second sub-stages S22 which are alternately arranged, wherein the first first sub-stage occurs before the second sub-stage, and the last second sub-stage occurs after the last first sub-stage.

[0207] In the first sub-stage S21, the signals of the first scan signal terminal G1 and the first emitting signal terminal EM1 are low level signals, the signal of the control signal terminal CON is written into the signal of the data signal terminal, the first transistor T1 and the fifth transistor T5 are turned off, and the first node N1, the second node N2, the third node N3 and the fourth node N4 keep the signals of the last stage.

[0208] In this stage, the voltage value of the signal of the first node N1 satisfies V N1= Vref, the voltage value of the signal of the second node N2 satisfies V N2 = Vinit, the voltage value of the signal of the third node N3 satisfies V N3 = Vinit, the voltage value of the signal of the fourth node N4 satisfies V N4 = Vinit.

[0209] In the second sub-stage S22, the signals of the first scan signal terminal G1 and the first light-emitting signal terminal EM1 are high level signals, and the control signal terminal CON writes the signal of the reference signal terminal. The first transistor T1 and the fifth transistor T5 are turned on, and the fourth transistor T4 and the sixth transistor T6 are turned off.

[0210] The first transistor T1 is turned on, and the signal of the control signal terminal CON continuously writes the first node N1, so that the first node N1 is initialized and the charge of the first node N1 is cleared. The fifth transistor T5 is turned on, and the signal of the first power supply terminal ELVDD is written to the third node N3 through the turned-on fifth transistor T5, the second node N2 and the turned-on third transistor T3, until the voltage value of the signal of the third node N3 satisfies V N3 = Vref-Vth. Since the sixth transistor T6 is turned off, the fourth node N4 keeps the signal of the last stage.

[0211] In this stage, the voltage value of the signal of the first node N1 satisfies V N1 = Vref, the voltage value of the signal of the second node N2 satisfies V N2 = Vdd, the voltage value of the signal of the third node N3 V N3 = Vref-Vth, the voltage value of the signal of the fourth node N4 satisfies V N4 = Vinit, wherein Vdd is the voltage value of the signal of the first power supply terminal ELVDD.

[0212] In the third stage S3, the data writing stage, the signal of the first scan signal terminal G1 is a high level signal, the signals of the third scan signal terminal G3, the first light-emitting signal terminal EM1 and the second light-emitting signal terminal EM2 are low level signals, and the control signal terminal CON writes the data voltage of the signal of the data signal terminal. The first transistor T1 is turned on, and the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 are turned off.

[0213] The first transistor T1 is turned on, so that the data voltage of the control signal terminal CON is written to the first node N1. Since the signal of the first node N1 jumps, the signal of the third node N3 also jumps under the action of the first capacitor C1, and the voltage value of the signal of the third node N3 satisfies V N3= Vref - Vth + a (Vdata - Vref), 0 < a < 1, a = C1 / (C1+C2), C1 is a capacitance value of the first capacitor C1, and C2 is a capacitance value of the second capacitor C2.

[0214] In the fourth stage S4, the light emitting stage, the signals of the first light emitting signal terminal EM1 and the second light emitting signal terminal EM2 are high level signals, and the signals of the first scanning signal terminal G1 and the third scanning signal terminal G3 are low level signals. The fifth transistor T5 and the sixth transistor T6 are turned on, and the first transistor T1, the second transistor T2 and the fourth transistor T4 are turned off.

[0215] The turning on of the fifth transistor T5 and the sixth transistor T6 makes the power voltage outputted by the first power supply terminal ELVDD provide a driving current to the first electrode of the light emitting device EL through the turned-on fifth transistor T5, the turned-on third transistor T3 and the turned-on sixth transistor T6, so as to drive the light emitting device EL to emit light.

[0216] In the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (the driving transistor) of each pixel driving circuit is determined by the voltage difference between the gate electrode and the second electrode thereof. Since the voltage of the signal of the first node N1 satisfies V N1 = Vdata, and the voltage value of the signal of the third node N3 satisfies V N3 = Vref - Vth + a (Vdata - Vinit)

[0217] Thus, the driving current I of the third transistor T3 is: I = K*(Vgs-Vth) 2 = K*[Vdata-Vref+Vth- a (Vdata-Vref)-Vth] 2 = K*[(1-a)(Vdata-Vref)] 2

[0218] wherein I is the driving current flowing through the third transistor T3, that is, the driving current driving the light emitting device EL, K is a constant related to the process and design, and Vgs is the voltage difference between the gate electrode and the second electrode of the third transistor T3.

[0219] It can be seen from the derivation of the above current formula that, in the light emitting stage, the driving current of the third transistor T3 of each pixel driving circuit is not affected by the threshold voltage of the third transistor T3, thereby eliminating the influence of the threshold voltage of the third transistor T3 on the driving current, and ensuring the uniformity of the display brightness of the display product and improving the display effect of the entire display product.

[0220] The time when the fifth time t5 and the ninth time t9 overlap is the time when the first stage S1 is located, the sixth time t6 is the time when the second sub-stage S22 is located, the seventh time t7 is the time when the third stage S3 is located, and the time when the eighth time t8 and the tenth time t10 overlap is the time when the fourth stage S4 is located.

[0221] According to the working process of the pixel driving circuit provided according to FIGS. 12-13, it can be known that the compensation stage in the pixel driving circuit provided by the embodiment of the present disclosure is independent of the data writing stage, and the duration of the compensation stage depends on the duration of the first emission signal end EM1 being an effective level signal. The longer the duration of the first emission signal end EM1 being an effective level signal, the longer the compensation time of the pixel driving circuit. In addition, the driving current of the pixel driving circuit provided by the present disclosure is independent of the threshold voltage and mobility of the driving transistor, that is, the compensation time of the pixel driving circuit provided by the present disclosure can not be limited by the data writing time, resolution, and mobility and threshold voltage of the transistor, thereby improving the application range of the pixel driving circuit and the brightness uniformity of the display substrate where the pixel driving circuit is located.

[0222] The embodiment of the present disclosure also provides a driving method of a pixel driving circuit, configured to drive the pixel driving circuit provided by any one of the preceding embodiments. The driving method of the pixel driving circuit can include the following steps:

[0223] In step 100, the first control sub-circuit provides a signal to the first node under the control of signals at the at least one scan signal end, the at least one input signal end, and the third node.

[0224] In step 200, the second control sub-circuit provides a signal of the first power supply end to the second node and a signal of the third node to the fourth node under the control of signals at the first emission signal end and the second emission signal end.

[0225] In step 300, the third control sub-circuit provides a signal of the initial signal end INIT to the second node 4 under the control of a signal at the third scan signal end 4.

[0226] In step 400, the driving sub-circuit provides a driving signal to the third node under the control of signals at the first node and the second node.

[0227] The embodiment of the present disclosure also provides a display device, which includes the pixel driving circuit of any one of the preceding embodiments.

[0228] In an exemplary embodiment, when the at least one scan signal terminal includes a first scan signal terminal and a second scan signal terminal, the display device further includes a first data unit, a second data unit, a third data unit, a fourth data unit, and a fifth data unit, the first data unit is electrically connected to the first scan signal terminal and configured to provide a signal to the first scan signal terminal, the second data unit is electrically connected to the second scan signal terminal and configured to provide a signal to the second scan signal terminal, the third data unit is electrically connected to the third scan signal terminal and configured to provide a signal to the third scan signal terminal, the fourth data unit is electrically connected to the first light-emitting signal terminal and configured to provide a signal to the first light-emitting signal terminal, and the fifth data unit is electrically connected to the second light-emitting signal terminal and configured to provide a signal to the second light-emitting signal terminal.

[0229] In an exemplary embodiment, when the at least one scan signal terminal includes a first scan signal terminal and a second scan signal terminal, a time at which the first data unit provides an active level signal to the first scan signal terminal does not overlap with a time at which the second data unit provides an active level signal to the second scan signal terminal and a time at which the third data unit provides an active level signal to the third scan signal terminal, and a time at which the second data unit provides an active level signal to the second scan signal terminal at least partially overlaps with a time at which the third data unit provides an active level signal to the third scan signal terminal.

[0230] In an exemplary embodiment, when the at least one scan signal terminal includes a first scan signal terminal and a second scan signal terminal, at least part of a time at which the fourth data unit provides an active level signal to the first light-emitting signal terminal and at least part of a time at which the fifth data unit provides an active level signal to the second light-emitting signal terminal respectively at least partially overlap with a time at which the second data unit provides an active level signal to the second scan signal terminal.

[0231] In an exemplary embodiment, when the at least one scan signal terminal includes a first scan signal terminal and a second scan signal terminal, a time at which the fourth data unit provides an active level signal to the first light-emitting signal terminal includes a first time and a second time, and a time at which the fifth data unit provides an active level signal to the second light-emitting signal terminal includes a third time and a fourth time, wherein the first time occurs before the second time, the third time occurs before the fourth time, the third time occurs before the first time, and the second time and the fourth time at least partially overlap.

[0232] In the example embodiment, when the at least one scan signal terminal includes a first scan signal terminal and a second scan signal terminal, the third data unit provides the active level signal to the third scan signal terminal at a time that is at least partially overlapped with the time at which the second data unit provides the active level signal to the second scan signal terminal.

[0233] In the example embodiment, when the at least one scan signal terminal includes a first scan signal terminal and a second scan signal terminal, the first data unit provides the active level signal to the first scan signal terminal at a time that is between the first time and the second time.

[0234] In the example embodiment, when the first time lasts for K*H, the third scan signal terminal connected to the nth row of pixel driving circuits is the same as the first scan signal terminal connected to the nth+K+1 row of pixel driving circuits, H is the time for driving one row of pixel driving circuits, K is a positive integer greater than or equal to 1, n is a positive integer greater than or equal to 1 and less than M-K, and M is the total number of rows of pixel driving circuits.

[0235] In the example embodiment, when the at least one scan signal terminal includes a first scan signal terminal, the display device further includes a first data unit, a third data unit, a fourth data unit, a fifth data unit, and a sixth data unit. The first data unit is electrically connected to the first scan signal terminal and is configured to provide a signal to the first scan signal terminal. The third data unit is electrically connected to the third scan signal terminal and is configured to provide a signal to the third scan signal terminal. The fourth data unit is electrically connected to the first light-emitting signal terminal and is configured to provide a signal to the first light-emitting signal terminal. The fifth data unit is electrically connected to the second light-emitting signal terminal and is configured to provide a signal to the second light-emitting signal terminal. The sixth data unit is electrically connected to the control signal terminal and is configured to provide a signal to the control signal terminal.

[0236] In the example embodiment, when the at least one scan signal terminal includes a first scan signal terminal, the time at which the first data unit provides the active level signal to the first scan signal terminal is at least partially overlapped with the time at which the third data unit provides the active level signal to the third scan signal terminal, the time at which the fourth data unit provides the active level signal to the first light-emitting signal terminal, and the time at which the fifth data unit provides the active level signal to the second light-emitting signal terminal. The time at which the third data unit provides the active level signal to the third scan signal terminal is at least partially overlapped with the time at which the fifth data unit provides the active level signal to the second light-emitting signal terminal. The time at which the fourth data unit provides the active level signal to the first light-emitting signal terminal is not overlapped with the time at which the fifth data unit provides the active level signal to the second light-emitting signal terminal.

[0237] In the example embodiment, when the at least one scan signal terminal comprises a first scan signal terminal, the time at which the first data unit provides the active level signal to the first scan signal terminal comprises a fifth time, a sixth time arranged at intervals, and a seventh time, the time at which the fourth data unit provides the active level signal to the first light emitting signal terminal comprises an eighth time and a sixth time arranged at intervals, the time at which the fifth data unit provides the active level signal to the second light emitting signal terminal comprises a ninth time and a tenth time, the fifth time occurs before the first sixth time and is separated from the first sixth time by an interval, the seventh time occurs after the last sixth time and is separated from the last sixth time by an interval, the eighth time and the tenth time occur after the seventh time, and the ninth time occurs before the tenth time.

[0238] In the example embodiment, when the at least one scan signal terminal comprises a first scan signal terminal, the ninth time at least partially overlaps the fifth time, the eighth time at least partially overlaps the tenth time, and the time at which the third data unit provides the active level signal to the third scan signal terminal at least partially overlaps the fifth time and the ninth time, respectively.

[0239] In the example embodiment, when the at least one scan signal terminal comprises a first scan signal terminal, the sixth data unit is configured to provide a reference signal to the control signal terminal at the fifth time, the sixth time, a time between the last sixth time and the seventh time, a portion of the time at the eighth time, and a portion of the time at the tenth time, and to provide a data signal to the control signal terminal at a time between the fifth time and the first sixth time, between adjacent sixth times, the seventh time, at least a portion of the time at the eighth time, and at least a portion of the time at the tenth time, wherein the reference signal is a signal of the reference signal terminal and the data signal is a signal of the data signal terminal.

[0240] In the example embodiment, when the pixel driving circuit is electrically connected to the first scan signal terminal, the second scan signal terminal, the third scan signal terminal, the reference signal terminal, the initial signal terminal, and the data signal terminal, respectively, the first scan signal terminals connected to the pixel driving circuits in the same row are connected to the same signal line, the second scan signal terminals connected to the pixel driving circuits in the same row are connected to the same signal line, the third scan signal terminals connected to the pixel driving circuits in the same row are connected to the same signal line, the reference signal terminals connected to the pixel driving circuits in the same row are connected to the same signal line, the initial signal terminals connected to the pixel driving circuits in the same row are connected to the same signal line, the data signal terminals connected to different pixel driving circuits in the same row are connected to different signal lines, and the data signal terminals connected to the pixel driving circuits in the same column are connected to the same signal line.

[0241] In an example embodiment, when the pixel driving circuit is electrically connected with the first scan signal end, the second scan signal end, the third scan signal end, the reference signal end, the initial signal end and the data signal end respectively, the display device can comprise: a plurality of pixel driving circuit groups, the plurality of pixel driving circuit groups comprising: at least two pixel driving circuits located in at least one row. The first scan signal ends connected by the pixel driving circuits located in the same pixel driving circuit group are connected with the same signal line, the second scan signal ends connected by the pixel driving circuits located in the same pixel driving circuit group are connected with the same signal line, the third scan signal ends connected by the pixel driving circuits located in the same pixel driving circuit group are connected with the same signal line, the reference signal ends connected by the pixel driving circuits located in the same pixel driving circuit group are connected with the same signal line, and the initial signal ends connected by the pixel driving circuits located in the same pixel driving circuit group are connected with the same signal line.

[0242] In an example embodiment, when the pixel driving circuit is electrically connected with the first scan signal end, the third scan signal end, the control signal end and the initial signal end respectively, the first scan signal ends connected by the pixel driving circuits located in the same row are connected with the same signal line, the third scan signal ends connected by the pixel driving circuits located in the same row are connected with the same signal line, the initial signal ends connected by the pixel driving circuits located in the same row are connected with the same signal line, the control signal ends connected by the pixel driving circuits located in the same column are connected with the same signal line, and the control signal ends connected by the pixel driving circuits located in different rows are connected with different signal lines.

[0243] In an example embodiment, when the pixel driving circuit is electrically connected with the first scan signal end, the third scan signal end, the control signal end and the initial signal end respectively, the display device comprises: a plurality of pixel driving circuit groups, the plurality of pixel driving circuit groups comprising: at least two pixel driving circuits located in at least one row. The first scan signal ends connected by the pixel driving circuits located in the same pixel driving circuit group are connected with the same signal line, the third scan signal ends connected by the pixel driving circuits located in the same pixel driving circuit group are connected with the same signal line, and the initial signal ends connected by the pixel driving circuits located in the same pixel driving circuit group are connected with the same signal line.

[0244] In an example embodiment, the plurality of pixel driving circuits in one pixel driving circuit group can be located in the same row, and can also be located in at least two rows, and the present disclosure does not make any limitation in this regard.

[0245] Fig. 16 is an equivalent circuit diagram of a pixel driving circuit group, Fig. 17 is an equivalent circuit diagram of a pixel driving circuit group, Fig. 18 is an equivalent circuit diagram of a pixel driving circuit group. Fig. 19 is an equivalent circuit diagram of a pixel driving circuit group, Fig. 20 is an equivalent circuit diagram of a pixel driving circuit group, Fig. 21 is an equivalent circuit diagram of a pixel driving circuit group. As shown in Figs. 16 to 21, T1(i) is a first transistor in the i-th pixel driving circuit in a pixel driving circuit group, T2(i) is a second transistor in the i-th pixel driving circuit in a pixel driving circuit group, T3(i) is a third transistor in the i-th pixel driving circuit in a pixel driving circuit group, T4(i) is a fourth transistor in the i-th pixel driving circuit in a pixel driving circuit group, T5(i) is a first transistor in the i-th pixel driving circuit in a pixel driving circuit group, T6(i) is a sixth transistor in the i-th pixel driving circuit in a pixel driving circuit group, C1(i) is a first capacitor in the i-th pixel driving circuit in a pixel driving circuit group, C2(i) is a second capacitor in the i-th pixel driving circuit in a pixel driving circuit group, EL(i) is a light emitting device connected to the i-th pixel driving circuit in a pixel driving circuit group. As shown in Figs. 16 to 18, DATA(i) is a data signal terminal connected to the i-th pixel driving circuit in a pixel driving circuit group. As shown in Figs. 19 to 21, CON(i) is a control signal terminal connected to the i-th pixel driving circuit in a pixel driving circuit group. Wherein, i is a positive integer greater than or equal to 1 and less than or equal to N, N is the number of pixel driving circuits included in a pixel driving circuit group

[0246] As shown in FIGS. 16-18, in exemplary embodiments, the display device further comprises a plurality of signal lines. When the pixel driving circuit is electrically connected with the first scan signal terminal G1, the second scan signal terminal G2, the third scan signal terminal G3, the reference signal terminal REF, the initial signal terminal INIT and the data signal terminal DATA respectively, the fourth transistor T4 in at least two pixel driving circuits in the same pixel driving circuit group is the same transistor, or the fifth transistor T5 in at least two pixel driving circuits in the same pixel driving circuit group is the same transistor, or the fourth transistor T4 in at least two pixel driving circuits in the same pixel driving circuit group is the same transistor and the fifth transistor T5 in at least two pixel driving circuits in the same pixel driving circuit group is the same transistor. FIG. 16 is an example of the fourth transistor T4 in at least two pixel driving circuits in the same pixel driving circuit group being the same transistor. FIG. 17 is an example of the fifth transistor T5 in at least two pixel driving circuits in the same pixel driving circuit group being the same transistor. FIG. 18 is an example of the fourth transistor T4 in at least two pixel driving circuits in the same pixel driving circuit group being the same transistor and the fifth transistor T5 in at least two pixel driving circuits in the same pixel driving circuit group being the same transistor. FIGS. 16-18 are examples of N pixel driving circuits in the same row being a pixel driving circuit group.

[0247] As shown in FIGS. 19-21, in an exemplary embodiment, the display device can further include a plurality of signal lines; when the pixel driving circuits are electrically connected to the first scan signal terminal G1, the third scan signal terminal G3, the initial signal terminal INIT and the control signal terminal CON respectively, the fourth transistor T4 in at least two pixel driving circuits in the same pixel driving circuit group is the same transistor, or the fifth transistor T5 in at least two pixel driving circuits in the same pixel driving circuit group is the same transistor, or the fourth transistor T4 in at least two pixel driving circuits in the same pixel driving circuit group is the same transistor and the fifth transistor T5 in at least two pixel driving circuits in the same pixel driving circuit group is the same transistor. FIG. 19 illustrates an example in which the fourth transistor T4 in at least two pixel driving circuits in the same pixel driving circuit group is the same transistor. FIG. 20 illustrates an example in which the fifth transistor T5 in at least two pixel driving circuits in the same pixel driving circuit group is the same transistor. FIG. 21 illustrates an example in which the fourth transistor T4 in at least two pixel driving circuits in the same pixel driving circuit group is the same transistor and the fifth transistor T5 in at least two pixel driving circuits in the same pixel driving circuit group is the same transistor. FIGS. 19-21 illustrate an example in which N pixel driving circuits in the same row form a pixel driving circuit group.

[0248] In an exemplary embodiment, the fourth transistor T4 in at least two pixel driving circuits in the same pixel driving circuit group is the same transistor, or the fifth transistor T5 in at least two pixel driving circuits in the same pixel driving circuit group is the same transistor, or the fourth transistor T4 in at least two pixel driving circuits in the same pixel driving circuit group is the same transistor and the fifth transistor T5 in at least two pixel driving circuits in the same pixel driving circuit group is the same transistor, which can simplify the structure of the pixel driving circuit group in the display area in the display device, reduce the area occupied by the pixel driving circuit group, and achieve high PPI.

[0249] In an exemplary embodiment, the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, etc., and the present application is not limited thereto.

[0250] The drawings of the present application only involve the structures involved in the present application, and other structures can be referred to the general design.

[0251] For clarity, in the drawings used to describe the embodiments of the disclosure, the thickness and size of layers or microstructures are exaggerated. It can be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, it can be "directly" on or under the other element, or an intervening element can also be present.

[0252] Although the embodiments disclosed by the present disclosure are as above, the content described is only the embodiments adopted for the convenience of understanding the present disclosure, and is not intended to limit the present disclosure. Any person skilled in the art of the present disclosure can make any modification and change in the form and details without departing from the spirit and scope of the present disclosure, but the patent protection scope of the present disclosure shall be subject to the scope defined by the appended claims.

Claims

1. A pixel driving circuit, comprising: a driving subcircuit, a first control subcircuit, a second control subcircuit, and a third control subcircuit; The first control subcircuit is electrically connected to the at least one scan signal terminal, the at least one input signal terminal, the first node, and the third node, respectively, and is configured to provide a signal to the first node under the control of the signals of the at least one scan signal terminal, the at least one input signal terminal, and the third node; The second control subcircuit is electrically connected to the first light-emitting signal terminal, the second light-emitting signal terminal, the first power supply terminal, the second node, the third node, and the fourth node, respectively, and is configured to provide a signal from the first power supply terminal to the second node and a signal from the third node to the fourth node under the control of signals from the first light-emitting signal terminal and the second light-emitting signal terminal; The third control subcircuit is electrically connected to the third scan signal terminal, the second node and the initial signal terminal respectively, and is configured to provide the signal of the initial signal terminal to the second node under the control of the signal of the third scan signal terminal; The driving sub-circuit is electrically connected to the first node, the second node and the third node respectively, and is configured to provide a driving signal to the third node under the control of signals of the first node and the second node.

2. The pixel driving circuit according to claim 1, wherein: At least one scanning signal terminal includes: a first scanning signal terminal and a second scanning signal terminal, and at least one input signal terminal includes: a data signal terminal and a reference signal terminal; The first control subcircuit is configured to provide a signal from the data signal terminal or the reference signal terminal to the first node under the control of the signals from the first scan signal terminal and the second scan signal terminal, and store a voltage difference between the signals from the first node and the third node.

3. The pixel driving circuit according to claim 2, wherein: The first control subcircuit includes: a data writing subcircuit, an initialization subcircuit and a first storage subcircuit; The data writing sub-circuit is electrically connected to the first scan signal terminal, the data signal terminal and the first node respectively, and is configured to provide the signal of the data signal terminal to the first node under the control of the signal of the first scan signal terminal; The initialization sub-circuit is electrically connected to the second scan signal terminal, the reference signal terminal and the first node respectively, and is configured to provide the signal of the reference signal terminal to the first node under the control of the signal of the second scan signal terminal; The first storage sub-circuit is electrically connected to the first node and the third node, respectively, and is configured to store a voltage difference between signals at the first node and the third node.

4. The pixel driving circuit according to claim 3, wherein: The data writing sub-circuit includes: a first transistor, the initialization sub-circuit includes: a second transistor, and the first storage sub-circuit includes: a first capacitor; The control electrode of the first transistor is electrically connected to the first scan signal terminal, the first electrode of the first transistor is electrically connected to the data signal terminal, and the second electrode of the first transistor is electrically connected to the first node; The control electrode of the second transistor is electrically connected to the second scan signal terminal, the first electrode of the second transistor is electrically connected to the reference signal terminal, and the second electrode of the second transistor is electrically connected to the first node; A first end of the first capacitor is electrically connected to the first node, and a second end of the first capacitor is electrically connected to the third node.

5. The pixel driving circuit according to claim 1, wherein: The at least one scanning signal terminal includes: a first scanning signal terminal, the at least one input signal terminal includes: a control signal terminal, the control signal terminal is a data signal terminal at least part of the time, and is a reference signal terminal at least part of the time; The first control subcircuit is configured to provide a signal from the control signal terminal to the first node under the control of a signal from the first scan signal terminal, and store a voltage difference between signals at the first node and a third node.

6. The pixel driving circuit according to claim 5, wherein: The first control subcircuit includes: a node control subcircuit and a first storage subcircuit; The node control subcircuit is electrically connected to the first scan signal terminal, the control signal terminal and the first node respectively, and is configured to provide a signal from the control signal terminal to the first node under the control of a signal from the first scan signal terminal; The first storage sub-circuit is electrically connected to the first node and the third node, respectively, and is configured to store a voltage difference between signals at the first node and the third node.

7. The pixel driving circuit according to claim 6, wherein: The node control subcircuit includes: a first transistor, and the first storage subcircuit includes: a first capacitor; The control electrode of the first transistor is electrically connected to the first scan signal terminal, the first electrode of the first transistor is electrically connected to the control signal terminal, and the second electrode of the first transistor is electrically connected to the first node; A first end of the first capacitor is electrically connected to the first node, and a second end of the capacitor is electrically connected to the third node.

8. The pixel driving circuit according to claim 3 or 6, wherein: The first control subcircuit is also electrically connected to the constant voltage signal terminal, and the first control subcircuit further includes: a second storage subcircuit; Therefore, the second storage sub-circuit is electrically connected to the constant voltage signal terminal and the third node, respectively, and is configured to store the voltage difference between the constant voltage signal terminal and the signal of the third node.

9. The pixel driving circuit according to claim 8, wherein: The second storage sub-circuit includes: a second capacitor; A first end of the second capacitor is electrically connected to the constant voltage signal end, and a second end of the second capacitor is electrically connected to the third node.

10. The pixel driving circuit according to claim 1, wherein: The driving sub-circuit includes: a third transistor, and the second control sub-circuit includes: a fifth transistor and a sixth transistor; The control electrode of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the third node; The control electrode of the fifth transistor is electrically connected to the first light emitting signal terminal, the first electrode of the fifth transistor is electrically connected to the first power supply terminal, and the second electrode of the fifth transistor is electrically connected to the second node; The control electrode of the sixth transistor is electrically connected to the second light emitting signal terminal, the first electrode of the sixth transistor is electrically connected to the third node, and the second electrode of the sixth transistor is electrically connected to the fourth node.

11. The pixel driving circuit according to claim 1, wherein: The third control subcircuit includes: a fourth transistor; The control electrode of the fourth transistor is electrically connected to the third scan signal terminal, the first electrode of the fourth transistor is electrically connected to the initial signal terminal, and the second electrode of the fourth transistor is electrically connected to the second node.

12. The pixel driving circuit according to claim 2, wherein: The first control subcircuit includes: a first transistor, a second transistor and a first capacitor, or includes: a first transistor, a second transistor, a first capacitor and a second capacitor, the second control subcircuit includes: a fifth transistor and a sixth transistor, the third control subcircuit includes: a fourth transistor, and the driving transistor includes: a third transistor; The control electrode of the first transistor is electrically connected to the first scan signal terminal, the first electrode of the first transistor is electrically connected to the data signal terminal, and the second electrode of the first transistor is electrically connected to the first node; The control electrode of the second transistor is electrically connected to the second scan signal terminal, the first electrode of the second transistor is electrically connected to the reference signal terminal, and the second electrode of the second transistor is electrically connected to the first node; The control electrode of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the second node, and the The second electrodes of the three transistors are electrically connected to the third node; The control electrode of the fourth transistor is electrically connected to the third scan signal terminal, the first electrode of the fourth transistor is electrically connected to the initial signal terminal, and the second electrode of the fourth transistor is electrically connected to the second node; The control electrode of the fifth transistor is electrically connected to the first light emitting signal terminal, the first electrode of the fifth transistor is electrically connected to the first power supply terminal, and the second electrode of the fifth transistor is electrically connected to the second node; The control electrode of the sixth transistor is electrically connected to the second light emitting signal terminal, the first electrode of the sixth transistor is electrically connected to the third node, and the second electrode of the sixth transistor is electrically connected to the fourth node; A first end of the first capacitor is electrically connected to the first node, and a second end of the first capacitor is electrically connected to the third node; A first end of the second capacitor is electrically connected to the constant voltage signal end, and a second end of the second capacitor is electrically connected to the third node.

13. The pixel driving circuit according to claim 5, wherein: The first control subcircuit includes: a first transistor and a first capacitor, or includes: a first transistor, a first capacitor and a second capacitor, the second control subcircuit includes: a fifth transistor and a sixth transistor, the third control subcircuit includes: a fourth transistor, and the driving transistor includes: a third transistor; The control electrode of the first transistor is electrically connected to the first scan signal terminal, the first electrode of the first transistor is electrically connected to the control signal terminal, and the second electrode of the first transistor is electrically connected to the first node; The control electrode of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the third node; The control electrode of the fourth transistor is electrically connected to the third scan signal terminal, the first electrode of the fourth transistor is electrically connected to the initial signal terminal, and the second electrode of the fourth transistor is electrically connected to the second node; The control electrode of the fifth transistor is electrically connected to the first light emitting signal terminal, the first electrode of the fifth transistor is electrically connected to the first power supply terminal, and the second electrode of the fifth transistor is electrically connected to the second node; The control electrode of the sixth transistor is electrically connected to the second light emitting signal terminal, the first electrode of the sixth transistor is electrically connected to the third node, and the second electrode of the sixth transistor is electrically connected to the fourth node; A first end of the first capacitor is electrically connected to the first node, and a second end of the first capacitor is electrically connected to the third node; A first end of the second capacitor is electrically connected to the constant voltage signal end, and a second end of the second capacitor is electrically connected to the third node.

14. The pixel driving circuit according to claim 8, wherein: The pixel driving circuit is electrically connected to the light emitting device, and the light emitting device is electrically connected to the fourth node and the second power supply terminal respectively; The constant voltage signal terminal is the same signal terminal as one of the reference signal terminal, the initial signal terminal, the first power terminal, and the second power terminal.

15. A display device comprising: The pixel driving circuit according to any one of claims 1 to 14 is arranged in an array.

16. The display device according to claim 15, wherein At least one scanning signal terminal includes: a first scanning signal terminal and a second scanning signal terminal; The display device further includes: a first data unit, a second data unit, a third data unit, a fourth data unit, and a fifth data unit, wherein the first data unit is electrically connected to the first scan signal terminal and configured to provide a signal to the first scan signal terminal, the second data unit is electrically connected to the second scan signal terminal and configured to provide a signal to the second scan signal terminal, the third data unit is electrically connected to the third scan signal terminal and configured to provide a signal to the third scan signal terminal, the fourth data unit is electrically connected to the first light-emitting signal terminal and configured to provide a signal to the first light-emitting signal terminal, and the fifth data unit is electrically connected to the second light-emitting signal terminal and configured to provide a signal to the second light-emitting signal terminal; The time when the first data unit provides the valid level signal to the first scan signal terminal does not overlap with the time when the second data unit provides the valid level signal to the second scan signal terminal and the time when the third data unit provides the valid level signal to the third scan signal terminal, and the time when the second data unit provides the valid level signal to the second scan signal terminal at least partially overlaps with the time when the third data unit provides the valid level signal to the third scan signal terminal; At least part of the time when the fourth data unit provides a valid level signal to the first light-emitting signal terminal and at least part of the time when the fifth data unit provides a valid level signal to the second light-emitting signal terminal overlap at least partly with the time when the second data unit provides a valid level signal to the second scan signal terminal.

17. The display device according to claim 16, wherein: The time when the fourth data unit provides a valid level signal to the first light signal terminal includes: a first time and a second time, and the time when the fifth data unit provides a valid level signal to the second light signal terminal includes: a third time and a fourth time; The first time occurs before the second time, the third time occurs before the fourth time, the third time occurs before the first time, and the second time and the fourth time at least partially overlap; The time when the third data unit provides the valid level signal to the third scanning signal terminal, the first time, and the third time are respectively located within the time when the second data unit provides the valid level signal to the second scanning signal terminal, and the time when the third data unit provides the valid level signal to the third scanning signal terminal at least partially overlaps with the third time and does not overlap with the first time; The time when the first data unit provides the effective level signal to the first scanning signal terminal is between the first time and the second time.

18. The display device according to claim 17, wherein: When the first time lasts for a duration of K*H, the third scanning signal terminal connected to the pixel driving circuit of the nth row and the first scanning signal terminal connected to the pixel driving circuit of the (n+K+1)th row are the same signal terminal, H is the time for driving a row of pixel driving circuits, K is a positive integer greater than or equal to 1, n is a positive integer greater than or equal to 1 and less than MK, and M is the total number of rows of pixel driving circuits.

19. The display device according to claim 15, wherein: The at least one scanning signal terminal includes: a first scanning signal terminal; The display device further includes: a first data unit, a third data unit, a fourth data unit, and a fifth data unit, wherein the first data unit is electrically connected to the first scan signal terminal and configured to provide a signal to the first scan signal terminal, the third data unit is electrically connected to the third scan signal terminal and configured to provide a signal to the third scan signal terminal, the fourth data unit is electrically connected to the first light-emitting signal terminal and configured to provide a signal to the first light-emitting signal terminal, and the fifth data unit is electrically connected to the second light-emitting signal terminal and configured to provide a signal to the second light-emitting signal terminal; The time when the first data unit provides a valid level signal to the first scan signal terminal overlaps at least partially with the time when the third data unit provides a valid level signal to the third scan signal terminal, the time when the fourth data unit provides a valid level signal to the first light-emitting signal terminal, and the time when the fifth data unit provides a valid level signal to the second light-emitting signal terminal; the time when the third data unit provides a valid level signal to the third scan signal terminal overlaps at least partially with the time when the fifth data unit provides a valid level signal to the second light-emitting signal terminal, and at least part of the time when the fourth data unit provides a valid level signal to the first light-emitting signal terminal does not overlap with at least part of the time when the fifth data unit provides a valid level signal to the second light-emitting signal terminal.

20. The display device according to claim 19, wherein The time when the first data unit provides a valid level signal to the first scanning signal terminal includes: a fifth time, a sixth time set at multiple intervals, and a seventh time. The time when the fourth data unit provides a valid level signal to the first light-emitting signal terminal includes: an eighth time and a sixth time set at multiple intervals. The time when the fifth data unit provides a valid level signal to the second light-emitting signal terminal is a ninth time and a tenth time. The fifth time occurs before the first sixth time and there is a gap between the fifth time and the first sixth time; the seventh time occurs after the last sixth time and there is a gap between the seventh time and the last sixth time; the eighth time and the tenth time occur after the seventh time; and the ninth time occurs before the tenth time; The ninth time at least partially overlaps with the fifth time, the eighth time at least partially overlaps with the tenth time, and the time when the third data unit provides the valid level signal to the third scan signal terminal at least partially overlaps with the fifth time and the ninth time respectively.

21. The display device according to claim 20, further comprising: a sixth data unit, the sixth data unit being electrically connected to the control signal terminal and configured to provide a signal to the control signal terminal; The sixth data unit is configured to provide a reference signal to the control signal terminal at the fifth time, the sixth time, the time between the last sixth time and the seventh time, part of the eighth time, and part of the tenth time, and to provide a data signal to the control signal terminal at the time between the fifth time and the first sixth time, between adjacent sixth times, the seventh time, at least part of the eighth time, and at least part of the tenth time, wherein the reference signal is a signal of the reference signal terminal, and the data signal is a signal of the data signal terminal.

22. The display device according to claim 15, further comprising: Multiple signal lines; The pixel driving circuits are electrically connected to the first scanning signal terminal, the second scanning signal terminal, the third scanning signal terminal, the reference signal terminal, the initial signal terminal and the data signal terminal respectively, and at least one pixel driving circuit includes: a fourth transistor and a fifth transistor; The display device includes: a plurality of pixel driving circuit groups, the plurality of pixel driving circuit groups including: at least two pixel driving circuits located in at least one row; The first scanning signal terminals connected to the pixel driving circuits in the same pixel driving circuit group are connected to the same signal line, the second scanning signal terminals connected to the pixel driving circuits in the same pixel driving circuit group are connected to the same signal line, the third scanning signal terminals connected to the pixel driving circuits in the same pixel driving circuit group are connected to the same signal line, the reference signal terminals connected to the pixel driving circuits in the same pixel driving circuit group are connected to the same signal line, and the initial signal terminals connected to the pixel driving circuits in the same pixel driving circuit group are connected to the same signal line; The fourth transistors in at least two pixel driving circuits in the same pixel driving circuit group are the same transistor, or the fifth transistors in at least two pixel driving circuits in the same pixel driving circuit group are the same transistor, or the fourth transistors in at least two pixel driving circuits in the same pixel driving circuit group are the same transistor, and the fifth transistors in at least two pixel driving circuits in the same pixel driving circuit group are the same transistor.

23. The display device according to claim 15, further comprising: Multiple signal lines; The pixel driving circuits are electrically connected to the first scanning signal terminal, the third scanning signal terminal, the initial signal terminal and the control signal terminal respectively, and at least one pixel driving circuit includes: a fourth transistor and a fifth transistor; The display device includes: a plurality of pixel driving circuit groups, the plurality of pixel driving circuit groups including: at least two pixel driving circuits located in at least one row; The first scanning signal terminals connected to the pixel driving circuits in the same pixel driving circuit group are connected to the same signal line, the third scanning signal terminals connected to the pixel driving circuits in the same pixel driving circuit group are connected to the same signal line, and the initial signal terminals connected to the pixel driving circuits in the same pixel driving circuit group are connected to the same signal line; The fourth transistors in at least two pixel driving circuits in the same pixel driving circuit group are the same transistor, or the fifth transistors in at least two pixel driving circuits in the same pixel driving circuit group are the same transistor, or the fourth transistors in at least two pixel driving circuits in the same pixel driving circuit group are the same transistor, and the fifth transistors in at least two pixel driving circuits in the same pixel driving circuit group are the same transistor.

24. A method for driving a pixel driving circuit, configured to drive the pixel driving circuit according to any one of claims 1 to 14, the method comprising: The first control subcircuit provides a signal to the first node under the control of at least one scan signal terminal, at least one input signal terminal and a signal of the third node; The second control subcircuit provides the signal of the first power supply terminal to the second node and provides the signal of the third node to the fourth node under the control of the signals of the first light-emitting signal terminal and the second light-emitting signal terminal; The third control subcircuit provides the signal of the initial signal terminal to the second node under the control of the signal of the third scan signal terminal; The driving sub-circuit provides a driving signal to the third node under the control of the signals at the first node and the second node.

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