Semiconductor device and manufacturing method therefor, and electronic device

Abstract

A semiconductor device and a manufacturing method therefor, and an electronic device. The semiconductor device comprises: a plurality of memory cells stacked in a direction perpendicular to a substrate and periodically distributed in different layers, wherein each memory cell comprises a transistor, the transistor at least comprises a semiconductor layer and a gate electrode, the gate electrode and the semiconductor layer extend in a first direction parallel to the substrate, and the semiconductor layer surrounds the gate electrode; and bit lines passing through the different layers and extending in the direction perpendicular to the substrate, wherein the semiconductor layers of the plurality of transistors arranged in the direction perpendicular to the substrate are connected to the same bit line.

Description

Semiconductor device, method of manufacturing the same, and electronic device

[0001] The present application claims priority from the Chinese patent application No. 202410408624.0 filed on April 7, 2024 and entitled "Semiconductor device, method of manufacturing the same, and electronic device", the contents of which should be understood as incorporated herein by reference. TECHNICAL FIELD

[0002] The embodiments of the present disclosure relate to, but are not limited to, semiconductor technology, and in particular, to a semiconductor device, a method of manufacturing the same, and an electronic device. BACKGROUND

[0003] A semiconductor memory device generally includes a substrate and a plurality of memory cells disposed on the substrate, and in order to reduce the cost of products as much as possible, it is desired to make as many memory cells as possible on a limited substrate. Since the advent of Moore's Law, various semiconductor structure designs and process optimizations have been proposed in the industry to meet people's current product needs.

[0004] SUMMARY

[0005] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0006] The embodiments of the present disclosure provide a semiconductor device, a method of manufacturing the same, and an electronic device.

[0007] In a first aspect, the embodiments of the present disclosure provide a semiconductor device, comprising: a plurality of memory cells, stacked along a direction perpendicular to a substrate and periodically distributed in different layers; the memory cell comprises a transistor, the transistor at least comprising a semiconductor layer and a gate electrode, the gate electrode and the semiconductor layer extending along a first direction parallel to the substrate, the semiconductor layer surrounding the gate electrode; a bit line, extending through the different layers and along a direction perpendicular to the substrate; the semiconductor layer of the transistor along the direction perpendicular to the substrate is connected to the same bit line.

[0008] In an exemplary example, the semiconductor layer of the transistor is a cylindrical structure with an opening facing the first direction, the cylindrical structure comprising an inner surface constituting a hollow portion and an outer surface other than the inner surface; the gate electrode of the transistor is located in the hollow portion of the cylindrical structure, the inner surface surrounds the gate electrode, and the gate electrode is insulated from the semiconductor layer; the bit line is in contact with a part of the outer surface of the cylindrical structure parallel to the first direction, and the part of the bit line in contact with the semiconductor layer is multiplexed as a first electrode of the transistor.

[0009] In an example, the transistor further comprises a gate insulating layer disposed between the gate electrode and the semiconductor layer; the semiconductor layer surrounds the gate insulating layer, and the gate insulating layer surrounds the gate electrode; in the first direction, the gate electrode protrudes from the cylindrical structure of the semiconductor layer by a dimension greater than that of the gate insulating layer.

[0010] In an example, the semiconductor layer is in contact with two bit lines, the two bit lines being located on opposite sides of the semiconductor layer along a second direction, the second direction being parallel to the substrate and perpendicular to the first direction.

[0011] In an example, the semiconductor layer is in contact with one bit line, the bit line surrounding the semiconductor layer.

[0012] In an example, the memory cell further comprises word lines distributed in different layers and extending in a direction parallel to the substrate; the portion of the gate electrode protruding from the cylindrical structure is electrically connected to the word lines disposed in the same layer.

[0013] In an example, the memory cell further comprises a capacitor distributed in different layers; the capacitor is located on one side of the transistor along the first direction; the capacitor comprises a first electrode plate, the first electrode plate being in contact with a portion of the outer surface of the semiconductor layer that is perpendicular to the first direction and away from the opening, and the portion of the semiconductor layer in contact with the first electrode plate is multiplexed as a second electrode of the transistor.

[0014] In an example, the capacitor further comprises a second electrode plate and a third electrode plate; in a plane perpendicular to the substrate and the first direction, the first electrode plate surrounds the second electrode plate on the outside, and the third electrode plate surrounds the first electrode plate on the outside.

[0015] In a second aspect, the present disclosure provides a method for manufacturing a semiconductor device, comprising: providing a substrate; depositing a first insulating film and a second insulating film alternately on the substrate to form a stack structure; forming a plurality of first trenches perpendicular to the substrate on the stack structure, the plurality of first trenches being arranged in a second direction parallel to the substrate, the first trenches dividing the stack structure into a plurality of transistor regions arranged in the second direction; forming a bit line in the first trenches, the bit line extending through different layers and in a direction perpendicular to the substrate; etching the second insulating film in the transistor regions in a direction parallel to the substrate to form a plurality of transistor trenches, the transistor trenches extending in a first direction in a plane parallel to the substrate and perpendicular to the second direction, the plurality of transistor trenches being arranged in a direction perpendicular to the substrate; depositing a semiconductor layer and a gate electrode in the transistor trenches, the semiconductor layer extending in the first direction and abutting an inner wall of the transistor trench, the semiconductor layer of a plurality of transistors arranged in a direction perpendicular to the substrate being connected to the same bit line, the gate electrode extending in the first direction, the semiconductor layer surrounding the gate electrode.

[0016] In an exemplary embodiment, before the forming of the plurality of transistor trenches, the method further comprises: defining a capacitor region on the stack structure, the capacitor region at least partially overlapping the first trenches, the bit line being located on one side of the capacitor region in the first direction; etching a surface of the capacitor region away from the bit line in a direction parallel to the substrate to remove the second insulating film in the capacitor region to form a plurality of first plate trenches, the first plate trenches extending in the first direction, the plurality of first plate trenches being arranged in a direction perpendicular to the substrate; forming the first plate in the first plate trenches from the side of the capacitor region away from the bit line in a direction parallel to the substrate; the first plate extending in the first direction and abutting an inner wall of the first plate trench; the first plate being in contact with the semiconductor layer, a portion of the first plate in contact with the semiconductor layer being reused as a second electrode of the transistor.

[0017] In an example, the method further comprises: sequentially depositing a sixth insulating film, a third conductive film and a first support film from a side of the capacitor region away from the bit line in a direction parallel to the substrate to form a first dielectric layer, a second plate and a first support layer; the first dielectric layer is in close contact with the first plate, the first dielectric layers in different layers are connected to each other; the second plate is in close contact with the first dielectric layer, the second plates in different layers are connected to each other; the first support layer is filled in the second plate; in a plane perpendicular to the substrate and the first direction, the first plate is wrapped outside the first dielectric layer, the first dielectric layer is wrapped outside the second plate, and the second plate is wrapped outside the first support layer; etching the stack structure in the capacitor region to expose the first plate in the capacitor region; sequentially depositing a seventh insulating film, a fourth conductive film and a second support film in the capacitor region to form a second dielectric layer, a third plate and a second support layer; the second dielectric layer is wrapped outside the first plate, the third plate is wrapped outside the second dielectric layer, the second support layer is filled outside the third plate and fills the entire capacitor region; in the plane perpendicular to the substrate and the first direction, the third plate is wrapped outside the first plate.

[0018] In an example, the sequentially depositing a semiconductor layer and a gate electrode in the transistor trench comprises: sequentially depositing a first semiconductor film, an eighth insulating film and a fifth conductive film from a side of the transistor region in a direction parallel to the substrate, and removing the fifth conductive film, the eighth insulating film and the first semiconductor film from a side of the transistor region in the first direction to disconnect the first semiconductor film between adjacent transistors in the second direction and the first semiconductor film between adjacent transistors in a direction perpendicular to the substrate, to form the semiconductor layer, a gate insulating layer and the gate electrode; wherein the semiconductor layer is a cylindrical structure with an opening facing the first direction, the cylindrical structure includes an inner surface constituting a hollow portion and an outer surface other than the inner surface; the gate electrode is located in the hollow portion of the cylindrical structure, the inner surface of the semiconductor layer surrounds the gate insulating layer, and the gate insulating layer surrounds the gate electrode; in the first direction, the size of the gate electrode protruding from the cylindrical structure of the semiconductor layer is greater than the size of the gate insulating layer protruding from the cylindrical structure.

[0019] In an example, the method further comprises: depositing a sixth conductive film on a side of the transistor region in a direction parallel to the substrate, and etching the sixth conductive film to form a word line extending in the second direction in the transistor trench; and electrically connecting the part of the gate electrode protruding from the cylindrical structure to the word line in the same layer.

[0020] In an example, the semiconductor layer is in contact with two bit lines, the two bit lines being located on opposite sides of the semiconductor layer in the second direction; the forming the bit line in the first trench comprises: sequentially forming a first protective layer and a first filling layer in the first trench by deposition, the first protective layer being in close contact with the inner wall of the first trench, and the first filling layer filling the first trench; defining a plurality of bit line regions on the stack structure, removing the first filling layer in the bit line regions to form initial bit line through holes; removing the first protective layer in the initial bit line through holes in the second direction to form bit line through holes; the orthographic projection of the bit line regions on the substrate is within the range of the first trench, and the plurality of bit line regions are arranged in the second direction in sequence; depositing a first conductive film in the bit line through holes, and removing the first conductive film and the first protective layer on the side of the bit line through hole close to the substrate to form an initial bit line; depositing a fifth insulating film in the bit line through hole to form a second filling layer; the initial bit line is in close contact with the bit line through hole, and the second filling layer fills the bit line through hole; defining a plurality of first punching regions in a direction perpendicular to the substrate, the plurality of first punching regions being located on both sides of the bit line through hole in the first direction and within the range of the first trench; removing the first filling layer in the first punching regions to form first through holes; etching the exposed initial bit line in the first direction in the first through holes to form the bit line.

[0021] In an example, the semiconductor layer is in contact with a bit line, and the bit line surrounds the semiconductor layer. Forming the bit line in the first trench includes: sequentially forming a first protective layer and a first filling layer in the first trench by deposition, the first protective layer abutting the inner wall of the first trench, and the first filling layer filling the first trench; defining a plurality of bit line regions on the stack structure, removing the first filling layer in the bit line regions to form initial bit line holes; removing the first protective layer in the initial bit line holes in the second direction to form bit line holes; the orthographic projection of the bit line regions on the substrate is within the range of the first trench, and the plurality of bit line regions are arranged in sequence along the second direction; etching the first insulating film in the bit line holes along the second direction to make the adjacent bit line holes communicate with each other; depositing a first conductive film in the bit line holes, and removing the first conductive film and the first protective layer on the side close to the substrate in the bit line holes to form initial bit lines; depositing a fifth insulating film in the bit line holes to form a second filling layer; the initial bit lines abut the bit line holes, and the second filling layer fills the bit line holes; defining a plurality of first punching regions in a direction perpendicular to the substrate, the plurality of first punching regions are located on both sides of the bit line holes along the first direction and within the range of the first trench; removing the first filling layer in the first punching regions to form first holes; etching the exposed initial bit lines in the first holes along the first direction to form the bit lines.

[0022] In a third aspect, the embodiments of the present disclosure further provide an electronic device including the semiconductor device as described above.

[0023] In the embodiments of the present disclosure, the gate electrode of the transistor and the semiconductor layer extend along the first direction parallel to the substrate, the semiconductor layer surrounds the gate electrode, and the bit line extends along the direction perpendicular to the substrate and is connected with the semiconductor layers of different layers of transistors. Such a structure design makes the bit line more easily contact the transistor, which is helpful for subsequent wiring of the semiconductor device. In addition, the transistor is arranged along the direction parallel to the substrate, which is easy to remove the interlayer and intercolumn parasitic MOS through the etching process, and the process method is simple. Moreover, the bit line is arranged along the direction perpendicular to the substrate, which is beneficial to increase the spacing between adjacent bit lines, can reduce the capacitive coupling between the bit lines, reduce the parasitic capacitance of the wiring, and better meet the user's demand for high-performance memory devices.

[0024] Other aspects can become apparent from a review of the drawings and detailed description.

[0025] SUMMARY

[0026] The accompanying drawings are included to provide a further understanding of the technical solutions of the present disclosure, constitute a part of the specification, and are used to explain the technical solutions of the present disclosure together with the embodiments of the present disclosure, and do not constitute a limitation on the technical solutions of the present disclosure.

[0027] Fig. 1 is a schematic diagram of a perspective view of a semiconductor device in at least one embodiment of the present disclosure;

[0028] Fig. 2 is a top view of Fig. 1;

[0029] Fig. 3A is a sectional view of Fig. 1 in the AA direction;

[0030] Fig. 3B is a sectional view of Fig. 1 in the BB direction;

[0031] Fig. 3C is a sectional view of Fig. 1 in the CC direction;

[0032] Fig. 4 is a schematic diagram of a perspective view of a semiconductor device in yet another exemplary embodiment;

[0033] Fig. 5A is a sectional view of Fig. 4 in the AA direction;

[0034] Fig. 5B is a sectional view of Fig. 4 in the CC direction;

[0035] Fig. 6A is a schematic diagram of a perspective view after forming a stack structure in at least one embodiment of the present disclosure;

[0036] Fig. 6B is a sectional view of Fig. 6A in the AA direction;

[0037] Fig. 7A is a schematic diagram of a perspective view after forming a first trench in at least one embodiment of the present disclosure;

[0038] Fig. 7B is a sectional view of Fig. 7A in the AA direction;

[0039] Fig. 7C is a sectional view of Fig. 7A in the BB direction;

[0040] Fig. 8A is a schematic diagram of a perspective view after forming a first filling layer in at least one embodiment of the present disclosure;

[0041] Fig. 8B is a sectional view of Fig. 8A in the AA direction;

[0042] Fig. 8C is a sectional view of Fig. 8A in the BB direction;

[0043] Fig. 9A is a schematic diagram of a perspective view after forming a bit line via in at least one embodiment of the present disclosure;

[0044] Fig. 9B is a top view of Fig. 9A;

[0045] Fig. 9C is a sectional view of Fig. 9A in the AA direction;

[0046] Fig. 9D is a sectional view of Fig. 9A in the CC direction;

[0047] FIG. 10A is a schematic perspective view of forming a second filling layer in at least one embodiment of the present disclosure;

[0048] FIG. 10B is a top view of FIG. 10A;

[0049] FIG. 10C is a sectional view of FIG. 10A along AA direction;

[0050] FIG. 10D is a sectional view of FIG. 10A along CC direction;

[0051] FIG. 11A is a schematic perspective view of forming a first via in at least one embodiment of the present disclosure;

[0052] FIG. 11B is a top view of FIG. 11A;

[0053] FIG. 11C is a sectional view of FIG. 11A along AA direction;

[0054] FIG. 12A is a schematic perspective view of forming a bit line in at least one embodiment of the present disclosure;

[0055] FIG. 12B is a top view of FIG. 12A;

[0056] FIG. 12C is a sectional view of FIG. 12A along AA direction;

[0057] FIG. 13A is a schematic perspective view of exposing a capacitor region in at least one embodiment of the present disclosure;

[0058] FIG. 13B is a sectional view of FIG. 13A along AA direction;

[0059] FIG. 14A is a schematic perspective view of forming a first plate slot in at least one embodiment of the present disclosure;

[0060] FIG. 14B is a sectional view of FIG. 14A along AA direction;

[0061] FIG. 14C is a sectional view of FIG. 14A along BB direction;

[0062] FIG. 15A is a schematic perspective view of forming a first plate and a first protection layer in at least one embodiment of the present disclosure;

[0063] FIG. 15B is a sectional view of FIG. 15A along AA direction;

[0064] FIG. 15C is a sectional view of FIG. 15A along BB direction;

[0065] FIG. 16A is a schematic perspective view of forming a first support layer in at least one embodiment of the present disclosure;

[0066] FIG. 16B is a top view of FIG. 16A;

[0067] FIG. 16C is a sectional view of FIG. 16A along AA direction;

[0068] FIG. 16D is a cross-sectional view of FIG. 16A along the BB direction;

[0069] FIG. 17A is a perspective view of removing the first filling layer in the capacitor region in at least one embodiment of the present disclosure;

[0070] FIG. 17B is a top view of FIG. 17A;

[0071] FIG. 17C is a cross-sectional view of FIG. 17A along the AA direction;

[0072] FIG. 17D is a cross-sectional view of FIG. 17A along the BB direction;

[0073] FIG. 18A is a perspective view of removing the first protective layer in the capacitor region in at least one embodiment of the present disclosure;

[0074] FIG. 18B is a top view of FIG. 18A;

[0075] FIG. 18C is a cross-sectional view of FIG. 18A along the AA direction;

[0076] FIG. 18D is a cross-sectional view of FIG. 18A along the BB direction;

[0077] FIG. 19A is a perspective view of removing the first insulating film in the capacitor region in at least one embodiment of the present disclosure;

[0078] FIG. 19B is a cross-sectional view of FIG. 19A along the BB direction;

[0079] FIG. 20A is a perspective view of forming the second support layer in at least one embodiment of the present disclosure;

[0080] FIG. 20B is a top view of FIG. 20A;

[0081] FIG. 20C is a cross-sectional view of FIG. 20A along the AA direction;

[0082] FIG. 21A is a perspective view of exposing the transistor region in at least one embodiment of the present disclosure;

[0083] FIG. 21B is a cross-sectional view of FIG. 21A along the AA direction;

[0084] FIG. 22A is a perspective view of forming the transistor trench in at least one embodiment of the present disclosure;

[0085] FIG. 22B is a cross-sectional view of FIG. 22A along the AA direction;

[0086] FIG. 22C is a cross-sectional view of FIG. 22A along the CC direction;

[0087] FIG. 23A is a perspective view of forming the gate electrode in at least one embodiment of the present disclosure;

[0088] FIG. 23B is a top view of FIG. 23A;

[0089] FIG. 23C is a cross-sectional view of FIG. 23A along the AA direction;

[0090] FIG. 24 is a perspective view of the gate electrode after being exposed again in accordance with one embodiment of the present disclosure;

[0091] FIG. 25 is a cross-sectional view of the bit line via along the second direction after removing the first insulating film on both sides of the bit line via in the second direction.

[0092] DETAILED DESCRIPTION

[0093] Embodiments of the present disclosure will be described below with reference to the accompanying drawings. The embodiments can be implemented in various forms. One skilled in the art understands that the embodiments and the contents can be changed into other forms without departing from the spirit of the present disclosure and the scope. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the embodiments below. The embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other without conflict.

[0094] In the drawings, the size, the thickness, or the region of one or more constituent elements can be exaggerated for clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to such a scale. The shapes and the sizes of one or more components in the drawings and the embodiments of the present disclosure do not reflect the actual one, and the present disclosure is not limited to a certain scale.

[0095] The ordinal numbers "first", "second", "third", and the like in the present specification are used to avoid confusion among constituent elements and are not intended to indicate or imply a quantity or a particular order. "A plurality of" in the present disclosure means two or more.

[0096] In the present specification, the words "center", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like used to describe the positional relationship of the constituent elements with reference to the drawings are used for the convenience of explanation of the present specification and simplification of the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be construed as limiting the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction of the constituent elements described. Therefore, it is not limited to the words described in the specification, and can be appropriately changed according to the situation.

[0097] In this specification, unless otherwise explicitly specified and limited, the terms "mount", "connected", "connection" should be interpreted broadly. For example, it can be fixed connection, or detachable connection, or integral connection; can be physical connection or signal connection; can be direct connection, or indirect connection through intermediate parts, or internal connection of two elements. For those skilled in the art, the meaning of the above terms in this disclosure can be understood according to the circumstances.

[0098] In this specification, "connection" or "electric connection" can include the case where the constituent elements are connected together through an element having some electrical effect. The element having some electrical effect is not particularly limited as long as it can perform transmission of electrical signals between the constituent elements to be connected. Examples of the element having some electrical effect include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, other elements having various functions, and the like.

[0099] In this specification, a transistor can include a gate (also referred to as a gate electrode), a channel, a first electrode, and a second electrode. In this specification, the first electrode can be a drain electrode, and the second electrode can be a source electrode, or the first electrode can be a source electrode, and the second electrode can be a drain electrode. The source electrode can also be referred to as a source electrode terminal, a source region, or a source. The drain electrode can also be referred to as a drain electrode terminal, a drain region, or a drain. In the case of using a transistor whose polarity is reversed, or in the case where the direction of current flowing in a circuit is changed, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Thus, in this specification, the "source electrode" and the "drain electrode" can be interchanged.

[0100] In this specification, "parallel" means a state where an angle formed by two straight lines is greater than or equal to -10° and less than or equal to 10°, and thus, a state where the angle is greater than or equal to -5° and less than or equal to 5° is also included. In addition, "perpendicular" means a state where an angle formed by two straight lines is greater than or equal to 80° and less than or equal to 100°, and thus, a state where the angle is greater than or equal to 85° and less than or equal to 95° is also included.

[0101] In this specification, "A and B are provided in the same layer" includes a film layer formed of the same material or different materials positioned on the same film layer. For example, A and B are formed in the same film layer by the same material and then formed by the same patterning process or different patterning processes. A and B provided in the same layer can be positioned on the same horizontal plane but do not necessarily have to be positioned on the same film layer, or can be positioned in different regions of the same film layer but do not necessarily have to be positioned on the same horizontal plane.

[0102] In the embodiments of the present disclosure, "A and B are an integrated structure connected to each other" can include that the connected film layers are integrated by patterning on one film layer. For example, A and B are structures connected by being formed on one film layer using the same material and by being formed at the same time through the same patterning process.

[0103] In the embodiments of the present disclosure, "substrate" means and includes a base material or structure on which materials such as vertical field effect transistors are formed. The substrate can be a semiconductor substrate, a base semiconductor layer on a support structure, a metal electrode, or a semiconductor substrate having one or more layers, structures, or regions formed thereon. The substrate can be a conventional silicon substrate or other bulk substrate including a layer of semiconductor material.

[0104] The embodiments of the present disclosure provide a semiconductor device, comprising: a plurality of memory cells, stacked along a direction perpendicular to a substrate and periodically distributed in different layers; the memory cells comprising transistors, the transistors comprising at least a semiconductor layer and a gate electrode, the gate electrode and the semiconductor layer extending along a first direction parallel to the substrate, the semiconductor layer surrounding the gate electrode; a bit line extending through the different layers and along a direction perpendicular to the substrate; the semiconductor layer of a plurality of the transistors arranged along a direction perpendicular to the substrate being connected to the same bit line.

[0105] In the embodiments of the present disclosure, by arranging the gate electrode and the semiconductor layer of the transistor to extend along a first direction parallel to the substrate, and arranging the semiconductor layer to surround the gate electrode, and arranging the bit line to extend along a direction perpendicular to the substrate and to be connected to the semiconductor layer of the transistors in different layers, such a structure design makes the bit line more easily contact the transistor, which is helpful for subsequent wiring of the semiconductor device. Moreover, the transistors are arranged along a direction parallel to the substrate, which is easy to remove the interlayer and intercolumn parasitic MOS through an etching process, and the process method is simple. Furthermore, the bit line is arranged along a direction perpendicular to the substrate, which is beneficial to increase the spacing between adjacent bit lines, can reduce the capacitive coupling between the bit lines, reduce the parasitic capacitance of the wiring, and can better meet the user's demand for high-performance memory devices.

[0106] In an example, the semiconductor layer of the transistor is a cylindrical structure with an opening facing the first direction, the cylindrical structure comprising an inner surface constituting a hollow portion and an outer surface other than the inner surface; the gate electrode of the transistor is located in the hollow portion of the cylindrical structure, the inner surface surrounds the gate electrode, and the gate electrode is arranged in insulation with the semiconductor layer; the bit line contacts a part of the outer surface parallel to the first direction, and the part of the bit line in contact with the semiconductor layer is multiplexed as a first electrode of the transistor.

[0107] In an example, the transistor further includes a gate insulating layer disposed between the gate electrode and the semiconductor layer; the semiconductor layer surrounds the gate insulating layer, and the gate insulating layer surrounds the gate electrode; in the first direction, the gate electrode protrudes from the cylindrical structure of the semiconductor layer by a dimension greater than that of the gate insulating layer.

[0108] In an example, the semiconductor device further includes word lines distributed in different layers and extending in a direction parallel to the substrate; the portion of the gate electrode protruding from the cylindrical structure is electrically connected to the word line disposed in the same layer.

[0109] In an example, a plurality of columns of memory cells and a plurality of word lines are distributed in the same layer, and a column extends along a word line in the same direction.

[0110] In an example, a first insulating film is further included to separate memory cells in different layers from each other by the first insulating film.

[0111] FIG. 1 is a schematic diagram of a semiconductor device in at least one embodiment of the present disclosure, FIG. 2 is a top view of FIG. 1, FIG. 3A is a cross-sectional view of FIG. 1 in the AA direction, FIG. 3B is a cross-sectional view of FIG. 1 in the BB direction, and FIG. 3C is a cross-sectional view of FIG. 1 in the CC direction. In the present example, five layers of memory cells stacked in a direction perpendicular to the substrate are taken as an example for illustration, and each layer of memory cells can include a plurality of memory cells arranged in a first direction D1 and a second direction D2.

[0112] In some examples, the first direction D1 and the second direction D2 can be parallel to the plane in which the substrate 100 is located, and the third direction D3 can be perpendicular to the plane in which the substrate 100 is located. The first direction D1 and the second direction D2 can intersect, for example, the first direction D1 can be perpendicular to the second direction D2. In the plane parallel to the plane in which the substrate 100 is located, the plurality of memory cells arranged in the first direction D1 can be referred to as a row of memory cells, and the plurality of memory cells arranged in the second direction D2 can be referred to as a column of memory cells. In the present example, in each layer, three rows of memory cells can be arranged in the first direction D1, and one column of memory cells can be arranged in the second direction D2. In order to clearly show the structures of the parts, only the structures of the memory cells located on both sides in the second direction D2 are shown in the drawings of the embodiments of the present disclosure. In the third direction D3, each layer of memory cells can be separated by a first insulating film 11.

[0113] The storage unit in the semiconductor device provided by the embodiment can be a 1T1C structure, that is, a single storage unit can include one transistor and one capacitor. The transistor functions as a switch of the storage unit and can control whether the capacitor allows the charge to pass through. The capacitor is used to store the charge. When the word line (WL, World Line) is loaded with an opening voltage, the transistor is turned on, and the charge information stored in the capacitor can be read through the bit line (BL, Bit Line). A plurality of columns of storage units and a plurality of word lines can be distributed in the same layer. A column of storage units along the extension direction of the word line can be connected to the same word line. In the embodiment, a single word line in the same layer is taken as an example for illustration.

[0114] The dashed area P in FIG. 2 schematically shows a single storage unit. In combination with FIGS. 1 to 3C, each layer of storage units is connected to a word line 34 in the same layer. The word line 34 can extend along the second direction D2. The word lines 34 in different layers are separated by the first insulating film 11 and are arranged at intervals. The bit line 17 extends along the third direction D3 and penetrates through the storage units in different layers. A plurality of storage units located in the extension direction of the bit line 17 are connected to the bit line 17. A plurality of bit lines 17 can be arranged in sequence along the second direction D2. The plurality of bit lines 17 are separated by the second filling layer 16 and are arranged at intervals.

[0115] In some examples, the transistor can include a first electrode, a second electrode, a gate electrode 33, and a semiconductor layer 31. The word line 34 can be connected to the gate electrode 33 of the transistor, for example, the word line 34 and the gate electrode of the transistor in the same layer can be in contact with each other, or can be an integrated structure, thereby being connected to the storage unit. The bit line 17 can be connected to the first electrode of the transistor, for example, the bit line 17 and the first electrode of the transistor can be an integrated structure. The second electrode of the transistor can be connected to the plate of the capacitor, for example, the second electrode of the transistor and the plate of the capacitor can be connected to each other or be an integrated structure.

[0116] In some examples, the semiconductor layer 31 of the transistor is a cylindrical structure with an opening facing the first direction D1. The cylindrical structure includes an inner surface constituting a hollow portion and an outer surface other than the inner surface. The gate electrode 33 of the transistor is located in the hollow portion of the cylindrical structure. The inner surface of the semiconductor layer 31 surrounds the gate electrode 33. The gate insulating layer 32 is arranged between the gate electrode 33 and the semiconductor layer 31. The semiconductor layer 31 surrounds the gate insulating layer 32. The gate insulating layer 32 surrounds the gate electrode 33. In the first direction D1, the size of the gate electrode 33 protruding from the cylindrical structure of the semiconductor layer 31 is greater than the size of the gate insulating layer 32 protruding from the cylindrical structure.

[0117] In some examples, the semiconductor layers 31 between different rows of transistors arranged along the second direction D2 are disconnected from each other, and the semiconductor layers 31 between different layers of transistors arranged along the third direction D3 are disconnected from each other, effectively removing parasitic channels and improving the performance of the semiconductor device.

[0118] In some examples, the bit lines 17 are in contact with the portions of the outer surface of the semiconductor layers 31 that are parallel to the first direction D1, and the portions of the semiconductor layers 31 in contact with the bit lines 17 can be reused as the first electrodes of the transistors.

[0119] In some examples, the extension direction of the word lines 34 can intersect the extension direction of the cylindrical structure of the semiconductor layers 31, and the word lines 34 and the gate electrodes 33 that are arranged in the same layer are electrically connected to the portions of the semiconductor layers 31 that protrude from the cylindrical structure of the semiconductor layers 31.

[0120] In some examples, as shown in FIGS. 3A and 3C, the semiconductor layers 31 of a single transistor can be in contact with two bit lines 17 that are located on opposite sides of the semiconductor layers 31 along the second direction D2, and the two bit lines 17 sandwich the semiconductor layers 31 of multiple transistors arranged in different layers. After the semiconductor device of the present embodiment is formed, the two bit lines 17 can be connected to each other, which is not limited by the present embodiment.

[0121] In some examples, the capacitors are distributed in different layers, and the capacitors are located on one side of the transistors along the first direction D1. The capacitors include first electrode plates 20 that are in contact with the portions of the outer surface of the semiconductor layers 31 that are perpendicular to the first direction D1 and away from the openings, and the portions of the semiconductor layers 31 in contact with the first electrode plates 20 can be reused as the second electrodes of the transistors.

[0122] In some examples, the capacitor can include a first electrode plate 20, a second electrode plate 23 and a third electrode plate 26. The first electrode plate 20 can extend along the first direction D1, the cross section of the first electrode plate 20 along the second direction D2 and the third direction D3 can be annular, and the cross section of the first electrode plate 20 along the first direction D1 and the third direction D3 can be "C" shaped. The second electrode plate 23 can be located inside the annulus formed by the first electrode plate 21, for example, the cross section of the second electrode plate 23 along the first direction D1 and the third direction D3 can be "U" shaped, the "U" shape of the second electrode plate 23 is located inside the "C" shape of the first electrode plate 21, and the multiple layers of the second electrode plate 23 perpendicular to the substrate 100 direction are connected to each other; the cross section of the second electrode plate 23 along the second direction D2 and the third direction D3 can be annular, and the annulus of the first electrode plate 20 can surround the annulus of the second electrode plate 23, and the first dielectric layer 22 is filled between the first electrode plate 20 and the second electrode plate 23. The cross section of the third electrode plate 26 along the second direction D2 and the third direction D3 can be annular, and the annulus of the third electrode plate 26 can surround the annulus of the first electrode plate 20; the cross section of the third electrode plate 26 along the first direction D1 and the third direction D3 can be annular and located on both sides of the "C" shape of the first electrode plate 21 along the third direction D3, the second dielectric layer 25 is filled between the third electrode plate 26 and the first electrode plate 20, and the second support layer 27 is arranged on the side of the third electrode plate 26 away from the first electrode plate 20.

[0123] In order for the circuit to read out signals, the 1T1C memory device with a three-dimensional structure often needs to set a larger capacitor, and reduce the capacitive coupling between the metal lines of the three-dimensional device as much as possible, that is, reduce the bit line capacitance. In the embodiment, the second electrode plate 23 and the third electrode plate 26 are arranged on the inner and outer sides of the first electrode plate 20 respectively to form two layers of capacitors inside and outside. Compared with a single-layer capacitor with only two electrode plates, the double-layer capacitor occupies a smaller area and has a smaller length under the same capacitor size, which helps to reduce the volume of the semiconductor device and prevent the collapse of the stacked structure during preparation. By vertically arranging the bit lines, the bit line spacing can be increased, the coupling between the bit lines can be reduced, the bit line capacitance can be effectively reduced, and the process complexity can be reduced.

[0124] In some examples, a first support layer 24 is arranged on the side of the capacitor away from the bit line 17, and the first support layer 24 fills between capacitors of different layers; a third support layer 35 is arranged on the side of the word line 34 away from the bit line 17, and the third support layer 35 fills between transistors of different layers. The first support layer 24 and the third support layer 35 can play a supporting role for the semiconductor device, ensuring the stability of the structure of the semiconductor device.

[0125] In some examples, a stop layer (not shown) can be provided between the substrate 100 and the semiconductor device, which helps to define the stop position of the process during preparation and protects the substrate 100, which is not limited in the present application.

[0126] Figure 4 is a schematic diagram of the structure of a semiconductor device in another example embodiment. Figure 4 differs from Figure 1 in that the structure of the bit line 17 is different, and the remaining structures can be described with reference to the description of Figures 1 to 3C, which will not be repeated here.

[0127] Figure 5A is a cross-sectional view of Figure 4 in the AA direction, and Figure 5B is a cross-sectional view of Figure 4 in the CC direction. The cross-sectional view of Figure 4 in the BB direction can be described with reference to Figure 3B. In combination with Figures 4 to 5B, the semiconductor layer 31 of a single transistor can be in contact with a bit line 17, which extends vertically in the third direction D3 and surrounds the semiconductor layer 31 in the plane of the second direction D2 and the third direction D3. In the semiconductor device of the present embodiment, the same transistor is connected to a bit line 17, which does not need to be connected to two separate bit lines 17 subsequently compared to the scheme shown in Figure 1.

[0128] The technical scheme of the present embodiment will be further described below through the preparation process of the semiconductor device of the present embodiment. The "patterning process" in the present embodiment includes deposition of a film layer, coating of photoresist, mask exposure, development, etching, stripping of photoresist, etc., which is a mature preparation process in the related art. The "lithography process" in the present embodiment includes coating of a film layer, mask exposure and development, which is a mature preparation process in the related art. Deposition can use known processes such as sputtering, evaporation, chemical vapor deposition, etc., coating can use known coating processes, and etching can use known methods, which are not limited herein.

[0129] In some examples, the preparation process of the semiconductor device shown in Figure 1 can include the following steps. In the present example, the cross-sectional view in the AA direction refers to the cross-sectional view in the AA direction and perpendicular to the plane of the substrate, the cross-sectional view in the BB direction refers to the cross-sectional view in the BB direction and perpendicular to the plane of the substrate, and the cross-sectional view in the CC direction refers to the cross-sectional view in the CC direction and perpendicular to the plane of the substrate.

[0130] (1) Form a laminated structure by sequentially and alternately depositing the first insulating film 11 and the second insulating film 12 on the substrate 100. Figure 6A is a schematic diagram of the laminated structure after formation in at least one embodiment of the present disclosure, and Figure 6B is a cross-sectional view of Figure 6A in the AA direction.

[0131] In some examples, the substrate 100 can be a semiconductor substrate, such as a silicon substrate, and the stack structure can be formed on a silicon wafer. The material of the first insulating film 11 can include an oxide, such as silicon dioxide (SiO2), and tetraethoxysilane (TEOS) can be used as a silicon source for the silicon dioxide in chemical vapor deposition. The material of the second insulating film 12 can include a nitride, which refers to a class of compound materials composed of nitrogen and metal elements (such as aluminum, gallium, titanium, etc.). The nitride film can be formed by plasma-enhanced chemical vapor deposition (PECVD).

[0132] In some examples, the stack structure can include five first insulating films 11 and five second insulating films 12 arranged alternately. The number of first insulating films 11 and second insulating films 12 included in the stack structure is not limited in the present embodiment. In some examples, the thickness of the first insulating film 11 closest to the substrate 100 can be greater than the thickness of the first insulating film 11 sandwiched by two second insulating films 12, and the thickness of the plurality of second insulating films 12 can be substantially the same. The thickness of the first insulating film 11 can be the distance between the surface of the first insulating film 11 close to the substrate 100 and the surface of the first insulating film 11 away from the substrate 100 in the third direction D3, and the thickness of the second insulating film 12 can be the distance between the surface of the second insulating film 12 close to the substrate 100 and the surface of the second insulating film 12 away from the substrate 100 in the third direction D3. The thickness of each first insulating film 11 and second insulating film 12 can be set as needed, and the present embodiment does not limit this.

[0133] In some examples, the first insulating film 11 and the second insulating film 12 can cover the substrate 100. The orthographic projection of the first insulating film 11 on the substrate 100 can coincide with the orthographic projection of the second insulating film 12 on the substrate 100, for example, the orthographic projection shape can be a rectangle, and the orthographic projection of the first insulating film 11 on the substrate 100 can coincide with the substrate 100.

[0134] In some examples, before forming the stack structure, a stop layer can be formed on the substrate 100, and the trench in the subsequent process can penetrate the stack structure to expose the surface of the stop layer, i.e., the stop layer can be disposed between the substrate 100 and the semiconductor device. The material of the stop layer can be the same as that of the first insulating film, and the material and thickness of the stop layer can be set as needed, and the present embodiment does not limit this.

[0135] (2) A plurality of first trenches T1 perpendicular to the substrate 100 are etched on the stack structure by a lithography process, a third insulating film and a fourth insulating film are sequentially deposited in the first trenches T1 to form a first protective layer 13 and a first filling layer 14. FIG. 7A is a schematic perspective view of the stack structure after the first trenches are formed in at least one embodiment of the present disclosure, FIG. 7B is a sectional view of FIG. 7A along the direction AA, and FIG. 7C is a sectional view of FIG. 7A along the direction BB. FIG. 8A is a schematic perspective view of the stack structure after the first filling layer is formed in at least one embodiment of the present disclosure, FIG. 8B is a sectional view of FIG. 8A along the direction AA, and FIG. 8C is a sectional view of FIG. 8A along the direction BB.

[0136] In some examples, the material of the third insulating film can include an oxide, for example, the same material as the first insulating film can be used, and the material of the fourth insulating film can include a nitride, for example, the same material as the second insulating film can be used. The third insulating film can be deposited by atomic layer deposition, and the fourth insulating film can be deposited by PECVD.

[0137] In some examples, as shown in FIGS. 7A-7C, the plurality of first trenches T1 can be arranged in the second direction D2 on the stack structure, and a single first trench T1 can have a cuboid shape, the length of the cuboid can extend in the first direction D1, the width of the cuboid can extend in the second direction D2, and the height of the cuboid can extend in the third direction D3. The inner wall of the first trench T1 can include a side wall and a bottom wall, the side wall can include the first insulating film 11 and the second insulating film 12 arranged in sequence, and the bottom wall can be the first insulating film 11 closest to the substrate 100, and in the third direction D3, the bottom wall can be located inside the first insulating film 11 closest to the substrate 100. The sizes of the plurality of first trenches T1 can be equal, and in the drawings of the present embodiment, two first trenches T1 are taken as an example for illustration, and the number of first trenches T1 and the sizes of different first trenches T1 can be set as needed, which is not limited in the present embodiment.

[0138] In some examples, in the case where the stop layer is formed, the first trench T1 can penetrate through the stack structure, and the bottom wall of the first trench T1 can be the stop layer, which is not limited in the present embodiment.

[0139] In some examples, as shown in FIGS. 8A-8C, the first protective layer 13 can be in close contact with the side wall and the bottom wall of the first trench T1, the side of the first protective layer 13 away from the substrate 100 is formed with a groove similar in shape to the first trench T1, and the first filling layer 14 can fill the groove of the first protective layer 13, so that the first protective layer 13 and the first filling layer 14 can fill the first trench T1. In subsequent processes, the first protective layer 13 and the first filling layer 14 can act as a sacrificial material, and can also provide support to the film layers of the stack structure to prevent the stack structure from collapsing.

[0140] In some examples, the thickness of the first protective layer 13 in this step can be determined according to the etching selection ratio between the first filling layer 14 material and the first protective layer 13 material, so as to ensure that the first protective layer 13 will not be affected in the subsequent wet etching process of the first filling layer 14. The thickness of the first protective layer 13 can be determined according to the specific process, which is not limited in the embodiment.

[0141] (3) Defining a bit line area W on the stack structure by a photolithography process, removing the first filling layer 14 in the bit line area W by the photolithography process to form an initial bit line via hole, and then performing wet etching on the first protective layer 13 in the initial bit line via hole along the second direction D2 to remove the first protective layer 13 in the second direction D2 of the initial bit line via hole and form a bit line via hole K1. FIG. 9A is a perspective view of the bit line via hole after formation according to at least one embodiment of the present disclosure, FIG. 9B is a top view of FIG. 9A, FIG. 9C is a cross-sectional view of FIG. 9A along the AA direction, and FIG. 9D is a cross-sectional view of FIG. 9A along the CC direction.

[0142] In some examples, as shown in FIG. 9B, the orthographic projection of the bit line area W on the substrate 100 along the third direction D3 can be located within the range of the first trench T1. As shown in FIGS. 9A, 9C and 9D, the bit line via hole K1 can expose the first filling layer 14 in the first direction D1, and can expose the sidewall of the first trench T1 in the second direction D2. The size of the bit line via hole K1 in the first direction D1 and the size of the bit line via hole K1 in the second direction D2 can be equal, both being the second width S2, that is, the orthographic projection of the bit line via hole K1 on the substrate 100 along the third direction D3 can be a square. The shape and size of the bit line via hole K1 can be set as needed, which is not limited in the embodiment.

[0143] (4) Depositing a first conductive thin film in the bit line via hole K1, removing the first conductive thin film and the first protective layer 13 at the bottom of the bit line via hole K1 by dry etching to form an initial bit line 15, and then depositing a fifth insulating thin film in the bit line via hole K1 to form a second filling layer 16. FIG. 10A is a perspective view of the second filling layer after formation according to at least one embodiment of the present disclosure, FIG. 10B is a top view of FIG. 10A, FIG. 10C is a cross-sectional view of FIG. 10A along the AA direction, and FIG. 10D is a cross-sectional view of FIG. 10A along the CC direction.

[0144] In some examples, the material of the first conductive thin film can be a metal or alloy material, and can adopt a single layer or a stack structure. For example, the material of the first conductive thin film can be titanium nitride. The material of the fifth insulating thin film can include an oxide, for example, the same material as the first insulating thin film can be adopted. The first conductive thin film and the fifth insulating thin film can be deposited by an atomic layer deposition method.

[0145] In some examples, as shown in FIGS. 10A-10D, the initial bit line 15 can be in close contact with the sidewall of the bit line via hole K1, and in the third direction D3, the initial bit line 15 encloses a groove similar in shape to the bit line via hole K1, which exposes the bottom wall of the first trench T1, and the second filling layer 16 can fill the groove enclosed by the initial bit line 15. The thickness of each side of the initial bit line 15 can be the third width S3.

[0146] (5) A plurality of first punching areas F are defined on the side surface of the stack structure away from the substrate 100 by a photolithography process, the plurality of first punching areas F are located within the range of the first trench T1 on both sides of the initial bit line 15 in the first direction D1, and the first filling layer 14 in the first punching area F is removed by a photolithography process to form a first via hole K2. FIG. 11A is a perspective view of the first via hole after formation in at least one embodiment of the present disclosure, FIG. 11B is a top view of FIG. 11A, FIG. 11C is a cross-sectional view of FIG. 11A along the AA direction, and the cross-sectional view of FIG. 11A along the CC direction can refer to FIG. 10D.

[0147] In some examples, as shown in FIGS. 11A-11C, the first via hole K2 exposes the first protective layer 13, the first filling layer 14, and the initial bit line 15 in the first direction D1, and the first via hole K2 exposes the first protective layer 13 in the second direction D2 and the third direction D3. The shape and size of the first punching area F and the first via hole K2 can be set according to the process, and the present embodiment does not limit the shape and size of the first punching area F and the first via hole K2.

[0148] Subsequently, wet etching is used to perform lateral etching on the initial bit line 15 in the first direction D1 in the first via hole K2 to remove the initial bit line 15 exposed in the first direction D1, and the initial bit line 15 remaining in the second direction D2 in the first via hole K2 forms a bit line 17. FIG. 12A is a perspective view of the bit line after formation in at least one embodiment of the present disclosure, FIG. 12B is a top view of FIG. 12A, FIG. 12C is a cross-sectional view of FIG. 12A along the AA direction, and the cross-sectional view of FIG. 12A along the CC direction can refer to FIG. 10D.

[0149] In some examples, as shown in FIGS. 12A-12C, after the formation of the bit line 17, the first protective layer 13 exposed by the first via hole K2 is retained, and the sidewall and bottom wall of the first trench T1 are exposed at the etched initial bit line 15.

[0150] (6) A first insulating film is deposited on the stack structure formed in the preceding step, filling the first via hole K2 in the first trench T1 and the groove formed by etching the initial bit line 15, and the stack structure is recovered. Subsequently, a plurality of capacitor regions Q are defined on the stack structure by photolithography, the capacitor regions Q at least partially overlap the first trench T1, and the bit line 17 is located on one side of the capacitor region Q along the first direction D1. The stack structure on the side of the capacitor region Q away from the bit line 17 is etched by photolithography along the third direction D3, and the surface of the capacitor region Q away from the bit line 17 is exposed. FIG. 13A is a schematic perspective view of the capacitor region after being exposed, and FIG. 13B is a sectional view of FIG. 13A along the AA direction. The sectional view of FIG. 13A along the CC direction can refer to FIG. 10D.

[0151] In some examples, as shown in FIGS. 13A and 13B, the orthographic projection of the capacitor region Q on the substrate 100 and the orthographic projection of the first trench T1 on the substrate 100 at least partially overlap along the third direction D3. The plurality of capacitor regions Q can be arranged in sequence along the second direction D2, and the number of the plurality of capacitor regions Q is not limited in the embodiment.

[0152] In some examples, when etching the stack structure on the side of the capacitor region Q away from the bit line 17, the etching can be stopped at the plane where the bottom wall of the first trench T1 is located, and the portion of the first insulating film 11 closest to the substrate 100 is retained. The sidewall of the first trench T1 away from the bit line 17 can be etched away. In some examples, when the stop layer is formed on the substrate 100, the etching can be stopped at the stop layer when etching the stack structure on the side of the capacitor region Q away from the bit line 17.

[0153] (7) The surface on the side of the capacitor region Q away from the bit line 17 is etched by wet etching along the first direction D1, the second insulating film 12 in the capacitor region Q is removed, and a first plate trench T2 is formed. The first plate trench T2 extends laterally in the layer where the second insulating film 12 is located along the first direction D1, and the opening of the first plate trench T2 is located away from the bit line 17. FIG. 14A is a schematic perspective view of the first plate trench after being formed, and FIG. 14B is a sectional view of FIG. 14A along the AA direction. FIG. 14C is a sectional view of FIG. 14A along the BB direction.

[0154] In some examples, as shown in FIGS. 14A to 14C, after the second insulating film 12 in the capacitor region Q is removed, the first protective layer 13 in the capacitor region Q is exposed. The sidewall of the first plate trench T2 along the second direction D2 is the first protective layer 13, the sidewall of the first plate trench T2 along the third direction D3 is the first insulating film 11, and the bottom wall is the second insulating film 12.

[0155] (8) A second conductive film and a second protective film are sequentially deposited from the side of the capacitor region Q away from the bit line, and the second conductive film and the second protective film are laterally etched along the side of the capacitor region Q away from the bit line using wet etching to remove the second conductive film and the second protective film outside the range of the first electrode groove T2, thereby forming a first electrode 20 and a second protective layer 21. FIG15A is a perspective schematic diagram of at least one embodiment of the present disclosure after the first electrode plate and the second protective layer are formed, FIG15B is a cross-sectional view of FIG15A along the AA direction, and FIG15C is a cross-sectional view of FIG15A along the BB direction.

[0156] In some examples, the second conductive film may include a metal material, such as titanium nitride, and the second protective film may include an oxide, such as aluminum oxide.

[0157] In some examples, as shown in Figures 15A to 15C , the first electrode plate 20 is closely attached to the inner wall of the first electrode plate slot T2. The first electrode plate 20 has a groove similar in shape to the first electrode plate slot T2. The second protective layer 21 fills the groove of the first electrode plate 20. The second protective layer 21 can provide support for the laminated structure. The first electrode plates 20 of different layers are disconnected from each other. In the second direction D2, the first electrode plates 20 are located on both sides of the first filling layer 14. In the plane of the second direction D2 and the third direction D3, the cross-section of the first electrode plate 20 can be in the shape of a square.

[0158] (9) The second protective layer 21 is removed, and a sixth insulating film, a third conductive film, and a first supporting film are sequentially deposited along the first direction D1 from the side of the capacitor region Q away from the bit line 17 to form a first dielectric layer 22, a second electrode 23, and a first supporting layer 24. FIG16A is a perspective schematic diagram after the first supporting layer is formed in at least one embodiment of the present disclosure, FIG16B is a top view of FIG16A, FIG16C is a cross-sectional view of FIG16A along the AA direction, and FIG16D is a cross-sectional view of FIG16A along the BB direction.

[0159] In some examples, the sixth insulating film can be made of a high-k dielectric material, such as a dielectric material with a dielectric constant K ≥ 3.9. The High-k dielectric material can include, but is not limited to, at least one of the following: silicon oxide, hafnium oxide, and helium-zirconium-aluminum (Hf-Zr-Al). The sixth insulating film can be a single layer or a stacked layer structure. The third conductive film can be made of a metal material, such as titanium nitride. The first supporting film can be made of polysilicon.

[0160] In some examples, as shown in Figures 16A to 16D, the first dielectric layer 22 is tightly attached to the groove of the first plate 20. The first dielectric layers 22 of the entire stacked structure are interconnected and cover the first plates 20 of different layers. The second plate 23 is located on the side of the first dielectric layer 22 away from the first plate 20. The first dielectric layer 22 is separated from the second plate 23 and the first plate 20, forming two plates of the capacitor. The first support layer 24 is located on the side of the second plate 23 away from the first plate 20. The second plate 23 has a groove similar in shape to the first plate groove T2. The first support layer 24 fills the groove of the second plate 23 and can completely fill the stacked structure on the side of the capacitor region Q away from the bit line 17. The first support layer 24 can provide support for the stacked structure. The cross-section of the second plate 23 in the plane of the second direction D2 and the third direction D3 can be in the shape of a "square", with the first plate 20 surrounding the outside of the second plate 23.

[0161] (10) The stacked structure is photolithographically etched in the third direction D3 to remove the first filling layer 14 located in the capacitor region Q. FIG17A is a perspective schematic diagram of at least one embodiment of the present disclosure after the first filling layer in the capacitor region is removed, FIG17B is a top view of FIG17A, FIG17C is a cross-sectional view of FIG17A along the AA direction, and FIG17D is a cross-sectional view of FIG17A along the BB direction.

[0162] In some examples, as shown in FIG. 17A to FIG. 17D , after the first filling layer 14 in the capacitor region Q is removed, the first protection layer 13 in the capacitor region Q is exposed.

[0163] Subsequently, the first protective layer 13 is wet-etched along the second direction D2 within the capacitor region Q to remove the first protective layer 13 within the capacitor region Q, exposing the first electrode 20 in the second direction D2. Figure 18A is a perspective schematic diagram of at least one embodiment of the present disclosure after the first protective layer within the capacitor region has been removed, Figure 18B is a top view of Figure 18A, Figure 18C is a cross-sectional view of Figure 18A taken along line AA, and Figure 18D is a cross-sectional view of Figure 18A taken along line BB.

[0164] In some examples, as shown in FIG. 18A to FIG. 18D , after the first protection layer 13 located in the capacitor region Q is removed, the first electrode 20 is exposed inside the stacked structure along the first direction D1 .

[0165] Then, the first insulating film 11 is etched by wet etching in the second direction D2 within the capacitor region Q, and the first insulating film 11 within the capacitor region Q is removed, and the first plate 20 is exposed in the third direction D3. Since the capacitor region Q is supported on both sides in the first direction D1, the collapse of the stacked structure does not occur. FIG. 19A is a perspective view of the semiconductor device after the first insulating film within the capacitor region is removed, and FIG. 19B is a cross-sectional view of FIG. 19A along the BB direction.

[0166] In some examples, as shown in FIGS. 19A and 19B, within the capacitor region Q, the first insulating film 11 above the bottom wall of the first trench T1 is removed, and after this step, the first plate 20 within the capacitor region Q is exposed, which facilitates the subsequent formation of the third plate of the capacitor.

[0167] Then, the seventh insulating film, the fourth conductive film, and the second support film are sequentially deposited within the capacitor region Q to form the second dielectric layer 25, the third plate 26, and the second support layer 27. FIG. 20A is a perspective view of the semiconductor device after the second support layer is formed, FIG. 20B is a top view of FIG. 20A, FIG. 20C is a cross-sectional view of FIG. 20A along the AA direction, and the cross-sectional view of FIG. 20A along the BB direction can be referred to FIG. 4.

[0168] In some examples, as shown in FIGS. 20A to 20C, the second dielectric layer 25 surrounds the outside of the first plate 20, the third plate 26 surrounds the outside of the second dielectric layer 25, and the second support layer 27 fills the outside of the third plate 26 and fills the entire stacked structure of the capacitor region Q. The capacitor of the semiconductor device includes the first plate 20, the second plate 23, and the third plate 26, and in the plane of the second direction D2 and the third direction D3, the third plate 26 surrounds the outside of the first plate 20, the first plate 20 surrounds the outside of the second plate 23, the second dielectric layer 25 fills between the third plate 26 and the first plate 20, and the first dielectric layer 22 fills between the first plate 20 and the second plate 23.

[0169] In some examples, the first plate 20 surrounds the outside of the second plate 23, and the third plate 26 surrounds the outside of the first plate 20 to form a double-layer capacitor. Compared with the single-layer capacitor (only a single upper plate and a single lower plate are provided) in the conventional structure, the double-layer capacitor of the present embodiment has two additional contact surfaces, which reduces the area occupied by the capacitor when the size of the capacitor is unchanged, thereby reducing the volume of the semiconductor device. In addition, when the lateral etching is performed, since the length of the double-layer capacitor is smaller, the risk of collapse of the stacked structure is reduced.

[0170] (11) In the third direction D3, a plurality of transistor regions G are defined on the stack structure by lithography, the stack structure is divided into the plurality of transistor regions G by the first trench T1, and the bit line 17 is located in the transistor region G. The stack structure is etched in the third direction D3 to expose a side surface of the transistor region in the first direction D1. FIG. 21A is a perspective view of the stack structure after the transistor region is exposed, and FIG. 21B is a cross-sectional view of FIG. 21A along the AA direction. A cross-sectional view of FIG. 21A along the CC direction can be referred to FIG. 10D.

[0171] In some examples, as shown in FIGS. 21A and 21B, the transistor region G and the capacitor region Q are adjacent to each other. The plurality of transistor regions G can be arranged in sequence in the second direction D2, and the number of the plurality of transistor regions G is not limited in the present embodiment.

[0172] In some examples, when the stack structure on the side of the transistor region G in the first direction D1 is etched, the etching can be stopped at a plane where the bottom wall of the first trench T1 is located, and a portion of the first insulating film 11 closest to the substrate 100 is reserved.

[0173] Subsequently, the surface of the transistor region G exposed on the side of the transistor region G in the first direction D1 is wet-etched in the first direction D1 to remove the second insulating film 12 in the transistor region G, expose the surface of the first plate 20, and form a transistor trench T3. FIG. 22A is a perspective view of the stack structure after the transistor trench is formed, FIG. 22B is a cross-sectional view of FIG. 22A along the AA direction, and FIG. 22C is a cross-sectional view of FIG. 22A along the CC direction.

[0174] In some examples, as shown in FIGS. 22A to 22C, the extension direction of the transistor trench T3 is parallel to the substrate 100, the bottom wall of the transistor trench T3 is the first plate 20, the side wall of the transistor trench T3 in the second direction D2 is the first protective layer 13, the second filling layer 16, and the bit line 17, and the side wall of the transistor trench T3 in the third direction D3 is the first insulating film 11. In the plane parallel to the substrate 100, the transistor trench T3 surrounds the second filling layer 16 and the bit line 17, and a transistor of a semiconductor device will be subsequently formed in the transistor trench T3. After the transistor trench T3 is formed, the second insulating film 12 of the stack structure is completely removed.

[0175] Subsequently, the first semiconductor thin film, the eighth insulating thin film and the fifth conductive thin film are sequentially deposited on one side of the transistor region G in the first direction D1 by atomic layer deposition, and part of the fifth conductive thin film, the eighth insulating thin film and the first semiconductor thin film on one side of the transistor region G in the first direction D1 are removed to disconnect the first semiconductor thin film between adjacent transistors in the second direction and the first semiconductor thin film between adjacent transistors in the direction perpendicular to the substrate, thereby forming the semiconductor layer 31, the gate insulating layer 32 and the gate electrode 33. FIG. 23A is a schematic perspective view after forming the gate electrode in at least one embodiment of the present disclosure, FIG. 23B is a top view of FIG. 23A, FIG. 23C is a sectional view of FIG. 23A along the direction of AA, and FIG. 23D is a sectional view of FIG. 23A along the direction of BB. The sectional views can be referred to FIG. 5.

[0176] In some examples, the material of the eighth insulating thin film can be a high dielectric constant dielectric material, for example, can be an aluminum oxide, a hafnium oxide or the like. The material of the first semiconductor thin film can be a semiconductor, for example, IGZO, and the material of the fifth conductive thin film can be a metal oxide material, which can be Indium Gallium Zinc Oxide (IGZO). When the metal oxide material is IGZO, the leakage current of the transistor is small, thereby ensuring the low refresh rate of the dynamic memory. In some examples, the material of the metal oxide can also be ITO, IWO, ZnOx, InOx, In2O3, InWO, SnO2, TiOx, InSnOx, ZnxOyNz, MgxZnyOz, InxZnyOz, InxGayZnzOa, ZrxInyZnzOa, HfxInyZnzOa, SnxInyZnzOa, AlxSnyInzZnaOd, SixInyZnzOa, ZnxSnyOz, AlxZnySnzOa, GaxZnySnzOa, ZrxZnySnzOa, InGaSiO, IAZO, IGO, IZO (indium-zinc-oxide), IZOx or the like, as long as the leakage current of the transistor can meet the requirements, which can be adjusted according to actual conditions.

[0177] In some examples, as shown in FIGS. 23A-23C, the semiconductor layer 31 is in close contact with the inner wall of the transistor trench T3, and the semiconductor layer 31 is in contact with the exposed first electrode plate 20. The part of the first electrode plate 20 in contact with the semiconductor layer 31 can be reused as the second electrode of the transistor. The semiconductor layer 31 is in contact with the exposed bit line 17. The part of the bit line 17 in contact with the semiconductor layer 31 can be reused as the first electrode of the transistor. The semiconductor layer 31 is formed with a groove similar in shape to the transistor trench T3. The gate insulating layer 32 is in close contact with the groove of the semiconductor layer 31. The gate insulating layer 32 is formed with a groove similar in shape to the groove of the semiconductor layer 31 on the side away from the semiconductor layer 31. The gate electrode 33 is filled in the groove of the gate insulating layer 32.

[0178] The semiconductor layer 31 and the gate insulating layer 32 in the semiconductor region G are subjected to wet etching to disconnect the transistors between different layers and different columns from each other, thereby removing the parasitic channel. The first insulating film is deposited in the semiconductor region G along the first direction D1 so that the first insulating film fills the transistor trench T3. The first insulating film in the transistor trench T3 is etched again to expose the gate electrode 33 again. FIG. 24 is a schematic perspective view showing the semiconductor device after the gate electrode 33 is exposed again according to at least one embodiment of the present disclosure.

[0179] In some examples, as shown in FIG. 24, the first insulating film can cover the edge of the semiconductor layer 31 by backfilling the first insulating film in the transistor trench T3, thereby avoiding the contact between the semiconductor layer 31 and the subsequently formed word line.

[0180] Subsequently, the sixth conductive film is deposited in the transistor region G along the first direction D1, and the sixth conductive film is etched to form the word line 34 in the transistor trench T3. The third support film is deposited in the transistor region G along the first direction D1 to form the third support layer 35 on the stack structure, and the third support layer 35 fills the stack structure on the side of the word line 34 from which the first insulating film is removed.

[0181] At this point, the semiconductor device shown in FIG. 1 is prepared.

[0182] The semiconductor device in FIG. 4 is prepared in a process substantially the same as that of the semiconductor device shown in FIG. 1, except for the process of forming the bit line 17. The process of forming the bit line 17 of the semiconductor device shown in FIG. 4 is briefly described below, and the processes of forming the remaining structures can be referred to the above description of the process of preparing the semiconductor device shown in FIG. 1.

[0183] (21) After the above step (3) is completed, the first insulating film 11 is laterally etched in the second direction D2 within the bit line via hole K1, the first insulating film 11 on both sides of the bit line via hole K1 in the second direction D2 is removed, and the adjacent bit line via holes K1 are connected to each other. Since the size of the bit line via hole K1 is small, and the second insulating film 12 on both sides of the bit line via hole K1 in the second direction D2 serves as a support, the stacked structure will not collapse. FIG. 25 is a sectional view of the bit line via hole in the second direction after the first insulating film on both sides of the bit line via hole in the second direction is removed.

[0184] In some examples, as shown in FIG. 25, after the first insulating film 11 on both sides of the bit line via hole K1 in the second direction D2 is removed, the adjacent bit line via holes K1 are connected to each other. The bit line via hole K1 exposes the first protective layer 13 in the third direction D3, and the connected part of the adjacent bit line via holes K1 exposes the first insulating film 11.

[0185] Subsequently, the above step (4) and the subsequent steps can be continued. After the first conductive film is deposited in step (4) to form the initial bit line 15, the initial bit line also fills the position of the first insulating film removed in step (21), so that in the second direction D2, the initial bit lines 15 located in the adjacent bit line via holes are connected to each other, and the subsequent adjacent bit lines 17 located in the adjacent bit line via holes are also connected to each other, thereby forming a bit line 17 surrounding the semiconductor layer 31.

[0186] The semiconductor device provided by the embodiments of the present disclosure is provided with a plurality of layers of storage units arranged in a direction perpendicular to the substrate, each layer of storage units is connected with a word line arranged in the layer, a single storage unit can include a transistor and a capacitor, a bit line extends in a direction perpendicular to the substrate, a plurality of transistors in the direction of extension of the bit line are connected with the bit line, and the bit line is located on one side of the semiconductor layer and connected with the semiconductor layer. The storage unit of this structure is helpful for subsequent wiring, reduces the parasitic capacitance of the wiring, not only helps to form a memory device in subsequent wiring, but also helps to reduce the device area, is more friendly to circuit load, and is also helpful for signal reading of the SA circuit of the memory device.

[0187] The method for manufacturing a semiconductor device provided by the embodiments of the present disclosure adopts a multi-layer stack of a first insulating film and a second insulating film, forms a support structure in a first trench, and then manufactures a capacitor and a transistor on both sides of the first direction of the stack structure. By defining the bit line, word line, transistor and capacitor area in advance, the vertical bit line is manufactured first, which helps to increase the bit line spacing, reduce the capacitive coupling between the bit lines, and reduce the circuit load. Then the capacitor is manufactured, and by adding a layer of capacitor plate, the capacitance can be increased without increasing the occupied area. Finally, the transistor and the word line are manufactured, the transistor uses lateral atomic layer deposition, and the wet etching is used to remove the parasitic MOS between the layers and columns. This manufacturing method has simple steps, easy removal of parasitic channels, reduces the process difficulty, and is conducive to the realization of multi-layer stack.

[0188] The embodiments of the present disclosure also provide a method for manufacturing a semiconductor device, including: providing a substrate, sequentially and alternately depositing a first insulating film and a second insulating film on the substrate to form a stack structure; forming a plurality of first trenches perpendicular to the substrate on the stack structure, the plurality of first trenches are sequentially arranged along a second direction parallel to the substrate, and the first trenches divide the stack structure into a plurality of transistor regions arranged along the second direction; forming a bit line in the first trench, the bit line penetrates different layers and extends along a direction perpendicular to the substrate; etching the second insulating film in the transistor region along a direction parallel to the substrate to form a plurality of transistor trenches; the transistor trenches extend along the first direction and expose the bit line, the first direction is in a plane parallel to the substrate and perpendicular to the second direction; the plurality of transistor trenches are sequentially arranged along a direction perpendicular to the substrate; sequentially depositing a semiconductor layer and a gate electrode in the transistor trenches; the semiconductor layer extends along the first direction and closely adheres to the inner wall of the transistor trench, and the semiconductor layers of a plurality of transistors arranged along a direction perpendicular to the substrate are connected to the same bit line; the gate electrode extends along the first direction, and the semiconductor layer surrounds the gate electrode.

[0189] In an example, before forming the plurality of transistor trenches, the method further comprises: defining a capacitor region on the stack structure, the capacitor region at least partially overlapping the first trench, the bit line being located on one side of the capacitor region in the first direction; etching a surface of the capacitor region away from the bit line in a direction parallel to the substrate to remove the second insulating film in the capacitor region, forming a plurality of first plate slots, the first plate slots extending along the first direction, the plurality of first plate slots being arranged in sequence in a direction perpendicular to the substrate; forming the first plate in the first plate slots by deposition from the side of the capacitor region away from the bit line in a direction parallel to the substrate; the first plate extending along the first direction and abutting the inner wall of the first plate slot; the first plate being in contact with the semiconductor layer, the portion of the first plate in contact with the semiconductor layer being reused as the second electrode of the transistor.

[0190] In an example, the capacitor further comprises a second plate and a third plate; the method further comprises: sequentially depositing a sixth insulating film, a third conductive film and a first support film from the side of the capacitor region away from the bit line in a direction parallel to the substrate to form a first dielectric layer, a second plate and a first support layer; the first dielectric layer abutting the first plate, the first dielectric layers in different layers being connected to each other; the second plate abutting the first dielectric layer, the second plates in different layers being connected to each other; the first support layer filling in the second plate; in a plane perpendicular to the substrate and the first direction, the first plate is wrapped outside the first dielectric layer, the first dielectric layer is wrapped outside the second plate, and the second plate is wrapped outside the first support layer; etching the stack structure in the capacitor region to expose the first plate in the capacitor region; sequentially depositing a seventh insulating film, a fourth conductive film and a second support film in the capacitor region to form a second dielectric layer, a third plate and a second support layer; the second dielectric layer wrapped outside the first plate, the third plate wrapped outside the second dielectric layer, and the second support layer filling outside the third plate and filling the entire capacitor region; in a plane perpendicular to the substrate and the first direction, the third plate is wrapped outside the first plate.

[0191] In an example, the sequentially depositing the semiconductor layer and the gate electrode in the transistor trench comprises: sequentially depositing a first semiconductor thin film, an eighth insulating thin film and a fifth conductive thin film from one side of the transistor region in the first direction, and removing the fifth conductive thin film, the eighth insulating thin film and the first semiconductor thin film from the one side of the transistor region in the first direction to disconnect the first semiconductor thin film between adjacent transistors in the second direction and the first semiconductor thin film between adjacent transistors in a direction perpendicular to the substrate, thereby forming the semiconductor layer, the gate insulating layer and the gate electrode; wherein the semiconductor layer is a cylindrical structure with an opening facing the first direction, the cylindrical structure comprises an inner surface forming a hollow portion and an outer surface other than the inner surface; the gate electrode is located in the hollow portion of the cylindrical structure, the inner surface of the semiconductor layer surrounds the gate insulating layer, and the gate insulating layer surrounds the gate electrode; in the first direction, the size of the gate electrode protruding out of the cylindrical structure is greater than the size of the gate insulating layer protruding out of the cylindrical structure.

[0192] In an example, the memory unit further comprises word lines distributed in different layers and extending in a direction parallel to the substrate; the method further comprises: depositing a sixth conductive thin film from one side of the transistor region in the first direction, and etching the sixth conductive thin film to form the word lines extending in the second direction in the transistor trench; the part of the gate electrode protruding out of the cylindrical structure is electrically connected to the word line arranged in the same layer.

[0193] In an example, the semiconductor layer is in contact with two bit lines, the two bit lines are located at opposite sides of the semiconductor layer along the second direction; the forming the bit line in the first trench comprises: sequentially forming a first protective layer and a first filling layer in the first trench by deposition, the first protective layer is in close contact with the inner wall of the first trench, and the first filling layer fills the first trench; defining a plurality of bit line regions on the stack structure, removing the first filling layer in the bit line regions to form initial bit line through holes; removing the first protective layer in the initial bit line through holes along the second direction to form bit line through holes; the orthographic projection of the bit line region on the substrate is located in the range of the first trench, and a plurality of the bit line regions are arranged in sequence along the second direction; depositing a first conductive film in the bit line through holes, and removing the first conductive film and the first protective layer close to one side of the substrate in the bit line through holes to form an initial bit line; depositing a fifth insulating film in the bit line through holes to form a second filling layer; the initial bit line is in close contact with the bit line through hole, and the second filling layer fills the bit line through hole; defining a plurality of first punching regions in a direction perpendicular to the substrate, a plurality of the first punching regions are located at both sides of the bit line through hole along the first direction and in the range of the first trench; removing the first filling layer in the first punching region to form a first through hole; etching away the exposed initial bit line in the first through hole along the first direction to form the bit line.

[0194] In an example, the semiconductor layer is in contact with a bit line, and the bit line surrounds the semiconductor layer. Forming the bit line in the first trench includes: sequentially forming a first protective layer and a first filling layer in the first trench by deposition, the first protective layer abutting the inner wall of the first trench, and the first filling layer filling the first trench; defining a plurality of bit line regions on the stack structure, removing the first filling layer in the bit line regions to form initial bit line holes; removing the first protective layer in the initial bit line holes in the second direction to form bit line holes; the orthographic projection of the bit line regions on the substrate is within the range of the first trench, and the plurality of bit line regions are arranged in sequence along the second direction; etching the first insulating film in the bit line holes along the second direction to make the adjacent bit line holes communicate with each other; depositing a first conductive film in the bit line holes, and removing the first conductive film and the first protective layer in the bit line holes close to the substrate to form initial bit lines; depositing a fifth insulating film in the bit line holes to form a second filling layer; the initial bit lines abut the bit line holes, and the second filling layer fills the bit line holes; defining a plurality of first punching regions in a direction perpendicular to the substrate, the plurality of first punching regions are located on both sides of the bit line holes along the first direction and within the range of the first trench; removing the first filling layer in the first punching regions to form first holes; etching the exposed initial bit lines in the first holes along the first direction to form the bit lines.

[0195] The embodiments of the present disclosure further provide an electronic device including the semiconductor device described above. The electronic device can be a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, a mobile power supply, or the like. The storage device can include a memory in a computer, and the like, which is not limited herein.

[0196] Although the embodiments of the present disclosure are described above, the content described above is only the embodiments adopted for the purpose of facilitating the understanding of the present disclosure, and is not intended to limit the present disclosure. Any person skilled in the art of the present disclosure can make any modification and change in the form and details without departing from the spirit and scope of the present disclosure, but the patent protection scope of the present disclosure shall be subject to the scope defined by the appended claims.

Claims

1. A semiconductor device comprising: Multiple memory cells are stacked in a direction perpendicular to the substrate and periodically distributed in different layers; The memory cell includes a transistor, the transistor including at least a semiconductor layer and a gate electrode, the gate electrode and the semiconductor layer extending along a first direction parallel to the substrate, and the semiconductor layer surrounding the gate electrode; A bit line, penetrating the different layers and extending in a direction perpendicular to the substrate; The semiconductor layers of the plurality of transistors arranged in a direction perpendicular to the substrate are connected to the same bit line.

2. The semiconductor device according to claim 1, wherein The semiconductor layer of the transistor is a cylindrical structure with an opening facing the first direction, and the cylindrical structure includes an inner surface constituting a hollow portion and an outer surface other than the inner surface; The gate electrode of the transistor is located in the hollow portion of the cylindrical structure, the inner surface surrounds the gate electrode, and the gate electrode is insulated from the semiconductor layer; The bit line contacts a portion of the outer surface of the tubular structure that is parallel to the first direction, and a portion of the bit line that contacts the semiconductor layer is reused as a first electrode of the transistor.

3. The semiconductor device according to claim 2, wherein The transistor also includes a gate insulating layer arranged between the gate electrode and the semiconductor layer; the semiconductor layer surrounds the gate insulating layer, and the gate insulating layer surrounds the gate electrode; in the first direction, the size of the tubular structure of the gate electrode protruding from the semiconductor layer is larger than the size of the gate insulating layer protruding from the tubular structure.

4. The semiconductor device according to claim 2, wherein The semiconductor layer contacts two bit lines. The two bit lines are located at opposite sides of the semiconductor layer along a second direction. The second direction is parallel to the substrate and perpendicular to the first direction.

5. The semiconductor device according to claim 2, wherein The semiconductor layer contacts a bit line, and the bit line surrounds the semiconductor layer.

6. The semiconductor device according to claim 3, further comprising: A plurality of word lines are distributed in different layers and extend in a direction parallel to the substrate; a portion of the gate electrode protruding from the tubular structure is electrically connected to the word lines arranged in the same layer.

7. The semiconductor device according to claim 2, wherein The memory cell further includes: a capacitor distributed in different layers; the capacitor is located on one side of the transistor along the first direction; The capacitor includes a first electrode plate, which contacts a portion of the outer surface of the semiconductor layer away from the opening. The portion of the first electrode plate contacting the semiconductor layer is reused as the second electrode of the transistor.

8. The semiconductor device according to claim 7, wherein The capacitor further includes a second plate and a third plate; in a plane perpendicular to the substrate and the first direction, the first plate surrounds the outside of the second plate, and the third plate surrounds the outside of the first plate.

9. A method for preparing a semiconductor device, comprising: Providing a substrate, and alternately depositing a first insulating film and a second insulating film on the substrate to form a stacked structure; forming a plurality of first trenches perpendicular to the substrate on the stacked structure, wherein the plurality of first trenches are sequentially arranged along a second direction parallel to the substrate, and the first trenches divide the stacked structure into a plurality of transistor regions arranged along the second direction; forming a bit line in the first trench, wherein the bit line penetrates different layers and extends in a direction perpendicular to the substrate; Etching the second insulating film in the transistor region along a direction parallel to the substrate to form a plurality of transistor trenches; The transistor trench extends along a first direction and exposes the bit line, wherein the first direction is in a plane parallel to the substrate and perpendicular to the second direction; a plurality of the transistor trenches are arranged in sequence along a direction perpendicular to the substrate; A semiconductor layer and a gate electrode are sequentially deposited in the transistor trench; the semiconductor layer extends along the first direction and adheres closely to the inner wall of the transistor trench, and the semiconductor layers of the plurality of transistors arranged perpendicular to the substrate direction are connected to the same bit line; the gate electrode extends along the first direction, and the semiconductor layer surrounds the gate electrode.

10. The manufacturing method according to claim 9, before forming the plurality of transistor trenches, the method further comprises: A capacitor region is defined on the stacked structure, the capacitor region at least partially overlaps with the first trench, and the bit line is located on one side of the capacitor region in the first direction; Etching a surface of the capacitor region away from the bit line in a direction parallel to the substrate to remove the second insulating film in the capacitor region to form a plurality of first electrode plate grooves, wherein the first electrode plate grooves extend along the first direction and are sequentially arranged in a direction perpendicular to the substrate; In a direction parallel to the substrate, the first electrode plate is formed by deposition in the first electrode plate groove from a side of the capacitor region away from the bit line; the first electrode plate extends along the first direction and is closely attached to an inner wall of the first electrode plate groove; The first electrode plate is in contact with the semiconductor layer, and a portion of the first electrode plate in contact with the semiconductor layer is reused as a second electrode of the transistor.

11. The preparation method according to claim 10, further comprising: In a direction parallel to the substrate, a sixth insulating film, a third conductive film, and a first supporting film are sequentially deposited from a side of the capacitor region away from the bit line to form a first dielectric layer, a second electrode plate, and a first supporting layer; the first dielectric layer is closely attached to the first electrode plate, and the first dielectric layers located at different layers are connected to each other; the second electrode plate is closely attached to the first dielectric layer, and the second electrode plates located at different layers are connected to each other; and the first supporting layer is filled in the second electrode plate; In a plane perpendicular to the substrate and the first direction, the first electrode plate surrounds the outside of the first dielectric layer, the first dielectric layer surrounds the outside of the second electrode plate, and the second electrode plate surrounds the outside of the first supporting layer; The stacked structure is etched in the capacitor region to expose the first electrode in the capacitor region; a seventh insulating film, a fourth conductive film, and a second supporting film are sequentially deposited in the capacitor region to form a second dielectric layer, a third electrode plate, and a second supporting layer; the second dielectric layer surrounds the outside of the first electrode plate, the third electrode plate surrounds the outside of the second dielectric layer, and the second supporting layer fills the outside of the third electrode plate and fills the entire capacitor region; In a plane perpendicular to the substrate and the first direction, the third electrode plate surrounds the outer side of the first electrode plate.

12. The preparation method according to claim 10, wherein The step of sequentially depositing a semiconductor layer and a gate electrode in the transistor trench comprises: In a direction parallel to the substrate, a first semiconductor film, an eighth insulating film, and a fifth conductive film are sequentially deposited from one side of the transistor region in the first direction, and a portion of the fifth conductive film, the eighth insulating film, and the first semiconductor film on one side of the transistor region along the first direction is removed to disconnect the first semiconductor film between adjacent transistors along the second direction and the first semiconductor film between adjacent transistors along a direction perpendicular to the substrate. A semiconductor thin film, forming the semiconductor layer, the gate insulating layer and the gate electrode; wherein the semiconductor layer is a tubular structure with an opening toward the first direction, the tubular structure includes an inner surface constituting a hollow portion and an outer surface other than the inner surface; the gate electrode is located in the hollow portion of the tubular structure, the inner surface of the semiconductor layer surrounds the gate insulating layer, and the gate insulating layer surrounds the gate electrode; in the first direction, the size of the gate electrode protruding from the tubular structure of the semiconductor layer is larger than the size of the gate insulating layer protruding from the tubular structure.

13. The preparation method according to claim 12, further comprising: Depositing a sixth conductive film from one side of the transistor region in the first direction in a direction parallel to the substrate, and etching the sixth conductive film to form a word line extending along the second direction in the transistor trench; The portion of the gate electrode protruding from the tubular structure is electrically connected to the word line provided in the same layer.

14. The preparation method according to claim 9, wherein The semiconductor layer is in contact with the two bit lines, and the two bit lines are located on opposite sides of the semiconductor layer along the second direction; and forming the bit lines in the first trench includes: forming a first protective layer and a first filling layer in the first trench by deposition in sequence, wherein the first protective layer is closely attached to the inner wall of the first trench, and the first filling layer completely fills the first trench; A plurality of bit line regions are defined on the stacked structure, the first filling layer in the bit line regions is removed to form initial bit line through holes; the first protection layer in the initial bit line through holes located in the second direction is removed to form bit line through holes; the orthographic projections of the bit line regions on the substrate are located within the range of the first trench, and the plurality of bit line regions are sequentially arranged along the second direction; Depositing a first conductive film in the bit line through hole, and removing the first conductive film and the first protective layer located on the side of the bit line through hole close to the substrate to form an initial bit line; depositing a fifth insulating film in the bit line through hole to form a second filling layer; the initial bit line is closely attached to the bit line through hole, and the second filling layer completely fills the bit line through hole; A plurality of first punching areas are defined in a direction perpendicular to the substrate, and the plurality of first punching areas are located on both sides of the bit line through hole along the first direction and within the range of the first groove; the first filling layer in the first punching area is removed to form a first through hole; and the exposed initial bit line is etched away along the first direction in the first through hole to form the bit line.

15. The preparation method according to claim 9, wherein The semiconductor layer contacts one of the bit lines, and the bit line surrounds the semiconductor layer; and forming the bit line in the first trench includes: forming a first protective layer and a first filling layer in the first trench by deposition in sequence, wherein the first protective layer is closely attached to the inner wall of the first trench, and the first filling layer completely fills the first trench; A plurality of bit line regions are defined on the stacked structure, the first filling layer in the bit line regions is removed to form initial bit line through holes; the first protection layer located in the second direction of the initial bit line through holes is removed to form bit line through holes; the orthographic projections of the bit line regions on the substrate are located within the range of the first trench, and the plurality of bit line regions are sequentially arranged along the second direction; Etching the first insulating film along the second direction in the bit line through hole so that adjacent bit line through holes are connected to each other; Depositing a first conductive film in the bit line through hole, and removing the first conductive film and the first protective layer located on the side of the bit line through hole close to the substrate to form an initial bit line; depositing a fifth insulating film in the bit line through hole to form a second filling layer; the initial bit line is closely attached to the bit line through hole, and the second filling layer completely fills the bit line through hole; A plurality of first punching areas are defined in a direction perpendicular to the substrate, and the plurality of first punching areas are located on both sides of the bit line through hole along the first direction and within the range of the first groove; the first filling layer in the first punching area is removed to form a first through hole; and the exposed initial bit line is etched away along the first direction in the first through hole to form the bit line. 16 . An electronic device comprising the semiconductor device according to claim 1 .

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