Display substrate and preparation method therefor, and display apparatus

Abstract

The present disclosure belongs to the technical field of display. Provided are a display substrate and a preparation method therefor, and a display apparatus, which can solve the problem where existing pixel defining layers can be made of black materials, but have a poor liquid-repellent performance, which affects the uniformity of formed organic thin film layers. The display substrate in the present disclosure comprises a base and a pixel defining layer located on the base. The pixel defining layer comprises a plurality of pixel barriers, wherein each pixel barrier comprises a barrier layer and a plurality of nano-microstructures that are sequentially arranged in a direction away from the base, and an air film is formed around the nano-microstructures.

Description

Display substrate, preparation method thereof and display device TECHNICAL FIELD

[0001] The present disclosure belongs to the technical field of display, and particularly relates to a display substrate, a preparation method thereof and a display device. BACKGROUND

[0002] An organic light-emitting diode (OLED) is a light-emitting device using an organic solid-state semiconductor as a light-emitting material, and has a broad application prospect due to its simple preparation process, low cost, low power consumption, high luminous brightness and wide working temperature range. SUMMARY

[0003] The present disclosure aims to at least solve one of the technical problems existing in the prior art, and provides a display substrate, a preparation method thereof and a display device.

[0004] In a first aspect, the present disclosure provides a display substrate, comprising: a substrate, a pixel definition layer on the substrate; the pixel definition layer comprises: a plurality of pixel barriers.

[0005] The pixel barrier comprises: a blocking layer and a plurality of nano microstructures arranged in sequence in a direction away from the substrate; and an air film is formed around the nano microstructure.

[0006] In some embodiments, the ratio of the height of the blocking layer to the height of the pixel barrier is 0 to 0.5.

[0007] In some embodiments, the ratio of the height of the nano microstructure to the height of the pixel barrier is 0.5 to 1.0.

[0008] In some embodiments, the height of the pixel barrier is 1 micrometer to 2 micrometers, the height of the blocking layer is 0 micrometer to 1 micrometer, and the height of the nano microstructure is 0.5 micrometer to 2 micrometers.

[0009] In some embodiments, the height of each blocking layer is equal, and / or the height of each nano microstructure is equal.

[0010] In some embodiments, the ratio of the gap width between adjacent nano microstructures to the width of the nano microstructure is 1.0 to 2.5.

[0011] In some embodiments, the gap width between adjacent nano microstructures is 100 nanometers to 200 nanometers, and the width of the nano microstructure is 80 nanometers to 100 nanometers.

[0012] In some embodiments, the nanostructure is a nanopillar.

[0013] In some embodiments, the blocking layer and the nanostructure are both made of light-absorbing material.

[0014] In some embodiments, the blocking layer and the nanostructure are integrally formed.

[0015] In some embodiments, the pixel defining layer further comprises a receiving portion between adjacent pixel barriers.

[0016] The receiving portion has an inverted-trapezoidal cross-sectional shape perpendicular to the substrate.

[0017] In some embodiments, the display substrate further comprises a driving circuit layer and a plurality of light-emitting devices; the light-emitting device comprises a first electrode and a second electrode arranged oppositely, and a light-emitting layer between the first electrode and the second electrode.

[0018] The driving circuit layer is between the substrate and the pixel defining layer.

[0019] The first electrode is connected to the driving circuit layer and exposed by the receiving portion.

[0020] The light-emitting layer is in the receiving portion.

[0021] The second electrode covers the light-emitting layer and the nanostructure.

[0022] In some embodiments, the driving circuit layer comprises a plurality of thin film transistors; the thin film transistor comprises an active layer, a gate insulating layer, a gate electrode, an interlayer insulating layer, a source electrode and a drain electrode arranged in sequence away from the substrate; the display substrate further comprises a planarization layer.

[0023] The source electrode and the drain electrode are respectively connected to two ends of the active layer through a via hole penetrating through the interlayer insulating layer and the gate insulating layer.

[0024] The planarization layer covers the source electrode and the drain electrode.

[0025] The first electrode is connected to the drain electrode through a via hole penetrating through the planarization layer.

[0026] In a second aspect, the embodiments of the present disclosure provide a display device, wherein the display device comprises the display substrate provided in the above.

[0027] In a third aspect, the embodiments of the present disclosure provide a preparation method of a display substrate, wherein the preparation method of the display substrate comprises:

[0028] forming a pixel defining material layer on the substrate;

[0029] etching the pixel defining material layer to form a plurality of pixel barriers;

[0030] etching the pixel barriers to form a barrier layer and a plurality of nano microstructures on the barrier layer, so that an air film is formed around the nano microstructures. BRIEF DESCRIPTION OF DRAWINGS

[0031] FIG. 1 is a structural schematic diagram of an exemplary display substrate.

[0032] FIG. 2 is a structural schematic diagram of a display substrate provided by an embodiment of the present disclosure.

[0033] FIG. 3 is a schematic diagram of a partial structure of the display substrate shown in FIG. 2.

[0034] FIG. 4 is a structural schematic diagram of an exemplary pixel driving circuit.

[0035] FIG. 5 is a flowchart of a preparation method of a display panel provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0036] In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. The components of the embodiments of the present disclosure described and shown in the drawings herein can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present disclosure provided in the drawings is not intended to limit the scope of the claimed present disclosure, but only represents selected embodiments of the present disclosure. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present disclosure.

[0037] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the ordinary meaning of such terms for a person skilled in the art to which the present disclosure pertains. The terms "first", "second" and similar terms used in the present disclosure do not denote any order, quantity or importance, but are used to distinguish different components. Similarly, the terms "one", "a" or "the" and similar terms do not denote a quantity restriction, but mean that there is at least one. The terms "include", "comprise" and similar terms mean that the elements or objects before the terms encompass the elements or objects listed after the terms and their equivalents, and do not exclude other elements or objects. The terms "connect" or "connected" and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms "upper", "lower", "left", "right" and the like are only used to represent relative positional relationships, and when the absolute positions of the described objects are changed, the relative positional relationships can also be changed accordingly.

[0038] It should be noted that "on", "formed on" and "disposed on" in the present disclosure can mean that one layer is directly formed or disposed on another layer, or that one layer is indirectly formed or disposed on another layer, that is, there are other layers between the two layers.

[0039] In the present disclosure, "a plurality of or several" means two or more. The term "and / or" describes the association relationship between the associated objects, which means that there can be three relationships, for example, A and / or B can mean that A exists alone, A and B exist together, and B exists alone. The character " / " generally represents that the associated objects before and after are in an "or" relationship.

[0040] It can be understood that in the embodiments of the present disclosure, "disposed in the same layer" means that two or more functional layers (or structural layers) are formed in the same layer and with the same material in the layer structure of the display substrate, that is, in the preparation process, the two or more functional layers (or structural layers) can be formed by the same material layer, and the required patterns and structures can be formed by the same patterning process.

[0041] It should be noted that the transistors used in the embodiments of the present disclosure can be thin film transistors or field effect transistors or other devices with the same characteristics. In the embodiments, the coupling mode of the drain and the source of each transistor can be interchanged, and therefore, the drain and the source of each transistor in the embodiments of the present disclosure are actually indistinguishable. Here, only to distinguish the two poles of the transistor other than the control pole (i.e., the gate), one pole is referred to as the drain and the other pole is referred to as the source. The thin film transistors used in the shift register in the embodiments of the present disclosure can be P-type transistors or N-type transistors. The control pole can be the gate, the first pole can be the source, and the second pole can be the drain. For the P-type transistor, when a low-level signal is input to the gate, the source and the drain are turned on, and when a high-level signal is input to the gate, the source and the drain are turned off. For the N-type transistor, the working principle is opposite, and the working principle will not be described in detail. The light emitting device can be an OLED device or the like, in which the first electrode can be an anode, the second electrode can be a cathode, and the light emitting layer can emit light under the driving of the electric field of the anode and the cathode.

[0042] FIG. 1 is a structural schematic diagram of an exemplary display substrate. As shown in FIG. 1, the display substrate includes a substrate 101, a pixel definition layer 102 on the substrate 101. The pixel definition layer 102 includes a plurality of pixel barriers 1021 and a receiving portion 1022 between adjacent pixel barriers 1021.

[0043] The display substrate further includes a driving circuit layer 103, a plurality of light emitting devices 104, a planarization layer 105, and an encapsulation layer 106. The driving circuit layer 103 is located between the substrate 101 and the pixel definition layer 102. The light emitting device 104 includes oppositely arranged first and second electrodes 1041 and 1042 and a light emitting layer 1043 between the first and second electrodes 1041 and 1042. The first and second electrodes 1041 and 1042 can be an anode and a cathode, respectively, and the light emitting layer 1043 can emit light under the driving of the voltage between the anode and the cathode.

[0044] It can be understood that, in addition to the light-emitting layer 1043 described above, the light-emitting device can further include other various functional layers between the first electrode 1041 and the second electrode 1042, for example, at least one of a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL) (not shown in the figure), for the purpose of facilitating the transmission of electrons and holes to the light-emitting layer 1043. The first electrode 1041 is located between the driving circuit layer 103 and the pixel definition layer 102, and can be exposed by the accommodation portion 1022. The light-emitting layer 1043 is located within the accommodation portion 1022. The second electrode 1042 covers the light-emitting layer 1042 and the pixel barrier 1021 of the pixel definition layer 102. Generally, the second electrode 1042 of each light-emitting device 104 is an integral planar electrode.

[0045] The planarization layer 105 can perform planarization processing on the circuit layer 103 to provide a relatively flat surface for other film layers (such as the first electrode 1041) thereon. The encapsulation layer 106 can cover the second electrode 1042 and encapsulate the entire light-emitting device 104 to prevent water and oxygen and other gases from entering the light-emitting layer 1043 of the light-emitting device 104 and affecting the display effect.

[0046] In the field of display technology, a solution process method is usually used to prepare the organic thin film layer such as the light-emitting layer 1043. The solution process includes but is not limited to inkjet printing, spin coating, screen printing, and transfer printing, etc. In the solution process, the ink in the accommodation portion 1022 of the pixel definition layer 102 is prone to "climbing effect".

[0047] "Climbing effect" refers to the phenomenon that, at the position where the solution contacts the solid, due to the influence of the characteristics of the solution itself and surface tension and other factors, the liquid level of the solution near the solid-liquid contact position is higher than that far from the solid-liquid contact position. The "climbing effect" causes the thickness of the organic thin film layer near the pixel barrier 1021 to be larger, and the uneven thickness of the organic thin film layer in the accommodation portion 1022 further causes the uneven brightness of the pixels, which seriously affects the display effect of the display substrate.

[0048] With the continuous development of display technology, higher requirements are put forward for the performance of the display substrate. In order to ensure the display effect of the display substrate and avoid light leakage of the pixel definition layer 102, a pixel definition material containing black dye is needed to form the pixel definition layer 102. However, the current black pixel definition material is a liquid-repellent material, which further aggravates the "climbing effect" of the ink in the accommodation portion 1022, affecting the display effect of the display panel.

[0049] To at least solve one of the above technical problems, the display substrate, the manufacturing method thereof and the display device are provided.

[0050] In a first aspect, the display substrate is provided, and a structure diagram of the display substrate is shown in FIG. 2, and a diagram of a partial structure of the display substrate shown in FIG. 2 is shown in FIG. 3. As shown in FIGS. 2 and 3, the display substrate includes a substrate 101, and a pixel definition layer 102 on the substrate 101. The pixel definition layer 102 includes a plurality of pixel barriers 1021. The pixel barrier 1021 includes a blocking layer 1021a and a plurality of nano microstructures 1021b arranged in sequence in a direction away from the substrate 101. An air film is formed around the nano microstructure 1021b.

[0051] The substrate 101 can be made of a rigid material such as glass, which can improve the bearing capacity of the substrate 101 to other film layers thereon. Of course, the substrate 101 can also be made of a flexible material such as polyimide (PI), which can improve the anti-bending and anti-stretching performance of the display substrate as a whole, so as to avoid the stress generated in the process of bending, stretching and twisting from causing the substrate 101 to break and cause open circuit defects. In actual application, the material of the substrate 101 can be reasonably selected according to actual needs to ensure that the display substrate has good performance.

[0052] It can be understood that a buffer layer and other structural film layers can also be arranged on the substrate 101. The buffer layer can be made of at least one of silicon nitride (SiN) and silicon oxide (SiO2), which can form a single-layer structure made of a single material, or a multi-layer structure made of multiple different materials. The film layer in contact with the active layer of the transistor is a silicon oxide (SiO2) layer, so as to avoid water and oxygen and other gases from the side of the substrate 101 to invade into other film layers thereon to cause damage to the display substrate. For example, the buffer layer can be a silicon nitride (SiN) and silicon oxide (SiO2) laminated structure, in which the thickness of the silicon nitride (SiN) is to The thickness of the silicon oxide (SiO2) is to

[0053] The pixel defining layer 102 is composed of a plurality of pixel barriers 1021 arranged at intervals, which can be made of light-absorbing materials such as organic materials such as acrylic, resin, polyimide, or benzocyclobutene, etc., with carbon black additives added to make it black, so as to avoid light leakage caused by partial exposure of the pixel defining layer 102, affecting the display effect of the display substrate. However, the embodiments of the present disclosure are not limited thereto, and the pixel defining layer 102 can also be made of opaque metal materials such as alloys of molybdenum and titanium (MoTi), chromium (Cr), molybdenum (Mo), tungsten (W), vanadium (V), niobium (Nb), tantalum (Ta), manganese (Mn), cobalt (Co), nickel (Ni), or any combination thereof with high light absorption. The pixel defining layer 102 actually serves to define a plurality of pixel regions arranged in an array on the substrate 101 (not shown in the figure).

[0054] The pixel barrier 1021 includes a barrier layer 1021a and a plurality of nano microstructures 1021b. The barrier layer 1021a mainly functions to define the pixel region and also supports the plurality of nano microstructures 1021b thereon. The plurality of nano microstructures 1021b have certain gaps therebetween, and an air film can be formed on the surface of the nano microstructure 1021b and around it, similar to the surface of a cicada wing, which can have good liquid-repellent effect and avoid ink climbing on the edge of the pixel region.

[0055] In the display substrate provided by the embodiments of the present disclosure, the pixel barrier 1021 can adopt a double-layer structure of the barrier layer 1021a and the plurality of nano microstructures 1021b, the plurality of nano microstructures 1021b have certain gaps therebetween, and an air film can be formed on the surface of the nano microstructure 1021b and around it, similar to the surface of a cicada wing, which can have good liquid-repellent effect and avoid ink climbing on the edge of the pixel region, thus preventing the inhomogeneous thickness of the organic thin film layer formed by the ink from causing inhomogeneous brightness of the pixel, thereby improving the display effect of the display substrate.

[0056] In some embodiments, the ratio of the height of the barrier layer 1021a to the height of the pixel barrier 1021 is 0 to 0.5, and the ratio of the height of the nano microstructure 1021b to the height of the pixel barrier 1021 is 0.5 to 1.0.

[0057] In actual applications, most of the structures in the pixel barrier 102 (e.g., more than half of the overall height of the pixel barrier 102) can be set as the nano microstructure 1021b, so as to ensure that most of the structures in the pixel barrier 1021 have good liquid-repellent performance and avoid ink climbing on the edge of the pixel region.

[0058] Of course, a small part of the pixel barrier, such as half of the overall height of the pixel barrier 102, can be set as the nano microstructure 1021b, so as to ensure that the upper half of the pixel barrier 102 has the liquid-repellent property, avoid the ink climbing at the edge of the pixel area, and reduce the process steps, reduce the process difficulty, and save the preparation cost in the process of preparing the display substrate.

[0059] In actual application, the height of the pixel barrier 1021 is 1-2 microns, the height of the barrier layer 1021a is 0-1 micron, and the height of the nano microstructure 1021b is 0.5-2 microns. For example, the height of the pixel barrier 1021 is 2 microns, the height of the barrier layer 1021a is 1 micron, and the height of the nano microstructure 1021b is 1 micron. The height of the barrier layer 1021a and the height of the nano microstructure 1021b each account for half of the overall height of the pixel barrier 1021. It can be understood that the specific height of the barrier layer 1021a and the nano microstructure 1021b in the pixel barrier 1021 can be set according to actual needs,

[0060] In some embodiments, the height of each barrier layer 1021a is equal, and / or the height of each nano microstructure 1021b is equal.

[0061] The equal height of each barrier layer 1021a and / or the equal height of each nano microstructure 1021b can ensure that the pixel barrier 1021 formed by the two has good ink blocking effect, avoid ink overflow during preparation, and at the same time can ensure the uniform thickness of the formed organic thin film layer, so as to ensure the uniform pixel brightness of the pixel area, thereby improving the display effect of the display substrate.

[0062] In some embodiments, the ratio of the gap width between adjacent nano microstructures 1021b to the width of the nano microstructure 1021b is 1.0-2.5.

[0063] In actual application, the plurality of nano microstructures 1021b can be arranged in an array, and the gap width between adjacent nano microstructures 1021b can be greater than the width of the nano microstructure 1021b, for example, the ratio of the gap width between adjacent nano microstructures 1021b to the width of the nano microstructure 1021b is 1.0-2.5, so as to ensure that the gap between adjacent nano microstructures 1021b is sufficient, so that an air film can be formed on the surface of the nano microstructure 1021b and around it, similar to the surface of a cicada wing, which can have good liquid-repellent effect and avoid ink climbing at the edge of the pixel area.

[0064] In some embodiments, the gap width between adjacent nanostructures 1021b can be 100-200 nm, and the width of the nanostructure 1021b itself can be 80-100 nm. For example, when the width of the nanostructure 1021b itself is 100 nm and the gap width between adjacent nanostructures 1021b is 100 nm, the size of the nanostructure 1021b itself can be small, and there is enough gap between adjacent nanostructures 1021b, so that an air film can be formed on the surface of the nanostructure 1021b and around it, ensuring that the nanostructure 1021b has good liquid repellency, avoiding ink climbing on the edge of the pixel area, and thus preventing the uneven thickness of the organic thin film layer formed by the ink from causing uneven brightness of the pixel, thereby improving the display effect of the display substrate.

[0065] The nanostructure 1021b can be a nanopillar, and the specific shape can be a cylinder, a cone, a circular truncated cone, a triangular pillar, a square pillar, or the like. Of course, the nanostructure 1021b can also have other shapes, as long as an air film can be formed on the surface of the nanostructure 1021b and around it, and thus is not listed one by one.

[0066] In some embodiments, the materials of the barrier layer 1021a and the nanostructure 1021b are light-absorbing materials.

[0067] The barrier layer 1021a and the nanostructure 1021b are made of light-absorbing materials, such as acrylic, resin, polyimide, or benzocyclobutene, and the like organic materials, which are added with carbon black additives to make them black, so as to avoid light leakage caused by the partial exposure of the pixel defining layer 102, and thus affecting the display effect of the display substrate. However, the embodiments of the present disclosure are not limited to this, and the barrier layer 1021a and the nanostructure 1021b can also be made of opaque metal materials, such as molybdenum and titanium alloy (MoTi), chromium (Cr), molybdenum (Mo), tungsten (W), vanadium (V), niobium (Nb), tantalum (Ta), manganese (Mn), cobalt (Co), nickel (Ni), or any combination thereof having high light absorption.

[0068] In some embodiments, the barrier layer 1021a and the nanostructure 1021b are integrally formed.

[0069] In practical applications, the barrier layer 1021a and the nano microstructure 1021b can be made of the same material and by the same process, and the two form an integral structure, which can reduce the process steps and save the preparation cost. At the same time, no gap is generated between the two, which is conducive to the firm combination between the two. It can be understood that the barrier layer 1021a and the nano microstructure 1021b can also be made of different materials and by different processes, which will not be described in detail here.

[0070] As shown in FIG. 2, the pixel definition layer 102 further includes: a receiving part 1022 between the adjacent pixel barriers 1021; the receiving part 1022 has an inverted trapezoidal cross-sectional shape in the direction perpendicular to the substrate 101.

[0071] The receiving part 1022 can be used to hold the ink for forming the organic thin film layer, and has an inverted trapezoidal cross-sectional shape in the direction perpendicular to the substrate 101, which can form an upper small funnel shape, which is conducive to increasing the volume of the receiving part 1022 and ensuring the thickness of the organic thin film layer formed therein. And it is conducive to the injection of ink to ensure that the ink is injected into the corresponding receiving part 1022 and avoid mutual crosstalk between different inks.

[0072] As shown in FIG. 2, the display substrate further includes: a driving circuit layer 103 and a plurality of light emitting devices 104; the light emitting device 104 includes: a first electrode 1041 and a second electrode 1042 oppositely arranged, and a light emitting layer 1043 between the first electrode 1041 and the second electrode 1042; the driving circuit layer 103 is between the substrate 101 and the pixel definition layer 102; the first electrode 1041 is connected with the driving circuit layer 103 and is exposed by the receiving part 1022; the light emitting layer 1043 is in the receiving part 1022; and the second electrode 1042 covers the light emitting layer 1043 and the nano microstructure 1021b.

[0073] The driving circuit layer 103 can include a plurality of pixel driving circuits, which can provide driving signals for the light emitting device 104 to make the light emitting device 104 emit light and realize the display function. FIG. 4 is a structural schematic diagram of an exemplary pixel driving circuit. As shown in FIG. 4, the pixel driving circuit includes: a first initialization transistor T1, a threshold compensation transistor T2, a driving transistor T3, a data writing transistor T4, a first light emitting control transistor T5, a second light emitting control transistor T6, a second initialization transistor T7, a third initialization transistor T8, a storage capacitor Cst and a light emitting device OLED.

[0074] The gate of the driving transistor T3 is connected with the first node N1, the source is connected with the second node N2, and the drain is connected with the third node N3. The gate of the data writing transistor T4 is connected with the first scan signal line Pgate, the source is connected with the data signal line Data, and the drain is connected with the second node N2. The gate of the threshold compensation transistor T2 is connected with the second scan signal line Ngate, the source is connected with the third node N3, and the drain is connected with the first node N1. One end of the storage capacitor Cst is connected with the first node N1, and the other end is connected with the first power signal line VDD. The gate of the first light emitting control transistor T5 is connected with the light emitting control signal line EM, the source is connected with the first power signal line VDD, and the drain is connected with the second node N2. The gate of the second light emitting control transistor T6 is connected with the light emitting control signal line EM, the source is connected with the third node N3, and the drain is connected with the fourth node N4. The gate of the first initialization transistor T1 is connected with the first reset signal line Preset1, the source is connected with the first initialization signal line Vinit1, and the drain is connected with the third node N3. The gate of the second initialization transistor T7 is connected with the second reset signal line Preset2, the source is connected with the second initialization signal line Vinit2, and the drain is connected with the fourth node N4. The gate of the third initialization transistor T8 is connected with the second reset signal line Preset2, the source is connected with the third initialization signal line Vref, and the drain is connected with the second node N2. The anode of the light emitting device OLED is connected with the fourth node N4, and the cathode is connected with the second power signal line VSS.

[0075] In the embodiment, the threshold compensation transistor T2 is an N-type transistor, for example, the threshold compensation transistor T2 can be an N-type metal oxide thin film transistor. The metal oxide thin film transistor has a small leakage current, so that the leakage of the first node N1 through the threshold compensation transistor T2 in the light emitting stage can be avoided. Meanwhile, the first initialization transistor T1, the driving transistor T3, the data writing transistor T4, the first light emitting control transistor T5, the second light emitting control transistor T6, the second initialization transistor T7, and the third initialization transistor T8 are P-type transistors, for example, the first initialization transistor T1, the driving transistor T3, the data writing transistor T4, the first light emitting control transistor T5, the second light emitting control transistor T6, the second initialization transistor T7, and the third initialization transistor T8 are P-type low temperature poly-silicon thin film transistors. The low temperature poly-silicon thin film transistor has a high carrier mobility, so that the display panel with high resolution, high response speed, high pixel density, and high aperture ratio can be realized. The first initialization signal line Vinit1, the second initialization signal line Vinit2, and the third initialization signal line Vref can output the same or different voltage signals according to actual conditions.

[0076] The first electrode 1041 and the second electrode 1042 are opposite in polarity, where the first electrode 1041 can be specifically an anode of the light-emitting device, which can be made of at least one of silver (Ag), aluminum (Al), titanium (Ti), and the like. The second electrode 1042 can be specifically a cathode of the light-emitting device, which can be made of indium tin oxide (ITO), indium zinc oxide (IZO), and the like, to improve the transparency of the display substrate as a whole. The cathodes of the light-emitting devices 104 can be connected as a whole to form a planar electrode, which covers the light-emitting layer 1043 and the nano microstructure 1021b. Both the anode and the cathode can be a single-layer structure made of a single material as described above, or a multi-layer structure made of multiple materials as described above, which can be selected as needed. The first electrode 1041 can be connected to the drain 1031f of the thin film transistor TFT in the driving circuit layer 103, to provide a driving voltage for the light-emitting device 104 through the driving circuit layer 103, so that the light-emitting layer 1043 of the light-emitting device 104 can emit light under the electric field driving of the first electrode 1041 and the second electrode 1042, to realize multi-color display. It can be understood that the light-emitting device can further include other functional layers, such as at least one of a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL), which can be set according to the film layer structure in the related art, and will not be described in detail herein.

[0077] As shown in FIG. 2, the driving circuit layer 103 includes a plurality of thin film transistors 1031 (i.e., each transistor in the pixel driving circuit described above), which includes, in sequence from the direction away from the substrate 101, an active layer 1031a, a gate insulating layer 1031b, a gate 1031c, an interlayer insulating layer 1031d, a source 1031e, and a drain 1031f. The source 1031e and the drain 1031f are respectively connected to both ends of the active layer 1031a through a via hole penetrating through the interlayer insulating layer 1031d and the gate insulating layer 1031b.

[0078] As shown in FIG. 2, the driving circuit layer 103 further includes at least one planarization layer 105, and the first electrode 1041 of the light-emitting device 104 is connected to the drain 1031f of the thin film transistor 1031 in the driving circuit layer 103 through a via hole penetrating through the planarization layer 105. At this time, the planarization layer 105 can be one layer. For example, the display substrate further includes a connection electrode, the first electrode 1041 of the light-emitting device 104 is connected to the drain 1031f of the thin film transistor 1031 in the driving circuit layer 103 through the connection electrode, and two or three planarization layers 105 are needed to planarize the film layers, at this time, the planarization layer 105 can be multiple layers.

[0079] The planarization layer 105 can be made of organic materials such as acrylic, resin, polyimide, benzocyclobutene, etc. and can be selected according to actual needs. The planarization layer 105 can perform planarization processing on structures such as the source electrode 1031e and the drain electrode 1031f to form a relatively flat surface, facilitating the lamination of other film layers thereon.

[0080] As shown in FIG. 2, the display substrate includes an encapsulation layer 106 located away from the base 101 in the direction of the second electrode 11042; the encapsulation layer 106 includes a first inorganic encapsulation layer 1061, an organic encapsulation layer 1063, and a second inorganic encapsulation layer 1062 arranged in sequence in the direction away from the base 101.

[0081] The first inorganic encapsulation layer 1061 and the second inorganic encapsulation layer 1062 can be formed of inorganic materials such as silicon nitride, silicon oxide, silicon oxynitride, etc., and the organic encapsulation layer 1063 can be formed of organic materials such as polyimide (PI) and epoxy resin. The encapsulation layer 106 formed of the composite film layer can form multiple protections for the light-emitting device 104 in the display substrate, has better encapsulation effect, and avoids damage to the light-emitting device 104 caused by the invasion of water and oxygen and other gases.

[0082] In a second aspect, the embodiments of the present disclosure provide a display device, which includes the display substrate provided in any of the above embodiments. The display device can be any product or component with display function such as a television, a mobile phone, a display, a notebook computer, a digital photo frame, a navigator, etc. The implementation principle of the display device is similar to that of the display substrate, which will not be described herein.

[0083] In a third aspect, the embodiments of the present disclosure provide a preparation method of a display substrate. FIG. 5 is a flowchart of a preparation method of a display panel according to an embodiment of the present disclosure. As shown in FIG. 5, the preparation method of the display panel includes the following steps S501 to S503.

[0084] S501, forming a pixel definition material layer on a base.

[0085] In step S501, a pixel defining material layer can be formed on the substrate 101 by coating, deposition or other methods. The pixel defining material layer can be made of a light-absorbing material, such as an organic material, e.g., acrylic, resin, polyimide or benzocyclobutene, to which carbon black additives are added to make it black so as to avoid light leakage caused by partial exposure of the pixel defining layer 102 and affect the display effect of the display substrate. However, the embodiments of the present disclosure are not limited thereto, and the pixel defining layer 102 can also be made of an opaque metal material, such as an alloy of molybdenum and titanium (MoTi), chromium (Cr), molybdenum (Mo), tungsten (W), vanadium (V), niobium (Nb), tantalum (Ta), manganese (Mn), cobalt (Co), nickel (Ni) or any combination thereof having a high light absorption rate.

[0086] In step S502, the pixel defining material layer is etched to form a plurality of pixel barriers.

[0087] In step S502, the pixel material layer can be etched to remove the pixel material at the pixel area where ink is to be printed, thereby forming a plurality of pixel barriers 1021 and a plurality of accommodating portions 1022.

[0088] In step S503, the pixel barriers are etched to form a barrier layer and a plurality of nano microstructures on the barrier layer, so that an air film is formed around the nano microstructures.

[0089] In step S503, the pixel barriers 1021 can be further etched. The etching precision in this step is much higher than that in step S502. A mask plate can be used to shield to improve the etching precision, thereby forming a barrier layer 1021a and a plurality of nano microstructures 1021b. The plurality of nano microstructures 1021b have certain gaps therebetween, and an air film can be formed on the surface of the nano microstructures 1021b and around the nano microstructures 1021b, similar to the surface of a cicada wing, which can have a good liquid-repellent effect and avoid ink climbing on the edge of the pixel area. Therefore, the thickness of the organic thin film layer formed by the ink can be uniform, and the brightness of the pixel can also be uniform, thereby improving the display effect of the display substrate.

[0090] It can be understood that other structures in the display substrate, such as the driving circuit layer 103, the light-emitting device 104, the planarization layer 105, the encapsulation layer 106 and the like, can be prepared according to the preparation process in the related art, and will not be described in detail herein.

[0091] It can be understood that the above embodiments are only exemplary embodiments adopted to illustrate the principles of the present disclosure, and the present disclosure is not limited thereto. Various modifications and improvements can be made by those of ordinary skill in the art without departing from the spirit and essence of the present disclosure, and these modifications and improvements are also considered to be within the protection scope of the present disclosure.

Claims

1. A display substrate, wherein: The display substrate comprises: a base, a pixel defining layer located on the base; the pixel defining layer comprises: a plurality of pixel blocking walls; The pixel retaining wall comprises: a barrier layer and a plurality of nano-micro structures arranged in sequence along a direction away from the substrate; an air film is formed around the nano-micro structure.

2. The display substrate according to claim 1, wherein The ratio of the height of the blocking layer to the height of the pixel blocking wall is 0 to 0.

5.

3. The display substrate according to claim 1, wherein The ratio of the height of the nanostructure to the height of the pixel retaining wall is 0.5 to 1.

0.

4. The display substrate according to claim 1, wherein The height of the pixel blocking wall is 1 micron to 2 microns; the height of the blocking layer is 0 micron to 1 micron; and the height of the nanostructure is 0.5 micron to 2 microns.

5. The display substrate according to claim 1, wherein The heights of the barrier layers are equal, and / or the heights of the nanostructures are equal. The display substrate according to claim 1 , wherein: The ratio of the gap width between adjacent nano-microstructures to the width of the nano-microstructure is 1.0 to 2.

5.

7. The display substrate according to claim 6, wherein: The width of the gap between adjacent nano-microstructures is 100 nanometers to 200 nanometers, and the width of the nano-microstructure is 80 nanometers to 100 nanometers.

8. The display substrate according to claim 1, wherein The nanostructure is a nanocolumn.

9. The display substrate according to claim 1, wherein: The materials of the barrier layer and the nanostructure are both light-absorbing materials.

10. The display substrate according to claim 1, wherein The barrier layer and the nanostructure are an integrally formed structure.

11. The display substrate according to claim 1, wherein: The pixel defining layer further includes: a receiving portion located between adjacent pixel blocking walls; The cross-section of the accommodation portion along a direction perpendicular to the base is in an inverted trapezoidal shape.

12. The display substrate according to claim 11, wherein: The display substrate further comprises: a driving circuit layer and a plurality of light emitting devices; the light emitting devices comprise: a first electrode and a second electrode arranged opposite to each other, and a light emitting layer located between the first electrode and the second electrode; The driving circuit layer is located between the substrate and the pixel defining layer; The first electrode is connected to the driving circuit layer and exposed from the accommodation portion; The light-emitting layer is located in the accommodation portion; The second electrode covers the light-emitting layer and the nanostructure.

13. The display substrate according to claim 12, wherein: The driving circuit layer includes: a plurality of thin film transistors; the thin film transistors include: an active layer, a gate insulating layer, a gate, an interlayer insulating layer, a source electrode and a drain electrode arranged in sequence along a direction away from the substrate; the display substrate also includes: a planarization layer; The source electrode and the drain electrode are respectively connected to two ends of the active layer through via holes penetrating the interlayer insulating layer and the gate insulating layer; The planarization layer covers the source electrode and the drain electrode; The first electrode is connected to the drain electrode through a via hole penetrating the planarization layer.

14. A display device, wherein: The display device comprises the display substrate according to any one of claims 1 to 13.

15. A method for preparing a display substrate, wherein: The method for preparing the display substrate includes: forming a pixel-defining material layer on a substrate; Etching the pixel defining material layer to form a plurality of pixel retaining walls; The pixel barrier walls are etched to form a barrier layer and a plurality of nano-microstructures on the barrier layer, so that an air film is formed around the nano-microstructures.

Images