Computing device and control method

Abstract

Provided in the embodiments of the present application are a computing device and a method. The computing device comprises: a first card slot, a first circuit board and a mainboard, wherein the first card slot is used for the insertion of the first circuit board; the first circuit board comprises an M.2 connector, which is configured to connect to a solid state drive (SSD); the mainboard comprises a baseboard management controller (BMC); presence pins of the first circuit board are connected to the BMC; a presence pin and SSD-type pin of the M.2 connector are connected to a serial bus interface of the BMC; and the BMC is used for detecting the states of the presence pins of the first circuit board, so as to determine whether the first circuit board is present, when the first circuit board is present, on the basis of the level of the presence pin of the M.2 connector, determining whether the SSD is present, and when the SSD is present, determining the type of the SSD by means of the level of the SSD-type pin. The computing device can save the internal space of a chassis, is convenient to maintain, and can be compatible with a SATA M.2 interface and an NVMe M.2 interface.

Description

Computing device and control method

[0001] This application claims priority to the Chinese Patent Application No. 202410437270.2, filed on April 11, 2024, entitled “A computing device and control method”, the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] Embodiments of the present application relate to the technical field of servers, and in particular to a computing device and control method. BACKGROUND

[0003] At present, a solid state drive (SSD) is needed in a server to store files such as documents or videos. The SSD is connected to a mainboard of the server through an M.2 interface (Next Generation Form Factor, NGFF), and the mainboard reads and writes data in the SSD. The M.2 interface is a new interface specification that replaces the mini-Serial Advanced Technology Attachment (mSATA) interface, and can be compatible with SATA and peripheral component interconnect express (PCIE) standards.

[0004] The M.2 interface is mainly adapted to Socket 2 and Socket 3. Socket 2 can support M.2 SSDs compatible with SATA and PCIe x2 channel interfaces, and the corresponding key position is B Key. Socket 3 supports M.2 SSDs compatible with PCIe x4 channel interfaces, and the corresponding key position is M Key. At present, the interfaces of the SSDs include SATA M.2 interfaces and Non-Volatile Memory express (NVMe) M.2 interfaces. The SATA M.2 interface can be inserted into two types of SSDs, M Key and B Key, but the NVMe M.2 interface can only be inserted into M Key type SSD.

[0005] In the prior art, the M.2 interface and the SSD are both arranged on a carrier board, and the carrier board is arranged inside a case of the server, thereby occupying the space inside the case. Moreover, when the SSD has a problem, the case must be disassembled for maintenance, which is difficult. In addition, the current M.2 interface cannot be compatible with the SATA M.2 interface and the NVMe M.2 interface. SUMMARY

[0006] The embodiment of the present application provides a computing device and a control method, which can save the internal space of a case, is convenient to maintain, and can be compatible with a SATA M.2 interface and an NVMe M.2 interface.

[0007] The embodiment of the present application provides a computing device, which comprises a first card slot, a first circuit board and a mainboard; the first card slot is used for inserting the first circuit board; the first circuit board comprises an M.2 connector; the M.2 connector is used for connecting a solid state disk (SSD); the mainboard comprises a baseboard management controller (BMC); in-position pins of the first circuit board are connected to the BMC; in-position pins and SSD type pins of the M.2 connector are connected to a serial bus interface of the BMC; the BMC is used for detecting the state of the in-position pins of the first circuit board to determine whether the first circuit board is in position; in the case that the first circuit board is in position, whether the SSD is in position is determined according to the level of the in-position pins of the M.2 connector; in the case that the SSD is in position, the type of the SSD is determined through the level of the SSD type pins.

[0008] The embodiment of the present application is used for saving the internal space of a case, facilitating maintenance of an SSD and an M.2 connector, and making the M.2 connector compatible with two types of interfaces, namely, a SATA interface and an NVMe interface; a first circuit board of a new design is inserted into a first card slot; an M.2 connector and a serial bus expansion device are designed on the first circuit board; in-position pins of the first circuit board are connected to a BMC on a server mainboard; the in-position pins and SSD type pins of the M.2 connector are connected to a serial bus interface of the BMC through the serial bus expansion device; the BMC determines whether an SSD on the first circuit board is in position by detecting the state of the in-position pins; when the SSD is in position, the type of the SSD is determined to be a SATA type or an NVMe type; the two types of SSDs can be compatible with each other, the application scenarios are expanded, and the use is more flexible.

[0009] In a possible implementation manner, the mainboard further comprises a central processing unit; the M.2 connector is connected to the central processing unit; the BMC is further used for informing the central processing unit of the type of the SSD; and the central processing unit is used for determining a protocol matched with the type of the SSD according to the type of the SSD, wherein the protocol comprises a serial advanced technology attachment (SATA) protocol and a non-volatile memory host controller (NVMe) protocol.

[0010] Since the first circuit board can be replaced without opening the box in structure, if the M.2 SSD fails, the first circuit board can be removed to replace the M.2 SSD without opening the machine case under the condition that the whole machine is disconnected from the power supply, thereby avoiding plugging and unplugging cables and moving the whole computing device out of the cabinet and disassembling the machine, especially in the case that the whole computing device is heavy, the plug-pull maintenance mode of the present application brings great convenience to operation and maintenance. The M.2 SSD carrier plate in the form of the OCP card provided in the embodiment of the present application only occupies the space of one OCP card in size, and does not need to reserve a special space for the M.2 SSD carrier plate in advance in the machine case of the computing device, and at the same time, the M.2 SSD carrier plate can be conveniently removed without opening the machine case of the computing device, thereby realizing maintenance of the M.2 SSD without opening the box.

[0011] In a possible implementation, the M.2 connector includes a first M.2 connector and a second M.2 connector, the first circuit board further includes a serial bus expander; the first M.2 connector is used to connect a first SSD, and the second M.2 connector is used to connect a second SSD; the first SSD and the second SSD are backups of each other; the present pin and the SSD type pin of the first M.2 connector are connected to the serial bus interface of the BMC through the serial bus expander; the present pin and the SSD type pin of the second M.2 connector are connected to the serial bus interface of the BMC through the serial bus expander; the first M.2 connector includes PCIE X4 pins, the PCIE X3 pin of the first M.2 connector is connected to the central processor, and the remaining PCIE X1 pin of the first M.2 connector is connected to the central processor as a SATA pin; the second M.2 connector includes PCIE X4 pins, the PCIE X3 pin of the second M.2 connector is connected to the central processor, and the remaining PCIE X1 pin of the second M.2 connector is connected to the central processor as a SATA pin.

[0012] Generally, in order to realize data backup, two M.2 connectors are arranged on the OCP card to connect two SSDs. The following describes an implementation that the OCP card can connect two SSDs. The M.2 connector provided in the embodiment of the present application can be compatible with the SATA type SSD and the NVMe type SSD, thereby expanding the application scenarios and bringing great convenience to actual use.

[0013] In a possible implementation, the first and second in-position pins of the first circuit board are connected to two IO pins of the BMC respectively, and the first and second in-position pins are both grounded on the first circuit board; the third and fourth in-position pins of the first circuit board are connected to another two IO pins of the BMC respectively; the third and fourth in-position pins of the first circuit board are both left floating on the first circuit board; and the BMC is configured to determine that the first circuit board is in position when it is detected that the levels of the two IO pins connected to the first and second in-position pins are low.

[0014] The high and low level states of the in-position pins are not specifically limited in the embodiments of the present application. For example, in a possible implementation, when the level of an in-position pin is high, it is determined that the SSD is in position; and conversely, when the level of an in-position pin is low, it is determined that the SSD is not in position. Similarly, the high and low level states of the SSD type pin are not specifically limited in the embodiments of the present application. For example, in a possible implementation, when the level of an SSD type pin is low, it is determined that the SSD type is SATA type; and conversely, when the level of an SSD type pin is high, it is determined that the SSD type is NVMe type.

[0015] In a possible implementation, the first circuit board further stores a board ID; and the BMC is further configured to read the board ID, determine whether the first circuit board is an M.2 carrier board through the board ID, and if the first circuit board is not an M.2 carrier board, configure the central processor to the first circuit board according to the bandwidth requirement of a standard OCP card.

[0016] The BMC can determine the function of the inserted OCP card by reading the Board ID information. Specifically, the BMC determines whether the first circuit board 100 is an M.2 carrier board through the Board ID, and if the first circuit board 100 is not an M.2 carrier board, configures the first circuit board 100 according to a standard OCP card.

[0017] In a possible implementation, the BMC is specifically configured to determine that the SSD type is NVMe when it is detected that the level of the SSD type pin is high, and determine that the SSD type is SATA when it is detected that the level of the SSD type pin is low.

[0018] The high and low levels of the SSD type pin are not specifically limited in the embodiments of the present application, and can be set according to actual needs.

[0019] Based on the computing device provided in the above embodiments, the embodiments of the present application further provide a control method of a computing device, the computing device comprising: a first card slot, a first circuit board and a mainboard; the first card slot is used for inserting the first circuit board; the first circuit board comprises: an M.2 connector; the M.2 connector is used for connecting a solid state disk (SSD); the mainboard comprises a baseboard management controller (BMC); an in-place pin of the first circuit board is connected to the BMC; an in-place pin of the M.2 connector and an SSD type pin of the M.2 connector are both connected to a serial bus interface of the BMC; the method comprises: judging whether the first circuit board is in place according to a level of the in-place pin of the first circuit board; in the case that the first circuit board is in place, judging whether the SSD is in place according to a level of the in-place pin of the M.2 connector; in the case that the SSD is in place, determining a type of the SSD through a level of the SSD type pin.

[0020] In a possible implementation, the method provided by the embodiments of the present application further comprises: determining a protocol matched with the type of the SSD according to the type of the SSD; the protocol comprises a serial advanced technology attachment (SATA) protocol and a non-volatile memory host controller interface (NVMe) protocol.

[0021] In a possible implementation, the method provided by the embodiments of the present application further comprises: reading a board ID stored on the first circuit board, judging whether the first circuit board is an M.2 carrier board through the board ID, and if the first circuit board is not the M.2 carrier board, configuring the first circuit board by the central processing unit according to a bandwidth requirement of a standard OCP card.

[0022] In a possible implementation, the method provided by the embodiments of the present application further comprises: determining the type of the SSD through a level of the SSD type pin, specifically comprising: determining that the type of the SSD is NVMe when detecting that the level of the SSD type pin is high; and determining that the type of the SSD is SATA when detecting that the level of the SSD type pin is low. BRIEF DESCRIPTION OF DRAWINGS

[0023] FIG. 1A is a schematic diagram of a computing device provided by the embodiments of the present application;

[0024] FIG. 1B is a schematic diagram of another computing device provided by the embodiments of the present application;

[0025] FIG. 1C is a schematic diagram of still another computing device provided by the embodiments of the present application;

[0026] FIG. 2 is a schematic diagram of a SATA M.2 provided by the embodiments of the present application;

[0027] FIG. 3 is a schematic diagram of an NVMe M.2 according to an embodiment of the present application;

[0028] FIG. 4 is a schematic diagram of another computing device according to an embodiment of the present application;

[0029] FIG. 5 is a flowchart of a control method of a computing device according to an embodiment of the present application;

[0030] FIG. 6 is a flowchart of another control method of a computing device according to an embodiment of the present application. DETAILED DESCRIPTION

[0031] The computing device provided by the embodiments of the present application is not limited to a specific application scenario. For example, the computing device is introduced by taking a server as an example, and the type of the server is not limited, for example, the computing device can be a server. The server can be located in a data center or other areas, and the embodiments of the present application are not limited.

[0032] The server is a kind of computing device, and the server runs faster and has higher load than the ordinary computer. The server provides computing or application services for other clients (such as PC, smart phone and other devices) in the network. The server has high-speed CPU operation ability, long-time reliable operation, powerful external data throughput capacity and better scalability. The server is divided into rack type, blade type, tower type and cabinet type according to the appearance; the server can also include AI server according to the function, such as GPU server and the like.

[0033] The single board is a commonly used component in the server, and the single board can be understood as a general term for a circuit board, which can be a mainboard, a power management board, a network data exchange board and the like. Other components can be arranged on the single board, such as a controller, a processor or other chips, to realize the operation function of the server. The single board can also be provided with an electrical connector, and the single board can be connected to other electrical components through the electrical connector, or connected to another single board through the electrical connector.

[0034] The server can include a single board and a power supply, and the power supply is used to supply power to each load on the single board; the load can be a central processing unit, a memory, a baseboard management controller and the like arranged on the single board.

[0035] The embodiments of the present application do not specifically limit the type of single board, and the single board can be a mainboard or other single board.

[0036] The mainboard is a kind of circuit board in a server, and the mainboard can be provided with a controller, a memory bank, an electrical connector and the like. The controller can include a central processing unit (CPU), a south bridge chip PCH, a micro controller unit (MCU), a complex programming logic device (CPLD), a field programmable gate array (FPGA) and the like. Among them, the CPU can be electrically connected with peripheral devices through internal wires on the mainboard and the electrical connector, for example, the CPU is electrically connected with a network card, a display card and the like through the electrical connector. The mainboard of a general server can be provided with a CPU, a PCH and a CPLD, wherein the CPU can be one or more.

[0037] The embodiments of the present application do not specifically limit the specific type of the memory bank, for example, the memory bank includes but is not limited to the following types: dual-inline-memory-modules (DIMM), single inline memory module (SIMM). The memory chip on the DIMM can be Synchronous Dynamic Random Access Memory (SDRAM), Double Data Rate Synchronous Dynamic Random Access Memory 4 (DDR4), Double Data Rate Synchronous Dynamic Random Access Memory 5 (DDR5).

[0038] A baseboard management controller (BMC) can be arranged on the mainboard.

[0039] The BMC is an essential component of the server, which is used to monitor the operation status of the server, such as temperature, fan speed, power supply status, operating system status and the like. The BMC is independent of the server operation and is not affected by the server, and can perform some operations such as firmware upgrade, machine equipment viewing, remote control machine startup and the like in the standby state of the server without starting up, and can record key logs when the server is down.

[0040] SSD, solid state drive, is a hard disk made of solid state electronic storage chip array.

[0041] Open Compute Project (OCP) card, a hardware design specification customized for data center, including customized design specification of computer room, cabinet, server, storage, network equipment, and management specification of cloud hardware. The OCP card is an open computing project network interface card. The side of the server case generally includes a plurality of first card slots, but generally some of the first card slots are vacant and no OCP card is inserted.

[0042] Embodiments of the present application are to save the internal space of the case, facilitate the maintenance of the SSD and the M.2 connector, and the M.2 connector can be compatible with both SATA and NVMe interfaces. A first circuit board is inserted into the first card slot. The first circuit board has the same size and interface shape as the existing OCP card, and can also be an M.2 carrier board. An M.2 connector and a serial bus expander are designed on the first circuit board. The in-place pins of the first circuit board are connected to the BMC on the server motherboard. The in-place pins and the SSD type pins of the M.2 connector are connected to the serial bus interface of the BMC through the serial bus expander. The BMC determines whether the SSD on the first circuit board is in place by detecting the state of the in-place pin. When the SSD is in place, it continues to determine whether the type of the SSD is SATA or NVMe.

[0043] In order for those skilled in the art to better understand the technical solutions provided by the embodiments of the present application, the following will be described in detail in conjunction with the drawings.

[0044] Referring to FIG. 1A, it is a schematic diagram of a computing device provided by an embodiment of the present application.

[0045] The side of the server 1000 case generally includes a plurality of first card slots, for example, the first card slot can be used to insert the OCP card, but generally the first card slot of the server 1000 is vacant and no OCP card is inserted. The vacant first card slot can be used to insert the first circuit board 100 provided by the embodiments of the present application. The first circuit board 100 has the same size and interface shape as the existing OCP card, and can also be an M.2 carrier board.

[0046] Referring to FIG. 1B, it is a schematic diagram of another computing device provided by an embodiment of the present application.

[0047] The computing device provided by the embodiment of the present application comprises a first circuit board 100 and a mainboard 200, and the mainboard 200 is provided with a first card slot 300, for example, the first card slot can be an OCP slot, and an OCP card or the first circuit board 100 in the embodiment of the present application can be inserted. The first circuit board 100 provided by the embodiment of the present application can be used as an M.2 carrier board, and the number of M.2 connectors provided by the embodiment of the present application is not limited, that is, one M.2 connector or multiple M.2 connectors can be provided. The M.2 connector can be inserted into SATA or NVMe. Referring to FIG. 1C, which is a schematic diagram of another computing device provided by the embodiment of the present application.

[0048] The computing device provided by the embodiment of the present application comprises a first card slot (not shown), a first circuit board 100 and a mainboard (MB) 200. The following will take a server as an example for introduction.

[0049] The OCP card slot is used for inserting the first circuit board 100. It should be understood that the first card slot is located on the side of the server chassis, which is not shown in FIG. 1C, and the first circuit board 100 can be directly inserted into the first card slot. Generally, multiple first card slots are provided in the chassis, and there will be idle first card slots. Therefore, the embodiment of the present application uses the idle first card slot to insert the OCP card designed in the embodiment of the present application. It should be understood that the first circuit board 100 involved in the embodiment of the present application is different from the traditional OCP card. The first circuit board 100 provided by the embodiment of the present application is used as an M.2 carrier board, and the M.2 carrier board is provided with an M.2 connector. The M.2 carrier board can be connected to the mainboard and used to expand the storage device. For example, at least one M.2 SSD can be installed on the M.2 carrier board, for example, one M.2 SSD or multiple M.2 SSDs can be installed. The carrier board can be installed with an SSD of SATA type and an SSD of NVMe type.

[0050] As shown in FIG. 1C, the OCP card provided by the embodiment of the present application comprises a first M.2 connector 101 and a serial bus expander 103. The first M.2 connector 101 is used for connecting a solid state disk (SSD, not shown in the figure). The first M.2 connector 101 provided by the embodiment of the present application can be connected to an SSD of SATA type and an SSD of NVMe type, that is, it can be compatible with an SSD of SATA type and an SSD of NVMe type.

[0051] The mainboard 200 comprises a BMC 202.

[0052] The in-position pins of the first circuit board 100 are connected to the BMC 202; it should be understood that the in-position pins of the first circuit board 100 provided in the embodiments of the present application comply with the standard protocol of the OCP card, and the first circuit board 100 includes four in-position pins, which are a first in-position pin PRSNTB3#, a second in-position pin PRSNTB2#, a third in-position pin PRSNTB1# and a fourth in-position pin PRSNTB0#.

[0053] In one possible implementation, the first in-position pin PRSNTB3# and the second in-position pin PRSNTB2# are respectively connected to two IO pins of the BMC 202, and the first in-position pin PRSNTB3# and the second in-position pin PRSNTB2# are both grounded on the first circuit board 100; the third in-position pin PRSNTB1# and the fourth in-position pin PRSNTB0# of the first circuit board 100 are respectively connected to other two IO pins of the BMC 202, that is, the other two IO pins inside the BMC are connected to a high potential through a resistor, or are directly connected to a high potential; the third in-position pin PRSNTB1# and the fourth in-position pin PRSNTB0# of the first circuit board 100 are both suspended on the first circuit board 100.

[0054] The serial bus expander 103 is generally an expansion interface of an Inter-Integrated Circuit (I2C) bus, which is used for serial communication between the first circuit board 100 and the BMC 202. The I2C is a kind of serial communication bus, which uses a multi-master-slave architecture. The I2C serial communication bus generally includes two signal lines, one is a bidirectional data line SDA, and the other is a clock line SCL. The serial data SDA of all devices connected to the I2C bus is connected to the SDA of the bus, and the clock line SCL of each device is connected to the SCL of the bus.

[0055] The in-position pin M2_PRSNT1# of the first M.2 connector 101 and the SSD type pin PEDET1 are both connected to the serial bus interface Searial Bus of the BMC through the serial bus expander 103.

[0056] The BMC 202 is configured to determine whether the first circuit board 100 is in position by detecting the state of the in-position pin of the first circuit board 100, determine whether the SSD is in position by detecting the state of the in-position pin of the M.2 connector when the first circuit board 100 is in position, and obtain the type of the SSD through the SSD type pin when the SSD is in position.

[0057] BMC 202 is used to detect that the levels of two IO pins are low, that is, to detect that the levels of the two IO pins connected to the first presence pin PRSNTB3# and the second presence pin PRSNTB2# are both low, to determine that the first circuit board 100 is present. Because the first presence pin PRSNTB3# and the second presence pin PRSNTB2# are both grounded on the first circuit board 100, the BMC 202 recognizes that the levels of the two IO pins are both low.

[0058] The above four presence pins are compatible with the presence detection of the OCP card. Moreover, according to the detection of the four presence pins, the BMC can allocate PCIE bandwidth to the first circuit board 100.

[0059] The above describes the case where the BMC determines that the first circuit board 100 is present. The following describes the case where the BMC continues to determine that the SSD is present when the first circuit board 100 is present. Because the first circuit board 100 provided in the embodiment of the present application includes an M.2 connector for connecting the SSD, when the first circuit board 100 is present, the M.2 connector is included, and it is only necessary to further determine whether the SSD is connected to the M.2 connector.

[0060] The BMC 202 on the mainboard can automatically recognize whether the first M.2 connector 101 on the first circuit board 100 is connected to a SATA SSD or an NVMe SSD, and configure the interface, so as to realize the compatibility of the server to the two types of SSDs.

[0061] Specifically, when determining whether the SSD is connected to the first M.2 connector 101 and the type of the connected SSD, the BMC 202 reads the level of the presence pin M2 PRSNT1# of the first M.2 connector 101 through the serial bus expander 103, to determine that the SSD is present. Moreover, the BMC 202 reads the SSD type pin PEDET1 through the serial bus expander 103, to determine whether the SSD is of the SATA type or the NVMe type. The embodiment of the present application does not specifically limit the high and low level states of the presence pin, for example, in one possible implementation, when the level of the presence pin M2 PRSNT1# is high, it is determined that the SSD is present; otherwise, when the level of the presence pin M2 PRSNT1# is low, it is determined that the SSD is not present. Similarly, the embodiment of the present application also does not specifically limit the high and low level states of the SSD type pin PEDET1, for example, in one possible implementation, when the level of the SSD type pin PEDET1 is low, it is determined that the SSD is of the SATA type; otherwise, when the level of the SSD type pin PEDET1 is high, it is determined that the SSD is of the NVMe type.

[0062] Since the first circuit board 100 can be replaced without opening the box in structure, if the M.2 SSD fails, the first circuit board 100 can be removed to replace the M.2 SSD without opening the machine case under the condition that the whole machine is disconnected from the power supply, so that the work of plugging and unplugging the cable and moving the whole computing device out of the cabinet and disassembling is avoided, especially in the case that the whole computing device is heavy, the plug-in and plug-out maintenance mode of the present application brings great convenience to operation and maintenance.

[0063] The M.2 SSD carrier in the form of the OCP card provided by the embodiment of the present application only occupies the space of one OCP card in size, and does not need to reserve a special space for the M.2 SSD carrier in advance in the machine case of the computing device, and at the same time, the M.2 SSD carrier can be conveniently removed without opening the machine case of the computing device, so that the maintenance of the M.2 SSD without opening the box is realized.

[0064] In addition, the mainboard 200 further includes a processor CPU and an integrated south bridge (Platform Controller Hub, PCH) 201. In the embodiment of the present application, the first M.2 connector 101 is connected to the processor CPU 201 as an example for introduction. The CPU 201 has an IO expansion capability, and usually these IO expansion ports can be compatible with multiple protocols, for example, PCIE and SATA two protocols can be supported on the same IO port at the same time, and different functions can be realized according to actual needs for configuration.

[0065] The basic input output system (Basic Input Output System, BIOS) is also run on the CPU 201, and is responsible for self-checking and parameter configuration in the starting process of the computing device business system. In the starting process, the BIOS can also obtain information from the BMC 202, and flexibly configure the parameters in the business system according to the obtained information.

[0066] The PCIE interface of the first M.2 connector 101 is connected to the CPU 201.

[0067] The BMC 202 is also used to inform the CPU 201 of the SSD type.

[0068] The CPU 201 is configured to determine a protocol matching the SSD type according to the SSD type, and the SSD type includes SATA and NVMe. The SSD of the SATA type only uses one pin of the PCIE, that is, PCIE X1 / SATA0 shown in FIG. 1. The NVMe uses four pins of the PCIE, and therefore, the CPU 201 configures a PCIE interface with four pins to connect the first M.2 connector 101. Generally, the SSD of the SATA type and the SSD of the NVMe type do not exist at the same time, and therefore, the CPU 201 can configure four PCIE pins, as shown in FIG. 1C, in which the SATA uses one pin of the PCIE X1 / SATA0, and the NVMe uses four pins, that is, the NVMe uses the PCIE X3 in addition to the PCIE X1 / SATA0 shared with the SATA.

[0069] The computing device provided in the embodiment of the present application uses the OCP card as the M.2 carrier board, the M.2 connector is arranged on the OCP card, and the M.2 connector can be used to plug the SSD. Since the OCP card is located on the side of the case of the computing device, the OCP card can be directly plugged and unplugged, and when the SSD or the M.2 connector fails, the OCP card can be directly plugged and unplugged for maintenance without the need to disassemble the case. Moreover, since the computing device provided in the embodiment of the present application uses the idle slot of the OCP card, it is not necessary to specially reserve space in the case of the computing device to set the M.2 carrier board, so that the internal space of the case can be saved. Moreover, the M.2 connector on the OCP card provided in the embodiment of the present application can be compatible with the SSD of the SATA type and the SSD of the NVMe type, and has universality.

[0070] If the M.2 connector can only be compatible with the NVMe SSD and is not compatible with the SATA SSD, the actual application scenario is limited. Since the M.2 is mostly used for the system disk in the industry, the SATA SSD is widely used because of strong software compatibility and easy use, and if only the NVMe SSD can be compatible, the application has great limitations. The M.2 connector provided in the embodiment of the present application can be compatible with the SSD of the SATA type and the SSD of the NVMe type, so that the application scenario is expanded, and great convenience is brought to the actual use.

[0071] In addition, compared with the traditional PCIE M.2 adapter card, since the PCIE slot is expanded from the mainboard through the PCIE M.2 adapter card, and the OCP card is directly plugged into the mainboard, compared with the PCIE M.2 adapter card, the M.2 carrier board in the form of the OCP card provided in the embodiment of the present application uses one less PCIE M.2 adapter card, and the cost can be saved.

[0072] In order to facilitate understanding, the difference between the key position of the SATA and the key position of the NVMe will be introduced below in combination with the drawings.

[0073] Referring to FIG. 2, which is a schematic diagram of a SATA M.2 provided in an embodiment of the present application.

[0074] The SATA M.2 includes two key positions, i.e., B Key and M Key. The SATA M.2 can be applied to Socket 2 and Socket 3.

[0075] Referring to FIG. 3, which is a schematic diagram of an NVMe M.2 provided in an embodiment of the present application.

[0076] The NVMe M.2 includes one key position, i.e., M Key. The NVMe M.2 is only applied to Socket 3.

[0077] The M.2 connector on the OCP card provided in an embodiment of the present application can connect both the key position of the SATA and the key position of the NVMe.

[0078] Generally, in order to realize data backup, two M.2 connectors are arranged on the OCP card to connect two SSDs. The following describes an implementation manner in which the OCP card can connect two SSDs.

[0079] Referring to FIG. 4, which is a schematic diagram of another computing device provided in an embodiment of the present application.

[0080] By comparing FIG. 4 with FIG. 1, it can be found that the first circuit board 100 shown in FIG. 4 further includes a second M.2 connector 102 compared with the first circuit board 100 shown in FIG. 1. The second M.2 connector 102 includes a present position pin M2 PRSNT2# and an SSD type pin PEDET2.

[0081] The computing device provided in an embodiment of the present application includes a first M.2 connector 101 and a second M.2 connector 102. The first M.2 connector 101 is used to connect a first SSD, and the second M.2 connector 102 is used to connect a second SSD. The first SSD and the second SSD are backup for each other. The present position pin M2 PRSNT2# and the SSD type pin PEDET1 of the first M.2 connector are connected to a serial bus interface Searial Bus of a BMC 202 through a serial bus extender 103. The present position pin M2 PRSNT2# and the SSD type pin PEDET2 of the second M.2 connector 102 are connected to the serial bus interface Searial Bus of the BMC through the serial bus extender 103.

[0082] The first M.2 connector 101 includes PCIE X4 pins, the PCIE X3 pins of the first M.2 connector 101 are connected to the CPU 201, and the remaining PCIE X1 pins of the first M.2 connector 101 are connected to the CPU 201 as SATA pin 0; the second M.2 connector 102 includes PCIE X4 pins, the PCIE X3 pins of the second M.2 connector 102 are connected to the CPU 201, and the remaining PCIE X1 pins of the second M.2 connector 102 are connected to the CPU 201 as SATA pin 1.

[0083] The BMC 202 reads the level of the in-place pin M2 PRSNT2# of the second M.2 connector 101 through the serial bus expander 103 to determine whether the SSD is in place. In addition, the BMC 202 reads the SSD type pin PEDET2 through the serial bus expander 103 to determine whether the type of the SSD is SATA or NVMe.

[0084] The application embodiment is not limited to the high and low level states of the in-place pin, for example, in one possible implementation, when the level of the in-place pin M2 PRSNT2# is high, it is determined that the SSD is in place; otherwise, when the level of the in-place pin M2 PRSNT2# is low, it is determined that the SSD is not in place. Similarly, the application embodiment is not limited to the high and low level states of the SSD type pin PEDET2, for example, in one possible implementation, when the level of the SSD type pin PEDET2 is low, it is determined that the type of the SSD is SATA; otherwise, when the level of the SSD type pin PEDET2 is high, it is determined that the type of the SSD is NVMe.

[0085] In addition, the second M.2 connector 102 is also connected to the CPU 201 through the PCIE interface.

[0086] The CPU 201 is configured to determine a protocol matching the type of the SSD according to the type of the SSD, and the type of the SSD includes SATA and NVMe. The SSD of the SATA type only uses one pin of PCIE, that is, PCIE X1 / SATA1 as shown in FIG. 4. The NVMe uses four pins of PCIE, and therefore, the CPU 201 is configured to connect the second M.2 connector 102 through the PCIE interface of four pins. Generally, the SSD of the SATA type and the SSD of the NVMe type do not exist at the same time, and therefore, the CPU 201 is configured to use four PCIE pins, that is, as shown in FIG. 4, the SATA uses one pin of PCIE X1 / SATA1, and the NVMe uses PCIE X3 and PCIE X1 / SATA1.

[0087] The computing device provided in the embodiments of the present application stores a Board Identity (Board ID) on the first circuit board 100. For example, the first circuit board 100 includes a storage chip, and the storage chip stores the Board ID.

[0088] The BMC 202 is further configured to read the Board ID through the serial bus expander 103. The BMC 202 can determine the function of the inserted OCP card by reading the Board ID information. Specifically, the BMC 202 determines whether the first circuit board 100 is an M.2 carrier board through the Board ID. If the first circuit board 100 is not an M.2 carrier board, the BMC 202 configures the OCP card according to the standard OCP card.

[0089] The BMC 202 determines whether the OCP card is installed on the OCP slot through the four present signals PRSNTB0#-PRSNTB3# of the first circuit board 100. Then, the BMC 202 determines the type of the installed OCP card according to the Board ID on the OCP card. If the OCP card is a standard general OCP card, the BMC 202 can allocate the PCIE bandwidth according to the signal combination of the PRSNTB0#-PRSNTB3#.

[0090] If the BMC 202 determines that the installed OCP card is an M.2 carrier board according to the Board ID, the BMC 202 continues to determine whether the M.2 SSD card is installed on the M.2 carrier board according to the M2_PRSNT# and PEDET signals. The BMC 202 determines whether the installed M.2 SSD card is a SATA M.2 SSD or an NVMe M.2 SSD. If the installed M.2 SSD card is a SATA M.2 SSD, the BMC 202 needs to notify the BIOS in the CPU 201 to configure the M.2 connector as a SATA interface. If the installed M.2 SSD card is an NVMe M.2 SSD, the BMC 202 notifies the BIOS in the CPU 201 to configure the M.2 connector as a PCIE interface, so as to realize the compatibility of different types of M.2 SSDs.

[0091] The computing device provided in the embodiments of the present application can be provided with two M.2 connectors on the OCP card. The BMC can automatically identify whether the M.2 connector of the OCP card is connected to a SATA SSD or an NVMe SSD, and perform corresponding configuration on the PCIE interface of the CPU, so as to realize the compatibility of the motherboard to the two types of SSDs.

[0092] It should be understood that the number of M.2 connectors provided on the OCP card is not specifically limited in the embodiments of the present application. The number of M.2 connectors can be one, two or more. The above only takes one M.2 connector and two M.2 connectors as examples for introduction. The working principle when the number of M.2 connectors is more is similar, and will not be described here.

[0093] Based on the computing device provided in the above embodiments, the embodiment of the present application further provides a clock configuration method of the computing device, which will be described in detail below with reference to the accompanying drawings.

[0094] Referring to FIG. 5, it is a flow chart of a control method of a computing device provided by the embodiment of the present application.

[0095] The control method of the computing device provided by the embodiment of the present application, the computing device comprises: a first card slot, a first circuit board and a mainboard; the first card slot is used for inserting an OCP card; the OCP card comprises: an M.2 connector; the M.2 connector is used for connecting a solid state disk (SSD); the mainboard comprises a baseboard management controller (BMC); an in-place pin of the OCP card is connected to the BMC; the in-place pin and the SSD type pin of the M.2 connector are both connected to a serial bus interface of the BMC.

[0096] The method comprises:

[0097] S501: The BMC determines whether the first circuit board is in place according to the state of the in-place pin of the first circuit board;

[0098] The in-place pin of the OCP card is connected to the BMC; it should be understood that the in-place pin of the OCP card provided by the embodiment of the present application complies with the standard protocol of the OCP card, and the OCP card comprises four in-place pins. Two in-place pins are both connected to ground on the OCP card; the pin is suspended on the OCP card. When the BMC detects that the level of the two IO pins is low, it is determined that the OCP card is in place.

[0099] S502: In the case that the first circuit board is in place, the BMC determines whether the SSD is in place according to the state of the in-place pin of the M.2 connector;

[0100] The BMC reads the level of the in-place pin of the M.2 connector through the serial bus expander to determine whether the SSD is in place.

[0101] S503: In the case that the SSD is in place, the BMC obtains the type of the SSD through the SSD type pin.

[0102] For example, when the BMC reads the level of the SSD type pin through the serial bus expander and the level is low, it is determined that the type of the SSD is SATA type; otherwise, when the level of the SSD type pin PEDET1 is high, it is determined that the type of the SSD is NVMe type.

[0103] The control method of the computing device provided in the embodiments of the present application can determine whether the OCP card is in place through the in-place pin, and when the OCP card is in place, determine whether the SSD is in place by detecting the state of the in-place pin of the M.2 connector; when the SSD is in place, the BMC obtains the type of the SSD through the SSD type pin. The M.2 connector on the OCP card can be compatible with the SATA type SSD and the NVMe type SSD, has universality, expands the application scenario of the SSD, and brings great convenience to actual use.

[0104] The central processing unit CPU can determine a protocol matched with the type of the SSD according to the type of the SSD; for example, the type of the SSD includes SATA and NVMe.

[0105] In a possible implementation manner, the control method provided in the embodiments of the present application further includes, after step S501:

[0106] The board ID is read through the serial bus expander, and whether the OCP card is an M.2 carrier board is determined through the board ID; if the OCP card is not an M.2 carrier board, the OCP card is configured according to a standard OCP card.

[0107] In order for those skilled in the art to better understand and implement the technical solutions provided in the embodiments of the present application, a complete process in which the BMC identifies the OCP card is introduced below with reference to the accompanying drawings.

[0108] Referring to FIG. 6, this is a flowchart of another control method of a computing device provided in the embodiments of the present application.

[0109] The control method of the computing device provided in the embodiments of the present application includes:

[0110] S601: The BMC determines whether the first circuit board is in place according to the in-place pin signal of the first circuit board.

[0111] After the hardware system of the computing device is deployed, the power supply is connected, the alternating current is powered on, and the BMC is started. It should be understood that the side of the server chassis is provided with a first card slot, and whether the first circuit board is in place is determined, that is, whether the first card slot is inserted with the first circuit board.

[0112] If there is no first circuit board, the server will start according to the default logic and ignore the PCIE bandwidth configuration on the first card slot. The first card slot can be an OCP card slot on the rear side of the server.

[0113] For example, the serial bus expander is an I2C bus.

[0114] S602: In the case where the first circuit board is in place, the BMC reads the Board ID of the first circuit board through the serial bus expander, and determines whether the first circuit board is an M.2 adapter card.

[0115] S603: In the case that the first circuit board is an M.2 adapter card, the BMC reads the present pin of the M.2 connector through the serial bus expander, and judges whether the SSD is present.

[0116] S604: In the case that the SSD is present, the BMC reads the type pin of the SSD through the serial bus expander, and judges whether the SSD type is SATA or NVMe. If the SSD is not present, the BIOS in the CPU configures the bandwidth according to two X4 PCIE interfaces.

[0117] If the BMC judges that the M.2 connector is not inserted with the SSD, the BMC delivers the information that the SSD is not present to the BIOS of the CPU.

[0118] S605: When judging that the SSD is a SATA M.2 SSD, the BIOS in the CPU configures the bandwidth according to two SATA interfaces, and guarantees that the SATA M.2 SSD is available.

[0119] S606: When judging that the SSD is an NVMe M.2 SSD, the BIOS in the CPU configures the bandwidth according to two X4 PCIE interfaces, and guarantees that the NVMe M.2 SSD is available.

[0120] The control method of the computing device provided in the embodiments of the present application can set multiple M.2 connectors on the first circuit board, and the BMC can automatically identify whether the M.2 connector of the first circuit board is connected with a SATA SSD or an NVMe SSD, and perform corresponding configuration on the PCIE interface of the CPU, so as to realize the compatibility of the motherboard to the two types of SSDs.

[0121] The control method of the computing device provided in the embodiments of the present application designs an M.2 carrier plate which is the same as the OCP card in form (including size and the physical size of the gold finger / connector connected with the motherboard, which is the same as the OCP card), and the M.2 carrier plate is provided with an M.2 connector which can be used to insert the SSD. Since the OCP card slot is located on the side of the case of the computing device, it can be directly inserted and pulled out, and when the SSD or the M.2 connector fails, it can be directly inserted and pulled out for maintenance without the need to disassemble the case. Moreover, the computing device provided in the embodiments of the present application utilizes the idle slot of the OCP card, and does not need to specially reserve space in the case of the computing device to set the M.2 carrier plate, so that the internal space of the case can be saved. Moreover, the M.2 connector on the OCP card provided in the embodiments of the present application can be compatible with the SATA type SSD and the NVMe type SSD, and has universality.

[0122] Since M.2 is mostly used for system disks in the industry, SATA SSDs are widely used due to strong software compatibility and easy use, and if only NVMe SSDs can be compatible, there is a greater limitation in application. The M.2 connector provided in the embodiments of the present application can be compatible with SATA type SSDs and NVMe type SSDs, expand the application scenarios, and bring great convenience to actual use.

[0123] In addition, compared with the traditional PCIE M.2 adapter card, the first circuit board provided in the embodiments of the present application is directly plugged into the mainboard, compared with the PCIE slot which is expanded from the mainboard through the PCIE M.2 adapter card, the OCP card form of the M.2 carrier provided in the embodiments of the present application uses one less PCIE M.2 adapter card, which can save costs.

[0124] The above is only a preferred embodiment of the present application, and does not limit the present application in any form. Although the present application has been disclosed as above with a preferred embodiment, it is not intended to limit the present application. Any person skilled in the art can make many possible changes and modifications to the technical solutions of the present application, or modify equivalent embodiments with equivalent changes, without departing from the scope of the technical solutions of the present application, by using the disclosed methods and technical contents. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application, without departing from the content of the technical solutions of the present application, still belongs to the protection scope of the technical solutions of the present application.

Claims

1. A computing device, characterized in that include: a first card slot, a first circuit board, and a main board; The first card slot is used to plug the first circuit board; The first circuit board includes: an M.2 connector; the M.2 connector is used to connect to a solid state drive (SSD); The mainboard includes a baseboard management controller BMC; The in-position pin of the first circuit board is connected to the BMC; The in-position pin of the M.2 connector and the SSD type pin of the M.2 connector are connected to the serial bus interface of the BMC; The BMC is used to detect the status of the presence pin of the first circuit board to determine whether the first circuit board is in place; when the first circuit board is in place, determine whether the SSD is in place according to the level of the presence pin of the M.2 connector; when the SSD is in place, determine the type of the SSD according to the level of the SSD type pin.

2. The computing device according to claim 1, wherein The mainboard also includes: a central processing unit; The M.2 connector is connected to the central processing unit; The BMC is further configured to inform the central processing unit of the SSD type; The central processing unit is used to determine a protocol matching the SSD type according to the SSD type, where the protocol includes a Serial Advanced Technology Attachment interface SATA protocol and a Non-Volatile Memory Host Controller Interface NVMe protocol.

3. The computing device according to claim 1, wherein: The M.2 connector includes a first M.2 connector and a second M.2 connector, and the first circuit board further includes a serial bus expander; The first M.2 connector is used to connect a first SSD, and the second M.2 connector is used to connect a second SSD; The first SSD and the second SSD serve as backup for each other; The in-position pin and the SSD type pin of the first M.2 connector are both connected to the serial bus interface of the BMC through the serial bus expander; The in-position pin and the SSD type pin of the second M.2 connector are both connected to the serial bus interface of the BMC through the serial bus expander; The first M.2 connector includes a PCIE X4 pin, a PCIE X3 pin of the first M.2 connector is connected to the central processing unit, and the remaining PCIE X1 pins of the first M.2 connector are used as SATA pins to connect to the central processing unit; The second M.2 connector includes a PCIE X4 pin, a PCIE X3 pin of the second M.2 connector is connected to the central processing unit, and the remaining PCIE X1 pins of the second M.2 connector are used as SATA pins to connect to the central processing unit.

4. The computing device according to claim 1, wherein: A first on-position pin and a second on-position pin of the first circuit board are respectively connected to two IO pins of the BMC, and the first on-position pin and the second on-position pin are both grounded on the first circuit board; a third on-position pin and a fourth on-position pin of the first circuit board are respectively connected to the other two IO pins of the BMC; and the third on-position pin and the fourth on-position pin of the first circuit board are both left floating on the first circuit board; The BMC is configured to determine that the first circuit board is in place when detecting that the levels of the two IO pins connected to the first in-place pin and the second in-place pin are low.

5. The computing device according to any one of claims 1 to 4, characterized in that: The first circuit board also stores a board ID; The BMC is further configured to read the board ID and determine whether the first circuit board is an M.2 carrier board based on the board ID. If it is not the M.2 carrier board, the central processor is configured to configure the first circuit board according to the bandwidth requirements of the standard OCP card.

6. The computing device according to any one of claims 1 to 4, wherein: The BMC is specifically used to determine that the SSD type is NVMe when it is detected that the level of the SSD type pin is high; and to determine that the SSD type is SATA when it is detected that the level of the SSD type pin is low.

7. A method for controlling a computing device, characterized in that: The computing device includes: a first card slot, a first circuit board, and a motherboard; the first card slot is used to plug the first circuit board; the first circuit board includes: an M.2 connector; the M.2 connector is used to connect to a solid-state drive (SSD); the motherboard includes a baseboard management controller (BMC); a position pin of the first circuit board is connected to the BMC; the position pin of the M.2 connector and the SSD type pin of the M.2 connector are both connected to a serial bus interface of the BMC; The method includes: determining whether the first circuit board is in place according to the level of the in-place pin of the first circuit board; When the first circuit board is in place, determining whether the SSD is in place according to the level of the in-place pin of the M.2 connector; When the SSD is in place, the type of the SSD is determined by the level of the SSD type pin.

8. The control method according to claim 7, characterized in that: Also includes: Determine a protocol matching the SSD type according to the SSD type; the protocol includes a Serial Advanced Technology Attachment interface SATA protocol and a Non-Volatile Memory Host Controller Interface NVMe protocol.

9. The control method according to claim 7, characterized in that: The first circuit board also stores a board ID, and the method further includes: The board ID is read, and whether the first circuit board is an M.2 carrier board is determined by the board ID. If it is not the M.2 carrier board, the central processor is enabled to configure the first circuit board according to the bandwidth requirement of the standard OCP card.

10. The computing device according to claim 1, wherein: The determining the type of the SSD by the level of the SSD type pin specifically includes: When the level of the SSD type pin is detected to be high, the SSD type is determined to be NVMe; when the level of the SSD type pin is detected to be low, the SSD type is determined to be SATA.

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