Method and apparatus for executing leveled homomorphic encryption computation

Abstract

Embodiments of the present description provide a method and apparatus for executing a leveled homomorphic encryption computation. The method is executed by a GPU, and comprises: acquiring target data, waiting for undergoing current-layer processing under the action of a target homomorphic operation function; reading a first-type pre-calculation parameter corresponding to a current layer from a global memory, and reading a second-type pre-calculation parameter corresponding to the current layer from a constant memory, wherein the second-type pre-calculation parameter is used by a plurality of threads, and the data volume is less than a preset threshold; at least on the basis of the first-type pre-calculation parameter and the second-type pre-calculation parameter, performing the current-layer processing on the target data to obtain an intermediate result; and according to the use requirements of the intermediate result between the threads, storing the intermediate result in a corresponding storage structure among a plurality of storage structures.

Description

Method and apparatus for performing hierarchical homomorphic encryption operation

[0001] The present application claims priority to the Chinese patent application No. 202410425396.8, filed on April 9, 2024, and entitled "Method and apparatus for performing hierarchical homomorphic encryption operation", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] One or more embodiments of the present specification relate to the technical field of data security, and in particular to a method and apparatus for performing hierarchical homomorphic encryption operation. BACKGROUND

[0003] Hierarchical homomorphic encryption operation is one of the main technical means currently used to solve data privacy protection. However, due to the problem of operation efficiency, accelerating hierarchical homomorphic encryption operation based on a heterogeneous framework is a necessary step for productization and commercialization. The graphics processing unit (GPU) in the heterogeneous framework has rich computing resources and can be used to accelerate many graphics processing algorithms. Therefore, using GPU to accelerate hierarchical homomorphic encryption operation is one of the mainstream exploration schemes in the industry. SUMMARY

[0004] One or more embodiments of the present specification describe a method and apparatus for performing hierarchical homomorphic encryption operation, which can improve the efficiency of hierarchical homomorphic encryption operation.

[0005] In a first aspect, a method for performing hierarchical homomorphic encryption operation is provided, which is executed by a graphics processing unit (GPU). The GPU has a plurality of storage structures, including at least a global memory and a constant memory. The method comprises:

[0006] obtaining target data to be processed by a target homomorphic operation function in a current layer;

[0007] reading a first type of pre-computed parameters corresponding to the current layer from the global memory, and reading a second type of pre-computed parameters corresponding to the current layer from the constant memory, wherein the second type of pre-computed parameters are used by a plurality of threads, and the data volume is less than a predetermined threshold;

[0008] performing current layer processing on the target data based on at least the first type of pre-computed parameters and the second type of pre-computed parameters, to obtain an intermediate result;

[0009] storing the intermediate result in a corresponding storage structure of the plurality of storage structures according to the usage demand of the intermediate result among threads.

[0010] In a second aspect, an apparatus for performing hierarchical homomorphic encryption operations is provided, which is arranged in a graphics processing unit (GPU) having a plurality of memory structures, the plurality of memory structures including at least a global memory and a constant memory, and the apparatus includes:

[0011] an obtaining unit configured to obtain target data to be processed by a target homomorphic operation function;

[0012] a reading unit configured to read first pre-computed parameters corresponding to a current layer from the global memory and read second pre-computed parameters corresponding to the current layer from the constant memory, wherein the second pre-computed parameters are used by a plurality of threads and have a data volume less than a predetermined threshold;

[0013] an executing unit configured to perform current layer processing on the target data based on at least the first pre-computed parameters and the second pre-computed parameters to obtain intermediate results;

[0014] a storing unit configured to store the intermediate results in corresponding memory structures of the plurality of memory structures according to usage requirements among threads.

[0015] In a third aspect, a computer readable storage medium is provided, which stores a computer program, and when the computer program is executed in a computer, the computer is caused to execute the method of the first aspect.

[0016] In a fourth aspect, a computing device is provided, which includes a memory and a processor, and the memory stores executable code, and when the processor executes the executable code, the method of the first aspect is implemented.

[0017] The method and apparatus for performing hierarchical homomorphic encryption operations provided by one or more embodiments of the present specification can fully utilize the performance advantages of different memory structures by storing pre-computed parameters of a homomorphic operation function in different memory structures of a GPU according to categories and storing intermediate results obtained in the process of executing the homomorphic operation function in different memory structures of the GPU according to usage requirements among threads, thereby improving the efficiency of hierarchical homomorphic encryption operations. BRIEF DESCRIPTION OF DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present specification, the drawings needed in the embodiment description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present specification, and for those skilled in the art, other drawings can also be obtained without creative labor based on these drawings.

[0019] FIG. 1 shows a heterogeneous framework schematic diagram;

[0020] Figure 2 illustrates a method of performing hierarchical homomorphic encryption operations based on a heterogeneous framework;

[0021] Figure 3 illustrates a hierarchical pre-computed parameter;

[0022] Figure 4 illustrates a modular deployment of operators in one example;

[0023] Figure 5 illustrates a resource pooling management;

[0024] Figure 6 illustrates a method flow diagram of performing hierarchical homomorphic encryption operations according to one embodiment;

[0025] Figure 7 illustrates a device diagram of performing hierarchical homomorphic encryption operations according to one embodiment. DETAILED DESCRIPTION

[0026] The schemes provided in the present specification will be described below with reference to the accompanying drawings.

[0027] The aforementioned heterogeneous framework will be described first.

[0028] Figure 1 illustrates a heterogeneous framework. In Figure 1, the heterogeneous framework includes a CPU (also referred to as a host) and a GPU (also referred to as a device), which are connected through a PCle bus to work together. Specifically, the GPU is usually used to perform computation-intensive tasks, such as large matrix operations. The CPU can be used to perform complex logical operations, and thus is suitable for controlling intensive tasks. In addition, threads running on the CPU are heavyweight, and the context switching overhead is large, but threads running on the GPU are lightweight. Therefore, the heterogeneous framework based on the CPU and the GPU can complement each other, with the CPU responsible for processing logically complex serial programs, and the GPU focusing on processing data-intensive parallel computing programs, thereby maximizing efficiency.

[0029] In Figure 1, the GPU can include multiple memory structures: shared memory, constant memory, registers, and global memory (also referred to as video memory). Among them, the shared memory can be accessed by all threads within a thread block, and its lifetime is consistent with the thread block. The constant memory is a read-only memory, which is used to store data that will not be changed during kernel execution. It should be understood that the threads can broadcast the contents read from the constant memory to other threads in the thread bundle after reading. Therefore, when all threads in the thread bundle read data from the same address in the constant cache, the reading speed is comparable to reading from the register. The register is only accessed by a single thread. The global memory can be accessed by all threads, and can be accessed by the CPU.

[0030] It should be understood that different storage structures in the GPU have different performance advantages, such as a large storage space of the global memory and a fast reading speed of the constant memory, and the like. The present solution will fully utilize the performance advantages of different storage structures of the GPU to accelerate the homomorphic encryption operation, which will be described in detail later.

[0031] FIG. 2 shows a schematic diagram of a method for performing a homomorphic encryption operation based on a heterogeneous framework. In FIG. 2, first, a user configures basic parameters (also referred to as algorithm parameters) of each homomorphic operation function in the homomorphic encryption operation to be executed through a CPU. Taking CKKS, BFV or TFHE as an example, the basic parameters can include a polynomial length N, a number of RNS decompositions pnum, a plaintext modulus t and a ciphertext modulus Q (a product of pnum qis), and the like. Then, the CPU calculates pre-computed parameters based on the basic parameters configured by the user, and synchronizes the basic parameters and the pre-computed parameters to the GPU. The pre-computed parameters can include pnum moduli under RNS decomposition, pnum sets of N-length NTT coefficients and CRT transformation coefficients, and the like. It should be understood that the basic parameters and the pre-computed parameters on the CPU side can constitute context parameters on the CPU side, and the basic parameters and the pre-computed parameters on the GPU side can constitute context parameters on the GPU side.

[0032] It should be noted that for some pre-computed parameters, the CPU can organize them according to levels. For example, the pnum moduli can be organized into pnum levels. For the pre-computed parameters maintained by the CPU according to levels, the GPU also maintains them according to levels.

[0033] After synchronizing the pre-computed parameters to the GPU, the user can build a corresponding application for the homomorphic encryption operation to be executed, which includes a Host code part running on the CPU side and a device code part running on the GPU side. Through execution of the Host code part, a part of homomorphic operations in the homomorphic encryption operation can be performed on the CPU side, and through execution of the device code part, another part of homomorphic operations can be performed on the GPU side, that is, a part of homomorphic operations in the homomorphic encryption operation is performed on the CPU side, and another part of homomorphic operations is performed on the GPU side. Of course, in actual applications, all homomorphic operations in the homomorphic encryption operation can be performed on the GPU side, which is not limited in the present solution.

[0034] It should be understood that after executing the above-mentioned application, the operation result of the homomorphic encryption operation can be obtained.

[0035] It should be noted that in order to improve the efficiency of the hierarchical homomorphic encryption operation, the scheme accelerates the homomorphic operation executed on the GPU. Specifically, the following improvements are made to the algorithm framework executed on the GPU:

[0036] First, different storage structures of the GPU are used hierarchically.

[0037] First, pre-computed parameters are stored in different storage structures of the GPU according to their categories. Specifically, pre-computed parameters whose data volume is greater than a predetermined threshold or which will not be accessed by multiple threads at the same address (hereinafter referred to as first category pre-computed parameters) are stored in the global memory. Pre-computed parameters that will be used by multiple threads within a thread block and have a data volume less than a predetermined threshold (i.e., second category pre-computed parameters) are stored in the constant memory.

[0038] As mentioned earlier, since threads can broadcast the contents read from the constant memory to other threads in the thread bundle, storing the above-mentioned second category pre-computed parameters in the constant memory can improve the reading efficiency. For pre-computed parameters that will not be accessed by multiple threads at the same address, since they cannot take advantage of the constant memory when stored in the constant memory, they are stored in the global memory.

[0039] Second, intermediate results obtained during the execution of the homomorphic operation function are stored in different storage structures of the GPU according to their usage requirements among threads, which will be described in detail later.

[0040] Based on the first improvement, the performance advantages of different storage structures can be fully utilized, thereby accelerating the execution of homomorphic operations on the GPU.

[0041] Second, for pre-computed parameters organized in a hierarchy, the CPU and the GPU maintain the same layer identifier for the same level.

[0042] Figure 3 shows a schematic diagram of hierarchical pre-computed parameters. In Figure 3, the CPU maintains the same L-level pre-computed parameters for the homomorphic operation function as the GPU, and the Lth level of the CPU has the same layer identifier as the Lth level of the GPU, the L-1th level of the CPU has the same layer identifier as the L-1th level of the GPU, and so on.

[0043] In Figure 3, each level of pre-computed parameters is stored in different storage structures according to their categories. For example, part of the Lth level pre-computed parameters will be stored in the global memory, and another part will be stored in the constant memory.

[0044] Based on the second improvement, the communication efficiency between the CPU and the GPU can be accelerated, thereby accelerating the execution of homomorphic operations on the GPU.

[0045] Thirdly, the operators in the homomorphic operation function are decoupled, and multiple implementation modules are maintained for target operators therein. After the user configures the basic parameters, the GPU adaptively selects the corresponding target implementation module for the target operator according to the configured basic parameters. The target operator herein includes any one of the following: a modulo operation operator, an NTT operator, a base conversion operator, a Galois operator, and the like.

[0046] Figure 4 shows a schematic diagram of modular deployment of operators in one example. In Figure 4, the NTT operator and the modulo operation operator each correspond to three implementation modules, and each implementation module processes different module bit widths. After the user configures pnum qis, for each operator, among the three implementation modules corresponding thereto, the module bit width processed is not less than the pre-configured module bit width (i.e., the bit width of qi), and the implementation module with the optimal performance under the current hardware environment is selected as the target implementation module.

[0047] In addition, resource pooling management is also performed in the present scheme, which can be specifically seen from Figure 5. In Figure 5, a stream pool, a random number pool, and a video memory pool are constructed in the GPU, wherein multiple streams Stream0-StreamN are initialized in the stream pool. The stream herein can be regarded as a series of tasks (possibly issued by different host threads) executed in sequence, and multiple tasks in the same stream are executed in series, and tasks between different streams can be executed in parallel. During the homomorphic operation, one or more streams in the stream pool can be used to improve the parallelism of the calculation (i.e., the GPU manages concurrent tasks through streams). It should be noted that the multiple streams in the stream pool can be uniformly initialized before the beginning of the hierarchical homomorphic encryption operation, and uniformly released after the end of the hierarchical homomorphic encryption operation, so that the performance impact caused by stream initialization and stream release during the homomorphic operation can be avoided.

[0048] The random number pool described above can be regarded as a fixed-size space allocated in the global memory, which is filled with random numbers for subsequent operation process. When all random numbers are used, they will be filled with new random numbers. The random number pool will be released after the homomorphic operation, so that the performance impact caused by frequent generation of random numbers during the operation process can be avoided.

[0049] The above-mentioned video memory pool can be regarded as a larger space allocated in the global memory for use in subsequent operation processes. Specifically, in the operation process, a small area (hereinafter referred to as a video memory block) can be applied from the video memory pool and allocated to a certain variable. After the declaration period of the variable ends, the corresponding video memory block is recycled and identified as available, and continues to be allocated to a certain variable in the subsequent operation process. When the video memory pool space is not enough, a new area will be initialized again until the entire GPU runs out of video memory and an error of insufficient video memory occurs. The video memory pool will not be released during the homomorphic operation process, and will be released after the homomorphic operation ends, thereby avoiding the performance impact caused by frequent initialization and release of video memory during the operation process.

[0050] It should be noted that in practice, the video memory block in the video memory pool can also be allocated to a certain stream in the stream pool and exclusively occupied by the stream. Other streams need to be synchronized first (see the dashed arrow in FIG. 5) to prevent data reading and writing errors.

[0051] The following describes the process of performing homomorphic operations on the GPU based on the above improvements.

[0052] FIG. 6 shows a method flowchart for performing hierarchical homomorphic encryption operations according to an embodiment, which is executed by the GPU in the heterogeneous framework. It should be noted that the method includes multiple rounds of iteration, and FIG. 6 shows the method steps included in any round of iteration. It should be understood that all homomorphic operations on the GPU can be completed by repeatedly executing the method steps shown in FIG. 6. As shown in FIG. 6, the method can include the following steps:

[0053] Step S602: Obtain target data to be processed by a target homomorphic operation function for the current layer.

[0054] The above-mentioned target homomorphic operation function refers to a homomorphic operation function executed on the GPU among the multiple homomorphic operation functions included in the hierarchical homomorphic encryption operation to be executed.

[0055] In addition, when the above-mentioned any round of iteration is the first round of iteration, the above-mentioned target data can be the plaintext or ciphertext calculation result provided by the CPU after the execution of the homomorphic operation function on the CPU side is completed, or the user input data forwarded by the CPU. When the above-mentioned any round of iteration is the non-first round of iteration, the above-mentioned target data is the plaintext or ciphertext calculation result obtained in the last round of iteration.

[0056] In the case where the target data is provided by the CPU to the GPU, the target layer identifier can also be included in the variable structure (such as a class) corresponding to the target data, so that the GPU can determine the current layer based on the target layer identifier.

[0057] In the case that the target data is the plaintext or ciphertext calculation result obtained in the last iteration, the GPU can determine the target layer identifier corresponding to the plaintext or ciphertext calculation result (specifically, refer to the determination method of the layer identifier corresponding to the final result below), and determine the current layer based thereon.

[0058] It should be noted that for the target data described above, the GPU can take it as a variable and apply a memory block from the memory pool to store the target data.

[0059] Step S604, read the first type of pre-computed parameters corresponding to the current layer from the global memory, and read the second type of pre-computed parameters corresponding to the current layer from the constant memory.

[0060] Among them, the data amount of the first type of pre-computed parameters is greater than a predetermined threshold or the same address will not be taken by multiple threads. The second type of pre-computed parameters will be used by multiple threads in a thread block, and the data amount is less than a predetermined threshold. In one example, the first type of pre-computed parameters here can be, for example, CRT transformation coefficients, etc., and the second type of pre-computed parameters can be, for example, pnum moduli under RNS decomposition and NTT coefficients, etc.

[0061] Since the threads can broadcast the contents read from the constant memory to other threads in the thread bundle to which they belong, storing the second type of pre-computed parameters described above in the constant memory can improve the reading efficiency.

[0062] Specifically, the GPU reads the first type of pre-computed parameters corresponding to the current layer from the global memory and reads the second type of pre-computed parameters corresponding to the current layer from the constant memory according to the target layer identifier described above.

[0063] For example, assuming that the target layer identifier described above is the layer identifier corresponding to the Lth layer in FIG. 3, the first type of pre-computed parameters of the Lth layer can be read from the global memory and the second type of pre-computed parameters of the Lth layer can be read from the constant memory according to the target layer identifier.

[0064] Of course, in practice, the basic parameters related to the target homomorphic operation function are also read from the global memory. The basic parameters here can be, for example, polynomial length N, RNS decomposition number pnum, plaintext modulus t, and ciphertext modulus Q, etc.

[0065] Step S606, at least based on the first type of pre-computed parameters and the second type of pre-computed parameters, performing current layer processing on the target data to obtain an intermediate result.

[0066] In a case that the target homomorphic operation function is an encryption function or a decryption function, the performing the current layer processing on the target data includes: reading a certain number of random numbers from the random number pool, and performing the current layer processing on the target data based on the read random numbers, the first type of pre-computed parameters, and the second type of pre-computed parameters.

[0067] It should be noted that the scheme reads random numbers from the random number pool, which can avoid the performance impact caused by frequent generation of random numbers in the operation process.

[0068] In practice, the target homomorphic operation function can include a plurality of target operators, where the target operator refers to an operator for which the GPU maintains a plurality of implementation modules. The plurality of target operators includes at least one of a modulo operation operator, a number theory transform (NTT) operator, a base conversion operator, and a Galois operator.

[0069] In a case that the target homomorphic operation function includes a plurality of target operators, the performing the current layer processing on the target data includes: executing each target implementation module pre-selected for the plurality of target operators. Each target implementation module is an implementation module corresponding to each of the plurality of target operators, and has a modulus bit width not less than a pre-configured modulus bit width (i.e., the bit width of qi) and optimal performance in the current hardware environment.

[0070] It should be noted that the modular design of the target operator not only enhances the flexibility of the target operator execution, but also facilitates performance testing of the target operator.

[0071] In addition, in step S606, the performing the current layer processing on the target data can be based on the base parameters read from the global memory, and the first type of pre-computed parameters and the second type of pre-computed parameters.

[0072] Taking a case that the target homomorphic operation function includes an NTT operator as an example, the read base parameters can include a polynomial length N, modulus qi of RNS decomposition, and modulus number pnum, and the read first type of pre-computed parameters can include pnum NTT coefficients. The performing the current layer processing on the target data includes: dividing the target data into pnum independent computing tasks according to the modulus qi of RNS decomposition. Each independent computing task is allocated to a certain stream applied from the stream pool, so as to perform NTT transform with a length of the polynomial length N on the pnum independent computing tasks based on the pnum NTT coefficients in parallel using multi-threading.

[0073] It should be understood that the pnum independent computing tasks can be calculated faster after each independent computing task is assigned to a certain stream applied from the stream pool. In addition, since the stream pool is uniformly initialized before the hierarchical homomorphic encryption operation starts and uniformly released after the hierarchical homomorphic encryption operation ends, the performance impact caused by stream initialization and stream release during the homomorphic operation can be avoided.

[0074] At step S608, the intermediate result is stored in a corresponding storage structure in the plurality of storage structures according to the use requirement of the intermediate result among threads.

[0075] It should be noted that the above intermediate result can be divided into two categories: input or final output of the kernel function, and intermediate output of the kernel function.

[0076] In the case that the above intermediate result is the input or final output of the kernel function, the intermediate result can be stored in the global memory.

[0077] In the case that the above intermediate result is the intermediate output of the kernel function, the intermediate result is stored in a corresponding storage structure in the plurality of storage structures according to the use requirement of the intermediate result among threads.

[0078] Specifically, if the use requirement indicates synchronization or cross-thread use among threads in a thread block, the intermediate result is stored in the shared memory; if the use requirement indicates single-thread use, the intermediate result is stored in the register to use the register resource as much as possible; if the use requirement indicates synchronization or use across thread blocks, the intermediate result is stored in the global memory.

[0079] Of course, in practice, in addition to the above intermediate result, the GPU can also obtain a final result corresponding to the target homomorphic operation function. For this final result, the GPU can determine the layer identifier corresponding to the final result according to the modulus loss number corresponding to the target homomorphic operation function.

[0080] Specifically, the GPU can take the modulus loss number corresponding to the target homomorphic operation function as the loss layer number n. Then, the update layer can be determined according to the difference between the current layer and the loss layer number. For example, when the current layer is the Lth layer, the update layer is the L-nth layer. Finally, the layer identifier corresponding to the L-nth layer is taken as the layer identifier corresponding to the final result.

[0081] It should be noted that after the GPU obtains the above calculation result and the corresponding layer identifier, if the iteration end condition has not been reached at this time (for example, there are still homomorphic operation functions to be executed), then the calculation result is taken as the target data, and the next round of iteration is performed on the updated layer as the current layer until the iteration end condition is reached. If the iteration end condition is reached, the GPU can provide the final result and the corresponding layer identifier to the CPU, so that the CPU determines the operation result of the hierarchical homomorphic encryption operation.

[0082] In summary, the present scheme makes the following improvements to the algorithm framework executed on the GPU: 1. The pre-computed parameters and intermediate results are classified and stored in different storage structures on the GPU to take advantage of the performance of different levels of storage, and efficient pooling management is performed on important resources (random numbers, streams, and memory) required during the operation to avoid the performance impact of temporary allocation and release. 2. In order to avoid frequent transmission of context parameters between devices, a layer identifier mechanism is constructed, so that within a device (i.e. within a GPU), the pre-computed parameters of the corresponding layer can be selected by the layer identifier, and between devices (i.e. between CPU and GPU), the layer identifier can be used for fast synchronization, significantly improving the communication efficiency of the context between devices. 3. The algorithm implementation is highly modularized, each operator contains one or more implementations, and the optimal implementation combination can be selected adaptively according to different basic parameters, and the performance and development efficiency can be improved by quickly testing different GPU hardware combinations.

[0083] Corresponding to the above method of performing hierarchical homomorphic encryption operation, an embodiment of the present specification also provides a device for performing hierarchical homomorphic encryption operation, which is arranged in a graphics processor GPU. The GPU has a plurality of storage structures, including at least a global memory and a constant memory. As shown in FIG. 7, the device can include:

[0084] The acquisition unit 702 is configured to acquire target data to be processed by a target homomorphic operation function in a current layer.

[0085] The reading unit 704 is configured to read first pre-computed parameters corresponding to the current layer from the global memory, and read second pre-computed parameters corresponding to the current layer from the constant memory, wherein the second pre-computed parameters are used by a plurality of threads, and the data volume is less than a predetermined threshold.

[0086] The execution unit 706 is configured to perform current layer processing on the target data based on at least the first pre-computed parameters and the second pre-computed parameters, to obtain an intermediate result.

[0087] The storage unit 708 is configured to store the intermediate result in a corresponding storage structure of the plurality of storage structures according to the usage demand of the intermediate result among threads.

[0088] In an embodiment, the plurality of storage structures further include: shared memory and registers;

[0089] The storage unit 708 is specifically configured to:

[0090] If the usage requirement indicates synchronization between threads in a thread block or cross-thread usage, the intermediate result is stored in the shared memory;

[0091] If the usage requirement indicates single-thread usage, the intermediate result is stored in the register;

[0092] If the usage requirement indicates synchronization or usage across thread blocks, the intermediate result is stored in the global memory.

[0093] In an embodiment, the GPU is included in a heterogeneous framework, the heterogeneous framework further includes a CPU, and the GPU and the CPU both maintain a plurality of levels of first type pre-computed parameters and second type pre-computed parameters for a target homomorphic operation function, and the CPU and the GPU each maintain the same layer identifier for the same level;

[0094] The obtaining unit 702 is specifically configured to:

[0095] receive target data and a target layer identifier corresponding to a current layer from the CPU;

[0096] The reading unit 704 is specifically configured to:

[0097] read, according to the target layer identifier, the first type pre-computed parameters corresponding to the current layer from the global memory, and read the second type pre-computed parameters corresponding to the current layer from the constant memory.

[0098] In an embodiment, the target homomorphic operation function includes a plurality of target operators, and the GPU maintains a plurality of implementation modules corresponding to the plurality of target operators respectively;

[0099] The execution unit 706 is specifically configured to:

[0100] perform current layer processing on the target data by using each target implementation module pre-selected for the plurality of target operators; wherein the target implementation module corresponding to any target operator is obtained based on a current hardware environment and a pre-configured modulus bit width.

[0101] In an embodiment, the plurality of target operators include at least one of the following: a modulo operation operator, a number theory transform (NTT) operator, a base conversion operator, and a Galois operator, etc.

[0102] In an embodiment, the GPU is initialized with a flow pool, and the target homomorphic operation function includes a number theory transform (NTT) operator;

[0103] The execution unit 706 includes:

[0104] The splitting submodule 7062 is configured to split the target data into a plurality of independent computing tasks.

[0105] The allocating submodule 7064 is configured to allocate each independent computing task to a stream applied from the stream pool, so as to perform the NTT transformation on each independent computing task in parallel by using multi-threading.

[0106] In one embodiment, the GPU is initialized with a random number pool, and the target homomorphic operation function is an encryption function or a decryption function.

[0107] The execution unit 706 is specifically configured to:

[0108] read a certain number of random numbers from the random number pool, perform the current layer processing on the target data based on the read random numbers, and the first type of pre-computed parameters and the second type of pre-computed parameters.

[0109] In one embodiment, the apparatus further includes a determining unit 710 and a sending unit 712.

[0110] The obtaining unit 702 is further configured to obtain a final result corresponding to the target homomorphic operation function.

[0111] The determining unit 710 is configured to determine the number of loss layers as the modulus loss number corresponding to the target homomorphic operation function, and determine the update layer according to the difference between the current layer and the number of loss layers.

[0112] The sending unit 712 is configured to provide the layer identifier corresponding to the update layer and the final result to the CPU, so that the CPU determines the operation result of the hierarchical homomorphic encryption operation.

[0113] The functions of each functional module of the apparatuses in the above embodiments of the present specification can be realized by each step of the above method embodiments, and therefore, the specific working process of the apparatuses provided in an embodiment of the present specification will not be repeated here.

[0114] The apparatus for performing hierarchical homomorphic encryption operation provided in an embodiment of the present specification can improve the efficiency of the hierarchical homomorphic encryption operation.

[0115] According to another aspect, an embodiment also provides a computer readable storage medium having a computer program stored thereon, which, when executed in a computer, causes the computer to perform the method described in combination with FIG. 6.

[0116] According to another aspect, an embodiment also provides a computing device including a memory and a processor, the memory having executable code stored therein, and the processor implementing the method described in combination with FIG. 6 when executing the executable code.

[0117] The various embodiments in the specification are described in progressive manner, and the same or similar parts among the various embodiments can be referred to each other. Each embodiment focuses on the difference from other embodiments. In particular, the medium or device embodiments are described simply because they are substantially similar to the method embodiments, and the relevant parts can be referred to the description of the method embodiments.

[0118] The above describes specific embodiments of the present specification. Other embodiments are within the scope of the appended claims. In some cases, the acts or steps recited in the claims can be performed in a different order than the order described in the embodiments and still achieve the desired result. In addition, the processes depicted in the figures do not necessarily require the particular order shown or sequential order in order to achieve the desired results. In some implementations, multitasking and parallel processing can be advantageous or possible.

[0119] The above describes specific embodiments of the present specification. Other embodiments are within the scope of the appended claims. In some cases, the acts or steps recited in the claims can be performed in a different order than the order described in the embodiments and still achieve the desired result. In addition, the processes depicted in the figures do not necessarily require the particular order shown or sequential order in order to achieve the desired results. In some implementations, multitasking and parallel processing can be advantageous or possible.

[0119] The above describes specific embodiments of the present specification. Other embodiments are within the scope of the appended claims. In some cases, the acts or steps recited in the claims can be performed in a different order than the order described in the embodiments and still achieve the desired result. In addition, the processes depicted in the figures do not necessarily require the particular order shown or sequential order in order to achieve the desired results. In some implementations, multitasking and parallel processing can be advantageous or possible.

Claims

1. A method for performing a hierarchical homomorphic encryption operation, performed by a graphics processing unit (GPU), wherein the GPU has multiple storage structures, the multiple storage structures comprising at least: Global memory and constant memory, the method comprising: Obtain target data to be processed by the target homomorphic operation function at the current layer; Reading first-category pre-calculated parameters corresponding to the current layer from the global memory, and reading second-category pre-calculated parameters corresponding to the current layer from the constant memory, wherein the second-category pre-calculated parameters are used by multiple threads and the amount of data is less than a predetermined threshold; Based on at least the first type of pre-calculation parameters and the second type of pre-calculation parameters, performing current layer processing on the target data to obtain an intermediate result; According to the usage requirements of the intermediate results between threads, the intermediate results are stored in a corresponding storage structure among the multiple storage structures.

2. The method according to claim 1, wherein The plurality of storage structures further comprises: a shared memory and registers; Storing the intermediate result in a corresponding storage structure among the multiple storage structures includes: If the usage requirement indicates synchronization between threads in a thread block or cross-thread usage, storing the intermediate result in the shared memory; If the usage requirement indicates usage within a single thread, storing the intermediate result in the register; If the usage requirement indicates synchronization or usage across thread blocks, the intermediate result is stored in the global memory.

3. The method according to claim 1, wherein The GPU is included in a heterogeneous framework, which also includes a CPU. The GPU and the CPU both maintain multiple levels of first-class pre-calculation parameters and second-class pre-calculation parameters for the target homomorphic operation function, and the CPU and the GPU each maintain the same layer identifier for the same layer. The obtaining of target data to be processed in the current layer using the target homomorphic operation function includes: receiving the target data and a target layer identifier corresponding to the current layer from the CPU; The step of reading the first type of pre-calculated parameters corresponding to the current layer from the global memory and reading the second type of pre-calculated parameters corresponding to the current layer from the constant memory includes: According to the target layer identifier, first-type pre-calculation parameters corresponding to the current layer are read from the global memory, and second-type pre-calculation parameters corresponding to the current layer are read from the constant memory.

4. The method according to claim 1, wherein The target homomorphic operation function includes a plurality of target operators; the GPU maintains a plurality of implementation modules corresponding to each of the plurality of target operators; The performing current layer processing on the target data includes: The current layer processing is performed on the target data using the target implementation modules pre-selected for the target operators; the target implementation module corresponding to any target operator is selected based on the current hardware environment and the pre-configured modulus bit width.

5. The method according to claim 4, wherein The plurality of target operators include at least one of the following: a modular operation operator, a number theoretic transformation (NTT) operator, a basis conversion operator, and a Galois operator.

6. The method according to claim 1, wherein A stream pool is initialized in the GPU; The target homomorphic operation function includes: a number theory transformation NTT operator; The performing current layer processing on the target data includes: dividing the target data into a plurality of independent computing tasks; Each independent computing task is assigned to a certain stream requested from the stream pool, so as to perform NTT transformation on each independent computing task in parallel by utilizing multiple threads.

7. The method according to claim 1, wherein A random number pool is initialized in the GPU; The target homomorphic operation function is an encryption function or a decryption function; The performing current layer processing on the target data includes: A certain number of random numbers are read from the random number pool, and current layer processing is performed on the target data based on the random numbers, the first type of pre-calculation parameters, and the second type of pre-calculation parameters.

8. The method according to claim 1, further comprising: Obtaining a final result corresponding to the target homomorphic operation function; Taking the number of modulus losses corresponding to the target homomorphic operation function as the number of loss layers, and determining the update layer according to the difference between the current layer and the number of loss layers; The layer identifier corresponding to the updated layer and the final result are provided to the CPU, so that the CPU determines the result of the hierarchical homomorphic encryption operation.

9. A device for performing hierarchical homomorphic encryption operations, provided on a graphics processing unit (GPU), wherein the GPU has multiple storage structures, the multiple storage structures comprising at least: Global memory and constant memory, the device comprises: An acquisition unit, configured to acquire target data to be processed in the current layer using a target homomorphic operation function; a reading unit, configured to read first-category pre-calculated parameters corresponding to the current layer from the global memory, and read second-category pre-calculated parameters corresponding to the current layer from the constant memory, wherein the second-category pre-calculated parameters are used by multiple threads and the amount of data is less than a predetermined threshold; An execution unit, configured to perform current layer processing on the target data based on at least the first type of pre-calculation parameters and the second type of pre-calculation parameters to obtain an intermediate result; The storage unit is used to store the intermediate result in a corresponding storage structure among the multiple storage structures according to the usage requirements of the intermediate result between threads.

10. The device according to claim 9, wherein The plurality of storage structures further comprises: a shared memory and registers; The storage unit is specifically used for: If the usage requirement indicates synchronization between threads in a thread block or cross-thread usage, storing the intermediate result in the shared memory; If the usage requirement indicates usage within a single thread, storing the intermediate result in the register; If the usage requirement indicates synchronization or usage across thread blocks, the intermediate result is stored in the global memory.

11. The device according to claim 9, wherein The GPU is included in a heterogeneous framework, which also includes a CPU. The GPU and the CPU both maintain multiple levels of first-class pre-calculation parameters and second-class pre-calculation parameters for the target homomorphic operation function, and the CPU and the GPU each maintain the same layer identifier for the same layer. The acquisition unit is specifically configured to: receiving the target data and a target layer identifier corresponding to the current layer from the CPU; The reading unit is specifically used for: According to the target layer identifier, first-type pre-calculation parameters corresponding to the current layer are read from the global memory, and second-type pre-calculation parameters corresponding to the current layer are read from the constant memory.

12. The device according to claim 9, wherein The target homomorphic operation function includes a plurality of target operators; the GPU maintains a plurality of implementation modules corresponding to each of the plurality of target operators; The execution unit is specifically used for: The current layer processing is performed on the target data using the target implementation modules pre-selected for the target operators; the target implementation module corresponding to any target operator is selected based on the current hardware environment and the pre-configured modulus bit width.

13. The device according to claim 12, wherein The plurality of target operators include at least one of the following: a modular operation operator, a number theoretic transformation (NTT) operator, a basis conversion operator, and a Galois operator.

14. The device according to claim 9, wherein A stream pool is initialized in the GPU; The target homomorphic operation function includes: a number theory transformation NTT operator; The execution unit includes: A splitting submodule, used for dividing the target data into several independent computing tasks; The allocation submodule is used to allocate each independent computing task to a certain stream requested from the stream pool, so as to perform NTT transformation on each independent computing task in parallel by using multiple threads.

15. The device according to claim 9, wherein A random number pool is initialized in the GPU; the target homomorphic operation function is an encryption function or a decryption function; The execution unit is specifically used for: A certain number of random numbers are read from the random number pool, and current layer processing is performed on the target data based on the random numbers, the first type of pre-calculation parameters, and the second type of pre-calculation parameters.

16. The apparatus according to claim 9, further comprising: Determine unit and send unit; The acquisition unit is further configured to acquire a final result corresponding to the target homomorphic operation function; The determining unit is configured to use the number of modulus losses corresponding to the target homomorphic operation function as the number of loss layers, and determine the update layer according to the difference between the current layer and the number of loss layers; The sending unit is used to provide the layer identifier corresponding to the update layer and the final result to the CPU, so that the CPU determines the operation result of the hierarchical homomorphic encryption operation.

17. A computer-readable storage medium having a computer program stored thereon, wherein: When the computer program is executed in a computer, the computer is caused to execute the method according to any one of claims 1 to 8.

18. A computing device comprising a memory and a processor, wherein: The memory stores executable code, and when the processor executes the executable code, the method according to any one of claims 1 to 8 is implemented.

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