Semiconductor device, electronic device, ph sensor, biosensor, and method for manufacturing semiconductor device

Abstract

Provided is a semiconductor device which includes a bottom-gate-type transistor provided on a substrate. The transistor includes: a gate electrode; an oxide semiconductor layer that is located on the gate electrode with a gate insulating layer interposed therebetween; an etching stop layer that is formed on the oxide semiconductor layer in contact with the oxide semiconductor layer and contains a cycloolefin polymer; and a source electrode and a drain electrode that are formed on the etching stop layer in contact with the etching stop layer.

Description

Semiconductor device, electronic device, pH sensor, biosensor, and method for manufacturing semiconductor device

[0001] The present invention relates to a semiconductor device, an electronic device, a pH sensor, a biosensor, and a method for manufacturing a semiconductor device.

[0002] Patent Document 1 discloses a thin film transistor having an Etching Stop Layer (ESL) protective film that prevents damage to an oxide semiconductor film when an electrode is formed.

[0003] Japanese Patent Application Laid-Open No. 2020-194945

[0004] A first aspect of the present invention is a semiconductor device including a bottom-gate transistor provided on a substrate, the transistor including a gate electrode, an oxide semiconductor layer located above the gate electrode with a gate insulating layer interposed therebetween, an etching stop layer containing a cycloolefin polymer formed on and in contact with the oxide semiconductor layer, and a source electrode and a drain electrode formed on and in contact with the etching stop layer.

[0005] Another aspect of the present invention is an electronic device including the semiconductor device described above.

[0006] Another aspect of the present invention is a pH sensor including a semiconductor device, the semiconductor device including: an oxide semiconductor layer; an etching stop layer formed on and in contact with the oxide semiconductor layer and containing a cycloolefin polymer; a first electrode and a second electrode formed on and in contact with the etching stop layer; and a reference electrode.

[0007] Another aspect of the present invention is a biosensor including a semiconductor device, the semiconductor device including: a gate electrode; an oxide semiconductor layer located on the gate electrode via a gate insulating layer; an etching stop layer containing a cycloolefin polymer formed on and in contact with the oxide semiconductor layer; and a source electrode and a drain electrode formed on and in contact with the etching stop layer.

[0008] Another aspect of the present invention is a method for manufacturing a semiconductor device, comprising the steps of forming a gate electrode on a substrate, forming a gate insulating layer on the gate electrode, forming an oxide semiconductor layer on the gate insulating layer, forming an insulating layer containing a cycloolefin polymer on the oxide semiconductor layer, patterning the insulating layer to form an etching stop layer, and forming a source electrode and a drain electrode on the oxide semiconductor layer and the etching stop layer.

[0009] FIG. 1 is a schematic diagram showing an example of a semiconductor device according to a first embodiment; FIG. 2 is a schematic diagram of a pH sensor including the semiconductor device according to the first embodiment; FIG. 3 shows the characteristics of semiconductor devices obtained in Example 1 and Comparative Examples 1 to 3; FIG. 4 shows a graph representing the measurement results of devices obtained in Examples 3 to 5; FIG. 5 is a schematic diagram showing an example of a semiconductor device according to a second embodiment; FIG. 6 shows a graph representing the measurement results of semiconductor devices obtained in Examples 6 and 7; and FIG. 7 shows a graph representing the measurement results of semiconductor devices obtained in Examples 8 to 10.

[0010] An embodiment of the present invention (hereinafter referred to as "the present embodiment") will be described below. The present embodiment is an example for explaining the present invention, and is not intended to limit the present invention to the following content.

[0011] In the drawings, the same elements are denoted by the same reference numerals, and redundant explanations will be omitted. Furthermore, unless otherwise specified, the positional relationships, such as up, down, left, and right, are based on the positional relationships shown in the drawings. Furthermore, the dimensional ratios of the drawings are not limited to those shown in the drawings.

[0012] Furthermore, terms with "approximately" attached indicate the meaning of the term excluding "approximately" within the scope of common technical knowledge of a person skilled in the art, and also include the meaning itself excluding "approximately". The same is true vice versa. For example, the term "circle" does not include "approximately" but naturally includes the meaning of "approximately circle" as long as it does not contradict the gist of the invention. Furthermore, the "cross section" in "cross-sectional view" or "cross-sectional view" refers to a cross section perpendicular to a horizontal plane.

[0013] [First Embodiment] <Configuration of Semiconductor Device 1> Fig. 1 is a schematic diagram showing an example of a semiconductor device 1 according to a first embodiment. Fig. 1 also shows an example of a cross section of the semiconductor device 1. The semiconductor device 1 has a bottom-gate top-contact (BGTC) transistor provided on a substrate. The transistor has a substrate 11, a gate electrode 12, a gate insulating layer 13, an oxide semiconductor layer 14, an insulating layer 15, a source electrode 16, and a drain electrode 17.

[0014] The material of the substrate 11 is not particularly limited, and known materials can be used. Specific examples include glass, resin, silicon, metal, alloy, and foils of these materials. Examples of resins that can be used include polyacrylate, polycarbonate, polyurethane, polystyrene, cellulose polymer, polyolefin, polyamide, polyimide, polyester, polyphenylene, polyethylene, polyethylene terephthalate, polyethylene naphthalate, polypropylene, ethylene-vinyl copolymer, polyvinyl chloride, cycloolefin polymer, and triacetyl cellulose.

[0015] If the substrate 11 is a flexible resin film substrate (sometimes called a "sheet substrate"), a roll-to-roll method or a roll-to-sheet method can be adopted, in which a film is continuously formed in a roll shape, which is expected to improve the efficiency and simplification of the manufacturing process and the yield.

[0016] The roll-to-roll method refers to a method in which a roll-shaped film substrate is unwound, a film is continuously formed on the unwound film substrate, and the unwound film substrate is then wound up into a roll again. The roll-to-sheet method refers to a method in which a roll-shaped film substrate is unwound, a film is continuously formed on the unwound film substrate, and the unwound film is then cut into sheets. When using a flexible substrate 11 compatible with the roll-to-roll method or the roll-to-sheet method, the thickness and rigidity (Young's modulus) of the substrate 11 may be within a range that prevents buckling and irreversible wrinkles from occurring in the substrate 11 when the substrate 11 passes through a transport path such as an exposure device.

[0017] The gate insulating layer 13 is not particularly limited, and known materials can be used. Specific examples include SiO ２ , Si ３ N ４ , SiON, Al ２ O ３ , Ta ２ O ５ , HfO ２ Inorganic materials such as those mentioned above, or organic materials such as photocurable resins and thermosetting resins can be used.

[0018] The oxide semiconductor layer 14 contains In, Ga, and Zn, or contains In, Ga, Zn, and Sn. The oxide semiconductor layer 14 is located on the gate electrode 12 via the gate insulating layer 13. The gate insulating layer 13 preferably has a thickness of less than 600 nm, more preferably less than 400 nm, and even more preferably less than 200 nm. The oxide semiconductor layer 14 preferably has a thickness of less than 50 nm, more preferably less than 30 nm, and even more preferably less than 20 nm.

[0019] The insulating layer 15 is formed on and in contact with the oxide semiconductor layer 14 to protect the oxide semiconductor layer 14. The insulating layer 15 contains a cycloolefin polymer. In this embodiment, ZEOCOAT (registered trademark) is used for the insulating layer 15. After being patterned, the insulating layer 15 becomes an etching stop layer 15a, a first insulating layer 15b, and a second insulating layer 15c.

[0020] 1, the first insulating layer 15b and the second insulating layer 15c are formed so as to cover both end portions of the oxide semiconductor layer 14 in the channel length direction of the semiconductor device 1. Although not shown in FIG. 1, both end portions of the oxide semiconductor layer 14 in the channel width direction of the semiconductor device 1 may be formed so as to be covered with the etching stop layer 15a, the first insulating layer 15b, and the second insulating layer 15c. As a result, the edges of the oxide semiconductor layer 14 are covered with the etching stop layer 15a, the first insulating layer 15b, and the second insulating layer 15c.

[0021] The etching stop layer 15a, the first insulating layer 15b, and the second insulating layer 15c may be separated from each other in a plan view, or may be partially connected to each other.

[0022] There are no limitations on the materials for the gate electrode 12, the source electrode 16, and the drain electrode 17, and known materials can be used for these electrodes. For example, Mo, W, Al, Cu, Au, Ni, a Cu—Al alloy, an Al—Si alloy, an Al—Nd alloy, a Mo—W alloy, or a Ni—P alloy can be used for the gate electrode 12, the source electrode 16, and the drain electrode 17.

[0023] <Method for Manufacturing Semiconductor Device 1> A substrate 11 is prepared, and a gate electrode 12 is formed on the substrate 11. There are no particular limitations on the method for forming the gate electrode 12, and any suitable method can be adopted. For example, a metal film made of Mo, W, Al, Cu, Au, Ni, a Cu-Al alloy, an Al-Si alloy, an Al-Nd alloy, a Mo-W alloy, a Ni-P alloy, or the like is formed on the substrate 11, and the metal film is exposed to light in a predetermined pattern, developed, and etched to obtain a gate electrode 12 having a desired shape.

[0024] Next, a gate insulating layer 13 is formed on the substrate 11 and the gate electrode 12. The method for forming the gate insulating layer 13 is not particularly limited, and a suitable method can be adopted as appropriate, taking into consideration the materials of the substrate 11 and the gate electrode 12. For example, the gate insulating layer 13 can be formed by cathode-coupled CVD (chemical vapor deposition), which applies high frequency to the lower electrode side.

[0025] When the gate insulating layer 13 is formed by the anode coupling CVD method, in which a high frequency is applied to the upper electrode side, there is a disadvantage that a high-quality insulating film cannot be obtained unless the substrate 11 is actively heated. On the other hand, when forming a film by the cathode coupling CVD method, the ion energy due to the self-bias is large, so film formation can be performed at a lower temperature than by the anode coupling CVD method. Therefore, particularly when a resin is used for the substrate 11, it is preferable to form the gate insulating layer 13 by the cathode coupling CVD method, because film formation can be performed at a temperature below the softening point.

[0026] Next, the oxide semiconductor layer 14 is formed on and in contact with the gate insulating layer 13. The method for forming the oxide semiconductor layer 14 is not particularly limited, and a known method can be used. For example, an oxide semiconductor film is formed on the gate insulating layer 13 by sputtering. The sputtering may be performed by simultaneous sputtering using one type of material as a target, or by co-sputtering using multiple types of materials as targets.

[0027] From the viewpoint of field-effect mobility and threshold voltage, the oxide semiconductor film is preferably formed at a temperature of 100° C. to 130° C. The oxide semiconductor film is patterned into a desired shape to form the oxide semiconductor layer 14. For example, the oxide semiconductor film is exposed to light in a predetermined pattern, developed, and etched to form the oxide semiconductor layer 14 in the desired shape.

[0028] Next, an insulating film is formed so as to be in contact with the gate insulating layer 13 and the oxide semiconductor layer 14. For example, the insulating film is formed by applying a substance containing a non-photosensitive cycloolefin polymer onto the gate insulating layer 13 and the oxide semiconductor layer 14 by spin coating, and then baking the applied substance in a baking furnace. Baking is preferably performed at 200°C or less, more preferably 170°C or less, and even more preferably 150°C or less. Thereafter, a resist is applied onto the insulating film, and the insulating film is partially exposed and developed to pattern the insulating film into a desired shape. The resist is then peeled off by dry etching. As a result, a contact hole is formed in the insulating layer 15, exposing a portion of the oxide semiconductor layer 14.

[0029] As another example, a substance containing a photosensitive cycloolefin polymer is applied by spin coating onto the gate insulating layer 13 and the oxide semiconductor layer 14, dried, and then partially exposed to light and developed to form a desired pattern. The resulting material is then baked in a baking furnace to form the insulating layer 15. As with the case of using a non-photosensitive cycloolefin polymer, baking is preferably performed at 200° C. or lower, more preferably 170° C. or lower, and even more preferably 150° C. or lower.

[0030] The insulating layer 15 after patterning, which is formed on a portion other than the end of the oxide semiconductor layer 14 and which prevents damage to the oxide semiconductor layer 14 when forming an electrode, is called the etching stop layer 15a, the insulating layer 15 formed in contact with one end of the oxide semiconductor layer 14 is called the first insulating layer 15b, and the insulating layer 15 formed in contact with the other end of the oxide semiconductor layer 14 is called the second insulating layer 15c. The etching stop layer 15a, the first insulating layer 15b, and the second insulating layer 15c all contain a cycloolefin polymer. Additionally, the etching stop layer 15a, the first insulating layer 15b, and the second insulating layer 15c may be partially connected or separated from each other in a plan view.

[0031] Next, the source electrode 16 and the drain electrode 17 are formed on the oxide semiconductor layer 14 and the etching stop layer 15a. Specifically, the source electrode 16 and the drain electrode 17 are formed so as to be in contact with the part of the oxide semiconductor layer 14 exposed from the contact hole. The source electrode 16 and the drain electrode 17 can be formed by a known method, for example, by forming a conductive layer by sputtering and then etching it into a predetermined shape.

[0032] In general, etching using acid is performed when forming the source electrode 16 and the drain electrode 17. The provision of the etching stop layer 15a prevents damage to the oxide semiconductor layer 14 when etching the source electrode 16 and the drain electrode 17. Additionally, when forming the etching stop layer 15a, it is necessary to consider the effect on the oxide semiconductor layer 14. For example, when the etching stop layer 15a is formed using a plasma CVD method as in the past, the substrate temperature during film formation generally reaches 200°C or higher, which may cause damage to the substrate 11 if a resin is used for the substrate 11. Furthermore, when the etching stop layer 15a is formed using a plasma CVD method, the oxide semiconductor layer 14 itself may also be damaged.

[0033] In this embodiment, by forming the etching stop layer 15a by a wet process using a cycloolefin polymer, it is possible to prevent damage to the substrate 11 and the oxide semiconductor layer 14 during the manufacture of the semiconductor device 1. Furthermore, since the etching stop layer 15a can be formed at a low temperature of 150°C or less, the semiconductor device 1 can be manufactured at a temperature below the softening point of the substrate 11. Furthermore, by forming the gate insulating layer 13 by the cathode coupling CVD method, it is possible to manufacture the semiconductor device 1 at a temperature below the softening point of the substrate 11.

[0034] <Characteristics of the semiconductor device 1> The semiconductor device 1 obtained by this manufacturing method has a field effect mobility of 2 cm ２ / V·s or more, and ２ / V·s or more is more preferable, ２ In addition, in the semiconductor device 1 obtained by the present manufacturing method, the threshold voltage shift of the transistor is preferably 0.8 V or less, more preferably 0.5 V or less, and further preferably 0.3 V or less.

[0035] 2 is a schematic diagram of a pH sensor 2 including the semiconductor device according to the first embodiment. The pH sensor 2 is, for example, a pH sensor (ion-sensitive field-effect transistor (FET)) using the semiconductor device according to this embodiment. The pH sensor 2 includes a substrate 11, an oxide semiconductor layer 14 provided on the substrate 11, an etching stop layer 15a formed on and in contact with the oxide semiconductor layer 14, a first insulating layer 15b provided on and in contact with one end of the oxide semiconductor layer 14, a second insulating layer 15c provided on and in contact with the other end of the oxide semiconductor layer 14, two Ag electrodes 60, a pool wall 70 made of silicone rubber, and a reference electrode 80 provided within the pool wall 70.

[0036] Similar to the semiconductor device 1 described above, the etching stop layer 15a, the first insulating layer 15b, and the second insulating layer 15c contain a cycloolefin polymer and are formed on and in contact with the oxide semiconductor layer 14. Each of the Ag electrodes 60 is formed on and in contact with the etching stop layer 15a and is in contact with the oxide semiconductor layer 14 via a contact hole.

[0037] The solution S to be measured (for example, hydrochloric acid in the case of an acidic solution, or sodium hydroxide solution in the case of an alkaline solution) is filled into a pool formed by a pool wall 70, and the potential difference with the reference electrode 80 is measured. Since the pH of the solution S depends on the amount of protons in the solution, the measurement principle of the pH sensor 2 is to electrically measure the amount of protons in the solution and calculate the pH value based on the measured amount of protons.

[0038] The semiconductor device 1 according to this embodiment can be provided with high stability against strong acids and strong bases, and therefore the pH sensor 2 using this semiconductor device exhibits high stability over a wide pH range, such as pH 1 to 14, and can perform rapid and accurate measurements even when the target sample is a strong acid or base.

[0039] For configurations common to the semiconductor device 1 of the first embodiment, the description of the first embodiment is to be referred to.

[0040] <Biosensor> Although not shown, the semiconductor device 1 according to this embodiment can also be used as a biosensor (sometimes called a biosensor chip). A biosensor is a chemical sensor that utilizes a molecular recognition mechanism of biological origin, and is used as a chemical recognition element for pH changes, oxidation-reduction reactions, etc. in a living body.

[0041] In this regard, the semiconductor device 1 according to this embodiment has high stability over a wide pH range, and therefore can be used as a biosensor that can accurately sense even when the measurement target is strongly acidic or strongly basic. For example, a specific antibody can be modified on the semiconductor surface, and a biosensor can be used that measures the amount of protons when a specific detection target such as DNA is adsorbed onto the surface.

[0042] The semiconductor device 1 according to this embodiment can be used in other electronic devices.

[0043] Examples Hereinafter, examples of the first embodiment will be described, but the present invention is not limited to the following examples in any way.

[0044] <Examples of the Configuration of the Insulating Layer 15> <Example 1> Although not shown, a semiconductor device 1 was fabricated in which the gate electrode 12 in FIG. 1 was not present, and the Si substrate 11 also served as the gate electrode. The Si substrate 11 was used as the substrate also serving as the gate electrode. A SiO 2 film was formed on the substrate 11 as the gate insulating layer 13. ２ A cathode-coupled plasma CVD method was used to form the gate insulating layer 13. Next, a thin film containing In, Ga, and Zn was formed as the oxide semiconductor layer 14 by sputtering.

[0045] Next, an insulating film was formed so as to be in contact with the gate insulating layer 13 and the oxide semiconductor layer 14. More specifically, an insulating film was formed on the upper surfaces of the gate insulating layer 13 and the oxide semiconductor layer 14 by spin coating using a substance containing a non-photosensitive cycloolefin polymer (Zeon Corporation's "ZEOCOAT ES2110-10"), and then baked in an air atmosphere at a temperature of 150°C for 3 hours. After baking, the insulating film was patterned using a resist mask provided on the insulating film. Then, dry etching was performed, and the resist mask was peeled off. As a result, contact holes were formed that exposed parts of the insulating layer 15 and the oxide semiconductor layer 14.

[0046] Next, a metal layer was formed on the oxide semiconductor layer 14 and the etching stop layer 15a, and then etched to form two electrodes. A laminated film made of Mo and AlNd was used for the metal layer, and an etching solution (KSMF-100, manufactured by Kanto Chemical) was used for etching. As a result, a source electrode 16 and a drain electrode 17 were formed.

[0047] Comparative Example 1 Using a substance containing siloxane (SL-PT030 manufactured by Toray Industries, Inc.), an insulating layer 15 was formed by spin coating on the top surfaces of the gate insulating layer 13 and the oxide semiconductor layer 14. Except for the above points, the comparative example was the same as Example 1.

[0048] Comparative Example 2 Using a substance containing siloxane (ILLUMIKA R2001-3 manufactured by Kaneka Corporation), an insulating layer 15 was formed by spin coating on the top surfaces of the gate insulating layer 13 and the oxide semiconductor layer 14. Except for the above points, the comparative example was the same as Example 1.

[0049] Comparative Example 3 An insulating layer 15 was formed by spin coating on the top surfaces of the gate insulating layer 13 and the oxide semiconductor layer 14 using a substance containing siloxane (AZ LExp. S10-002 manufactured by Merck). Except for the above points, the comparative example was the same as Example 1.

[0050] FIG. 3 shows the measurement results of the Vg-Id curves of the semiconductor devices 1 obtained in Example 1 and Comparative Examples 1 to 3. Table 1 shows the mobility of the semiconductor devices fabricated in Example 1 and Comparative Examples 1 to 3, the threshold voltage Vth (forward direction: Vg = -10 to +20 V) when Vg was swept from -10 V to 20 V, the S value (SS), the threshold voltage Vth rev (reverse direction: Vg = +20 to -10 V) when Vg was swept from 20 V to -10 V, and the threshold voltage shift (ΔVth), which is the fluctuation range of the threshold voltage Vth and the threshold voltage Vth rev. The Vg-Id curves in FIG. 3 are the measurement results when Vds = 10 V (Vds source-drain voltage) and W / L = 100 μm / 20 μm (W: channel width, L: channel length). The vertical axes of FIGS. 3, 4, 6, and 7 represent the values ​​1. The notation En is 1 x 10 ｎ For example, 1. E-12 = 1 x 10 －１２ is.

[0051]

[0052] <Evaluation> It was confirmed that the semiconductor devices 1 according to Comparative Examples 1 to 3 are not preferable because they have a large ΔVth (threshold voltage shift) which is the fluctuation range between Vth and Vth rev, compared to the semiconductor device 1 according to Example 1.

[0053] <Example Regarding Boundary Portion Between Oxide Semiconductor Layer 14 and Etching Stop Layer 15a>

[0054] Example 2 After fabricating the semiconductor device 1 in the same manner as in Example 1, the film thickness of the etching stop layer 15a was measured as shown in the table below.

[0055] Comparative Example 4 As in Comparative Example 1, an insulating film was applied to the upper surfaces of the gate insulating layer 13 and the oxide semiconductor layer 14 by spin coating using a substance containing siloxane (SL-PT030 manufactured by Toray Industries, Inc.), and then baked by heating at 150°C for 3 hours. Then, an insulating layer 15 and contact holes were formed using a resist mask. Then, dry etching was performed, and the resist mask was peeled off. Next, a source electrode 16 and a drain electrode 17 were formed. Then, the film thickness of the etching stop layer 15a was measured as shown in the table below.

[0056] Comparative Example 5 Using a substance containing siloxane (SL-N5500 manufactured by Toray Industries, Inc.), an insulating layer 15 was formed on the upper surfaces of the gate insulating layer 13 and the oxide semiconductor layer 14 by spin coating. Except for the above points, the process was the same as in Example 1. Thereafter, the film thickness of the etching stop layer 15a was measured as shown in the table below.

[0057] Comparative Example 6 An insulating layer 15 was formed on the upper surfaces of the gate insulating layer 13 and the oxide semiconductor layer 14 by spin coating using a substance containing acrylic (NS-A2511 manufactured by Toray Industries, Inc.). Except for the above, the experiment was the same as in Example 1. The thickness of the etching stop layer 15a was then measured as shown in the table below. Comparative Example 7 As in Comparative Example 2, an insulating layer 15 was formed on the upper surfaces of the gate insulating layer 13 and the oxide semiconductor layer 14 by spin coating using a substance containing siloxane (ILLUMIKA R2001-3 manufactured by Kaneka Corporation). Except for the above, the experiment was the same as in Example 1. The thickness of the etching stop layer 15a was then measured as shown in the table below. Comparative Example 8 An insulating layer 15 was formed on the upper surfaces of the gate insulating layer 13 and the oxide semiconductor layer 14 by spin coating using a substance containing siloxane (AZ LExp. S05-018 manufactured by Merck). Except for the above, the experiment was the same as in Example 1. Thereafter, the thickness of the etching stop layer 15a was measured as shown in the table below.

[0058] Table 2 shows the film thickness of the etching stop layer 15a in Example 2 and Comparative Examples 4 to 8.

[0059]

[0060] <Evaluation> The semiconductor devices 1 according to Example 2 and Comparative Examples 4 to 8 were visually inspected from above. The top surface of the etching stop layer 15a was visible between the source electrode 16 and the drain electrode 17, and the boundary between the etching stop layer 15a and the oxide semiconductor layer 14 was visible through the etching stop layer 15a. In the semiconductor device 1 according to Example 2, there was no color unevenness in the relevant area, and it was confirmed that the etching stop layer 15a and the oxide semiconductor layer 14 were in close contact over the entire surface. On the other hand, the semiconductor devices 1 according to Comparative Examples 4 to 8 had partial color unevenness, and it was confirmed that damage had occurred at the boundary between the etching stop layer 15a and the oxide semiconductor layer 14 during the processing. Furthermore, it was confirmed that the etching stop layer in Comparative Examples 7 and 8 was thick and had poor processability.

[0061] <Examples of Film Thickness>

[0062] Examples 3 to 5 Semiconductor devices 1 were fabricated in the same manner as in Example 1. As shown in the table below, the thickness of the oxide semiconductor layer 14 in each semiconductor device 1 was varied.

[0063] Table 3 shows the mobility, threshold voltage (Vth) when Vg is swept in the positive direction, S value (SS), threshold voltage (Vth rev) when Vg is swept in the negative direction, and threshold voltage shift (ΔVth), which is the fluctuation range of Vth and Vth rev, of the semiconductor device 1 of Examples 3 to 5. FIG. 4 shows the Vg-Id curves of the semiconductor device 1 obtained in Examples 3 to 5. Note that FIG. 4 shows the measurement results when Vds = 10 V (Vds: voltage between the source and drain) and W / L = 100 μm / 20 μm (W: channel width, L: channel length (distance between the source and drain regions)).

[0064]

[0065] <Evaluation> In all of Examples 3 to 5, the threshold voltage shift ΔVth was 0.3 V or less, which was preferable. Note that when the film thickness of the oxide semiconductor layer 14 was 10 nm or more and 20 nm or less, the field effect mobility was 8 cm ２ / V·s or more, and it was confirmed that more preferable semiconductor characteristics were obtained.

[0066] Second Embodiment A semiconductor device 1 according to a second embodiment will be described. Differences from the semiconductor device 1 according to the first embodiment will be described below. The semiconductor device 1 according to the second embodiment has a passivation layer 18 in contact with the source electrode 16, the drain electrode 17, and the etching stop layer 15a.

[0067] 5 is a schematic diagram showing an example of a semiconductor device 1 according to the second embodiment. The semiconductor device 1 according to the second embodiment includes a substrate 11, a gate electrode 12, a gate insulating layer 13, an oxide semiconductor layer 14, an insulating layer 15 (an etching stop layer 15 a, a first insulating layer 15 b, and a second insulating layer 15 c), a source electrode 16, a drain electrode 17, and a passivation layer 18.

[0068] The passivation layer 18 is formed by using organosilane gas and N ２ The organic silane gas is formed using at least one of hexamethyldisilazane (HMDS), hexamethyldisiloxane (HMDSO), tetraethoxysilane (TEOS), tetramethyldisiloxane (TMDSO), and tetramethylcyclotetrasiloxane (TMCTS). For example, the organic silane gas and N ２ The passivation layer 18 is formed by deposition using a plasma CVD method in an O gas atmosphere. By providing the passivation layer 18, improvements in semiconductor properties such as mobility are expected.

[0069] In the semiconductor device 1 of this embodiment, UV irradiation may be performed after the passivation layer 18 is formed. In this case, the passivation layer 18 is irradiated with organic silane gas and N ２ After forming a film by plasma CVD using O gas, ultraviolet rays (UV) are irradiated from above the substrate 11, and then the entire substrate 11 is annealed. This is expected to improve semiconductor properties such as mobility. The annealing atmosphere after UV irradiation is air atmosphere or nitrogen atmosphere.

[0070] Examples Hereinafter, examples of the second embodiment will be described, but the present invention is not limited to the following examples in any way.

[0071] <Examples 6 and 8> A semiconductor device 1 was fabricated in the same manner as in Example 1. The passivation layer 18 was not formed. The ratio of the channel width W to the channel length L was W / L = 50 μm / 20 μm in Example 6, and W / L = 100 μm / 20 μm in Example 8.

[0072] Examples 7 and 9 A substance containing a cycloolefin polymer (ZEOCOAT ES2110-10 manufactured by Zeon Corporation) was deposited on a semiconductor device 1 fabricated in the same manner as in Example 6, thereby obtaining a passivation layer 18. The ratio of the channel width W to the channel length L was W / L = 50 μm / 20 μm in Example 7, and W / L = 100 μm / 20 μm in Example 10.

[0073] Example 10 A semiconductor device 1 fabricated in the same manner as in Example 6 was treated with hexamethyldisilazane (HMDS, manufactured by Yamanaka Hewtec Co., Ltd.) and N ２ The passivation layer 18 was formed by plasma CVD using O gas. The ratio of the channel width W to the channel length L in Example 10 was W / L=100 μm / 20 μm.

[0074] FIG. 6 shows the Vg-Id curves of the semiconductor devices 1 obtained in Examples 6 and 7 with W / L = 50 μm / 20 μm. FIG. 7 shows the Vg-Id curves of the semiconductor devices 1 obtained in Examples 8 to 10 with W / L = 100 μm / 20 μm. Table 4 shows the W / L ratio, mobility, threshold voltage (Vth) during a positive Vg sweep, S value (SS), threshold voltage (Vthrev) during a negative Vg sweep, and threshold voltage shift (ΔVth) of the semiconductor devices 1 of Examples 6 to 10. FIG. 6 shows the measured values ​​of the semiconductor devices 1 fabricated in Examples 6 to 7 with Vds = 10 V and W / L = 50 μm / 20 μm, while FIG. 7 shows the measured values ​​of the semiconductor devices 1 fabricated in Examples 8 to 10 with Vds = 10 V and W / L = 100 μm / 20 μm.

[0075]

[0076] <Evaluation> In Examples 6 to 10, the field effect mobility was 6 cm ２ / V·s or more, and the threshold voltage shift ΔVth was 0.3 V or less, and it was confirmed that preferable semiconductor characteristics were obtained. ２ / V·s or more, and it was confirmed that more preferable semiconductor properties were obtained.

[0077] Although each embodiment of the present invention has been described above, the present invention is not limited to the above-described exemplary embodiment and includes various modifications. For example, the above-described exemplary embodiment has been described in detail to make the present invention easier to understand, and the present invention is not limited to an embodiment having all of the configurations described herein. Furthermore, it is possible to replace part of the configuration of one exemplary embodiment with the configuration of another exemplary embodiment. It is also possible to add the configuration of another exemplary embodiment to the configuration of one exemplary embodiment. Furthermore, it is also possible to add, delete, or replace part of the configuration of each exemplary embodiment with other configurations.

[0078] REFERENCE SIGNS LIST 1...Semiconductor device, 2...pH sensor, 11...Substrate, 12...Gate electrode, 13...Gate insulating layer, 14...Oxide semiconductor layer, 15...Insulating layer, 15a...Etching stop layer, 15b...First insulating layer, 15c...Second insulating layer, 16...Source electrode, 17...Drain electrode, 18...Passivation layer, 60...Ag electrode, 70...Pool wall, 80...Reference electrode

Claims

1. A semiconductor device comprising: a bottom-gate transistor provided on a substrate, the transistor comprising: a gate electrode; an oxide semiconductor layer located above the gate electrode with a gate insulating layer interposed therebetween; an etching stop layer containing a cycloolefin polymer formed on and in contact with the oxide semiconductor layer; and a source electrode and a drain electrode formed on and in contact with the etching stop layer.

2. A semiconductor device according to claim 1, wherein the substrate is made of resin.

3. A semiconductor device according to claim 1 or 2, comprising: a first insulating layer containing a cycloolefin polymer formed on and in contact with one end of the oxide semiconductor layer; and a second insulating layer containing a cycloolefin polymer formed on and in contact with the other end of the oxide semiconductor layer.

4. A semiconductor device according to any one of claims 1 to 3, wherein the oxide semiconductor layer has a thickness of 10 nm or more and less than 20 nm.

5. A semiconductor device according to any one of claims 1 to 4, wherein the field effect mobility of the transistor is 6 cm ２ / V·s or more.

6. A semiconductor device according to any one of claims 1 to 5, wherein the threshold voltage shift of the transistor is 0.3 V or less.

7. A semiconductor device according to any one of claims 1 to 6, wherein the oxide semiconductor layer contains In, Ga, and Zn, or contains In, Ga, Zn, and Sn.

8. An electronic device comprising the semiconductor device according to any one of claims 1 to 7.

9. A pH sensor including a semiconductor device, the semiconductor device having: an oxide semiconductor layer; an etching stop layer containing a cycloolefin polymer formed on and in contact with the oxide semiconductor layer; a first electrode and a second electrode formed on and in contact with the etching stop layer; and a reference electrode.

10. A biosensor including a semiconductor device, the semiconductor device having: a gate electrode; an oxide semiconductor layer located on the gate electrode via a gate insulating layer; an etching stop layer containing a cycloolefin polymer and formed on and in contact with the oxide semiconductor layer; and a source electrode and a drain electrode formed on and in contact with the etching stop layer.

11. A method for manufacturing a semiconductor device, comprising: forming a gate electrode on a substrate; forming a gate insulating layer on the gate electrode; forming an oxide semiconductor layer on the gate insulating layer; forming an insulating layer containing a cycloolefin polymer on the oxide semiconductor layer; patterning the insulating layer to form an etching stop layer; and forming a source electrode and a drain electrode on the oxide semiconductor layer and the etching stop layer.

12. A method for manufacturing a semiconductor device according to claim 11, wherein in the step of forming the etching stop layer, the insulating layer is patterned to form a first insulating layer in contact with one end of the oxide semiconductor layer and a second insulating layer in contact with the other end of the oxide semiconductor layer.

13. A method for manufacturing a semiconductor device according to claim 11 or 12, wherein the step of forming the etching stop layer is carried out at 150° C. or less.

14. A method for manufacturing a semiconductor device according to any one of claims 11 to 13, wherein in the step of forming the gate insulating layer, the gate insulating layer is formed by a cathode coupling method.

15. A method for manufacturing a semiconductor device according to any one of claims 11 to 14, wherein a passivation layer in contact with the source electrode, the drain electrode, and the etching stop layer is formed by etching with an organic silane gas and N ２ A method for manufacturing a semiconductor device using O gas.

16. A method for manufacturing a semiconductor device according to claim 15, wherein the organosilane gas is hexamethyldisilazane, hexamethyldisiloxane, tetraethoxysilane, tetramethyldisiloxane, or tetramethylcyclotetrasiloxane.

17. A method for manufacturing a semiconductor device according to claim 15 or 16, comprising the step of irradiating the passivation layer with UV light.

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