Printed wiring board

Abstract

This printed wiring board comprises a base film and a laminated portion. The base film has a main surface. The laminated portion is disposed on the main surface. The laminated portion includes a base layer and an electroplated layer. The base layer is in contact with the main surface. The electroplated layer is in contact with the base layer. The Young's modulus of the base layer is 0.5-0.9 times the Young's modulus of the electroplated layer.

Description

printed wiring board

[0001] The present disclosure relates to printed wiring boards.

[0002] International Publication No. 2019 / 208077 (Patent Document 1) discloses a substrate for a printed wiring board including a base film and an electroless plating layer.

[0003] International Publication No. 2019 / 208077

[0004] A printed wiring board according to the present disclosure includes a base film and a laminate portion. The base film has a main surface. The laminate portion is disposed on the main surface. The laminate portion includes an underlayer and an electroplated layer. The underlayer is in contact with the main surface. The electroplated layer is in contact with the underlayer. The Young's modulus of the underlayer is 0.5 to 0.9 times the Young's modulus of the electroplated layer.

[0005] FIG. 1 is a cross-sectional view showing the configuration of a substrate for printed wiring boards according to the first embodiment. FIG. 2 is a flowchart showing a method for manufacturing a substrate for printed wiring boards according to the first embodiment. FIG. 3 is a cross-sectional view showing one step of a method for manufacturing a substrate for printed wiring boards according to the first embodiment. FIG. 4 is a cross-sectional view showing one step of a method for manufacturing a substrate for printed wiring boards according to the first embodiment. FIG. 5 is a cross-sectional view showing a configuration of a modified example of a substrate for printed wiring boards according to the first embodiment. FIG. 6 is a flowchart showing a method for manufacturing a modified example of a substrate for printed wiring boards according to the first embodiment. FIG. 7 is a cross-sectional view showing one step of a method for manufacturing a substrate for printed wiring boards according to the first embodiment. FIG. 8 is a cross-sectional view showing one step of a method for manufacturing a substrate for printed wiring boards according to the first embodiment. FIG. 9 is a schematic configuration diagram of a plating apparatus. FIG. 10 is a cross-sectional view showing one step of a method for manufacturing a substrate for printed wiring boards according to the first embodiment. FIG. 11 is a cross-sectional view showing the configuration of a printed wiring board according to the second embodiment. FIG. 12 is a flowchart showing a method for manufacturing a printed wiring board according to the second embodiment. FIG. 13 is a cross-sectional view showing one step of a method for manufacturing a printed wiring board according to the second embodiment. FIG. 14 is a cross-sectional view showing one step of a method for manufacturing a printed wiring board according to the second embodiment. Fig. 15 is a cross-sectional view showing one step of a method for manufacturing a printed wiring board according to the second embodiment. Fig. 16 is a printed wiring board showing a region for measuring Young's modulus. Fig. 17 is a schematic cross-sectional view of a laminated portion shown in region XVII of Fig. 11. Fig. 18 is a cross-sectional view of a substrate for a printed wiring board showing a region for measuring Young's modulus. Fig. 19 is a plan view of an evaluation TEG (Test Element Group).

[0006] [Problem to be Solved by the Present Disclosure] There is a demand for finer circuits on printed wiring boards. In a semi-additive process suitable for forming finer circuits, a circuit composed of a laminate including an underlayer and an electroplated layer is formed on the surface of a base film on which an underlayer has been formed by undergoing the steps of resist pattern formation, electroplating, resist removal, and underlayer etching. In the step of etching the underlayer, it is difficult to uniformly etch the underlayer and the electroplated layer, which may impair the rectangularity of the circuit.

[0007] An object of the present disclosure is to provide a printed wiring board having a circuit with excellent rectangularity.

[0008] Effect of the Present Disclosure According to the present disclosure, it is possible to provide a printed wiring board having excellent rectangularity.

[0009] [Outline of the embodiment] First, the embodiments of the present disclosure will be listed and described.

[0010] (1) A printed wiring board according to the present disclosure includes a base film and a laminate portion. The base film has a main surface. The laminate portion is disposed on the main surface. The laminate portion includes an underlayer and an electroplated layer. The underlayer is in contact with the main surface. The electroplated layer is in contact with the underlayer. The Young's modulus of the underlayer is 0.5 to 0.9 times the Young's modulus of the electroplated layer.

[0011] (2) In the printed wiring board of (1) above, the Young's modulus of the underlayer may be 0.7 times or less the Young's modulus of the electrolytic plating layer.

[0012] (3) In the printed wiring board of (1) or (2) above, the Young's modulus of the electrolytic plating layer may be 85 GPa or more and 100 GPa or less.

[0013] (4) In the printed wiring board according to any one of (1) to (3), a direction perpendicular to the main surface may be defined as the first direction. A direction perpendicular to the first direction may be defined as the second direction. A direction perpendicular to the first direction and the second direction may be defined as the third direction. The laminated portion may be formed to extend linearly along the second direction. The laminated portion may include adjacent first and second laminated portions. The width of each of the first and second laminated portions may be 15 μm or less. The shortest distance in the third direction from the first laminated portion to the second laminated portion may be 15 μm or less.

[0014] (5) In the printed wiring board of (4), the width of each of the first laminate portion and the second laminate portion may be 10 μm or less, and the shortest distance from the first laminate portion to the second laminate portion in the third direction may be 10 μm or less.

[0015] (6) In the printed wiring board of (4) or (5), the width of each of the first laminated portion and the second laminated portion may be 2 μm or more, and the shortest distance from the first laminated portion to the second laminated portion in the third direction may be 2 μm or more.

[0016] (7) In the printed wiring board according to any one of (1) to (6) above, the height of the laminated portion may be 1 μm or more.

[0017] (8) In the printed wiring board according to any one of (1) to (7), the laminate may have a first surface farthest from the main surface. The Young's modulus of the underlayer may be the Young's modulus of the laminate measured in a first region up to 0.05 μm from the main surface. The Young's modulus of the electroplated layer may be the Young's modulus of the laminate measured in a second region from the center of the laminate to the first surface.

[0018] [Details of the embodiment] The details of the embodiment of the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are designated by the same reference numerals, and redundant description will not be repeated. The substrate for a printed wiring board and the printed wiring board according to the embodiment are referred to as a substrate for a printed wiring board 100 (100a, 100b) and a printed wiring board 200, respectively.

[0019] (Configuration of Substrate for Printed Wiring Board) The configuration of the substrate for printed wiring board 100a will be described below.

[0020] 1 is a cross-sectional view of a substrate 100a for a printed wiring board. As shown in FIG. 1, the substrate 100a for a printed wiring board includes a base film 1 and an underlayer 2.

[0021] The base film 1 has a main surface 1s. The base film 1 is made of a flexible insulating material, such as polyimide.

[0022] The base layer 2 is in contact with the principal surface 1s. The base layer 2 is composed of either a sputtered copper layer or a nano-copper sintered body layer. In the case of a nano-copper sintered body layer, the nano-copper sintered body layer is formed from a plurality of sintered copper particles. Therefore, the nano-copper sintered body layer is porous. The average particle size of the copper particles contained in the nano-copper sintered body layer may be 1 nm or more or 30 nm or more. The average particle size of the copper particles contained in the nano-copper sintered body layer may be 100 nm or less or 500 nm or less. In other words, the copper particles contained in the nano-copper sintered body layer may be nano-copper particles. The average particle size of the copper particles contained in the paste used to form the nano-copper sintered body layer is measured using a particle size distribution measurement device (e.g., a Microtrac particle size distribution meter UPA-150EX manufactured by Nikkiso Co., Ltd.). As described below, an electroless copper plating layer (not shown) may be formed on the principal surface 1s.

[0023] 1 , a direction perpendicular to the principal surface 1s is defined as a first direction X. The underlayer 2 has an underlayer surface 2s. The underlayer surface 2s is the surface of the underlayer 2 opposite to the surface in contact with the principal surface 1s. A distance H in the first direction from the principal surface 1s to the underlayer surface 2s (thickness H of the underlayer 2) may be 1 μm or less or 0.5 μm or less.

[0024] (Method for manufacturing substrate for printed wiring board) A method for manufacturing the substrate for printed wiring board 100a will be described below. Fig. 2 is a flowchart illustrating the method for manufacturing the substrate for printed wiring board 100a. As shown in Fig. 2, the method for manufacturing the substrate for printed wiring board 100a includes a step S1a of preparing a base film 1 and a step S2a of forming an underlayer 2.

[0025] The step S2a of forming the underlayer is performed after the step S1a of preparing the base film 1.

[0026] 3 is a cross-sectional view illustrating step S1a of preparing the base film 1. In step S1a of preparing the base film 1, the base film 1 is prepared as shown in Fig. 3. In step S1a of preparing the base film 1, the underlayer 2 is not disposed on the main surface 1s of the prepared base film 1.

[0027] Before disposing the underlayer 2, the principal surface 1s is subjected to, for example, an alkali treatment and an excimer treatment. If the base film 1 is made of, for example, polyimide, the alkali treatment on the principal surface 1s causes the polyimide to hydrolyze. As a result, carboxyl groups are formed on the principal surface 1s, making the base film 1 hydrophilic. If the principal surface 1s is then copper-metallized by applying a paste or electroless plating, the growth rate of the underlayer 2 increases in step S2a of forming the underlayer 2. If the growth rate of the underlayer 2 increases, the underlayer 2 is formed with a relatively low density. This allows the Young's modulus E1 of the underlayer 2 to be relatively reduced.

[0028] To further enhance the hydrophilicity of the principal surface 1s, the principal surface 1s may be subjected to an excimer treatment after the alkali treatment. Specifically, the principal surface 1s is irradiated with excimer light. The wavelength of the excimer light is, for example, 172 nm. The irradiation time with the excimer light is, for example, 60 seconds or more and 600 seconds or less.

[0029] FIG. 4 is a cross-sectional view illustrating step S2a of forming the underlayer 2. In step S2a of forming the underlayer 2, the underlayer 2 is formed on the main surface 1s as shown in FIG. In this step S2a, first, a paste containing copper particles is applied to the main surface 1s. Second, the solvent contained in the applied paste is dried. Third, the dried paste is fired. As a result, the copper particles contained in the dried paste are sintered to each other, forming the underlayer 2. In this way, sintering the paste containing copper particles creates voids in the underlayer 2, softening the underlayer 2. As a result, the Young's modulus E1 of the underlayer 2 can be reduced.

[0030] When a paste containing copper particles is sintered, the dispersant used to disperse the copper particles in the paste may not be thermally decomposed sufficiently, resulting in the dispersant remaining in the paste. Therefore, the paste containing copper particles is sintered using an IR (Infrared) oven using a far-infrared heater. This facilitates the formation of voids in the nano-copper sintered layer, thereby lowering the Young's modulus E1 of the underlayer 2.

[0031] When sintering the paste containing copper particles using an IR oven, the oxygen concentration may be 150 ppm or less, or may be 50 ppm or less. Furthermore, when sintering the paste containing copper particles using an IR oven, the temperature may be 250° C. or more and 300° C. or less. The time for sintering the paste containing copper particles using an IR oven may be 1 minute or more and 100 minutes or less.

[0032] The material constituting the dispersant may be a polymer material. The polymer material quickly absorbs far-infrared rays and is heated. This allows the dispersant to be efficiently thermally decomposed. This makes it easier for voids to form in the nano-copper sintered body layer, thereby reducing the Young's modulus E1 of the underlayer 2.

[0033] The dispersant disperses the metal particles precipitated in the dispersion medium well. From the viewpoint of preventing deterioration of the sintered body layer, it is desirable to use a dispersant that does not contain sulfur, phosphorus, boron, halogen, or alkali. Examples of such dispersants include amine-based polymer dispersants such as polyethyleneimine and polyvinylpyrrolidone, polycarboxylic acid-based polymer dispersants having carboxylic acid groups in the molecule such as polyacrylic acid and carboxymethyl cellulose, and polymer dispersants having polar groups such as poval (polyvinyl alcohol), styrene-maleic acid copolymer, olefin-maleic acid copolymer, and copolymers having a polyethyleneimine moiety and a polyethylene oxide moiety in one molecule.

[0034] The underlayer 2 may be formed by sputtering or by using a plating apparatus 300 described later.

[0035] After the underlayer 2 is formed using the plating apparatus 300, the underlayer 2 may be annealed. Specifically, in an inert gas atmosphere such as nitrogen, the annealing temperature is raised to a range of 150°C to 250°C and maintained at this annealing temperature for 30 minutes. This promotes recrystallization and softening of the underlayer 2. Thereafter, the annealing temperature is raised to a range of 300°C to 400°C and maintained at this annealing temperature for one hour. This allows the underlayer 2 to be formed with a relatively low density (e.g., including voids), thereby reducing the Young's modulus E1 of the underlayer 2.

[0036] 1 is manufactured. In the printed wiring board substrate 100a manufactured in this manner, when the electrolytic plated layer 3 is formed on the base layer surface 2s, the Young's modulus E1 of the base layer 2 is smaller than the Young's modulus E2 of the electrolytic plated layer 3. Specifically, the Young's modulus E2 of the electrolytic plated layer 3 is, for example, 85 GPa or more and 100 GPa or less. The Young's modulus E1 of the base layer 2 is 0.5 to 0.9 times the Young's modulus E2 of the electrolytic plated layer 3.

[0037] As will be described later, the etching solution used in the semi-additive process is generally a sulfuric acid-hydrogen peroxide etching solution. When etching the laminated portion 20 composed of the electroplated layer 3 and the underlayer 2, if the amount of etching of the laminated portion 20 is excessive, the underlayer 2 may be excessively etched. On the other hand, if the amount of etching of the laminated portion 20 is too small, part of the underlayer 2 in the laminated portion 20 may remain, and the rectangularity of the laminated portion 20 may be deteriorated.

[0038] In the printed wiring board substrate 100a according to the first embodiment, the Young's modulus E1 of the base layer 2 is 0.5 to 0.9 times the Young's modulus E2 of the electrolytic plated layer 3. Therefore, the etching rate of the base layer 2 is greater than the etching rate of the electrolytic plated layer 3. As a result, even if the etching amount of the laminated portion 20 is too small, the laminated portion 20 has excellent rectangularity. In this way, the printed wiring board 200 according to the second embodiment, which will be described later, is obtained.

[0039] The Young's modulus E1 of the underlayer 2 and the Young's modulus E2 of the electroplated layer 3 are measured by nanoindentation measurement. Specifically, as shown in FIG. 18 , for example, when a laminate 20 is formed to include the electroplated layer 3 and the underlayer 2, the electroplated layer 3 contacts the underlayer 2. FIG. 18 is a cross-sectional view of a printed wiring board substrate showing the Young's modulus measurement area. The laminate 20 has a first surface 21s. The first surface 21s is positioned so that the height Ht of the laminate from the main surface 1s to the first surface 21s is 10 μm or more. The printed wiring board substrate 500 having the laminate 20 formed thereon is subjected to cross-sectional processing before measuring the Young's modulus by nanoindentation measurement. For example, argon ion polishing can be used for this cross-sectional processing. Next, the Young's modulus E1 of the underlayer 2 and the Young's modulus E2 of the electroplated layer 3 are measured by nanoindentation measurement.

[0040] 18, the Young's modulus E1 of the base layer 2 may be the Young's modulus of the laminate 20 measured in a first region V1 extending from the principal surface 1s to 0.05 μm. The Young's modulus E2 of the electrolytic plating layer 3 may be the Young's modulus of the laminate 20 in a second region V2 extending from the center c of the laminate 20 to the first surface 21s.

[0041] The Young's modulus E1 of the underlayer 2 may be an average value of Young's moduli measured at three points in the first region V1. The Young's modulus E2 of the electrolytic plating layer 3 may be an average value of Young's moduli measured at three points in the second region V2.

[0042] (Configuration of a Modified Printed Wiring Board Substrate) FIG. 5 is a cross-sectional view of a modified printed wiring board substrate 100a according to embodiment 1. FIG. 5 corresponds to FIG. 1. The printed wiring board substrate 100b shown in FIG. 5 has a configuration similar to that of the printed wiring board substrate 100a shown in FIG. 1, but differs in that the base layer 2 includes an electroless copper plating layer. Specifically, the base layer 2 includes a first base layer 2a and a second base layer 2b. The first base layer 2a is specifically composed of either a sputtered copper layer or a nano-copper sintered body layer. The first base layer 2a has an intermediate base layer surface s. In the first base layer 2a, the intermediate base layer surface s is the surface opposite the main surface 1s. The second base layer 2b is in contact with the first base layer 2a at the intermediate base layer surface s. The second base layer 2b is, for example, a copper layer formed by electroless plating. In this manner, the base layer 2 is formed.

[0043] The distance Ha in the first direction X from the main surface 1s to the intermediate underlayer surface s (thickness Ha of the first underlayer 2a) may be 0.5 μm or less, or 0.1 μm or less.

[0044] The underlayer 2 does not necessarily have to include the first underlayer 2a. Specifically, the underlayer 2 may be composed of only the second underlayer 2b made of an electroless copper plating layer.

[0045] (Method for Manufacturing a Substrate for a Printed Wiring Board) A method for manufacturing the substrate for a printed wiring board 100b will be described below.

[0046] Fig. 6 is a flowchart illustrating a method for manufacturing the substrate 100b for printed wiring boards. Fig. 6 corresponds to Fig. 2. As shown in Fig. 6, the method for manufacturing the substrate 100b for printed wiring boards includes a step S1b of preparing a base film 1, a step S2b of forming a first underlayer 2a, a step S3b of forming a second underlayer 2b, and a step S4b of annealing the substrate 100b for printed wiring boards.

[0047] Step S2b of forming the first underlayer 2a is performed after step S1b of preparing the base film 1. Step S3b of forming the second underlayer 2b is performed after step S2b of forming the first underlayer 2a. Step S4b of annealing the printed wiring board substrate 100b is performed after step S3b of forming the second underlayer 2b.

[0048] 7 is a cross-sectional view illustrating step S1b of preparing a base film 1. In step S1b of preparing a base film 1, the base film 1 is prepared as shown in FIG. The base film 1 prepared in step S1b does not have an underlayer 2 disposed on the main surface 1s. Before disposing the underlayer 2, the main surface 1s is subjected to an alkali treatment and an excimer treatment.

[0049] FIG. 8 is a cross-sectional view illustrating step S2b of forming the first underlayer 2a. In step S2b of forming the first underlayer 2a, as shown in FIG. 8, the first underlayer 2a is formed on the main surface 1s. In this step S2b, first, a paste containing copper particles is applied to the main surface 1s. Second, the solvent contained in the applied paste is dried. Third, the dried paste is fired. As a result, the copper particles contained in the dried paste are sintered to each other, forming the first underlayer 2a. In this way, sintering the paste containing copper particles generates voids in the underlayer 2, and the density of the underlayer 2 is relatively reduced. As a result, the Young's modulus E1 of the underlayer 2 can be reduced.

[0050] When a paste containing copper particles is sintered, the dispersant used to disperse the copper particles in the paste may not be thermally decomposed sufficiently, resulting in the dispersant remaining in the paste. Therefore, the paste containing copper particles is sintered using an IR (Infrared) oven using a far-infrared heater. This facilitates the formation of voids in the nano-copper sintered layer, thereby lowering the Young's modulus E1 of the underlayer 2.

[0051] When sintering the paste containing copper particles using an IR oven, the oxygen concentration may be 150 ppm or less, or may be 50 ppm or less. Furthermore, when sintering the paste containing copper particles using an IR oven, the temperature may be 250° C. or more and 300° C. or less. The time for sintering the paste containing copper particles using an IR oven may be 1 minute or more and 100 minutes or less.

[0052] The material constituting the dispersant may be a polymer material. The polymer material quickly absorbs far-infrared rays and is heated. This allows the dispersant to be efficiently thermally decomposed. This makes it easier for voids to form in the nano-copper sintered body layer, thereby reducing the Young's modulus E1 of the underlayer 2.

[0053] The dispersant disperses the metal particles precipitated in the dispersion medium well. From the viewpoint of preventing deterioration of the sintered body layer, it is desirable to use a dispersant that does not contain sulfur, phosphorus, boron, halogen, or alkali. Examples of such dispersants include amine-based polymer dispersants such as polyethyleneimine and polyvinylpyrrolidone, polycarboxylic acid-based polymer dispersants having carboxylic acid groups in the molecule such as polyacrylic acid and carboxymethyl cellulose, and polymer dispersants having polar groups such as poval (polyvinyl alcohol), styrene-maleic acid copolymer, olefin-maleic acid copolymer, and copolymers having a polyethyleneimine moiety and a polyethylene oxide moiety in one molecule.

[0054] The first underlayer 2a may be formed by sputtering. Note that step S2b of forming the first underlayer 2a does not necessarily have to be performed.

[0055] The step S3b of forming the second underlayer 2b is performed using a plating apparatus 300. Fig. 9 is a schematic diagram of the plating apparatus 300 used in the step S3b of forming the second underlayer 2b. As shown in Fig. 9, the plating apparatus 300 includes a plating treatment tank 310, a plurality of rollers 320, electrode rollers 331 and 332, and a power source 340.

[0056] A plating solution is stored in the plating tank 310. The plating solution contains copper. The plating solution may also contain nickel. An electrode 311 is disposed inside the plating tank 310. The electrode 311 is made of a conductive material. The electrode 311 is made of titanium, for example. The electrode 311 is immersed in the plating solution.

[0057] The rollers 320 are aligned along the transport direction (see the arrow in FIG. 9 ) of the base film 1. The base film 1 is transported along the transport direction by rotating the rollers 320. During the transport process, the base film 1 passes through a plating solution stored in a plating treatment tank 310.

[0058] The electrode rollers 331 and 332 are disposed at positions where they come into contact with the base film 1 before it passes through the plating solution. At least one of the electrode rollers 331 and 332 comes into contact with the first underlayer 2 a. The electrode rollers 331 and 332 are made of, for example, stainless steel.

[0059] The power supply 340 is electrically connected to the electrode 311 and the electrode rollers 331 and 332. More specifically, the positive pole of the power supply 340 is electrically connected to the electrode 311, and the negative pole of the power supply 340 is electrically connected to the electrode rollers 331 and 332.

[0060] Fig. 10 is a cross-sectional view illustrating step S3b of forming the second underlayer 2b. In step S3b of forming the second underlayer 2b, as shown in Fig. 9, a power source 340 applies electricity between the electrode 311 and the electrode rollers 331 and 332. As shown in Fig. 10, driven by the electrical energy generated by this electricity application, the second underlayer 2b is rapidly formed on the surface (intermediate underlayer surface s) of the first underlayer 2a. Thereafter, the electricity between the electrode 311 and the electrode rollers 331 and 332 is stopped.

[0061] Next, step S4b is performed to anneal the printed wiring board substrate 100b. Specifically, after the base layer 2 is formed using the plating apparatus 300, the printed wiring board substrate 100b is annealed. In an inert gas atmosphere such as nitrogen, the annealing temperature is raised to a range of 150°C to 250°C and maintained at this annealing temperature for 30 minutes. This promotes recrystallization and softening of the base layer 2. Thereafter, the annealing temperature is raised to a range of 300°C to 400°C and maintained at this annealing temperature for 1 hour. As a result, the recrystallized base layer 2 is fixed to the base film 1. In this manner, the base layer 2 is formed while including voids, thereby reducing the Young's modulus E1 of the base layer 2.

[0062] In this manner, the substrate 100b for printed wiring boards is manufactured, having the structure shown in Fig. 5. The substrate 100b for printed wiring boards manufactured in this manner has the base layer 2 formed thereon, on which the laminated portion 20 having excellent rectangularity can be formed, similar to the substrate 100a for printed wiring boards.

[0063] (Configuration of Printed Wiring Board) The following describes the configuration of printed wiring board 200. Fig. 11 is a cross-sectional view of printed wiring board 200. As shown in Fig. 11, printed wiring board 200 includes base film 1 and a plurality of laminated portions 20.

[0064] The direction perpendicular to the main surface 1s is defined as a first direction X. The direction perpendicular to the first direction X is defined as a second direction Y. The direction perpendicular to the first direction X and the second direction Y is defined as a third direction Z.

[0065] The plurality of laminated portions 20 are arranged on the main surface 1s. The plurality of laminated portions 20 are formed so as to extend linearly along the second direction Y. The plurality of laminated portions 20 are arranged at equal intervals in the third direction Z. If the shortest distance S between two adjacent laminated portions 20 in the third direction Z and the width L of each of the plurality of laminated portions 20 are less than 2 μm, it will take a long time to form the resist pattern 4 in the step S5 of forming the resist pattern 4, which will be described later. Therefore, as shown in FIG. 11 , the shortest distance S between two adjacent laminated portions 20 in the third direction Z may be 2 μm or more. The width L of each of the plurality of laminated portions 20 may be 2 μm or more.

[0066] Specifically, the plurality of laminated units 20 include adjacent first laminated units 20 a and second laminated units 20 b. The shortest distance S in the third direction Z from the first laminated unit 20 a to the second laminated unit 20 b may be 2 μm or more. The shortest distance S in the third direction Z from the first laminated unit 20 a to the second laminated unit 20 b may be 15 μm or less, or may be 10 μm or less.

[0067] The width L of each of the plurality of laminated portions 20 may be 15 μm or less, or may be 10 μm or less. Specifically, the width L of each of the first laminated portion 20 a and the second laminated portion 20 b may be 15 μm or less, or may be 10 μm or less. In step S5 of forming a resist pattern 4, which will be described later, a dry film resist, which is an inexpensive plating resist that can be produced in large areas and mass-produced, can be used to form the laminated portion 20 having the above width L.

[0068] The laminated portion 20 includes an underlayer 2 and an electrolytically plated layer 3. The underlayer 2 is in contact with the main surface 1s. The electrolytically plated layer 3 is in contact with the underlayer 2. The electrolytically plated layer 3 is a copper layer formed by electrolytic plating.

[0069] (Method for Manufacturing Printed Wiring Board) A method for manufacturing the printed wiring board 200 will be described below.

[0070] 12 is a flowchart illustrating a method for manufacturing the printed wiring board 200. The printed wiring board 200 is basically manufactured using a semi-additive process. Specifically, as shown in FIG. 12 , the method for manufacturing the printed wiring board 200 includes a step S5 of forming a resist pattern 4, a step S6 of forming an electrolytic plating layer 3, a step S7 of removing the resist pattern 4, and a step S8 of removing the base layer 2.

[0071] First, step S5 of forming a resist pattern 4 is carried out. In step S5, the resist pattern 4 is formed on the base layer 2. Any method such as photolithography can be used to form the resist pattern 4. Step S6 of forming an electrolytic plated layer 3 is carried out after step S5 of forming the resist pattern 4. Step S7 of removing the resist pattern 4 is carried out after step S6 of forming the electrolytic plated layer 3. Step S8 of removing the base layer 2 is carried out after step S7 of removing the resist pattern 4. The printed wiring board 200 is manufactured using the printed wiring board substrate 100a or the printed wiring board substrate 100b according to the first embodiment.

[0072] 13 is a cross-sectional view illustrating step S5 of forming a resist pattern 4. In step S5 of forming a resist pattern 4, the resist pattern 4 is formed on the underlayer 2 as shown in FIG.

[0073] The resist pattern 4 has openings 4a. The openings 4a are regions where the resist pattern 4 is not formed. The underlying layer 2 is exposed from the openings 4a.

[0074] In step S5 of forming the resist pattern 4, first, a resist in the form of, for example, a film is applied onto the underlayer 2. Second, the resist placed on the underlayer 2 is exposed and developed. As a result, the remaining part of the resist that has not been removed becomes the resist pattern 4, and the removed part of the resist becomes the opening 4a.

[0075] 14 is a cross-sectional view illustrating step S6 of forming the electrolytic plated layer 3. In step S6 of forming the electrolytic plated layer 3, the electrolytic plated layer 3 is formed on the base layer 2 exposed from the opening 4a, as shown in FIG. 14. The electrolytic plated layer 3 is formed by passing a current through the base layer 2 in a plating solution containing copper.

[0076] 15 is a cross-sectional view illustrating step S7 of removing resist pattern 4. In step S7 of removing resist pattern 4, as shown in Fig. 15, resist pattern 4 is removed from underlayer 2. As a result, underlayer 2 is exposed between two adjacent electroplated layers 3.

[0077] In step S8 of removing the base layer 2, the portion of the base layer 2 exposed between two adjacent electroplated layers 3 is removed by etching. Specifically, the base layer 2 is removed using a sulfuric acid-hydrogen peroxide etching solution. When the printed wiring board substrate 100 according to embodiment 1 is used, the Young's modulus E1 of the base layer 2 is smaller than the Young's modulus E2 of the electroplated layer 3. Specifically, the Young's modulus E1 of the base layer 2 is 0.5 to 0.9 times the Young's modulus E2 of the electroplated layer 3. Therefore, the etching rate of the base layer 2 is greater than the etching rate of the electroplated layer 3. As a result, even if the etching amount of the laminated portion 20 is too small, the laminated portion 20 has excellent rectangularity.

[0078] As a result of the above, a printed wiring board 200 having the structure shown in FIG. 11 is formed.

[0079] 16 is a cross-sectional view of printed wiring board 200 showing the measurement area for Young's modulus. Young's modulus E1 of base layer 2 and Young's modulus E2 of electrolytic plated layer 3 are measured by nanoindentation measurement. Young's modulus E1 of base layer 2 is 0.5 to 0.9 times the Young's modulus E2 of electrolytic plated layer 3. In this way, printed wiring board 200 having laminate portion 20 with excellent rectangularity is obtained.

[0080] 16, the Young's modulus E1 of the base layer 2 may be the Young's modulus of the laminate 20 measured in a first region V1 extending from the principal surface 1s to 0.05 μm. The Young's modulus E2 of the electrolytic plating layer 3 may be the Young's modulus of the laminate 20 in a second region V2 extending from the center c of the laminate 20 to the first surface 21s.

[0081] FIG. 17 is a schematic cross-sectional view of the laminate 20 shown in region XVII of FIG. 11 . The rectangularity of the laminate 20 is evaluated using a rectangularity evaluation index Et. Specifically, in a cross-section of the laminate 20 perpendicular to the second direction Y, the laminate 20 has a first surface 21s, a second surface 22s, a minimum surface 23s, a maximum surface 24s, and two side surfaces 20s. The first surface 21s is the surface of the laminate 20 farthest from the main surface 1s in the first direction X. The second surface 22s is the surface of the laminate 20 in contact with the main surface 1s. The two side surfaces 20s connect the first surface 21s and the second surface 22s. The minimum surface 23s and the maximum surface 24s may be surfaces located between the first surface 21s and the second surface 22s. The minimum surface 23s and the maximum surface 24s may be surfaces along the main surface 1s. The smallest surface 23s has a smallest width W3. The smallest width W3 is the smallest width in the third direction Z of the stacked portion 20. Depending on the etching conditions, the first surface 21s can become the smallest surface 23s. The largest surface 24s has a largest width W4. The largest width W4 is the largest width in the third direction Z of the stacked portion 20. Depending on the etching conditions, the second surface 22s can become the largeest surface 24s. In this case, if the rectangularity evaluation index is Et, then Et = W3 / W4.

[0082] The value obtained by dividing the maximum width W4 from the minimum width W3 (i.e., the rectangularity evaluation index Et) may be 0.8 or more. Specifically, the rectangularity evaluation index Et is 0.8 or more. The rectangularity evaluation index Et may be 0.9 or more. In this manner, the rectangularity of the laminated portion 20 is evaluated.

[0083] The rectangularity of the laminated portion 20 may be evaluated from another perspective. Specifically, the rectangularity of the laminated portion 20 may be evaluated by either the recess amount L1 or the protrusion amount L2. When the laminated portion 20 is etched, the shape of the side surface 20s of the laminated portion 20 may be a V-shape that protrudes inward. Specifically, at least one of the two side surfaces 20s may include a first point p1 and a first recessed point p3a. The first point p1 is the point where the side surface 20s and the first surface 21s intersect. On the side surface 20s, the first recessed point p3a is located on the side where the first surface 21s is located in the third direction Z, as viewed from the first point p1. The first recessed point p3a is located at a position that is the longest distance from the first point p1 in the third direction Z. From a different perspective, the first recessed point p3a is located at a position that overlaps with the first surface 21s in a plan view viewed from the first direction X. At this time, the recess amount L1 is expressed as L1=l1 / Ht, where l1 is the distance in the third direction Z from the first point p1 to the first recessed point p3a.

[0084] The distance l1 in the third direction Z from the first point p1 to the first recessed point p3a may be 0.15 times or less, 0.10 times or less, or 0.05 times or less of the height Ht of the stacked portion 20 from the main surface 1s to the first surface 21s. Specifically, the recess depth L1 is 0.15 or less. The recess depth L1 may be 0.10 times or less, or 0.05 times or less.

[0085] At least one of the two side surfaces 20s may include a second point p2 and a second recessed point p3b. The second point p2 is the point where the side surface 20s and the second surface 22s intersect. On the side surface 20s, the second recessed point p3b is located on the side where the second surface 22s is located in the third direction Z as viewed from the second point p2. The second recessed point p3b is located at the position that is the longest distance from the second point p2 in the third direction Z. In this case, the protrusion amount L2 is L2 = l2 / Ht. The distance l2 is the distance in the third direction Z from the second point p2 to the second recessed point p3b. The first recessed point p3a is a point for evaluating the recess amount L1, and the second recessed point p3b is a point for evaluating the protrusion amount L2. When the shape of the laminated portion 20 is bilaterally symmetrical, the first recessed point p3a and the second recessed point p3b on the two side surfaces 20s are arranged at positions that are linearly symmetrical about the central axis (axis of symmetry) of the laminated portion 20.

[0086] The distance l2 in the third direction Z from the second point p2 to the second recessed point p3b may be 0.15 times or less, 0.10 times or less, or 0.05 times or less the height Ht of the stacked portion 20 from the main surface 1s to the first surface 21s. Specifically, the protrusion amount L2 is 0.15 or less. The protrusion amount L2 may be 0.10 or less, or 0.05 or less.

[0087] (Effects) A printed wiring board 200 according to the present disclosure includes a base film 1 and a laminate portion 20. The base film 1 has a main surface 1s. The laminate portion 20 is disposed on the main surface 1s. The laminate portion 20 includes an underlayer 2 and an electrolytic plated layer 3. The underlayer 2 is in contact with the main surface 1s. The electrolytic plated layer 3 is in contact with the underlayer 2. The Young's modulus E1 of the underlayer 2 is 0.5 to 0.9 times the Young's modulus E2 of the electrolytic plated layer 3.

[0088] In this way, even if the etching amount of the laminated portion 20 is too small, it is possible to obtain a printed wiring board 200 having a circuit with excellent rectangularity.

[0089] In the above-described printed wiring board 200, the Young's modulus E1 of the underlayer 2 is 0.7 times or less the Young's modulus E2 of the electrolytic plated layer 3.

[0090] In this way, even if the etching amount of the laminated portion 20 is too small, it is possible to obtain a printed wiring board 200 having a circuit with excellent rectangularity.

[0091] In the printed wiring board 200, the Young's modulus E2 of the electrolytic plating layer 3 may be 85 GPa or more and 100 GPa or less.

[0092] In this way, even if the etching amount of the laminated portion 20 is too small, it is possible to obtain a printed wiring board 200 having a circuit with excellent rectangularity.

[0093] In the printed wiring board 200, the direction perpendicular to the main surface 1s is defined as the first direction X. The direction perpendicular to the first direction X is defined as the second direction Y. The direction perpendicular to the first direction X and the second direction Y is defined as the third direction Z. The laminated portion 20 is formed to extend linearly along the second direction Y. The laminated portion 20 includes adjacent first laminated portions 20a and second laminated portions 20b. The width L of each of the first laminated portion 20a and the second laminated portion 20b is 15 μm or less. The shortest distance in the third direction Z from the first laminated portion 20a to the second laminated portion 20b is 15 μm or less.

[0094] In this way, even if the etching amount of the laminated portion 20 is too small, it is possible to obtain a printed wiring board 200 having a circuit with excellent rectangularity.

[0095] In the printed wiring board 200, the width L of each of the first laminated portion 20a and the second laminated portion 20b is 10 μm or less. The shortest distance in the third direction Z from the first laminated portion 20a to the second laminated portion 20b is 10 μm or less. The width of each of the first laminated portion 20a and the second laminated portion 20b may be 6 μm or less. The shortest distance S in the third direction Z from the first laminated portion 20a to the second laminated portion 20b may be 6 μm or less.

[0096] In this way, even if the etching amount of the laminated portion 20 is too small, it is possible to obtain a printed wiring board 200 having a circuit with excellent rectangularity.

[0097] In the printed wiring board 200, the width L of each of the first laminated portion 20a and the second laminated portion 20b is 2 μm or more. The shortest distance in the third direction Z from the first laminated portion 20a to the second laminated portion 20b is 2 μm or more.

[0098] In this way, even if the etching amount of the laminated portion 20 is too small, it is possible to obtain a printed wiring board 200 having a circuit with excellent rectangularity.

[0099] In the above-described printed wiring board 200, the height of the laminated portion 20 is 1 μm or more. In this way, even if the etching amount of the laminated portion 20 is too small, it is possible to obtain the printed wiring board 200 having a circuit with excellent rectangularity.

[0100] In the printed wiring board 200, the laminate 20 has a first surface 21s that is farthest from the main surface 1s. The Young's modulus E1 of the base layer 2 is the Young's modulus of the laminate 20 measured in a first region V1 that is 0.05 μm from the main surface 1s. The Young's modulus E2 of the electrolytic plating layer 3 is the Young's modulus of the laminate 20 measured in a second region V2 that is from the center of the laminate 20 to the first surface 21s.

[0101] In this way, even if the etching amount of the laminated portion 20 is too small, it is possible to obtain a printed wiring board 200 having a circuit with excellent rectangularity.

[0102] In order to verify the effects of the above-described substrate 100 for a printed wiring board and the printed wiring board 200 manufactured from the substrate 100 for a printed wiring board, the following measurements were carried out.

[0103] (Sample Preparation) First, a substrate 500 for printed wiring boards is prepared, in which the material constituting the base film 1 is polyimide. The substrates 500 for printed wiring boards in Samples 1 to 6 are comparative examples. The substrates 500 for printed wiring boards in Samples 7 to 11 are examples. The manufacturing conditions and evaluation results of the substrates 500 for printed wiring boards shown in Samples 1 to 11 are shown in Tables 1 to 3.

[0104]

[0105]

[0106]

[0107] The printed wiring board substrate 500 in Sample 1 was not subjected to alkali treatment or excimer treatment as pretreatment. The base layer 2 of the printed wiring board substrate 500 was composed of a Ni—Cr seed layer and a sputtered copper layer as the first base layer 2a, and an electroless copper plating layer as the second base layer 2b. The thickness Ha of the first base layer 2a was 0.006 μm. The electroless copper plating layer as the second base layer 2b was formed to a thickness of 0.355 μm. The thickness H of the base layer 2 was 0.361 μm. The thickness of the second base layer 2b was the thickness H of the base layer 2 minus the thickness Ha of the first base layer 2a. After the electroless copper plating layer was formed, annealing was not performed.

[0108] The printed wiring board substrate 500 in Sample 2 was subjected to alkali treatment and excimer treatment as pretreatments. The base layer 2 of the printed wiring board substrate 500 was composed of a nano-copper sintered body layer as the first base layer 2a and an electroless copper plating layer as the second base layer 2b. The thickness Ha of the first base layer 2a was 0.034 μm. The electroless copper plating layer as the second base layer 2b was formed to a thickness of 0.225 μm. The thickness H of the base layer 2 was 0.259 μm. After the electroless copper plating layer was formed, annealing was not performed.

[0109] The printed wiring board substrate 500 of Sample 3 was subjected to excimer treatment as a pretreatment. The base layer 2 of the printed wiring board substrate 500 was composed of a nano-copper sintered body layer as the first base layer 2a and an electroless copper plating layer as the second base layer 2b. The thickness Ha of the first base layer 2a was 0.041 μm. The electroless copper plating layer as the second base layer 2b was formed to a thickness of 0.223 μm. The thickness H of the base layer 2 was 0.264 μm. After the electroless copper plating layer was formed, annealing was performed. Specifically, annealing was performed in an inert gas atmosphere such as nitrogen at an annealing temperature of 300°C for 1 hour.

[0110] The printed wiring board substrate 500 in Sample 4 was subjected to alkali treatment as a pretreatment. The base layer 2 of the printed wiring board substrate 500 was composed of a nano-copper sintered body layer as the first base layer 2a and an electroless copper plating layer as the second base layer 2b. The thickness Ha of the first base layer 2a was 0.026 μm. The electroless copper plating layer as the second base layer 2b was formed to a thickness of 0.185 μm. The thickness H of the base layer 2 was 0.211 μm. After the electroless copper plating layer was formed, annealing was performed. Specifically, annealing was performed in an inert gas atmosphere such as nitrogen at an annealing temperature of 300°C for 1 hour.

[0111] The printed wiring board substrate 500 of Sample 5 was subjected to excimer treatment as a pretreatment. The base layer 2 of the printed wiring board substrate 500 was composed of an electroless copper plating layer. The thickness H of the base layer 2 was 1.150 μm. After the electroless copper plating layer was formed, annealing was performed. Specifically, annealing was performed in an inert gas atmosphere such as nitrogen at an annealing temperature of 300° C. for 1 hour.

[0112] The printed wiring board substrate 500 in Sample 6 was subjected to alkali treatment and excimer treatment as pretreatments. The base layer 2 of the printed wiring board substrate 500 was composed of a nano-copper sintered body layer as the first base layer 2a and an electroless copper plating layer as the second base layer 2b. The thickness Ha of the first base layer 2a was 0.400 μm. The electroless copper plating layer as the second base layer 2b was formed to a thickness of 2.180 μm. The thickness H of the base layer 2 was 2.580 μm. After the electroless copper plating layer was formed, annealing was performed. Specifically, annealing was performed in an inert gas atmosphere such as nitrogen at an annealing temperature of 300°C for 1 hour.

[0113] The printed wiring board substrate 500 of Sample 7 was subjected to alkali treatment and excimer treatment as pretreatment. The base layer 2 of the printed wiring board substrate 500 was composed of an electroless copper plating layer. The thickness H of the base layer 2 was 0.452 μm. After the electroless copper plating layer was formed, annealing was performed. Specifically, in an inert gas atmosphere such as nitrogen, the annealing temperature was increased to 200°C and maintained at this annealing temperature for 30 minutes. The annealing temperature was increased to 300°C and maintained at this annealing temperature for 1 hour. The temperature increase rate was 1°C / min or more and 15°C / min or less.

[0114] The printed wiring board substrate 500 in Sample 8 was subjected to alkali treatment and excimer treatment as pretreatment. The base layer 2 of the printed wiring board substrate 500 was composed of a sputtered copper layer. The thickness H of the base layer 2 was 0.070 μm. After the base layer 2 was formed, annealing was performed. Specifically, in an inert gas atmosphere such as nitrogen, the annealing temperature was increased to 200° C. and maintained at this annealing temperature for 30 minutes. The annealing temperature was increased to 300° C. and maintained at this annealing temperature for 1 hour. The temperature increase rate was 1° C. / min or more and 15° C. / min or less.

[0115] The printed wiring board substrate 500 of Sample 9 was subjected to alkali treatment and excimer treatment as pretreatments. The base layer 2 of the printed wiring board substrate 500 was composed of a nano-copper sintered body layer. The thickness H of the base layer 2 was 0.155 μm. Because an electroless copper plating layer was not formed, annealing was not performed after the formation of the base layer 2.

[0116] The printed wiring board substrate 500 in Sample 10 underwent alkali treatment and excimer treatment as pretreatments. The base layer 2 of the printed wiring board substrate 500 is composed of a nano-copper sintered body layer as the first base layer 2a and an electroless copper plating layer as the second base layer 2b. The thickness Ha of the first base layer 2a is 0.156 μm. The electroless copper plating layer as the second base layer 2b is formed to a thickness of 0.130 μm. The thickness H of the base layer 2 is 0.286 μm. After the electroless copper plating layer is formed, annealing is performed. Specifically, in an inert gas atmosphere such as nitrogen, the annealing temperature is raised to 200°C and maintained at this temperature for approximately 30 minutes. The annealing temperature is raised to 300°C and maintained at this temperature for one hour. The temperature rise rate is 1°C / min or more and 15°C / min or less.

[0117] The printed wiring board substrate 500 in Sample 11 underwent alkali treatment and excimer treatment as pretreatments. The base layer 2 of the printed wiring board substrate 500 was composed of a nano-copper sintered body layer as the first base layer 2a and an electroless copper plating layer as the second base layer 2b. The thickness Ha of the first base layer 2a was 0.195 μm. The electroless copper plating layer as the second base layer 2b was formed to a thickness of 0.672 μm. The thickness H of the base layer 2 was 0.867 μm. After the electroless copper plating layer was formed, annealing was performed. Specifically, in an inert gas atmosphere such as nitrogen, the annealing temperature was raised to 200°C and maintained at this temperature for approximately 30 minutes. The annealing temperature was raised to 300°C and maintained at this temperature for one hour. The temperature rise rate was 1°C / min or more and 15°C / min or less.

[0118] By forming an electrolytic plating layer 3 on each of the samples 1 to 11 prepared as described above, a printed wiring board substrate 500 having a laminated portion 20 formed thereon as shown in FIG. 18 is prepared.

[0119] <Evaluation of Young's modulus of laminate portion> The Young's modulus of laminate portion 20 was evaluated using printed wiring board substrates 500 of Samples 1 to 11. Fig. 18 is a cross-sectional view of printed wiring board substrate 500 on which electrolytic plated layer 3 is formed, showing the area where Young's modulus was measured. Young's modulus E1 of base layer 2 and Young's modulus E2 of electrolytic plated layer 3 were measured by nanoindentation measurement.

[0120] Before measuring the Young's modulus by nanoindentation, the cross section of the printed wiring board substrate 500 having the electrolytic plating layer 3 formed thereon is processed by argon ion polishing. The acceleration voltage of the ion beam is set to, for example, 6 kV.

[0121] Next, the Young's modulus E1 of the underlayer 2 and the Young's modulus E2 of the electroplated layer 3 are measured by nanoindentation measurement. The Young's modulus E1 of the underlayer 2 and the Young's modulus E2 of the electroplated layer 3 are measured using a Bruker Hysitron TI 980 Triboindenter. The indenter used is a Berkovich indenter. The Young's modulus in the nanoindentation measurement is measured in accordance with ISO 14577. The loading time is 5 seconds. The maximum loading time is 2 seconds. The unloading time is 5 seconds. The maximum load is 130 μN. The Young's modulus E1 of the underlayer 2 and the Young's modulus E2 of the electroplated layer 3 are measured in an environment of room temperature 20°C and standard atmospheric pressure.

[0122] The Young's modulus E1 of the underlayer 2 is defined as the Young's modulus of the laminate 20 measured in a first region V1 extending from the principal surface 1s to 0.05 μm. The Young's modulus E2 of the electrolytic plating layer 3 is defined as the Young's modulus of the laminate 20 in a second region V2 extending from the center c of the laminate 20 to the first surface 21s.

[0123] The Young's modulus E1 of the underlayer 2 is the average value of the Young's moduli measured at three points in the first region V1. The Young's modulus E2 of the electrolytic plating layer 3 is the average value of the Young's moduli measured at three points in the second region V2.

[0124] When the Young's modulus E1 of the base layer 2 is 0.5 to 0.7 times the Young's modulus E2 of the electroplated layer 3, the Young's modulus of the laminate 20 is evaluated as A in Table 1. When the Young's modulus E1 of the base layer 2 is more than 0.7 to 0.9 times the Young's modulus E2 of the electroplated layer 3, the Young's modulus of the laminate 20 is evaluated as B in Table 1. When the Young's modulus E1 of the base layer 2 is more than 0.9 to 0.95 times the Young's modulus E2 of the electroplated layer 3, the Young's modulus of the laminate 20 is evaluated as C in Table 1. When the Young's modulus E1 of the base layer 2 is more than 0.95 times the Young's modulus E2 of the electroplated layer 3, the Young's modulus of the laminate 20 is evaluated as D in Table 1. If the Young's modulus E1 of the underlayer 2 is less than 0.5 times the Young's modulus E2 of the electrolytic plated layer 3, the Young's modulus of the laminated portion 20 is evaluated as D in Table 1.

[0125] In Sample 1, the ratio (E1 / E2) of Young's moduli in the base layer 2 and the electrolytic plating layer 3 was 1.00. In Sample 2, the ratio (E1 / E2) of Young's moduli in the base layer 2 and the electrolytic plating layer 3 was 0.91. In Sample 3, the ratio (E1 / E2) of Young's moduli in the base layer 2 and the electrolytic plating layer 3 was 0.95. In Sample 4, the ratio (E1 / E2) of Young's moduli in the base layer 2 and the electrolytic plating layer 3 was 0.91. In Sample 5, the ratio (E1 / E2) of Young's moduli in the base layer 2 and the electrolytic plating layer 3 was 0.91. In Sample 6, the ratio (E1 / E2) of Young's moduli in the base layer 2 and the electrolytic plating layer 3 was 0.48.

[0126] In Sample 7, the ratio (E1 / E2) of Young's moduli of the base layer 2 to the electrolytic plating layer 3 was 0.79. In Sample 8, the ratio (E1 / E2) of Young's moduli of the base layer 2 to the electrolytic plating layer 3 was 0.86. In Sample 9, the ratio (E1 / E2) of Young's moduli of the base layer 2 to the electrolytic plating layer 3 was 0.55. In Sample 10, the ratio (E1 / E2) of Young's moduli of the base layer 2 to the electrolytic plating layer 3 was 0.59. In Sample 11, the ratio (E1 / E2) of Young's moduli of the base layer 2 to the electrolytic plating layer 3 was 0.71.

[0127] From the Young's modulus ratios (E1 / E2) in Samples 1 to 11, as shown in Tables 1 to 3, the Young's modulus of the laminated portion 20 in Samples 1 to 6 is evaluated as C or D. On the other hand, the Young's modulus of the laminated portion 20 in Samples 7 to 11 is evaluated as A or B. In particular, the Young's modulus of the laminated portion 20 in Samples 9 and 10 is evaluated as A.

[0128] As will be described later, when evaluating the Young's modulus of the laminated portion 20 of a printed wiring board 200 having wiring formed thereon, the target areas for performing the above-described measurements are the first area V1 and the second area V2 shown in FIG. 16.

[0129] <Evaluation of Rectangularity of Laminated Portion> When printed wiring boards 200 were manufactured using printed wiring board substrates 500 of Samples 1 to 11, the rectangularity of laminated portion 20 was evaluated.

[0130] The rectangularity of the laminated portion 20 is evaluated using a rectangularity evaluation index Et. As shown in FIG. 17 , the minimum surface 23s and the maximum surface 24s may be surfaces located between the first surface 21s and the second surface 22s. The minimum surface 23s has a minimum width W3. The minimum width W3 is the smallest width of the laminated portion 20 in the third direction Z. The maximum surface 24s has a maximum width W4. The maximum width W4 is the largest width of the laminated portion 20 in the third direction Z. Depending on the etching conditions, the first surface 21s may become the minimum surface 23s. Depending on the etching conditions, the second surface 22s may become the maximum surface 24s. In this case, when the rectangularity evaluation index is Et, Et = W3 / W4.

[0131] When the rectangularity evaluation index Et was 0.9 or more, the rectangularity of the laminated portion was evaluated as A. When the rectangularity evaluation index Et was 0.8 or more and less than 0.9, the rectangularity of the laminated portion was evaluated as B. When the rectangularity evaluation index Et was 0.7 or more and less than 0.8, the rectangularity of the laminated portion was evaluated as C. When the rectangularity evaluation index Et was less than 0.7, the rectangularity of the laminated portion was evaluated as D.

[0132] As shown in Tables 1 to 3, in Samples 1 to 6, the rectangularity of the laminated portion 20 was evaluated as C or D. On the other hand, in Samples 7 to 11, the rectangularity of the laminated portion 20 was evaluated as A or B. In particular, in Samples 9 and 10, the rectangularity of the laminated portion 20 was evaluated as A. This is largely due to the influence of the Young's modulus of the laminated portion 20.

[0133] <Evaluation of Fine Wire Formability in Laminated Portion> The fine wire formability in laminated portion 20 of printed wiring board 200 manufactured using printed wiring board substrate 500 of Samples 1 to 11 was evaluated.

[0134] An evaluation TEG was used to evaluate the fine line formability of the laminated portion 20. FIG. 19 is a plan view of the evaluation TEG. As shown in FIG. 19, the evaluation TEG has a base film 1 and a plurality of laminated portions 20. In the evaluation TEG, the main surface 1s has 20 wiring formation regions R1, 20 wiring formation regions R2, and 20 wiring formation regions R3. The 20 wiring formation regions R1, 20 wiring formation regions R2, and 20 wiring formation regions R3 are arranged in a row along the left-right direction.

[0135] A plurality of laminated portions 20 are formed on the wiring formation regions R1, R2, and R3. The laminated portions 20 formed on the wiring formation region R1 extend in the vertical direction (second direction Y in FIG. 19 ). The laminated portions 20 formed on the wiring formation region R2 and the laminated portions 20 formed on the wiring formation region R3 extend in directions inclined at 45° and −45° with respect to the vertical direction, respectively.

[0136] The L / S of the laminated portion 20 formed on the nth (n is a natural number equal to or less than 20) interconnect formation region R1 from the right is n μm / 100 μm. L is the width of each of the plurality of laminated portions 20. S is the shortest distance between two adjacent laminated portions 20. The L / S of the laminated portions 20 formed on the interconnect formation region R2 and the laminated portions 20 formed on the interconnect formation region R3 is n μm / 100 μm, similar to the L / S formed on the interconnect formation region R1. The aspect ratio of the laminated portion 20 (the value obtained by dividing the height Ht of the laminated portion 20 by the width L of the laminated portion 20) is set to 1 or more and 2 or less.

[0137] For each of the 20 wiring formation regions R1, each of the 20 wiring formation regions R2, and each of the 20 wiring formation regions R3, the stacked portion 20 was observed using a SEM (Scanning Electron Microscope) to determine whether the fine lines had been formed properly.

[0138] In Tables 1 to 3, when the minimum value of the width L of the laminated portion 20 that can be properly formed is 6 μm or less, the evaluation was given as A. When the minimum value of the width L of the laminated portion 20 that can be properly formed is more than 6 μm and not more than 10 μm, the evaluation was given as B. When the minimum value of the width L of the laminated portion 20 that can be properly formed is more than 10 μm and not more than 15 μm, the evaluation was given as C. When the minimum value of the width L of the laminated portion 20 that can be properly formed is more than 15 μm, the evaluation was given as D.

[0139] As shown in Tables 1 to 3, in Samples 5 and 6, the thin-line formability of the laminated portion 20 was evaluated as C or D. On the other hand, in Samples 1 to 4 and Samples 7 to 11, the thin-line formability of the laminated portion 20 was evaluated as A or B. From these results, it is considered that the thin-line formability of the laminated portion 20 is significantly affected by the thickness H of the base layer 2. In Samples 5 and 6, the thickness H of the base layer 2 is greater than 1 μm. On the other hand, in Samples 1 to 4 and Samples 7 to 11, the thickness H of the base layer 2 is less than 1 μm, and therefore the thin-line formability of the laminated portion 20 is good.

[0140] <Overall Evaluation> From the above, by lowering the Young's modulus E1 of the base layer 2, the rectangular shape of the laminate portion 20 is improved even if the etching amount of the laminate portion 20 is too small. Furthermore, by improving the fine line formability of the laminate portion 20, a printed wiring board 200 having a fine circuit can be obtained. In particular, the rectangular shape and fine line formability of the laminate portion 20 in the printed wiring boards manufactured using the printed wiring board substrates of Samples 9 and 10 are good.

[0141] The embodiments disclosed herein are illustrative in all respects and should not be considered limiting. The basic scope of the present disclosure is defined by the claims, not the above-described embodiments, and is intended to include all modifications within the meaning and scope of the claims.

[0142] 1 base film, 1s main surface, 2 underlayer, 2a first underlayer, 2b second underlayer, 2s underlayer surface, 3 electrolytic plating layer, 4 resist pattern, 4a opening, 20 laminated portion, 20a first laminated portion, 20b second laminated portion, 20s side, 21s first surface, 22s second surface, 23s smallest surface, 24s largest surface, 100, 100a, 100b, 500 printed wiring board substrate, 200 printed wiring board, 300 plating apparatus, 310 plating treatment tank, 311 electrode, 320 roller, 331, 332 electrode roller, 340 power supply, E1, E2 Young's modulus, Et rectangularity evaluation index, H, Ha, l1, l2 distance, H, Ha thickness, Ht height, L width, L1 recess amount, L2 Projection amount, R1, R2, R3 Wiring formation area, S Shortest distance, V1 First area, V2 Second area, W3 Minimum width, W4 Maximum width, X First direction, Y Second direction, Z Third direction, p1 First point, p2 Second point, p3a First recessed point, p3b Second recessed point, s Intermediate base layer surface.

Claims

1. A printed wiring board comprising: a base film having a principal surface; and a laminate portion disposed on said principal surface, said laminate portion including an underlayer in contact with said principal surface and an electroplated layer in contact with said underlayer, wherein the Young's modulus of said underlayer is 0.5 to 0.9 times the Young's modulus of said electroplated layer.

2. The printed wiring board according to claim 1, wherein the Young's modulus of said underlayer is 0.7 times or less the Young's modulus of said electrolytic plating layer.

3. The printed wiring board according to claim 1 or 2, wherein the Young's modulus of the electrolytic plating layer is 85 GPa or more and 100 GPa or less.

4. A printed wiring board according to any one of claims 1 to 3, wherein a direction perpendicular to said main surface is defined as a first direction, a direction perpendicular to said first direction is defined as a second direction, and a direction perpendicular to said first direction and said second direction is defined as a third direction, said laminate portion is formed to extend linearly along said second direction, and further said laminate portion includes adjacent first laminate portion and second laminate portion, each of said first laminate portion and said second laminate portion has a width of 15 μm or less, and the shortest distance in said third direction from said first laminate portion to said second laminate portion is 15 μm or less.

5. The printed wiring board according to claim 4, wherein the width of each of the first laminated portion and the second laminated portion is 10 μm or less, and the shortest distance in the third direction from the first laminated portion to the second laminated portion is 10 μm or less.

6. The printed wiring board according to claim 5, wherein the width of each of the first laminated portion and the second laminated portion is 2 μm or more, and the shortest distance from the first laminated portion to the second laminated portion in the third direction is 2 μm or more.

7. The printed wiring board according to any one of claims 1 to 6, wherein the height of the laminated portion is 1 μm or more.

8. A printed wiring board as claimed in any one of claims 1 to 7, wherein the laminate portion has a first surface farthest from the main surface, the Young's modulus of the base layer is the Young's modulus of the laminate portion measured in a first region up to 0.05 μm from the main surface, and the Young's modulus of the electrolytic plating layer is the Young's modulus of the laminate portion measured in a second region from the center of the laminate portion to the first surface.

Images