Display substrate and display device

Abstract

A display substrate, comprising: a base (10); a plurality of sub-pixels (PX) provided on one side of the base (10) and located in a display area (AA); a plurality of first data lines (DLa); a plurality of second data lines (DLb); a plurality of data connecting lines (25); a plurality of data lead-out lines located in a lead-out routing area; a plurality of first transfer units (300a, 300b) and a plurality of second transfer units (32a, 32b); and a plurality of data contact pads (27) located in a first signal access area (B134). The plurality of first transfer units (300a, 300b) are located on the side of the plurality of second transfer units (32a, 32b) distant from the display area (AA). The plurality of data lead-out lines are connected to the plurality of data contact pads (27) by means of the plurality of first transfer units (300a, 300b), and are connected to the plurality of second data lines (DLb) and the plurality of data connection lines (25) by means of the plurality of second transfer units (32a, 32b).

Description

Display substrate and display device TECHNICAL FIELD

[0001] The present document relates to, but is not limited to, the technical field of display, and in particular to a display substrate and a display device. BACKGROUND

[0002] Organic light emitting diode (OLED) and quantum dot light emitting diode (QLED) are active light emitting display devices, which have the advantages of self-emission, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, bendability and low cost.

[0003] SUMMARY

[0004] The following is a summary of the subject matter of the detailed description herein. This summary is not intended to limit the scope of the claims.

[0005] The present embodiment provides a display substrate and a display device.

[0006] In one aspect, the present embodiment provides a display substrate, comprising: a substrate, a plurality of sub-pixels, a plurality of first data lines, a plurality of second data lines, a plurality of data connection lines, a plurality of data lead-out lines, a plurality of data contact pads, and a plurality of groups of switching units. The substrate comprises a display area and a first frame area located on one side of the display area along a first direction, and the first frame area comprises a first signal access area and a lead-out area of wires located between the first signal access area and the display area. The plurality of sub-pixels are arranged on one side of the substrate and located in the display area. The plurality of first data lines, the plurality of second data lines, and the plurality of data connection lines are located in the display area; the plurality of first data lines and the plurality of second data lines are configured to provide data signals to the plurality of sub-pixels, and the plurality of first data lines are connected to the plurality of data connection lines. The plurality of data lead-out lines are located in the lead-out area of wires. The plurality of data contact pads are located in the first signal access area. The plurality of groups of first switching units and the plurality of groups of second switching units are located in the lead-out area of wires, the plurality of groups of first switching units are located on the side of the plurality of groups of second switching units away from the display area, the plurality of groups of first switching units are arranged along a second direction, the plurality of groups of second switching units are arranged along the second direction, and the second direction intersects the first direction. The plurality of data lead-out lines are connected to the plurality of data contact pads through the plurality of groups of first switching units, and are connected to the plurality of second data lines and the plurality of data connection lines through the plurality of groups of second switching units, so that the order of the data signals provided by the plurality of data contact pads matches the order of the data signals required by the plurality of second data lines and the plurality of data connection lines arranged along the second direction.

[0007] In some example embodiments, each group of first adapting units comprises m first connection ends, m second connection ends, and m first adapting lines; each first adapting line is connected between one first connection end and one second connection end; each first connection end is connected with one data lead-out line, and each second connection end is connected with one data contact pad; the m first connection ends are arranged along the second direction and correspond to different first arrangement serial numbers, and the m second connection ends are arranged along the second direction and correspond to different second arrangement serial numbers. The m first adapting lines in each group of first adapting units comprise a first-order adapting line, wherein the first arrangement serial number corresponding to the first connection end connected by the first-order adapting line is different from the second arrangement serial number corresponding to the second connection end connected by the first-order adapting line; m and a are integers greater than 1, and m is greater than or equal to a. The second direction intersects the first direction.

[0008] In some example embodiments, the a first-order adapting lines in each group of first adapting units comprise a1 first-order adapting lines and a2 second-order adapting lines, a1 and a2 are integers greater than 0, and the sum of a1 and a2 is a; the first arrangement serial number corresponding to the first connection end connected by the first-order adapting line is less than the second arrangement serial number corresponding to the second connection end connected by the first-order adapting line; the first arrangement serial number corresponding to the first connection end connected by the second-order adapting line is greater than the second arrangement serial number corresponding to the second connection end connected by the second-order adapting line.

[0009] In some example embodiments, the difference between the second arrangement serial number corresponding to the second connection end connected by the first-order adapting line and the first arrangement serial number corresponding to the first connection end connected by the first-order adapting line is greater than or equal to the difference between the first arrangement serial number corresponding to the first connection end connected by the second-order adapting line and the second arrangement serial number corresponding to the second connection end connected by the second-order adapting line.

[0010] In some example embodiments, the first-order adapting line in the substrate has an overlapping projection with at least one second-order adapting line in the substrate.

[0011] In some example embodiments, the m adapting lines in each group of first adapting units further comprise b first-order adapting lines, wherein the first arrangement serial number corresponding to the first connection end connected by the first-order adapting line is the same as the second arrangement serial number corresponding to the second connection end connected by the first-order adapting line; b is an integer greater than 1, and b is less than or equal to a.

[0012] In some example embodiments, the b first-order adapting lines and the first-order adapting line are in the same layer structure, or at least one first-order adapting line is located on the side close to the substrate of the first-order adapting line and the second-order adapting line.

[0013] In some example embodiments, m is 8; each group of first adapter units comprises eight first connection terminals, eight second connection terminals, and eight first adapter lines; the eight first connection terminals are arranged in sequence along the second direction, the eight second connection terminals are arranged in sequence along the second direction and located on a side of the eight first connection terminals close to the first signal access area, and the eight first adapter lines comprise two first plug sequence adapter lines, two second plug sequence adapter lines, and four first order adapter lines; the first plug sequence adapter line is configured to connect an i-th first connection terminal and an (i+1)-th second connection terminal; the second plug sequence adapter line is configured to connect an (i+1)-th first connection terminal and an i-th second connection terminal; and the value of i includes 1 and 5.

[0014] In some example embodiments, one pixel unit located in the display area comprises one first sub-pixel emitting first color light, one second sub-pixel emitting second color light, and two third sub-pixels emitting third color light. The plurality of data contact pads are configured to provide data signals to the sub-pixels of an e-th row of pixel units in the display area in a first time period and to the sub-pixels of an (e+1)-th row of pixel units in the display area in a second time period, where e is an integer greater than 0. In the first time period, the data signals transmitted by the eight second connection terminals in each group of first adapter units are configured to correspond to the third sub-pixel, the first sub-pixel, the second sub-pixel, the third sub-pixel, the third sub-pixel, the second sub-pixel, the first sub-pixel, and the third sub-pixel in sequence, or are configured to correspond to the first sub-pixel, the third sub-pixel, the third sub-pixel, the second sub-pixel, the second sub-pixel, the third sub-pixel, the third sub-pixel, and the first sub-pixel in sequence. In the second time period, the data signals transmitted by the eight second connection terminals in each group of first adapter units are configured to correspond to the third sub-pixel, the second sub-pixel, the first sub-pixel, the third sub-pixel, the third sub-pixel, the first sub-pixel, the second sub-pixel, and the third sub-pixel in sequence, or are configured to correspond to the second sub-pixel, the third sub-pixel, the third sub-pixel, the first sub-pixel, the first sub-pixel, the third sub-pixel, the third sub-pixel, and the second sub-pixel in sequence.

[0015] In some example embodiments, m is 12. Each group of first adapting units comprises twelve first connection ends, twelve second connection ends, and twelve first adapting lines; the twelve first connection ends are arranged in sequence along the second direction, the twelve second connection ends are arranged in sequence along the second direction and located on a side of the twelve first connection ends close to the first signal access area, and the twelve first adapting lines comprise four first plug sequence adapting lines, four second plug sequence adapting lines, and four first order adapting lines; the first plug sequence adapting line is configured to connect an i-th first connection end and an (i+1)-th second connection end; the second plug sequence adapting line is configured to connect an (i+1)-th first connection end and an i-th second connection end; and the value of i includes 1, 3, 7, and 9.

[0016] In some example embodiments, one pixel unit located in the display area comprises a first sub-pixel emitting first color light, a second sub-pixel emitting second color light, and two third sub-pixels emitting third color light. The plurality of data contact pads are configured to provide data signals to the sub-pixels of an e-th row of pixel units in the display area in a first time period and to the sub-pixels of an (e+1)-th row of pixel units in the display area in a second time period, where e is an integer greater than 0. In the first time period, the data signals transmitted by the twelve second connection ends in each group of first adapting units are configured to correspond to the third sub-pixel, the first sub-pixel, the third sub-pixel, the second sub-pixel, the second sub-pixel, the third sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, the first sub-pixel, the second sub-pixel, and the third sub-pixel in sequence; or, are configured to correspond to the first sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the third sub-pixel, the first sub-pixel, the second sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the third sub-pixel, and the first sub-pixel in sequence. In the second time period, the data signals transmitted by the twelve second connection ends in each group of first adapting units are configured to correspond to the third sub-pixel, the second sub-pixel, the third sub-pixel, the first sub-pixel, the first sub-pixel, the third sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the second sub-pixel, the first sub-pixel, and the third sub-pixel in sequence, or, are configured to correspond to the second sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, the third sub-pixel, the second sub-pixel, the first sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, the third sub-pixel, and the second sub-pixel in sequence.

[0017] In some example embodiments, m is 16. Each group of first adapter units comprises sixteen first connection ends, sixteen second connection ends, and sixteen first adapter lines. The sixteen first connection ends are arranged in sequence along the second direction. The sixteen second connection ends are arranged in sequence along the second direction and located on a side of the sixteen first connection ends close to the first signal access area. The sixteen first adapter lines comprise four first plug sequence adapter lines, four second plug sequence adapter lines, and eight first order adapter lines. The first plug sequence adapter line is configured to connect an i-th first connection end and an (i+1)-th second connection end. The second plug sequence adapter line is configured to connect an (i+1)-th first connection end and an i-th second connection end. The value of i includes 1, 3, 9, and 11.

[0018] In some example embodiments, one pixel unit located in the display area comprises one first sub-pixel emitting first color light, one second sub-pixel emitting second color light, and two third sub-pixels emitting third color light. The plurality of data contact pads are configured to provide data signals to the sub-pixels of an e-th row of pixel units in the display area in a first time period and to the sub-pixels of an (e+1)-th row of pixel units in the display area in a second time period, where e is an integer greater than 0. In the first time period, the data signals transmitted by the sixteen second connection ends in each group of first adapter units are configured to correspond to the third sub-pixel, the first sub-pixel, the third sub-pixel, the second sub-pixel, the second sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the first sub-pixel, the first sub-pixel, the third sub-pixel, the second sub-pixel, and the third sub-pixel in sequence, or are configured to correspond to the first sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, the second sub-pixel, the second sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, and the first sub-pixel in sequence. In the second time period, the data signals transmitted by the sixteen second connection ends in each group of first adapter units are configured to correspond to the third sub-pixel, the second sub-pixel, the third sub-pixel, the first sub-pixel, the first sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, the second sub-pixel, the second sub-pixel, the third sub-pixel, the first sub-pixel, and the third sub-pixel in sequence, or are configured to correspond to the second sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the first sub-pixel, the first sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, and the second sub-pixel in sequence.

[0019] In some example embodiments, m is 20. Each group of first switching units comprises twenty first connection ends, twenty second connection ends, and twenty first switching lines; the twenty first connection ends are arranged in sequence along the second direction, the twenty second connection ends are arranged in sequence along the second direction and located on a side of the twenty first connection ends close to the first signal access area, and the twenty first switching lines comprise six first plug sequence switching lines, six second plug sequence switching lines, and eight first order switching lines; the first plug sequence switching line is configured to connect an i-th first connection end and an i+1-th second connection end; the second plug sequence switching line is configured to connect an i+1-th first connection end and an i-th second connection end; and the value of i includes 1, 3, 5, 11, 13, and 15.

[0020] In some example embodiments, one pixel unit located in the display area comprises one first sub-pixel emitting first color light, one second sub-pixel emitting second color light, and two third sub-pixels emitting third color light. The plurality of data contact pads are configured to provide data signals to the sub-pixels of an e-th row of pixel units in the display area in a first time period and to the sub-pixels of an e+1-th row of pixel units in the display area in a second time period, where e is an integer greater than 0. In the first time period, the data signals transmitted by the twenty second connection ends in each group of first switching units are configured to correspond to the third sub-pixel, the first sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the second sub-pixel, the first sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the first sub-pixel, the first sub-pixel, the third sub-pixel, the second sub-pixel, and the third sub-pixel in sequence, or are configured to correspond to the first sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the first sub-pixel, the second sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, and the first sub-pixel in sequence. In the second time period, the data signals transmitted by the sixteen second connection ends in each group of first switching units are configured to correspond to the third sub-pixel, the second sub-pixel, the third sub-pixel, the first sub-pixel, the first sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, the second sub-pixel, the second sub-pixel, the third sub-pixel, the first sub-pixel, and the third sub-pixel in sequence, or are configured to correspond to the second sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the first sub-pixel, the first sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, and the second sub-pixel in sequence.

[0021] In some example embodiments, one pixel unit located in the display area includes: one first sub-pixel for emitting light of a first color, one second sub-pixel for emitting light of a second color, and two third sub-pixels for emitting light of a third color. The plurality of data lead lines connected with the first connection end of the plurality of groups of first adapter units includes: a first group of data lead lines and a second group of data lead lines, the first group of data lead lines and the second group of data lead lines are located in different conductive layers and are arranged alternately along the second direction, the first group of data lead lines are configured to transmit data signals required by the third sub-pixels, and the second group of data lead lines are configured to transmit data signals required by the first sub-pixel and the second sub-pixel.

[0022] In some example embodiments, the display substrate further includes: a plurality of groups of test circuits located in the trace lead-out area and arranged in sequence along the second direction; the plurality of groups of test circuits are located on the side of the plurality of groups of first adapter units away from the first signal access area along the first direction; wherein one group of test circuits is connected with m data lead lines connected with one group of first adapter units; the second direction intersects the first direction; each group of test circuits includes: a first test circuit and b second test circuits; twice the sum of a and b is equal to m, and a and b are both integers greater than 0. The first test circuit includes: a first test transistor, a second test transistor, and a third test transistor; the gate of the first test transistor is connected with a first test control line, the first electrode of the first test transistor is connected with a first test data line, the gate of the second test transistor is connected with a second test control line, the first electrode of the second test transistor is connected with a second test data line, and the second electrode of the first test transistor and the second electrode of the second test transistor are connected with the same data lead line; the gate of the third test transistor is connected with a third test control line, and the first electrode of the third test transistor is connected with a third test data line. The second test circuit includes: a fourth test transistor, a fifth test transistor, and a sixth test transistor; the gate of the fourth test transistor is connected with the second test control line, the first electrode of the fourth test transistor is connected with the first test data line, the gate of the fifth test transistor is connected with the first test control line, the first electrode of the fifth test transistor is connected with the second test data line, and the second electrode of the fourth test transistor and the second electrode of the fifth test transistor are connected with the same data lead line; the gate of the sixth test transistor is connected with the third test control line, and the first electrode of the third test transistor is connected with the third test data line; the second electrode of the first test transistor, the second electrode of the third test transistor, the second electrode of the fourth test transistor, and the second electrode of the sixth test transistor are connected with different data lead lines.

[0023] In some example embodiments, the first test transistor, the second test transistor and the third test transistor of the first test circuit are arranged along the first direction; the fourth test transistor, the fifth test transistor and the sixth test transistor of the second test circuit are arranged along the first direction. The first test transistor and the fourth test transistor are arranged in alignment in the second direction, the second test transistor and the fifth test transistor are arranged in alignment in the second direction, and the third test transistor and the sixth test transistor are arranged in alignment in the second direction.

[0024] In some example embodiments, m is 8. Each group of test circuits comprises two first test circuits and two second test circuits; wherein one first test circuit, two second test circuits and one first test circuit are arranged along the second direction.

[0025] In some example embodiments, m is 12. Each group of test circuits comprises three first test circuits and three second test circuits; wherein one first test circuit, two second test circuits, two first test circuits and one second test circuit are arranged along the second direction; or one first test circuit, one second test circuit, one first test circuit, two second test circuits and one first test circuit are arranged along the reverse direction of the second direction.

[0026] In some example embodiments, m is 16. Each group of test circuits comprises four first test circuits and four second test circuits; wherein one first test circuit, two second test circuits, one first test circuit, one second test circuit, two first test circuits and one second test circuit are arranged along the second direction; or one first test circuit, one second test circuit, one first test circuit, two second test circuits, one first test circuit, one second test circuit and one first test circuit are arranged along the reverse direction of the second direction.

[0027] In some example embodiments, m is 20. Each group of test circuits comprises five first test circuits and five second test circuits; wherein one first test circuit, two second test circuits, one first test circuit, one second test circuit, one first test circuit, one second test circuit, two first test circuits and one second test circuit are arranged along the second direction; or one first test circuit, one second test circuit, one first test circuit, one second test circuit, one first test circuit, two second test circuits, one first test circuit, one second test circuit and one first test circuit are arranged along the reverse direction of the second direction.

[0028] In some example embodiments, a single pixel unit of the display area includes c sub-pixels, m is k times of c, and k is an integer greater than 1.

[0029] In another aspect, the present embodiments provide a display device including the display substrate as described above.

[0030] In another aspect, the embodiment provides a display substrate, comprising: a substrate, a plurality of sub-pixels, a plurality of first data lines, a plurality of second data lines, a plurality of data connection lines, a plurality of data lead-out lines, and a plurality of test circuits. The substrate comprises: a display area and a first frame area located at one side of the display area along a first direction, the first frame area comprising: a first signal access area and a trace lead-out area located between the first signal access area and the display area. The plurality of sub-pixels are arranged at one side of the substrate and located in the display area. The plurality of first data lines, the plurality of second data lines, and the plurality of data connection lines are located in the display area; the plurality of first data lines and the plurality of second data lines are configured to provide data signals to the plurality of sub-pixels, and the plurality of first data lines are connected to the plurality of data connection lines. The plurality of data lead-out lines are located in the trace lead-out area, and the plurality of data lead-out lines are connected to the plurality of second data lines and the plurality of data connection lines. The plurality of test circuits are located in the trace lead-out area and arranged in sequence along a second direction, each test circuit is connected to m continuously arranged data lead-out lines, and the second direction intersects the first direction; m is an integer greater than 1. Each test circuit comprises: a first test circuit and a second test circuit, a and b are both integers greater than 0, and twice the sum of a and b is equal to m. The first test circuit comprises: a first test transistor, a second test transistor, and a third test transistor; a gate of the first test transistor is connected to a first test control line, a first electrode of the first test transistor is connected to a first test data line, a gate of the second test transistor is connected to a second test control line, a first electrode of the second test transistor is connected to a second test data line, a second electrode of the first test transistor and a second electrode of the second test transistor are connected to the same data lead-out line; a gate of the third test transistor is connected to a third test control line, and a first electrode of the third test transistor is connected to a third test data line. The second test circuit comprises: a fourth test transistor, a fifth test transistor, and a sixth test transistor; a gate of the fourth test transistor is connected to the second test control line, a first electrode of the fourth test transistor is connected to the first test data line, a gate of the fifth test transistor is connected to the first test control line, a first electrode of the fifth test transistor is connected to the second test data line, a second electrode of the fourth test transistor and a second electrode of the fifth test transistor are connected to the same data lead-out line; a gate of the sixth test transistor is connected to the third test control line, and a first electrode of the third test transistor is connected to the third test data line; a second electrode of the first test transistor, a second electrode of the third test transistor, a second electrode of the fourth test transistor, and a second electrode of the sixth test transistor are connected to different data lead-out lines.

[0031] In some example embodiments, the first test transistor, the second test transistor and the third test transistor of the first test circuit are arranged along the first direction; the fourth test transistor, the fifth test transistor and the sixth test transistor of the second test circuit are arranged along the first direction. The first test transistor and the fourth test transistor are arranged in alignment in the second direction, the second test transistor and the fifth test transistor are arranged in alignment in the second direction, and the third test transistor and the sixth test transistor are arranged in alignment in the second direction.

[0032] In some example embodiments, m is 8. Each group of test circuits comprises two first test circuits and two second test circuits; wherein one first test circuit, two second test circuits and one first test circuit are arranged along the second direction.

[0033] In some example embodiments, m is 12. Each group of test circuits comprises three first test circuits and three second test circuits; wherein one first test circuit, two second test circuits, two first test circuits and one second test circuit are arranged along the second direction; or one first test circuit, one second test circuit, one first test circuit, two second test circuits and one first test circuit are arranged along the reverse direction of the second direction.

[0034] In some example embodiments, m is 16. Each group of test circuits comprises four first test circuits and four second test circuits; wherein one first test circuit, two second test circuits, one first test circuit, one second test circuit, two first test circuits and one second test circuit are arranged along the second direction; or one first test circuit, one second test circuit, one first test circuit, two second test circuits, one first test circuit, one second test circuit and one first test circuit are arranged along the reverse direction of the second direction.

[0035] In some example embodiments, m is 20. Each group of test circuits comprises five first test circuits and five second test circuits; wherein one first test circuit, two second test circuits, one first test circuit, one second test circuit, one first test circuit, one second test circuit, two first test circuits and one second test circuit are arranged along the second direction; or one first test circuit, one second test circuit, one first test circuit, one second test circuit, one first test circuit, two second test circuits, one first test circuit, one second test circuit and one first test circuit are arranged along the reverse direction of the second direction.

[0036] Other aspects can become apparent upon reading the following detailed description and upon understanding the appended claims.

[0037] Overview of the attached figures

[0038] The accompanying drawings are provided to further understand the technical solutions of this disclosure and constitute a part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0039] Figure 1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0040] Figure 2 is a schematic diagram of the first border region of at least one embodiment of the present disclosure;

[0041] Figure 3A is a partial cross-sectional schematic diagram of the display area of ​​at least one embodiment of the present disclosure;

[0042] Figure 3B is another partial cross-sectional schematic diagram of the display area of ​​at least one embodiment of the present disclosure;

[0043] Figure 4 is a schematic diagram of the arrangement of sub-pixels in a display area according to at least one embodiment of the present disclosure;

[0044] Figure 5 is a partial wiring diagram of the first border region of at least one embodiment of the present disclosure;

[0045] Figure 6 is a schematic diagram of multiple sets of first-side first transition units according to at least one embodiment of the present disclosure;

[0046] Figure 7A is a schematic diagram of the first gate metal layer and the second gate metal layer in Figure 6;

[0047] Figure 7B is a schematic diagram of the first source / drain metal layer in Figure 6;

[0048] Figure 7C is a schematic diagram of the second source / drain metal layer in Figure 6;

[0049] Figure 8 is a partial cross-sectional view along the Q-Q' direction in Figure 6;

[0050] Figures 9A and 9B are schematic diagrams illustrating the interpolation principle of the data signals transmitted at the second connection end of the first transition unit on the first side shown in Figure 6.

[0051] Figure 10 is a schematic diagram of multiple sets of second-side first transition units according to at least one embodiment of the present disclosure;

[0052] Figure 11 is a schematic diagram of the data signal interpolation principle transmitted by the second connection end of the first adapter unit on the second side shown in Figure 10;

[0053] Figure 12 is a schematic diagram of a group of first-side second transition units according to at least one embodiment of the present disclosure;

[0054] Figure 13 is an equivalent circuit diagram of the first test circuit and the second test circuit of at least one embodiment of the present disclosure;

[0055] Figure 14A is a plan view of the first set of test circuits according to at least one embodiment of the present disclosure;

[0056] Figure 14B is a schematic diagram of the first source / drain metal layer in Figure 14A;

[0057] Figure 14C is a schematic diagram of the first semiconductor layer, the first gate metal layer and the second gate metal layer in Figure 14A;

[0058] Figure 15 is an equivalent circuit diagram of the third test circuit of at least one embodiment of the present disclosure;

[0059] Figure 16 is another schematic diagram of a set of first-side first-transition units according to at least one embodiment of the present disclosure;

[0060] Figure 17 is a schematic diagram of the first gate metal layer and the second gate metal layer in Figure 16;

[0061] Figure 18 is a schematic diagram of the data signal interpolation principle transmitted at the second connection end of the first transition unit on the first side shown in Figure 16.

[0062] Figure 19 is a schematic diagram of a group of first-side second transition units according to at least one embodiment of the present disclosure;

[0063] Figure 20 is a plan view of the first set of test circuits according to at least one embodiment of the present disclosure;

[0064] Figure 21 is a schematic diagram of a set of second-side first transition units according to at least one embodiment of the present disclosure;

[0065] Figure 22 is a schematic diagram of the data signal interpolation principle transmitted by the second connection end of the first adapter unit on the second side shown in Figure 21;

[0066] Figure 23 is a plan view of the second set of test circuits according to at least one embodiment of the present disclosure;

[0067] Figure 24 is another schematic diagram of a set of first-side first transition units according to at least one embodiment of the present disclosure;

[0068] Figure 25 is a schematic diagram of the data signal interpolation principle transmitted at the second connection end of the first transition unit on the first side shown in Figure 24.

[0069] Figure 26 is a plan view of the first set of test circuits corresponding to the first set of first-side first-transfer units shown in Figure 24;

[0070] Figure 27 is a schematic diagram of a group of second-side first transition units according to at least one embodiment of the present disclosure;

[0071] Figure 28 is a schematic diagram of the data signal interpolation principle transmitted by the second connection end of a set of second-side first adapter units shown in Figure 27;

[0072] Figure 29 is a plan view of the second set of test circuits according to at least one embodiment of the present disclosure;

[0073] Figure 30 is another schematic diagram of a set of first-side first transition units according to at least one embodiment of the present disclosure;

[0074] Figure 31 is a schematic diagram of the data signal interpolation principle transmitted by the second connection end of the first transition unit on the first side shown in Figure 30.

[0075] Figure 32 is a plan view of the first set of test circuits corresponding to the first set of first transition units on the first side shown in Figure 30;

[0076] Figure 33 is a schematic diagram of a set of second-side first transition units according to at least one embodiment of the present disclosure;

[0077] Figure 34 is a schematic diagram of the data signal interpolation principle transmitted by the second connection end of the first adapter unit on the second side shown in Figure 33.

[0078] Figure 35 is a plan view of the second set of test circuits according to at least one embodiment of the present disclosure;

[0079] Figures 36A to 36C are example diagrams showing the connection method of a plurality of first switching units according to at least one embodiment of the present disclosure;

[0080] Figure 37 is a schematic diagram of another arrangement of sub-pixels in the display area of ​​at least one embodiment of the present disclosure;

[0081] Figures 38A to 38F are example diagrams illustrating the connection method of a plurality of first switching units according to at least one embodiment of the present disclosure;

[0082] Figure 39 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.

[0083] Detailed Explanation

[0084] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. The implementation can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into other forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0085] In the accompanying drawings, the size of one or more constituent elements, the thickness of layers, or areas are sometimes exaggerated for clarity. Therefore, this disclosure is not necessarily limited to these dimensions, and the shape and size of one or more parts in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0086] The ordinal numbers such as "first," "second," and "third" used in this specification are used to avoid confusion among the constituent elements, not to limit the quantity. The term "multiple" in this disclosure refers to two or more quantities.

[0087] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of the constituent elements being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0088] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or joint; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this disclosure as appropriate. "Joining" can include "electrical connection," which can include situations where constituent elements are connected together by a component having some electrical function. There are no particular limitations on "components having some electrical function," as long as they enable the transmission of electrical signals between the connected constituent elements. Examples of "components having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other multifunctional components.

[0089] In this specification, a transistor is a device that includes at least three terminals: a gate (gate electrode), a drain, and a source. A transistor has a channel region between its drain (drain electrode terminal, drain region, or drain electrode) and its source (source electrode terminal, source region, or source electrode), and current can flow through the drain, the channel region, and the source. In this specification, the channel region refers to the region through which current primarily flows.

[0090] In this specification, the first terminal can be the drain and the second terminal can be the source, or vice versa. Additionally, the gate can also be called the control terminal. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged. Therefore, in this specification, the "source" and "drain" can be interchanged.

[0091] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0092] In this specification, circles, ellipses, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined. They can be approximate circles, ellipses, triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, such as chamfers, curved edges, and other variations.

[0093] In this specification, "approximately" and "about" mean without strictly defined limits, allowing for errors in the process and measurement. In this disclosure, "same" includes values ​​differing by less than 10%, such as values ​​differing by less than 5%.

[0094] In this specification, "A extends along direction B" means that A may include a main part and a secondary part connected to the main part. The main part is a line, line segment, or strip-shaped solid. The main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions. In this specification, "A extends along direction B" refers to "the main part of A extends along direction B".

[0095] The phrase "A and B are of the same layer" in this specification means that A and B are formed simultaneously through the same drafting process. "Same layer" does not always mean that the layer thickness or layer height is the same in the cross-sectional view. "The orthographic projection of A includes the orthographic projection of B" means that the orthographic projection of B falls within the orthographic projection area of ​​A, or the orthographic projection of A covers the orthographic projection of B.

[0096] Figure 1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 1, the display substrate can be a closed polygon including linear edges. The display substrate may include a display area AA and a border area BB surrounding the display area AA. For example, the display area AA may include a first display edge (lower display edge) and a second display edge (upper display edge) disposed opposite to each other in a first direction D1, and a third display edge (left display edge) and a fourth display edge (right display edge) disposed opposite to each other in a second direction D2. The first and second display edges can be mutually parallel linear edges, and the third and fourth display edges can be mutually parallel linear edges. Adjacent linear edges can be connected by curved edges (e.g., arcuate edges).

[0097] In some examples, as shown in Figure 1, the border area BB may include: a first border area B1 and a fourth border area B4 located on both sides of the display area AA along a first direction D1, and a second border area B2 and a third border area B3 located on both sides of the display area AA along a second direction D2. The first border area B1 may connect to a first display edge, the second border area B2 may connect to a third display edge, the third border area B3 may connect to a fourth display edge, and the fourth border area B4 may connect to a second display edge. The first border area B1 may communicate with the second border area B2 and the third border area B3, and the third border area B4 may communicate with the second border area B2 and the third border area B3. After the first border area B1, the second border area B2, the third border area B3, and the fourth border area B4 are connected, they can surround the display area AA. For example, the first border area B1 may also be called the lower border area of ​​the display substrate, the second border area B2 may also be called the left border area of ​​the display substrate, the third border area B3 may also be called the right border area of ​​the display substrate, and the fourth border area B4 may also be called the upper border area of ​​the display substrate. However, this embodiment is not limited in this respect.

[0098] Figure 2 is a schematic diagram of a first border region according to at least one embodiment of the present disclosure. In some examples, as shown in Figures 1 and 2, the first border region B1 may include: a first sub-region B11, a bent region B12, and a second sub-region B13 arranged sequentially along the side away from the display region AA in a first direction D1. The first sub-region B11 may also be referred to as a first fan-out region. The first sub-region B11 may communicate with the second border region B2 and the third border region B3, and be connected to the display region AA. The bent region B12 may connect the first sub-region B11 and the second sub-region B13. The bent region B12 may be configured to bend the second sub-region B13 to the back side of the display region AA.

[0099] In some examples, as shown in Figure 2, the second sub-region B13 of the first border region B1 may include: a second fan-out region B131, a circuit setting region B132, a third fan-out region B133, a first signal access region B134, and a second signal access region B135, sequentially arranged along the direction away from the bending region B12 in the first direction D1. The area of ​​the first signal access region B134 near the display region AA may also be referred to as the trace lead-out region. The trace lead-out region in this example may include: the first sub-region B11, the bending region B12, the second fan-out region B131, the circuit setting region B132, and the third fan-out region B133. However, this embodiment is not limited to this.

[0100] In some examples, the circuit setup area B132 may include multiple test circuits configured to provide test data signals to the data lines of the display area AA. In other examples, the circuit setup area may also include multiple electrostatic discharge circuits configured to prevent electrostatic damage to the display substrate by eliminating static electricity. This embodiment is not limited in this respect.

[0101] In some examples, the first signal access area B134 may be provided with a plurality of first contact pads, which may be configured to connect to an integrated circuit (IC). The second signal access area B135 may be provided with a plurality of second contact pads, which may be configured to bond to an external flexible printed circuit board (FPC). At least one first contact pad in the first signal access area B134 and at least one second contact pad in the second signal access area B135 may be connected by wiring.

[0102] In some examples, as shown in Figure 1, the display area AA of the display substrate may include at least: multiple sub-pixels PX, multiple gate lines GL, and multiple data lines (e.g., multiple first data lines DLa and multiple second data lines DLb). The multiple gate lines GL may extend along a second direction D2 and be arranged along a first direction D1; the multiple data lines may extend along the first direction D1 and be arranged along the second direction D2. For example, the multiple first data lines DLa may be located outside the multiple second data lines DLb in the second direction D2. The multiple data lines may be electrically connected to the multiple sub-pixels PX and may be configured to provide data signals to the multiple sub-pixels PX. The multiple gate lines GL may be electrically connected to the multiple sub-pixels PX and may be configured to provide pixel control signals to the multiple sub-pixels PX. For example, the pixel control signals may include scan signals, or may include scan signals and light emission control signals, or may include scan signals, reset control signals, and light emission control signals.

[0103] In some examples, the second direction D2 can be the extension direction of the grid lines GL within the display area AA (e.g., the row direction); the first direction D1 can be the extension direction of the data lines within the display area AA (e.g., the column direction). The first direction D1 and the second direction D2 can intersect each other, for example, they can be perpendicular to each other.

[0104] In some examples, the display area AA may also be provided with multiple data connection lines 25. A first data line DLa can be connected to a first data lead-out line of the first sub-region B11 via the data connection line 25. A second data line DLb can extend directly to the first sub-region B11 and connect to the first data lead-out line of the first sub-region B11. The data connection line 25 may include a first data connection segment 251 extending along a second direction D2 and a second data connection segment 252 extending along a first direction D1. The first data connection segment 251 can be connected between the first data line DLa and the second data connection segment 252, and the second data connection segment 252 can be connected to the first data lead-out line of the first sub-region B11. The second data connection segment 252 may be located on the side of the connected first data line DLa away from the edge of the display substrate. In some examples, the first data connection segment 251 and the second data connection segment 252 may be located on the side of the first data line DLa and the second data line DLb away from the substrate. However, this embodiment is not limited to this. By setting a data connection line within the display area, so that the first data lead-out line in the first sub-area is connected to the first data line through the data connection line, the length of the first sub-area along the first direction can be effectively reduced, thereby greatly reducing the size of the bottom bezel.

[0105] In some examples, a pixel unit of the display area AA may include three sub-pixels, which may be a first sub-pixel emitting a first color light (e.g., red light), a second sub-pixel emitting a second color light (e.g., blue light), and a third sub-pixel emitting a third color light (e.g., green light). However, this embodiment is not limited to this. In some examples, a pixel unit may include four sub-pixels, which may be a sub-pixel emitting red light, a sub-pixel emitting green light, a sub-pixel emitting blue light, and a sub-pixel emitting white light. For example, a pixel unit may include four sub-pixels, which may include one sub-pixel emitting red light, one sub-pixel emitting blue light, and two sub-pixels emitting green light.

[0106] In some examples, a sub-pixel may include a pixel circuit and a light-emitting element electrically connected to the pixel circuit. The pixel circuit may include multiple transistors and at least one capacitor. For example, the pixel circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. In these circuit structures, T refers to a thin-film transistor, C refers to a capacitor, the number before T represents the number of thin-film transistors in the circuit, and the number before C represents the number of capacitors in the circuit. In some examples, the multiple transistors in the pixel circuit may include P-type transistors and N-type transistors. In other examples, the multiple transistors in the pixel circuit may be either P-type transistors or N-type transistors. Using the same type of transistors in the pixel circuit simplifies the process flow, reduces the processing difficulty of the display substrate, and improves product yield.

[0107] In some examples, the shape of the light-emitting element of a sub-pixel can be rectangular, rhomboid, pentagonal, or hexagonal. When a pixel unit includes three sub-pixels, the light-emitting elements of the three sub-pixels can be arranged horizontally side-by-side, vertically side-by-side, or in a triangular arrangement; when a pixel unit includes four sub-pixels, the light-emitting elements of the four sub-pixels can be arranged horizontally side-by-side, vertically side-by-side, or in a square arrangement. However, this embodiment is not limited in this respect.

[0108] In some examples, the light-emitting element can be any of the following: a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), or a micro-LED (including mini-LED or micro-LED). For example, the light-emitting element can be an OLED, which can emit red, green, blue, or white light under the drive of its corresponding pixel circuit. The color of the light emitted by the light-emitting element can be determined as needed. In some examples, the light-emitting element may include an anode, a cathode, and an organic light-emitting layer located between the anode and cathode. The anode of the light-emitting element can be electrically connected to the corresponding pixel circuit. However, this embodiment is not limited in this respect.

[0109] Figure 3A is a partial cross-sectional schematic diagram of a display area according to at least one embodiment of the present disclosure. Figure 3A illustrates the structure of a sub-pixel of the display area as an example. In this example, the pixel circuit includes a low-temperature polysilicon thin-film transistor and an oxide thin-film transistor.

[0110] In some examples, as shown in FIG3A, in a direction perpendicular to the display substrate, the display area of ​​the display substrate may include at least: a substrate 10, and a circuit structure layer 12, a light-emitting structure layer 13, and an encapsulation structure layer 14 sequentially disposed on the substrate 10. The circuit structure layer 12 may include at least: pixel circuits for multiple sub-pixels, and the pixel circuit for each sub-pixel may include multiple transistors and at least one capacitor. The light-emitting structure layer 13 may include at least: light-emitting elements for multiple sub-pixels. In other examples, the display substrate may also include a touch structure layer located on the side of the encapsulation structure layer away from the substrate.

[0111] In some examples, Figure 3A illustrates a subpixel comprising a first-type transistor 21, a second-type transistor 22, and a capacitor 23. The first-type transistor 21 can be a low-temperature polycrystalline silicon thin-film transistor, and the second-type transistor 22 can be an oxide thin-film transistor.

[0112] In some examples, the circuit structure layer 12 of the display area may include: a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, a first source / drain metal layer, and a second source / drain metal layer disposed on the substrate 10. A first insulating layer 101 may be disposed between the first semiconductor layer and the first gate metal layer; a second insulating layer 102 may be disposed between the first gate metal layer and the second gate metal layer; a third insulating layer 103 may be disposed between the second gate metal layer and the second semiconductor layer; a fourth insulating layer 104 may be disposed between the second semiconductor layer and the third gate metal layer; a fifth insulating layer 105 may be disposed between the third gate metal layer and the first source / drain metal layer; a sixth insulating layer 106 (also referred to as a passivation layer) and a seventh insulating layer 107 (also referred to as a first planarization layer) may be disposed between the first source / drain metal layer and the second source / drain metal layer, wherein the seventh insulating layer 107 may be located on the side of the sixth insulating layer 106 away from the substrate 10; an eighth insulating layer 108 (also referred to as a second planarization layer) may be disposed on the side of the second source / drain metal layer away from the substrate 10. In this embodiment, the first insulating layer 101, the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104, the fifth insulating layer 105, and the sixth insulating layer 106 can be inorganic insulating layers, while the seventh insulating layer 107 and the eighth insulating layer 108 can be organic insulating layers. However, this embodiment is not limited to these. In other examples, a buffer layer can also be provided on the side of the first semiconductor layer near the substrate. The buffer layer can prevent harmful substances in the substrate from penetrating into the interior of the display substrate and can also increase the adhesion of the film layers in the display substrate to the substrate. In other examples, a bottom shielding metal layer (BSM) can also be provided on the side of the buffer layer near the substrate. The bottom shielding metal layer can be configured to at least partially cover the active layer of the transistors in the pixel circuit to avoid external light affecting the performance of the transistors. In other examples, the sixth insulating layer can be omitted between the first source / drain metal layer and the second source / drain metal layer, and only the seventh insulating layer can be provided between the first source / drain metal layer and the second source / drain metal layer.

[0113] In some examples, as shown in FIG3A, the first semiconductor layer of the display area may include at least: a first active layer 210 of a first type transistor 21. The first active layer 210 of the first type transistor 21 may include: a first region 2101, a second region 2102, and a channel region 2100 located between the first region 2101 and the second region 2102. The first gate metal layer may include at least: a first gate 213 of the first type transistor 21, and a first electrode 231 of the capacitor 23. The orthographic projection of the first gate 213 of the first type transistor 21 onto the substrate 10 may cover the orthographic projection of the channel region 2100 of the first active layer 210 onto the substrate 10. The second gate metal layer may include at least: a second electrode 232 of the capacitor 23, and a third gate 224 of the second type transistor 22. The orthographic projections of the second electrode 232 and the first electrode 231 of the capacitor 23 onto the substrate 10 may at least partially overlap, for example, they may coincide. The second semiconductor layer may include at least: a second active layer 220 of the second type transistor 22. The third gate metal layer may include at least: a second gate 223 of the second type transistor 22. The orthographic projection of the second gate 223 of the second type transistor 22 onto the substrate 10 may partially overlap with the orthographic projection of the second active layer 220 onto the substrate 10. The orthographic projection of the third gate 224 of the second type transistor 22 onto the substrate 10 may partially overlap with the orthographic projection of the second active layer 220 onto the substrate 10. The third gate 224 may be the bottom gate of the second type transistor 22, and the second gate 223 may be the top gate of the second type transistor 22.

[0114] In some examples, as shown in FIG3A, the first source-drain metal layer of the display area may include at least: a first source 211 and a first drain 212 of a first type transistor 21, and a second source 221 and a second drain 222 of a second type transistor 22. The fifth insulating layer 105 may have multiple pixel vias (e.g., including a first pixel via, a second pixel via, a third pixel via, and a fourth pixel via) in the display area. The fifth insulating layer 105, the fourth insulating layer 104, the third insulating layer 103, the second insulating layer 102, and the first insulating layer 101 in the first pixel via can be removed, exposing at least a portion of the surface of the first region 2101 of the first active layer 210; the fifth insulating layer 105, the fourth insulating layer 104, the third insulating layer 103, the second insulating layer 102, and the first insulating layer 101 in the second pixel via can be removed, exposing at least a portion of the surface of the second region 2102 of the first active layer 210. The fifth insulating layer 105, the fourth insulating layer 104, and the third insulating layer 103 within the third and fourth pixel vias can be removed, exposing at least a portion of the surface at both ends of the second active layer 220. The first source 211 of the first type transistor 21 can be electrically connected to the first region 2101 of the first active layer 210 through the first pixel via, and the first drain 212 can be electrically connected to the second region 2102 of the first active layer 210 through the second pixel via. The second source 221 of the second type transistor 22 can be electrically connected to one end of the second active layer 220 through the third pixel via, and the second drain 222 of the second type transistor 22 can be electrically connected to the other end of the second active layer 220 through the fourth pixel via. The second source-drain metal layer may include at least a first transition electrode 241. The first transition electrode 241 can be electrically connected to the first drain 212 of the first type transistor 21 in the pixel circuit through the fifth pixel via formed by the sixth insulating layer 106 and the seventh insulating layer 107. This example demonstrates the electrical connection between the pixel circuit and the light-emitting element via the first adapter electrode 241.

[0115] In some examples, the gate lines of the display area may be located, for example, in the first and third gate metal layers; the data lines of the display area may be located, for example, in the second source-drain metal layer; the first power lines of the display area may be located, for example, in the second source-drain metal layer; the first data connection segment of the data connection line of the display area may be located, for example, in the first source-drain metal layer; and the second data connection segment may be located, for example, in the second source-drain metal layer. This embodiment is not limited in this respect. In other examples, the circuit structure layer of the display area may further include a third source-drain metal layer located on the side of the second source-drain metal layer away from the substrate, and the data connection lines may be located in the third source-drain metal layer.

[0116] In some examples, as shown in Figure 3A, the light-emitting structure layer 13 may include a pixel definition layer 134 and multiple light-emitting elements. For example, each light-emitting element may include a stacked first electrode 131, an organic light-emitting layer 132, and a second electrode 133. The first electrode 131 of the light-emitting element can be an anode, and the first electrode 131 can be disposed on an eighth insulating layer 108 and electrically connected to a first transition electrode 241 through a sixth pixel via formed in the eighth insulating layer 108. The pixel definition layer 134 is disposed on the first electrode 131 and the eighth insulating layer 108, and the pixel definition layer 134 may have multiple pixel openings, one pixel opening exposing at least a portion of the surface of a corresponding first electrode 131. At least a portion of the organic light-emitting layer 132 can be disposed within a pixel opening and connected to the corresponding first electrode 131. The second electrode 133 can be disposed on the organic light-emitting layer 132 and connected to the organic light-emitting layer 132. The organic light-emitting layer 132 can emit light of a corresponding color under the drive of the first electrode 131 and the second electrode 133.

[0117] In some examples, the organic light-emitting layer 132 of the light-emitting element may include an emitting layer (EML) and at least one of the following film layers: a hole injection layer (HIL), a hole transport layer (HTL), a hole block layer (HBL), an electron block layer (EBL), an electron injection layer (EIL), and an electron transport layer (ETL). Under the voltage drive of the first electrode 131 and the second electrode 133, the light-emitting properties of the organic material can be utilized to emit light at the required grayscale.

[0118] In some examples, the light-emitting layers of different colored light-emitting elements can be different. For example, a red light-emitting element includes a red light-emitting layer, a green light-emitting element includes a green light-emitting layer, and a blue light-emitting element includes a blue light-emitting layer. To reduce process complexity and improve yield, the hole injection layer and hole transport layer on one side of the light-emitting layer can be common layers, as can the electron injection layer and electron transport layer on the other side. In some examples, any one or more of the hole injection layer, hole transport layer, electron injection layer, and electron transport layer can be fabricated in a single process (single vapor deposition process or single inkjet printing process), and isolation can be achieved through surface steps of the formed film layers or through surface treatment. For example, any one or more of the hole injection layer, hole transport layer, electron injection layer, and electron transport layer corresponding to adjacent sub-pixels can be isolated. In some examples, the organic light-emitting layer can be formed by vapor deposition using a fine metal mask (FMM) or an open mask, or by inkjet printing.

[0119] In some examples, as shown in Figure 3A, the encapsulation structure layer 14 may include a first encapsulation layer 141, a second encapsulation layer 142, and a third encapsulation layer 143 stacked together. The first and third encapsulation layers 141 and 143 may be made of inorganic materials, such as silicon nitride, silicon oxide, or silicon oxynitride. Inorganic materials have high density, preventing the intrusion of water, oxygen, etc. The second encapsulation layer 142 may be disposed between the first and third encapsulation layers 141 and 143 to ensure that external moisture cannot enter the light-emitting element. The second encapsulation layer 142 may be made of organic materials, such as polymer materials containing desiccants or polymer materials that can block moisture, or polymer resins to planarize the surface of the display substrate and relieve stress on the first and third encapsulation layers 141 and 143. It may also include water-absorbing materials such as desiccants to absorb water, oxygen, and other substances that have intruded into the interior. However, this embodiment is not limited to these limitations. For example, the encapsulation structure layer may employ a five-layer stacked structure of inorganic / organic / inorganic / organic / inorganic.

[0120] Figure 3B is another partial cross-sectional schematic diagram of the display area according to at least one embodiment of the present disclosure. In some examples, the transistor types of the multiple pixel transistors in the pixel circuit can be the same, for example, they can all be low-temperature polycrystalline silicon thin-film transistors. Figure 3B illustrates an example of each sub-pixel including a first-type transistor 21 and a capacitor 23.

[0121] In some examples, as shown in FIG3B, the circuit structure layer 12 of the display area may include: a first semiconductor layer, a first gate metal layer, a second gate metal layer, a first source / drain metal layer, and a second source / drain metal layer disposed on the substrate 10. A first insulating layer 101 may be disposed between the first semiconductor layer and the first gate metal layer; a second insulating layer 102 may be disposed between the first gate metal layer and the second gate metal layer; a third insulating layer 103 may be disposed between the second gate metal layer and the first source / drain metal layer; a sixth insulating layer 106 and a seventh insulating layer 107 may be disposed between the first source / drain metal layer and the second source / drain metal layer; and an eighth insulating layer 108 may be disposed on the side of the second source / drain metal layer away from the substrate 10. The seventh insulating layer 107 and the eighth insulating layer 108 may be organic insulating layers, and the first insulating layer 101, the second insulating layer 102, and the third insulating layer 103 may be inorganic insulating layers. The remaining structure of the display area of ​​the display substrate of this example can be referred to the description of the embodiment shown in FIG3A, and will not be repeated here.

[0122] With the widespread application of OLED display technology, consumers have placed higher demands on OLED display products, with high-resolution (PPI) displays and narrow-bezel displays becoming new trends in display product development. To achieve narrow bezels, data connection lines are placed in the display area, allowing data leads in the first bezel area to connect to the first data line, effectively reducing the length of the first sub-area and thus significantly reducing the size of the bottom bezel. However, during the process of connecting the first data line via the data connection line, the order of the data leads in the first bezel area is disrupted, resulting in a different order than the data lines in the display area. In some implementations, to ensure compatibility with conventional integrated circuits, jumper designs are required in the first bezel area (e.g., the second fan-out area) to ensure that the data signals transmitted by the data contact pads in the first signal access area are in the same order as the data lines in the display area. However, jumpers placed in the second fan-out area are prone to causing various problems: for example, some jumpers in the second fan-out area may overlap with other data leads or power lines, which may cause sudden changes in data signal load and difficulty in resistance compensation; also, due to the space limitations of the second fan-out area, the wiring of jumpers in the second fan-out area is dense and the gaps are small, which may cause metal material etching residue, resulting in short circuits.

[0123] This embodiment provides a display substrate, including: a substrate, multiple sub-pixels, multiple first data lines, multiple second data lines, multiple data transfer lines, multiple data lead-out lines, multiple data contact pads, multiple sets of first transfer units, and multiple sets of second transfer units. The substrate includes a display area and a first border area located on one side of the display area along a first direction. The first border area includes: a first signal access area and a trace lead-out area located between the first signal access area and the display area. Multiple sub-pixels are disposed on one side of the substrate and located within the display area. Multiple first data lines, multiple second data lines, and multiple data connection lines are located within the display area; the multiple first data lines and the multiple second data lines are configured to provide data signals to the multiple sub-pixels, and the multiple first data lines are connected to the multiple data connection lines. Multiple data lead-out lines are located within the trace lead-out area. Multiple data contact pads are located within the first signal access area. Multiple sets of first adapter units and multiple sets of second adapter units are located in the trace lead-out area. The multiple sets of first adapter units are located on the side of the multiple sets of second adapter units away from the display area. The multiple sets of first adapter units are arranged along a second direction, and the multiple sets of second adapter units are also arranged along a second direction. The second direction intersects the first direction; for example, the second direction can be perpendicular to the first direction. Multiple data lead-out lines are connected to the multiple data contact pads through the multiple sets of first adapter units, and are also connected to the multiple second data lines and the multiple data connection lines through the multiple sets of second adapter units, such that the order of the data signals provided by the multiple data contact pads matches the order of the data signals required by the multiple second data lines and the multiple data connection lines arranged along the second direction.

[0124] The display substrate provided in this embodiment connects multiple data leads and multiple data contact pads through multiple sets of first adapter units, and connects multiple data leads to multiple second data lines and multiple data connection lines through multiple sets of second adapter units. This allows the order of data signals transmitted by the multiple data contact pads to match the order of data signals required by the multiple second data lines and multiple data connection lines. This avoids the need for jumper design in the second fan-out area, reduces defects caused by jumper design, and improves the reliability of the display substrate.

[0125] In some examples, the order of data signals provided by multiple data contact pads can be adapted to the arrangement of the second data lines and data connection lines in the display area. The data signals provided by the multiple data contact pads have a first order, which changes after passing through multiple sets of first conversion units, for example, having a second order, and then changes again after passing through multiple sets of second conversion units, for example, returning to the first order, so that the second data lines and data connection lines in the display area can receive the required data signals.

[0126] In some exemplary embodiments, each group of first adapter units includes: m first connection terminals, m second connection terminals, and m first adapter cables; each first adapter cable connects between a first connection terminal and a second connection terminal; each first connection terminal is connected to a data lead-out line, and each second connection terminal is connected to a data contact pad; the m first connection terminals are arranged along the second direction and correspond to different first arrangement numbers, and the m second connection terminals are arranged along the second direction and correspond to different second arrangement numbers. The m first adapter cables in each group of first adapter units include: a sequence adapter cables, where the first arrangement number corresponding to the first connection terminal connected to each sequence adapter cable is different from the second arrangement number corresponding to the second connection terminal connected to it; wherein m and a are both integers greater than 1, and m is greater than or equal to a. In some examples, a first adapter unit may include: a first connection terminal, a first adapter cable, and a second connection terminal connected sequentially, and a first adapter unit can realize the transmission of one data signal between the data contact pad and the data lead-out line. In some examples, a second adapter unit may include a second adapter cable. A second adapter unit can transmit one data signal between a data lead and a second data line or data connection line. The display substrate provided in this embodiment, by setting multiple sets of first adapter units to connect multiple data leads and multiple data contact pads, can utilize multiple sets of first adapter units to adjust the order of data signals transmitted by the data contact pads. Simultaneously, by coordinating multiple sets of second adapter units to adjust the order of data signals, the jumper design in the second fan-out area can be avoided, which helps reduce defects caused by jumper design and thus improves the reliability of the display substrate.

[0127] In some exemplary embodiments, a single pixel unit of the display area may include: c sub-pixels, where m is a multiple of c, and k is an integer greater than 1. For example, a pixel unit may include four sub-pixels, where m can be an integer multiple of 4, such as 8, 12, 16, or 20; a pixel unit may include three sub-pixels, where m can be an integer multiple of 3, such as 6, 9, 12, or 15.

[0128] In some exemplary embodiments, the 'a' insertion sequence adapter lines in each group of first adapter units may include: a1 first insertion sequence adapter lines and a2 second insertion sequence adapter lines, where a1 and a2 are both integers greater than 0, and the sum of a1 and a2 is 'a'. The first row number corresponding to the first connection terminal connected to the first insertion sequence adapter line is less than the second row number corresponding to the second connection terminal connected to it; the first row number corresponding to the first connection terminal connected to the second insertion sequence adapter line is greater than the second row number corresponding to the second connection terminal connected to it. In some examples, the difference between the second row number corresponding to the second connection terminal connected to the first insertion sequence adapter line and the first row number corresponding to the first connection terminal connected to it may be greater than or equal to the difference between the first row number corresponding to the first connection terminal connected to the second insertion sequence adapter line and the second row number corresponding to the second connection terminal connected to it. This example adjusts the data signal transmission order by setting first and second insertion sequence adapter lines in each group of first adapter units, which avoids jumper design in the second fan-out area, helps reduce the defects caused by jumper design, and thus improves the reliability of the display substrate.

[0129] In some exemplary embodiments, the m first adapter lines within each group of first adapter units may further include: b first sequential adapter lines, wherein the first row number corresponding to the first connection terminal connected to each first sequential adapter line is the same as the second row number corresponding to the second connection terminal connected to it; b is an integer greater than 1, and b is less than or equal to a. In some examples, the b sequential adapter lines and the first insertion sequence adapter lines may be in the same layer, or at least one first sequential adapter line may be located on the side of the first insertion sequence adapter line and the second insertion sequence adapter line closer to the substrate. This example, by utilizing the cooperation of the first sequential adapter lines and the insertion sequence adapter lines within each group of first adapter units to adjust the transmission order of data signals, can avoid jumper design in the second fan-out area, which helps to reduce the defects caused by jumper design, thereby improving the reliability of the display substrate.

[0130] In some exemplary embodiments, m can be 8, and each group of first adapter units can include two first sequence adapter cables, two second sequence adapter cables, and four first order adapter cables. The first sequence adapter cable can be configured to connect the i-th first connection terminal to the (i+1)-th second connection terminal; the second sequence adapter cable can be configured to connect the (i+1)-th first connection terminal to the i-th second connection terminal; wherein the value of i can be 1 or 5.

[0131] In some exemplary embodiments, m can be 12, and each group of first adapter units can include four first sequence adapter cables, four second sequence adapter cables, and four first order adapter cables. The first sequence adapter cables can be configured to connect the i-th first connection terminal to the (i+1)-th second connection terminal; the second sequence adapter cables can be configured to connect the (i+1)-th first connection terminal to the i-th second connection terminal; wherein the value of i can be 1, 3, 7, or 9.

[0132] In some exemplary embodiments, m can be 16, and each group of first adapter units can include four first sequence adapter cables, four second sequence adapter cables, and eight first order adapter cables. The first sequence adapter cables can be configured to connect the i-th first connection terminal to the (i+1)-th second connection terminal; the second sequence adapter cables can be configured to connect the (i+1)-th first connection terminal to the i-th second connection terminal; wherein the value of i can be 1, 3, 9, or 11.

[0133] In some exemplary embodiments, m can be 20, and each group of first adapter units can include six first-order adapter cables, six second-order adapter cables, and eight first-sequence adapter cables. The first-order adapter cables can be configured to connect the i-th first connection terminal to the (i+1)-th second connection terminal; the second-order adapter cables can be configured to connect the (i+1)-th first connection terminal to the i-th second connection terminal; wherein the value of i can be 1, 3, 5, 11, 13, or 15.

[0134] In some exemplary embodiments, a pixel unit located in the display area includes: a first sub-pixel emitting a first color light, a second sub-pixel emitting a second color light, and two third sub-pixels emitting a third color light. Multiple data leads connected to the first connection terminals of the multiple sets of first adapter units may include: a first set of data leads and a second set of data leads. The first set of data leads and the second set of data leads are located in different conductive layers and are alternately arranged along the second direction. The first set of data leads is configured to transmit the data signal required by the third sub-pixel, and the second set of data leads is configured to transmit the data signals required by the first sub-pixel and the second sub-pixel. For example, the data signal corresponding to the third sub-pixel (e.g., green sub-pixel G) can be transmitted by a data lead located in the first gate metal layer, and the data signals corresponding to the first sub-pixel (e.g., red sub-pixel R) and the second sub-pixel (e.g., blue sub-pixel B) can be transmitted by a data lead located in the second gate metal layer. This ensures the uniformity of the signal transmission traces and avoids load differences caused by arranging the data leads transmitting the data signal corresponding to the third sub-pixel in different conductive layers, which would affect the display effect.

[0135] In some exemplary embodiments, the display substrate may further include: multiple sets of test circuits located in the trace lead-out area and arranged sequentially along a second direction. The multiple sets of test circuits may be located on the side of the multiple sets of first transition units away from the first signal access area in the first direction. Each set of test circuits is connected to m data leads connected to a set of first transition units. Each set of test circuits may include: a first test circuits and b second test circuits; the sum of a and b is twice m, and both a and b are integers greater than 0. The first test circuit may include: a first test transistor, a second test transistor, and a third test transistor. The gate of the first test transistor is connected to a first test control line, and the first electrode of the first test transistor is connected to a first test data line. The gate of the second test transistor is connected to a second test control line, and the first electrode of the second test transistor is connected to a second test data line. The second electrodes of the first and second test transistors are connected to the same data lead. The gate of the third test transistor is connected to a third test control line, and the first electrode of the third test transistor is connected to a third test data line. The second test circuit may include: a fourth test transistor, a fifth test transistor, and a sixth test transistor. The gate of the fourth test transistor is connected to the second test control line, and the first terminal of the fourth test transistor is connected to the first test data line. The gate of the fifth test transistor is connected to the first test control line, and the first terminal of the fifth test transistor is connected to the second test data line. The second terminals of the fourth and fifth test transistors are connected to the same data lead. The gate of the sixth test transistor is connected to the third test control line, and the first terminal of the third test transistor is connected to the third test data line. The second terminals of the first, third, fourth, and sixth test transistors are connected to different data leads. This example, by setting up multiple sets of test circuits to adjust the transmission order of test data signals, avoids jumper design in the second fan-out area, which helps reduce defects caused by jumper design and thus improves the reliability of the display substrate.

[0136] The following examples illustrate the solution of this embodiment.

[0137] Figure 4 is a schematic diagram of the arrangement of sub-pixels in a display area according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 4, each pixel unit in the display area may include: a first sub-pixel 15 emitting a first color light, a second sub-pixel 16 emitting a second color light, and two third sub-pixels 17a and 17b emitting a third color light. Multiple pixel units can be arranged in an array within the display area AA. The pixel circuits of the multiple sub-pixels can be arranged in an array along a first direction D1 and a second direction D2. Within a single pixel unit, the light-emitting elements of the four sub-pixels can be arranged in different columns along the second direction D2. The light-emitting elements of the first sub-pixel 15 and the second sub-pixel 16 can be arranged in the same row, and the light-emitting elements of the two third sub-pixels 17a and 17b can be arranged in the same row. The rows containing the light-emitting elements of the first sub-pixel 15 and the third sub-pixel 17a can be spaced apart along the first direction D1. In this example, the first sub-pixel 15 can be a red sub-pixel (R), the second sub-pixel 16 can be a blue sub-pixel (B), and the third sub-pixels 17a and 17b can be green sub-pixels (G). For example, the third sub-pixel 17a can be the first green sub-pixel (G1), and the third sub-pixel 17b can be the second green sub-pixel (G2).

[0138] In some examples, as shown in Figure 4, multiple pixel units arranged along the second direction D2 can be a row of pixel units, and multiple pixel units arranged along the first direction D1 can be a column of pixel units. Multiple pixel units can include multiple first pixel units and multiple second pixel units, and the arrangement order of the four sub-pixels within the first and second pixel units can be different. For example, the e-th row of pixel units can include: multiple first pixel units arranged sequentially along the second direction D2; the first sub-pixel 15, third sub-pixel 17a, second sub-pixel 16, and third sub-pixel 17b of the first pixel unit are arranged sequentially along the second direction D2. The (e+1)-th row of pixel units can include: multiple second pixel units arranged sequentially along the second direction D2; the second sub-pixel 16, third sub-pixel 17b, first sub-pixel 15, and third sub-pixel 17a of the second pixel unit can be arranged sequentially along the second direction D2. A column of pixel units can include: first pixel units and second pixel units alternately arranged along the first direction D1. Here, e can be an integer greater than 0. For example, the subpixels of odd-numbered rows of pixel units in the display area can be arranged in RG1BG2, and the subpixels of even-numbered rows of pixel units can be arranged in BG2RG1; or, the subpixels of odd-numbered rows of pixel units in the display area can be arranged in BG2RG1, and the subpixels of even-numbered rows of pixel units can be arranged in RG1BG2.

[0139] In some examples, multiple subpixels arranged along the first direction D1 can be a column of subpixels. The j-th column of subpixels may include: a first subpixel 15 and a second subpixel 16 alternately arranged along the first direction D1; the (j+1)-th column of subpixels may include: a third subpixel 17a and a third subpixel 17b alternately arranged along the first direction D1. j can be an integer greater than 1. The pixel circuitry of each column of subpixels can be connected to the same data line. For example, the j-th column of subpixels can be connected to data line DLj, and the (j+1)-th column of subpixels can be connected to data line DLj+1.

[0140] Figure 5 is a partial wiring diagram of the first border region according to at least one embodiment of the present disclosure. Figure 5 mainly illustrates the data lead-out lines of the first border region, while the remaining wiring of the first border region is omitted.

[0141] In some examples, as shown in Figure 5, the first sub-region B11 can be provided with multiple first data leads 261. These first data leads 261 can be configured to connect to multiple second data lines DLb and multiple data connection lines 25 in a fan-out routing manner within the display area AA. The multiple first data leads 261 can be electrically connected to the multiple second data lines DLb and the multiple data connection lines 25 in a one-to-one correspondence. For example, the multiple first data leads 261 can be alternately arranged on the first gate metal layer and the second gate metal layer.

[0142] In some examples, the bending region B12 may be provided with multiple data bending connection lines 264. These multiple data bending connection lines 264 may be electrically connected one-to-one with multiple first data leads 261. For example, the multiple data bending connection lines 264 may be located in the second source / drain metal layer. However, this embodiment is not limited to this. In other examples, the multiple data bending connection lines in the bending region may be located in the first source / drain metal layer.

[0143] In some examples, the second fan-out region B131 may be provided with multiple second data leads 262. These multiple second data leads 262 can be electrically connected to multiple data bend connection lines 264 in a one-to-one correspondence. For example, the multiple second data leads 262 can be alternately arranged in the first gate metal layer and the second gate metal layer.

[0144] In some examples, the third fan-out region B133 may be provided with multiple third data leads 263. These multiple third data leads 263 may be connected to multiple second data leads 262, for example, in a one-to-one electrical connection. For instance, the multiple third data leads 263 may be alternately arranged in the first gate metal layer and the second gate metal layer.

[0145] In this example, the trace lead-out area may include: a first sub-area B11, a bending area B12, a second fan-out area B131, a circuit setting area B132, and a third fan-out area B133. A data lead located in the trace lead-out area may include: a first data lead 261, a data bending connection line 264, a second data lead 262, and a third data lead 263 connected in sequence.

[0146] In some examples, the circuit setup area B132 can be equipped with multiple test circuits, and multiple third data leads 263 can be electrically connected to multiple test circuits. During the testing phase of the display substrate, multiple test circuits can provide test data signals to multiple second data lines DLb of the display area AA through multiple data leads (e.g., each data lead includes a third data lead 263, a second data lead 262, a data bend connection line 264, and a first data lead 261 connected in sequence). Test data signals can also be provided to multiple first data lines DLa through multiple data leads and multiple data connection lines 25 of the display area AA.

[0147] In some examples, the first signal access area B134 may be provided with multiple first contact pads, which may include multiple data contact pads 27. The multiple data contact pads 27 may be configured to provide data signals. The multiple data contact pads 27 may be arranged in a row along the second direction D2, or multiple rows (e.g., two or three rows) of data contact pads 27 may be arranged along the first direction D1. The multiple data contact pads 27 may be connected to multiple third data leads 263, for example, through one-to-one electrical connections. During the normal display phase of the display substrate, the multiple data contact pads 27 may provide data signals to multiple second data lines DLb of the display area AA via multiple data leads (e.g., each data lead includes a third data lead 263, a second data lead 262, a data bend connection line 264, and a first data lead 261 connected in sequence), and may also provide data signals to multiple first data lines DLa via multiple data leads and multiple data connection lines 25 of the display area AA.

[0148] In some examples, as shown in Figure 5, the first sub-region B11 can be equipped with multiple sets of second adapter units, and the third fan-out region B133 can be equipped with multiple sets of first adapter units. The multiple sets of second adapter units can be arranged sequentially along the second direction D2 and located on the side of the multiple first data leads 261 near the display area AA. The multiple first data leads 261 can be connected to the multiple second data lines DLb and multiple data connection lines 25 of the display area AA through the multiple sets of second adapter units. The multiple sets of first adapter units can be arranged sequentially along the second direction D2 and located on the side of the multiple third data leads 263 near the first signal access area B134. The multiple third data leads 263 can be connected to multiple data contact pads 27 within the first signal access area B134 through the multiple sets of first adapter units.

[0149] In some examples, as shown in Figure 5, the multiple sets of first adapter units may include multiple sets of first-side first adapter units 300a and multiple sets of second-side first adapter units 300b. The multiple sets of first-side first adapter units 300a and multiple sets of second-side first adapter units 300b may be located on both sides of the centerline parallel to the first direction D1 of the first border region B1. For example, the multiple sets of first-side first adapter units 300a may be connected to the data lines of the left half of the display region AA, and the multiple sets of second-side first adapter units 300b may be connected to the data lines of the right half of the display region.

[0150] In some examples, the multiple data contact pads 27 of the first signal access area B134 may include: a first set of data contact pads and a second set of data contact pads. The first set of data contact pads and the second set of data contact pads may be arranged along a second direction D2. The first set of data contact pads may be connected to multiple third data leads 263 through multiple sets of first-side first adapter units 300a, and the second set of data contact pads may be connected to multiple third data leads 263 through multiple sets of second-side first adapter units 300b.

[0151] In some examples, as shown in Figure 5, multiple sets of second adapter units may include multiple sets of first-side second adapter units 32a and multiple sets of second-side second adapter units 32b. The multiple sets of first-side second adapter units 32a and multiple sets of second-side second adapter units 32b may be located on both sides of the centerline parallel to the first direction D1 of the first border region B1. For example, the multiple sets of first-side second adapter units 32a may be connected to the second data lines and data connection lines of the left half of the display region AA, and the multiple sets of second-side second adapter units 32b may be connected to the second data lines and data connection lines of the right half of the display region. In some examples, the multiple sets of first-side second adapter units 32a may be connected to the multiple sets of first-side first adapter units 300a via multiple data leads, and the multiple sets of second-side second adapter units 32b may be connected to the multiple sets of second-side first adapter units 300b via multiple data leads. For example, the number of groups of the second transition unit on the first side can be the same as the number of groups of the first transition unit on the first side, and the number of groups of the second transition unit on the second side can be the same as the number of groups of the first transition unit on the second side.

[0152] Figure 6 is a schematic diagram of multiple sets of first-side first transition units according to at least one embodiment of the present disclosure. Figure 6 illustrates two sets of first-side first transition units as an example. Figure 7A is a schematic diagram of the first gate metal layer and the second gate metal layer in Figure 6. Figure 7B is a schematic diagram of the first source / drain metal layer in Figure 6. Figure 7C is a schematic diagram of the second source / drain metal layer in Figure 6. Figure 8 is a partial cross-sectional schematic diagram along the Q-Q' direction in Figure 6. In this example, the number m of the first transition wires included in each set of first transition units can be 8.

[0153] In some examples, as shown in Figures 6 to 8, a set of first-side first adapter units 300a may include: eight first connection terminals 311, eight second connection terminals 312, and eight first adapter lines. Within a set of first-side first adapter units 300a, the eight first connection terminals 311 may be arranged sequentially along the second direction D2. For example, the first arrangement number of the eight first connection terminals 311 arranged sequentially along the second direction D2 may correspond to 1 to 8. The eight first connection terminals 311 may be connected one-to-one with eight consecutively arranged third data leads (e.g., including third data leads 263-1, 263-2, 263-3, 263-4, 263-5, 263-6, 263-7, and 263-8). The third data leads 263-1, 263-3, 263-5, and 263-7 can be located in the second gate metal layer, and the third data leads 263-2, 263-4, 263-6, and 263-8 can be located in the first gate metal layer. For example, as shown in Figure 8, the third data lead located in the first gate metal layer may include the third data lead 263a.

[0154] In some examples, a single first connection terminal 311 may include a first connection electrode 311-1 and a second connection electrode 311-2 located in different conductive layers. The orthographic projection of the first connection electrode 311-1 and the second connection electrode 311-2 onto the substrate may be approximately a strip extending along a first direction D1. The length of the first connection electrode 311-1 along the first direction D1 may be greater than the length of the second connection electrode 311-2 along the first direction D1. For example, the first connection electrode 311-1 may be located in a first source / drain metal layer, and the second connection electrode 311-2 may be located in a second source / drain metal layer. Taking the film layer structure of the display substrate shown in FIG3B as an example, the first connection electrode 311-1 may be connected to a third data lead located in the first gate metal layer through multiple vias formed in the third insulating layer 103 and the second insulating layer 102, or it may be connected to a third data lead located in the second gate metal layer through multiple vias formed in the third insulating layer 103. The second connecting electrode 311-2 can be connected to the first connecting electrode 311-1 through multiple vias formed in the seventh insulating layer 107 and the sixth insulating layer 106. The orthographic projection of the second connecting electrode 311-2 onto the substrate and the orthographic projection of the third data lead onto the substrate may not overlap, or they may partially overlap. This embodiment is not limited in this respect.

[0155] In some examples, within a set of first-side first transition units 300a, eight second connection terminals 312 may be located on the side of the eight first connection terminals 311 near the first signal access area B134 in the first direction D1. The eight second connection terminals 312 may be arranged sequentially along the second direction D2; for example, the second arrangement sequence number of the eight second connection terminals 312 arranged sequentially along the second direction D2 may correspond to 1 to 8. The eight second connection terminals 312 and the eight first connection terminals 311 may be aligned in the first direction D1. The eight second connection terminals 312 may be connected one-to-one with eight consecutively arranged contact pad connection lines 265. Multiple contact pad connection lines 265 may be located in the first gate metal layer. Multiple contact pad connection lines 265 may be electrically connected one-to-one with multiple consecutively arranged data contact pads 27 within the first signal access area B134.

[0156] In some examples, a single second connection terminal 312 may include a third connection electrode 312-1 and a fourth connection electrode 312-2 located in different conductive layers. The orthographic projection of the third connection electrode 312-1 and the fourth connection electrode 312-2 onto the substrate may be approximately strip-shaped extending along a first direction D1. The length of the third connection electrode 312-1 along the first direction D1 may be greater than the length of the fourth connection electrode 312-2 along the first direction D1. For example, the third connection electrode 312-1 may be located in the first source / drain metal layer, and the fourth connection electrode 312-2 may be located in the second source / drain metal layer. Taking the film layer structure of the display substrate shown in FIG3B as an example, the third connection electrode 312-1 can be connected to the contact pad connection line 265 located in the first gate metal layer through multiple vias formed in the third insulating layer 103 and the second insulating layer 102. The fourth connection electrode 312-2 can be connected to the third connection electrode 312-1 through multiple vias formed in the seventh insulating layer 107 and the sixth insulating layer 106. The orthographic projection of the fourth connecting electrode 312-2 onto the substrate and the orthographic projection of the contact pad connecting line 265 onto the substrate may not overlap, or they may partially overlap. This embodiment is not limited in this respect.

[0157] In some examples, within a set of first-side first adapter units 300a, eight first adapter lines may be located between eight first connection terminals 311 and eight second connection terminals 312. Each first adapter line may be connected between one first connection terminal 311 and one second connection terminal 312. The eight first adapter lines may include: four first sequence adapter lines 314, two first insertion adapter lines 313a, and two second insertion adapter lines 313b. In this example, the eight first adapter lines may include two first reordering units, each of which may include: at least one first insertion adapter line (e.g., including one first insertion adapter line 313a) and at least one second insertion adapter line (e.g., including one second insertion adapter line 313b) that overlap in the orthographic projection onto the substrate. In the second direction D2, one first reordering unit, two first sequence adapter lines 314 may be arranged sequentially.

[0158] In some examples, the orthographic projection of the first sequence adapter 314 onto the substrate can be approximately a strip extending along the first direction D1. The orthographic projections of the first insertion adapter 313a and the second insertion adapter 313b onto the substrate can be approximately zigzag lines extending along the first direction D1. The orthographic projection of a first sequence switching unit onto the substrate can be approximately X-shaped. This embodiment is not limited in this respect.

[0159] In some examples, within a set of first-side first adapter units 300a, in the second direction D2, a first first-sequence adapter cable 313a can connect a first first connection terminal and a second second connection terminal; a first second-sequence adapter cable 313b can connect a second first connection terminal and a first second connection terminal; a second first-sequence adapter cable 313a can connect a fifth first connection terminal and a sixth second connection terminal; a second second-sequence adapter cable 313b can connect a sixth first connection terminal and a fifth second connection terminal. A first first-order adapter cable 314 can connect a third first connection terminal and a third second connection terminal; a second first-order adapter cable 314 can connect a fourth first connection terminal and a fourth second connection terminal; a third first-order adapter cable 314 can connect a seventh first connection terminal and a seventh second connection terminal; a fourth first-order adapter cable 314 can connect an eighth first connection terminal and an eighth second connection terminal.

[0160] In some examples, multiple first sequential adapter lines 314 can be in the same layer, for example, they can be located in the second source / drain metal layer. For example, the first sequential adapter line 314, the second connection electrode 311-2 of the connected first connection terminal 311, and the fourth connection electrode 312-2 of the connected second connection terminal 312 can be an integral structure that is interconnected.

[0161] In some examples, the first insertion line 313a and the second insertion line 313b can be located on different conductive layers. For example, the first insertion line 313a can be located on the first source / drain metal layer, and the second insertion line 313b can be located on the second source / drain metal layer. The first insertion line 313a, the first connection electrode 311-1 of the connected first connection terminal 311, and the third connection electrode 312-1 of the connected second connection terminal 312 can be an integral structure interconnected with each other. The second insertion line 313b, the second connection electrode 311-2 of the connected first connection terminal 311, and the fourth connection electrode 312-2 of the connected second connection terminal 312 can be an integral structure interconnected with each other.

[0162] Figures 9A and 9B are schematic diagrams illustrating the interpolation principle of the data signals transmitted by the second connection terminals of the first set of first-side first-transfer units shown in Figure 6. In some examples, as shown in Figures 9A and 9B, taking the sub-pixel arrangement of the display area as shown in Figure 4 as an example, the eight data signals transmitted by the second connection terminals of the first set of first-side first-transfer units can be configured to provide one data line to the display area. In this example, the order without interpolation adjustment corresponds to the arrangement order of multiple data lines in the display area; the first sub-pixel (e.g., red sub-pixel R) and the second sub-pixel (e.g., blue sub-pixel B) arranged in the same column are connected to the same data line, and the third sub-pixel (e.g., including the first green sub-pixel G1 and the second green sub-pixel G2) arranged in the same column are connected to the same data line.

[0163] In some examples, as shown in Figures 9A and 9B, taking eight data lines (e.g., data lines n-3 to n+4) without interpolation as an example, the eight data lines can be arranged along the second direction. By inserting one data line every other data line (i.e., a 1-in-1 method), the data connection lines connected to data lines n-3 to n-1 can be inserted between data lines n+1 to n+4. For example, the data connection line connected to data line n-1 can be inserted between data lines n+1 and n+2, the data connection line connected to data line n-2 can be inserted between data lines n+2 and n+3, and the data connection line connected to data line n-3 can be inserted between data lines n+3 and n+4. The minimum number of cycles for the data signal obtained by adjusting using the 1-in-1 method is 8.

[0164] In some examples, as shown in Figure 9A, taking the subpixel arrangement order of odd-numbered rows of pixel units in the display area as RG1BG2, the subpixel cycle corresponding to the eight data lines (the nth to n+4th after interpolation) obtained by the 1-in-1 interpolation method is: G2RBG1 G1BRG2. As shown in Figure 9B, taking the subpixel arrangement order of even-numbered rows of pixel units in the display area as BG2RG1, the subpixel cycle corresponding to the eight data lines (the nth to n+4th after interpolation) obtained by the 1-in-1 interpolation method is: G1BRG2 G2RBG1.

[0165] In some examples, the first data line within the display area is connected to the data lead-out line of the first border area via a data connection line. Therefore, the order of the data signals required by the multiple data lines within the display area differs from the arrangement order of the multiple data lines. According to the interpolation principle shown in Figures 9A and 9B, multiple data contact pads can provide data signals that satisfy the order of the multiple second data lines and the multiple data connection lines. Since the sub-pixel arrangement order of odd-numbered and even-numbered rows of pixel units within the display area is different, multiple data contact pads can provide corresponding data signals to the sub-pixels of odd-numbered and even-numbered rows of pixel units in different time periods. For example, multiple data contact pads can provide corresponding data signals to G2RBG1 and G1BRG2 along the second direction D2 in a sub-pixel cyclic order during the first time period to satisfy the data signals required by the odd-numbered rows of pixel units within the display area; multiple data contact pads can provide corresponding data signals to G1BRG2 and G2RBG1 along the second direction D2 in a sub-pixel cyclic order during the second time period to satisfy the data signals required by the even-numbered rows of pixel units within the display area. In some examples, multiple data contact pads can sequentially provide data signals to multiple rows of pixel units within a display area in a cyclical order of a first time period and a second time period. For instance, multiple data contact pads can provide data signals to subpixels of a row of pixel units (e.g., the first row of pixel units) in the first time period, and to subpixels of a row of pixel units (e.g., the second row of pixel units) in the first second time period; in the second first time period, multiple data contact pads can provide data signals to subpixels of a row of pixel units (e.g., the third row of pixel units) in the second first time period, and to subpixels of a row of pixel units (e.g., the fourth row of pixel units) in the second second time period, and so on, providing the required data signals to subpixels of multiple rows of pixel units within the display area respectively.

[0166] In other examples, when the subpixel arrangement order of even-numbered rows of pixel units in the display area is RG1BG2 and the subpixel arrangement order of odd-numbered rows of pixel units is BG2RG1, multiple data contact pads can provide corresponding data signals to G2RBG1 and G1BRG2 along the second direction D2 in the subpixel cyclic order during the first time period to satisfy the data signal requirements of even-numbered rows of pixel units in the display area; multiple data contact pads can also provide corresponding data signals to G1BRG2 and G2RBG1 along the second direction D2 in the second time period in the subpixel cyclic order during the second time period to satisfy the data signal requirements of odd-numbered rows of pixel units in the display area.

[0167] In some examples, during the first time period, as shown in Figure 6, the corresponding sub-pixel cycle of the data signals transmitted by the multiple data contact pads along the second direction D2 can be: G2RBG1 G1BRG2. The data signals transmitted by the multiple data contact pads are provided to the second connection terminals 312 of multiple sets of first-side first transition units 300a. For example, after passing through multiple sets of first-side first transition units 300a, the minimum cycle number of the data signal output from the first connection terminal 311 of the first-side first transition unit 300a is still 8, and the sub-pixel cycle corresponding to the data signal output from the first connection terminal 311 can be: RG2BG1 BG1RG2. During the second time period, the corresponding sub-pixel cycle of the data signals transmitted by the multiple data contact pads along the second direction D2 can be: G1BRG2 G2RBG1. After passing through multiple sets of first-side first transition units 300a, the sub-pixel cycle corresponding to the data signal output from the first connection terminal 311 of the multiple sets of first-side first transition units 300a can be: BG1RG2 RG2BG1.

[0168] In some examples, as shown in Figure 6, after being converted by a set of first-side first-transition units 300a, the data signal corresponding to the third sub-pixel (e.g., including the first green sub-pixel G1 and the second green sub-pixel G2) can be transmitted by the third data lead-out line located on the first gate metal layer, and the data signals corresponding to the first sub-pixel (e.g., the red sub-pixel R) and the second sub-pixel (e.g., the blue sub-pixel B) can be transmitted by the third data lead-out line located on the second gate metal layer. This can ensure the uniformity of the signal transmission traces and avoid the load difference caused by arranging the data lead-out lines that transmit the data signals corresponding to the third sub-pixel on different conductive layers, thus affecting the display effect.

[0169] Figure 10 is a schematic diagram of multiple sets of second-side first adapter units according to at least one embodiment of the present disclosure. Figure 10 illustrates two sets of second-side first adapter units as an example. In some examples, as shown in Figure 10, a set of second-side first adapter units 300b may include: eight first connection terminals 311, eight second connection terminals 312, and eight first adapter lines.

[0170] In some examples, within a set of second-side first transition units 300b, eight first connection terminals 311 can be arranged sequentially in the opposite direction of the second direction D2. For example, the first arrangement sequence number of the eight first connection terminals 311 arranged sequentially in the opposite direction of the second direction D2 can correspond to 1 to 8. The eight first connection terminals 311 can be connected one-to-one with eight consecutively arranged third data leads. Among them, the third data leads connected to the first, third, fifth, and seventh first connection terminals can be located in the first gate metal layer, and the third data leads connected to the second, fourth, sixth, and eighth first connection terminals can be located in the second gate metal layer.

[0171] In some examples, within a set of second-side first transition units 300b, eight second connection terminals 312 may be located on the side of the eight first connection terminals 311 near the first signal access area in the first direction D1. The eight second connection terminals 312 may be arranged sequentially in the opposite direction of the second direction D2; for example, the second arrangement sequence number of the eight second connection terminals 312 arranged sequentially in the opposite direction of the second direction D2 may correspond to 1 to 8. The eight second connection terminals 312 and the eight first connection terminals 311 may be aligned in the first direction D1. The eight second connection terminals 312 may be connected one-to-one with eight consecutively arranged contact pad connection lines 265. Multiple contact pad connection lines 265 may be located in the first gate metal layer. Multiple contact pad connection lines 265 may be electrically connected one-to-one with multiple consecutively arranged data contact pads 27 within the first signal access area B134.

[0172] In some examples, within a set of second-side first adapter units 300b, the eight first adapter lines may include four first sequence adapter lines 314, two first insertion sequence adapter lines 313a, and two second insertion sequence adapter lines 313b. The first row number of the first connection terminal 311 to which the first insertion sequence adapter line 313a is connected is less than the second row number of the second connection terminal 312 to which it is connected; the first row number of the first connection terminal 311 to which the second insertion sequence adapter line 313b is connected is greater than the second row number of the second connection terminal 312 to which it is connected. For example, the first insertion sequence adapter line 313a may be located in the second source / drain metal layer, and the second insertion sequence adapter line 313b may be located in the first source / drain metal layer.

[0173] In some examples, the eight first transponders may include two first transponder units, each of which may include: a first transponder unit (e.g., one first transponder unit 313a) and a second transponder unit (e.g., one second transponder unit 313b) that overlap in their orthogonal projection onto the substrate. In the opposite direction of the second direction D2, one first transponder unit, two first transponder units 314, and one first transponder unit and two first transponder units 314 may be arranged sequentially.

[0174] In some examples, the order of data signals transmitted by the second connection terminals of multiple sets of first-side first adapter units 300a can be mirrored with the order of data signals transmitted by the second connection terminals of multiple sets of second-side first adapter units 300b to match the arrangement of data lines and data connection lines in the display area. For example, multiple data lines and multiple data connection lines in the display area can be arranged symmetrically about the center line of the display area parallel to the first direction.

[0175] Figure 11 is a schematic diagram illustrating the interpolation principle of the data signals transmitted at the second connection end of the first adapter unit on the second side shown in Figure 10. In this example, the order without interpolation adjustment corresponds to the arrangement order of multiple data lines in the display area; the first sub-pixel (e.g., red sub-pixel R) and the second sub-pixel (e.g., blue sub-pixel B) arranged in the same column are connected to the same data line, and the third sub-pixel (e.g., including the first green sub-pixel G1 and the second green sub-pixel G2) arranged in the same column are connected to the same data line. In some examples, as shown in Figure 11, the eight data lines without interpolation adjustment (e.g., the (n-3)th to the (n+4)th data lines) are arranged in the opposite direction of the second direction D2, and their order can be adjusted by inserting one data line every other data line. The minimum number of cycles for the data signal obtained by adjusting in a 1-in-1 manner is 8.

[0176] In some examples, as shown in Figure 11, taking the sub-pixel arrangement order (e.g., the sub-pixel arrangement order of odd-numbered row pixel units) in the display area as RG1BG2, the sub-pixel cycle corresponding to the eight data lines (the nth to n+4th adjusted lines after interpolation) obtained in the opposite direction of the second direction D2 in a 1-in-1 manner is: RG2G1B BG1G2R. As shown in Figure 10, the sub-pixel cycle corresponding to the data signals provided by multiple data contact pads in the opposite direction of the second direction D2 can be: RG2G1B BG1G2R. The data signals transmitted by the multiple data contact pads are provided to the second connection terminals 312 of multiple sets of second-side first transition units 300b. For example, after passing through multiple sets of second-side first transition units 300b, the minimum cycle number of the data signals output by the first connection terminals 311 of multiple sets of second-side first transition units 300b is still 8, and the sub-pixel cycle corresponding to the data signals output by the first connection terminals 311 can be: G2RG1B G1BG2R.

[0177] In some examples, taking the subpixel arrangement order within the display area (e.g., the subpixel arrangement order of even-numbered row pixel units) as BG2RG1, the subpixel cycle corresponding to the eight data lines (the nth to n+4th lines after interpolation adjustment) obtained in the opposite direction of the second direction D2 using a 1-in-1 interpolation method is: BG1G2R RG2G1B; the subpixel cycle corresponding to the data signals provided by multiple data contact pads in the opposite direction of the second direction D2 is: BG1G2R RG2G1B. Therefore, after passing through the second group of first adapter units 300b, the subpixel cycle corresponding to the data signals output from the first connection terminal can be: G1BG2R G2RG1B. Further explanations regarding the interpolation principle can be found in the descriptions of the aforementioned embodiments, and will not be repeated here.

[0178] In some examples, as shown in Figure 10, after being converted by a set of second-side first conversion units 300b, the data signal corresponding to the third sub-pixel (e.g., including the first green sub-pixel G1 and the second green sub-pixel G2) can be transmitted by the third data lead-out line located on the first gate metal layer, and the data signals corresponding to the first sub-pixel (e.g., the red sub-pixel R) and the second sub-pixel (e.g., the blue sub-pixel B) can be transmitted by the third data lead-out line located on the second gate metal layer. This can ensure the uniformity of the signal transmission traces and avoid the load difference caused by arranging the data lead-out lines that transmit the data signals corresponding to the third sub-pixel on different conductive layers, thus affecting the display effect.

[0179] Figure 12 is a schematic diagram of a group of first-side second transition units according to at least one embodiment of the present disclosure. In some examples, each group of second transition units may include m second transition lines, and in this example, m may be 8. As shown in Figure 12, a group of first-side second transition units 32a may include eight second transition lines (e.g., four second sequence transition lines 324, two third insertion transition lines 323a, and two fourth insertion transition lines 323b). In this example, the eight second transition lines may include two second reordering units, and each second reordering unit may include at least one third insertion transition line (e.g., one third insertion transition line 323a) and at least one fourth insertion transition line (e.g., one fourth insertion transition line 323b) that overlap in the orthographic projection onto the substrate. In the second direction D2, one second reordering unit, two second sequence transition lines 324 may be arranged sequentially.

[0180] In some examples, one end of each second adapter cable can be connected to a second data line DLb or a data connection line 25, and the other end can be connected to a first data lead-out line 261. Taking the provision of data signals to at least one row of pixel units with a sub-pixel arrangement order of RG1BG2 in the display area as an example, the sub-pixel cycle corresponding to the data signals transmitted by multiple first data lead-out lines 261 along the second direction D2 can be: RG2BG1 BG1RG2. After being converted and output by the second adapter unit 32a on the first side, the corresponding sub-pixel cycle can be G2RBG1 G1BRG2, so that the order of the data signals transmitted by multiple data contact pads along the second direction matches the order of the data signals required by the second data lines and data connection lines connected to the corresponding pixel unit rows in the display area along the second direction D2. Taking the provision of data signals to at least one row of pixel units with a sub-pixel arrangement order of BG2RG1 within the display area as an example, the sub-pixel cycle corresponding to the data signals transmitted by multiple first data lines 261 along the second direction D2 can be: BG1RG2 RG2BG1. After being converted and output by the second conversion unit 32a on the first side, the corresponding sub-pixel cycle can be G1BRG2 G2RBG1. In this embodiment, the film layer of the second conversion line of the second conversion unit is not limited. For example, the film layer can be set similarly to that of the first conversion line, so it will not be described in detail here.

[0181] In some examples, a set of second-side second adapter units 32b can adjust the order of data signals output from the first connection terminal of a set of second-side first adapter units 300b to be the same as the order of data signals input from the second connection terminal. The structure of the second-side second adapter unit 32b in this example can refer to the structure of the first-side second adapter unit 32a, so it will not be described again here.

[0182] This example, by setting up multiple sets of first adapter units and corresponding sets of second adapter units, ensures that the order of data signals transmitted by multiple data contact pads matches the order of data signals required by the second data lines and data connection lines within the display area. This avoids the need for jumper design in the second fan-out area, thereby guaranteeing the reliability of the display product. This setup method ensures the display effect of a Full High Definition (FHD) display product using RGBG subpixel arrangement.

[0183] In some exemplary embodiments, the circuit setting area may be provided with multiple sets of test circuits arranged sequentially along a second direction. These multiple sets of test circuits may be located on the side of the multiple sets of first adapter units away from the first signal access area in the first direction. Each set of test circuits may be connected to multiple (e.g., eight) data leads connected to a set of first adapter units. Each set of test circuits may include at least one first test circuit and at least one second test circuit. The sum of the number of first and second test circuits within each set of test circuits may be twice the number of data leads connected to each set of first adapter units. For example, each first test circuit may be connected to two data leads, and each second test circuit may be connected to two data leads.

[0184] Figure 13 is an equivalent circuit diagram of a first test circuit and a second test circuit according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 13, the first test circuit 401 may include: a first test transistor CT1, a second test transistor CT2, and a third test transistor CT3. The gate of the first test transistor CT1 may be connected to the first test control line SW1, and the first terminal of the first test transistor CT1 may be connected to the first test data line DR; the gate of the second test transistor CT2 may be connected to the second test control line SW2, and the first terminal of the second test transistor CT2 may be connected to the second test data line DB; the gate of the third test transistor CT3 may be connected to the third test control line SW3, and the first terminal of the third test transistor CT3 may be connected to the third test data line DG. The second terminals of the first test transistor CT1 and the second terminals of the second test transistor CT2 may be connected to the same data lead (e.g., data lead DA-n). The second terminal of the third test transistor CT3 may be connected to another data lead (e.g., data lead DA-n+1).

[0185] In some examples, the second test circuit 402 may include a fourth test transistor CT4, a fifth test transistor CT5, and a sixth test transistor CT6. The gate of the fourth test transistor CT4 may be connected to the second test control line SW2, and its first terminal may be connected to the first test data line DR. The gate of the fifth test transistor CT5 may be connected to the first test control line SW1, and its first terminal may be connected to the second test data line DB. The gate of the sixth test transistor CT6 may be connected to the third test control line SW3, and its first terminal may be connected to the third test data line DG. The second terminals of the fourth test transistor CT4 and the fifth test transistor CT5 may be connected to the same data lead (e.g., data lead DA-n+2). The second terminal of the sixth test transistor CT6 may be connected to another data lead (e.g., data lead DA-n+3).

[0186] In some examples, the sub-pixels connected by data lead-in DA-n may include red sub-pixels (R) and blue sub-pixels (B), the sub-pixels connected by data lead-in DA-n+2 may include red sub-pixels (R) and blue sub-pixels (B), and the sub-pixels connected by data lead-in DA-n+1 and DA-n+3 may include a first green sub-pixel (G1) and a second green sub-pixel (G2).

[0187] In some examples, the second terminals of the first test transistor CT1, the third test transistor CT3, the fourth test transistor CT4, and the sixth test transistor CT6 can be connected to different data lines via different data leads.

[0188] In some examples, the first test control line SW1 can be configured to control the first test transistor CT1 in the first test circuit 401 and the fifth test transistor CT5 in the second test circuit 402 to turn on, and the second test control line SW2 can be configured to control the second test transistor CT2 in the first test circuit 401 and the fourth test transistor CT4 in the second test circuit 402 to turn on, so that the first test data signal transmitted by the first test data line DR and the second test data signal transmitted by the second test data line DB can be written to different data lines.

[0189] In some examples, during display testing (e.g., color display testing), a control device can provide a conduction signal to the first test control line SW1 (or the second test control line SW2) and the third test control line SW3, and provide the required test data signals to multiple test data lines respectively, so that multiple data lines in the display area can obtain test data signals, and determine whether there are defective sub-pixels by the color of the displayed screen, and locate the defective sub-pixels.

[0190] In some exemplary embodiments, a set of first adapter units may correspond to a set of test circuits. For example, multiple sets of test circuits may include: multiple first sets of test circuits and multiple second sets of test circuits; multiple data leads connected to a set of first-side first adapter units may be connected to a first set of test circuits, and multiple data leads connected to a set of second-side first adapter units may be connected to a second set of test circuits. In other words, a set of first-side first adapter units corresponds to a first set of test circuits, and a set of second-side first adapter units corresponds to a second set of test circuits.

[0191] Figure 14A is a plan view of the first set of test circuits according to at least one embodiment of the present disclosure. Figure 14B is a schematic diagram of the first source / drain metal layer in Figure 14A. Figure 14C is a schematic diagram of the first semiconductor layer, the first gate metal layer, and the second gate metal layer in Figure 14A.

[0192] In some examples, as shown in Figures 14A to 14C, the first set of test circuits may include two first test circuits 401 and two second test circuits 402. The first test circuit 401, the two second test circuits 402, and the first test circuit 401 may be arranged sequentially along the second direction D2. The first test transistor CT1, the second test transistor CT2, and the third test transistor CT3 of each first test circuit 401 may be arranged along the first direction D1, and the fourth test transistor CT4, the fifth test transistor CT5, and the sixth test transistor CT6 of each second test circuit 402 may be arranged along the first direction D1.

[0193] In some examples, the first test transistor CT1 and the fourth test transistor CT4 can be aligned along the second direction D2, the second test transistor CT2 and the fifth test transistor CT5 can be aligned along the second direction D2, and the third test transistor CT3 and the sixth test transistor CT6 can be aligned along the second direction D2.

[0194] In some examples, the first test circuit 401 may be located between the third data leads 263-1 and 263-2; the first test circuit 402 may be located between the third data leads 263-3 and 263-4; the second test circuit 402 may be located between the third data leads 263-5 and 263-6; and the second test circuit 401 may be located between the third data leads 263-7 and 263-8.

[0195] In some examples, the first test transistor CT1 and the second test transistor CT2 of the first first test circuit 401 can be connected to the third data lead 263-1, and the third test transistor CT3 can be connected to the third data lead 263-2. The fourth test transistor CT4 and the fifth test transistor CT5 of the first second test circuit 402 can be connected to the third data lead 263-3, and the sixth test transistor CT6 can be connected to the third data lead 263-4. The fourth test transistor CT4 and the fifth test transistor CT5 of the second second test circuit 402 can be connected to the third data lead 263-5, and the sixth test transistor CT6 can be connected to the third data lead 263-6. The first test transistor CT1 and the second test transistor CT2 of the second first test circuit 401 can be connected to the third data lead 263-7, and the third test transistor CT3 can be connected to the third data lead 263-8.

[0196] In some examples, the first semiconductor layer of the first frame region of the display substrate may include: active layers 411 and 412 of the first test transistor CT1 of the first test circuit 401, active layers 421 and 422 of the second test transistor CT2, active layer 431 of the third test transistor CT3, active layers 441 and 442 of the fourth test transistor CT4 of the second test circuit 402, active layers 451 and 452 of the fifth test transistor CT5, and active layer 461 of the sixth test transistor CT6. The active layers 411 and 412 of the first test transistor CT1, the active layers 421 and 422 of the second test transistor CT2, and the active layer 431 of the third test transistor CT3 may be arranged along a first direction D1; the active layers 441 and 442 of the fourth test transistor CT4, the active layers 451 and 452 of the fifth test transistor CT5, and the active layer 461 of the sixth test transistor CT6 may be arranged along the first direction D1.

[0197] In some examples, the first gate metal layer in the first border region of the display substrate may include: gates 413a and 413b of the first test transistor CT1, gates 423a and 423b of the second test transistor CT2, gate 433 of the third test transistor CT3, gates 443a and 443b of the fourth test transistor CT4, gates 453a and 453b of the fifth test transistor CT5, and gate 463 of the sixth test transistor CT6. The gates 413a and 413b of the first test transistor CT1 may be an interconnected integral structure, the gates 423a and 423b of the second test transistor CT2 may be an interconnected integral structure, the gates 443a and 443b of the fourth test transistor CT4 may be an interconnected integral structure, and the gates 453a and 453b of the fifth test transistor CT5 may be an interconnected integral structure.

[0198] In some examples, the first gate metal layer in the first border region of the display substrate may further include: third data leads 263-2, 263-4, 263-6, and 263-8. The second gate metal layer of the display substrate may include: third data leads 263-1, 263-3, 263-5, and 263-7.

[0199] In some examples, the first source / drain metal layer in the first border region of the display substrate may include: a first test control line SW1, a second test control line SW2, a third test control line SW3, first test data lines DR1 and DR2, second test data lines DB1 and DB2, a third test data line DG, a second electrode 414 of a first test transistor CT1, a second electrode 424 of a second test transistor CT2, a second electrode 434 and a first electrode 435 of a third test transistor CT3, a second electrode 444 of a fourth test transistor CT4, a second electrode 454 of a fifth test transistor CT5, and a second electrode 464 and a first electrode 465 of a sixth test transistor CT6.

[0200] In some examples, the first test control line SW1, the second test control line SW2, the third test control line SW3, the first test data lines DR1 and DR2, the second test data lines DB1 and DB2, and the third test data line DG may extend at least along the second direction D2. The first test transistor CT1 and the fourth test transistor CT4 may be located between the first test data lines DR1 and DR2 in the first direction D1, and the second test transistor CT2 and the fifth test transistor CT5 may be located between the second test data lines DB1 and DB2 in the first direction D1. The third test transistor CT3 and the sixth test transistor CT6 may be located on one side of the third test data line DG in the first direction D1. The first test control line SW1 and the second test control line SW2 may be located between the first test data line DR2 and the second test data line DB1, and the third test control line SW3 may be located between the second test data line DB2 and the third test data line DG.

[0201] In some examples, the second terminal 414 of the first test transistor CT1 in the first test circuit 401 can be connected to the third data lead 263-1 and the active layers 411 and 412 of the first test transistor CT1; the second terminal 424 of the second test transistor CT2 can be connected to the third data lead 263-1 and the active layers 421 and 422 of the second test transistor CT2; the second terminal 434 of the third test transistor CT3 can be connected to the third data lead 263-2 and the active layer 431 of the third test transistor CT3; and the first terminal 435 of the third test transistor CT3 can be connected to the active layer 431 of the third test transistor CT3.

[0202] In some examples, the second terminal 444 of the fourth test transistor CT4 of the first second test circuit 402 can be connected to the third data lead 263-3 and the active layers 441 and 442 of the fourth test transistor CT4; the second terminal 454 of the fifth test transistor CT5 can be connected to the third data lead 263-3 and the active layers 451 and 452 of the fifth test transistor CT5; the second terminal 464 of the sixth test transistor CT6 can be connected to the third data lead 263-4 and the active layer 461 of the sixth test transistor CT6; and the first terminal 465 of the sixth test transistor CT6 can be connected to the active layer 461 of the sixth test transistor CT6.

[0203] In some examples, the first test data line DR1 can be connected to the active layer 411 of the first test transistor CT1 and the active layer 441 of the fourth test transistor CT4, and the first test data line DR2 can be connected to the active layer 412 of the first test transistor CT1 and the active layer 442 of the fourth test transistor CT4. The second test data line DB1 can be connected to the active layer 421 of the second test transistor CT2 and the active layer 451 of the fifth test transistor CT5, and the second test data line DB2 can be connected to the active layer 422 of the second test transistor CT2 and the active layer 452 of the fifth test transistor CT5. The third test data line DG, the first terminal 435 of the third test transistor CT3, and the first terminal 465 of the sixth test transistor CT6 can be an integrated structure interconnected with each other.

[0204] In some examples, during the testing phase, the test circuit can provide test data signals to the sub-pixels of different rows of pixel units within the display area in time intervals. The first set of test circuits can provide corresponding test data signals to multiple third data leads (e.g., third data leads 263-1 to 263-8) in a cyclical order of RGBG and BGRG during the first test period. These test data signals, after being reordered by multiple sets of second conversion units, are provided to the second data lines and data connection lines of the display area to detect the display status of odd-numbered (or even-numbered) pixel units. The first set of test circuits can also provide corresponding test data signals to multiple third data leads in a cyclical order of BGRG and RGBG during the second test period. These test data signals, after being reordered by multiple sets of second conversion units, are provided to the second data lines and data connection lines of the display area to detect the display status of even-numbered (or odd-numbered) pixel units. The test data signals corresponding to the first green sub-pixel G1 and the second green sub-pixel G2 can be the same. The order of the data signals provided by the first set of test circuits can be the same as the order of the data signals output by the first output terminal of the first adapter unit on the first side. In some examples, the first set of test circuits can provide test data signals to the sub-pixels of the first row of pixel units during the first first test period, provide test data signals to the sub-pixels of the second row of pixel units during the first second test period, provide test data signals to the sub-pixels of the third row of pixel units during the second first test period, provide test data signals to the sub-pixels of the fourth row of pixel units during the second second test period, and so on, providing corresponding test data signals to multiple rows of pixel units respectively.

[0205] In this example, the first test transistor of the first test circuit and the fourth test transistor of the second test circuit are connected to different test control lines but to the same test data line. The second test transistor of the first test circuit and the fifth test transistor of the second test circuit are connected to different test control lines but to the same test data line. During the test phase, test data signals can be provided in the order of the data signals corresponding to the first output terminals of the first set of first-side first transfer units to meet the data line's requirements for test data signals.

[0206] In some examples, the structure of the second set of test circuits corresponding to the first transition unit on the second side of each group is similar to that of the first set of test circuits, so it will not be described again here.

[0207] This embodiment adjusts the transmission order of test data signals by setting up multiple sets of test circuits, which avoids the jumper design in the second fan-out area, helps to reduce the defects caused by jumper design, and thus improves the reliability of the display substrate.

[0208] Figure 15 is an equivalent circuit diagram of the third test circuit according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 15, the third test circuit may include: a seventh test transistor CT7, an eighth test transistor CT8, a ninth test transistor CT9, and a tenth test transistor CT10.

[0209] In some examples, the gates of the seventh test transistor CT7, the eighth test transistor CT8, the ninth test transistor CT9, and the tenth test transistor CT10 are all connected to the fourth test control line SW4. The first terminal of the seventh test transistor CT7 and the eighth test transistor CT8 are connected to the fourth test data line DD1, and the first terminals of the ninth test transistor CT9 and the tenth test transistor CT10 are connected to the fifth test data line DD2. The second terminals of the seventh test transistor CT7, the eighth test transistor CT8, the ninth test transistor CT9, and the tenth test transistor CT10 can be connected to different data lines via different data leads. For example, the second terminal of the seventh test transistor CT7 can be connected to data lead DA-n, the second terminal of the eighth test transistor CT8 can be connected to data lead DA-n+1, ​​the second terminal of the ninth test transistor CT9 can be connected to data lead DA-n+2, and the second terminal of the tenth test transistor CT10 can be connected to data lead DA-n+3.

[0210] In some examples, the third test circuit may be located in the circuit setup area on the side of the first test circuit and the second test circuit closer to the first signal access area, or it may be located on the side closer to the bend area. This embodiment is not limited in this respect.

[0211] In some examples, the third test circuit can be configured to provide test data signals to the data lines during monochrome display testing to perform monochrome display testing.

[0212] Figure 16 is another schematic diagram of a group of first-side first transition units according to at least one embodiment of the present disclosure. Figure 17 is a schematic diagram of the first gate metal layer and the second gate metal layer in Figure 16. Figure 18 is a schematic diagram of the interpolation principle of the data signals transmitted at the second connection end of the group of first-side first transition units shown in Figure 16. In this example, m can be 12. In this example and the following examples, the data signals required by the first green sub-pixel G1 and the second green sub-pixel G2 are the same, and the required test data signals are the same.

[0213] In some examples, as shown in Figures 16 and 17, a set of first-side first transition units 300a may include: twelve first connection terminals 311, twelve second connection terminals 312, and twelve first transition lines. The twelve first transition lines may include: four first sequence transition lines 314, four first insertion sequence transition lines 313a, and four second insertion sequence transition lines 313b. The twelve first transition lines may include four first reordering units, each of which may include: a first insertion sequence transition line (e.g., including one first insertion sequence transition line 313a) and a second insertion sequence transition line (e.g., including one second insertion sequence transition line 313b) that overlap in their orthographic projection onto the substrate. In the second direction D2, two first reordering units, two first sequence transition lines 314, and two first sequence transition lines 314 may be arranged sequentially.

[0214] In some examples, the twelve first connection terminals 311 can be connected one-to-one with twelve consecutively arranged third data leads 263-1 to 263-12. Among them, the third data leads 263-1, 263-3, 263-5, 263-7, 263-9 and 263-11 can be located in the second gate metal layer, and the third data leads 263-2, 263-4, 263-6, 263-8, 263-10 and 263-12 can be located in the first gate metal layer.

[0215] In some examples, within a set of first-side first adapter units 300a, in the second direction D2, a first first-order adapter cable 313a can connect a first first connection terminal and a second second connection terminal; a second first-order adapter cable 313a can connect a third first connection terminal and a fourth second connection terminal; a third first-order adapter cable 313a can connect a seventh first connection terminal and an eighth second connection terminal; and a fourth first-order adapter cable 313a can connect a ninth first connection terminal and a tenth second connection terminal. A first second-order adapter cable 313b can connect a second first connection terminal and a first second connection terminal; a second second-order adapter cable 313b can connect a fourth first connection terminal and a third second connection terminal; a third second-order adapter cable 313b can connect an eighth first connection terminal and a seventh second connection terminal; and a fourth second-order adapter cable 313b can connect a tenth first connection terminal and a ninth second connection terminal.

[0216] In some examples, the first first sequence adapter cable 314 can connect the fifth first connection terminal and the fifth second connection terminal; the second first sequence adapter cable 314 can connect the sixth first connection terminal and the sixth second connection terminal; the third first sequence adapter cable 314 can connect the eleventh first connection terminal and the eleventh second connection terminal; and the fourth first sequence adapter cable 314 can connect the twelfth first connection terminal and the twelfth second connection terminal.

[0217] In some examples, as shown in Figure 18, and taking the sub-pixel arrangement of the display area as shown in Figure 4, with the sub-pixel arrangement order of the odd-numbered rows of pixel units in the display area being RGBG, and taking twelve data lines (e.g., numbered n-3 to n+8) without interpolation adjustment as an example, the twelve data lines can be arranged along the second direction D2. Following the method of inserting one data line every two data lines (i.e., 2-in-1), the data connection lines connected to the (n-3)th to (n-1)th data lines can be inserted between the (n+1)th to (n+8)th data lines. For example, the data connection line connected to the (n-1)th data line can be inserted between the (n+2)th and (n+3)th data lines, the (n-2)th data line can be inserted between the (n+4)th and (n+5)th data lines, and the (n-3)th data line can be inserted between the (n+6)th and (n+7)th data lines. The minimum number of cycles for the data signal obtained using the 2-in-1 interpolation method is 12. The sub-pixel cycles corresponding to the twelve data lines obtained using the 2-in-1 interpolation method are: GRGB BGGR GRBG. In some examples, taking the sub-pixel arrangement order of the even-numbered rows of pixel units in the display area as BGRG, the sub-pixel cycles corresponding to the twelve data lines obtained using the 2-in-1 interpolation method can be: GBGR RGGB GBRG.

[0218] In some examples, multiple data contact pads can provide data signals to subpixels of different rows of pixel units in the display area in time periods. In the first time period, as shown in Figure 16, the corresponding subpixel cycle of the data signals transmitted by the multiple data contact pads along the second direction D2 can be: GRGB BGGR GRBG. The data signals transmitted by the multiple data contact pads are provided to the second connection terminals 312 of multiple sets of first-side first transition units 300a. For example, after passing through multiple sets of first-side first transition units 300a, the minimum cycle number of the data signal output by the first connection terminal 311 is still 12, and the subpixel cycle corresponding to the data signal output by the first connection terminal 311 in the second direction D2 can be: RGBG BGRG RGBG. In the second time period, the corresponding subpixel cycle of the data signals transmitted by the multiple data contact pads along the second direction D2 can be: GBGR RGGB GBRG. After passing through multiple sets of first-side first transition units 300a, the subpixel cycle corresponding to the data signal output by the first connection terminals 311 of the multiple sets of first-side first transition units 300a can be: BGRG RGBG BGRG.

[0219] Figure 19 is a schematic diagram of a group of first-side second transition units according to at least one embodiment of the present disclosure. In some examples, each group of second transition units may include m second transition wires, and in this example, m may be 12. As shown in Figure 19, a group of first-side second transition units 32a may include twelve second transition wires (e.g., four second sequence transition wires 324, two third insertion transition wires 323a, and two fourth insertion transition wires 323b). In this example, the twelve second transition wires may include four second reordering units, and each second reordering unit may include at least one third insertion transition wire (e.g., one third insertion transition wire 323a) and at least one fourth insertion transition wire (e.g., one fourth insertion transition wire 323b) that overlap in the orthographic projection onto the substrate. In the second direction D2, two second reordering units, two second sequence transition wires 324, and two second sequence transition wires 324 may be arranged sequentially.

[0220] In some examples, one end of each second adapter cable can be connected to a second data line DLb or a data connection line 25, and the other end can be connected to a first data lead-out line 261. In the first time period, the sub-pixel cycle corresponding to the data signals transmitted by multiple first data lead-out lines 261 along the second direction D2 can be: RGBG BGRG RGBG. After being converted and output by multiple sets of first-side second adapter units 32a, the corresponding sub-pixel cycle can be GRGB BGGR GRBG. In the second time period, the sub-pixel cycle corresponding to the data signals transmitted by multiple first data lead-out lines 261 along the second direction D2 can be: BGRG RGBG BGRG. After being converted and output by multiple sets of first-side second adapter units 32a, the corresponding sub-pixel cycle can be: GBGR RGGB GBRG. This ensures that the order of the data signals transmitted by the multiple data contact pads along the second direction D2 matches the order of the data signals required by the second data lines and data connection lines within the display area along the second direction D2. For example, the first time period can be configured to provide data signals to the odd-numbered rows of pixel units in the display area, and the second time period can be configured to provide data signals to the even-numbered rows of pixel units in the display area. This embodiment does not limit the film layer of the second adapter cable of the second adapter unit; for example, the film layer can be similar to that of the first adapter cable, so it will not be described further here.

[0221] In some examples, within the first signal access area, the first data contact pad arranged along the second direction can transmit the 384th data signal. This signal is then provided to the third data lead located on the first gate metal layer via the second connection terminal of the first adapter unit, a first adapter cable, and the first connection terminal. The third data lead then transmits the signal to the first data lead via the second data lead and a data bend connection cable. Finally, the first data lead transmits the signal to a data line connected to the green sub-pixel (e.g., the data line numbered 384 arranged along the second direction) via the second adapter cable of the second adapter unit. This example, by combining the adjustment of the order of the data signals transmitted by the data contact pads with the arrangement of multiple sets of first and second adapter units, avoids jumper design in the second fan-out area in the data connection line arrangement scheme of the display area, thereby ensuring the reliability of the display product.

[0222] Figure 20 is a plan view of the first set of test circuits according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 20, the first set of test circuits is connected to twelve third data leads (e.g., third data leads 263-1 to 263-12) connected to a first-side first adapter unit. The first set of test circuits may include three first test circuits 401 and three second test circuits 402. One first test circuit 401, two second test circuits 402, or two first test circuits 401 and one second test circuit 402 may be arranged sequentially along the second direction D2.

[0223] In some examples, the first test transistor CT1 and the second test transistor CT2 of the first first test circuit 401 can be connected to the third data lead 263-1, and the third test transistor CT3 can be connected to the third data lead 263-2. In the second first test circuit 401, the first test transistor CT1 and the second test transistor CT2 can be connected to the third data lead 263-7, and the third test transistor CT3 can be connected to the third data lead 263-8. In the third first test circuit 401, the first test transistor CT1 and the second test transistor CT2 can be connected to the third data lead 263-9, and the third test transistor CT3 can be connected to the third data lead 263-10.

[0224] In some examples, the fourth test transistor CT4 and the fifth test transistor CT5 of the first second test circuit 402 can be connected to the third data lead 263-3, and the sixth test transistor CT6 can be connected to the third data lead 263-4. In the second second test circuit 402, the fourth test transistor CT4 and the fifth test transistor CT5 can be connected to the third data lead 263-5, and the sixth test transistor CT6 can be connected to the third data lead 263-6. In the third second test circuit 402, the fourth test transistor CT4 and the fifth test transistor CT5 can be connected to the third data lead 263-11, and the sixth test transistor CT6 can be connected to the third data lead 263-12.

[0225] In some examples, the test circuit can provide test data signals to the sub-pixels of different rows of pixel units within the display area in time intervals. During the testing phase, the first set of test circuits can provide corresponding test data signals to multiple third data leads (e.g., including third data leads 263-1 to 263-12) in a cyclical order of RGBG BGRG RGBG during the first test period. These test data signals are then provided to the second data lines and data connection lines of the display area after being reordered by multiple sets of second conversion units, to detect the display status of odd-numbered (or even-numbered) pixel units. The first set of test circuits can also provide corresponding test data signals to multiple third data leads in a cyclical order of BGRG RGBG BGRG during the second test period. These test data signals are then provided to the second data lines and data connection lines of the display area after being reordered by multiple sets of second conversion units, to detect the display status of even-numbered (or odd-numbered) pixel units. Further descriptions of the test circuits can be found in the description of the foregoing embodiments, and will not be repeated here.

[0226] Figure 21 is a schematic diagram of a set of second-side first adapter units according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 21, a set of second-side first adapter units 300b may include: twelve first connection terminals 311, twelve second connection terminals 312, and twelve first adapter lines. Within a set of second-side first adapter units 300b, the twelve first connection terminals 311 may be arranged sequentially in the opposite direction of the second direction D2. For example, the first arrangement sequence number of the twelve first connection terminals 311 arranged sequentially in the opposite direction of the second direction D2 may correspond to 1 to 12. The twelve first connection terminals 311 may be connected one-to-one with twelve consecutively arranged third data leads. The third data leads connected to the first, third, fifth, seventh, ninth, and eleventh first connection terminals can be located in the first gate metal layer, and the third data leads connected to the second, fourth, sixth, eighth, tenth, and twelfth first connection terminals can be located in the second gate metal layer.

[0227] In some examples, within a set of second-side first adapter units 300b, twelve second connection terminals 312 can be arranged sequentially in the opposite direction of the second direction D2. For example, the second arrangement sequence number of the twelve second connection terminals 312 arranged sequentially in the opposite direction of the second direction D2 can correspond to 1 to 12. The twelve first adapter cables may include four first sequence adapter cables 314, four first insertion sequence adapter cables 313a, and four second insertion sequence adapter cables 313b.

[0228] Figure 22 is a schematic diagram illustrating the interpolation principle of the data signals transmitted at the second connection end of the first adapter unit on the second side shown in Figure 21. In this example, the order without interpolation adjustment corresponds to the arrangement order of multiple data lines in the display area; the first sub-pixel (e.g., red sub-pixel R) and the second sub-pixel (e.g., blue sub-pixel B) arranged in the same column are connected to the same data line, and the third sub-pixel (e.g., green sub-pixel G) arranged in the same column is also connected to the same data line. In some examples, as shown in Figure 22, the twelve data lines without interpolation adjustment (e.g., the (n-3)th to (n+8)th data lines) can be arranged in the opposite direction of the second direction D2, and the order can be adjusted by inserting one data line every two data lines. The minimum number of cycles for the data signal obtained by adjusting in a 2-in-1 manner is 12. Taking RGBG as an example, with a subpixel arrangement order (e.g., the subpixel arrangement order of odd-numbered rows of pixel units), as shown in Figure 22, the subpixel cycle corresponding to the twelve data lines (the nth to n+8th lines after interpolation adjustment) obtained by the 2-in-1 interpolation method is: RGBG GRBG BGGR. Taking BGRG as an example, with a subpixel arrangement order (e.g., the subpixel arrangement order of even-numbered rows of pixel units), the subpixel cycle corresponding to the twelve data lines (the nth to n+8th lines after interpolation adjustment) obtained by the 2-in-1 interpolation method can be BGRG GBRG RGGB.

[0229] In some examples, multiple data contact pads can provide data signals to sub-pixels of different rows of pixel units in the display area in time periods. In the first time period, as shown in Figure 21, the sub-pixel cycle corresponding to the data signals provided by the multiple data contact pads along the opposite direction of the second direction D2 can be: RGBG GRBG BGGR. The data signals transmitted by the multiple data contact pads are provided to the second connection terminals 312 of multiple sets of second-side first transition units 300b. For example, after passing through multiple sets of second-side first transition units 300b, the minimum cycle number of the data signals output by the first connection terminals 311 of multiple sets of second-side first transition units 300b is still 12, and along the opposite direction of the second direction D2, the sub-pixel cycle corresponding to the twelve data signals can be: GRGB GRGB GBGR. In the second time period, the data signals transmitted by multiple data contact pads along the second direction D2 can correspond to the following sub-pixel cycle: BGRG GBRG RGGB. After passing through multiple sets of second-side first adapter units 300b, the data signals output by the first connection terminal 311 of multiple sets of second-side first adapter units 300b can correspond to the following sub-pixel cycle: GBGR GBGR GRGB.

[0230] Figure 23 is a plan view of the second set of test circuits according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 23, the second set of test circuits can be connected to twelve third data leads 263 connected to a set of second-side first adapter units. The second set of test circuits may include: three first test circuits 401 and three second test circuits 402. One first test circuit 401, one second test circuit 402, one first test circuit 401, two second test circuits 402, and one first test circuit 401 can be arranged sequentially in the opposite direction of the second direction D2.

[0231] In some examples, during the testing phase, the test data signals provided by the test circuit at different times may differ. The test circuit can provide corresponding test data signals according to the scanning pattern of the display area line by line. For example, for odd-numbered row pixel units, the second set of test circuits can provide corresponding test data signals to multiple data leads in the reverse direction of the second direction D2 according to the cyclic sequence of GRGB GRGB GBGR; for even-numbered row pixel units, the second set of test circuits can provide corresponding test data signals to multiple data leads in the reverse direction of the second direction D2 according to the cyclic sequence of GBGR GBGR GRGB. Further descriptions of the test circuit in this example can be found in the description of the foregoing embodiments, and will not be repeated here.

[0232] Figure 24 is another schematic diagram of a set of first-side first transition units according to at least one embodiment of the present disclosure. Figure 25 is a schematic diagram of the interpolation principle of the data signals transmitted at the second connection end of the set of first-side first transition units shown in Figure 24. In this example, m can be 16.

[0233] In some examples, as shown in Figure 24, a set of first-side first transition units 300a may include: sixteen first connection terminals 311, sixteen second connection terminals 312, and sixteen first transition lines. The sixteen first transition lines may include: eight first sequence transition lines 314, four first insertion sequence transition lines 313a, and four second insertion sequence transition lines 313b. The sixteen first transition lines may include four first reordering units, each of which may include: a first insertion sequence transition line (e.g., one first insertion sequence transition line 313a) and a second insertion sequence transition line (e.g., one second insertion sequence transition line 313b) that overlap in their orthographic projection onto the substrate. In the second direction D2, two first reordering units, four first sequence transition lines 314, and two first reordering units and four first sequence transition lines 314 may be arranged sequentially.

[0234] In some examples, the sixteen first connection terminals 311 can be connected one-to-one with sixteen consecutively arranged third data leads. The sixteen third data leads can be alternately arranged in the first gate metal layer and the second gate metal layer.

[0235] In some examples, within a set of first-side first adapter units 300a, in the second direction D2, a first first-order adapter cable 313a can connect a first first connection terminal and a second second connection terminal; a second first-order adapter cable 313a can connect a third first connection terminal and a fourth second connection terminal; a third first-order adapter cable 313a can connect a ninth first connection terminal and a tenth second connection terminal; and a fourth first-order adapter cable 313a can connect an eleventh first connection terminal and a twelfth second connection terminal. A first second-order adapter cable 313b can connect a second first connection terminal and a first second connection terminal; a second second-order adapter cable 313b can connect a fourth first connection terminal and a third second connection terminal; a third second-order adapter cable 313b can connect a tenth first connection terminal and a ninth second connection terminal; and a fourth second-order adapter cable 313b can connect a twelfth first connection terminal and an eleventh second connection terminal.

[0236] In some examples, the first first-order adapter cable 314 can connect to the fifth first connection terminal and the fifth second connection terminal; the second first-order adapter cable 314 can connect to the sixth first connection terminal and the sixth second connection terminal; the third first-order adapter cable 314 can connect to the seventh first connection terminal and the seventh second connection terminal; the fourth first-order adapter cable 314 can connect to the eighth first connection terminal and the eighth second connection terminal; the fifth first-order adapter cable 314 can connect to the thirteenth first connection terminal and the thirteenth second connection terminal; the sixth first-order adapter cable 314 can connect to the fourteenth first connection terminal and the fourteenth second connection terminal; the seventh first-order adapter cable 314 can connect to the fifteenth first connection terminal and the fifteenth second connection terminal; and the eighth first-order adapter cable 314 can connect to the sixteenth first connection terminal and the sixteenth second connection terminal.

[0237] In some examples, as shown in Figure 25, and taking the sub-pixel arrangement of the display area as shown in Figure 4, with the sub-pixel arrangement order of the odd-numbered rows of pixel units in the display area being RGBG, and using sixteen data lines (e.g., numbered n-3 to n+12) without interpolation adjustment as an example, the sixteen data lines can be arranged along the second direction D2. Following the method of inserting one data line every three data lines (i.e., the 3-in-1 method), the data connection lines connected to the (n-3)th to (n-1)th data lines can be inserted between the (n+1)th to (n+12)th data lines. For example, the (n-1)th data line can be inserted between the (n+3)th and (n+4)th data lines, the (n-2)th data line can be inserted between the (n+6)th and (n+7)th data lines, and the (n-3)th data line can be inserted between the (n+9)th and (n+10)th data lines. The minimum number of cycles for the data signal obtained using the 3-in-1 method is 16. Taking the subpixel arrangement order of a row of display units as RGBG as an example, the subpixel cycle corresponding to the sixteen data lines obtained by the 3-in-1 interpolation method is: GRGB BGRG GBGR RGBG. Taking the subpixel arrangement order of a row of display units as BGRG as an example, the subpixel cycle corresponding to the sixteen data lines obtained by the 3-in-1 interpolation method can be: GBGR RGBG GRGB BGRG.

[0238] In some examples, multiple data contact pads can provide data signals to the subpixels of different rows of pixel units in the display area in time periods. In the first time period, as shown in Figure 24, the subpixel cycle corresponding to the data signals transmitted by the multiple data contact pads along the second direction D2 can be: GRGB BGRG GBGR RGBG. After multiple data signals pass through multiple sets of first-side first adapter units 300a, the minimum number of data signal cycles remains 16, and the subpixel cycle corresponding to the sixteen data signals along the second direction D2 can be: RGBG BGRG BGRG RGBG. In the second time period, the subpixel cycle corresponding to the data signals transmitted by the multiple data contact pads along the second direction D2 can be: GBGR RGBG GRGB BGRG. After passing through multiple sets of first-side first adapter units 300a, the subpixel cycle corresponding to the data signals output from the first connection terminal 311 of the multiple sets of first-side first adapter units 300a can be: BGRG RGBG RGBG BGRG.

[0239] Figure 26 is a plan view of the first group of test circuits corresponding to the first set of first-side first transition units shown in Figure 24. In some examples, as shown in Figure 26, one first group of test circuits is connected to sixteen third data leads connected to the first set of first-side first transition units. The first group of test circuits may include: four first test circuits 401 and four second test circuits 402. Specifically, one first test circuit 401, two second test circuits 402, one first test circuit 401, one second test circuit 402, two first test circuits 401, and one second test circuit 402 can be arranged sequentially along the second direction D2.

[0240] In some examples, the test circuit can provide test data signals to the sub-pixels of different rows of pixel units within the display area in time intervals. During the testing phase, the first set of test circuits can provide corresponding test data signals to multiple third data leads in a cyclical order of RGBG BGRG BGRG RGBG during the first test period. These test data signals are then provided to the second data lines and data connection lines of the display area after being reordered by multiple sets of second conversion units, in order to detect the display status of odd-numbered (or even-numbered) pixel units. The first set of test circuits can also provide corresponding test data signals to multiple third data leads in a cyclical order of BGRG RGBG RGBG BGRG during the second test period. These test data signals are then provided to the second data lines and data connection lines of the display area after being reordered by multiple sets of second conversion units, in order to detect the display status of even-numbered (or odd-numbered) pixel units. Other descriptions of the test circuits can be found in the description of the foregoing embodiments, and will not be repeated here.

[0241] Figure 27 is a schematic diagram of a set of second-side first adapter units according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 27, a set of second-side first adapter units 300b may include: sixteen first connection terminals 311, sixteen second connection terminals 312, and sixteen first adapter lines. Within a set of second adapter units 300b, the sixteen first connection terminals 311 may be arranged sequentially in the opposite direction of the second direction D2. For example, the first arrangement sequence number of the sixteen first connection terminals 311 arranged sequentially in the opposite direction of the second direction D2 may correspond to 1 to 16. The sixteen first connection terminals 311 may be connected to sixteen consecutively arranged third data leads. The third data leads connected to the first, third, fifth, seventh, ninth, eleventh, thirteenth, and fifteenth first connection terminals can be located in the first gate metal layer, while the third data leads connected to the second, fourth, sixth, eighth, tenth, twelfth, fourteenth, and sixteenth first connection terminals can be located in the second gate metal layer.

[0242] In some examples, within a set of second-side first adapter units 300b, sixteen second connection terminals 312 can be arranged sequentially in the opposite direction of the second direction D2. For example, the second arrangement sequence number of the sixteen second connection terminals 312 arranged sequentially in the opposite direction of the second direction D2 can correspond to 1 to 16. The sixteen first adapter cables may include eight first sequence adapter cables 314, four first insertion sequence adapter cables 313a, and four second insertion sequence adapter cables 313b.

[0243] Figure 28 is a schematic diagram illustrating the interpolation principle of the data signals transmitted at the second connection end of the first adapter unit on the second side shown in Figure 27. In this example, the order without interpolation adjustment corresponds to the arrangement order of multiple data lines in the display area; the first sub-pixel (e.g., red sub-pixel R) and the second sub-pixel (e.g., blue sub-pixel B) arranged in the same column are connected to the same data line, and the third sub-pixel (e.g., green sub-pixel G) arranged in the same column is also connected to the same data line. In some examples, as shown in Figure 28, the sixteen data lines without interpolation adjustment (e.g., lines n-3 to n+12) are arranged in the opposite direction of the second direction D2, and their order can be adjusted by inserting one data line every three data lines. The minimum number of cycles of the data signal obtained by adjusting according to the 3-in-1 method is 16. Taking the sub-pixel arrangement order of a row of pixel units as RGBG as an example, as shown in Figure 28, the sub-pixel cycles corresponding to the sixteen data lines (lines n to n+12 after interpolation adjustment) obtained by the 3-in-1 method are: RGBG GRGB BGRG GBGR. Taking the subpixel arrangement order of a row of pixel units as BGRG as an example, the subpixel cycle corresponding to the sixteen data lines (the nth to n+12th after interpolation) obtained by the 3-in-1 method can be: BGRG GBGR RGBG GRGB.

[0244] In some examples, multiple data contact pads can provide data signals to the subpixels of different rows of pixel units in the display area in time periods. In the first time period, as shown in Figure 27, the subpixel cycle corresponding to the data signals provided by the multiple data contact pads along the opposite direction of the second direction D2 can be: RGBG GRGB BGRG GBGR. The minimum cycle number of the data signals after passing through multiple sets of second-side first adapter units 300b is still 16, and along the opposite direction of the second direction D2, the subpixel cycle corresponding to the sixteen data signals can be: GRGB GRGB GBGR GBGR. In the second time period, the subpixel cycle corresponding to the data signals provided by the multiple data contact pads along the opposite direction of the second direction D2 can be: BGRG GBGR RGBG GRGB. After passing through multiple sets of second-side first adapter units 300b, along the opposite direction of the second direction D2, the subpixel cycle corresponding to the data signals output from the first connection terminal 311 of the multiple sets of second-side first adapter units 300b can be: GBGR GBGR GRGB GRGB.

[0245] Figure 29 is a plan view of the second set of test circuits according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 29, the second set of test circuits can be connected to sixteen third data leads 263 connected to a set of second-side first adapter units. The second set of test circuits may include: four first test circuits 401 and four second test circuits 402. Specifically, one first test circuit 401, one second test circuit 402, one first test circuit 401, two second test circuits 402, one first test circuit 401, one second test circuit 402, and one first test circuit 401 can be arranged sequentially in the opposite direction of the second direction D2.

[0246] In some examples, the test data signals provided by the test circuit at different times during the testing phase can be different. The test circuit can provide corresponding test data signals according to the scanning pattern of the display area line by line. For example, for odd-numbered row pixel units, the second set of test circuits can provide corresponding test data signals to multiple data leads in the reverse direction of the second direction D2 according to the cyclic sequence of GRGB GRGB GBGR GBGR; for even-numbered row pixel units, the second set of test circuits can provide corresponding test data signals to multiple data leads in the reverse direction of the second direction D2 according to the cyclic sequence of GBGR GBGR GRGB GRGB. Further descriptions of the test circuit in this example can be found in the description of the foregoing embodiments, and will not be repeated here.

[0247] Figure 30 is another schematic diagram of a set of first-side first-transfer units according to at least one embodiment of the present disclosure. Figure 31 is a schematic diagram of the interpolation principle of the data signals transmitted at the second connection end of the set of first-side first-transfer units shown in Figure 30. In this example, m can be 20.

[0248] In some examples, as shown in Figure 30, a set of first-side first transition units 300a may include: twenty first connection terminals 311, twenty second connection terminals 312, and twenty first transition lines. The twenty first transition lines may include: eight first sequence transition lines 314, six first insertion sequence transition lines 313a, and six second insertion sequence transition lines 313b. The twenty first transition lines may include six first reordering units, each of which may include: a first insertion sequence transition line (e.g., including one first insertion sequence transition line 313a) and a second insertion sequence transition line (e.g., including one second insertion sequence transition line 313b) that overlap in their orthographic projection onto the substrate. In the second direction D2, three first reordering units, four first sequence transition lines 314, and three first reordering units and four first sequence transition lines 314 may be arranged sequentially.

[0249] In some examples, twenty first connection terminals 311 can be connected one-to-one with twenty consecutively arranged third data leads. The twenty third data leads can be alternately arranged in the first gate metal layer and the second gate metal layer.

[0250] In some examples, within a set of first-side first-transfer units 300a, in the second direction D2, a first first-sequence adapter cable 313a can connect a first first connection terminal and a second second connection terminal; a second first-sequence adapter cable 313a can connect a third first connection terminal and a fourth second connection terminal; a third first-sequence adapter cable 313a can connect a fifth first connection terminal and a sixth second connection terminal; a fourth first-sequence adapter cable 313a can connect an eleventh first connection terminal and a twelfth second connection terminal; a fifth first-sequence adapter cable 313a can connect a thirteenth first connection terminal and a fourteenth second connection terminal; and a sixth first-sequence adapter cable 313a can connect a fifteenth first connection terminal and a sixteenth second connection terminal.

[0251] In some examples, within a set of first-side first adapter units 300a, in the second direction D2, a first second-order adapter cable 313b can connect a second first connection terminal and a first second connection terminal; a second second-order adapter cable 313b can connect a fourth first connection terminal and a third second connection terminal; a third second-order adapter cable 313b can connect a sixth first connection terminal and a fifth second connection terminal; a fourth second-order adapter cable 313b can connect a twelfth first connection terminal and an eleventh second connection terminal; a fifth second-order adapter cable 313b can connect a fourteenth first connection terminal and a thirteenth second connection terminal; and a sixth second-order adapter cable 313b can connect a sixteenth first connection terminal and a fifteenth second connection terminal.

[0252] In some examples, within a set of first-side first adapter units 300a, in the second direction D2, the first first-sequence adapter cable 314 can connect the seventh first connection terminal and the seventh second connection terminal; the second first-sequence adapter cable 314 can connect the eighth first connection terminal and the eighth second connection terminal; the third first-sequence adapter cable 314 can connect the ninth first connection terminal and the ninth second connection terminal; the fourth first-sequence adapter cable 314 can connect the tenth first connection terminal and the tenth second connection terminal; the fifth first-sequence adapter cable 314 can connect the seventeenth first connection terminal and the seventeenth second connection terminal; the sixth first-sequence adapter cable 314 can connect the eighteenth first connection terminal and the eighteenth second connection terminal; the seventh first-sequence adapter cable 314 can connect the nineteenth first connection terminal and the nineteenth second connection terminal; and the eighth first-sequence adapter cable 314 can connect the twentieth first connection terminal and the twentieth second connection terminal.

[0253] In some examples, as shown in Figure 31, and with the sub-pixel arrangement of the display area as shown in Figure 4, taking the RGBG sub-pixel arrangement order of the odd-numbered rows of pixel units in the display area as an example, and using twenty data signals (e.g., numbers n-3 to n+16) without interpolation adjustment as an example, the twenty data lines can be arranged along the second direction D1, and can be inserted in a manner that skips four data lines (i.e., 4-in-1). The data connection lines connected to the (n-3)th to (n-1)th data lines can be inserted between the (n+1)th to (n+16)th data lines. For example, the (n-1)th data line can be inserted between the (n+4)th and (n+5)th data lines, the (n-2)th data line can be inserted between the (n+8)th and (n+9)th data lines, and the (n-3)th data line can be inserted between the (n+12)th and (n+13)th data lines. The minimum number of cycles for the data signal obtained by adjusting in the 4-in-1 manner is 20. Taking the subpixel arrangement order of a row of pixel units as RGBG as an example, the subpixel cycle corresponding to the twenty data lines obtained by interpolation (4 interpolations to 1) is: GRGB GBRG BGGR GBGR RGBG. Taking the subpixel arrangement order of a row of pixel units as BGRG, the subpixel cycle corresponding to the twenty data lines obtained by interpolation (4 interpolations to 1) can be: GBGR GRBG RGGB GRGB BGRG.

[0254] In some examples, multiple data contact pads can provide data signals to the subpixels of different rows of pixel units in the display area in time periods. In the first time period, as shown in Figure 30, the subpixel cycle corresponding to the data signals transmitted by the multiple data contact pads along the second direction D2 can be: GRGB GBRG BGGR GBGR RGBG. After multiple data signals pass through multiple sets of first-side first transition units 300a, the minimum number of data signal cycles remains 20, and the subpixel cycle corresponding to the twenty data signals along the second direction D2 can be: RGBG BGRG BGRG BGRG RGBG. In the second time period, the subpixel cycle corresponding to the data signals transmitted by the multiple data contact pads along the second direction D2 can be: GBGR GRBG RGGB GRGB BGRG. After passing through multiple sets of first-side first transition units 300a, the subpixel cycle corresponding to the data signals output from the first connection terminal 311 of the multiple sets of first-side first transition units 300a can be: BGRG RGBG RGBG RGBG BGRG.

[0255] Figure 32 is a plan view of the first group of test circuits corresponding to the first set of first-side first transition units shown in Figure 30. In some examples, as shown in Figure 32, one first group of test circuits is connected to twenty third data leads connected to the first set of first-side first transition units. The first group of test circuits may include: five first test circuits 401 and five second test circuits 402. Specifically, one first test circuit 401, two second test circuits 402, one first test circuit 401, one second test circuit 402, one first test circuit 401, one second test circuit 402, two first test circuits 401, and one second test circuit 402 can be arranged sequentially along the second direction D2.

[0256] In some examples, the test data signals provided by the test circuit at different times during the testing phase can be different. The test circuit can provide corresponding test data signals according to the scanning pattern of the display area line by line. For example, for odd-numbered row pixel units, the first group of test circuits can provide corresponding test data signals to multiple data leads along the second direction D2 in a cyclical order of RGBG BGRG BGRG BGRG RGBG; for even-numbered row pixel units, the first group of test circuits can provide corresponding test data signals to multiple data leads along the second direction D2 in a cyclical order of BGRG RGBG RGBG RGBG BGRG. Other descriptions of the test circuit can be found in the description of the foregoing embodiments, and will not be repeated here.

[0257] Figure 33 is a schematic diagram of a set of second-side first adapter units according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 33, a set of second-side first adapter units 300b may include: twenty first connection terminals 311, twenty second connection terminals 312, and twenty first adapter lines. Within a set of second-side first adapter units 300b, the twenty first connection terminals 311 may be arranged sequentially in the opposite direction of the second direction D2. For example, the first arrangement sequence number of the twenty first connection terminals 311 arranged sequentially in the opposite direction of the second direction D2 may correspond to 1 to 20. The twenty first connection terminals 311 may be connected to twenty consecutively arranged third data leads. The third data lead connected to the first, third, fifth, seventh, ninth, eleventh, thirteenth, fifteenth, seventeenth, and nineteenth first connection terminals can be located in the first gate metal layer, while the third data lead connected to the second, fourth, sixth, eighth, tenth, twelfth, fourteenth, sixteenth, eighteenth, and twentieth first connection terminals can be located in the second gate metal layer.

[0258] In some examples, within a set of second-side first adapter units 300b, twenty second connection terminals 312 can be arranged sequentially in the opposite direction of the second direction D2. For example, the second arrangement sequence number of the twenty second connection terminals 312 arranged sequentially in the opposite direction of the second direction D2 can correspond to 1 to 20. The twenty first adapter cables may include eight first sequence adapter cables 314, six first insertion sequence adapter cables 313a, and six second insertion sequence adapter cables 313b.

[0259] Figure 34 is a schematic diagram illustrating the interpolation principle of the data signals transmitted at the second connection end of the first adapter unit on the second side shown in Figure 33. In some examples, as shown in Figure 34, taking the sub-pixel arrangement order of a row of pixel units as RGBG, the sub-pixel cycle corresponding to the twenty data lines obtained by the 4-in-1 interpolation method is: RGBG RGGB GRBG BGRG GBGR. Taking the sub-pixel arrangement order of a row of pixel units as BGRG, the sub-pixel cycle corresponding to the twenty data lines obtained by the 4-in-1 interpolation method is: BGRG BGGR GBRG RGBG GRGB.

[0260] In some examples, multiple data contact pads can provide data signals to subpixels of different rows of pixel units in the display area in time periods. In the first time period, as shown in Figure 33, the subpixel cycle corresponding to the data signals provided by the multiple data contact pads along the opposite direction of the second direction D2 can be: RGBG RGGB GRBG BGRG GBGR. The minimum number of cycles for the data signals after passing through multiple sets of second-side first adapter units 300b is still 20, and along the opposite direction of the second direction, the subpixel cycle corresponding to the twenty data signals can be: GRGB GRGB GRGB GBGR GBGR. In the second time period, the subpixel cycle corresponding to the data signals transmitted by the multiple data contact pads along the opposite direction of the second direction D2 can be: BGRG BGGR GBRG RGBG GRGB. After passing through multiple sets of second-side first adapter units 300b, the subpixel cycle corresponding to the data signals output from the first connection terminal 311 of the multiple sets of second-side first adapter units 300b can be: GBGR GBGR GBGR GRGB GRGB.

[0261] Figure 35 is a plan view of the second set of test circuits according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 35, the second set of test circuits can be connected to twenty third data leads 263 connected to a set of second-side first adapter units. The second set of test circuits may include: five first test circuits 401 and five second test circuits 402. Specifically, one first test circuit 401, one second test circuit 402, one first test circuit 401, one second test circuit 402, one first test circuit 401, two second test circuits 402, one first test circuit 401, one second test circuit 402, and one first test circuit 401 can be arranged sequentially in the opposite direction of the second direction D2.

[0262] In some examples, the test data signals provided by the test circuit at different times during the testing phase can be different. The test circuit can provide corresponding test data signals according to the scanning pattern of the display area line by line. For example, for odd-numbered row pixel units, the second set of test circuits can provide corresponding test data signals to multiple data leads in the reverse direction of the second direction D2 according to the cyclic sequence of GRGB GRGB GRGB GBGR GBGR; for even-numbered row pixel units, the second set of test circuits can provide corresponding test data signals to multiple data leads in the reverse direction of the second direction D2 according to the cyclic sequence of GBGR GBGR GBGR GRGB GRGB. Further descriptions of the test circuit in this example can be found in the description of the foregoing embodiments, and will not be repeated here.

[0263] Figures 36A to 36C are example diagrams illustrating the connection method of multiple first transition units according to at least one embodiment of the present disclosure. Figures 36A to 36C are illustrated using the sub-pixel arrangement of the display area as shown in Figure 4 as an example.

[0264] In some examples, as shown in FIG36A, in the second direction D2, the first insertion line 313a can connect the first first connection terminal 311 and the fourth second connection terminal 312; the first second insertion line 313b can connect the second first connection terminal 311 and the first second connection terminal 312; the second second insertion line 313b can connect the third first connection terminal 311 and the second second connection terminal 312; and the third second insertion line 313b can connect the fourth first connection terminal 311 and the third second connection terminal 312. The orthographic projection of the first insertion line 313a onto the substrate overlaps with the orthographic projection of the three second insertion lines 313b onto the substrate. In some examples, the first insertion line 313a can be located in the first source / drain metal layer, and the three second insertion lines 313b can be located in the second source / drain metal layer. However, this embodiment is not limited to this. In other examples, the first interpolation adapter may be located in the second source-drain metal layer, and the second interpolation adapter may be located in the first source-drain metal layer.

[0265] In some examples, as shown in Figure 36A, when the data signals transmitted at the second connection terminal 312 are configured to correspond to GBGR sequentially, after passing through four first adapter lines, the data signals transmitted at the first connection terminal 311 are configured to correspond to RGBG sequentially. This example, by setting the first adapter unit, allows the data signals corresponding to the first sub-pixel (e.g., red sub-pixel R) and the second sub-pixel (e.g., blue sub-pixel B) to be transmitted on the data lead-out lines located on the second gate metal layer (or the first gate metal layer), and allows the data signal corresponding to the third sub-pixel (e.g., green sub-pixel G) to be transmitted on the data lead-out lines located on the first gate metal layer (or the second gate metal layer), thereby ensuring the uniformity of signal transmission.

[0266] In some examples, as shown in Figure 36B, in the second direction D2, the first insertion adapter 313a can connect the first first connection terminal 311 and the third second connection terminal 312; the second insertion adapter 313b can connect the third first connection terminal 311 and the first second connection terminal 312; the first first sequence adapter 314 can connect the second first connection terminal and the second second connection terminal; the second first sequence adapter 314 can connect between the fourth first connection terminal and the fourth second connection terminal. The orthographic projection of the first first sequence adapter 314 onto the substrate overlaps with the orthographic projections of both the first and second insertion adapters 313a and 313b onto the substrate. The orthographic projection of the second first sequence adapter 314 onto the substrate does not overlap with the orthographic projections of both the first and second insertion adapters 313a and 313b onto the substrate.

[0267] In some examples, as shown in Figure 36B, the first insertion sequence adapter 313a may be located in the first source / drain metal layer, and the second insertion sequence adapter 313b may be located in the second source / drain metal layer. A first first sequence adapter 314 may be located in the first gate metal layer. The first connection electrode of the first connection terminal 311 connected to the first first sequence adapter 314 may be located in the first source / drain metal layer, the second connection electrode may be located in the first gate metal layer, the third connection electrode of the second connection terminal 312 connected to the first first sequence adapter 314 may be located in the first source / drain metal layer, and the fourth connection electrode may be located in the first gate metal layer. The first first sequence adapter 314, the second connection electrode of the connected first connection terminal 311, and the fourth connection electrode of the connected second connection terminal 312 may be an integrally connected structure. A second first sequence adapter 314 may be located in the second source / drain metal layer. However, this embodiment is not limited to this. In other examples, the first insertion sequence adapter may be located in the second source / drain metal layer, and the second insertion sequence adapter may be located in the first source / drain metal layer.

[0268] In some examples, as shown in Figure 36B, when the data signals transmitted at the second connection terminal 312 are configured to correspond sequentially to RGBG, after passing through four first adapter lines, the data signals transmitted at the first connection terminal 311 are configured to correspond sequentially to RGBG. This example, by setting the first adapter unit, allows the data signals corresponding to the first sub-pixel (e.g., red sub-pixel R) and the second sub-pixel (e.g., blue sub-pixel B) to be transmitted on the data lead-out lines located on the second gate metal layer (or the first gate metal layer), and allows the data signal corresponding to the third sub-pixel (e.g., green sub-pixel G) to be transmitted on the data lead-out lines located on the first gate metal layer (or the second gate metal layer), thereby ensuring the uniformity of signal transmission.

[0269] In some examples, as shown in Figure 36C, in the second direction D2, the first insertion sequence adapter cable 313a can connect the first first connection terminal 311 and the fourth second connection terminal 312; the first second insertion sequence adapter cable 313b can connect the third first connection terminal 311 and the first second connection terminal 312; the second second insertion sequence adapter cable 313b can connect the fourth first connection terminal 311 and the third second connection terminal 312; and the first sequence adapter cable 314 can connect the second first connection terminal and the second second connection terminal.

[0270] In some examples, as shown in FIG36C, the orthographic projection of the first sequence adapter 314 on the substrate overlaps with the orthographic projections of the first interpolation adapter 313a and the first second interpolation adapter 313b on the substrate, but may not overlap with the orthographic projection of the second second interpolation adapter 313b on the substrate. The orthographic projection of the first interpolation adapter 313a on the substrate may overlap with the orthographic projections of the two second interpolation adapters 313b on the substrate. In some examples, the first interpolation adapter 313a may be located in the first source / drain metal layer, the two second interpolation adapters 313b may be located in the second source / drain metal layer, and the first sequence adapter 314 may be located in the first gate metal layer. However, this embodiment is not limited in this respect.

[0271] Figure 37 is a schematic diagram of another arrangement of sub-pixels in a display area according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 37, each pixel unit of the display area may include: a first sub-pixel 15 emitting a first color light, a second sub-pixel 16 emitting a second color light, and a third sub-pixel 17 emitting a third color light. Multiple sub-pixels can be arranged in an array along a first direction D1 and a second direction D2. Multiple first sub-pixels 15 can be arranged in a column along the first direction D1, multiple second sub-pixels 16 can be arranged in a column along the first direction D1, and multiple third sub-pixels 17 can be arranged in a column along the first direction D1. The first sub-pixels 15, third sub-pixels 17, and second sub-pixels 16 can be arranged periodically along the second direction D2. In this example, the first sub-pixel 15 can be a red sub-pixel (R), the second sub-pixel 16 can be a blue sub-pixel (B), and the third sub-pixel 17 can be a green sub-pixel (G); the multiple sub-pixels can be arranged in a Real RGB configuration.

[0272] Figures 38A to 38F are example diagrams illustrating the connection method of multiple first adapter units according to at least one embodiment of the present disclosure. Figures 38A to 38F are illustrated using the sub-pixel arrangement of the display area as shown in Figure 37 as an example. In some examples, a group of first adapter units in the first border area can adopt the connection method of three first adapter units as shown in at least one of Figures 38A to 38F. The transmission order of the data signals of the data contact pads connected to the second connection ends of the multiple groups of first adapter units in this example can be obtained by referring to the 1-to-1 or multiple-to-1 method of the aforementioned embodiments.

[0273] In some examples, as shown in Figure 38A, in the second direction D2, the three first connection terminals 311 and the three second connection terminals 312 can be connected one-to-one via three first sequential connection lines 314. When the data signals transmitted at the second connection terminals 312 are configured to correspond sequentially to RGB, after passing through the three first sequential adapter lines 314, the data signals transmitted at the first connection terminals 311 are configured to correspond sequentially to RGB. For example, the three first sequential adapter lines 314 can all be located in the second source-drain metal layer.

[0274] In some examples, as shown in Figure 38B, in the second direction D2, three first connection terminals 311 and three second connection terminals 312 can be connected sequentially via a first sequential connection line 314, a first interpolation connection line 313a, and a second interpolation connection line 313b. Specifically, the first sequential connection line 314 connects the first first connection terminal 311 and the first second connection terminal 312; the first interpolation connection line 313a connects the second first connection terminal 311 and the third second connection terminal 312; and the second interpolation connection line 313b connects the third first connection terminal 311 and the second second connection terminal 312. The orthographic projections of the first interpolation connection line 313a and the second interpolation connection line 313b onto the substrate may overlap. For example, the first sequential connection line 314 and the second interpolation connection line 313b may be located in the second source / drain metal layer, and the first interpolation connection line 313a may be located in the first source / drain metal layer. When the data signals transmitted through the three second connection terminals 312 are configured to correspond to RBG in sequence, after passing through the three adapter cables, the data signals transmitted through the three first connection terminals 311 are configured to correspond to RGB in sequence.

[0275] In some examples, as shown in Figure 38C, in the second direction D2, three first connection terminals 311 and three second connection terminals 312 can be connected sequentially via a first interpolation connection line 313a, a second interpolation connection line 313b, and a first sequential connection line 314. Specifically, the first interpolation connection line 313a connects the first first connection terminal and the second second connection terminal, the second interpolation connection line 313b connects the second first connection terminal and the first second connection terminal, and the first sequential connection line 314 connects the third first connection terminal and the third second connection terminal. The orthographic projections of the first interpolation connection line 313a and the second interpolation connection line 313b onto the substrate may overlap. For example, the first sequential connection line 314 and the second interpolation connection line 313b may be located in the second source / drain metal layer, and the first interpolation connection line 313a may be located in the first source / drain metal layer. When the data signals transmitted by the three second connection terminals 312 are configured to correspond sequentially to GRB, after passing through the three first interpolation lines, the data signals transmitted by the three first connection terminals 311 are configured to correspond sequentially to RGB.

[0276] In some examples, as shown in Figure 38D, in the second direction D2, three first connection terminals 311 and three second connection terminals 312 can be connected sequentially via one first insertion adapter 313a and two second insertion adapters 313b. Specifically, the first insertion adapter 313a connects the first first connection terminal to the three second connection terminals, the first second insertion adapter 313b connects the second first connection terminal to the first second connection terminal, and the second second insertion adapter 313b connects the third first connection terminal to the second second connection terminal. The orthographic projection of the first insertion adapter 313a onto the substrate may overlap with the orthographic projection of the two second insertion adapters 313b onto the substrate. For example, the first insertion adapter 313a may be located in the first source / drain metal layer, and the two second insertion adapters 313b may be located in the second source / drain metal layer. When the data signals transmitted by the three second connection terminals 312 are configured to correspond sequentially to GBR, after passing through the three first adapters, the data signals transmitted by the three first connection terminals 311 are configured to correspond sequentially to RGB.

[0277] In some examples, as shown in Figure 38E, in the second direction D2, three first connection terminals 311 and three second connection terminals 312 can be connected sequentially via two first interpolation lines 313a and one second interpolation line 313b. Specifically, the first interpolation line 313a connects the first first connection terminal and the second second connection terminal, the second first interpolation line 313a connects the second first connection terminal and the third second connection terminal, and the second interpolation line 313b connects the third first connection terminal and the first second connection terminal. The orthographic projection of the second interpolation line 313b onto the substrate overlaps with the orthographic projection of the two first interpolation lines 313a onto the substrate. For example, the two first interpolation lines 313a can be located in the second source / drain metal layer, and the second interpolation line 313b can be located in the first source / drain metal layer. When the data signals transmitted by the three second connection terminals 312 are configured to correspond sequentially to BRG, after passing through the three first interpolation lines, the data signals transmitted by the three first connection terminals 311 are configured to correspond sequentially to RGB.

[0278] In some examples, as shown in Figure 38F, in the second direction D2, three first connection terminals 311 and three second connection terminals 312 can be connected sequentially via a first insertion line 313a, a first sequence line 314, and a second insertion line 313b. Specifically, the first insertion line 313a connects the first first connection terminal and the third second connection terminal, the first sequence line 314 connects the second first connection terminal and the second second connection terminal, and the second insertion line 313b connects the third first connection terminal and the first second connection terminal. The orthographic projection of the first insertion line 313a onto the substrate overlaps with the orthographic projections of the first sequence line 314 and the second insertion line 313b onto the substrate. For example, the first insertion line 313a can be located in the second source / drain metal layer, the second insertion line 313b can be located in the first source / drain metal layer, and the first sequence line 314 can be located in the first gate metal layer. When the data signals transmitted through the three second connection terminals 312 are configured to correspond to BGR in sequence, after passing through the three first adapter cables, the data signals transmitted through the three first connection terminals 311 are configured to correspond to RGB in sequence.

[0279] The display substrate provided in this embodiment, by setting multiple sets of first adapter units to connect multiple data leads and multiple data contact pads, can use multiple sets of first adapter units to adjust the order of data signals transmitted by the data contact pads. At the same time, with the addition of multiple sets of second adapter units to adjust the order of data signals, the jumper design in the second fan-out area can be avoided, which helps to reduce the defects caused by jumper design and thus improve the reliability of the display substrate.

[0280] This embodiment also provides a display substrate, including a substrate, multiple sub-pixels, multiple first data lines, multiple second data lines, multiple data connection lines, multiple data lead-out lines, and multiple sets of test circuits. The substrate includes a display area and a first border area located on one side of the display area along a first direction. The first border area includes a first signal access area and a trace lead-out area located between the first signal access area and the display area. Multiple sub-pixels are disposed on one side of the substrate and located in the display area. Multiple first data lines, multiple second data lines, and multiple data connection lines are located in the display area; the multiple first data lines and the multiple second data lines are configured to provide data signals to the multiple sub-pixels, and the multiple first data lines are connected to the multiple data connection lines. Multiple data lead-out lines are located in the trace lead-out area, and the multiple data lead-out lines are connected to the multiple second data lines and the multiple data connection lines. Multiple test circuits are located in the trace lead-out area and arranged sequentially along the second direction. Each test circuit is connected to m continuously arranged data leads, and the second direction intersects the first direction; m is an integer greater than 1. Each test circuit includes: a first test circuits and b second test circuits, where a and b are both integers greater than 0, and twice the sum of a and b equals m. The first test circuit includes: a first test transistor, a second test transistor, and a third test transistor; the gate of the first test transistor is connected to the first test control line, and the first electrode of the first test transistor is connected to the first test data line; the gate of the second test transistor is connected to the second test control line, and the first electrode of the second test transistor is connected to the second test data line; the second electrodes of the first test transistor and the second electrode of the second test transistor are connected to the same data lead-out line; the gate of the third test transistor is connected to the third test control line, and the first electrode of the third test transistor is connected to the third test data line. The second test circuit includes: a fourth test transistor, a fifth test transistor, and a sixth test transistor; the gate of the fourth test transistor is connected to the second test control line, the first terminal of the fourth test transistor is connected to the first test data line, the gate of the fifth test transistor is connected to the first test control line, the first terminal of the fifth test transistor is connected to the second test data line, and the second terminals of the fourth and fifth test transistors are connected to the same data lead; the gate of the sixth test transistor is connected to the third test control line, and the first terminal of the third test transistor is connected to the third test data line; the second terminals of the first, third, fourth, and sixth test transistors are connected to different data leads.

[0281] This embodiment adjusts the transmission order of test data signals by setting up multiple sets of test circuits, which avoids the jumper design in the second fan-out area, helps to reduce the defects caused by jumper design, and thus improves the reliability of the display substrate.

[0282] In some exemplary embodiments, the first test transistor, the second test transistor, and the third test transistor of the first test circuit are arranged along the first direction; the fourth test transistor, the fifth test transistor, and the sixth test transistor of the second test circuit are arranged along the first direction. The first test transistor and the fourth test transistor are aligned in the second direction, the second test transistor and the fifth test transistor are aligned in the second direction, and the third test transistor and the sixth test transistor are aligned in the second direction.

[0283] In some exemplary embodiments, m is 8; each set of test circuits includes: two first test circuits and two second test circuits; wherein, one first test circuit, two second test circuits and one first test circuit are arranged along the second direction.

[0284] In some exemplary embodiments, m is 12; each group of test circuits includes: three first test circuits and three second test circuits; wherein, one first test circuit, two second test circuits, two first test circuits and one second test circuit are arranged along the second direction; or, one first test circuit, one second test circuit, one first test circuit, two second test circuits and one first test circuit are arranged in the opposite direction to the second direction.

[0285] In some exemplary embodiments, m is 16; each group of test circuits includes: four first test circuits and four second test circuits; wherein, one first test circuit, two second test circuits, one first test circuit, one second test circuit, two first test circuits and one second test circuit are arranged along the second direction; or, one first test circuit, one second test circuit, one first test circuit, two second test circuits, one first test circuit, one second test circuit and one first test circuit are arranged in the opposite direction of the second direction.

[0286] In some exemplary embodiments, m is 20; each group of test circuits includes: five first test circuits and five second test circuits; wherein, one first test circuit, two second test circuits, one first test circuit, one second test circuit, one first test circuit, one second test circuit, two first test circuits and one second test circuit are arranged along the second direction; or, one first test circuit, one second test circuit, one first test circuit, one second test circuit, one first test circuit, two second test circuits, one first test circuit, one second test circuit and one first test circuit are arranged in the opposite direction of the second direction.

[0287] For further explanation of this embodiment, please refer to the description of the foregoing embodiments, and therefore it will not be repeated here.

[0288] Figure 39 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 39, the display substrate 910 can be an OLED display substrate. The display device 91 can be any product or component with display function, such as an OLED display device, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. However, this embodiment is not limited thereto.

[0289] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0290] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A display substrate, comprising: a substrate comprising a display area and a first bezel area located at one side of the display area along a first direction, the first bezel area comprising a first signal access area and a trace lead-out area located between the first signal access area and the display area; a plurality of sub-pixels located at one side of the substrate and in the display area; a plurality of first data lines, a plurality of second data lines, and a plurality of data connection lines located in the display area, the plurality of first data lines and the plurality of second data lines configured to provide data signals to the plurality of sub-pixels, the plurality of first data lines connected to the plurality of data connection lines; a plurality of data lead-out lines located in the trace lead-out area; a plurality of data contact pads located in the first signal access area; a plurality of first adapter units and a plurality of second adapter units located in the trace lead-out area, the plurality of first adapter units located at a side of the plurality of second adapter units away from the display area, the plurality of first adapter units arranged along a second direction, the plurality of second adapter units arranged along the second direction, the second direction intersecting the first direction; wherein the plurality of data lead-out lines are connected to the plurality of data contact pads through the plurality of first adapter units, and are connected to the plurality of second data lines and the plurality of data connection lines through the plurality of second adapter units, so that the order of the data signals provided by the plurality of data contact pads matches the order of the data signals required by the plurality of second data lines and the plurality of data connection lines arranged along the second direction. 2.The display substrate of claim 1, wherein, Each first adapter unit comprises m first connection ends, m second connection ends, and m first adapter lines, each first adapter line connected between one first connection end and one second connection end, each first connection end connected to one data lead-out line, and each second connection end connected to one data contact pad, the m first connection ends arranged along the second direction and corresponding to different first arrangement serial numbers, and the m second connection ends arranged along the second direction and corresponding to different second arrangement serial numbers. The m first adapter lines in each first adapter unit comprise a first insertion sequence adapter line, the first arrangement serial number corresponding to the first connection end connected by each first insertion sequence adapter line being different from the second arrangement serial number corresponding to the second connection end connected by each first insertion sequence adapter line, wherein m and a are both integers greater than 1, and m is greater than or equal to a. 3.The display substrate of claim 2, wherein, The a first insertion sequence adapter lines in each first adapter unit comprise a1 first insertion sequence adapter lines and a2 second insertion sequence adapter lines, a1 and a2 are both integers greater than 0, and the sum of a1 and a2 is a. The first arrangement serial number corresponding to the first connection end connected by the first insertion sequence adapter line is less than the second arrangement serial number corresponding to the second connection end connected by the first insertion sequence adapter line. The first arrangement serial number corresponding to the first connection end connected by the second insertion sequence adapter line is greater than the second arrangement serial number corresponding to the second connection end connected by the second insertion sequence adapter line. 4.The display substrate of claim 3, wherein, The difference between the second arrangement serial number corresponding to the second connecting end connected by the first plug-in sequence adapter line and the first arrangement serial number corresponding to the first connecting end connected by the first plug-in sequence adapter line is greater than or equal to the difference between the first arrangement serial number corresponding to the first connecting end connected by the second plug-in sequence adapter line and the second arrangement serial number corresponding to the second connecting end connected by the second plug-in sequence adapter line. 5.The display substrate of claim 3, wherein, The first plug-in sequence adapter line and at least one second plug-in sequence adapter line overlap in the orthographic projection on the substrate. 6.The display substrate according to any one of claims 3 to 5, wherein The m first adapter lines in each group of first adapter units further include b first sequence adapter lines, each first sequence adapter line has the same first arrangement serial number corresponding to the first connecting end connected by the first sequence adapter line and the second arrangement serial number corresponding to the second connecting end connected by the first sequence adapter line, b is an integer greater than 1, and b is less than or equal to a. 7.The display substrate of claim 6, wherein, The b first sequence adapter lines and the first plug-in sequence adapter line are in the same layer structure, or at least one first sequence adapter line is located on the side close to the substrate of the first plug-in sequence adapter line and the second plug-in sequence adapter line. 8.The display substrate of claim 6, wherein, M is 8. Each group of first adapter units includes eight first connecting ends, eight second connecting ends, and eight first adapter lines. The eight first connecting ends are arranged in sequence along the second direction. The eight second connecting ends are arranged in sequence along the second direction and located on the side close to the first signal access area of the eight first connecting ends. The eight first adapter lines include two first plug-in sequence adapter lines, two second plug-in sequence adapter lines, and four first sequence adapter lines. The first plug-in sequence adapter line is configured to connect the i th first connecting end and the i+1 th second connecting end. The second plug-in sequence adapter line is configured to connect the i+1 th first connecting end and the i th second connecting end. The value of i includes 1 and 5. 9.The display substrate of claim 8, wherein, One pixel unit located in the display area includes one first sub-pixel emitting first color light, one second sub-pixel emitting second color light, and two third sub-pixels emitting third color light. The plurality of data contact pads are configured to provide data signals to the sub-pixels of the e th row of pixel units in the display area in a first time period and to the sub-pixels of the e+1 th row of pixel units in the display area in a second time period, where e is an integer greater than 0. In the first time period, the data signals transmitted by the eight second connecting ends in each group of first adapter units are configured to correspond to the third sub-pixel, the first sub-pixel, the second sub-pixel, the third sub-pixel, the third sub-pixel, the second sub-pixel, the first sub-pixel, and the third sub-pixel in sequence, or are configured to correspond to the first sub-pixel, the third sub-pixel, the third sub-pixel, the second sub-pixel, the second sub-pixel, the third sub-pixel, the third sub-pixel, and the first sub-pixel in sequence. In the second time period, the data signals transmitted by the eight second connection terminals in each group of first switching units are configured to correspond to the third sub-pixel, the second sub-pixel, the first sub-pixel, the third sub-pixel, the third sub-pixel, the first sub-pixel, the second sub-pixel and the third sub-pixel in sequence, or are configured to correspond to the second sub-pixel, the third sub-pixel, the third sub-pixel, the first sub-pixel, the first sub-pixel, the third sub-pixel, the third sub-pixel and the second sub-pixel in sequence. 10.The display substrate of claim 6, wherein, m is 12; Each group of first switching units comprises twelve first connection terminals, twelve second connection terminals and twelve first switching lines. The twelve first connection terminals are arranged in sequence along the second direction. The twelve second connection terminals are arranged in sequence along the second direction and located on the side of the twelve first connection terminals close to the first signal access area. The twelve first switching lines comprise four first plug sequence switching lines, four second plug sequence switching lines and four first sequence switching lines. The first plug sequence switching line is configured to connect the i-th first connection terminal and the i+1-th second connection terminal. The second plug sequence switching line is configured to connect the i+1-th first connection terminal and the i-th second connection terminal. The value of i includes 1, 3, 7 and 9. 11.The display substrate of claim 10, wherein, One pixel unit located in the display area comprises one first sub-pixel emitting first color light, one second sub-pixel emitting second color light and two third sub-pixels emitting third color light. The plurality of data contact pads are configured to provide data signals to the sub-pixels of the e-th row of pixel units in the display area in a first time period and to the sub-pixels of the e+1-th row of pixel units in the display area in a second time period, where e is an integer greater than 0. In the first time period, the data signals transmitted by the twelve second connection terminals in each group of first switching units are configured to correspond to the third sub-pixel, the first sub-pixel, the third sub-pixel, the second sub-pixel, the second sub-pixel, the third sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, the first sub-pixel, the second sub-pixel and the third sub-pixel in sequence, or are configured to correspond to the first sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the third sub-pixel, the first sub-pixel, the second sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the third sub-pixel and the first sub-pixel in sequence. In the second time period, the data signals transmitted by the twelve second connection terminals in each group of first switching units are configured to correspond to the third sub-pixel, the second sub-pixel, the first sub-pixel, the third sub-pixel, the third sub-pixel, the first sub-pixel, the second sub-pixel and the third sub-pixel in sequence, or are configured to correspond to the second sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, the third sub-pixel, the second sub-pixel, the first sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, the third sub-pixel and the second sub-pixel in sequence. 12.The display substrate of claim 6, wherein, m is 16; Each group of first switching units comprises sixteen first connection ends, sixteen second connection ends, and sixteen first switching lines; the sixteen first connection ends are arranged in sequence along the second direction, the sixteen second connection ends are arranged in sequence along the second direction and located on the side of the sixteen first connection ends close to the first signal access area, and the sixteen first switching lines comprise four first plug sequence switching lines, four second plug sequence switching lines, and eight first order switching lines; The first plug sequence switching line is configured to connect the i-th first connection end and the i+1-th second connection end; The second plug sequence switching line is configured to connect the i+1-th first connection end and the i-th second connection end; Wherein, the value of i includes 1, 3, 9, and 11. 13.The display substrate of claim 12, wherein, One pixel unit located in the display area comprises a first sub-pixel emitting first color light, a second sub-pixel emitting second color light, and two third sub-pixels emitting third color light; The plurality of data contact pads are configured to provide data signals to the sub-pixels of the e-th row of pixel units in the display area in a first time period and to the sub-pixels of the e+1-th row of pixel units in the display area in a second time period, where e is an integer greater than 0; In the first time period, the data signals transmitted by the sixteen second connection ends in each group of first switching units are configured to correspond to the third sub-pixel, the first sub-pixel, the third sub-pixel, the second sub-pixel, the second sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the first sub-pixel, the first sub-pixel, the third sub-pixel, the second sub-pixel, and the third sub-pixel in sequence, or are configured to correspond to the first sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, the second sub-pixel, the second sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, and the first sub-pixel in sequence; In the second time period, the data signals transmitted by the sixteen second connection ends in each group of first switching units are configured to correspond to the third sub-pixel, the second sub-pixel, the third sub-pixel, the first sub-pixel, the first sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, the second sub-pixel, the second sub-pixel, the third sub-pixel, the first sub-pixel, and the third sub-pixel in sequence, or are configured to correspond to the second sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the first sub-pixel, the first sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, and the second sub-pixel in sequence. m is 20; 14.The display substrate of claim 6, wherein, ​ Each group of first switching units comprises twenty first connection ends, twenty second connection ends and twenty first switching lines; the twenty first connection ends are arranged in sequence along the second direction, the twenty second connection ends are arranged in sequence along the second direction and located on the side of the twenty first connection ends close to the first signal access area, and the twenty first switching lines comprise six first plug sequence switching lines, six second plug sequence switching lines and eight first order switching lines; The first plug sequence switching line is configured to connect the i-th first connection end and the i+1-th second connection end; The second plug sequence switching line is configured to connect the i+1-th first connection end and the i-th second connection end; Wherein, the value of i includes 1, 3, 5, 11, 13 and 15. 15.The display substrate of claim 14, wherein, One pixel unit located in the display area comprises a first sub-pixel emitting first color light, a second sub-pixel emitting second color light and two third sub-pixels emitting third color light; The plurality of data contact pads are configured to provide data signals to the sub-pixels of the e-th row of pixel units in the display area in a first time period and to the sub-pixels of the e+1-th row of pixel units in the display area in a second time period, where e is an integer greater than 0; In the first time period, the data signals transmitted by the twenty second connection ends in each group of first switching units are configured to correspond to the third sub-pixel, the first sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the second sub-pixel, the first sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the first sub-pixel, the first sub-pixel, the third sub-pixel, the second sub-pixel and the third sub-pixel in sequence; or, are configured to correspond to the first sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the first sub-pixel, the second sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel and the first sub-pixel in sequence; In the second time period, the data signals transmitted by the twenty second connection ends in each group of first switching units are configured to correspond to the third sub-pixel, the second sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, the first sub-pixel, the second sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, the second sub-pixel, the second sub-pixel, the third sub-pixel, the first sub-pixel and the third sub-pixel in sequence; or, are configured to correspond to the second sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, the second sub-pixel, the first sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel and the second sub-pixel in sequence. 16.The display substrate of claim 2, wherein, One pixel unit located in the display region comprises: a first sub-pixel for emitting first color light, a second sub-pixel for emitting second color light, and two third sub-pixels for emitting third color light; The plurality of data lead-out lines connected with the first connection ends of the plurality of groups of first switching units comprises: a first group of data lead-out lines and a second group of data lead-out lines, the first group of data lead-out lines and the second group of data lead-out lines are located in different conductive layers and are arranged alternately along the second direction, the first group of data lead-out lines are configured to transmit data signals required by the third sub-pixels, and the second group of data lead-out lines are configured to transmit data signals required by the first sub-pixels and the second sub-pixels.

17. The display substrate of any one of claims 1-16, further comprising: The plurality of groups of test circuits are located in the wiring lead-out region and are arranged in sequence along the second direction. The plurality of groups of test circuits are located on the side of the plurality of groups of first switching units away from the first signal access region in the first direction; one group of test circuits is connected with m data lead-out lines connected with one group of first switching units; the second direction intersects the first direction; Each group of test circuits comprises: a first test circuit and b second test circuits; the sum of a and b is twice m, and a and b are both integers greater than 0. The first test circuit comprises: a first test transistor, a second test transistor and a third test transistor; the gate of the first test transistor is connected with a first test control line, the first pole of the first test transistor is connected with a first test data line, the gate of the second test transistor is connected with a second test control line, the first pole of the second test transistor is connected with a second test data line, and the second pole of the first test transistor and the second pole of the second test transistor are connected with the same data lead-out line; the gate of the third test transistor is connected with a third test control line, and the first pole of the third test transistor is connected with a third test data line. The second test circuit comprises: a fourth test transistor, a fifth test transistor and a sixth test transistor; the gate of the fourth test transistor is connected with the second test control line, the first pole of the fourth test transistor is connected with the first test data line, the gate of the fifth test transistor is connected with the first test control line, the first pole of the fifth test transistor is connected with the second test data line, and the second pole of the fourth test transistor and the second pole of the fifth test transistor are connected with the same data lead-out line; the gate of the sixth test transistor is connected with the third test control line, and the first pole of the third test transistor is connected with the third test data line; the second pole of the first test transistor, the second pole of the third test transistor, the second pole of the fourth test transistor and the second pole of the sixth test transistor are connected with different data lead-out lines. 18.The display substrate of claim 17, wherein, The first test transistor, the second test transistor and the third test transistor of the first test circuit are arranged along the first direction; the fourth test transistor, the fifth test transistor and the sixth test transistor of the second test circuit are arranged along the first direction. The first test transistor and the fourth test transistor are arranged in alignment in the second direction, the second test transistor and the fifth test transistor are arranged in alignment in the second direction, and the third test transistor and the sixth test transistor are arranged in alignment in the second direction.

19. The display substrate of claim 17 or 18, wherein, m is 8; Each group of test circuits comprises two first test circuits and two second test circuits; wherein one first test circuit, two second test circuits and one first test circuit are arranged along the second direction. 20.The display substrate according to claim 17 or 18, wherein, m is 12; Each group of test circuits comprises three first test circuits and three second test circuits; wherein one first test circuit, two second test circuits, two first test circuits and one second test circuit are arranged along the second direction, or one first test circuit, one second test circuit, one first test circuit, two second test circuits and one first test circuit are arranged along the opposite direction of the second direction.

21. The display substrate of claim 17 or 18, wherein, m is 16; Each group of test circuits comprises four first test circuits and four second test circuits; wherein one first test circuit, two second test circuits, one first test circuit, one second test circuit, two first test circuits and one second test circuit are arranged along the second direction, or one first test circuit, one second test circuit, one first test circuit, two second test circuits, one first test circuit, one second test circuit and one first test circuit are arranged along the opposite direction of the second direction.

22. The display substrate of claim 17 or 18, wherein, m is 20; Each group of test circuits comprises five first test circuits and five second test circuits; wherein one first test circuit, two second test circuits, one first test circuit, one second test circuit, one first test circuit, one second test circuit, two first test circuits and one second test circuit are arranged along the second direction, or one first test circuit, one second test circuit, one first test circuit, one second test circuit, one first test circuit, two second test circuits, one first test circuit, one second test circuit and one first test circuit are arranged along the opposite direction of the second direction. The single pixel unit of the display area comprises c sub-pixels, m is k times of c, and k is an integer greater than 1. 23.The display substrate according to any one of claims 1 to 22, wherein 24. A display device comprising the display substrate according to any one of claims 1 to 23.

25. A display substrate comprising: a substrate comprising a display area and a first frame area located on one side of the display area along a first direction, the first frame area comprising a first signal access area and a wire leading-out area located between the first signal access area and the display area; a plurality of sub-pixels located on one side of the substrate and in the display area; a plurality of first data lines, a plurality of second data lines and a plurality of data connection lines located in the display area, the plurality of first data lines and the plurality of second data lines being configured to provide data signals to the plurality of sub-pixels, and the plurality of first data lines being connected to the plurality of data connection lines; ​ A plurality of data lead-out lines are located in the lead-out area, and are connected with the plurality of second data lines and the plurality of data connection lines; A plurality of test circuits are located in the lead-out area and are arranged in a second direction in sequence, each test circuit is connected with m continuously arranged data lead-out lines, the second direction is perpendicular to the first direction; m is an integer greater than 1; Each test circuit includes a first test circuit and a second test circuit, a and b are both integers greater than 0, and twice the sum of a and b is equal to m; The first test circuit includes a first test transistor, a second test transistor and a third test transistor; the gate of the first test transistor is connected with a first test control line, the first pole of the first test transistor is connected with a first test data line, the gate of the second test transistor is connected with a second test control line, the first pole of the second test transistor is connected with a second test data line, and the second pole of the first test transistor and the second pole of the second test transistor are connected with the same data lead-out line; the gate of the third test transistor is connected with a third test control line, and the first pole of the third test transistor is connected with a third test data line; The second test circuit includes a fourth test transistor, a fifth test transistor and a sixth test transistor; the gate of the fourth test transistor is connected with the second test control line, the first pole of the fourth test transistor is connected with the first test data line, the gate of the fifth test transistor is connected with the first test control line, the first pole of the fifth test transistor is connected with the second test data line, and the second pole of the fourth test transistor and the second pole of the fifth test transistor are connected with the same data lead-out line; the gate of the sixth test transistor is connected with the third test control line, and the first pole of the third test transistor is connected with the third test data line; the second pole of the first test transistor, the second pole of the third test transistor, the second pole of the fourth test transistor and the second pole of the sixth test transistor are connected with different data lead-out lines. 26.The display substrate of claim 25, wherein, The first test transistor, the second test transistor and the third test transistor of the first test circuit are arranged in the first direction; the fourth test transistor, the fifth test transistor and the sixth test transistor of the second test circuit are arranged in the first direction; The first test transistor and the fourth test transistor are arranged in alignment in the second direction, the second test transistor and the fifth test transistor are arranged in alignment in the second direction, and the third test transistor and the sixth test transistor are arranged in alignment in the second direction. m is 8; 27. The display substrate of claim 25, wherein, Each test circuit includes two first test circuits and two second test circuits; one first test circuit, two second test circuits and one first test circuit are arranged along the second direction. m is 12; 28.The display substrate of claim 25, wherein, ​ Each group of test circuits comprises three first test circuits and three second test circuits; wherein one first test circuit, two second test circuits, two first test circuits and one second test circuit are arranged along the second direction; or one first test circuit, one second test circuit, one first test circuit, two second test circuits and one first test circuit are arranged along the reverse direction of the second direction. 29.The display substrate of claim 25, wherein, m is 16; Each group of test circuits comprises four first test circuits and four second test circuits; wherein one first test circuit, two second test circuits, one first test circuit, one second test circuit, two first test circuits and one second test circuit are arranged along the second direction; or one first test circuit, one second test circuit, one first test circuit, two second test circuits, one first test circuit, one second test circuit and one first test circuit are arranged along the reverse direction of the second direction. 30.The display substrate of claim 25, wherein, m is 20; Each group of test circuits comprises five first test circuits and five second test circuits; wherein one first test circuit, two second test circuits, one first test circuit, one second test circuit, one first test circuit, one second test circuit, two first test circuits and one second test circuit are arranged along the second direction; or one first test circuit, one second test circuit, one first test circuit, one second test circuit, one first test circuit, two second test circuits, one first test circuit, one second test circuit and one first test circuit are arranged along the reverse direction of the second direction.

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