Semiconductor structure and preparation method therefor

Abstract

A semiconductor structure and a preparation method therefor. The semiconductor structure comprises: bit lines, wherein the bit lines extend in a first direction and are spaced apart from each other in a second direction, and the first direction intersects with the second direction; shielding lines, respectively located between every two adjacent bit lines and extending in the first direction, wherein the shielding lines and the bit lines are alternately arranged in the second direction; active pillars, located on the bit lines and arranged in an array in the first direction and the second direction; and bit line contact structures, wherein each bit line contact structure is located between the corresponding bit line and the corresponding active pillar, and is connected to the bit line and the active pillar, and the width of the bit line contact structure in the second direction is less than the width of the bit line and the width of the active pillar in the second direction.

Description

Semiconductor structure and method of manufacturing the same

[0001] This application claims priority to the Chinese patent application No. 202410452734.7, filed on April 15, 2024, entitled "Semiconductor structure and method of manufacturing the same", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the technical field of integrated circuits, and in particular to a semiconductor structure and a method of manufacturing the same. BACKGROUND

[0003] With the development of Dynamic Random Access Memory (DRAM) technology, the size of the memory cell is getting smaller and smaller, and the array architecture is evolving from 8F 2 to 6F 2 to 4F 2 (F: the minimum pattern size that can be obtained under given process conditions).

[0004] However, in the structure designed at 4F 2 , how to minimize the area of the single array region transistor and pursue higher chip area utilization rate is still a problem to be solved.

[0005] SUMMARY

[0006] Therefore, the present application provides a semiconductor structure and a method of manufacturing the same, which can reduce the device volume and reduce the difficulty of the manufacturing process.

[0007] In one aspect, according to some embodiments, the present application provides a semiconductor structure, characterized in that it comprises:

[0008] active pillars arranged in an array in a first direction and a second direction, the first direction intersecting the second direction;

[0009] bit lines extending in the first direction and arranged at intervals in the second direction, and connecting the active pillars arranged in the first direction;

[0010] shield lines located between two adjacent bit lines and extending in the first direction, and arranged alternately with the bit lines in the second direction;

[0011] bit line contact structures located between the bit lines and the active pillars and connecting the bit lines and the active pillars, the width of the bit line contact structure in the second direction being smaller than the width of the bit lines and the active pillars in the second direction.

[0012] In some embodiments, the bit line contact structure connects two adjacent active pillars in the second direction.

[0013] In some embodiments, the shield line has a width in the third direction that is not less than a width of the bit line in the third direction, the third direction intersecting the first direction and the second direction.

[0014] In some embodiments, the width of the bit line decreases as the bit line extends toward the bit line contact structure.

[0015] In some embodiments, the semiconductor structure further comprises:

[0016] a bit line protection layer on a side of the bit line away from the bit line contact structure;

[0017] a bit line isolation layer between two adjacent bit lines, the shield line being in the bit line isolation layer;

[0018] The bit line protection layer and the bit line isolation layer are made of different materials.

[0019] In some embodiments, the bit line comprises at least one layer of metal material.

[0020] The shield line comprises at least one layer of metal material.

[0021] In some embodiments, the semiconductor structure further comprises:

[0022] a shield line blocking layer covering the shield line layer.

[0023] In some embodiments, there is a gap between the bit line isolation layer and the shield line.

[0024] In some embodiments, the shield line has a cross-sectional shape perpendicular to the first direction that is conical, strip-shaped, elliptical, star-shaped, or other suitable shape.

[0025] In some embodiments, the semiconductor structure further comprises:

[0026] a word line extending in the second direction and spaced apart in the first direction, the word line being connected to the active pillar in the second direction;

[0027] a storage structure connected to the active pillar and located at an end of the active pillar away from the bit line.

[0028] In another aspect, the present application also provides, according to some embodiments, a method for manufacturing a semiconductor structure, comprising:

[0029] forming an active pillar, the active pillar being arranged in an array in a first direction and a second direction, the first direction intersecting the second direction;

[0030] forming bit lines, the bit lines extending in the first direction, spaced apart in the second direction, and connected to the active pillars arranged in the first direction;

[0031] forming shield lines, the shield lines located between two adjacent bit lines, and extending in the first direction, alternately arranged with the bit lines in the second direction;

[0032] forming bit line contact structures, the bit line contact structures connecting the bit lines and the active pillars, the bit line contact structures having a width in the second direction smaller than the width of the bit lines and the active pillars in the second direction.

[0033] In some embodiments, the forming bit lines comprises:

[0034] providing a substrate, the substrate having a first surface and a second surface in a third direction, the third direction intersecting the first direction and the second direction;

[0035] patterning and etching bit line isolation trenches on the first surface, the bit line isolation trenches having a bottom size larger than a top size, the bit line isolation trenches extending in the first direction, spaced apart in the second direction;

[0036] filling the bit line isolation trenches to form bit line isolation layers;

[0037] grinding the second surface to expose the bit line isolation layers, and etching the substrate to form bit line trenches using the bit line isolation layers as a mask;

[0038] filling the bit line trenches with at least one layer of metal material to form the bit lines;

[0039] forming bit line protection layers on the bit lines, the bit line protection layers being different from the bit line isolation layer material.

[0040] In some embodiments, the forming shield lines comprises:

[0041] etching the bit line isolation layers to form shield line trenches using the bit line protection layers as a mask on the second surface, the shield line trenches having a depth not less than the depth of the bit line trenches;

[0042] filling the shield line trenches with at least one layer of metal material to form the shield lines.

[0043] In some embodiments, the bit line contact structures comprise metal silicide, and forming metal silicide comprises:

[0044] depositing a layer of metal material at the bottom of the bit line trenches, and high-temperature processing to form metal silicide; or

[0045] Depositing a metal material layer at the bottom of the bit line isolation trench, and high-temperature processing to form a metal silicide.

[0046] In some embodiments, after filling the bit line isolation trench to form a bit line isolation layer, the method further comprises:

[0047] forming word line isolation trenches on the first surface by patterned etching, the word line isolation trenches having a depth less than that of the bit line isolation trenches, the bit line isolation trenches extending in a second direction and being spaced apart in a first direction, the word line isolation trenches and the bit line isolation trenches forming the active pillars;

[0048] After forming the active pillars, the method further comprises:

[0049] forming word lines in the word line isolation trenches, the word lines extending in the second direction and being spaced apart in the first direction, the word lines being connected to the active pillars in the second direction;

[0050] forming a storage structure at an end of the active pillars away from the bit line.

[0051] The semiconductor structure and the method for manufacturing the same provided by the present application have at least the following beneficial effects:

[0052] The semiconductor structure and the method for manufacturing the same provided by the present application can reduce the resistance of the bit line by forming a metal bit line on the back of the wafer, and can reduce the coupling capacitance between adjacent bit lines by forming a metal shielding line between the bit lines, thereby improving the stability of the device. By using different etching selectivity ratios between the substrate, the bit line isolation layer and the bit line protection layer, and using a self-aligned etching process, the number of masks can be reduced, and the production cost can be reduced. In addition, adjacent bit lines can share one bit line, which can reduce the difficulty of the device process. BRIEF DESCRIPTION OF DRAWINGS

[0053] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort.

[0054] FIG. 1a is a top view of a semiconductor structure provided by some disclosed embodiments, and FIGS. 1b and 1c are cross-sectional structure schematic views in the direction of the bit line and the word line, respectively;

[0055] FIG. 2 is a cross-sectional structure schematic view of a semiconductor structure provided by some embodiments of the present application in the direction of the word line;

[0056] Fig. 3a-3e are schematic cross-sectional views of a semiconductor structure along a word line direction according to some embodiments of the present application;

[0057] Fig. 4a-4l are schematic cross-sectional views of a semiconductor structure along a word line direction according to some embodiments of the present application;

[0058] Fig. 5a-5f are schematic cross-sectional views of a semiconductor structure along a word line direction according to some embodiments of the present application;

[0059] BRIEF DESCRIPTION OF DRAWINGS 1, substrate; 2, word line; 3, bit line; 4, active pillar; 5, word line isolation trench; 6, bit line isolation trench; 601, initial bit line isolation trench; 602, first bit line isolation trench; 603, second bit line isolation trench; 7, sidewall protection layer; 8, bit line isolation layer; 9, storage contact; 10, bit line contact structure; 11, storage structure; 12, bit line trench; 13, bit line material layer; 301, first bit line material layer; 302, second bit line material layer; 14, bit line protection layer; 15, shield line trench; 16, shield line; 1601, first shield line material layer; 1602, second shield line material layer; 17, void; 18, shield line barrier layer. DETAILED DESCRIPTION

[0060] For the purpose of the present application, the following description will be made with reference to the accompanying drawings. In the drawings, preferred embodiments of the present application are shown. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of the present application is more thorough and complete.

[0061] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0062] It will be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on or connected to the other element or layer, or intervening elements or layers can be present. In addition, it will be understood that, when a term is used in the singular, it can be intended to include the plural, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0063] Spatially relative terms, such as "on", "above", "below", "bottom", "top", "side", "upper", "lower", "horizontal", "vertical", and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. For example, if a device in the figures is turned over, elements described as "above" other elements or features would then be oriented "below" the other elements or features. Thus, the exemplary term "above" can encompass both an orientation that is above and below. The device can be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0064] As used herein, the singular forms "a", "an" and "the" include plural referents unless the context clearly dictates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0065] Embodiments of the application are described herein with reference to the drawings, which are idealized illustrations of cross-sectional views of schematic diagrams of embodiments of the application (and intermediate structures) as idealized embodiments of the application. It is expected that variations in the shapes of the illustrated shapes will occur as a result, for example, of manufacturing processes and / or tolerances, and therefore the embodiments of the application should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. The regions illustrated in the figures are schematic and many of the regions are not drawn to scale. Therefore, embodiments of the application should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. The regions illustrated in the figures are schematic and many of the regions are not drawn to scale. Thus, the shapes and relative proportions of the regions illustrated in the figures should not be construed as limiting.

[0066] Referring to FIG. 1a, in some related embodiments, a semiconductor structure can include a plurality of bit lines 3 extending along a first direction (e.g., X direction) and arranged along a second direction (e.g., Y direction), a plurality of word lines 2 extending along the second direction and arranged along the first direction, the bit lines 3 and the word lines 2 intersecting at active pillars 4 in space, and the plurality of active pillars 4 extending along a third direction (e.g., Z direction) perpendicular to the substrate 1 and arranged in an array. In the preparation of the bit lines 3, first, a bit line isolation trench 6 is formed and filled, as shown in FIG. 1c, then a word line isolation trench 5 is etched, as shown in FIG. 1b, and the substrate is modified in the word line isolation trench by ion implantation, doping or metal diffusion to form the bit lines 3. As the size of the bit lines 3 becomes smaller and smaller, the resistance of the bit lines 3 becomes larger and larger, and at the same time, the distance between adjacent bit lines 3 becomes smaller and smaller, and the corresponding coupling effect becomes larger and larger, which greatly affects the performance of the semiconductor structure. In addition, the process of forming the bit lines 3 also causes certain damage to the word line isolation trench, the storage contact and the active pillar, which greatly limits the development of the semiconductor structure preparation process.

[0067] The present application provides a semiconductor structure and a preparation method thereof, which can reduce the size of the device, and the details will be described in the subsequent embodiments.

[0068] In one aspect, the present application provides a semiconductor structure according to some embodiments.

[0069] Referring to FIG. 2, in some embodiments, the semiconductor structure can include a plurality of bit lines 3, a plurality of active pillars 4, a plurality of shield lines 16 and bit line contact structures 10. The plurality of bit lines 3 extend along a first direction (e.g., X direction) and are arranged along a second direction (e.g., Y direction) with a spacing, the first direction intersecting the second direction; the plurality of shield lines 16 are located between adjacent two bit lines 3 and extend along the first direction, and are arranged alternately with the bit lines 3 along the second direction; the plurality of active pillars 4 extend along a third direction (e.g., Z direction) away from the bit lines 3 and are arranged in an array along the first direction and the second direction; and the bit line contact structures 10 are located between the bit lines 3 and the active pillars 4 and connect the bit lines 3 and the active pillars 4, and the width of the bit line contact structures 10 along the second direction is smaller than the width of the bit lines 3 and the active pillars 4 along the second direction.

[0070] In the semiconductor structure provided in the above embodiments, the shield lines 16 are located between adjacent bit lines 3 and are arranged alternately with the bit lines 3 along the second direction, the shield lines 16 can reduce the coupling effect between adjacent two bit lines 3 and provide stability of the semiconductor structure. The width of the bit line contact structures 10 along the second direction is smaller than the width of the bit lines 3 and the active pillars 4 along the second direction, which can increase the width of the bit lines 3 along the second direction, reduce the resistance of the bit lines 3, and at the same time, reduce the difficulty of preparation of the bit lines 3.

[0071] Referring to FIG. 2 and FIG. 3a, in some embodiments, one bit line contact structure can connect one active pillar 4, and one bit line contact structure 10 can also connect two adjacent active pillars 4 in the second direction, as shown in FIG. 2, that is, two adjacent active pillars 4 share one bit line contact structure 10 and one bit line 3, which can reduce the bit line density, increase the integration, increase the distance between bit lines, and also increase the width of the bit line 3, reduce the resistance of the bit line 3, and improve the performance of the device.

[0072] Referring to FIG. 2, in some embodiments, the width D1 of the shielding line 16 in the third direction (for example, the Z direction) is not less than the width D2 of the bit line 3 in the third direction (for example, the Z direction), and the width D1 of the shielding line 16 in the third direction (for example, the Z direction) is greater than the width D2 of the bit line 3 in the third direction (for example, the Z direction), and optionally, the width D1 of the shielding line 16 in the third direction (for example, the Z direction) is greater than the sum of the width of the bit line 3 and the width of the bit line contact structure 10 in the third direction (for example, the Z direction), so that the shielding line 16 can completely shield the coupling effect between adjacent bit lines 3, and improve the performance of the device.

[0073] Referring to FIG. 2, in some embodiments, the width of the bit line 3 in the second direction (for example, the Y direction) decreases as the bit line extends to the bit line contact structure, which can be understood as a reverse trapezoidal shape, which can reduce the resistance of the bit line 3 and reduce the difficulty of the preparation process of the bit line 3.

[0074] Referring to FIG. 2, in some embodiments, the semiconductor structure can include a bit line protection layer 14 and a bit line isolation layer 8, the bit line protection layer 14 is located on the side of the bit line 3 away from the bit line contact structure 10 and extends in the first direction (for example, X), and is arranged in the second direction (for example, Y), and the bit line isolation layer 8 is located between adjacent bit lines 3 to insulate and isolate adjacent bit lines. The materials of the bit line protection layer 14 and the bit line isolation layer 8 are not specifically limited. As an example, the material of the bit line protection layer 14 can include but is not limited to silicon nitride, silicon oxide, silicon oxynitride, and silicon carbon nitride, or a combination thereof, and the material of the bit line isolation layer 8 can include but is not limited to silicon nitride, silicon oxide, silicon oxynitride, and silicon carbon nitride, or a combination thereof. However, the materials of the bit line isolation layer 8 and the bit line protection layer 14 must be different, for example, the bit line protection layer 14 can be silicon nitride, and the bit line isolation layer can be silicon oxide, so that in the etching of the bit line isolation layer 8, a self-aligned method can be used, taking the bit line protection layer 14 as a template, and selectively etching the bit line isolation layer 8, which can reduce the process difficulty and save costs.

[0075] Please continue to refer to FIG. 2 and refer to FIG. 3c, in some embodiments, the bit line 3 and the shield line 16 can be one layer or multiple layers, for example, in FIG. 3c, the bit line 3 includes a bit line first material layer 301 and a bit line second material layer 302, the positional relationship of the bit line first material layer 301 and the bit line second material layer 302 is not specifically limited, for example, the bit line first material layer 301 and the bit line second material layer 302 can be stacked, surrounded, and half surrounded, etc. The shield line 16 can include a shield line first material layer 1601 and a shield line second material layer 1602, the positional relationship of the shield line first material layer 1601 and the shield line second material layer 1602 is not specifically limited, for example, the shield line first material layer 1601 and the shield line second material layer 1602 can be stacked, surrounded, and half surrounded, etc. The material of the bit line 3 and the shield line 16 is not specifically limited, for example, the material of the bit line 3 can include, for example, doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or a combination thereof. For example, the bit line 3 can include but is not limited to doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, or a combination thereof. The material of the shield line 16 can include, for example, doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or a combination thereof. For example, the shield line 16 can include but is not limited to doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, or a combination thereof. The bit line 3 and the shield line 16 at least include a metal material layer, which can reduce the resistance of the bit line 3 and the shield line 16 and improve the performance of the device.

[0076] Please continue to refer to FIG. 2, in some embodiments, the semiconductor structure can include a direct current bias (DC bias), the DC bias and the shield line 16 can be connected through a connection contact (not shown), to give the shield line 16 a stable voltage, so that the shield line 16 forms a conductive barrier, and when one of the two adjacent bit lines 3 is powered on or powered off, the other one is less affected or not affected.

[0077] Referring to FIG. 3b, in some embodiments, the shield line 16 does not completely contact the bit line isolation layer 8 at least in some portions, and there is a gap 17 between the shield line 16 and the bit line isolation layer 8. The relative position of the gap 17 between the shield line 16 and the bit line isolation layer 8 is not specifically limited, and as an example, the gap 17 can be located at the bottom of the shield line, one side of the sidewall, and semi-surrounding the shield line, etc. The size and shape of the gap 17 are also not specifically limited, and as an example, the gap can be spherical, droplet-shaped, short tube-shaped, ellipsoidal, long strip-shaped, or other suitable shapes. Since the dielectric constant of air is 1.001, close to the dielectric constant of vacuum, the gap 17 and the bit line isolation layer 8 together embody a low dielectric constant effect to reduce the overall dielectric constant, which can reduce the parasitic capacitance and avoid the capacitive coupling effect between the bit line 3 and the adjacent bit line 3, thereby reducing the influence of the parasitic capacitance on the performance parameters of the device.

[0078] Referring to FIG. 3d, in some embodiments, the shield line 16 has an irregular structure in the cross-sectional shape perpendicular to the first direction, which can be, for example, conical, long strip-shaped, oval, star-shaped, or other suitable shapes. The shield line is formed in the bit line isolation layer 8, and the size of the shield line 16 is affected by the material of the bit line isolation layer 8 and the etching ability of the equipment. The shield line 16 in an irregular structure can increase the process preparation window and reduce the preparation process cost.

[0079] Referring to FIG. 3e, in some embodiments, a shield line blocking layer 18 can also be provided above the shield line 16, which covers the shield line 16 and can protect the shield line 16 from being damaged in subsequent processes. The material of the shield line blocking layer 18 is not limited and can be the same as or different from the material of the bit line protection layer 14.

[0080] Referring to FIGS. 2 and 3a-3e, in some embodiments, the semiconductor structure further includes a word line 2, a storage contact 9 at one end of the active pillar, a storage structure 11, and a back-end-of-line and protection layer (not shown in the figure) located on the storage structure 11. Specifically, the word line 2 extends along the second direction and is arranged in the first direction. The word line surrounds the active pillar 4 on one side, two sides, or three sides and controls the charge movement of the active pillar 4. The material of the word line is not specifically limited, and as an example, the material of the word line 2 can include, for example, doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or a combination thereof. For example, the word line 2 can include but is not limited to doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, or a combination thereof.

[0081] The storage contact 9 is located at the end of the active pillar 4 away from the bit line contact 10, connecting the active pillar 4 and the storage structure 11, and the material of the storage contact 9 is not limited, for example, the material of the storage contact 9 can include at least one of doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi and combinations thereof, which can reduce the contact resistance between the active pillar 4 and the storage structure 11.

[0082] The storage structure 11 can be a capacitor structure including upper and lower electrode plates and a high-k dielectric material between the upper and lower electrode plates, or a variable resistance storage structure which is switched to two resistance states by an electrical pulse applied to the memory element, for example, the variable resistance storage structure can include a phase change material, a perovskite compound, a transition metal oxide, a magnetic material, a ferromagnetic material or an antiferromagnetic material whose crystal state changes according to the amount of current.

[0083] In another aspect, the present application also provides a method for manufacturing a semiconductor structure according to some embodiments. In order to more clearly illustrate the method for manufacturing a semiconductor structure according to some embodiments of the present application, the following can be understood in combination with FIGS. 1-3.

[0084] FIGS. 4a-4l are views showing intermediate steps for describing a method for manufacturing a semiconductor memory device according to some embodiments.

[0085] Referring to FIG. 4a, a substrate 1 is provided, which has opposite first and second surfaces in a third direction (e.g., Z direction), and an initial bit line isolation trench 601 is formed by patterning and etching the first surface.

[0086] Specifically, in some embodiments, the material of the substrate 1 is not limited, for example, the material of the substrate 1 can include silicon (Si), silicon germanium (SiGe), silicon germanium carbon (SiGeC), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), indium phosphide (InP) or other III / V semiconductor materials or II / VI semiconductor materials, etc.

[0087] In some embodiments, the forming of the initial bit line isolation groove 601 by the patterned etching can include forming a mask layer on the first surface of the substrate 1, the mask layer can include one, two or more layers of material, depositing a photoresist layer, exposing and developing the photoresist layer, and then etching the mask layer and the substrate 1 to form the initial bit line isolation groove 601. The etching method can use dry etching, wet etching or a combination of both, without specific limitation. Referring to FIG. 2 and FIG. 3a, one column of active pillars 4 can be connected to one column of bit lines 3, or two adjacent columns of active pillars 4 can share one column of bit lines 3. In this way, two adjacent columns of active pillars 4 can share one bit line, which can reduce the space between adjacent bit lines, reduce the size of the device, and make the internal layout of the semiconductor structure more reasonable, thereby effectively improving the storage density of the semiconductor structure. In this embodiment, two columns of active pillars 4 share one bit line 3 as an example, and the initial bit line isolation groove 601 is formed with a double pitch, i.e. the distance between adjacent initial bit line isolation grooves 601 is twice the distance between an active pillar 4 and a bit line isolation groove 6. In this way, the process preparation window can be increased, and the stability of the device performance can be improved.

[0088] Referring to FIG. 4b, in some embodiments, the mask layer that has not been etched away is modified to have a size that matches the width of the bit line groove 6, or the width of the exposed substrate that has not been etched away is equivalent to the width of the active pillar 4. The specific width is not limited, and can be any width between 10 nm and 40 nm, for example, according to process requirements. A sidewall protection layer 7 is deposited on the first surface of the substrate and the surface of the mask layer that has not been etched away on the first surface of the substrate. The sidewall protection layer 7 can protect the first surface of the substrate and the surface of the mask layer that has not been etched away on the first surface of the substrate from being damaged in subsequent processes. The sidewall protection layer 7 is etched to open the sidewall protection layer at the bottom of the initial bit line isolation groove 601, and then a same-direction etching is used to form a first bit line isolation groove 602. The same-direction etching can use dry etching, wet etching or a combination of both, without specific limitation. Due to the use of same-direction etching, the width of the first bit line isolation groove 602 in the second direction is greater than the width of the initial bit line isolation groove 601 in the second direction, and part of the substrate on both sides of the first bit line isolation groove 602 is etched away.

[0089] Referring to FIG. 4c, in some embodiments, the initial bit line isolation trench 601 and the first bit line isolation trench 602 are filled with an insulating material, and a planarization process exposes the mask layer that is not removed by etching. Specifically, in some embodiments, the insulating material can include, but is not limited to, silicon nitride, silicon oxide, silicon oxynitride, silicon carbon nitride, or the like or a combination thereof, and the material of the insulating material is different from that of the mask layer. The deposition method can include, but is not limited to, chemical vapor deposition, flowable chemical vapor deposition, atomic layer deposition, spin coating, high intensity deposition, or the like or a combination thereof. The mask layer that is not removed is selectively etched, the material of the mask layer is different from that of the bit line isolation layer 8, and the etching can be performed by a self-alignment method without a photomask. The etching method can use dry etching, wet etching, or a combination thereof. The mask layer is modified to have a size consistent with the bit line isolation trench 6, and after the mask layer is removed, the pattern of the second bit line isolation trench 603 is formed.

[0090] Referring to FIG. 4d, in some embodiments, the second bit line isolation trench 603 is formed according to the pattern of the second bit line isolation trench 603 formed by the above steps. The second bit line isolation trench 603 extends in the first direction and is arranged between adjacent first bit line isolation trenches 602 in the second direction. Since the first bit line isolation trench 602 and the second bit line isolation trench 603 are arranged in a staggered manner and are formed in steps, the distance between adjacent bit line isolation trenches 6 is large when the first bit line isolation trench 602 and the second bit line isolation trench 603 are separately prepared, which increases the process window and improves the stability of the device.

[0091] Referring to FIG. 4e, in some embodiments, the bit line contact 10 is formed at the bottom of the second bit line isolation trench 603 and contacts the substrate on both sides, and the storage contact 9 is formed at the top of the active pillar, which contacts the adjacent first bit line isolation trench 602 in the second direction. Specifically, a sidewall protection layer is formed on the second bit line isolation trench 603 and the substrate surface to prevent damage or impact on the substrate in subsequent processes. The protection layer at the bottom of the second bit line isolation trench 603 and the substrate surface is etched to expose the substrate. The bit line contact 10 and the storage contact 9 are formed by ion implantation, deposition of high-concentration doping material for diffusion, or deposition of metal material for metal silicidation reaction, etc. The bit line contact 10 and the storage contact 9 can be formed in steps or in one step, without specific limitation. The material of the storage contact 9 is not limited specifically, and as an example, the material of the storage contact 9 can include at least one of doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, and combinations thereof. The material of the bit line contact 10 is not limited specifically, and as an example, the material of the bit line contact 10 can include at least one of doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, and combinations thereof.

[0092] Referring to FIG. 4f, in some embodiments, the bit line isolation layer 8 is formed by filling the second bit line isolation trench 603 with insulating material, and planarization processing. The bit line isolation structure 8 extends in the first direction and is arranged at intervals in the second direction.

[0093] Referring to FIG. 1b and FIG. 4g, in some embodiments, the substrate first surface is patterned and etched to form word line isolation trenches 5, and the word line isolation trenches 5 and bit line isolation trenches 6 form the active pillar 4. A word line 2 is formed in the word line isolation trenches 5, the word line 2 extends along the second direction and is arranged in the first direction, the word line surrounds the active pillar 4 on one side, two sides or three sides of the active pillar 4, and controls the charge movement of the active pillar 4. The material of the word line is not specifically limited, and as an example, the material of the word line 2 can include, for example, doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide or a combination thereof. For example, the word line 2 can include, but is not limited to, doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi or a combination thereof.

[0094] A storage structure 11 is formed on the storage contact 9, and a back-end-of-line (not shown in the figure) is formed on the storage structure 11. The storage structure 11 can be a capacitor structure, the capacitor includes an upper electrode plate, a lower electrode plate and a high-k dielectric material between the upper electrode plate and the lower electrode plate; or a variable resistance storage structure, the variable resistance storage structure is switched to two resistance states by an electrical pulse applied to the memory element, for example, the variable resistance storage structure can include a phase change material, a perovskite compound, a transition metal oxide, a magnetic material, a ferromagnetic material or an antiferromagnetic material, whose crystal state changes according to the amount of electricity.

[0095] Referring to FIG. 4h, in some embodiments, the substrate is flipped, and a thinning process is performed on the second surface of the substrate by using a grinding process, taking the bit line isolation layer 8 as the etching stop layer.

[0096] Referring to FIG. 4i, in some embodiments, since the material of the bit line isolation layer 8 is different from that of the substrate, a self-aligned process can be used to selectively etch and remove the substrate material to form a bit line trench 12. The self-aligned process can reduce the number of exposures and reduce the process cost.

[0097] Referring to FIG. 4j, in some embodiments, a bit line material layer 13 is deposited in the bit line trench 12, and the material of the bit line material is not specifically limited, and as an example, the bit line material layer 13 can include, but is not limited to, doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi or a combination thereof.

[0098] Referring to FIG. 4k, in some embodiments, the etching back of the bit line material layer 13 forms the bit line 3, and the bit line protection layer 14 is formed on the bit line 3, and the bit line protection layer 14 is planarized by using a grinding process. Specifically, a selective etching method is used to etch and remove part of the bit line material layer 13, so that the bit line material layer 13 is formed only in the bit line trench 12 to form the bit line 3. Dry etching can be used, wet etching can be used, or a combination of the two can be used. The bit line protection layer 14 is deposited on the bit line 3. The material of the bit line protection layer 14 can include, but is not limited to, silicon nitride, silicon oxide, silicon oxynitride, and silicon carbon nitride, or a combination thereof. The material of the bit line protection layer 14 is different from the material of the bit line isolation layer 8.

[0099] Referring to FIG. 4l, in some embodiments, the bit line isolation layer 8 is etched to form the shielding line trench 15 in the bit line isolation layer 8. Specifically, since the material of the bit line isolation layer 8 and the material of the bit line protection layer 14 are different, a self-aligned etching method can be used to etch and remove part of the bit line isolation layer 8 to form the shielding line trench 15. Dry etching can be used, wet etching can be used, or a combination of the two can be used. In some embodiments, dry etching can be used to form a trench with a certain depth, and then wet etching can be used to etch in the same direction at the bottom of the trench to make the width of the bottom of the trench larger, thereby forming a different trench. This prevents the problem of open circuit caused by the inability of the shielding line material to fill the small bottom of the trench. The use of a self-aligned etching process can reduce the number of photolithography processes, reduce production costs, and improve the stability of the device.

[0100] As known from the foregoing steps, the width of the bit line isolation layer 8 in the second direction is large, and the process window of the shielding line trench 15 is also large. At the same time, the depth of the shielding line trench 15 in the third direction is also large. The bottom of the shielding line trench 15 is lower than the lowest plane of the bit line 3 in the third direction. In this way, the bit line shielding line 16 formed subsequently can protect the bit line 3 from signal interference from adjacent bit lines. In some embodiments, the bottom of the shielding line trench 15 can be lower than the lowest plane of the bit line contact 10 in the third direction, thereby improving the stability of the device. The shape of the shielding line trench 15 is not specifically limited. As an example, the cross-sectional shape of the shielding line trench 15 in the second direction can be conical, strip-shaped, elliptical, star-shaped, or other suitable shapes.

[0101] Please continue to refer to FIG. 2 and FIG. 3a-3e, the conductive material is deposited in the shielding line trench 15 to form the shielding line 16, in some embodiments, the shielding line 16 can be one layer, or can be multiple layers, for example, in FIG. 3c, the shielding line 16 can include a shielding line first material layer 1601 and a shielding line second material layer 1602, the positional relationship of the shielding line first material layer 1601 and the shielding line second material layer 1602 is not specifically limited, for example, the shielding line first material layer 1601 and the shielding line second material layer 1602 can be stacked, surrounded, and half-enclosed, etc. The material of the shielding line 16 can include, for example, doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or a combination thereof. For example, the shielding line 16 can include, but is not limited to, doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, or a combination thereof. The shielding line 16 at least includes a metal material layer, which can reduce the resistance of the shielding line 16 and improve the performance of the device.

[0102] Please continue to refer to FIG. 3b, in some embodiments, the shielding line 16 and the bit line isolation layer 8 are not in complete contact at least in part, and there is a gap 17 between the shielding line 16 and the bit line isolation layer 8, the relative position of the gap 17 and the bit line isolation layer 8 is not specifically limited, for example, the gap 17 can be located at the bottom of the shielding line, one side of the sidewall, and half-enclosed shielding line, etc. The size and shape of the gap 17 are also not specifically limited, for example, the gap can be spherical, droplet-shaped, short pipe-shaped, ellipsoidal, long strip-shaped, or other suitable shapes. Since the dielectric constant of air is 1.001, close to the dielectric constant of vacuum, the gap 17 and the bit line isolation layer 8 together exhibit a low dielectric constant effect to reduce the overall dielectric constant, which can reduce the parasitic capacitance and avoid the capacitive coupling effect between the bit line 3 and the adjacent bit line 3, thereby reducing the influence of the parasitic capacitance on the performance parameters of the device.

[0103] Please continue to refer to FIG. 3d, in some embodiments, the cross-sectional shape of the shielding line 16 on the third party can be irregular, for example, it can be conical, long strip-shaped, elliptical, star-shaped, or other suitable shapes. The shielding line is formed in the bit line isolation layer 8, and the size of the shielding line 16 is affected by the material and equipment etching capability of the bit line isolation layer 8. The irregular structure of the shielding line 16 can increase the process preparation window and reduce the preparation process cost.

[0104] Please continue to refer to FIG. 3e, in some embodiments, a shielding line barrier 18 can also be disposed above the shielding line 16, the shielding line barrier 18 covers the shielding line 16 and can protect the shielding line 16 from being damaged in subsequent processes. The material of the shielding line barrier 18 is not limited and can be the same as or different from the material of the bit line protection layer 14.

[0105] Please continue to refer to FIG. 2, in some embodiments, the width D1 of the shielding line 16 in the third direction (for example, the Z direction) is not less than the width D2 of the bit line 3 in the third direction (for example, the Z direction). The width D1 of the shielding line 16 in the third direction (for example, the Z direction) exceeds the width D2 of the bit line 3 in the third direction (for example, the Z direction). Optionally, the width D1 of the shielding line 16 in the third direction (for example, the Z direction) exceeds the sum of the width of the bit line 3 and the width of the bit line contact structure 10 in the third direction (for example, the Z direction). In this way, the shielding line 16 can completely shield the coupling effect between adjacent bit lines 3 and improve the performance of the device.

[0106] Please continue to refer to FIG. 2, in some embodiments, the semiconductor structure can include a direct current bias (DC bias) which can be connected to the shielding line 16 through a connection contact (not shown) to give the shielding line 16 a stable voltage, so that the shielding line 16 forms a conductive barrier, thereby reducing or eliminating the influence of one of the two adjacent bit lines 3 when the other is powered on or off.

[0107] FIGS. 5a-5f are views illustrating intermediate steps for describing a method for manufacturing a semiconductor memory device according to some embodiments. For the sake of convenience of description, parts that are repetitive of those described with reference to FIGS. 4a-4l will be briefly described or omitted. For reference, FIG. 5a is a view illustrating an intermediate step after FIG. 4d.

[0108] Referring to FIG. 5a, in some embodiments, the second bit line isolation trench 603 is directly filled. The material filling the second bit line isolation trench 603 is not limited, and can be the same as or different from the material filling the first bit line isolation trench 602. Planarization is performed to expose the first surface of the substrate 1, or the top of the active pillar 4 is not completely filled, and a storage contact 9 is formed on the top of the active pillar. Specifically, the storage contact 9 is formed by ion implantation, deposition of a high-concentration doped material for diffusion, deposition of a metal material for metal silicidation, or other suitable methods. The material of the storage contact 9 is not limited, and as an example, the material of the storage contact 9 can include at least one of doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, or a combination thereof.

[0109] Referring to FIG. 1b and FIG. 5b, in some embodiments, the first surface of the substrate is patterned and etched to form a word line isolation trench 5, and the word line isolation trench 5 and the bit line isolation trench 6 form the active pillar 4. A word line 2 is formed in the word line isolation trench, the word line 2 extends in the second direction and is arranged in the first direction, and the word line surrounds the active pillar 4 on one side, two sides, or three sides of the active pillar 4 to control the charge movement of the active pillar 4. The material of the word line is not limited, and as an example, the material of the word line 2 can include, for example, doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or a combination thereof. For example, the word line 2 can include, but is not limited to, doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, or a combination thereof.

[0110] A storage structure 11 is formed on the storage contact 9, and a back-end-of-line (not shown in the figure) is formed on the storage structure 11. The storage structure 11 can be a capacitor structure including upper and lower electrode plates and high-k dielectric material between the upper and lower electrode plates, or a variable resistance storage structure that is switched to two resistance states by an electrical pulse applied to the memory element, for example. The variable resistance storage structure can include a phase change material whose crystal state changes according to an amount of current, a perovskite compound, a transition metal oxide, a magnetic material, a ferromagnetic material, or an antiferromagnetic material.

[0111] Referring to FIG. 5c and FIG. 5d, in some embodiments, the substrate is flipped, the second surface of the substrate 1 is thinned, and planarization is performed with the first bit line isolation layer 8 as the etching stop layer.

[0112] Referring to FIG. 5e, in some embodiments, since the bit line isolation layer 8 is made of a material different from the substrate material, a self-alignment process can be used to selectively etch the substrate material to form the bit line trench 12. The self-alignment process can reduce the number of exposure times and lower the process cost.

[0113] Referring to FIG. 5f, in some embodiments, the bit line contact 10 is formed at the bottom of the bit line trench 12. The bit line contact 10 can be formed by ion implantation, deposition of high-concentration doping material for diffusion, or deposition of metal material for metal silicidation reaction, etc. The material of the bit line contact 10 is not specifically limited. For example, the material of the bit line contact 10 can include at least one of doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, and combinations thereof.

[0114] Subsequently, referring to FIGS. 4j-4l, the bit line 3 and the shield line 16 are formed. Thus, the semiconductor memory device described with reference to FIGS. 2 and 3a-3e can be manufactured.

[0115] It should be noted that the semiconductor structure preparation methods in the embodiments of the present application can be used to prepare corresponding semiconductor structures, and thus the technical features of the method embodiments and the structure embodiments can be replaced and supplemented with each other without conflict, so that those skilled in the art can understand the technical content of the present application.

[0116] The technical features of the above-described embodiments can be combined in any manner. To make the description concise, all possible combinations of the technical features of the above-described embodiments are not described, but as long as the combinations of the technical features do not conflict, they should be considered within the scope of the present application.

[0117] The above-described embodiments only express several implementation manners of the present application, and the description is relatively specific and detailed, but it should not be understood as a limitation on the patent scope of the application. It should be noted that for those skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are within the protection scope of the present application. Therefore, the patent protection scope of the present application should be subject to the appended claims.

Claims

1. A semiconductor structure, comprising: active pillars (4) arranged in an array in a first direction and a second direction, the first direction intersecting the second direction; bit lines (2) extending in the first direction and spaced apart in the second direction, the bit lines (2) connecting the active pillars (4) arranged in the first direction; shield lines (16) located between two adjacent bit lines (2) and extending in the first direction, the shield lines (16) being alternately arranged with the bit lines (2) in the second direction; bit line contact structures (10) located between and connecting the bit lines (2) and the active pillars (4), the bit line contact structures (10) having a width in the second direction smaller than the width of the bit lines (2) and the active pillars (4) in the second direction.

2. The semiconductor structure of claim 1, wherein, The bit line contact structures (10) connect two adjacent active pillars (4) in the second direction.

3. The semiconductor structure of claim 1 or 2, wherein, The shield lines (16) have a width in a third direction not smaller than the width of the bit lines (2) in the third direction, the third direction intersecting the first direction and the second direction.

4. The semiconductor structure of claim 3, wherein, The width of the bit lines (2) in the second direction decreases as the bit lines (2) extend towards the bit line contact structures (10).

5. The semiconductor structure according to any one of claims 1-3, further comprising: bit line protection layers (14) located on the side of the bit lines (2) away from the bit line contact structures (10); bit line isolation layers (8) located between two adjacent bit lines (2), the shield lines (16) being located in the bit line isolation layers (8); The bit line protection layers (14) and the bit line isolation layers (8) are made of different materials.

6. The semiconductor structure of any of claims 1-3, wherein, The bit lines (2) comprise at least one layer of metal material; The shield lines (16) comprise at least one layer of metal material.

7. The semiconductor structure according to any one of claims 4-6, further comprising: shield line blocking layers (18) covering the shield lines (16).

8. The semiconductor structure of any of claims 1-7, wherein, There is a gap (17) between the bit line isolation layers (8) and the shield lines (16).

9. The semiconductor structure of any of claims 1-8, wherein, The shield lines (16) have a cross-sectional shape perpendicular to the first direction which is conical, long strip-shaped, elliptical, star-shaped or other suitable shape.

10. The semiconductor structure according to any one of claims 1-9, further comprising: word lines (2) extending in the second direction and spaced apart in the first direction, the word lines (2) connecting the active pillars (4) in the second direction; storage structures (11) connected to the active pillars (4) and located at the end of all the active pillars (4) away from the bit lines (2).

11. A method for manufacturing a semiconductor structure, comprising: forming active pillars (4) arranged in an array in a first direction and a second direction, the first direction intersecting the second direction; forming bit lines (2) extending in a first direction, spaced apart in a second direction, and connecting active pillars (4) arranged in the first direction; forming shield lines (16) between two adjacent bit lines (2), extending in the first direction, and alternately arranged with the bit lines (2) in the second direction; forming bit line contact structures (10) connecting the bit lines (2) and the active pillars (4), the bit line contact structures (10) having a width in the second direction smaller than the width of the bit lines (2) and the active pillars (4) in the second direction.

12. The method of producing a semiconductor structure according to claim 11, wherein, The forming bit lines (2) comprises: providing a substrate (1) having a first surface and a second surface in a third direction intersecting the first direction and the second direction; forming bit line isolation trenches (6) on the first surface by patterning and etching, the bit line isolation trenches (6) having a bottom size larger than a top size, extending in the first direction, and spaced apart in the second direction; filling the bit line isolation trenches (6) to form bit line isolation layers (8); grinding the second surface to expose the bit line isolation layers (8), and etching the substrate to form bit line trenches (12) using the bit line isolation layers (8) as a mask; filling the bit line trenches (12) with at least one layer of metal material to form the bit lines (2); forming bit line protection layers (14) on the bit lines (2), the bit line protection layers (14) being different from the material of the bit line isolation layers (8).

13. The method of producing a semiconductor structure according to claim 11 or 12, wherein, The forming shield lines (16) comprises: etching the bit line isolation layers (8) on the second surface using the bit line protection layers (14) as a mask to form shield line trenches (15), the shield line trenches (15) having a depth not less than the depth of the bit line trenches (12); filling the shield line trenches (15) with at least one layer of metal material to form the shield lines (16).

14. The method of fabricating a semiconductor structure according to any one of claims 11-13, wherein, The bit line contact structures (10) comprise metal silicide, and the forming metal silicide comprises: depositing a layer of metal material at the bottom of the bit line trenches (12) and heat treating to form metal silicide; or depositing a layer of metal material at the bottom of the bit line isolation trenches (6) and heat treating to form metal silicide.

15. The method of fabricating a semiconductor structure of claim 12, wherein, After filling the bit line isolation trenches (6) to form the bit line isolation layers (8), the method further comprises: forming word line isolation trenches (5) on the first surface by patterning and etching, the word line isolation trenches (5) having a depth smaller than the depth of the bit line isolation trenches (6), extending in the second direction, and spaced apart in the first direction, the word line isolation trenches (5) and the bit line isolation trenches (6) forming the active pillars (4); After forming the active pillars (4), the method further comprises: forming word lines (2) in the word line isolation trenches (5), the word lines (2) extending in the second direction, spaced apart in the first direction, and connecting the active pillars (4) in the second direction; A memory structure (11) is formed at the end of the active pillar (4) away from the bit line (2).

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