Solar cell and preparation method therefor, and photovoltaic module

Abstract

Disclosed are a solar cell and a preparation method therefor, and a photovoltaic module. The solar cell comprises a silicon substrate. The silicon substrate comprises a first surface and a second surface that are arranged opposite each other, the second surface comprises a first region and a second region, a first tunneling passivation contact structure is provided on the first region, a second passivation structure is provided on the first region and the second region, and the second passivation structure on the first region is stacked on the first tunneling passivation contact structure, wherein the height difference H1 between the surface of the side of the second passivation structure away from the silicon substrate over the first region and the surface over the second region is 0.01-8 μm, and / or, the height difference H2 between the surface of the side of the second passivation structure facing the silicon substrate over the first region and the surface over the second region is 0.01-8 μm.

Description

Solar cell and preparation method thereof, photovoltaic module

[0001] Cross-reference to related applications

[0002] The present application claims priority to the Chinese Patent Application No. 202411184801.8, filed on August 27, 2024, entitled “Solar cell and preparation method thereof”, the Chinese Patent Application No. 202422086173.1, filed on August 27, 2024, entitled “Photovoltaic cell and photovoltaic module”, the Chinese Patent Application No. 202411352531.7, filed on September 26, 2024, entitled “Solar cell and preparation method thereof”, the Chinese Patent Application No. 202410563104.7, filed on May 8, 2024, entitled “Solar cell and preparation method thereof”, the Chinese Patent Application No. 202410485399.0, filed on April 19, 2024, entitled “Solar cell and preparation method thereof”, all of which are incorporated herein by reference in their entirety. TECHNICAL FIELD

[0003] The present disclosure belongs to the technical field of solar cells, and particularly relates to a solar cell and a preparation method thereof, and a photovoltaic module. BACKGROUND

[0004] With the rapid development of the photovoltaic industry, the performance and efficiency requirements of solar cells in the domestic and foreign photovoltaic markets are also continuously increasing, and manufacturers in the industry are striving to research and develop high-efficiency cells. The TOPCon (Tunnel Oxide Passivated Contact) cell can improve the surface passivation performance of the cell, reduce the metal contact recombination current, and effectively improve the open-circuit voltage and short-circuit current of the cell by sequentially preparing an ultra-thin tunnel oxide layer and a doped polysilicon layer on the back surface of the silicon substrate. In recent years, the market share of the TOPCon cell has rapidly increased, and has gradually surpassed the PERC cell to become the mainstream technology of solar cells.

[0005] The back surface of the TOPCon cell forms a tunnel passivation contact structure by using a tunnel oxide layer and a doped polysilicon layer, and the cell efficiency is significantly improved. The thicker the thickness of the doped polysilicon on the back surface, the larger the resistance to metal paste burning window, but the parasitic absorption is also higher. Therefore, one of the efficiency improvement schemes of the TOPCon cell is the back Poly finger structure, which reduces or completely removes the thickness of the doped polysilicon in the non-metal area, and reduces the parasitic absorption of the long-wave band on the back surface. Therefore, it is necessary to control the thickness of the polysilicon in the metal area and the non-metal area.

[0006] If the back surface metal region doped polysilicon is too thin, the paste sintering penetrates the doped polysilicon, destroys the bottom tunneling oxide layer, causes poor passivation effect, and the battery efficiency is low; if the back surface non-metal region doped polysilicon is too thick, the parasitic absorption is high, and the battery efficiency is low; if the non-metal region doped polysilicon is too thin, the field passivation effect is poor, and the battery efficiency is low. At present, the thickness of the back surface doped polysilicon layer of the TOPCon battery in mass production is generally between 100 nm and 150 nm, which is mainly limited by the paste sintering window, so it cannot be thinned further.

[0007] Therefore, in view of the above technical problems, it is necessary to provide a solar cell and a preparation method thereof.

[0008] Disclosed content

[0009] The purpose of the present disclosure is to provide a solar cell and a preparation method thereof, so as to balance the passivation effect and reduce the parasitic absorption, improve the process window, and significantly improve the battery efficiency and the double-side rate.

[0010] In order to achieve the above-mentioned purpose, the technical scheme provided by an embodiment of the present disclosure is as follows:

[0011] A solar cell, comprising a silicon substrate, the silicon substrate comprising a first surface and a second surface arranged oppositely, the second surface comprising a first region and a second region, the first region being provided with a first tunneling passivation contact structure, the first region and the second region being provided with a second passivation structure, the second passivation structure on the first region being stacked on the first tunneling passivation contact structure, wherein the height difference H1 of the side surface of the second passivation structure away from the silicon substrate on the first region and the second region is 0.01 μm-8 μm, and / or the height difference H2 of the side surface of the second passivation structure toward the silicon substrate on the first region and the second region is 0.01 μm-8 μm.

[0012] In an embodiment, the second passivation structure on the second region is in contact with the second surface of the silicon substrate, the first tunneling passivation contact structure on the first region comprises a tunneling layer and a second doped layer stacked in sequence, and the solar cell further comprises a second electrode located on the first region and in contact with the second doped layer.

[0013] In an embodiment, the height difference H1 of the side surface of the second passivation structure away from the silicon substrate on the first region and the second region is 0.05 μm-8 μm or 3 μm-6 μm; and / or the height difference H2 of the side surface of the second passivation structure toward the silicon substrate on the first region and the second region is 0.05 μm-8 μm or 3 μm-6 μm.

[0014] In one embodiment, the tunneling layer is any one or a combination of silicon oxide layer, silicon oxynitride layer; and / or, the thickness of the tunneling layer is 0.5nm-3nm or 1.5nm-2.5nm; and / or, the second doped layer is a doped polysilicon layer with a thickness of 1nm-150nm or 50nm-100nm; and / or, the second doped layer has the same doping type as the doping type of the silicon substrate, and a surface doping concentration of 2E20cm -3 -3E21cm -3 or 5E20cm -3 -2E21cm -3 .

[0015] In one embodiment, the silicon substrate is recessed on the second region.

[0016] In one embodiment, the first region and the second region in the second surface of the silicon substrate are both polished surfaces after pyramid structure texturing, and the tower base size on the first region is smaller than the tower base size on the second region.

[0017] In one embodiment, the tower base size on the first region is 3μm-20μm, and the tower base size on the second region is 3μm-50μm; or, the tower base size on the first region is 8μm-15μm, and the tower base size on the second region is 15μm-30μm.

[0018] In one embodiment, the second region is provided with a second tunneling passivation contact structure, and the second passivation structure on the second region is stacked on the second tunneling passivation contact structure, and the thickness of the second tunneling passivation contact structure is smaller than the thickness of the first tunneling passivation contact structure.

[0019] In one embodiment, the first region is provided with a tunneling layer, a second doped layer, a barrier layer and a third doped layer, the second region is provided with a tunneling layer and a second doped layer, and the solar cell further comprises a second electrode located on the first region and in contact with the third doped layer.

[0020] In an embodiment, the first region is provided with a tunneling layer, a second doped layer, a barrier layer and a third doped layer, the second region is provided with a tunneling layer and a second doped layer; or, the first region is provided with a tunneling layer, a second doped layer, a barrier layer and a third doped layer, the second region is provided with a tunneling layer, a second doped layer, a barrier layer and a third doped layer, the thickness of the third doped layer in the second region is less than that in the first region; or, the first region is provided with a tunneling layer, at least two second doped layers and at least two barrier layers which are alternately stacked, and a third doped layer, the second region is provided with a tunneling layer, at least two second doped layers and at least one barrier layer which are alternately stacked; or, the first region is provided with a tunneling layer, at least two second doped layers and at least two barrier layers which are alternately stacked, and a third doped layer, the second region is provided with a tunneling layer, at least two second doped layers and at least two barrier layers which are alternately stacked, and a third doped layer, the thickness of the third doped layer in the second region is less than that in the first region.

[0021] In an embodiment, the first tunneling and passivation contact structure comprises a tunneling layer and at least one doped layer which are stacked on the first region, the second tunneling and passivation contact structure comprises a tunneling layer and at least one doped layer which are stacked on the first region, and the total thickness of the doped layer in the first region is greater than that in the second region.

[0022] In an embodiment, the height difference H1 of the second passivation structure from the side surface of the silicon substrate in the first region and the second region is 0.01 μm to 0.153 μm or 0.048 μm to 0.102 μm; and / or, the height difference H2 of the second passivation structure to the side surface of the silicon substrate in the first region and the second region is 0.01 μm to 0.153 μm or 0.048 μm to 0.102 μm.

[0023] In an embodiment, the tunneling layer is any one or a combination of a silicon oxide layer and a silicon oxynitride layer; and / or, the thickness of the tunneling layer is 0.5 nm to 3 nm or 1.5 nm to 2.5 nm; and / or, the barrier layer is any one or a combination of a silicon oxide layer and a silicon carbide layer; and / or, the thickness of the barrier layer is 0.5 nm to 3 nm or 1.5 nm to 2 nm; and / or, the second doped layer has the same doping type as that of the silicon substrate, and the surface doping concentration is 1E20 cm-9E20 cm-3E20 cm-5E20 cm-; and / or, the third doped layer has the same doping type as that of the silicon substrate, and the surface doping concentration is 2E20 cm-5E20 cm-. -3 -3 -3 -3 ; and / or, the third doped layer has the same doping type as that of the silicon substrate, and the surface doping concentration is 2E20 cm-5E20 cm-.​​​-3 ~3E21cm -3 or 5E20cm -3 ~2E21cm -3 ; and / or, the second doped layer is a doped polysilicon layer with a thickness of 1nm-100nm or 1nm-50nm; and / or, the third doped layer is a doped polysilicon layer with a thickness of 1nm-150nm or 50nm-100nm; and / or, the total thickness of the second doped layer and the third doped layer on the first region is 50nm-150nm or 60nm-100nm.

[0024] In an embodiment, the first region comprises a plurality of first sub-regions distributed in parallel and at equal intervals, and the second region comprises a plurality of second sub-regions distributed in parallel and at equal intervals, the first sub-regions and the second sub-regions are alternately distributed, and the width of the first sub-region is 20μm-600μm, and the width of the second sub-region is 100μm-800μm.

[0025] In an embodiment, the second passivation structure comprises one or more combinations of a silicon oxide layer, an aluminum oxide layer, a silicon nitride layer, and a silicon oxynitride layer.

[0026] In an embodiment, the second passivation structure comprises a silicon oxide layer, an aluminum oxide layer, and a silicon nitride layer stacked in sequence, wherein the thickness of the silicon oxide layer is 0.1nm-3nm, the thickness of the aluminum oxide layer is 3nm-10nm or 4nm-8nm, and the thickness of the silicon nitride layer is 60nm-100nm or 70nm-90nm; or, the second passivation structure comprises a silicon oxide layer and a silicon nitride layer stacked in sequence, wherein the thickness of the silicon oxide layer is 1nm-30nm, and the thickness of the silicon nitride layer is 60nm-100nm or 70nm-90nm.

[0027] In an embodiment, the first doped layer has a doping type opposite to that of the silicon substrate, a surface doping concentration of 1E18cm -3 ~5E19cm -3 , and a thickness of 10nm-100nm; and / or, the first doped layer is stacked with a first passivation structure, and the first passivation structure comprises an aluminum oxide layer and a silicon nitride layer stacked in sequence, wherein the thickness of the aluminum oxide layer is 3nm-10nm or 4nm-8nm, and the thickness of the silicon nitride layer is 60nm-100nm or 70nm-90nm.

[0028] A photovoltaic module, comprising the solar cell described above.

[0029] Another embodiment of the present disclosure provides a technical solution as follows:

[0030] A method for manufacturing a solar cell, the method comprising the steps of: providing a silicon substrate, the silicon substrate comprising a first surface and a second surface oppositely arranged, the second surface comprising a first region and a second region; manufacturing a tunneling passivation contact structure on the first region of the second surface; manufacturing a second passivation structure on the first region and the second region of the second surface; wherein a height difference H1 of a side surface of the second passivation structure away from the silicon substrate on the first region and the second region is 0.01-8 μm, and / or a height difference H2 of a side surface of the second passivation structure toward the silicon substrate on the first region and the second region is 0.01-8 μm.

[0031] In one embodiment, after manufacturing the tunneling passivation contact structure on the first region of the second surface and before manufacturing the second passivation structure on the first region and the second region of the second surface, the method further comprises: manufacturing a mask layer on the second surface; patterning and opening the mask layer on the second region by a laser process; removing all or part of the tunneling passivation contact structure on the second region by a wet etching process, while retaining the tunneling passivation contact structure on the first region; and removing the mask layer on the first region to expose the tunneling passivation contact structure on the first region.

[0032] In one embodiment, the method further comprises: manufacturing a pyramid texturing structure on the first surface and the second surface of the silicon substrate by an alkali texturing process, the pyramid size being 0.5-3 μm; and polishing the second surface of the silicon substrate by an alkali solution before manufacturing the tunneling passivation contact structure, to form a plurality of tower bases on the second surface, the tower base size being 3-20 μm or 8-15 μm.

[0033] In one embodiment, the tunneling passivation contact structure comprises a tunneling layer, a second doped layer, a barrier layer, and a third doped layer stacked in sequence; the wet etching process comprises: removing all or part of the third doped layer on the second region by an alkali etching process; or removing all of the third doped layer and the barrier layer and at least part of the second doped layer on the second region by an alkali etching process.

[0034] In one embodiment, the tunneling passivation contact structure comprises a tunneling layer, at least two second doped layers and at least two barrier layers stacked alternately, and a third doped layer; the wet etching process comprises: removing all or part of the third doped layer on the second region by an alkali etching process; or removing all of the third doped layer and the outermost barrier layer and at least part of the outermost second doped layer on the second region by an alkali etching process.

[0035] Compared with the prior art, the present disclosure has the following beneficial effects:

[0036] The present disclosure removes the mask layer on the back non-metal region through a laser process, and then removes or thins the tunneling passivation contact structure on the second region of the back through a chemical etching process, so as to ensure that the silicon substrate is not damaged, and the tunneling passivation contact structure on the first region is not affected, and the passivation effect and the reduction of parasitic absorption can be considered, so as to significantly improve the cell efficiency and the double-sided rate while improving the process window.

[0037] The chemical etching process can further polish the silicon substrate on the second region, so as to increase the height difference between the first region and the second region, and form a larger tower base on the second region, so as to further improve the cell efficiency.

[0038] Through the introduction of the back barrier layer of the cell, the doping concentration change of the doping layer can be effectively improved during the laser process, and the damage of the tunneling layer is avoided, so as to further improve the passivation effect. At the same time, the barrier layer has a certain blocking ability to the piercing of the back paste, which helps to reduce the total thickness of the back doping layer and improve the open circuit voltage (Voc) of the cell. BRIEF DESCRIPTION OF DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments described in the present disclosure, and other drawings can also be obtained by those skilled in the art without creative labor.

[0040] FIG. 1 is a structural schematic diagram of a solar cell in Embodiment 1 of the present disclosure;

[0041] FIG. 2 is a partial structural schematic diagram of M in FIG. 1;

[0042] FIG. 3 is a planar schematic diagram of the second surface of a silicon substrate in Embodiment 1 of the present disclosure;

[0043] FIG. 4 is a planar schematic diagram of the second surface and the second electrode in Embodiment 1 of the present disclosure;

[0044] FIGS. 5a-5j are process flow diagrams for preparing a solar cell in Embodiment 1 of the present disclosure;

[0045] FIG. 6 is a structural schematic diagram of a solar cell in Embodiment 2 of the present disclosure;

[0046] FIG. 7 is a partial structural schematic diagram of N in FIG. 6;

[0047] FIG. 8 is a planar schematic diagram of the second surface of a silicon substrate in Embodiment 3 of the present disclosure;

[0048] Fig. 9 is a schematic diagram of a partial structure at A in Fig. 8;

[0049] Figs. 10a-10j are process flow diagrams for preparing a solar cell in Embodiment 3 of the present disclosure;

[0050] Fig. 11 is a schematic diagram of a structure of a solar cell in Embodiment 4 of the present disclosure;

[0051] Fig. 12 is a schematic diagram of a partial structure at B in Fig. 11;

[0052] Fig. 13 is a schematic diagram of a structure of a solar cell in Embodiment 5 of the present disclosure;

[0053] Fig. 14 is a schematic diagram of a partial structure at C in Fig. 13;

[0054] Fig. 15 is a schematic diagram of a structure of a solar cell in Embodiment 6 of the present disclosure;

[0055] Fig. 16 is a schematic diagram of a partial structure at D in Fig. 15;

[0056] Fig. 17 is an SEM image of a pyramid textured surface in Embodiment 1 of the present disclosure;

[0057] Fig. 18 is an SEM image of a first region on a back surface of a silicon substrate in Embodiment 1 of the present disclosure;

[0058] Fig. 19 is an SEM image of a second region on a back surface of a silicon substrate in Embodiment 1 of the present disclosure.

[0059] Reference signs: 100, solar cell; 10, silicon substrate; S1, first surface; S2, second surface; S21, first region; S22, second region; 11, first doped layer; 12, tunneling layer; 13, second doped layer; 21, aluminum oxide layer; 31, silicon nitride layer; 22, silicon oxide layer; 32, silicon nitride layer; 14, barrier layer; 131, one second doped layer; 132, third doped layer; 15, mask layer; 41, first electrode; 42, second electrode; 101, first sub-region; 102, second sub-region; 421, fine grid line; 110, first tunneling passivation contact structure; 120, second tunneling passivation contact structure; 130, first passivation structure; 140, second passivation structure. DETAILED DESCRIPTION

[0060] In order to enable a person skilled in the art to better understand the technical solutions in the present disclosure, the technical solutions in the embodiments of the present disclosure will be clearly and completely described in the following with reference to the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by a person skilled in the art without creative work should fall within the protection scope of the present disclosure.

[0061] In the present disclosure, unless explicitly specified and limited, a first feature is "on" or "under" a second feature can be that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, the first feature "above", "over" and "on" the second feature can be that the first feature is directly above or obliquely above the second feature, or only indicates that the horizontal height of the first feature is higher than that of the second feature. The first feature "below", "under" and "under" the second feature can be that the first feature is directly below or obliquely below the second feature, or only indicates that the horizontal height of the first feature is less than that of the second feature.

[0062] The present disclosure discloses a solar cell, comprising a silicon substrate, the silicon substrate comprising a first surface and a second surface arranged oppositely, the second surface comprising a first region and a second region, the first region being provided with a first tunneling passivation contact structure, the first region and the second region being provided with a second passivation structure, the second passivation structure on the first region being stacked on the first tunneling passivation contact structure, wherein the height difference H1 of the side surface of the second passivation structure away from the silicon substrate on the first region and the second region is 0.01 μm-8 μm, and / or the height difference H2 of the side surface of the second passivation structure toward the silicon substrate on the first region and the second region is 0.01 μm-8 μm.

[0063] According to some embodiments of the present application, the first surface is a light-receiving surface, the second surface is a back surface, the first region is a metal region, and the second region is a non-metal region, wherein the thicknesses of the second passivation structures stacked in the direction perpendicular to the back surface of the silicon substrate on the metal region and the non-metal region are equal, and the thickness of the stacked structure on the metal region is greater than that on the non-metal region.

[0064] The present disclosure further discloses a preparation method of a solar cell, comprising the following steps:

[0065] Providing a silicon substrate, the silicon substrate comprising a first surface and a second surface arranged oppositely, the second surface comprising a first region and a second region;

[0066] Preparing a tunneling passivation contact structure and a mask layer on the second surface;

[0067] Performing patterned opening of the mask layer on the second region by a laser process;

[0068] all or part of the tunneling passivation contact structure on the second region is removed by a wet etching process, and the tunneling passivation contact structure on the first region is reserved;

[0069] the mask layer on the first region is removed to expose the tunneling passivation contact structure on the first region;

[0070] a second passivation structure is prepared on the second surface;

[0071] wherein the height difference H1 of the side surface of the second passivation structure away from the silicon substrate on the first region and the second region is 0.01 μm to 8 μm, and / or the height difference H2 of the side surface of the second passivation structure toward the silicon substrate on the first region and the second region is 0.01 μm to 8 μm.

[0072] The present disclosure also discloses a photovoltaic module comprising the above-mentioned solar cell.

[0073] The present disclosure removes the mask layer on the back non-metal region by a laser process, and then removes all or part of the tunneling passivation contact structure on the back non-metal region by a chemical etching process, which can take into account the passivation effect and reduce parasitic absorption, improve the process window, and significantly improve the cell efficiency and bifaciality.

[0074] The present disclosure is further described below in combination with specific examples.

[0075] Embodiment 1:

[0076] As shown in FIG. 1 and FIG. 2, the structure of the solar cell in the present embodiment is shown, which is a TOPCon cell, comprising a silicon substrate 10, the silicon substrate 10 comprising a first surface S1 and a second surface S2 arranged oppositely, the second surface S2 comprising a first region S21 and a second region S22, the first surface S1 being the front surface (i.e. light-receiving surface) of the silicon substrate 10, the second surface S2 being the back surface (i.e. back light surface) of the silicon substrate 10, the first region S21 being a back metal region, and the second region S22 being a back non-metal region.

[0077] Alternatively, the thicknesses of the second passivation structures 140 stacked in the direction perpendicular to the second surface S2 of the silicon substrate 10 on the first region S21 and the second region S22 are equal, and the thickness of the stacked structure on the first region S21 is greater than that on the second region S22; the thickness of the stacked structure on the first region S21 is greater than that on the second region S22 by 0.05 μm to 8 μm or 3 μm to 6 μm.

[0078] The silicon substrate 10 in the present embodiment is an N-type silicon substrate, and the resistivity is 0.3 Ω·cm to 7 Ω·cm, preferably 0.5 Ω·cm to 3.5 Ω·cm.

[0079] Further, the first surface S1 of the silicon substrate 10 is formed with a pyramid structure by alkali texturing, the pyramid structure is in the shape of a truncated pyramid, such as a triangular truncated pyramid, a quadrangular truncated pyramid, etc., and the pyramid size is defined as the average of the width of the base of the truncated pyramid. For example, taking the quadrangular truncated pyramid as an example, the base is approximately square, and the pyramid size is the length of the side of the square.

[0080] In this embodiment, the pyramid size ranges from 0.5 μm to 3 μm. FIG. 17 shows the SEM image of the pyramid structure in this embodiment, and the three pyramid sizes marked in the figure are 2.67 μm, 2.60 μm and 2.75 μm, and the average of all pyramid sizes is about 2.7 μm.

[0081] The first region S21 and the second region S22 of the second surface S2 are both polished surfaces after polishing of the pyramid structure. In this embodiment, the silicon substrate 10 is recessed on the second region S22, and the base size of the pyramid on the first region S21 is smaller than that on the second region S22. During the alkali polishing process, the pyramid structure on the back of the silicon substrate 10 is polished to form a base, which is the pedestal left after polishing of the pyramid structure. The base can be in the shape of a triangle, a quadrangle, etc., and the base size is defined as the average of the width of the base, and taking the square base as an example, the base size is the average of the length of the side of the square.

[0082] In the alkali polishing process, the base size is larger than the pyramid size, and the deeper the etching depth, the larger the base size. In this embodiment, the base size on the first region S21 ranges from 3 μm to 20 μm, and is preferably from 8 μm to 15 μm, and the base size on the second region ranges from 3 μm to 50 μm, and is preferably from 15 μm to 30 μm.

[0083] FIG. 18 shows the SEM image of the first region S21 in this embodiment, and the base sizes marked in the figure are 11.37 μm, 11.52 μm, 11.44 μm, 11.53 μm and 11.13 μm, and the average of the base sizes on the first region S21 is about 11.4 μm. FIG. 19 shows the SEM image of the second region S22 in this embodiment, and the etching depth of the second region S22 is deeper, and the base size is larger, such as the base sizes marked in the figure, which are 20.30 μm, 20.23 μm and 19.29 μm, and the average of the base sizes on the second region S22 is about 20 μm.

[0084] In this embodiment, the first doped layer 11 is formed on the first surface S1 of the silicon substrate 10 by diffusion process or PECVD process. For example, the first doped layer 11 is a P-type doped layer (i.e., P+emitter) formed by boron doping process, and the doping concentration is 1E18 cm -3 ~ 5E19 cm -3, preferably 200 Ω / sq to 400 Ω / sq.

[0085] Referring to FIG. 1 and FIG. 2, in the embodiment, the first region S21 on the second surface S2 of the silicon substrate 10 is provided with a first tunneling passivation contact structure 110, which comprises a tunneling layer 12 and a second doped layer 13 stacked in sequence.

[0086] The tunneling layer 12 is one or a combination of a silicon oxide (SiO X ) layer and a silicon oxynitride (SiO X N Y ) layer, preferably a silicon oxide layer, with a thickness of 0.5 nm to 3 nm, preferably 1.5 nm to 2.5 nm. -3 The second doped layer 13 is a phosphorus-doped polysilicon layer with a doping concentration of 2E20 cm -3 to 3E21 cm -3 , preferably 5E20 cm -3 to 2E21 cm X , and a thickness of 1 nm to 150 nm, preferably 50 nm to 100 nm.

[0087] In addition, in the embodiment, the first surface S1 and the second surface S2 of the silicon substrate 10 are respectively provided with a first passivation structure 130 and a second passivation structure 140.

[0088] Specifically, the first passivation structure 130 is stacked on the first doped layer 11 and comprises an aluminum oxide (SiO X ) layer 21 and a silicon nitride (SiN X ) layer 31 stacked in sequence, wherein the thickness of the aluminum oxide layer 21 is 3 nm to 10 nm, preferably 4 nm to 8 nm, and the thickness of the silicon nitride layer 31 is 60 nm to 100 nm, preferably 70 nm to 90 nm.

[0089] The second passivation structure 140 is stacked on the second region S22 and the surface of the second doped layer 13 and comprises a combination of one or more of a silicon oxide (SiO X ) layer, an aluminum oxide (AlO X ) layer, and a silicon nitride (SiO X ) layer. For example, in the embodiment, the second passivation structure 140 comprises a silicon oxide (SiO X ) layer 22 and a silicon nitride (SiO X ) layer 32 stacked in sequence, wherein the thickness of the silicon oxide layer is 1 nm to 30 nm, and the thickness of the silicon nitride layer is 60 nm to 100 nm, preferably 70 nm to 90 nm.

[0090] Since the silicon substrate 10 is recessed in the second region S22 in the embodiment, there is a height difference between the first region S21 and the second region S22. As shown in FIG. 2, the height difference of the second passivation structure 140 on the side surface away from the silicon substrate 10 (i.e. the outer side surface of the silicon nitride layer 32) between the first region S21 and the second region S22 is H1, and the height difference of the second passivation structure 140 on the side surface toward the silicon substrate 10 (i.e. the inner side surface of the silicon oxide layer 22) between the first region S21 and the second region S22 is H2.

[0091] The first region S21 is laminated with the tunneling layer 12 and the second doped layer 13, and thus the height difference H2 is the sum of the recess depth of the second region S22 and the thickness of the tunneling layer 12 and the second doped layer 13, which is 0.05 μm to 8 μm, and preferably 3 μm to 6 μm. For example, the sum of the thickness of the tunneling layer 12 and the second doped layer 13 is about 100 nm (0.1 μm) in the embodiment, the height difference H2 is about 4 μm, and the recess depth of the second region S22 is about 3.9 μm.

[0092] The silicon oxide layer 22 and the silicon nitride layer 32 in the embodiment are deposited by the PECVD process on the front surface, and thus the silicon oxide layer 22 and the silicon nitride layer 32 have the same thickness on the first region S21 and the second region S22, and thus the height difference H1 is equal to the height difference H2. In other embodiments, when the second passivation structure 140 has different thicknesses on the first region S21 and the second region S22, the height difference H1 is not equal to the height difference H2.

[0093] In the disclosure, the second passivation structure 140 laminated in the direction perpendicular to the second surface (e.g. the back surface) of the silicon substrate 10 has the same thickness on the first region (e.g. the metal region) S21 and the second region (e.g. the non-metal region) S22 (not considering the second passivation structure 140 on the sidewall of the first tunneling passivation contact structure 110). At this time, the height difference H2 of the second passivation structure on the side surface toward the silicon substrate between the first region and the second region is 0.01 μm to 8 μm, and the height difference of the second passivation structure on the side surface away from the silicon substrate between the first region S21 and the second region S22 is also H, i.e. 0.01 μm to 8 μm.

[0094] In another embodiment of the disclosure, the second passivation structure 140 includes a silicon oxide layer, an aluminum oxide layer and a silicon nitride layer laminated in sequence, wherein the thickness of the silicon oxide layer is 0.1 nm to 3 nm, the thickness of the aluminum oxide layer is 3 nm to 10 nm, and preferably 4 nm to 8 nm, and the thickness of the silicon nitride layer is 60 nm to 100 nm, and preferably 70 nm to 90 nm.

[0095] In addition, the first electrode 41 in the embodiment is located on the first surface S1 of the silicon substrate 10 and in contact with the first doped layer 11, and the second electrode 42 is located on the second surface S2 of the silicon substrate 10, specifically in the first region S21 in the second surface S2, and in contact with the second doped layer 13.

[0096] As shown in FIG. 3, the first region S21 in the embodiment includes a plurality of first sub-regions 101 distributed in parallel and at equal intervals, the second region S22 includes a plurality of second sub-regions 102 distributed in parallel and at equal intervals, and the first sub-regions 101 and the second sub-regions 102 are staggered. The width of the first sub-region 101 is smaller than the width of the second sub-region 102, for example, the width ratio of the two can be 1:(5-20), preferably, the width of the first region S21 is 20-600 μm, and the area of the first region S21 accounts for about 10% of the area of the entire second surface S2.

[0097] As shown in FIG. 4, the second electrode 42 is a gate line electrode, which includes at least a plurality of fine gate lines 421 distributed in parallel, and the width of the first sub-region 101 is greater than or equal to the width of the fine gate line 421. Optionally, the second electrode 42 can also include a plurality of main gate lines (not shown) distributed perpendicularly to the fine gate lines 421.

[0098] Taking a 210TOPCon cell as an example, the cell size is 203.396±15 mm, the fine gate line 421 is 230, the width is 15-100 μm, and the interval between adjacent fine gate lines 421 is 0.907±0.015 mm. The interval between adjacent first sub-regions 101 is equal to the interval between adjacent fine gate lines 421, one fine gate line 421 is distributed on each first sub-region 101, the width of the first sub-region 101 is greater than the width of the fine gate line 421, and the width of the first sub-region is 50-150 μm, for example, when the width of the fine gate line is 40 μm, the width of the first sub-region is 80 μm.

[0099] The preparation method of the solar cell in the embodiment specifically includes the following steps:

[0100] 1. Double-sided texturing

[0101] As shown in FIG. 5a, a silicon substrate 10 is provided, which includes a first surface S1 and a second surface S2 arranged oppositely, the second surface S2 includes a first region S21 and a second region S22, the first surface S1 is the front surface (i.e. light receiving surface) of the silicon substrate 10, the second surface S2 is the back surface (i.e. back light surface) of the silicon substrate 10, the first region S21 is a back surface metal region, and the second region S22 is a back surface non-metal region.

[0102] The silicon substrate 10 in the embodiment is an N-type silicon substrate with a resistivity of 0.3 Ω·cm to 7 Ω·cm, preferably 0.5 Ω·cm to 3.5 Ω·cm.

[0103] As shown in Fig. 5b, the first surface S1 and the second surface S2 of the silicon substrate 10 in the embodiment are formed with a pyramid structure by an alkali texturing process, and the pyramid size is 0.5 μm to 3 μm.

[0104] 2. Boron diffusion

[0105] As shown in Fig. 5c, a P-type doped first doped layer (i.e., P+emitter) 11 is formed on the first surface S1 of the silicon substrate 10 by a boron diffusion process. Specifically, the boron source deposition propulsion method is used in a high-temperature furnace tube for diffusion. After diffusion, the doping concentration of the first doped layer 11 is 1E18 cm -3 ~ 5E19 cm -3 , and the square resistance is 100 Ω / sq to 500 Ω / sq, preferably 200 Ω / sq to 400 Ω / sq. In the boron diffusion process, the second surface S2 of the silicon substrate 10 is formed with a BSG (not shown).

[0106] In other embodiments, the first doped layer 11 can also be prepared by a PECVD process. First, an amorphous silicon layer doped with boron with a thickness of 10 nm to 100 nm is deposited on the first surface S1 by a PECVD process. After high-temperature oxidation annealing, a P-type doped polysilicon layer is formed.

[0107] 3. Backside polishing

[0108] As shown in Fig. 5d, the silicon substrate 10 after boron diffusion is first subjected to single-side chain equipment, and the backside silicon oxide is removed by using a hydrofluoric acid solution. Then, the backside is subjected to alkali polishing to remove the edge junction and the backside BSG. Finally, the silicon substrate 10 is cleaned.

[0109] In the alkali polishing process, the pyramid structure of the backside of the silicon substrate 10 is polished to form a tower base, which is the pedestal left after the pyramid-shaped textured surface is polished. In the embodiment, the tower base size of the backside of the silicon substrate 10 after alkali polishing is 3 μm to 20 μm, preferably 8 μm to 15 μm.

[0110] 4. Preparation of backside tunneling passivation contact structure

[0111] As shown in Fig. 5e, a tunneling layer 12, a second doped layer 13, and a mask layer 15 are sequentially prepared on the second surface S2.

[0112] For example, in the embodiment, a silicon oxide tunneling layer is first deposited on the backside by a PECVD process, and the thickness is 0.5 nm to 3 nm, preferably 1.5 nm to 2.5 nm;

[0113] Then a phosphorus doped amorphous silicon layer is deposited by PECVD process, the doping concentration is 2E20cm -3 ~ 3E21cm -3 , preferably 5E20cm -3 ~ 2E21cm -3 , the thickness is 1nm~150nm, preferably 50nm~100nm; finally a mask layer 15 is deposited, the mask layer 15 is any one or combination of silicon oxide (SiO X ) layer, silicon oxynitride (SiO X N Y ) layer and silicon nitride (SiN X ) layer, the thickness is 1nm~100nm, preferably 5nm~30nm.

[0114] 5. Annealing

[0115] The silicon substrate 10 with tunneling passivation contact structure deposited on the back is placed in a high temperature annealing furnace for high temperature annealing, the annealing temperature is 850℃~950℃, preferably 890℃~920℃, during the annealing process, the phosphorus is activated, thereby converting the doped amorphous silicon layer into a doped polysilicon layer.

[0116] 6. Laser opening film

[0117] As shown in Fig. 5f, the mask layer 15 on the second area (non-metal area) S22 is patterned and opened by laser process.

[0118] The energy required for laser opening film is affected by the thickness of the mask layer 15, in the embodiment, the laser can be green picosecond laser or purple picosecond laser, the laser power is 0.3W~25W, preferably 0.3W~5W, the laser frequency is 100kHz~1000kHz, preferably 300kHz~600kHz, the laser scanning rate is 10000mm / s~100000mm / s, preferably 10000mm / s~60000mm / s, the laser processing times is 1~100 times, preferably 1~10 times.

[0119] 7. Wet etching

[0120] As shown in Fig. 5g, the second doped layer 13, the tunneling layer 12 and part of the silicon substrate 10 on the second area S22 are removed by wet etching process, the tunneling layer 12 and the second doped layer 13 on the first area S21 are reserved.

[0121] First, the front side and the edge side PSG are removed by using hydrofluoric acid. Then, the front side and the edge side wrap plating and the tunnel layer 12, the second doped layer 13 and part of the silicon substrate 10 on the second region S22 are removed by using alkali etching process. The etching liquid is composed of sodium hydroxide / potassium hydroxide + additives + pure water, the etching temperature is 50-90°C, preferably 60-80°C, the etching time is 100-500s, preferably 200-300s, the size of the tower on the second region S22 of the silicon substrate 10 after alkali etching is 3-50μm, preferably 15-30μm. Finally, the front side BSG and the mask layer 15 on the first region S21 of the back side are removed by using hydrofluoric acid, and RCA cleaning is performed.

[0122] After the wet etching process, the height difference between the surface of the second doped layer 13 away from the surface of the silicon substrate 10 and the second surface in the second region S22 is 0.05-8μm, preferably 3-6μm.

[0123] 8. Preparation of the first passivation structure

[0124] As shown in Fig. 5h, first, an aluminum oxide layer 21 is deposited on the first surface by using ALD process, the thickness is 3-10nm, preferably 4-8nm, then a silicon nitride layer 31 is deposited on the surface of the aluminum oxide layer by using PECVD process, the thickness is 60-100nm, preferably 70-90nm.

[0125] 9. Preparation of the second passivation structure

[0126] As shown in Fig. 5i, first, a silicon oxide layer 22 and a silicon nitride layer 32 are deposited on the surface of the second region and the second doped layer by using PECVD process, the thickness of the silicon oxide layer 22 is 0.1-3nm, the thickness of the silicon nitride layer 32 is 60-100nm, preferably 70-90nm.

[0127] In other embodiments, first, a silicon oxide layer and an aluminum oxide layer are deposited on the surface of the second region S22 and the second doped layer 13 by using ALD process, H2O is introduced during the deposition of the silicon oxide layer, the deposition temperature is 180-300°C, the thickness is 0.1-3nm, TMA and H2O are introduced during the deposition of the aluminum oxide layer, the deposition temperature is 180-300°C, the thickness is 3-10nm, preferably 4-8nm, then a silicon nitride layer is deposited on the surface of the aluminum oxide layer by using PECVD process, the thickness is 60-100nm, preferably 70-90nm.

[0128] It should be understood that the second passivation structure is prepared on the second region S22 and the surface of the second doped layer 13 in the embodiment, and the second passivation structure is simultaneously formed on the sidewalls of the tunneling layer 12 and the second doped layer 13 in the deposition process. The thickness of the second passivation structure on the sidewalls is far less than the width of the tunneling layer 12 and the second doped layer 13 (20 μm-600 μm).

[0129] 10. Printed metal electrode

[0130] As shown in FIG. 5j, the first electrode 41 and the second electrode 42 are printed on the front surface and the back surface respectively by a screen printing process, and then sintering and light injection or electrical injection treatment are performed to form an ohmic contact.

[0131] The first electrode 41 and the second electrode 42 are gate line electrodes in the prior art, and generally include a main gate line and a fine gate line. It should be noted that since the fine gate line in the second electrode 42 needs to be printed on the first region, the width of the first sub-region needs to be greater than the width of the fine gate line in the second electrode 42, so that the alignment of the fine gate line can be achieved.

[0132] The TOPCon cell can be prepared through the above steps, and finally the cell is tested, sorted, and stored.

[0133] Embodiment 2

[0134] As shown in FIGS. 6 and 7, the structure of the solar cell in the embodiment is shown. The structure and preparation process of the solar cell in the embodiment are substantially the same as those in the embodiment, and the difference lies in that:

[0135] In the embodiment, the first region S21 and the second region S22 on the second surface S2 of the silicon substrate 10 are arranged in a flush manner, and the tower base size on the two regions is 3 μm-20 μm, and is preferably 8 μm-15 μm. The height difference between the surface of the second doped layer 13 away from the silicon substrate 10 and the second surface (i.e., the back surface) in the second region (i.e., the non-metal region) S22 is the height difference of the surface of the second passivation structure 140 away from the silicon substrate 10 on the first region (i.e., the metal region) S21 and the second region (i.e., the non-metal region) S22. Therefore, the height differences H1 and H2 on the first region S21 and the second region S22 are the sum of the thicknesses of the tunneling layer 12 and the second doped layer 13, and the value is preferably 0.05 μm-0.1 μm.

[0136] Correspondingly, in the preparation method of the solar cell in the embodiment, the second doped layer 13 on the second region S22 is removed by controlling the process parameters in the alkali etching process in the wet etching process, and the silicon substrate 10 is not removed. In addition, the tunneling layer 12 on the second region S22 is simultaneously removed when the mask layer is removed by using hydrofluoric acid.

[0137] Embodiment 3:

[0138] As shown in FIGS. 8 and 9, the structure of the solar cell in this embodiment is a schematic diagram of a TOPCon solar cell, wherein the silicon substrate 10 and the structure on the first surface S1 (i.e., the front surface or light-receiving surface) thereof are the same as those in the embodiment, and will not be described again here.

[0139] Different from the embodiment 1, the first tunneling passivation contact structure 110 and the second tunneling passivation contact structure 120 are respectively arranged on the first region S21 and the second region S22 on the second surface S2 of the silicon substrate 10 in this embodiment.

[0140] The first tunneling passivation contact structure 110 on the first region S21 includes a tunneling layer 12, a second doped layer 131, a barrier layer 14 and a third doped layer 132 which are sequentially stacked. Specifically, the tunneling layer 12 is one or a combination of a silicon oxide (SiO X ) layer, a silicon oxynitride (SiO X N Y ) layer, and preferably a silicon oxide layer, with a thickness of 0.5 nm to 3 nm, and preferably 1.5 nm to 2.5 nm; the barrier layer 14 is one or a combination of a silicon oxide (SiO X ) layer and a silicon carbide layer, and preferably a silicon oxide (SiO X ) layer, with a thickness of 0.5 nm to 3 nm, and preferably 1.5 nm to 2 nm.

[0141] In this embodiment, the doping type of the second doped layer 131 and the third doped layer 132 is the same as that of the silicon substrate 10, and preferably, the surface doping concentration of the third doped layer 132 is greater than that of the second doped layer 131; at the same time, the thickness of the third doped layer 132 is greater than that of the second doped layer 131, and the total thickness of the second doped layer 131 and the third doped layer 132 is 50 nm to 150 nm, and preferably 60 nm to 100 nm.

[0142] For example, in this embodiment, the second doped layer 131 is a phosphorus-doped polysilicon layer, with a surface doping concentration of 1E20cm -3 to 9E20cm -3 , and preferably 3E20cm -3 to 5E20cm -3 , and a thickness of 1 nm to 100 nm, and preferably 1 nm to 50 nm; the third doped layer 132 is a phosphorus-doped polysilicon layer, with a surface doping concentration of 2E20cm -3 to 3E21cm -3 , and preferably 5E20cm -3 to 2E21cm -3The thickness of the second doped layer 131 is 1 nm to 150 nm, preferably 50 nm to 100 nm.

[0143] The second tunneling passivation contact structure 120 on the second region S22 comprises a tunneling layer 12 and a second doped layer 131 stacked in sequence, and the tunneling layer 12 and the second doped layer 131 are completely identical to the tunneling layer 12 and the second doped layer 131 on the first region S21, which will not be repeated here.

[0144] In the embodiment, the first surface S1 and the second surface S2 of the silicon substrate 10 further comprise a first passivation structure and a second passivation structure stacked thereon, respectively, and the first passivation structure and the second passivation structure are completely identical to those in Embodiment 1, which will not be repeated here.

[0145] In addition, in the embodiment, the first electrode 41 is located on the first surface S1 of the silicon substrate 10 and contacts the first doped layer 11, and the second electrode 42 is located on the second surface S2 of the silicon substrate 10, specifically in the first region S21 in the second surface S2, and contacts the third doped layer 132.

[0146] Since the first region S21 and the second region S22 in the embodiment are provided with the first tunneling passivation contact structure and the second tunneling passivation contact structure, respectively, the heights of the two tunneling passivation contact structures are different, and the height difference between the first region (metal region) S21 and the second region (non-metal region) S22 (the surface of the third doped layer 132 in the first region (metal region) S21 away from the surface of the silicon substrate 10 and the surface of the second doped layer 131 in the second region (non-metal region) S22 away from the surface of the silicon substrate 10) is the height difference of the side surface of the second passivation structure away from the silicon substrate 10 on the first region (metal region) S21 and the second region (non-metal region) S22, that is, the height differences H1 and H2 on the first region S21 and the second region S22 are the sum of the thicknesses of the third doped layer 132 and the barrier layer 14, which is 0.01 μm to 0.153 μm, that is, 10 nm to 153 nm, and preferably 0.048 μm to 0.102 μm, that is, 48 nm to 102 nm. In the embodiment, when the thickness of the barrier layer 14 is 2 nm and the thickness of the third doped layer 132 is 98 nm, the height differences H1 and H2 are both 100 nm.

[0147] The preparation method of the solar cell in the embodiment specifically comprises the following steps:

[0148] 1. Double-sided texturing

[0149] As shown in Fig. 10a, a silicon substrate 10 is provided, which includes a first surface S1 and a second surface S2 oppositely arranged, the second surface S2 includes a first region S21 and a second region S22, the first surface S1 is a front surface (i.e. light receiving surface) of the silicon substrate 10, the second surface S2 is a back surface (i.e. back light surface) of the silicon substrate 10, the first region S21 is a back surface metal region, and the second region S22 is a back surface non-metal region.

[0150] The silicon substrate 10 in the embodiment is an N-type silicon substrate, and the resistivity is 0.3 Ω·cm-7 Ω·cm, preferably 0.5 Ω·cm-3.5 Ω·cm.

[0151] As shown in Fig. 10b, the first surface S1 and the second surface S2 of the silicon substrate 10 in the embodiment are formed with a pyramid structure by an alkali texturing process, and the pyramid size is 0.5 μm-3 μm.

[0152] 2. Boron diffusion

[0153] As shown in Fig. 10c, a P-type doped first doped layer (i.e. P+emitter) 11 is formed on the first surface S1 of the silicon substrate 10 by a boron diffusion process, and the boron source deposition propulsion method is used in a high-temperature furnace tube for diffusion. After diffusion, the doping concentration of the first doped layer 11 is 1E18 cm-5E19 cm, and the square resistance is 100 Ω / sq-500 Ω / sq, preferably 200 Ω / sq-400 Ω / sq. In the boron diffusion process, a BSG (not shown) is formed on the second surface S2 of the silicon substrate 10. -3 -3

[0154] In other embodiments, the first doped layer 11 can also be prepared by a PECVD process. First, an amorphous silicon layer doped with boron with a thickness of 10 nm-100 nm is deposited on the first surface S1 by a PECVD process, and then a P-type doped polysilicon layer is formed after high-temperature oxidation annealing.

[0155] 3. Back surface polishing

[0156] As shown in Fig. 10d, the silicon substrate 10 after boron diffusion is first subjected to single-sided chain equipment, and the back surface silicon oxide is removed by using a hydrofluoric acid solution, and then the back surface is subjected to alkali polishing to remove the edge junction and back surface plating (BSG), and finally cleaning is performed.

[0157] In the alkali polishing process, the pyramid structure of the back surface of the silicon substrate 10 is polished to form a tower base, which is a pedestal left after the pyramid-shaped textured surface is polished. In the embodiment, the tower base size of the back surface of the silicon substrate 10 after alkali polishing is 3 μm-20 μm, preferably 8 μm-15 μm.

[0158] 4. Preparation of back surface tunneling passivation contact structure​​

[0159] As shown in Fig. 10e, a tunneling layer 12, a second doped layer 131, a barrier layer 14, a third doped layer 132 and a mask layer 15 are sequentially deposited on the second surface S2.

[0160] Exemplarily, in the embodiment, a silicon oxide tunneling layer is first deposited on the back surface by using a PECVD process, with a thickness of 0.5 nm to 3 nm, preferably 1.5 nm to 2.5 nm; then a phosphorus-doped amorphous silicon layer is deposited by using a PECVD process, with a surface doping concentration of 1E20 cm -3 to 9E20 cm -3 , preferably 3E20 cm -3 to 5E20 cm -3 , and a thickness of 1 nm to 100 nm, preferably 1 nm to 50 nm; then a silicon oxide barrier layer is deposited by using a PECVD process, with a thickness of 0.5 nm to 3 nm, preferably 1.5 nm to 2 nm; then a phosphorus-doped amorphous silicon layer is deposited by using a PECVD process, with a surface doping concentration of 2E20 cm -3 to 3E21 cm -3 , preferably 5E20 cm -3 to 2E21 cm -3 , and a thickness of 1 nm to 150 nm, preferably 50 nm to 100 nm; finally, a mask layer 15 is deposited, which is a combination of any one or more of a silicon oxide (SiO X ) layer, a silicon oxynitride (SiO X N Y ) layer and a silicon nitride (SiN X ) layer, with a thickness of 1 nm to 100 nm, preferably 5 nm to 30 nm.

[0161] 5. Annealing

[0162] The silicon substrate 10 with the tunneling passivation contact structure deposited on the back surface is placed in a high-temperature annealing furnace for high-temperature annealing, with an annealing temperature of 850 °C to 950 °C, preferably 890 °C to 920 °C. During the annealing process, the phosphorus is activated, thereby converting the doped amorphous silicon layer into a doped polysilicon layer.

[0163] 6. Laser opening

[0164] As shown in Fig. 10f, the mask layer 15 on the second region (non-metal region) S22 is patterned and opened by using a laser process.

[0165] The energy required for laser opening the mask layer 15 is affected by the thickness of the mask layer 15. In the embodiment, the laser can be a green picosecond laser or a purple picosecond laser, the laser power is 0.3 W to 25 W, preferably 0.3 W to 5 W, the laser frequency is 100 kHz to 1000 kHz, preferably 300 kHz to 600 kHz, the laser scanning speed is 10000 mm / s to 100000 mm / s, preferably 10000 mm / s to 60000 mm / s, and the laser processing times is 1 to 100 times, preferably 1 to 10 times.

[0166] 7. Wet etching

[0167] As shown in FIG. 10g, the third doped layer 132 and the barrier layer 14 on the second region S22 are removed by a wet etching process, and the third doped layer 132 and the barrier layer 14 on the first region S21 are retained.

[0168] First, the front and edge PSG are removed by hydrofluoric acid; then, the front and edge wrap plating and the third doped layer 132 on the second region S22 are removed by an alkali etching process. The etching liquid composition is sodium hydroxide / potassium hydroxide + additives + pure water; finally, the front BSG and the mask layer 15 on the first region S21 and the barrier layer 14 on the second region S22 are removed by hydrofluoric acid, and RCA cleaning is performed.

[0169] After the wet etching process, the height difference between the surface of the third doped layer 132 on the first region S21 away from the silicon substrate 10 and the surface of the second doped layer 131 on the second region S22 away from the silicon substrate 10 is 0.01 μm to 0.153 μm, i.e. 10 nm to 153 nm.

[0170] 8. Preparation of the first passivation structure

[0171] As shown in FIG. 10h, first, an aluminum oxide layer 21 is deposited on the first surface by ALD process, with a thickness of 3 nm to 10 nm, preferably 4 nm to 8 nm; then, a silicon nitride layer 31 is deposited on the aluminum oxide surface by PECVD process, with a thickness of 60 nm to 100 nm, preferably 70 nm to 90 nm.

[0172] 9. Preparation of the second passivation structure

[0173] As shown in FIG. 10i, first, a silicon oxide layer 22 and a silicon nitride layer 32 are deposited on the surfaces of the first region S21 and the second region S22 by PECVD process, the thickness of the silicon oxide layer 22 is 0.1 nm to 3 nm, and the thickness of the silicon nitride layer 32 is 60 nm to 100 nm, preferably 70 nm to 90 nm.

[0174] In other embodiments, the ALD process can also be used to deposit a silicon oxide layer and an aluminum oxide layer on the surfaces of the first region S21 and the second region S22, H2O is introduced during the deposition of the silicon oxide layer, the deposition temperature is 180-300°C, and the thickness is 0.1-3 nm; TMA and H2O are introduced during the deposition of the aluminum oxide layer, the deposition temperature is 180-300°C, and the thickness is 3-10 nm, preferably 4-8 nm; and then the PECVD process is used to deposit a silicon nitride layer on the surface of the aluminum oxide layer, the thickness is 60-100 nm, preferably 70-90 nm.

[0175] It should be understood that, in the present embodiment, the second passivation structure is prepared on the surfaces of the first region S21 and the second region S22, and the second passivation structure is simultaneously formed on the sidewalls of the first tunneling passivation contact structure. The thickness of the second passivation structure on the sidewalls (about 90 nm) is much smaller than the width of the first tunneling passivation contact structure (20-600 μm).

[0176] 10. Printed metal electrode

[0177] As shown in FIG. 10j, the first electrode 41 and the second electrode 42 are printed on the front surface and the back surface, respectively, by the screen printing process, and then sintering and light injection or electrical injection treatment are performed to form an ohmic contact.

[0178] The first electrode 41 and the second electrode 42 are gate line electrodes in the prior art, which generally include main gate lines and fine gate lines. It should be noted that, since the fine gate lines in the second electrode 42 need to be printed on the first region, the width of the first sub-region needs to be greater than the width of the fine gate lines in the second electrode 42, so that the alignment of the fine gate lines can be achieved.

[0179] The TOPCon cell can be prepared through the above steps, and finally the cell is tested, sorted, and stored.

[0180] Embodiment 4:

[0181] As shown in FIG. 11 and FIG. 12, the solar cell in the present embodiment is substantially the same as that in Embodiment 3, except that in the present embodiment, the second region S22 on the second surface S2 of the silicon substrate 10 is sequentially stacked with a tunneling layer 12, a second doped layer 131, a barrier layer 14, and a third doped layer 132’, the tunneling layer 12, the second doped layer 131, and the barrier layer 14 on the first region S21 are completely the same as the tunneling layer 12, the second doped layer 131, and the barrier layer 14 on the second region S22, and the thickness of the third doped layer 132’ is less than that of the third doped layer 132.

[0182] The preparation method of the solar cell in this embodiment is also substantially the same as that in Embodiment 3, except that the wet etching step in Step 7 is different. In this embodiment, an alkali etching process is used to remove part of the third doped layer on the second region S22 and the mask layer on the first region S21, and to retain the third doped layer 132 on the first region S21. By controlling the parameters of the alkali etching process, the third doped layer on the second region S22 is thinned instead of being completely removed.

[0183] In this embodiment, since part of the third doped layer 132' on the second region S22 is retained, the acid solution does not corrode the barrier layer 14 on the second region S22 when the acid washing process is performed. Therefore, the barrier layer 14 and part of the third doped layer 132' are retained on the second region.

[0184] Corresponding to the thickness range of the barrier layer 14 and the third doped layer 132 in Embodiment 3, the height difference H1 and H2 between the first region S21 and the second region S22 is the height difference between the third doped layers 132 and 132', which is less than the thickness of the third doped layer 132, and is 0.01 μm to 0.149 μm, i.e. 10 nm to 149 nm, and preferably 0.05 μm to 0.09 μm, i.e. 50 nm to 90 nm.

[0185] For example, in this embodiment, the thickness of the barrier layer 14 on the first region S21 is about 2 nm, the thickness of the third doped layer 132 is 100 nm, and the thickness of the retained third doped layer 132' on the second region S22 is about 40 nm. Therefore, the height difference H1 and H2 between the first region S21 and the second region S22 is about 60 nm (i.e. 0.06 μm).

[0186] Embodiment 5:

[0187] Referring to FIG. 13 and FIG. 14, the solar cell in this embodiment is substantially the same as that in Embodiment 3, except that the tunneling layer 11 on the second surface S2 of the silicon substrate 10 in this embodiment is provided with alternately stacked second doped layers 131 and barrier layers 14.

[0188] Specifically, in this embodiment, the first region S21 on the second surface S2 of the silicon substrate 10 is sequentially provided with the tunneling layer 12, the second doped layer 131, the barrier layer 14, the second doped layer 131, the barrier layer 14, and the third doped layer 132. The second region S22 on the second surface S2 of the silicon substrate 10 is sequentially provided with the tunneling layer 12, the second doped layer 131, the barrier layer 14, and the second doped layer 131.

[0189] The preparation method of the solar cell in this embodiment is also substantially the same as that in Embodiment 3, except that the wet etching step in Step 7 is different. In this embodiment, the third doped layer 132 on the second region S22 is removed by alkali etching, and the outermost blocking layer 14 on the second region S22 and the mask layer on the first region S21 are removed by acid solution.

[0190] Similarly to Embodiment 3, the height differences H1 and H2 between the first region S21 and the second region S22 in this embodiment depend on the thickness ranges of the third doped layer 132 and the outermost blocking layer 14, which will not be described herein again.

[0191] Embodiment 6:

[0192] Referring to FIG. 15 and FIG. 16, the solar cell in this embodiment is substantially the same as that in Embodiment 5, except that the second region S22 on the second surface S2 of the silicon substrate 10 in this embodiment has the tunneling layer 12, the second doped layer 131, the blocking layer 14, the second doped layer 131, the blocking layer 14, and the third doped layer 132' stacked in sequence, and the thickness of the third doped layer 132' is less than the thickness of the third doped layer 132 on the first region S21.

[0193] The preparation method of the solar cell in this embodiment is also substantially the same as that in Embodiment 5, except that the wet etching step in Step 7 is different. In this embodiment, the alkali etching process is used to remove part of the third doped layer on the second region S22 and the mask layer on the first region S21, and the third doped layer 132 on the first region S21 is retained. By controlling the parameters of the alkali etching process, the third doped layer on the second region S22 is thinned, rather than completely removed.

[0194] In this embodiment, since part of the third doped layer 132' on the second region S22 is retained, the acid solution does not corrode the blocking layer 14 on the second region S22 during the acid washing process. Therefore, the blocking layer 14 and part of the third doped layer 132' are retained on the second region.

[0195] Similarly to Embodiment 4, the height differences H1 and H2 between the first region S21 and the second region S22 in this embodiment depend on the thickness ranges of the third doped layer and the outermost blocking layer 14, which will not be described herein again.

[0196] It should be understood that the number of the second doped layer 131 and the blocking layer 14 is not limited to the number in the above embodiments, wherein:

[0197] For the thinning scheme of the outermost third doped layer of the second region, for example, a non-metal region, the first region, for example, a metal region, and the second region, for example, a non-metal region, each include a tunneling layer, an M1 layer second doped layer and an M1 layer barrier layer alternately stacked on the tunneling layer, and a third doped layer stacked on the outermost barrier layer, M1 being a positive integer;

[0198] For the removal scheme of the outermost third doped layer of the second region, for example, a non-metal region, the first region, for example, a metal region, includes a tunneling layer, an M2 layer second doped layer and an M2 layer barrier layer alternately stacked on the tunneling layer, and a third doped layer stacked on the outermost barrier layer, the second region, for example, a non-metal region, includes a tunneling layer, an M2-1 layer second doped layer and an M2-1 layer barrier layer alternately stacked on the tunneling layer, M2 being a positive integer.

[0199] For other embodiments of the second doped layer and the barrier layer with other numbers of layers, no further examples are given here.

[0200] The present disclosure is based on the existing TOPCon cell structure, a tunneling passivation contact structure and a mask layer 15 are deposited on the back surface, then the second region S22 (non-metal region) is patterned and opened by a laser process, and then the tunneling passivation contact structure on the second region S22 (non-metal region) is removed or thinned by a wet etching process, providing a new solution for improving the efficiency of TOPCon cells.

[0201] The main deposition methods of poly (polysilicon) are LPCVD and PECVD. Considering the production capacity and the cost of quartz pieces, PECVD is more suitable for mass production. However, compared with LPCVD, the mask of PE Poly outer layer needs higher energy to open. Laser technology can be used to remove the mask of the non-metal region and the underlying poly (polysilicon), but as the laser power increases, the degree of opening of the back mask is from the mask being completely opened to the mask structure being loose to the mask being completely gasified to the mask + part of the poly being gasified. When the power increases to a certain level, the silicon substrate will be damaged, thereby reducing the cell efficiency.

[0202] The present disclosure removes the mask layer 15 on the non-metal region on the back surface by a laser process, and then removes or thins the tunneling passivation contact structure on the second region S22 on the back surface by a chemical etching process, which can ensure that the silicon substrate 10 is not damaged, and the tunneling passivation contact structure on the first region S21 is not affected, and can take into account the passivation effect and reduce parasitic absorption, thereby significantly improving the cell efficiency and the double-sided rate while improving the process window.

[0203] In the embodiment 1, the chemical etching process can further polish the silicon substrate 10 on the second region S22, so as to increase the height difference between the first region S21 and the second region S22, and form a tower base with a larger size on the second region S22, thereby further improving the cell efficiency.

[0204] In the embodiments 3-6, by introducing the back surface barrier layer 14, the variation of the doping concentration of the doping layer can be effectively improved during the laser process, the damage of the tunneling layer is avoided, the passivation effect is further improved, and the barrier layer has a certain blocking ability to the penetration of the back paste, which helps to reduce the total thickness of the back doping layer and improve the open circuit voltage (Voc) of the cell.

[0205] Tests show that, compared with directly removing the second doping layer 13 and the tunneling layer 12 on the second region S22 by laser, the efficiency of the solar cell in the present disclosure can be improved by more than 0.15%.

[0206] It is obvious for those skilled in the art that the present disclosure is not limited to the details of the above exemplary embodiments, and the present disclosure can be implemented in other specific forms without departing from the spirit or essential characteristics of the present disclosure. Therefore, the embodiments should be regarded as exemplary and non-limiting, the scope of the present disclosure is defined by the appended claims rather than the above description, and all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be included in the present disclosure. Any reference signs in the claims should not be regarded as limiting the claims involved.

[0207] In addition, it should be understood that although the present specification is described in terms of embodiments, each embodiment does not contain only one independent technical solution, and the description manner of the specification is only for clarity, those skilled in the art should regard the specification as a whole, and the technical solutions in each embodiment can also be properly combined to form other embodiments that those skilled in the art can understand.

Claims

1. A solar cell (100), characterized by, The solar cell (100) comprises a silicon substrate (10), the silicon substrate (10) comprising oppositely arranged first and second surfaces (S1, S2), the second surface (S2) comprising a first region (S21) and a second region (S22), the first region (S21) being provided with a first tunneling passivation contact structure (110), the first region (S21) and the second region (S22) being provided with a second passivation structure (140), the second passivation structure (140) on the first region (S21) being stacked on the first tunneling passivation contact structure (110), wherein The height difference H1 of the side surface of the second passivation structure (140) away from the silicon substrate (10) on the first region (S21) and the second region (S22) is 0.01 μm-8 μm, and / or the height difference H2 of the side surface of the second passivation structure (140) toward the silicon substrate (10) on the first region (S21) and the second region (S22) is 0.01 μm-8 μm.

2. The solar cell (100) according to claim 1, characterized in that The second passivation structure (140) on the second region (S22) is in contact with the second surface (S2) of the silicon substrate (10), the first tunneling passivation contact structure (110) on the first region (S21) comprises a tunneling layer (12) and a second doped layer (13) stacked in sequence, and the solar cell (100) further comprises a second electrode (42) located on the first region (S21) and in contact with the second doped layer (13).

3. The solar cell (100) according to claim 2, characterized in that The height difference H1 of the side surface of the second passivation structure (140) away from the silicon substrate (10) on the first region (S21) and the second region (S22) is 0.05 μm-8 μm or 3 μm-6 μm; and / or, The height difference H2 of the side surface of the second passivation structure (140) toward the silicon substrate (10) on the first region (S21) and the second region (S22) is 0.05 μm-8 μm or 3 μm-6 μm.

4. The solar cell (100) according to claim 2 or 3, characterized in that The tunneling layer (12) is any one or a combination of a plurality of silicon oxide layers and silicon oxynitride layers; and / or, The thickness of the tunneling layer (12) is 0.5 nm-3 nm or 1.5 nm-2.5 nm; and / or, The second doped layer (13) is a doped polysilicon layer with a thickness of 1 nm-150 nm or 50 nm-100 nm; and / or, The second doped layer (13) has the same doping type as the silicon substrate (10) and a surface doping concentration of 2E20 cm -3 ~ 3E21 cm -3 or 5E20 cm -3 ~ 2E21 cm -3 .

5. The solar cell (100) according to any one of claims 1 to 4, characterized in that The silicon substrate (10) is recessed on the second region (S22).

6. The solar cell (100) according to any of claims 1 to 5, characterized in that The first region (S21) and the second region (S22) in the second surface (S2) of the silicon substrate (10) are both polished surfaces after pyramid structure texturing and polishing, and the size of the tower base on the first region (S21) is smaller than the size of the tower base on the second region (S22).

7. The solar cell (100) according to claim 6, characterized in that The size of the tower base on the first region (S21) is 3 μm-20 μm, and the size of the tower base on the second region (S22) is 3 μm-50 μm; or, The tower base size on the first region (S21) is 8-15 μm, and the tower base size on the second region (S22) is 15-30 μm.

8. The solar cell (100) according to claim 1, characterized in that The second region (S22) is provided with a second tunneling passivation contact structure (120), and the second passivation structure (140) on the second region (S22) is stacked on the second tunneling passivation contact structure (120), and the thickness of the second tunneling passivation contact structure (120) is less than the thickness of the first tunneling passivation contact structure (110).

9. The solar cell (100) according to any of claims 1 to 8, characterized in that The first region (S21) is provided with a tunneling layer (12), a second doped layer (131), a barrier layer (14), and a third doped layer (132), the second region (S22) is provided with a tunneling layer (12) and a second doped layer (131), and the solar cell (100) further comprises a second electrode (42) located on the first region (S21) and in contact with the third doped layer (132).

10. The solar cell (100) according to claim 9, characterized in that The first region (S21) is provided with a tunneling layer (12), a second doped layer (131), a barrier layer (14), and a third doped layer (132), the second region (S22) is provided with a tunneling layer (12) and a second doped layer (131); or, The first region (S21) is provided with a tunneling layer (12), a second doped layer (131), a barrier layer (14), and a third doped layer (132), the second region (S22) is provided with a tunneling layer (12), a second doped layer (131), a barrier layer (14), and a third doped layer (132), and the thickness of the third doped layer (132) on the second region (S22) is less than the thickness of the third doped layer (132) on the first region (S21); or, The first region (S21) is provided with a tunneling layer (12), at least two second doped layers (131) and at least two barrier layers (14) which are alternately stacked, and a third doped layer (132), the second region (S22) is provided with a tunneling layer (12), at least two second doped layers (131) and at least one barrier layer (14) which are alternately stacked; or, The first region (S21) is provided with a tunneling layer (12), at least two second doped layers (131) and at least two barrier layers (14) which are alternately stacked, and a third doped layer (132), the second region (S22) is provided with a tunneling layer (12), at least two second doped layers (131) and at least two barrier layers (14) which are alternately stacked, and a third doped layer (132), and the thickness of the third doped layer (132) on the second region (S22) is less than the thickness of the third doped layer (132) on the first region (S21).

11. The solar cell (100) according to claim 8, characterized in that The first tunneling passivation contact structure (110) comprises a tunneling layer (12) and at least one doped layer stacked on the first region (S21), and the second tunneling passivation contact structure (120) comprises a tunneling layer (12) and at least one doped layer stacked on the first region (S21), and the total thickness of the doped layers on the first region (S21) is greater than the total thickness of the doped layers on the second region (S22).

12. The solar cell (100) according to any of claims 8-11, characterized in that, The height difference H1 of the second passivation structure (140) on the side surface away from the silicon substrate (10) on the first region (S21) and the second region (S22) is 0.01 μm-0.153 μm or 0.048 μm-0.102 μm; and / or, The height difference H2 of the second passivation structure (140) on the side surface toward the silicon substrate (10) on the first region (S21) and the second region (S22) is 0.01 μm-0.153 μm or 0.048 μm-0.102 μm.

13. The solar cell (100) according to claim 9 or 10, characterized in that The tunneling layer (12) is any one or a combination of multiple of a silicon oxide layer, a silicon nitride oxide layer; and / or, The thickness of the tunneling layer (12) is 0.5 nm-3 nm or 1.5 nm-2.5 nm; and / or, The barrier layer (14) is any one or a combination of multiple of a silicon oxide layer, a silicon carbide layer; and / or, The thickness of the barrier layer (14) is 0.5 nm-3 nm or 1.5 nm-2 nm; and / or, The second doped layer (131) has the same doping type as the silicon substrate (10) and a surface doping concentration of 1 E20 cm -3 ~ 9 E20 cm -3 or 3 E20 cm -3 ~ 5 E20 cm -3 ; and / or, The third doped layer (132) has the same doping type as the silicon substrate (10) and a surface doping concentration of 2E20 cm -3 ~ 3E21 cm -3 or 5E20 cm -3 ~ 2E21 cm -3 and / or, The second doped layer (131) is a doped polysilicon layer, and the thickness is 1 nm-100 nm or 1 nm-50 nm; and / or, The third doped layer (132) is a doped polysilicon layer, and the thickness is 1 nm-150 nm or 50 nm-100 nm; and / or, The total thickness of the second doped layer (131) and the third doped layer (132) on the first region (S21) is 50 nm-150 nm or 60 nm-100 nm.

14. The solar cell (100) according to any of claims 1 to 13, characterized in that The first region (S21) comprises a plurality of first sub-regions (101) distributed in parallel and at equal intervals, the second region (S22) comprises a plurality of second sub-regions (102) distributed in parallel and at equal intervals, the first sub-regions (101) and the second sub-regions (102) are alternately distributed, and the width of the first sub-region (101) is 20 μm-600 μm, and the width of the second sub-region (102) is 100 μm-800 μm.

15. The solar cell (100) according to any of claims 1 to 14, characterized in that The second passivation structure (140) comprises a combination of one or more of a silicon oxide layer, an aluminum oxide layer, a silicon nitride layer, and a silicon nitride oxide layer.

16. The solar cell (100) according to claim 15, characterized in that The second passivation structure (140) comprises a silicon oxide layer, an aluminum oxide layer, and a silicon nitride layer stacked in sequence, wherein the thickness of the silicon oxide layer is 0.1 nm-3 nm, the thickness of the aluminum oxide layer is 3 nm-10 nm or 4 nm-8 nm, and the thickness of the silicon nitride layer is 60 nm-100 nm or 70 nm-90 nm; or, The second passivation structure (140) comprises a silicon oxide layer, an aluminum oxide layer, and a silicon nitride layer stacked in sequence, wherein the thickness of the silicon oxide layer is 0.1 nm-3 nm, the thickness of the aluminum oxide layer is 3 nm-10 nm or 4 nm-8 nm, and the thickness of the silicon nitride layer is 60 nm-100 nm or 70 nm-90 nm; or, The second passivation structure (140) comprises a silicon oxide layer (22) and a silicon nitride layer (32) stacked in sequence, wherein the thickness of the silicon oxide layer (22) is 1-30 nm, and the thickness of the silicon nitride layer (32) is 60-100 nm or 70-90 nm.

17. The solar cell (100) according to any of claims 1 to 16, characterized in that The first doped layer (11) has a doping type opposite to that of the silicon substrate (10) and a surface doping concentration of 1E18 cm -3 ~ 5E19 cm -3 and / or a thickness of 10 nm to 100 nm. The first doped layer (11) is stacked with a first passivation structure (130), and the first passivation structure (130) comprises an aluminum oxide layer (21) and a silicon nitride layer (31) stacked in sequence, wherein the thickness of the aluminum oxide layer (21) is 3-10 nm or 4-8 nm, and the thickness of the silicon nitride layer (31) is 60-100 nm or 70-90 nm.

18. A photovoltaic module, characterized by, The photovoltaic module comprises the solar cell (100) according to any one of claims 1-17.

19. A method for manufacturing a solar cell, comprising: providing a silicon substrate, wherein the silicon substrate comprises a first surface and a second surface arranged oppositely, and the second surface comprises a first region and a second region; manufacturing a tunneling passivation contact structure on the first region of the second surface; manufacturing a second passivation structure on the first region and the second region of the second surface; wherein the height difference H1 of the side surface of the second passivation structure away from the silicon substrate on the first region and the second region is 0.01-8 μm, and / or the height difference H2 of the side surface of the second passivation structure toward the silicon substrate on the first region and the second region is 0.01-8 μm.

20. The method of claim 19, wherein, After manufacturing the tunneling passivation contact structure on the first region of the second surface and before manufacturing the second passivation structure on the first region and the second region of the second surface, the method further comprises: manufacturing a mask layer on the second surface; performing patterned opening of the mask layer on the second region by a laser process; removing all or part of the tunneling passivation contact structure on the second region by a wet etching process, and retaining the tunneling passivation contact structure on the first region; and removing the mask layer on the first region to expose the tunneling passivation contact structure on the first region.

21. The method of claim 20, wherein, The method further comprises: manufacturing a pyramid texturing structure on the first surface and the second surface of the silicon substrate by an alkali texturing process, and the pyramid size is 0.5-3 μm; and polishing the second surface of the silicon substrate by an alkali solution before manufacturing the tunneling passivation contact structure, and forming a plurality of tower bases on the second surface, and the tower base size is 3-20 μm or 8-15 μm.

22. The method of claim 21, wherein, The tunneling passivation contact structure comprises a tunneling layer, a second doped layer, a barrier layer and a third doped layer stacked in sequence; and the wet etching process comprises: removing all or part of the third doped layer on the second region by an alkali etching process; or removing all of the third doped layer, the barrier layer and at least part of the second doped layer on the second region by an alkali etching process.

23. The preparation method according to claim 21, characterized in that The tunneling passivation contact structure comprises a tunneling layer, at least two second doped layers and at least two barrier layers which are alternately stacked, and a third doped layer; the wet etching process comprises: The third doped layer on the second region is removed by an alkali etching process; or, the third doped layer, the outermost barrier layer and at least part of the outermost second doped layer on the second region are removed by an alkali etching process. The third doped layer on the second region is removed by an alkali etching process; or, the third doped layer, the outermost barrier layer and at least part of the outermost second doped layer on the second region are removed by an alkali etching process.

Images