Solar cell and preparation method therefor

Abstract

The present application provides a solar cell and a preparation method therefor. The solar cell comprises a silicon substrate, a front electrode arranged on a front face of the silicon substrate, and a back electrode arranged on a back face of the silicon substrate. The back face of the silicon substrate comprises a grid line area and a non-grid line area. The back electrode is arranged in the grid line area. The grid line area is provided with a first passivated contact structure. A tunnel layer, at least one first doped polycrystalline silicon layer, at least one spacer layer, and a second doped polycrystalline silicon layer are sequentially stacked on the first passivated contact structure. The passivated contact structure of the solar cell of the present invention has different film layers and thicknesses in the grid line area and the non-grid line area. The grid line area is provided with a four-layer structure consisting of the tunnel layer, the first doped polycrystalline silicon layer, the spacer layer, and the second doped polycrystalline silicon layer, and the grid line area is large in thickness and is provided with two doped polycrystalline silicon layers, preventing a grid line slurry from penetrating through the doped polycrystalline silicon layer and damaging an underlying tunnel oxide layer during sintering, thereby ensuring a field passivation effect. The non-grid line area only comprises the tunnel layer and the first doped polycrystalline silicon layer, and is much thinner than the grid line area, thereby reducing parasitic absorption of backlight, and improving photoelectric efficiency.

Description

Solar cell and preparation method thereof

[0001] The present application claims priority to Chinese Patent Application No. 202410485399.0, filed on April 19, 2024, entitled "Solar cell and preparation method thereof", Chinese Patent Application No. 202410563104.7, filed on May 8, 2024, entitled "Solar cell and preparation method thereof", and Chinese Patent Application No. 202411184801.8, filed on August 27, 2024, entitled "Solar cell and preparation method thereof", the contents of which are incorporated herein by reference in their entirety. TECHNICAL FIELD

[0002] The present application relates to the field of photovoltaics, and in particular to a solar cell and a preparation method thereof. BACKGROUND

[0003] TOPCon (Tunnel Oxide Passivated Contact) solar cells use a tunnel layer and a doped polysilicon layer on the back surface to form a passivation contact structure, achieving field passivation effect, reducing contact resistance, and improving open-circuit voltage and short-circuit current of the cell, thereby improving the conversion efficiency of the cell.

[0004] However, the thickness of the doped polysilicon layer on the back surface is between 100 nm and 150 nm, which affects the absorption of back surface light and in turn affects the efficiency of the cell.

[0005] Therefore, it is necessary to provide an improved solar cell and a preparation method thereof to solve the above technical problems. SUMMARY

[0006] The present application aims to provide a solar cell and a preparation method thereof, which improve the passivation effect of the back surface of the cell, increase the light utilization rate, have better cell efficiency, and simplify the process.

[0007] To achieve the above-mentioned purpose, the present application provides a solar cell, comprising a silicon substrate, a passivation contact structure located on the back surface of the silicon substrate, and a back electrode located on the back surface of the passivation contact structure; characterized in that the passivation contact structure comprises a tunnel layer located on the back surface of the silicon substrate, a first doped polysilicon layer located on the back surface of the tunnel layer, a spacer layer located on the back surface of the first doped polysilicon layer, and a second doped polysilicon layer located on the back surface of the spacer layer, wherein the spacer layer is discontinuously arranged.

[0008] Optionally, the spacer layer is selected from one or more combinations of a silicon oxide layer, a silicon oxynitride layer, or a silicon carbide layer.

[0009] Optionally, the thickness of the tunneling layer is 1 nm to 3 nm, and / or the thickness of the spacer layer is 0.5 nm to 3 nm, preferably, the thickness of the tunneling layer, the spacer layer is 1.5 nm to 2 nm.

[0010] Optionally, the thickness of the first doped polysilicon layer is less than or equal to the thickness of the second doped polysilicon layer.

[0011] Optionally, the doping type of the first doped polysilicon layer and the second doped polysilicon layer is the same as the doping type of the silicon substrate, and the doping concentration of the second doped polysilicon layer is greater than the doping concentration of the first doped polysilicon layer; the doping concentration of the first doped polysilicon layer is 1E+20 cm -3 to 9E+20 cm -3 , and the doping concentration of the second doped polysilicon layer is 2E+20 cm -3 to 3E+21 cm -3 .

[0012] Optionally, the solar cell further comprises a back surface passivation layer and a back surface anti-reflection layer arranged in sequence on the back surface of the passivation contact structure, and a front surface diffusion layer, a front surface passivation layer, a front surface anti-reflection layer, and a front surface electrode arranged in sequence on the front surface of the silicon substrate; the back surface electrode is in contact with the second doped polysilicon layer through the back surface anti-reflection layer and the back surface passivation layer, and the front surface electrode is in contact with the front surface diffusion layer through the front surface anti-reflection layer and the front surface passivation layer.

[0013] Another object of the present application is to provide a preparation method of a solar cell, comprising the following steps:

[0014] Depositing a tunneling layer, a first doped amorphous silicon layer, a spacer layer, and a second doped amorphous silicon layer in sequence on the back surface of the silicon substrate.

[0015] Forming a mask locally on the second doped amorphous silicon layer.

[0016] Converting the first phosphorus-doped amorphous silicon layer into a first doped polysilicon layer, and converting the second phosphorus-doped amorphous silicon layer into a second doped polysilicon layer.

[0017] Removing the second doped polysilicon layer in the region other than the mask; removing the mask and the spacer layer to form a discontinuous spacer layer.

[0018] Still another object of the present application is to provide a preparation method of a solar cell, comprising the following steps:

[0019] Providing a silicon substrate, the silicon substrate comprising a first surface and a second surface arranged oppositely, and the second surface comprising a first region and a second region.

[0020] forming a second phosphorus-doped amorphous silicon layer on the second surface of the silicon substrate;

[0021] transforming the first phosphorus-doped amorphous silicon layer into a first doped polysilicon layer and the second phosphorus-doped amorphous silicon layer into a second doped polysilicon layer;

[0022] forming a mask layer on the surface of the second doped polysilicon layer in the first region;

[0023] removing at least part of the second doped polysilicon layer in the second region and the oxide layer in the first region, while retaining the second doped polysilicon layer in the first region;

[0024] forming an electrode on the first region in contact with the second doped polysilicon layer.

[0025] Optionally, using the oxide layer as a mask layer, an alkali solution is used to remove all of the second doped polysilicon layer in the second region, and an acid solution is used to remove the outermost spacer layer in the second region and the oxide layer in the first region; or, using the oxide layer as a mask, an alkali solution is used to remove part of the second doped polysilicon layer in the second region, and an acid solution is used to remove the oxide layer in the first region.

[0026] Optionally, the tunneling layer is one or a combination of silicon oxide layer and silicon oxynitride layer, and has a thickness of 1-3 nm; and / or, the spacer layer is one or a combination of silicon oxide layer, silicon oxynitride layer and silicon carbide layer, and has a thickness of 0.5-3 nm or 1.5-2 nm.

[0027] Optionally, the mask layer is formed by laser processing in an oxygen atmosphere.

[0028] Yet another object of the present application is to provide a solar cell including a silicon substrate having a first surface and a second surface arranged oppositely, the second surface including a first region and a second region, the first region being provided with a tunneling layer, a first doped layer and a spacer layer, and a second doped layer, the second region being provided with a tunneling layer and a first doped layer, the solar cell further including an electrode on the first region and in contact with the second doped layer.

[0029] Optionally, the first region is provided with a tunneling layer, a first doped layer, a spacer layer and a second doped layer, and the second region is provided with a tunneling layer and a first doped layer; or,

[0030] the first region is provided with a tunneling layer, a first doped layer, a spacer layer and a second doped layer, and the second region is provided with a tunneling layer, a first doped layer, a spacer layer and a second doped layer, the thickness of the second doped layer in the second region being less than that of the second doped layer in the second region; or,

[0031] The first region is provided with a tunneling layer, at least two layers of first doped layers and at least two layers of interval layers which are alternately stacked, and a second doped layer, and the second region is provided with a tunneling layer, at least two layers of first doped layers and at least one layer of interval layers which are alternately stacked.

[0032] The first region is provided with a tunneling layer, at least two layers of first doped layers and at least two layers of interval layers which are alternately stacked, and a second doped layer, and the second region is provided with a tunneling layer, at least two layers of first doped layers and at least two layers of interval layers which are alternately stacked, and a second doped layer, and the thickness of the second doped layer on the second region is less than that of the second doped layer on the second region.

[0033] Yet another purpose of the present application is to provide a solar cell, comprising a silicon substrate, the silicon substrate comprising a first surface and a second surface arranged oppositely, a first electrode arranged on the first surface of the silicon substrate, and a second electrode arranged on the second surface of the silicon substrate, the second surface of the silicon substrate comprising a metal region and a non-metal region, the second electrode being arranged on the metal region, and the metal region having a first passivation contact structure, the first passivation contact structure comprising a tunneling layer, at least one layer of first doped polysilicon layer, at least one layer of interval layer, and second doped polysilicon layer which are sequentially stacked.

[0034] Optionally, from the perspective of the front projection surface, in the projection direction opposite to the second electrode, the projection width dimension of the metal region on the projection surface is not less than the projection width dimension of the second electrode.

[0035] Optionally, the non-metal region has a second passivation contact structure, the second passivation contact structure comprising a tunneling layer and a first doped polysilicon layer which are sequentially arranged, or comprising a tunneling layer, a first doped polysilicon layer and an interval layer, and a second doped polysilicon layer which are sequentially arranged, or comprising a tunneling layer and a second doped polysilicon layer which are sequentially arranged, or comprising a tunneling layer, at least two layers of first doped polysilicon layer and at least one layer of interval layer which are alternately stacked, or comprising a tunneling layer, at least two layers of first doped polysilicon layer and at least two layers of interval layer which are alternately stacked, and a second doped polysilicon layer.

[0036] Optionally, the first passivation contact structure and the second passivation contact structure have a height difference relative to the back surface of the silicon substrate.

[0037] Compared with the prior art, the present application has the following beneficial effects:

[0038] In the present application, the SE (Selective Emitter) structure on the back surface of the battery has a simple preparation process, and the oxidation of the first region (metal region) can be completed by using a laser process, thereby eliminating the mask manufacturing process in the polysilicon process and the front chain process before the removal of the plated wire.

[0039] In addition, the second doped layer of the second region (non-metal region) on the back of the battery is removed in whole or in part, while the second doped layer of the first region (metal region) is not affected, without changing the paste, the passivation effect and the parasitic absorption are considered, the process window is improved, and the battery efficiency and the double-sided rate are significantly improved;

[0040] The introduction of the interval layer / barrier layer on the back of the battery can effectively improve the change of the doping concentration of the doped layer in the laser process, avoid the damage of the tunneling layer, further improve the passivation effect, and at the same time, the interval layer / barrier layer has a certain blocking ability to the penetration of the back paste, which helps to reduce the total thickness of the back doped layer and improve the open circuit voltage (Voc) of the battery;

[0041] In other words, in the solar cell of the present application, the film layer and its thickness of the passivation contact structure in the grid line region and the non-grid line region are different, the grid line region has a four-layer structure of a tunneling layer, a first doped polysilicon layer, a barrier layer and a second doped polysilicon layer, the thickness is large and has two doped polysilicon layers, which avoids the penetration of the doped polysilicon layer and the damage of the bottom tunneling oxide layer when the grid line paste is sintered, thereby ensuring the field passivation effect; and the non-grid line region only includes a tunneling layer and a first doped polysilicon layer, which greatly thins the thickness compared with the grid line region, reduces the parasitic absorption of the back light, and improves the photoelectric efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0042] FIG. 1 is a schematic structural diagram of a solar cell of the present application;

[0043] FIG. 2 is a flow chart of a preparation method of a passivation contact structure of a solar cell of the present application;

[0044] FIG. 3 is a schematic structural diagram of a solar cell in Example 1 of the present application;

[0045] FIG. 4 is a schematic diagram of a partial structure at A in FIG. 3;

[0046] FIG. 5 is a schematic plan view of a second surface of a silicon substrate in Example 1 of the present application;

[0047] FIG. 6 is a schematic plan view of the second surface and the second electrode in Example 1 of the present application;

[0048] FIGS. 7a-7j are schematic process flow diagrams of the preparation of a solar cell in Example 1 of the present application;

[0049] FIG. 8 is a schematic diagram of a laser scanning pattern in the laser process in Example 1 of the present application;

[0050] FIG. 9 is a schematic structural diagram of a solar cell in Example 2 of the present application;

[0051] FIG. 10 is a schematic diagram of a partial structure at B in FIG. 9;

[0052] Fig. 11 is a schematic diagram of the structure of a solar cell according to Embodiment 3 of the present application;

[0053] Fig. 12 is a schematic diagram of the partial structure at C in Fig. 11;

[0054] Fig. 13 is a schematic diagram of the structure of a solar cell according to Embodiment 4 of the present application;

[0055] Fig. 14 is a schematic diagram of the partial structure at D in Fig. 13;

[0056] Fig. 15 is a schematic diagram of the partial structure of a solar cell according to the present application;

[0057] [Corrected according to Rule 91 10.02.2025] Fig. 16 is an SEM image of a pyramid-textured surface according to the present application;

[0058] [Corrected according to Rule 91 10.02.2025] Fig. 17 is an SEM image of a first region on the back surface of a silicon substrate according to the present application;

[0059] [Corrected according to Rule 91 10.02.2025] Fig. 18 is an SEM image of a second region on the back surface of a silicon substrate according to the present application. DETAILED DESCRIPTION

[0060] In order to make the objects, technical solutions, and advantages of the present application clearer, the following will be used in conjunction with the accompanying drawings and specific embodiments to describe the present application in detail. However, these embodiments are not intended to limit the present application, and any changes made to the structure, method, or function by one of ordinary skill in the art based on these embodiments are included in the protection scope of the present application.

[0061] Here, it should be noted that, in order to avoid obscuring the present application due to unnecessary details, only structures and / or processing steps closely related to the solutions of the present application are shown in the accompanying drawings, and other details not closely related to the present application are omitted. Some dimensions of the structures or parts in the drawings can be exaggerated relative to other structures, and this is only used to show the basic structure of the subject matter of the present application.

[0062] In addition, it should also be noted that the terms "comprise", "include" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or equipment including a series of elements includes not only those elements, but also other elements not explicitly listed, or further includes elements inherent to such a process, method, article, or equipment.

[0063] Again, in the present application, unless otherwise explicitly specified and limited, the first feature is "on" or "under" the second feature can be that the first and second features are in direct contact, or the first and second features are indirectly in contact through an intermediate medium. Moreover, the first feature "on", "above" and "on top of" the second feature can be that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is horizontally higher than the second feature. The first feature "under", "below" and "underneath" the second feature can be that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is horizontally lower than the second feature.

[0064] The inventor found that the doping polysilicon layer on the back of the TOPCon solar cell is limited by the sintering window of the paste and cannot be further thinned down, but the thicker doping polysilicon layer has high parasitic absorption of light, which affects the utilization of back light and in turn affects the cell efficiency. Based on this, the present application optimizes the passivation contact structure on the back of the TOPCon solar cell, ensures the thickness required by the grid line area, avoids the penetration of the doping polysilicon layer and the damage to the bottom tunneling oxide layer during the sintering of the grid line paste, thereby ensuring the field passivation effect; at the same time, the doping polysilicon layer in the non-grid line area is thinned to reduce the parasitic absorption of long-wavelength light on the back.

[0065] Fig. 1 shows the schematic structure of the solar cell 100 of the present application, which is a TOPCon cell, including a silicon substrate 10, a passivation contact structure 20 / 30 arranged on the back of the silicon substrate 10, electrodes 41 / 42 arranged on the front and back of the silicon substrate 10 respectively, passivation layers 51 / 52 and anti-reflection layers 61 / 62. The solar cell 100 of the present application realizes the field passivation on the back through the passivation contact structure 20 / 30, thereby improving the cell efficiency.

[0066] It can be understood that the front of the silicon substrate 10 is the light-receiving surface, and the back is the back light surface. The back of the silicon substrate 10 includes a metal area and a non-metal area. The metal area can be a grid line area, and the non-metal area is a non-grid line area. The electrodes include a front electrode 41 arranged on the light-receiving surface of the silicon substrate 10, and a back electrode 42 arranged on the back grid line area. The passivation layers and the anti-reflection layers include front passivation layers 51, back passivation layers 52, front anti-reflection layers 61 and back anti-reflection layers 62, respectively. The structure on the front of the silicon substrate 10 can be a front diffusion layer, a front passivation layer 51 and a front anti-reflection layer 61 arranged in sequence, etc.

[0067] The film layer materials and thicknesses of the metal area and the non-metal area on the back of the silicon substrate 10 are optimized in the present application, and the back passivation effect and the utilization of light are improved at the same time. A first passivation contact structure 20 is formed in the metal area, and a second passivation contact structure 30 is formed in the non-metal area.

[0068] Figure 2 is a schematic process flow chart for preparing the passivated contact structure 20 / 30 of the solar cell 100 of the present application, the preparation method of the passivated contact structure comprising the following steps:

[0069] S1: sequentially depositing a tunnel layer 12, a first phosphorus-doped amorphous silicon layer 13, a spacer / barrier layer 14, and a second phosphorus-doped amorphous silicon layer 15 on the back surface of the silicon substrate 10;

[0070] S2: performing scanning on the grid line area of the second phosphorus-doped amorphous silicon layer 15 to form an oxide layer mask by oxidation, preferably, the oxide layer is formed by laser treatment in a high-concentration oxygen atmosphere;

[0071] S3: annealing treatment to convert the first phosphorus-doped amorphous silicon layer 13 into a first doped polysilicon layer 131 and the second phosphorus-doped amorphous silicon layer 15 into a second doped polysilicon layer 132;

[0072] S4: removing the second doped polysilicon layer 132 in the non-grid line area;

[0073] S5: removing the oxide layer mask and the barrier layer 14 to form a first passivated contact structure 20 in the grid line area and a second passivated contact structure 30 in the non-grid line area.

[0074] The solar cell and the preparation method thereof of the present application will be further described in detail below in combination with specific embodiments.

[0075] Embodiment 1

[0076] Figures 3 to 8 show the solar cell and the preparation method thereof of Embodiment 1.

[0077] Figure 3 shows a schematic structural diagram of the solar cell 100 in Embodiment 1, which is a TOPCon cell, comprising a silicon substrate 10, as shown in Figure 7a, the silicon substrate 10 comprises a first surface S1 and a second surface S2 arranged oppositely, the second surface S2 comprises a first region S21 and a second region S22, the first surface S1 is the front surface (i.e. light-receiving surface) of the silicon substrate 10, the second surface S2 is the back surface (i.e. back light surface) of the silicon substrate 10, the first region S21 is a back surface metal region, and the second region S22 is a back surface non-metal region. The back surface metal region is a grid line area, and the back surface non-metal region is a non-grid line area.

[0078] The silicon substrate 10 in Embodiment 1 is an N-type silicon substrate, and the resistivity is 0.3Ω·cm to 7Ω·cm, preferably 0.5Ω·cm to 3.5Ω·cm.

[0079] Further, a light-trapping structure is formed on the first surface S1 of the silicon substrate 10, for example, a pyramid texture 70 (as shown in FIG. 1) can be formed on the first surface S1 of the silicon substrate 10 by alkali texturing, and the pyramid size is 0.5 μm to 3 μm. The pyramid texture 70 can reduce the front surface reflectivity of the solar cell, and in other embodiments, the pyramid texture 70 can also be a non-pyramid structure.

[0080] In the embodiment 1, the front surface doped layer 11 (i.e. emitter) is formed on the first surface S1 of the silicon substrate 10 by a diffusion process or a PECVD process. For example, the front surface doped layer 11 is a P-type doped layer (i.e. P+ emitter) formed by a boron doping process, and the doping concentration is 3E+18 cm -3 to 3E+19 cm -3 , the sheet resistance is 40 Ω / sq to 300 Ω / sq, and preferably 150 Ω / sq to 250 Ω / sq.

[0081] Referring to FIG. 3 and in combination with FIG. 4, in the embodiment 1, the first passivated contact structure 20 is formed on the first region S21 on the second surface S2 of the silicon substrate 10, and the first passivated contact structure 20 is composed of a tunneling layer 12, a first doped layer 131, a spacer / barrier layer 14, and a second doped layer 132 which are sequentially stacked. The tunneling layer 12 is one or a combination of a silicon oxide layer, a silicon oxynitride layer, and preferably a silicon oxide layer, and the thickness is 0.5 nm to 3 nm, and preferably 1.5 nm to 2.5 nm. The spacer / barrier layer 14 is one or a combination of a silicon oxide layer, a silicon carbide layer, and the like, and the thickness is 0.5 nm to 3 nm, and preferably 1.5 nm to 2 nm. In terms of material selection, the actual scene requirements can be selected, for example, the silicon carbide layer can also be used in the tunneling layer, or the silicon oxynitride layer can also be used in the spacer / barrier layer, and the like, which will not be described here. For the convenience of understanding, in the following embodiments, the barrier layer 14 is described.

[0082] In the embodiment 1, the second passivated contact structure 30 is formed on the second region S22 on the second surface S2 of the silicon substrate 10, and the second passivated contact structure 30 is composed of a tunneling layer 12 and a first doped layer 131 which are sequentially stacked. Understandably, the tunneling layer 12 and the first doped layer 131 on the second region S22 are completely the same as the tunneling layer 12 and the first doped layer 131 on the first region S21, which will not be described here.

[0083] In the present application, the first doped layer 131 and the second doped layer 132 have the same doping type as the silicon substrate, and the surface doping concentration of the second doped layer 132 can be greater than the surface doping concentration of the first doped layer 131; at the same time, the thickness of the second doped layer 132 can be greater than the thickness of the first doped layer 131, and the total thickness of the first doped layer 131 and the second doped layer 132 is 50nm-150nm, preferably 60nm-100nm.

[0084] Exemplarily, in embodiment 1, the first doped layer 131 is a phosphorus-doped polysilicon layer, the surface doping concentration is 1E+20cm -3 -9E+20cm -3 , preferably 3E+20cm -3 -5E+20cm -3 , and the thickness is 1nm-100nm, preferably 1nm-50nm; the second doped layer 132 is a phosphorus-doped polysilicon layer, the surface doping concentration is 2E+20cm -3 -3E+21cm -3 , preferably 5E+20cm -3 -2E+21cm -3 , and the thickness is 1nm-100nm, preferably 1nm-50nm.

[0085] Preferably, in embodiment 1, the front surface S1 of the silicon substrate 10 is sequentially stacked with a front passivation layer 51 and a front anti-reflection layer 61, the second surface S2 of the silicon substrate 10 is sequentially stacked with a back passivation layer 52 and a back anti-reflection layer 62, and the back passivation layer 52 and the back anti-reflection layer 62 cover the second doped layer 132 and extend into the second area S22. Exemplarily, the front passivation layer 51 and the back passivation layer 52 are both aluminum oxide passivation layers, and the thickness is 2nm-7nm, preferably 3nm-6nm; the front anti-reflection layer 61 and the back anti-reflection layer 62 can be any one or a stack film formed by one or more of silicon nitride layer, silicon oxynitride layer and silicon oxide layer, and the thickness is 60nm-130nm.

[0086] In addition, in embodiment 1, the front electrode 41 is located on the first surface S1 of the silicon substrate 10 and in contact with the front doped layer 11, and the back electrode 42 is located on the second surface S2 of the silicon substrate 10, specifically on the first area S21 in the second surface S2, and in contact with the second doped layer 132.

[0087] Referring to FIG. 5, the first region S21 in the embodiment 1 includes a plurality of first sub-regions 101 which are parallel and equidistantly distributed, the second region S22 includes a plurality of second sub-regions 102 which are parallel and equidistantly distributed, and the first sub-regions 101 and the second sub-regions 102 are staggered. The width of the first sub-regions 101 is less than the width of the second sub-regions 102, for example, the width ratio of the two can be 1:(5-20), preferably, the first region S21 accounts for about 10% of the area of the second surface S2.

[0088] Referring to FIG. 6, the second electrode 42 is a gate line electrode, which includes at least a plurality of fine gate lines 421 which are parallel distributed, and the width of the first sub-regions 101 is greater than or equal to the width of the fine gate lines 421. Optionally, the second electrode 42 can also include a plurality of main gate lines (not shown) which are perpendicular to the fine gate lines 421.

[0089] In this embodiment, taking the 210TOPCon cell as an example, the size is 203.396±15mm, the number of the fine gate lines 421 is 230, the width is 15μm-100μm, and the distance between adjacent fine gate lines is 0.907±0.015mm. The distance between adjacent first sub-regions 101 is equal to the distance between adjacent fine gate lines, one fine gate line 421 is distributed on each first sub-region 101, the width of the first sub-region 101 is greater than the width of the fine gate line 421, and the width of the first sub-region is 50μm-150μm, for example, when the width of the fine gate line is 40μm, the width of the first sub-region is 80μm.

[0090] It should be noted that, from the perspective of the front projection plane, when observed in the projection direction opposite to the second electrode 42, the projection width of the metal region on the projection plane is not less than the projection width of the second electrode 42.

[0091] The preparation method of the solar cell in this embodiment specifically includes the following steps:

[0092] 1. Double-sided texturing

[0093] Referring to FIG. 7a, a silicon substrate 10 is provided, which includes a first surface S1 and a second surface S2 arranged oppositely, the second surface S2 includes a first region S21 and a second region S22, the first surface S1 is the front surface (i.e. the light-receiving surface) of the silicon substrate 10, the second surface S2 is the back surface (i.e. the back light surface) of the silicon substrate 10, the first region S21 is a back surface gate line region, and the second region S22 is a back surface non-gate line region.

[0094] The silicon substrate 10 in this embodiment is an N-type silicon substrate, and the resistivity is 0.3Ω·cm-7Ω·cm, preferably 0.5Ω·cm-3.5Ω·cm.

[0095] Referring to FIG. 7b, the first surface S1 and the second surface S2 of the silicon substrate 10 are formed with a pyramid texturing structure by an alkali texturing process, and the pyramid size is 0.5 μm to 3 μm.

[0096] 2. Boron diffusion

[0097] Referring to FIG. 7c, a P-type doped front surface doped layer (i.e., P+ emitter) 11 is formed on the first surface S1 of the silicon substrate 10 by a boron diffusion process. Specifically, the boron source deposition propulsion method is used in a high-temperature furnace tube for diffusion. After diffusion, the doping concentration of the first doped layer is 3E+18 cm -3 ~ 3E+19 cm -3 , the square resistance is 40 Ω / sq to 300 Ω / sq, and preferably 150 Ω / sq to 250 Ω / sq. In the boron diffusion process, the second surface S2 of the silicon substrate is formed with a BSG (not shown).

[0098] 3. Back surface polishing

[0099] Referring to FIG. 7d, the silicon substrate 10 after boron diffusion is first passed through a single-sided chain device, and the back surface silicon oxide is removed by using a hydrofluoric acid solution. Then, the back surface is subjected to alkali polishing to remove the edge junction and the back surface plating (BSG). Finally, the silicon substrate 10 is cleaned.

[0100] 4. Preparation of back surface tunneling passivation contact structure

[0101] Referring to FIG. 7e, a tunneling layer 12, a first doped layer 131, a barrier layer 14, and a second doped layer 132 are sequentially formed on the second surface S2.

[0102] Exemplarily, in the embodiment, a 1 nm to 3 nm thick silicon oxide tunneling layer is first deposited on the back surface by using a PECVD process, and then a 1 nm to 100 nm thick, and preferably 1 nm to 50 nm thick, phosphorus-doped amorphous silicon layer is deposited. Then, a 1 nm to 3 nm thick, and preferably 1.5 nm to 2 nm thick, silicon oxide barrier layer is deposited. Finally, a 1 nm to 50 nm thick, and preferably 50 nm to 100 nm thick, phosphorus-doped amorphous silicon layer is deposited.

[0103] 5. Annealing activation

[0104] The silicon substrate 10 on which the tunneling layer 12, the first doped layer 131, the barrier layer 14, and the second doped layer 132 are deposited is subjected to annealing treatment. Before the annealing treatment, the first doped layer 131 and the second doped layer 132 are both phosphorus-doped amorphous silicon layers, and the annealing treatment is used to convert the phosphorus-doped amorphous silicon layers into doped polycrystalline silicon layers.

[0105] Exemplarily, in the embodiment, the annealing treatment is performed in a high-temperature annealing furnace, the annealing temperature is 880-980°C, preferably 900-950°C, after the annealing, the doped amorphous silicon is converted into doped polysilicon, the phosphorus is activated, and the tunneling passivation contact structure can be formed on the back surface, the surface doping concentration of the first doped layer 131 is 1E+20 cm -3 ~ 9E+20 cm -3 , preferably 3E+20 cm -3 ~ 5E+20 cm -3 , such as 4E+20 cm -3 , the surface doping concentration of the second doped layer 132 is 2E+20 cm -3 ~ 3E+21 cm -3 , preferably 5E+20 cm -3 ~ 2E+21 cm -3 , such as 1E+21 cm -3 .

[0106] 6. Laser oxidation

[0107] Referring to FIG. 7f, the second doped layer 132 on the first region S21 is processed by a laser process, and an oxide layer 133 is formed on the surface of the second doped layer on the first region S21.

[0108] In the laser oxidation step, a silicon oxide (SiOX) layer is formed on the surface of the phosphorus-doped amorphous silicon layer on the first region S21 by using the instantaneous high temperature of the laser, and the silicon oxide layer serves as a mask for subsequent processes.

[0109] Specifically, the laser process is performed in an atmosphere containing oxygen, the volume concentration of oxygen is 20%-80%; the laser power is 1-100 W, preferably 30-60 W; the laser frequency is 1-1000 kHz, preferably 300-600 kHz; the laser scanning rate is 10000-100000 mm / s, preferably 30000-60000 mm / s; the laser processing times is 1-100, preferably 1-10. The thickness of the oxide layer 133 formed by the laser process is 1-50 nm.

[0110] Exemplarily, in a specific embodiment of the laser process, the volume concentration of oxygen is 20%, the laser power is 50 W, the laser frequency is 500 kHz, the laser scanning rate is 50000 mm / s, and the laser processing times is 2.

[0111] FIG. 8 shows the laser scanning pattern in the laser process of the embodiment, the black line part corresponds to the laser scanning region, i.e., the first region S21 (i.e., the metal gate line region), and the blank part is the second region S22 (i.e., the non-gate line region).

[0112] After the laser process, the first region S21 is formed with a structure of tunneling layer + phosphorus-doped polysilicon layer + barrier layer + phosphorus-doped polysilicon layer + silicon oxide layer, and the second region S22 is formed with a structure of tunneling layer + phosphorus-doped polysilicon layer + barrier layer + phosphorus-doped polysilicon layer.

[0113] It should be understood that the laser scanning pattern in the present application can be designed according to different electrode structures, so as to form a patterned silicon oxide mask in the laser scanning region (i.e. the back metal region). The laser scanning pattern for other electrode structures is not exemplified here. In addition, the annealing step and the oxidation step can be exchanged in order according to the actual processing scene, that is, the mask can be formed first, and then the phosphorus-doped amorphous silicon layer is converted into a doped polysilicon layer through annealing.

[0114] In the prior art, a mask layer is usually deposited by a PECVD process and is patterned. In the present application, the patterned mask can be prepared by one-step laser process, which greatly simplifies the process flow.

[0115] High temperature is generated in the laser process, which has a great influence on the doping amount of phosphorus, and is easy to cause excessive phosphorus to pass through and damage the tunneling layer, resulting in poor surface passivation effect and serious low open-circuit voltage of the battery. In the present application, the barrier layer is introduced to have a certain blocking effect on the advancement of phosphorus. By controlling the laser process parameters, the stack structure of the barrier layer and the doped layer with different layers can be adapted.

[0116] 7. Removing the wrap plating and chemical etching

[0117] As shown in FIGS. 7f and 7g, the chemical etching process is used to remove the entire second doped layer 132 on the second region S22 and the oxide layer 133 on the first region S21, and the second doped layer 132 on the first region S21 is retained, and then the first passivation contact structure 20 is formed at the first region S21, and the second passivation contact structure 30 is formed at the second region S22.

[0118] This step specifically includes:

[0119] Alkali etching: using the oxide layer 133 as a mask, the second doped layer 132 on the second region S22 is removed by using an alkali solution, and the front and edge wrap plating are also removed, the mass fraction of the alkali solution is 3% to 5%, and the processing time is 100s to 500s, and preferably 350s;

[0120] Acid washing: using an acid solution to remove the barrier layer 14 on the second region S22 and the oxide layer on the first region S21, and also removing the front PSG, the mass fraction of the acid solution is 5% to 20%, and the processing time is 100s to 500s, and preferably 300s;

[0121] Finally, RCA cleaning is performed. RCA cleaning is a prior art and will not be described here.

[0122] Preferably, the acid solution in this embodiment is obtained by mixing an industrial-grade hydrofluoric acid solution (mass fraction ~ 40%) with water in a certain proportion, and the base solution is obtained by mixing an industrial-grade sodium hydroxide solution (mass fraction ~ 32%) with water in a certain proportion.

[0123] In the prior art, a front chain process (acid washing) is usually performed before the alkali etching step. The silicon oxide mask is formed by the PECVD process in this embodiment, and no silicon oxide is formed on the edge, so the front chain process is not required.

[0124] 8. Preparation of passivation layer

[0125] As shown in FIG. 7h, a front passivation layer 51 and a back passivation layer 52 are respectively prepared on the first surface S1 and the second surface S2 of the silicon substrate by an ALD process. The front passivation layer 51 and the back passivation layer 52 are both aluminum oxide passivation layers, and the thickness is 2 nm to 7 nm, preferably 3 nm to 6 nm.

[0126] 9. Preparation of anti-reflection layer

[0127] As shown in FIG. 7i, a front anti-reflection layer 61 and a back anti-reflection layer 62 are respectively prepared on the first surface S1 and the second surface S2 of the silicon substrate by a PECVD process. The front anti-reflection layer 61 and the back anti-reflection layer 62 can be any one or a stack of multiple layers selected from a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer, and the thickness is 60 nm to 130 nm.

[0128] 10. Printing of metal electrode

[0129] As shown in FIG. 7j, a front electrode 41 and a back electrode 42 are respectively printed on the front and back surfaces by a screen printing process, and then sintering and light injection or electrical injection treatment are performed to form an ohmic contact.

[0130] The front electrode 41 and the back electrode 42 are gate line electrodes in the prior art, which usually include a main gate line and a fine gate line. It should be noted that the fine gate line in the back electrode 42 needs to be printed on the first region, so the width of the first sub-region needs to be greater than the width of the fine gate line in the back electrode 42, so that the alignment of the fine gate line can be achieved.

[0131] The TOPCon cell can be prepared by the above steps, and finally the cell is tested, sorted, and stored.

[0132] Example 2

[0133] Referring to FIG. 9 and in combination with FIG. 10, the solar cell 100 in Embodiment 2 is substantially the same as the solar cell structure in Embodiment 1, except that in Embodiment 2, the second passivation contact structure 30 formed at the second region S22 of the second surface S2 of the silicon substrate 10 is composed of a tunneling layer 12, a first doped layer 131 and a barrier layer 14, and a second doped layer 132a, which are sequentially stacked. The tunneling layer 12, the first doped layer 131, and the barrier layer 14 of the second passivation contact structure 30 are completely the same as the tunneling layer 12, the first doped layer 131, and the barrier layer 14 in the first passivation contact structure 20 at the first region S21, except that the thickness of the second doped layer 132a in the second passivation contact structure 30 is less than the thickness of the second doped layer 132 in the first passivation contact structure 20.

[0134] The preparation method of the solar cell in this embodiment is also substantially the same as the preparation method in Embodiment 1, except that the stripping and chemical etching step in the seventh step. In Embodiment 2, a chemical etching process is used to remove part of the second doped layer 132 on the second region S22 and the oxide layer 133 on the first region S21, retain the second doped layer 132 on the first region S21, and thin the second doped layer 132 on the second region S22 to form the second doped layer 132a, instead of completely removing it.

[0135] This step specifically includes:

[0136] Alkaline etching: using an alkaline solution to remove part of the second doped layer 132 on the second region S22 (finally retaining part of the second doped layer 132a), while removing the front and edge wrap plating, the mass fraction of the alkaline solution is 3% to 15%, and the processing time is less than that in Embodiment 1, such as 50s;

[0137] Acid washing: using an acid solution to remove the oxide layer 133 on the first region S21, while removing the front PSG, the mass fraction of the acid solution is 5% to 20%, and the processing time is 100s to 500s, preferably 300s;

[0138] Finally, RCA cleaning is performed, which is a prior art and will not be described here.

[0139] In Embodiment 2, since part of the second doped layer 132a on the second region S22 is retained, the acid solution will not corrode the barrier layer 14 on the second region S22 during the acid washing process, and therefore the barrier layer 14 and part of the second doped layer 132a are retained on the second region.

[0140] Embodiment 3

[0141] Referring to FIG. 11 and in combination with FIG. 12, the solar cell 100 in Embodiment 3 is substantially the same as the solar cell structure in Embodiment 1, except that in Embodiment 3, the tunneling layer 12 on the second surface S2 of the silicon substrate 10 is provided with the first doped layer 131 and the barrier layer 14 which are alternately stacked.

[0142] Specifically, in Embodiment 3, the first region S21 on the second surface S2 of the silicon substrate 10 is sequentially provided with the tunneling layer 12, the first doped layer 131, the barrier layer 14, the first doped layer 131, the barrier layer 14 and the second doped layer 132, and the second region S22 on the second surface S2 of the silicon substrate 10 is sequentially provided with the tunneling layer 12, the first doped layer 131 and the barrier layer 14. In other words, in Embodiment 3, the first passivated contact structure 20 is six layers, which is sequentially stacked by the tunneling layer 12, the first doped layer 131, the barrier layer 14, the first doped layer 131, the barrier layer 14 and the second doped layer 132. The second passivated contact structure 30 is four layers, which is sequentially stacked by the tunneling layer 12, the first doped layer 131, the barrier layer 14 and the first doped layer 131.

[0143] The preparation method of the solar cell in Embodiment 3 is substantially the same as the preparation method of the solar cell in Embodiment 1, except that the preparation step of the back surface tunneling passivation structure in Step 4.

[0144] For example, in Embodiment 3, a PECVD process is used to first deposit a 1 nm to 3 nm thick silicon oxide tunneling layer on the back surface, and then deposit a phosphorus-doped amorphous silicon layer; then deposit a silicon oxide barrier layer; then deposit a phosphorus-doped amorphous silicon layer; then deposit a silicon oxide barrier layer; and finally deposit a phosphorus-doped amorphous silicon layer. The total thickness of all the phosphorus-doped amorphous silicon layers is controlled to be 50 nm to 150 nm, preferably 60 nm to 100 nm, and the thickness of the outermost phosphorus-doped amorphous silicon layer is preferably 50 nm to 100 nm.

[0145] Correspondingly, in the step of removing the passivation layer and chemical etching in Step 7 of Embodiment 3, the second doped layer 132 on the second region S22 is removed by alkali etching, and the outermost barrier layer 14 on the second region S22 and the oxide layer 133 on the first region S21 are removed by acid solution.

[0146] Embodiment 4

[0147] Referring to FIG. 13 and in combination with FIG. 14, the solar cell in Embodiment 4 is substantially the same as the solar cell in Embodiment 3, except that in Embodiment 4, the second passivation contact structure 30 on the second region S22 on the second surface S2 of the silicon substrate 10 is composed of the tunneling layer 12, the first doped layer 131, the barrier layer 14, the first doped layer 131, the barrier layer 14, and the second doped layer 132a, which are sequentially stacked. The thickness of the second doped layer 132a is less than the thickness of the second doped layer 132 of the first passivation contact structure. In other words, in Embodiment 4, the first passivation contact structure 20 has six layers, and the second passivation contact structure 30 also has six layers.

[0148] The method for preparing the solar cell in Embodiment 4 is substantially the same as the method for preparing the solar cell in Embodiment 3, except that the seventh step of removing the plating and chemical etching. In Embodiment 4, a chemical etching process is used to remove part of the second doped layer 132 on the second region S22 and the oxide layer 133 on the first region S21, retain the second doped layer 132 on the first region S21, and thin the second doped layer 132 on the second region S22 to form the second doped layer 132a, instead of completely removing it.

[0149] In Embodiment 4, since part of the second doped layer 132a on the second region S22 is retained, when the acid washing process is performed, the acid solution does not corrode the outermost barrier layer 14 on the second region S22. Therefore, the outermost barrier layer 14 and part of the second doped layer 132a are retained at the second region S22.

[0150] Embodiment 5

[0151] The solar cell and the method for preparing the solar cell in Embodiment 5 are substantially the same as the solar cell and the method for preparing the solar cell in Embodiment 1, except that the front doped layer 11 in Embodiment 1 is prepared by a boron diffusion process, while the front doped layer 11 in Embodiment 5 is prepared by a PECVD process.

[0152] Specifically, in this embodiment, a boron-doped amorphous silicon layer is first deposited on the first surface S1 by a PECVD process, and then a P-type doped polysilicon layer is formed after high-temperature oxidation and annealing.

[0153] It should be understood that the above-mentioned Embodiments 3 and 4 are described by taking two layers of second doped layers and two layers of barrier layers as an example, and in other embodiments, three or more layers of second doped layers and barrier layers can also be provided. Any technical solution that removes all or part of the third doped layer on the second region S22 by alkali etching falls within the scope of protection of the present application, and will not be described one by one here.

[0154] In summary, in the solar cell 100 described in Embodiments 1-5 above, the first passivated contact structure 20 provided in the first region S21 includes the tunneling layer 12, at least one first doped layer 131, at least one barrier layer 14, and a second doped layer 132. The electrode 42 contacts the second doped layer 132. Between the tunneling layer 12 and the second doped layer 132, the first doped layer 131 and the barrier layer 14 can be alternately arranged according to actual scenarios. It can be understood that a back passivation layer 52 and a back anti-reflection layer 62 are further formed on the back of the second doped layer 132.

[0155] Similarly, the second passivated contact structure 30 provided in the second region S22 includes the tunneling layer 12 and the first doped layer 131. In some design scenarios, the second passivated contact structure 30 can further include the barrier layer 14 and the first doped layer 131 on the back of the first doped layer 131; in other design scenarios, the second passivated contact structure 30 can further include the barrier layer 14 and a second doped layer 132a on the back of the first doped layer 131; and the first doped layer 131 and the barrier layer 14 can be alternately arranged between the tunneling layer 12 and the second doped layer 132a. In addition, the second doped layer 132a in the second passivated contact structure 30 and the second doped layer 132 in the first passivated contact structure 20 are the same doped layer, and the thicknesses of the two are different. Furthermore, the back passivation layer 52 and the back anti-reflection layer 62 are also provided on the back of the outermost first doped layer 131 or the second doped layer 132a of the second passivated contact structure 30.

[0156] Referring to FIG. 15, in the present application, a height difference H1 / H2 is formed between the first passivated contact structure 20 and the second passivated contact structure 30. The label H1 represents the height difference formed between the outer side of the back anti-reflection layer 62 of the first region S21 and the outer side of the back anti-reflection layer 62 of the second region S22; and the label H2 represents the height difference formed along the thickness direction of the silicon substrate 10 between the outermost surface of the first passivated contact structure 20 and the outermost surface of the second passivated contact structure 30.

[0157] In terms of the present application, according to the number of layers and the composition of the first passivated contact structure 20 and the second passivated contact structure 30, the value of the height difference H1 / H2 is equal to the thickness difference between the second doped layer 132 and the second doped layer 132a, or equal to the sum of the thicknesses of the barrier layer 14 and the second doped layer 132. For example:

[0158] In Embodiment 1, the first passivated contact structure 20 has four layers, and the second passivated contact structure 30 has two layers, and thus the height difference H1 / H2 between the two is equal to the sum of the thicknesses of the barrier layer 14 and the second doped layer 132.

[0159] In Embodiment 2, the first passivation contact structure 20 is four layers, and the second passivation contact structure 30 is four layers, and the height difference H1 / H2 between the two is equal to the thickness difference between the second doped layer 132 and the second doped layer 132a.

[0160] In Embodiment 3, the first passivation contact structure 20 is six layers, and the second passivation contact structure 30 is four layers, and the height difference H1 / H2 between the two is equal to the sum of the thicknesses of the barrier layer 14 and the second doped layer 132.

[0161] In Embodiment 4, the first passivation contact structure 20 is six layers, and the second passivation contact structure 30 is six layers, and the height difference H1 / H2 between the two is equal to the thickness difference between the second doped layer 132 and the second doped layer 132a.

[0162] It can be understood that when the thickness of the back passivation layer 52 in the first region S21 and the second region S22 is inconsistent, and / or the thickness of the back anti-reflection layer 62 in the first region S21 and the second region S22 is inconsistent, the height difference H1 / H2 between the first and second passivation contact structures 20, 30 also includes the thickness difference of the back passivation layer / back anti-reflection layer 52, 62. Examples are not described here.

[0163] In the present application, the preferred value of the height difference H1 / H2 is 0.01 μm-8 μm.

[0164] Referring to FIGS. 16-18, the size of the pyramid structure 70 in the present application is in the range of 0.5 μm-3 μm. FIG. 16 is a SEM image of the pyramid structure 70 in the present application, and the three pyramid sizes indicated are 2.67 μm, 2.60 μm and 2.75 μm, and the average of all pyramid sizes is about 2.7 μm. The first region S21 and the second region S22 of the second surface S2 are both polished surfaces after polishing of the pyramid structure. Among them, the silicon substrate 10 is recessed on the second region S22, and the size of the tower base on the first region S21 is smaller than the size of the tower base on the second region S22. In the alkali polishing process, the pyramid structure on the back of the silicon substrate is polished to form a tower base, which is the base left after polishing of the pyramid structure. The tower base can be triangular, quadrilateral, etc., and the size of the tower base is defined as the average of the width of the tower base pattern. In the case of a square tower base, the size of the tower base is the average of the square side length. The size of the tower base formed in the alkali polishing process will be larger than the size of the pyramid, and the deeper the etching depth, the larger the size of the tower base. In the present application, the size of the tower base on the first region S21 is 3 μm-20 μm, preferably 8 μm-15 μm, and the size of the tower base on the second region is 3 μm-50 μm, preferably 15 μm-30 μm.

[0165] Figure 17 shows the SEM image of the first area S21, and the tower base sizes marked in the figure are 11.37 μm, 11.52 μm, 11.44 μm, 11.53 μm, 11.13 μm, and the average size of the tower base on the first area S21 is about 11.4 μm. Figure 18 shows the SEM image of the second area S22, and the etching depth of the second area S22 is deeper, and the tower base size formed is larger, such as the tower base sizes marked in the figure are 20.30 μm, 20.23 μm, 19.29 μm, and the average size of the tower base on the second area S22 is about 20 μm.

[0166] The preparation process of the battery back SE (Selective Emitter) structure in the application is simple, and the oxidation of the first area (metal area) can be completed by using a laser process, thereby eliminating the mask manufacturing process in the polysilicon process and the front chain process before the plating is removed;

[0167] In addition, the second doping layer of the second area (non-metal area) on the back of the battery is removed in whole or in part, and the second doping layer of the first area (metal area) is not affected, without changing the paste, the passivation effect and the reduction of parasitic absorption can be considered, the process window is improved, and the battery efficiency and the double-sided rate are significantly improved;

[0168] The introduction of the back barrier layer of the battery can effectively improve the doping concentration change of the doping layer in the laser process, avoid the damage of the tunneling layer, further improve the passivation effect, and at the same time, the barrier layer has a certain blocking ability to the penetration of the back paste, which helps to reduce the total thickness of the back doping layer and improve the open circuit voltage (Voc) of the battery.

[0169] It is apparent for those skilled in the art that the application is not limited to the details of the above-described exemplary embodiments, but can be implemented in other concrete forms without departing from the spirit or essential characteristics of the application. Therefore, the embodiments should be considered as exemplary and non-limiting, and the scope of the application is defined by the appended claims rather than the above description, and all changes falling within the meaning and range of the equivalent elements of the claims are intended to be included in the application. Any reference signs in the claims should not be regarded as limiting the claims involved.

[0170] In addition, it should be understood that although the present specification is described in terms of embodiments, not every embodiment contains only one independent technical solution, and the description of the specification is only for the sake of clarity, and those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can be combined appropriately to form other embodiments that those skilled in the art can understand.

Claims

1. A solar cell comprising a silicon substrate, a passivated contact structure on the backside of the silicon substrate, a backside electrode on the backside of the passivated contact structure; characterized in that, The passivation contact structure comprises a tunneling layer on the back surface of the silicon substrate, a first doped polysilicon layer on the back surface of the tunneling layer, a spacer layer on the back surface of the first doped polysilicon layer, and a second doped polysilicon layer on the back surface of the spacer layer, wherein the spacer layer is discontinuously arranged.

2. The solar cell according to claim 1, characterized in that, The spacer layer is selected from a combination of one or more of a silicon oxide layer, a silicon oxynitride layer, or a silicon carbide layer.

3. The solar cell according to claim 1, characterized in that, The thickness of the tunneling layer is 1-3 nm, and / or the thickness of the spacer layer is 0.5-3 nm, preferably, the thickness of the tunneling layer and the spacer layer is 1.5-2 nm.

4. The solar cell of claim 1, wherein The thickness of the first doped polysilicon layer is less than or equal to the thickness of the second doped polysilicon layer.

5. The solar cell of claim 1, wherein The doping type of the first doped polysilicon layer and the second doped polysilicon layer is the same as the doping type of the silicon substrate, and the doping concentration of the second doped polysilicon layer is greater than the doping concentration of the first doped polysilicon layer; or the doping concentration of the first doped polysilicon layer is 1E+20cm -3 ~ 9E+20cm -3 , and the doping concentration of the second doped polysilicon layer is 2E+20cm -3 ~ 3E+21cm -3 .

6. The solar cell of claim 1, wherein The solar cell further comprises a back surface passivation layer and a back surface anti-reflection layer arranged in sequence on the back surface of the passivation contact structure, and a front surface diffusion layer, a front surface passivation layer, a front surface anti-reflection layer, and a front surface electrode arranged in sequence on the front surface of the silicon substrate. The back surface electrode is in contact with the second doped polysilicon layer through the back surface anti-reflection layer and the back surface passivation layer, and the front surface electrode is in contact with the front surface diffusion layer through the front surface anti-reflection layer and the front surface passivation layer.

7. A method for preparing a solar cell, characterized in that: The method comprises the following steps: Depositing a tunneling layer, a first doped amorphous silicon layer, a spacer layer, and a second doped amorphous silicon layer in sequence on the back surface of a silicon substrate; Forming a mask layer on the second doped amorphous silicon layer; Converting the first doped amorphous silicon layer into a first doped polysilicon layer and the second doped amorphous silicon layer into a second doped polysilicon layer; Removing the second doped polysilicon layer in regions other than the mask layer; and Removing the mask layer and part of the spacer layer to form a discontinuous spacer layer. The method comprises the following steps:

8. A method for producing a solar cell, characterized by, Providing a silicon substrate comprising a first surface and a second surface arranged oppositely, wherein the second surface comprises a first region and a second region; Preparing a tunneling layer, a first phosphorus-doped amorphous silicon layer, a spacer layer, and a second phosphorus-doped amorphous silicon layer in sequence on the second surface of the silicon substrate; Converting the first phosphorus-doped amorphous silicon layer into a first doped polysilicon layer and the second phosphorus-doped amorphous silicon layer into a second doped polysilicon layer; Forming a mask layer on the surface of the second doped polysilicon layer in the first region; Removing at least part of the second doped polysilicon layer in the second region and the mask layer in the first region while retaining the second doped polysilicon layer in the first region; Preparing an electrode in contact with the second doped polysilicon layer on the first region. Using an alkali solution to remove all of the second doped polysilicon layer on the second region with the oxide layer as a mask layer, and then using an acid solution to remove the outermost spacer layer on the second region and the oxide layer on the first region; or using an alkali solution to remove part of the second doped polysilicon layer on the second region with the oxide layer as a mask layer, and then using an acid solution to remove the oxide layer on the first region.

9. The production method according to claim 8, characterized by, The tunneling layer is one or a combination of both of a silicon oxide layer and a silicon oxynitride layer, and has a thickness of 1-3 nm; and / or the spacer layer is one or a combination of two or more of a silicon oxide layer, a silicon oxynitride layer, and a silicon carbide layer, and has a thickness of 0.5-3 nm or 1.5-2 nm.

10. The preparation method according to claim 8, characterized in that The mask layer is formed by laser processing in an oxygen atmosphere.

11. The method of claim 7, wherein, ​ 12. A solar cell, characterized by, The solar cell comprises a silicon substrate, the silicon substrate comprises a first surface and a second surface arranged oppositely, the second surface comprises a first region and a second region, the first region is provided with a tunneling layer, a first doped layer, a barrier layer and a second doped layer, the second region is provided with a tunneling layer and a first doped layer, and the solar cell further comprises an electrode located on the first region and in contact with the second doped layer.

13. The solar cell of claim 11, wherein, The first region is provided with a tunneling layer, a first doped layer, a barrier layer and a second doped layer, and the second region is provided with a tunneling layer and a first doped layer; or The first region is provided with a tunneling layer, a first doped layer, a barrier layer and a second doped layer, and the second region is provided with a tunneling layer, a first doped layer, a barrier layer and a second doped layer, and the thickness of the second doped layer on the second region is less than that on the first region; or The first region is provided with a tunneling layer, at least two first doped layers and at least two barrier layers which are alternately stacked, and a second doped layer, and the second region is provided with a tunneling layer, at least two first doped layers and at least one barrier layer which are alternately stacked; or The first region is provided with a tunneling layer, at least two first doped layers and at least two barrier layers which are alternately stacked, and a second doped layer, and the second region is provided with a tunneling layer, at least two first doped layers and at least two barrier layers which are alternately stacked, and a second doped layer, and the thickness of the second doped layer on the second region is less than that on the first region.

14. A solar cell, characterized by, The silicon substrate comprises a first surface and a second surface arranged oppositely, a first electrode provided on the first surface of the silicon substrate, and a second electrode provided on the second surface of the silicon substrate, the second surface of the silicon substrate comprises a metal region and a non-metal region, the second electrode is provided on the metal region, and the metal region has a first passivation contact structure which comprises a tunneling layer, at least one first doped polysilicon layer, at least one spacer layer and a second doped polysilicon layer which are sequentially stacked.

15. The solar cell of claim 14, wherein, From the perspective of the front projection plane, the projection width size of the metal region on the projection plane is not less than the projection width size of the second electrode in the projection direction opposite to the second electrode.

16. The solar cell of claim 15, wherein, The non-metal region has a second passivation contact structure, the second passivation contact structure comprises a tunneling layer and a first doped polysilicon layer which are sequentially stacked, or comprises a tunneling layer, a first doped polysilicon layer and a spacer layer which are sequentially stacked, and a second doped polysilicon layer, or comprises a tunneling layer and a second doped polysilicon layer which are sequentially stacked, or comprises a tunneling layer, at least two first doped polysilicon layers and at least one spacer layer which are alternately stacked, or comprises a tunneling layer, at least two first doped polysilicon layers and at least two spacer layers which are alternately stacked, and a second doped polysilicon layer.

17. The solar cell of claim 15, wherein, The first passivation contact structure and the second passivation contact structure have a height difference relative to the back surface of the silicon substrate.

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