Pixel module, driving method, and display device

Abstract

A pixel module, a driving method, and a display device. The pixel module comprises multiple rows and columns of sub-pixels, multiple rows of scanning lines, and multiple columns of data lines; two sub-pixels located in an n-th row are disposed among a (2n-1)-th row of scanning line, a 2n-th row of scanning line, an m-th column of data line, and an (m+1)-th column of data line, wherein n and m are positive integers; each sub-pixel receives a data voltage under the control of a scanning signal; among the sub-pixels electrically connected to the (2n-1)-th row of scanning line and the sub-pixels electrically connected to a (2n+1)-th row of scanning line, the sub-pixels electrically connected to the same column of data line have the same color; and among the sub-pixels electrically connected to the 2n-th row of scanning line and the sub-pixels electrically connected to a (2n+2)-th row of scanning line, the sub-pixels electrically connected to the same column of data line have the same color. When the pixel module is in a dual gate mode, color display errors would not occur when a monochromatic picture is displayed.

Description

Pixel module, driving method and display device

[0001] Cross Reference to Related Applications

[0002] This application claims priority to Chinese Patent Application No. 202410471912.0, filed on April 18, 2024, the contents of which are incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The present disclosure relates to the technical field of display, and in particular, to a pixel module, a driving method and a display device. BACKGROUND

[0004] The existing pixel module will appear display color error when displaying monochrome picture in DLG (Dual Gate) mode. SUMMARY

[0005] The main purpose of the present disclosure is to provide a pixel module, a driving method and a display device, which solve the problem that the existing pixel module will appear display color error when displaying monochrome picture in DLG (Dual Gate) mode.

[0006] In one aspect, the present disclosure provides a pixel module, comprising a plurality of rows and columns of sub-pixels, a plurality of rows of scan lines and a plurality of columns of data lines;

[0007] Two sub-pixels in the nth row are arranged between the (2n-1)th row of scan lines, the 2nth row of scan lines, the mth column of scan lines and the (m+1)th column of scan lines; n and m are positive integers;

[0008] The sub-pixels are respectively electrically connected to a row of scan lines and a column of data lines, and are used to receive a data voltage provided by the data line under the control of a scan signal provided by the scan line;

[0009] Among the sub-pixels electrically connected to the (2n-1)th row of scan lines and the sub-pixels electrically connected to the (2n+1)th row of scan lines, the sub-pixels electrically connected to the same column of data lines have the same color;

[0010] Among the sub-pixels electrically connected to the 2nth row of scan lines and the sub-pixels electrically connected to the (2n+2)th row of scan lines, the sub-pixels electrically connected to the same column of data lines have the same color.

[0011] Optionally, the 6th sub-pixel in the 4th row and the 5th column is electrically connected to the 8th row of scan lines and the 3rd column of data lines, respectively, and is used to receive a data voltage provided by the 3rd column of data lines under the control of a scan signal provided by the 8th row of scan lines;

[0012] The 6th column sub-pixel in the 4th row of the 3rd group is electrically connected with the 6th row scanning line of the 8th group and the 2nd column data line, for receiving the data voltage provided by the 2nd column data line under the control of the scanning signal provided by the 6th row scanning line of the 8th group;

[0013] The 3rd column sub-pixel in the 4th row of the 3rd group is electrically connected with the 6th row scanning line of the 8th group and the 1st column data line, for receiving the data voltage provided by the 1st column data line under the control of the scanning signal provided by the 6th row scanning line of the 8th group;

[0014] The 2nd column sub-pixel in the 4th row of the 3rd group is electrically connected with the 7th row scanning line of the 8th group and the 1st column data line, for receiving the data voltage provided by the 1st column data line under the control of the scanning signal provided by the 7th row scanning line of the 8th group;

[0015] The 1st column sub-pixel in the 4th row of the 3rd group is electrically connected with the 6th row scanning line of the 8th group and the 3rd column data line, for receiving the data voltage provided by the 3rd column data line under the control of the scanning signal provided by the 6th row scanning line of the 8th group;

[0016] The 3rd column sub-pixel in the 4th row of the 3rd group is electrically connected with the 7th row scanning line of the 8th group and the 3rd column data line, for receiving the data voltage provided by the 3rd column data line under the control of the scanning signal provided by the 7th row scanning line of the 8th group;

[0017] a and b are positive integers.

[0018] Optionally, the 5th column sub-pixel in the 4th row of the 2nd group is electrically connected with the 5th row scanning line of the 8th group and the 2nd column data line, for receiving the data voltage provided by the 2nd column data line under the control of the scanning signal provided by the 5th row scanning line of the 8th group;

[0019] The 4th column sub-pixel in the 4th row of the 2nd group is electrically connected with the 4th row scanning line of the 8th group and the 2nd column data line, for receiving the data voltage provided by the 2nd column data line under the control of the scanning signal provided by the 4th row scanning line of the 8th group;

[0020] The 3rd column sub-pixel in the 4th row of the 2nd group is electrically connected with the 4th row scanning line of the 8th group and the 1st column data line, for receiving the data voltage provided by the 1st column data line under the control of the scanning signal provided by the 4th row scanning line of the 8th group;

[0021] The 6th column sub-pixel in the 4th row of the 4th sub-pixel group is electrically connected with the 8th row scanning line and the 3rd column data line respectively, and is used for receiving the data voltage provided by the 3rd column data line under the control of the scanning signal provided by the 8th row scanning line.

[0022] The 6th column sub-pixel in the 4th row of the 4th sub-pixel group is electrically connected with the 8th row scanning line and the 3rd column data line respectively, and is used for receiving the data voltage provided by the 3rd column data line under the control of the scanning signal provided by the 8th row scanning line.

[0023] The 6th column sub-pixel in the 4th row of the 4th sub-pixel group is electrically connected with the 8th row scanning line and the 3rd column data line respectively, and is used for receiving the data voltage provided by the 3rd column data line under the control of the scanning signal provided by the 8th row scanning line.

[0024] The 6th column sub-pixel in the 4th row of the 4th sub-pixel group is electrically connected with the 8th row scanning line and the 3rd column data line respectively, and is used for receiving the data voltage provided by the 3rd column data line under the control of the scanning signal provided by the 8th row scanning line.

[0025] The 6th column sub-pixel in the 4th row of the 4th sub-pixel group is electrically connected with the 8th row scanning line and the 3rd column data line respectively, and is used for receiving the data voltage provided by the 3rd column data line under the control of the scanning signal provided by the 8th row scanning line.

[0026] The 6th column sub-pixel in the 4th row of the 4th sub-pixel group is electrically connected with the 8th row scanning line and the 3rd column data line respectively, and is used for receiving the data voltage provided by the 3rd column data line under the control of the scanning signal provided by the 8th row scanning line.

[0027] The 6th column sub-pixel in the 4th row of the 4th sub-pixel group is electrically connected with the 8th row scanning line and the 3rd column data line respectively, and is used for receiving the data voltage provided by the 3rd column data line under the control of the scanning signal provided by the 8th row scanning line.

[0028] The 6th column sub-pixel in the 4th row of the 4th sub-pixel group is electrically connected with the 8th row scanning line and the 3rd column data line respectively, and is used for receiving the data voltage provided by the 3rd column data line under the control of the scanning signal provided by the 8th row scanning line.

[0029] The 6th column sub-pixel in the 4th row of the 4th sub-pixel group is electrically connected with the 8th row scanning line and the 3rd column data line respectively, and is used for receiving the data voltage provided by the 3rd column data line under the control of the scanning signal provided by the 8th row scanning line.

[0030] Optionally, the sub-pixels in the 6thb-5thcolumn of the 4throw are electrically connected with the 8th-1strow of scan lines and the 3rd-1stcolumn of data lines respectively, for receiving data voltage provided by the 3rd-1stcolumn of data lines under the control of the scanning signal provided by the 8th-1strow of scan lines;

[0031] The sub-pixels in the 6thb-4thcolumn of the 4throw are electrically connected with the 8throw of scan lines and the 3rd-1stcolumn of data lines respectively, for receiving data voltage provided by the 3rd-1stcolumn of data lines under the control of the scanning signal provided by the 8throw of scan lines;

[0032] The sub-pixels in the 6thb-3rcolumn of the 4throw are electrically connected with the 8throw of scan lines and the 3rdcolumn of data lines respectively, for receiving data voltage provided by the 3rdcolumn of data lines under the control of the scanning signal provided by the 8throw of scan lines;

[0033] The sub-pixels in the 6thb-2ndcolumn of the 4throw are electrically connected with the 8th-1strow of scan lines and the 3rdcolumn of data lines respectively, for receiving data voltage provided by the 3rdcolumn of data lines under the control of the scanning signal provided by the 8th-1strow of scan lines;

[0034] The sub-pixels in the 6thb-1stcolumn of the 4throw are electrically connected with the 8throw of scan lines and the 3rd+1stcolumn of data lines respectively, for receiving data voltage provided by the 3rd+1stcolumn of data lines under the control of the scanning signal provided by the 8throw of scan lines;

[0035] The sub-pixels in the 6thbcolumn of the 4throw are electrically connected with the 8th-1strow of scan lines and the 3rd+1stcolumn of data lines respectively, for receiving data voltage provided by the 3rd+1stcolumn of data lines under the control of the scanning signal provided by the 8th-1strow of scan lines.

[0036] Optionally, the sub-pixels in the 6thb-5thcolumn of the 4th-3rrow are electrically connected with the 8th-7throw of scan lines and the 3rd-2ndcolumn of data lines respectively, for receiving data voltage provided by the 3rd-2ndcolumn of data lines under the control of the scanning signal provided by the 8th-7throw of scan lines;

[0037] The sub-pixels in the 6thb-4thcolumn of the 4th-3rrow are electrically connected with the 8th-6throw of scan lines and the 3rd-2ndcolumn of data lines respectively, for receiving data voltage provided by the 3rd-2ndcolumn of data lines under the control of the scanning signal provided by the 8th-6throw of scan lines;

[0038] The sub-pixels in the 6thb-3rcolumn of the 4th-3rrow are electrically connected with the 8th-7throw of scan lines and the 3rd-1stcolumn of data lines respectively, for receiving data voltage provided by the 3rd-1stcolumn of data lines under the control of the scanning signal provided by the 8th-7throw of scan lines;

[0039] The sub-pixels in the 6th b-1 column of the 4th a-3 row are respectively electrically connected with the 8th a-7 row scanning line and the 3rd b column data line, for receiving the data voltage provided by the 3rd b column data line under the control of the scanning signal provided by the 8th a-7 row scanning line;

[0040] The sub-pixels in the 6th b-1 column of the 4th a-3 row are respectively electrically connected with the 8th a-7 row scanning line and the 3rd b column data line, for receiving the data voltage provided by the 3rd b column data line under the control of the scanning signal provided by the 8th a-7 row scanning line;

[0041] The sub-pixels in the 6th b-1 column of the 4th a-3 row are respectively electrically connected with the 8th a-7 row scanning line and the 3rd b column data line, for receiving the data voltage provided by the 3rd b column data line under the control of the scanning signal provided by the 8th a-7 row scanning line;

[0042] a and b are positive integers.

[0043] Optionally, the sub-pixels in the 6th b-5 column of the 4th a-2 row are respectively electrically connected with the 8th a-5 row scanning line and the 3rd b-2 column data line, for receiving the data voltage provided by the 3rd b-2 column data line under the control of the scanning signal provided by the 8th a-5 row scanning line;

[0044] The sub-pixels in the 6th b-4 column of the 4th a-2 row are respectively electrically connected with the 8th a-4 row scanning line and the 3rd b-2 column data line, for receiving the data voltage provided by the 3rd b-2 column data line under the control of the scanning signal provided by the 8th a-4 row scanning line;

[0045] The sub-pixels in the 6th b-3 column of the 4th a-2 row are respectively electrically connected with the 8th a-5 row scanning line and the 3rd b-1 column data line, for receiving the data voltage provided by the 3rd b-1 column data line under the control of the scanning signal provided by the 8th a-5 row scanning line;

[0046] The sub-pixels in the 6th b-2 column of the 4th a-2 row are respectively electrically connected with the 8th a-4 row scanning line and the 3rd b-1 column data line, for receiving the data voltage provided by the 3rd b-1 column data line under the control of the scanning signal provided by the 8th a-4 row scanning line;

[0047] The sub-pixels in the 6th b-1 column of the 4th a-2 row are respectively electrically connected with the 8th a-5 row scanning line and the 3rd b column data line, for receiving the data voltage provided by the 3rd b column data line under the control of the scanning signal provided by the 8th a-5 row scanning line;

[0048] The 6th column sub-pixel in the 4a-1th row is electrically connected with the 8a-3th row scanning line and the 3b-1th column data line respectively, for receiving the data voltage provided by the 3b-1th column data line under the control of the scanning signal provided by the 8a-3th row scanning line.

[0049] Optionally, the 6th column sub-pixel in the 4a-1th row is electrically connected with the 8a-3th row scanning line and the 3b-1th column data line respectively, for receiving the data voltage provided by the 3b-1th column data line under the control of the scanning signal provided by the 8a-3th row scanning line.

[0050] The 6th column sub-pixel in the 4a-1th row is electrically connected with the 8a-3th row scanning line and the 3b-1th column data line respectively, for receiving the data voltage provided by the 3b-1th column data line under the control of the scanning signal provided by the 8a-3th row scanning line.

[0051] The 6th column sub-pixel in the 4a-1th row is electrically connected with the 8a-3th row scanning line and the 3b-1th column data line respectively, for receiving the data voltage provided by the 3b-1th column data line under the control of the scanning signal provided by the 8a-3th row scanning line.

[0052] The 6th column sub-pixel in the 4a-1th row is electrically connected with the 8a-3th row scanning line and the 3b-1th column data line respectively, for receiving the data voltage provided by the 3b-1th column data line under the control of the scanning signal provided by the 8a-3th row scanning line.

[0053] The 6th column sub-pixel in the 4a-1th row is electrically connected with the 8a-3th row scanning line and the 3b-1th column data line respectively, for receiving the data voltage provided by the 3b-1th column data line under the control of the scanning signal provided by the 8a-3th row scanning line.

[0054] The 6th column sub-pixel in the 4a-1th row is electrically connected with the 8a-3th row scanning line and the 3b-1th column data line respectively, for receiving the data voltage provided by the 3b-1th column data line under the control of the scanning signal provided by the 8a-3th row scanning line.

[0055] Optionally, the 6th column sub-pixel in the 4a-1th row is electrically connected with the 8a-3th row scanning line and the 3b-1th column data line respectively, for receiving the data voltage provided by the 3b-1th column data line under the control of the scanning signal provided by the 8a-3th row scanning line.

[0056] The 6th column sub-pixel in the 4a-1th row is electrically connected with the 8a-3th row scanning line and the 3b-1th column data line respectively, for receiving the data voltage provided by the 3b-1th column data line under the control of the scanning signal provided by the 8a-3th row scanning line.

[0057] The sub-pixels in the 6th column of the 4th row are respectively electrically connected with the 8th row of scan lines and the 3rd column of data lines, and are configured to receive data voltages provided by the corresponding data lines under the control of the scan signals provided by the 8th row of scan lines.

[0058] The sub-pixels in the 6th column of the 4th row are respectively electrically connected with the 8th row of scan lines and the 3rd column of data lines, and are configured to receive data voltages provided by the corresponding data lines under the control of the scan signals provided by the 8th row of scan lines.

[0059] The sub-pixels in the 6th column of the 4th row are respectively electrically connected with the 8th row of scan lines and the 3rd column of data lines, and are configured to receive data voltages provided by the corresponding data lines under the control of the scan signals provided by the 8th row of scan lines.

[0060] The sub-pixels in the 6th column of the 4th row are respectively electrically connected with the 8th row of scan lines and the 3rd column of data lines, and are configured to receive data voltages provided by the corresponding data lines under the control of the scan signals provided by the 8th row of scan lines.

[0061] Optionally, the sub-pixels in the 3rd-2 column have a first color, the sub-pixels in the 3rd-1 column have a second color, and the sub-pixels in the 3rd column have a second color.

[0062] In a second aspect, the embodiments of the present disclosure provide a driving method applied to the pixel module, and a driving cycle includes a plurality of driving stages arranged in sequence; the driving method includes:

[0063] In the 2c-1 stage, the 4c-3 row of scan lines and the 4c-1 row of scan lines are turned on to control the sub-pixels electrically connected with the 4c-3 row of scan lines and the sub-pixels electrically connected with the 4c-1 row of scan lines to receive data voltages on the corresponding data lines;

[0064] In the 2c stage, the 4c-2 row of scan lines and the 4c row of scan lines are turned on to control the sub-pixels electrically connected with the 4c-2 row of scan lines and the sub-pixels electrically connected with the 4c row of scan lines to receive data voltages on the corresponding data lines;

[0065] c is a positive integer.

[0066] Optionally, the 2c-1 stage is a 2c pre-charge stage; the 2c stage is a 2c+1 pre-charge stage; and the driving method further includes:

[0067] In the second 2c-1 stage, the fourth 4c-2 row scanning line and the fourth 4c row scanning line are turned on, and the sub-pixels electrically connected with the fourth 4c-2 row scanning line and the sub-pixels electrically connected with the fourth 4c row scanning line receive data voltages on corresponding data lines to pre-charge the sub-pixels electrically connected with the fourth 4c-2 row scanning line and the sub-pixels electrically connected with the fourth 4c row scanning line.

[0068] In the second 2c stage, the fourth 4c+1 row scanning line and the fourth 4c+3 row scanning line are turned on, and the sub-pixels electrically connected with the fourth 4c-2 row scanning line and the sub-pixels electrically connected with the fourth 4c+1 row scanning line receive data voltages on corresponding data lines to pre-charge the sub-pixels electrically connected with the fourth 4c+3 row scanning line and the sub-pixels electrically connected with the fourth 4c row scanning line.

[0069] In a third aspect, the display device is provided.

[0070] Optionally, the display device further comprises a driving module; the driving module comprises eight clock signal lines and a plurality of driving circuits.

[0071] The eighth 8d-7 driving circuit is electrically connected with the first clock signal line, the eighth 8d-6 driving circuit is electrically connected with the second clock signal line, the eighth 8d-5 driving circuit is electrically connected with the third clock signal line, the eighth 8d-4 driving circuit is electrically connected with the fourth clock signal line, the eighth 8d-3 driving circuit is electrically connected with the fifth clock signal line, the eighth 8d-2 driving circuit is electrically connected with the sixth clock signal line, the eighth 8d-1 driving circuit is electrically connected with the seventh clock signal line, and the eighth 8d driving circuit is electrically connected with the eighth clock signal line; d is a positive integer.

[0072] The driving signal output end of the eighth 8d-7 driving circuit is electrically connected with the input end of the eighth 8d-6 driving circuit, and the driving signal output end of the eighth 8d-6 driving circuit is electrically connected with the reset end of the eighth 8d-7 driving circuit; d is a positive integer.

[0073] Optionally, the display device further comprises a driving module; the driving module comprises twelve clock signal lines and a plurality of driving circuits.

[0074] The 12d-11th level driving circuit is electrically connected with the first clock signal line, the 12d-10th level driving circuit is electrically connected with the second clock signal line, the 12d-9th level driving circuit is electrically connected with the third clock signal line, the 12d-8th level driving circuit is electrically connected with the fourth clock signal line, the 12d-7th level driving circuit is electrically connected with the fifth clock signal line, the 12d-6th level driving circuit is electrically connected with the sixth clock signal line, the 12d-5th level driving circuit is electrically connected with the seventh clock signal line, the 12d-4th level driving circuit is electrically connected with the eighth clock signal line, the 12d-3th level driving circuit is electrically connected with the ninth clock signal line, the 12d-2th level driving circuit is electrically connected with the tenth clock signal line, the 12d-1th level driving circuit is electrically connected with the eleventh clock signal line, and the 12d level driving circuit is electrically connected with the twelfth clock signal line; d is a positive integer.

[0075] The driving signal output end of the e level driving circuit is electrically connected with the input end of the e+4 level driving circuit, and the driving signal output end of the e+4 level driving circuit is electrically connected with the reset end of the e level driving circuit; e is a positive integer.

[0076] Optionally, the display device also includes a driving module; the driving module includes sixteen clock signal lines and multiple levels of driving circuits.

[0077] The 16d-15th level driving circuit is electrically connected with the first clock signal line, the 16d-14th level driving circuit is electrically connected with the second clock signal line, the 16d-13th level driving circuit is electrically connected with the third clock signal line, the 16d-12th level driving circuit is electrically connected with the fourth clock signal line, the 16d-11th level driving circuit is electrically connected with the fifth clock signal line, the 16d-19th level driving circuit is electrically connected with the sixth clock signal line, the 16d-9th level driving circuit is electrically connected with the seventh clock signal line, the 16d-8th level driving circuit is electrically connected with the eighth clock signal line, the 16d-7th level driving circuit is electrically connected with the ninth clock signal line, the 16d-6th level driving circuit is electrically connected with the tenth clock signal line, the 16d-5th level driving circuit is electrically connected with the eleventh clock signal line, the 16d-4th level driving circuit is electrically connected with the twelfth clock signal line, the 16d-3th level driving circuit is electrically connected with the thirteenth clock signal line, the 16d-2th level driving circuit is electrically connected with the fourteenth clock signal line, the 16d-1th level driving circuit is electrically connected with the fifteenth clock signal line, and the 16d level driving circuit is electrically connected with the sixteenth clock signal line; d is a positive integer.

[0078] The driving signal output end of the e level driving circuit is electrically connected with the input end of the e+8 level driving circuit, and the driving signal output end of the e+8 level driving circuit is electrically connected with the reset end of the e level driving circuit; e is a positive integer.

[0079] In the pixel module provided in the embodiments of the present disclosure, in the sub-pixels electrically connected to the 2n-1th row scanning line and the sub-pixels electrically connected to the 2n+1th row scanning line, the sub-pixels electrically connected to the same column data line have the same color, so that when the 2n-1th row scanning line and the 2n+1th row scanning line are opened at the same time, the column data line provides the corresponding data voltage to the sub-pixels with the same color, so that when the pixel module is in the DLG (Dual Gate, double gate) mode, the display color error does not occur when a monochrome picture is displayed. BRIEF DESCRIPTION OF DRAWINGS

[0080] FIG. 1A and FIG. 1B are structural diagrams of a pixel module according to at least one embodiment of the present disclosure;

[0081] FIG. 2 is a working timing diagram of at least one embodiment of the pixel module shown in FIG. 1A;

[0082] FIG. 3 is a schematic diagram of at least one embodiment of the pixel module shown in FIG. 1A when displaying a red picture;

[0083] FIG. 4 is a schematic diagram of at least one embodiment of the pixel module shown in FIG. 1A when displaying a green picture;

[0084] FIG. 5 is a schematic diagram of at least one embodiment of the pixel module shown in FIG. 1A when displaying a blue picture;

[0085] FIG. 6 is a polarity display schematic diagram of at least one embodiment of the pixel module shown in FIG. 1A;

[0086] FIG. 7A and FIG. 7B are structural diagrams of a pixel module according to at least one embodiment of the present disclosure;

[0087] FIG. 8 is a working timing diagram of at least one embodiment of the pixel module shown in FIG. 7A;

[0088] FIG. 9 is a structural diagram of at least one embodiment of a driving module in a display device according to the present disclosure;

[0089] FIG. 10 is a structural diagram of at least one embodiment of a driving module in a display device according to the present disclosure;

[0090] FIG. 11 is a structural diagram of at least one embodiment of a driving module in a display device according to the present disclosure. DETAILED DESCRIPTION

[0091] The technical solutions in the embodiments of the present disclosure will be described clearly and completely in combination with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present disclosure.

[0092] The transistor used in all embodiments of the present disclosure can be a thin film transistor or a field effect transistor or other devices with the same characteristics. In the embodiments of the present disclosure, in order to distinguish the two poles of the transistor other than the gate, one pole is called the first pole and the other pole is called the second pole.

[0093] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first pole can be a drain and the second pole can be a source, or the first pole can be a source and the second pole can be a drain.

[0094] The pixel module described in the embodiments of the present disclosure includes a plurality of rows and columns of sub-pixels, a plurality of rows of scan lines and a plurality of columns of data lines.

[0095] Two sub-pixels located in the nth row are arranged between the (2n-1)th row of scan lines, the 2nth row of scan lines, the mth column of scan lines and the (m+1)th column of scan lines; n and m are positive integers;

[0096] The sub-pixels are respectively electrically connected to a row of scan lines and a column of data lines, for receiving a data voltage provided by the data line under the control of a scan signal provided by the scan line;

[0097] Among the sub-pixels electrically connected to the (2n-1)th row of scan lines and the sub-pixels electrically connected to the (2n+1)th row of scan lines, the sub-pixels electrically connected to the same column of data lines have the same color;

[0098] Among the sub-pixels electrically connected to the 2nth row of scan lines and the sub-pixels electrically connected to the (2n+2)th row of scan lines, the sub-pixels electrically connected to the same column of data lines have the same color.

[0099] In the pixel module described in the embodiments of the present disclosure, among the sub-pixels electrically connected to the (2n-1)th row of scan lines and the sub-pixels electrically connected to the (2n+1)th row of scan lines, the sub-pixels electrically connected to the same column of data lines have the same color, so that when the (2n-1)th row of scan lines and the (2n+1)th row of scan lines are opened at the same time, the same column of data lines provides a corresponding data voltage to the sub-pixels with the same color, so that when the pixel module is in the DLG (Dual Gate) mode, when a monochrome image is displayed, no display color error occurs.

[0100] According to a specific embodiment, the 4a-3th row and 6b-5th column sub-pixel is respectively electrically connected to the 8a-7th row of scan lines and the 3b-2th column of data lines, for receiving a data voltage provided by the 3b-2th column of data lines under the control of a scan signal provided by the 8a-7th row of scan lines;

[0101] The 6th column sub-pixel in the 4th row of the 3rd group is electrically connected with the 6th row scanning line of the 8th group and the 1st column data line of the 3rd group, for receiving the data voltage provided by the 1st column data line of the 3rd group under the control of the scanning signal provided by the 6th row scanning line of the 8th group;

[0102] The 3rd column sub-pixel in the 4th row of the 3rd group is electrically connected with the 6th row scanning line of the 8th group and the 1st column data line of the 3rd group, for receiving the data voltage provided by the 1st column data line of the 3rd group under the control of the scanning signal provided by the 6th row scanning line of the 8th group;

[0103] The 2nd column sub-pixel in the 4th row of the 3rd group is electrically connected with the 7th row scanning line of the 8th group and the 1st column data line of the 3rd group, for receiving the data voltage provided by the 1st column data line of the 3rd group under the control of the scanning signal provided by the 7th row scanning line of the 8th group;

[0104] The 1st column sub-pixel in the 4th row of the 3rd group is electrically connected with the 6th row scanning line of the 8th group and the column data line of the 3rd group, for receiving the data voltage provided by the column data line of the 3rd group under the control of the scanning signal provided by the 6th row scanning line of the 8th group;

[0105] The column sub-pixel in the 4th row of the 3rd group is electrically connected with the 7th row scanning line of the 8th group and the column data line of the 3rd group, for receiving the data voltage provided by the column data line of the 3rd group under the control of the scanning signal provided by the 7th row scanning line of the 8th group;

[0106] a and b are positive integers.

[0107] In at least one embodiment of the present disclosure, the 5th column sub-pixel in the 4th row of the 3rd group is electrically connected with the 5th row scanning line of the 8th group and the 2nd column data line of the 3rd group, for receiving the data voltage provided by the 2nd column data line of the 3rd group under the control of the scanning signal provided by the 5th row scanning line of the 8th group;

[0108] The 4th column sub-pixel in the 4th row of the 3rd group is electrically connected with the 4th row scanning line of the 8th group and the 2nd column data line of the 3rd group, for receiving the data voltage provided by the 2nd column data line of the 3rd group under the control of the scanning signal provided by the 4th row scanning line of the 8th group;

[0109] The 3rd column sub-pixel in the 4th row of the 3rd group is electrically connected with the 4th row scanning line of the 8th group and the 1st column data line of the 3rd group, for receiving the data voltage provided by the 1st column data line of the 3rd group under the control of the scanning signal provided by the 4th row scanning line of the 8th group;

[0110] The 6th b-2 column sub-pixel of the 4th a-2 row is electrically connected with the 8th a-5 row scanning line and the 3rd b-1 data line respectively, for receiving the data voltage provided by the 3rd b-1 column data line under the control of the scanning signal provided by the 8th a-5 row scanning line;

[0111] The 6th b-1 column sub-pixel of the 4th a-2 row is electrically connected with the 8th a-4 row scanning line and the 3rd b column data line respectively, for receiving the data voltage provided by the 3rd b column data line under the control of the scanning signal provided by the 8th a-4 row scanning line;

[0112] The 6th b column sub-pixel of the 4th a-2 row is electrically connected with the 8th a-5 row scanning line and the 3rd b column data line respectively, for receiving the data voltage provided by the 3rd b column data line under the control of the scanning signal provided by the 8th a-5 row scanning line.

[0113] In at least one embodiment of the present disclosure, the 6th b-5 column sub-pixel of the 4th a-1 row is electrically connected with the 8th a-3 row scanning line and the 3rd b-1 column data line respectively, for receiving the data voltage provided by the 3rd b-1 column data line under the control of the scanning signal provided by the 8th a-3 row scanning line;

[0114] The 6th b-4 column sub-pixel of the 4th a-1 row is electrically connected with the 8th a-2 row scanning line and the 3rd b-1 column data line respectively, for receiving the data voltage provided by the 3rd b-1 column data line under the control of the scanning signal provided by the 8th a-2 row scanning line;

[0115] The 6th b-3 column sub-pixel of the 4th a-1 row is electrically connected with the 8th a-2 row scanning line and the 3rd b column data line respectively, for receiving the data voltage provided by the 3rd b column data line under the control of the scanning signal provided by the 8th a-2 row scanning line;

[0116] The 6th b-2 column sub-pixel of the 4th a-1 row is electrically connected with the 8th a-3 row scanning line and the 3rd b column data line respectively, for receiving the data voltage provided by the 3rd b column data line under the control of the scanning signal provided by the 8th a-3 row scanning line;

[0117] The 6th b-1 column sub-pixel of the 4th a-1 row is electrically connected with the 8th a-2 row scanning line and the 3rd b+1 column data line respectively, for receiving the data voltage provided by the 3rd b+1 column data line under the control of the scanning signal provided by the 8th a-2 row scanning line;

[0118] The 6th b column sub-pixel of the 4th a-1 row is electrically connected with the 8th a-3 row scanning line and the 3rd b+1 column data line respectively, for receiving the data voltage provided by the 3rd b+1 column data line under the control of the scanning signal provided by the 8th a-3 row scanning line.

[0119] In at least one embodiment of the present disclosure, the sub-pixel in the 4th row and the 6th column is electrically connected with the 8th row of scan lines and the 3rd column of data lines respectively, for receiving the data voltage provided by the 3rd column of data lines under the control of the scanning signal provided by the 8th row of scan lines;

[0120] The sub-pixel in the 4th row and the 6th column is electrically connected with the 8th row of scan lines and the 3rd column of data lines respectively, for receiving the data voltage provided by the 3rd column of data lines under the control of the scanning signal provided by the 8th row of scan lines;

[0121] The sub-pixel in the 4th row and the 6th column is electrically connected with the 8th row of scan lines and the 3rd column of data lines respectively, for receiving the data voltage provided by the 3rd column of data lines under the control of the scanning signal provided by the 8th row of scan lines;

[0122] The sub-pixel in the 4th row and the 6th column is electrically connected with the 8th row of scan lines and the 3rd column of data lines respectively, for receiving the data voltage provided by the 3rd column of data lines under the control of the scanning signal provided by the 8th row of scan lines;

[0123] The sub-pixel in the 4th row and the 6th column is electrically connected with the 8th row of scan lines and the 3rd column of data lines respectively, for receiving the data voltage provided by the 3rd column of data lines under the control of the scanning signal provided by the 8th row of scan lines;

[0124] The sub-pixel in the 4th row and the 6th column is electrically connected with the 8th row of scan lines and the 3rd column of data lines respectively, for receiving the data voltage provided by the 3rd column of data lines under the control of the scanning signal provided by the 8th row of scan lines.

[0125] FIG. 1A shows that the pixel module includes four rows and twelve columns of sub-pixels according to at least one embodiment of the present disclosure;

[0126] As shown in FIG. 1A, the sub-pixel in the first row and the first column is electrically connected with the first row of scan lines G1 and the first column of data lines DL1 respectively, for receiving the data voltage provided by the first column of data lines DL1 under the control of the scanning signal provided by the first row of scan lines G1;

[0127] The sub-pixel in the first row and the second column is electrically connected with the second row of scan lines G2 and the first column of data lines DL1 respectively, for receiving the data voltage provided by the first column of data lines DL1 under the control of the scanning signal provided by the second row of scan lines G2;

[0128] The first row third column sub-pixel P13 is electrically connected with the second row scanning line G2 and the second column data line DL2 respectively, for receiving the data voltage provided by the second column data line DL2 under the control of the scanning signal provided by the second row scanning line G2;

[0129] The first row fourth column sub-pixel P14 is electrically connected with the first row scanning line G1 and the second column data line DL2 respectively, for receiving the data voltage provided by the second column data line DL2 under the control of the scanning signal provided by the first row scanning line G1;

[0130] The first row fifth column sub-pixel P15 is electrically connected with the second row scanning line G2 and the third column data line DL3 respectively, for receiving the data voltage provided by the third column data line DL3 under the control of the scanning signal provided by the second row scanning line G2;

[0131] The first row sixth column sub-pixel is electrically connected with the first row scanning line G1 and the third column data line DL3 respectively, for receiving the data voltage provided by the third column data line DL3 under the control of the scanning signal provided by the first row scanning line G1;

[0132] The first row seventh column sub-pixel P17 is electrically connected with the first row scanning line G1 and the fourth column data line DL4 respectively, for receiving the data voltage provided by the fourth column data line DL4 under the control of the scanning signal provided by the first row scanning line G1;

[0133] The first row eighth column sub-pixel P18 is electrically connected with the second row scanning line G2 and the fourth column data line DL4 respectively, for receiving the data voltage provided by the fourth column data line DL4 under the control of the scanning signal provided by the second row scanning line G2;

[0134] The first row ninth column sub-pixel P19 is electrically connected with the second row scanning line G2 and the fifth column data line DL5 respectively, for receiving the data voltage provided by the fifth column data line DL5 under the control of the scanning signal provided by the second row scanning line G2;

[0135] The first row tenth column sub-pixel P110 is electrically connected with the first row scanning line G1 and the fifth column data line DL5 respectively, for receiving the data voltage provided by the fifth column data line DL5 under the control of the scanning signal provided by the first row scanning line G1;

[0136] The first row eleventh column sub-pixel P111 is electrically connected with the second row scanning line G2 and the sixth column data line DL6 respectively, for receiving the data voltage provided by the sixth column data line DL6 under the control of the scanning signal provided by the second row scanning line G2;

[0137] The first row twelfth column sub-pixel is electrically connected with the first row scanning line G1 and the sixth column data line DL6 respectively, for receiving the data voltage provided by the sixth column data line DL6 under the control of the scanning signal provided by the first row scanning line G1;

[0138] The second row first column sub-pixel P21 is electrically connected with the third row scanning line G3 and the first column data line DL1 respectively, for receiving the data voltage provided by the first column data line DL1 under the control of the scanning signal provided by the third row scanning line G3;

[0139] The second row second column sub-pixel P22 is electrically connected with the fourth row scanning line G4 and the first column data line DL1 respectively, for receiving the data voltage provided by the first column data line DL1 under the control of the scanning signal provided by the fourth row scanning line G4;

[0140] The second row fourth column sub-pixel P23 is electrically connected with the fourth row scanning line G4 and the second column data line DL2 respectively, for receiving the data voltage provided by the second column data line DL2 under the control of the scanning signal provided by the fourth row scanning line G4;

[0141] The second row fourth column sub-pixel P24 is electrically connected with the third row scanning line G3 and the second column data line DL2 respectively, for receiving the data voltage provided by the second column data line DL2 under the control of the scanning signal provided by the third row scanning line G3;

[0142] The second row fifth column sub-pixel P25 is electrically connected with the fourth row scanning line G4 and the third column data line DL3 respectively, for receiving the data voltage provided by the third column data line DL3 under the control of the scanning signal provided by the fourth row scanning line G4;

[0143] The second row sixth column sub-pixel P26 is electrically connected with the third row scanning line G3 and the third column data line DL3 respectively, for receiving the data voltage provided by the third column data line DL3 under the control of the scanning signal provided by the third row scanning line G3;

[0144] The second row seventh column sub-pixel P27 is electrically connected with the third row scanning line G3 and the fourth column data line DL4 respectively, for receiving the data voltage provided by the fourth column data line DL4 under the control of the scanning signal provided by the third row scanning line G3;

[0145] The second row eighth column sub-pixel P28 is electrically connected with the fourth row scanning line G4 and the fourth column data line DL4 respectively, for receiving the data voltage provided by the fourth column data line DL4 under the control of the scanning signal provided by the fourth row scanning line G4;

[0146] The sub-pixel P29 in the second row and the ninth column is electrically connected with the fourth row scan line G4 and the fifth column data line DL5 respectively, and is used for receiving a data voltage provided by the fifth column data line DL5 under control of a scanning signal provided by the fourth row scan line G4.

[0147] The sub-pixel P210 in the second row and the tenth column is electrically connected with the third row scan line G3 and the fifth column data line DL5 respectively, and is used for receiving a data voltage provided by the fifth column data line DL5 under control of a scanning signal provided by the third row scan line G3.

[0148] The sub-pixel P211 in the second row and the eleventh column is electrically connected with the fourth row scan line G4 and the sixth column data line DL6 respectively, and is used for receiving a data voltage provided by the sixth column data line DL6 under control of a scanning signal provided by the fourth row scan line G4.

[0149] The sub-pixel P212 in the second row and the twelfth column is electrically connected with the third row scan line G3 and the sixth column data line DL6 respectively, and is used for receiving a data voltage provided by the sixth column data line DL6 under control of a scanning signal provided by the third row scan line G3.

[0150] The sub-pixel P31 in the third row and the first column is electrically connected with the fifth row scan line G5 and the second column data line DL2 respectively, and is used for receiving a data voltage provided by the second column data line DL2 under control of a scanning signal provided by the fifth row scan line G5.

[0151] The sub-pixel P32 in the third row and the second column is electrically connected with the sixth row scan line G6 and the second column data line DL2 respectively, and is used for receiving a data voltage provided by the second column data line DL2 under control of a scanning signal provided by the sixth row scan line G6.

[0152] The sub-pixel P33 in the third row and the third column is electrically connected with the sixth row scan line G6 and the third column data line DL3 respectively, and is used for receiving a data voltage provided by the third column data line DL3 under control of a scanning signal provided by the sixth row scan line G6.

[0153] The sub-pixel P34 in the third row and the fourth column is electrically connected with the fifth row scan line G5 and the third column data line DL3 respectively, and is used for receiving a data voltage provided by the third column data line DL3 under control of a scanning signal provided by the fifth row scan line G5.

[0154] The sub-pixel P35 in the third row and the fifth column is electrically connected with the sixth row scan line G6 and the fourth column data line DL4 respectively, and is used for receiving a data voltage provided by the fourth column data line DL4 under control of a scanning signal provided by the sixth row scan line G6.

[0155] The third row and the sixth column sub-pixels are respectively electrically connected with the fifth row scanning line G5 and the fourth column data line DL4, for receiving the data voltage provided by the fourth column data line DL4 under the control of the scanning signal provided by the fifth row scanning line G5;

[0156] The third row and the seventh column sub-pixel P37 are respectively electrically connected with the fifth row scanning line G5 and the fifth column data line DL5, for receiving the data voltage provided by the fifth column data line DL5 under the control of the scanning signal provided by the fifth row scanning line G5;

[0157] The third row and the eighth column sub-pixel P38 are respectively electrically connected with the sixth row scanning line G6 and the fifth column data line DL5, for receiving the data voltage provided by the fifth column data line DL5 under the control of the scanning signal provided by the sixth row scanning line G6;

[0158] The third row and the ninth column sub-pixel P39 are respectively electrically connected with the sixth row scanning line G6 and the sixth column data line DL6, for receiving the data voltage provided by the sixth column data line DL6 under the control of the scanning signal provided by the sixth row scanning line G6;

[0159] The third row and the tenth column sub-pixel P310 are respectively electrically connected with the fifth row scanning line G5 and the sixth column data line DL6, for receiving the data voltage provided by the sixth column data line DL6 under the control of the scanning signal provided by the fifth row scanning line G5;

[0160] The third row and the eleventh column sub-pixel P311 are respectively electrically connected with the sixth row scanning line G6 and the seventh column data line DL7, for receiving the data voltage provided by the seventh column data line DL7 under the control of the scanning signal provided by the sixth row scanning line G6;

[0161] The third row and the twelfth column sub-pixel are respectively electrically connected with the fifth row scanning line G5 and the seventh column data line DL7, for receiving the data voltage provided by the seventh column data line DL7 under the control of the scanning signal provided by the fifth row scanning line G5;

[0162] The fourth row and the first column sub-pixel P41 are respectively electrically connected with the seventh row scanning line G7 and the second column data line DL2, for receiving the data voltage provided by the second column data line DL2 under the control of the scanning signal provided by the seventh row scanning line G7;

[0163] The fourth row and the second column sub-pixel P42 are respectively electrically connected with the eighth row scanning line G8 and the second column data line DL2, for receiving the data voltage provided by the second column data line DL2 under the control of the scanning signal provided by the eighth row scanning line G8;

[0164] The fourth row and the third column sub-pixel P43 are electrically connected with the eighth row scan line G8 and the third column data line DL3 respectively, for receiving the data voltage provided by the third column data line DL3 under the control of the scanning signal provided by the eighth row scan line G8;

[0165] The fourth row and the fourth column sub-pixel P44 are electrically connected with the seventh row scan line G7 and the third column data line DL3 respectively, for receiving the data voltage provided by the third column data line DL3 under the control of the scanning signal provided by the seventh row scan line G7;

[0166] The fourth row and the fifth column sub-pixel P45 are electrically connected with the eighth row scan line G8 and the fourth column data line DL4 respectively, for receiving the data voltage provided by the fourth column data line DL4 under the control of the scanning signal provided by the eighth row scan line G8;

[0167] The fourth row and the sixth column sub-pixel P46 are electrically connected with the seventh row scan line G7 and the fourth column data line DL4 respectively, for receiving the data voltage provided by the fourth column data line DL4 under the control of the scanning signal provided by the seventh row scan line G7;

[0168] The fourth row and the seventh column sub-pixel P47 are electrically connected with the seventh row scan line G7 and the fifth column data line DL3 respectively, for receiving the data voltage provided by the fifth column data line DL5 under the control of the scanning signal provided by the seventh row scan line G7;

[0169] The fourth row and the eighth column sub-pixel P48 are electrically connected with the eighth row scan line G8 and the fifth column data line DL5 respectively, for receiving the data voltage provided by the fifth column data line DL5 under the control of the scanning signal provided by the eighth row scan line G8;

[0170] The fourth row and the ninth column sub-pixel P49 are electrically connected with the eighth row scan line G8 and the sixth column data line DL6 respectively, for receiving the data voltage provided by the sixth column data line DL6 under the control of the scanning signal provided by the eighth row scan line G8;

[0171] The fourth row and the tenth column sub-pixel P410 are electrically connected with the seventh row scan line G7 and the sixth column data line DL6 respectively, for receiving the data voltage provided by the third column data line DL3 under the control of the scanning signal provided by the seventh row scan line G7;

[0172] The fourth row and the eleventh column sub-pixel P411 are electrically connected with the eighth row scan line G8 and the seventh column data line DL7 respectively, for receiving the data voltage provided by the seventh column data line DL11 under the control of the scanning signal provided by the eighth row scan line G8;

[0173] The fourth row twelfth column sub-pixel P412 is electrically connected with the seventh row scan line G7 and the seventh column data line DL7 respectively, for receiving a data voltage provided by the seventh column data line DL7 under the control of a scanning signal provided by the seventh row scan line G7.

[0174] In at least one embodiment shown in FIG. 1A, P11, P21, P31 and P41 are all red sub-pixels, P12, P22, P32 and P42 are all green sub-pixels, P13, P23, P33 and P43 are all blue sub-pixels; P14, P24, P34 and P44 are all red sub-pixels, P15, P25, P35 and P45 are all green sub-pixels, P16, P26, P36 and P46 are all blue sub-pixels; P17, P27, P37 and P47 are all red sub-pixels, P18, P28, P38 and P48 are all green sub-pixels, P19, P29, P39 and P49 are all blue sub-pixels; P110, P210, P310 and P410 are all red sub-pixels, P111, P211, P311 and P411 are all green sub-pixels, P112, P212, P312 and P412 are all blue sub-pixels.

[0175] In at least one embodiment shown in FIG. 1A, P11 and P12 are arranged between G1, G2, DL1 and DL2, P13 and P14 are arranged between G1, G2, DL2 and DL3, P15 and P16 are arranged between G1, G2, DL3 and DL4, P17 and P18 are arranged between G1, G2, DL4 and DL5, P19 and P110 are arranged between G1, G2, DL5 and DL6, P111 and P112 are arranged between G1, G2, DL6 and DL7;

[0176] P21 and P22 are arranged between G3, G4, DL1 and DL2, P23 and P24 are arranged between G3, G4, DL2 and DL3, P25 and P26 are arranged between G3, G4, DL3 and DL4, P27 and P28 are arranged between G3, G4, DL4 and DL5, P29 and P210 are arranged between G3, G4, DL5 and DL6, P211 and P212 are arranged between G3, G4, DL6 and DL7;

[0177] P31 and P32 are arranged between G5, G6, DL1 and DL2, P33 and P34 are arranged between G5, G6, DL2 and DL3, P35 and P36 are arranged between G5, G6, DL3 and DL4, P37 and P38 are arranged between G5, G6, DL4 and DL5, P39 and P310 are arranged between G5, G6, DL5 and DL6, P311 and P312 are arranged between G5, G6, DL6 and DL7;

[0178] P41 and P42 are disposed between G7, G8, DL1 and DL2, P43 and P44 are disposed between G7, G8, DL2 and DL3, P45 and P46 are disposed between G7, G8, DL3 and DL4, P47 and P48 are disposed between G7, G8, DL4 and DL5, P49 and P410 are disposed between G7, G8, DL5 and DL6, P411 and P412 are disposed between G7, G8, DL6 and DL7.

[0179] As shown in FIG. IB, on the basis of at least one embodiment of the pixel module shown in FIG. 1A, the first row first column sub-pixel includes the first row first column pixel electrode PJ11 and the first row first column thin film transistor T11; the first row second column sub-pixel includes the first row second column pixel electrode PJ12 and the first row second column thin film transistor T12; the first row third column sub-pixel includes the first row third column pixel electrode PJ13 and the first row third column thin film transistor T13; the first row fourth column sub-pixel includes the first row fourth column pixel electrode PJ14 and the first row fourth column thin film transistor T14; the first row fifth column sub-pixel includes the first row fifth column pixel electrode PJ15 and the first row fifth column thin film transistor T15; the first row sixth column sub-pixel includes the first row sixth column pixel electrode PJ16 and the first row sixth column thin film transistor T16; the first row seventh column sub-pixel includes the first row seventh column pixel electrode PJ17 and the first row seventh column thin film transistor T17; the first row eighth column sub-pixel includes the first row eighth column pixel electrode PJ18 and the first row eighth column thin film transistor T18; the first row ninth column sub-pixel includes the first row ninth column pixel electrode PJ19 and the first row ninth column thin film transistor T19; the first row tenth column sub-pixel includes the first row tenth column pixel electrode PJ110 and the first row tenth column thin film transistor T110; the first row eleventh column sub-pixel includes the first row eleventh column pixel electrode PJ111 and the first row eleventh column thin film transistor T111; the first row twelfth column sub-pixel includes the first row twelfth column pixel electrode PJ112 and the first row twelfth column thin film transistor T112;

[0180] The second row first column sub-pixel comprises a second row first column pixel electrode PJ21 and a second row first column thin film transistor T21; the second row second column sub-pixel comprises a second row second column pixel electrode PJ22 and a second row second column thin film transistor T22; the second row third column sub-pixel comprises a second row third column pixel electrode PJ23 and a second row third column thin film transistor T23; the second row fourth column sub-pixel comprises a second row fourth column pixel electrode PJ24 and a second row fourth column thin film transistor T24; the second row fifth column sub-pixel comprises a second row fifth column pixel electrode PJ25 and a second row fifth column thin film transistor T25; the second row sixth column sub-pixel comprises a second row sixth column pixel electrode PJ26 and a second row sixth column thin film transistor T26; the second row seventh column sub-pixel comprises a second row seventh column pixel electrode PJ27 and a second row seventh column thin film transistor T27; the second row eighth column sub-pixel comprises a second row eighth column pixel electrode PJ28 and a second row eighth column thin film transistor T28; the second row ninth column sub-pixel comprises a second row ninth column pixel electrode PJ29 and a second row ninth column thin film transistor T29; the second row tenth column sub-pixel comprises a second row tenth column pixel electrode PJ210 and a second row tenth column thin film transistor T210; the second row eleventh column sub-pixel comprises a second row eleventh column pixel electrode PJ211 and a second row eleventh column thin film transistor T211; the second row twelfth column sub-pixel comprises a second row twelfth column pixel electrode PJ212 and a second row twelfth column thin film transistor T212;

[0181] The third row first column sub-pixel comprises a third row first column pixel electrode PJ31 and a third row first column thin film transistor T31; the third row second column sub-pixel comprises a third row second column pixel electrode PJ32 and a third row second column thin film transistor T32; the third row third column sub-pixel comprises a third row third column pixel electrode PJ33 and a third row third column thin film transistor T33; the third row fourth column sub-pixel comprises a third row fourth column pixel electrode PJ34 and a third row fourth column thin film transistor T34; the third row fifth column sub-pixel comprises a third row fifth column pixel electrode PJ35 and a third row fifth column thin film transistor T35; the third row sixth column sub-pixel comprises a third row sixth column pixel electrode PJ36 and a third row sixth column thin film transistor T36; the third row seventh column sub-pixel comprises a third row seventh column pixel electrode PJ37 and a third row seventh column thin film transistor T37; the third row eighth column sub-pixel comprises a third row eighth column pixel electrode PJ38 and a third row eighth column thin film transistor T38; the third row ninth column sub-pixel comprises a third row ninth column pixel electrode PJ39 and a third row ninth column thin film transistor T39; the third row tenth column sub-pixel comprises a third row tenth column pixel electrode PJ310 and a third row tenth column thin film transistor T310; the third row eleventh column sub-pixel comprises a third row eleventh column pixel electrode PJ311 and a third row eleventh column thin film transistor T311; the third row twelfth column sub-pixel comprises a third row twelfth column pixel electrode PJ312 and a third row twelfth column thin film transistor T312;

[0182] The fourth row first column sub-pixel includes a fourth row first column pixel electrode PJ41 and a fourth row first column thin film transistor T41; the fourth row second column sub-pixel includes a fourth row second column pixel electrode PJ42 and a fourth row second column thin film transistor T42; the fourth row third column sub-pixel includes a fourth row third column pixel electrode PJ43 and a fourth row third column thin film transistor T43; the fourth row fourth column sub-pixel includes a fourth row fourth column pixel electrode PJ44 and a fourth row fourth column thin film transistor T44; the fourth row fifth column sub-pixel includes a fourth row fifth column pixel electrode PJ45 and a fourth row fifth column thin film transistor T45; the fourth row sixth column sub-pixel includes a fourth row sixth column pixel electrode PJ46 and a fourth row sixth column thin film transistor T46; the fourth row seventh column sub-pixel includes a fourth row seventh column pixel electrode PJ47 and a fourth row seventh column thin film transistor T47; the fourth row eighth column sub-pixel includes a fourth row eighth column pixel electrode PJ48 and a fourth row eighth column thin film transistor T48; the fourth row ninth column sub-pixel includes a fourth row ninth column pixel electrode PJ49 and a fourth row ninth column thin film transistor T49; the fourth row tenth column sub-pixel includes a fourth row tenth column pixel electrode PJ410 and a fourth row tenth column thin film transistor T410; the fourth row eleventh column sub-pixel includes a fourth row eleventh column pixel electrode PJ411 and a fourth row eleventh column thin film transistor T411; and the fourth row twelfth column sub-pixel includes a fourth row twelfth column pixel electrode PJ412 and a fourth row twelfth column thin film transistor T412.

[0183] In at least one embodiment of the present disclosure, in a sub-pixel, the gate of the thin film transistor is electrically connected with the corresponding row gate line, the first electrode of the thin film transistor is electrically connected with the corresponding pixel electrode, and the second electrode of the thin film transistor is electrically connected with the corresponding column data line.

[0184] As shown in FIG. 2, at least one embodiment of the pixel module shown in FIG. 1A of the present disclosure in operation, the display period can include a first stage S1, a second stage S2, a third stage S3 and a fourth stage S4 arranged in sequence;

[0185] In the first stage S1, G1 and G3 both provide a high voltage signal, P11 accesses the data voltage on DL1, P14 accesses the data voltage on DL2, P16 accesses the data voltage on DL3, P17 accesses the data voltage on DL4, P110 accesses the data voltage on DL5, and P112 accesses the data voltage on DL6;

[0186] P21 accesses the data voltage on DL1, P24 accesses the data voltage on DL2, P26 accesses the data voltage on DL3, P27 accesses the data voltage on DL4, P210 accesses the data voltage on DL5, and P212 accesses the data voltage on DL6;

[0187] P11 and P21 are both red sub-pixels, P14 and P24 are both red sub-pixels, P16 and P26 are both blue sub-pixels, P17 and P27 are both red sub-pixels, P110 and P210 are both red sub-pixels, P112 and P212 are both blue sub-pixels, so that when displaying a monochrome picture, there is no color confusion;

[0188] In the first stage S1, G2 and G4 provide high voltage signals, P12 and P22 are pre-charged by the data voltage on DL1, P13 and P23 are pre-charged by the data voltage on DL2, P15 and P25 are pre-charged by the data voltage on DL3, P18 and P28 are pre-charged by the data voltage on DL4, P19 and P29 are pre-charged by the data voltage on DL5, and P111 and P211 are pre-charged by the data voltage on DL6, so that when the polarity is reversed between adjacent frames, P12, P22, P13, P23, P15, P25, P18, P28, P19, P29, P111 and P211 can be pre-charged with the data voltage of the corresponding polarity, so that in the second stage S2, P12, P22, P13, P23, P15, P25, P18, P28, P19, P29, P111 and P211 can be quickly charged with the data voltage of the polarity;

[0189] In the second stage S2, G2 and G4 provide high voltage signals, P12 is connected to the data voltage on DL1, P13 receives the data voltage on DL2, P15 is connected to the data voltage on DL3, P18 is connected to the data voltage on DL4, P19 is connected to the data voltage on DL5, and P111 is connected to the data voltage on DL6; P22 is connected to the data voltage on DL1, P23 is connected to the data voltage on DL2, P25 is connected to the data voltage on DL3, P28 is connected to the data voltage on DL4, P29 is connected to the data voltage on DL5, and P2111 is connected to the data voltage on DL3;

[0190] In the second stage S2, G5 and G7 provide high voltage signals, P31 and P41 are pre-charged by the data voltage on DL2, P34 and P44 are pre-charged by the data voltage on DL3, P36 and P46 are pre-charged by the data voltage on DL4, P37 and P47 are pre-charged by the data voltage on DL5, P310 and P410 are pre-charged by the data voltage on DL6, P312 and P412 are pre-charged by the data voltage on DL7, so that when the polarity is reversed between adjacent frames, P31, P41, P34, P44, P36, P46, P37, P47, P310, P410, P312 and P412 can be pre-charged with the data voltage of the corresponding polarity, so that in the second stage S2, P31, P41, P34, P44, P36, P46, P37, P47, P310, P410, P312 and P412 can be quickly charged with the data voltage of the polarity;

[0191] In the third stage S3, G5 and G7 provide high voltage signals, P31 and P41 receive the data voltage on DL2, P34 and P44 access the data voltage on DL3, P36 and P45 access the data voltage on DL4, P37 and P47 access the data voltage on DL5, P310 and P410 access the data voltage on DL6, P312 and P412 access the data voltage on DL7;

[0192] In the third stage S3, G6 and G8 provide high voltage signals, P32 and P42 are pre-charged by the data voltage on DL2, P33 and P43 are pre-charged by the data voltage on DL3, P35 and P45 are pre-charged by the data voltage on DL4, P38 and P48 are pre-charged by the data voltage on DL5, P39 and P49 are pre-charged by the data voltage on DL6, P311 and P411 are pre-charged by the data voltage on DL7, so that when the polarity is reversed between adjacent frames, P32, P42, P33, P43, P35, P45, P38, P48, P39, P49, P311 and P411 can be pre-charged with the data voltage of the corresponding polarity, so that in the second stage S2, P32, P42, P33, P43, P35, P45, P38, P48, P39, P49, P311 and P411 can be quickly charged with the data voltage of the polarity;

[0193] In the fourth stage S4, G6 and G8 provide high voltage signals, P32 and P42 access data voltage on DL2, P33 and P43 access data voltage on DL3, P35 and P45 access data voltage on DL4, P38 and P48 access data voltage on DL5, P39 and P49 access data voltage on DL6, P311 and P411 access data voltage on DL7.

[0194] As shown in Fig. 3, when at least one embodiment of the pixel module shown in Fig. 1A is in the DLG mode, displaying a red picture,

[0195] First, G1 and G3 provide high voltage signals, DL1 provides a first red data voltage, DL2 provides a second red data voltage, DL4 provides a third red data voltage, DL5 provides a fourth red data voltage, P11 and P21 access the first red data voltage, P14 and P24 access the second red data voltage, P17 and P27 access the third red data voltage, P110 and P210 access the fourth red data voltage, P11, P31, P14, P34, P17, P27, P110 and P210 are all red sub-pixels, and the display color is without disorder;

[0196] Then, G2 and G4 provide high voltage signals, and each data line does not provide data voltage.

[0197] Then, G5 and G7 provide high voltage signals, DL2 provides a fifth red data voltage, DL3 provides a sixth data voltage, DL5 provides a seventh red data voltage, DL6 provides an eighth red data voltage, P31 and P41 access the fifth red data voltage, P34 and P44 access the second red data voltage, P37 and P47 access the third red data voltage, P310 and P410 access the fourth red data voltage, P31, P41, P34, P44, P37, P47, P310 and P410 are all red sub-pixels, and the display color is without disorder.

[0198] Then, G6 and G8 provide high voltage signals, and each data line does not provide data voltage.

[0199] As shown in Fig. 4, when at least one embodiment of the pixel module shown in Fig. 1A is in the DLG mode, displaying a green picture,

[0200] First, G1 and G3 provide high voltage signals, and each data line does not provide data voltage.

[0201] After that, G2 and G4 provide high voltage signals, DL1 provides a first green data voltage, DL3 provides a second green data voltage, DL4 provides a third green data voltage, DL6 provides a fourth green data voltage, P12 and P22 are connected to the first green data voltage, P15 and P25 are connected to the second green data voltage, P18 and P28 are connected to the third green data voltage, P111 and P211 are connected to the fourth green data voltage, P12, P22, P15, P25, P18, P28, P111 and P211 are all green sub-pixels, and the display color is not disordered;

[0202] After that, G5 and G7 provide high voltage signals, and each data line does not provide a data voltage;

[0203] After that, G6 and G8 provide high voltage signals, DL2 provides a fifth green data voltage, DL4 provides a sixth green data voltage, DL5 provides a seventh green data voltage, DL7 provides an eighth green data voltage, P32 and P42 are connected to the fifth green data voltage, P35 and P45 are connected to the sixth green data voltage, P38 and P48 are connected to the seventh green data voltage, P311 and P411 are connected to the eighth green data voltage, P32, P42, P35, P45, P38, P48, P311 and P411 are all green sub-pixels, and the display color is not disordered.

[0204] As shown in FIG. 5, when at least one embodiment of the pixel module shown in FIG. 1A is in the DLG mode, a blue picture is displayed,

[0205] First, G1 and G3 provide high voltage signals, DL3 provides a first blue data voltage, DL6 provides a second blue data voltage, P16 and P26 are connected to the first blue data voltage, and P112 and P212 are connected to the second blue data voltage;

[0206] After that, G2 and G4 provide high voltage signals, DL2 provides a third blue data voltage, DL5 provides a fourth blue data voltage, P13 and P23 are connected to the third blue data voltage, and P19 and P29 are connected to the fourth blue data voltage;

[0207] After that, G5 and G7 provide high voltage signals, DL4 provides a fifth blue data voltage, DL6 provides a sixth blue data voltage, P36 and P46 are connected to the fifth blue data voltage, and P312 and P412 are connected to the sixth blue data voltage;

[0208] After that, G6 and G8 provide high voltage signals, DL3 provides a seventh blue data voltage, DL6 provides an eighth blue data voltage, P33 and P43 are connected to the seventh blue data voltage, and P39 and P49 are connected to the eighth blue data voltage;

[0209] P16, P26, P112, P121, P13, P23, P19, P29, P36, P46, P312, P412, P33, P43, P39 and P49 are blue sub-pixels, and there is no problem in displaying color.

[0210] At least one embodiment of the pixel module shown in FIG. 1A in the normal display mode, that is, each row of scan lines outputs a high voltage signal in turn, when displaying a red picture,

[0211] First, G1 provides a high voltage signal, DL1 provides a first red data voltage, DL2 provides a second red data voltage, DL4 provides a third red data voltage, DL5 provides a fourth red data voltage, P11 is connected to the first red data voltage, P14 is connected to the second red data voltage, P17 is connected to the third red data voltage, and P110 is connected to the fourth red data voltage;

[0212] Then, G2 provides a high voltage signal, and each data line does not provide a data voltage;

[0213] Then, G3 provides a high voltage signal, DL1 provides a fifth red data voltage, DL2 provides a sixth red data voltage, DL4 provides a seventh red data voltage, DL5 provides an eighth red data voltage, P21 is connected to the fifth red data voltage, P24 is connected to the sixth red data voltage, P27 is connected to the seventh red data voltage, and P210 is connected to the eighth red data voltage;

[0214] Then, G4 provides a high voltage signal, and each data line does not provide a data voltage;

[0215] Then, G5 provides a high voltage signal, DL2 provides a ninth red data voltage, DL3 provides a tenth red data voltage, DL5 provides an eleventh red data voltage, DL6 provides a twelfth red data voltage, P31 is connected to the ninth red data voltage, P34 is connected to the tenth red data voltage, P37 is connected to the eleventh red data voltage, and P310 is connected to the twelfth red data voltage;

[0216] Then, G6 provides a high voltage signal, and each data line does not provide a data voltage;

[0217] Then, G7 provides a high voltage signal, DL2 provides a thirteenth red data voltage, DL3 provides a fourteenth red data voltage, DL5 provides a fifteenth red data voltage, DL6 provides a sixteenth red data voltage, P41 is connected to the thirteenth red data voltage, P44 is connected to the fourteenth red data voltage, P47 is connected to the fifteenth red data voltage, and P410 is connected to the sixteenth red data voltage;

[0218] P11, P14, P17, P110, P21, P24, P27, P210, P31, P34, P37, P310, P41, P44, P47 and P410 are all red data voltages, and the display color is correct.

[0219] At least one embodiment of the pixel module shown in FIG. 1A of the present disclosure is in a normal display mode, when displaying a monochrome picture, all sub-pixels are not pre-charged, the charging state is consistent, the brightness is consistent, and the picture quality is very good.

[0220] At least one embodiment of the pixel module described in FIG. 1A of the present disclosure is in a normal display mode, when displaying a mixed color picture, the display correctness is comparable to the related pixel module.

[0221] The pixel module described in at least one embodiment of the present disclosure can realize DLG display, can realize frequency multiplication of the refresh rate of the display panel, and improves the performance and competitiveness of the display panel.

[0222] In at least one embodiment of the pixel module shown in FIG. 1A, the connection mode of the first row of sub-pixels and the connection mode of the second row of sub-pixels are the same, the connection mode of the third row of sub-pixels and the connection mode of the fourth row of sub-pixels are the same, and the connection mode of the first row of sub-pixels and the connection mode of the third row of sub-pixels are opposite.

[0223] In the pixel module described in at least one embodiment of the present disclosure, each sub-pixel can include a pixel electrode and a thin film transistor electrically connected to each other;

[0224] The gate of the thin film transistor is electrically connected to the corresponding row gate line, the first pole of the thin film transistor is electrically connected to the corresponding pixel electrode, and the second pole of the thin film transistor is electrically connected to the corresponding column data line.

[0225] As shown in FIG. 6, at least one embodiment of the pixel module shown in FIG. 1A of the present disclosure is in operation, in the DLG display mode, when DL1 provides a positive polarity data voltage, DL2 provides a negative polarity data voltage, DL3 provides a positive polarity data voltage, DL4 provides a negative polarity data voltage, DL5 provides a positive polarity data voltage, DL6 provides a negative polarity data voltage, and DL7 provides a positive polarity data voltage,

[0226] First, G1 and G3 provide a high voltage signal, P11 and P21 are connected to a positive polarity data voltage, P14 and P24 are connected to a negative polarity data voltage, P16 and P26 are connected to a positive polarity data voltage, P17 and P27 are connected to a negative polarity data voltage, P110 and P210 are connected to a positive polarity data voltage, and P112 and P212 are connected to a negative polarity data voltage.

[0227] After that, G2 and G4 provide high voltage signals, P12 and P22 access positive polarity data voltage, P13 and P23 access negative polarity data voltage, P15 and P25 access positive polarity data voltage, P18 and P28 access negative polarity data voltage, P19 and P29 access positive polarity data voltage, P111 and P211 access negative polarity data voltage;

[0228] After that, G5 and G7 provide high voltage signals, P31 and P41 access negative polarity data voltage, P34 and P44 access positive polarity data voltage, P36 and P46 both access negative polarity data voltage, P37 and P47 both access positive polarity data voltage, P310 and P410 access negative polarity data voltage, P312 and P412 access positive polarity data voltage;

[0229] After that, G6 and G8 provide high voltage signals, P32 and P42 access negative polarity data voltage, P33 and P43 access positive polarity data voltage, P35 and P45 access negative polarity data voltage, P38 and P48 access positive polarity data voltage, P39 and P49 both access negative polarity data voltage, P311 and P411 both access positive polarity data voltage.

[0230] As shown in FIG. 6, the polarities of four adjacent sub-pixels are the same, and the polarities of the four adjacent sub-pixels are opposite to the polarities of their periphery adjacent sub-pixels.

[0231] According to another specific embodiment, the 4a-3rd row 6b-5th column sub-pixel is electrically connected with the 8a-7th row scan line and the 3b-2nd column data line respectively, for receiving the data voltage provided by the 3b-2nd column data line under the control of the scanning signal provided by the 8a-7th row scan line;

[0232] The 4a-3rd row 6b-4th column sub-pixel is electrically connected with the 8a-6th row scan line and the 3b-2nd column data line respectively, for receiving the data voltage provided by the 3b-2nd column data line under the control of the scanning signal provided by the 8a-6th row scan line;

[0233] The 4a-3rd row 6b-3rd column sub-pixel is electrically connected with the 8a-7th row scan line and the 3b-1st column data line respectively, for receiving the data voltage provided by the 3b-1st column data line under the control of the scanning signal provided by the 8a-7th row scan line;

[0234] The 4a-3rd row 6b-2nd column sub-pixel is electrically connected with the 8a-6th row scan line and the 3b-1st column data line respectively, for receiving the data voltage provided by the 3b-1st column data line under the control of the scanning signal provided by the 8a-6th row scan line;

[0235] The 6th column sub-pixels in the 4th row are electrically connected with the 8th row scan lines and the 3rd column data lines respectively, for receiving data voltages provided by the 3rd column data lines under the control of the scanning signals provided by the 8th row scan lines;

[0236] The 6th column sub-pixels in the 4th row are electrically connected with the 8th row scan lines and the 3rd column data lines respectively, for receiving data voltages provided by the 3rd column data lines under the control of the scanning signals provided by the 8th row scan lines;

[0237] a and b are positive integers.

[0238] In at least one embodiment of the present disclosure, the 6th-5th column sub-pixels in the 4th-2nd row are electrically connected with the 8th-5th row scan lines and the 3rd-2nd column data lines respectively, for receiving data voltages provided by the 3rd-2nd column data lines under the control of the scanning signals provided by the 8th-5th row scan lines;

[0239] The 6th-4th column sub-pixels in the 4th-2nd row are electrically connected with the 8th-4th row scan lines and the 3rd-2nd column data lines respectively, for receiving data voltages provided by the 3rd-2nd column data lines under the control of the scanning signals provided by the 8th-4th row scan lines;

[0240] The 6th-3rd column sub-pixels in the 4th-2nd row are electrically connected with the 8th-5th row scan lines and the 3rd-1st column data lines respectively, for receiving data voltages provided by the 3rd-1st column data lines under the control of the scanning signals provided by the 8th-5th row scan lines;

[0241] The 6th-2nd column sub-pixels in the 4th-2nd row are electrically connected with the 8th-4th row scan lines and the 3rd-1st column data lines respectively, for receiving data voltages provided by the 3rd-1st column data lines under the control of the scanning signals provided by the 8th-4th row scan lines;

[0242] The 6th-1st column sub-pixels in the 4th-2nd row are electrically connected with the 8th-5th row scan lines and the 3rd column data lines respectively, for receiving data voltages provided by the 3rd column data lines under the control of the scanning signals provided by the 8th-5th row scan lines;

[0243] The 6th column sub-pixels in the 4th row are electrically connected with the 8th row scan lines and the 3rd column data lines respectively, for receiving data voltages provided by the 3rd column data lines under the control of the scanning signals provided by the 8th row scan lines.

[0244] In at least one embodiment of the present disclosure, the sub-pixel of the 4th row and the 6th column is electrically connected with the scanning line of the 8th row and the data line of the 3rd column respectively, for receiving the data voltage provided by the data line of the 3rd column under the control of the scanning signal provided by the scanning line of the 8th row;

[0245] The sub-pixel of the 4th row and the 6th column is electrically connected with the scanning line of the 8th row and the data line of the 3rd column respectively, for receiving the data voltage provided by the data line of the 3rd column under the control of the scanning signal provided by the scanning line of the 8th row;

[0246] The sub-pixel of the 4th row and the 6th column is electrically connected with the scanning line of the 8th row and the data line of the 3rd column respectively, for receiving the data voltage provided by the data line of the 3rd column under the control of the scanning signal provided by the scanning line of the 8th row;

[0247] The sub-pixel of the 4th row and the 6th column is electrically connected with the scanning line of the 8th row and the data line of the 3rd column respectively, for receiving the data voltage provided by the data line of the 3rd column under the control of the scanning signal provided by the scanning line of the 8th row;

[0248] The sub-pixel of the 4th row and the 6th column is electrically connected with the scanning line of the 8th row and the data line of the 3rd column respectively, for receiving the data voltage provided by the data line of the 3rd column under the control of the scanning signal provided by the scanning line of the 8th row;

[0249] The sub-pixel of the 4th row and the 6th column is electrically connected with the scanning line of the 8th row and the data line of the 3rd column respectively, for receiving the data voltage provided by the data line of the 3rd column under the control of the scanning signal provided by the scanning line of the 8th row.

[0250] In at least one embodiment of the present disclosure, the sub-pixel of the 4th row and the 6th column is electrically connected with the scanning line of the 8th row and the data line of the 3rd column respectively, for receiving the data voltage provided by the data line of the 3rd column under the control of the scanning signal provided by the scanning line of the 8th row;

[0251] The sub-pixel of the 4th row and the 6th column is electrically connected with the scanning line of the 8th row and the data line of the 3rd column respectively, for receiving the data voltage provided by the data line of the 3rd column under the control of the scanning signal provided by the scanning line of the 8th row;

[0252] The sub-pixel of the 4th row and the 6th column is electrically connected with the scanning line of the 8th row and the data line of the 3rd column respectively, for receiving the data voltage provided by the data line of the 3rd column under the control of the scanning signal provided by the scanning line of the 8th row;

[0253] The sub-pixels in the 4th row and the 6th-2 column are respectively electrically connected with the 8th row scanning line and the 3rd column data line, for receiving the data voltage provided by the 3rd column data line under the control of the scanning signal provided by the 8th row scanning line;

[0254] The sub-pixels in the 4th row and the 6th-1 column are respectively electrically connected with the 8th-1 row scanning line and the 3rd+1 column data line, for receiving the data voltage provided by the 3rd+1 column data line under the control of the scanning signal provided by the 8th-1 row scanning line;

[0255] The sub-pixels in the 4th row and the 6th column are respectively electrically connected with the 8th row scanning line and the 3rd+1 column data line, for receiving the data voltage provided by the 3rd+1 column data line under the control of the scanning signal provided by the 8th row scanning line.

[0256] Optionally, the sub-pixels in the 3rd-2 column have a first color, the sub-pixels in the 3rd-1 column have a second color, and the sub-pixels in the 3rd column have the second color.

[0257] As shown in FIG. 7A, the sub-pixels in the first row and the first column are respectively electrically connected with the first row scanning line G1 and the first column data line DL1, for receiving the data voltage provided by the first column data line DL1 under the control of the scanning signal provided by the first row scanning line G1;

[0258] The sub-pixels in the first row and the second column are respectively electrically connected with the second row scanning line G2 and the first column data line DL1, for receiving the data voltage provided by the first column data line DL1 under the control of the scanning signal provided by the second row scanning line G2;

[0259] The sub-pixels in the first row and the third column are respectively electrically connected with the first row scanning line G1 and the second column data line DL2, for receiving the data voltage provided by the second column data line DL2 under the control of the scanning signal provided by the first row scanning line G1;

[0260] The sub-pixels in the first row and the fourth column are respectively electrically connected with the second row scanning line G2 and the second column data line DL2, for receiving the data voltage provided by the second column data line DL2 under the control of the scanning signal provided by the second row scanning line G2;

[0261] The sub-pixels in the first row and the fifth column are respectively electrically connected with the first row scanning line G1 and the third column data line DL3, for receiving the data voltage provided by the third column data line DL3 under the control of the scanning signal provided by the first row scanning line G1;

[0262] The first row and the sixth column sub-pixel P16 are electrically connected with the second row scanning line G2 and the third column data line DL3 respectively, for receiving the data voltage provided by the third column data line DL3 under the control of the scanning signal provided by the second row scanning line G2;

[0263] The first row and the seventh column sub-pixel P17 are electrically connected with the first row scanning line G1 and the fourth column data line DL4 respectively, for receiving the data voltage provided by the fourth column data line DL4 under the control of the scanning signal provided by the first row scanning line G1;

[0264] The first row and the eighth column sub-pixel P18 are electrically connected with the second row scanning line G2 and the fourth column data line DL4 respectively, for receiving the data voltage provided by the fourth column data line DL4 under the control of the scanning signal provided by the second row scanning line G2;

[0265] The first row and the ninth column sub-pixel P19 are electrically connected with the first row scanning line G1 and the fifth column data line DL5 respectively, for receiving the data voltage provided by the fifth column data line DL5 under the control of the scanning signal provided by the first row scanning line G1;

[0266] The first row and the tenth column sub-pixel P110 are electrically connected with the second row scanning line G2 and the fifth column data line DL5 respectively, for receiving the data voltage provided by the fifth column data line DL5 under the control of the scanning signal provided by the second row scanning line G2;

[0267] The first row and the eleventh column sub-pixel P111 are electrically connected with the first row scanning line G1 and the sixth column data line DL6 respectively, for receiving the data voltage provided by the sixth column data line DL6 under the control of the scanning signal provided by the first row scanning line G1;

[0268] The first row and the twelfth column sub-pixel P112 are electrically connected with the second row scanning line G2 and the sixth column data line DL6 respectively, for receiving the data voltage provided by the sixth column data line DL6 under the control of the scanning signal provided by the second row scanning line G2;

[0269] The second row and the first column sub-pixel P21 are electrically connected with the third row scanning line G3 and the first column data line DL1 respectively, for receiving the data voltage provided by the first column data line DL1 under the control of the scanning signal provided by the third row scanning line;

[0270] The second row and the second column sub-pixel P22 are electrically connected with the fourth row scanning line G4 and the first column data line DL1 respectively, for receiving the data voltage provided by the first column data line DL1 under the control of the scanning signal provided by the fourth row scanning line G4;

[0271] The second row and the third column sub-pixel P23 are electrically connected with the third row scan line G3 and the second column data line DL2 respectively, for receiving the data voltage provided by the second column data line DL2 under the control of the scanning signal provided by the third row scan line G3;

[0272] The second row and the fourth column sub-pixel P24 are electrically connected with the fourth row scan line G4 and the second column data line DL2 respectively, for receiving the data voltage provided by the second column data line DL2 under the control of the scanning signal provided by the fourth row scan line G4;

[0273] The second row and the fifth column sub-pixel P25 are electrically connected with the third row scan line G3 and the third column data line DL3 respectively, for receiving the data voltage provided by the third column data line DL3 under the control of the scanning signal provided by the third row scan line G3;

[0274] The second row and the sixth column sub-pixel P26 are electrically connected with the fourth row scan line G4 and the third column data line DL3 respectively, for receiving the data voltage provided by the third column data line DL3 under the control of the scanning signal provided by the fourth row scan line G4;

[0275] The second row and the seventh column sub-pixel P27 are electrically connected with the third row scan line G3 and the fourth column data line DL4 respectively, for receiving the data voltage provided by the fourth column data line DL4 under the control of the scanning signal provided by the third row scan line G3;

[0276] The second row and the eighth column sub-pixel P28 are electrically connected with the fourth row scan line G4 and the fourth column data line DL4 respectively, for receiving the data voltage provided by the fourth column data line DL4 under the control of the scanning signal provided by the fourth row scan line G4;

[0277] The second row and the ninth column sub-pixel P29 are electrically connected with the third row scan line G3 and the fifth column data line DL5 respectively, for receiving the data voltage provided by the fifth column data line DL5 under the control of the scanning signal provided by the third row scan line G3;

[0278] The second row and the tenth column sub-pixel P210 are electrically connected with the fourth row scan line G4 and the fifth column data line DL5 respectively, for receiving the data voltage provided by the fifth column data line DL5 under the control of the scanning signal provided by the fourth row scan line G4;

[0279] The second row and the eleventh column sub-pixel P211 are electrically connected with the third row scan line G3 and the sixth column data line DL6 respectively, for receiving the data voltage provided by the sixth column data line DL6 under the control of the scanning signal provided by the third row scan line G3;

[0280] The second row twelfth column sub-pixel P212 is electrically connected with the fourth row scan line G4 and the sixth column data line DL6 respectively, for receiving the data voltage provided by the sixth column data line DL6 under the control of the scanning signal provided by the fourth row scan line G4;

[0281] The third row first column sub-pixel P31 is electrically connected with the fifth row scan line G5 and the second column data line DL2 respectively, for receiving the data voltage provided by the second column data line DL2 under the control of the scanning signal provided by the fifth row scan line G5;

[0282] The third row second column sub-pixel P32 is electrically connected with the sixth row scan line G6 and the second column data line DL2 respectively, for receiving the data voltage provided by the second column data line DL2 under the control of the scanning signal provided by the sixth row scan line G6;

[0283] The third row third column sub-pixel P33 is electrically connected with the fifth row scan line G5 and the third column data line DL3 respectively, for receiving the data voltage provided by the third column data line DL3 under the control of the scanning signal provided by the fifth row scan line G5;

[0284] The third row fourth column sub-pixel P34 is electrically connected with the sixth row scan line G6 and the third column data line DL3 respectively, for receiving the data voltage provided by the third column data line DL3 under the control of the scanning signal provided by the sixth row scan line G6;

[0285] The third row fifth column sub-pixel P35 is electrically connected with the fifth row scan line G5 and the fourth column data line DL4 respectively, for receiving the data voltage provided by the fourth column data line DL4 under the control of the scanning signal provided by the fifth row scan line G5;

[0286] The third row sixth column sub-pixel P36 is electrically connected with the sixth row scan line G6 and the fourth column data line DL4 respectively, for receiving the data voltage provided by the fourth column data line DL4 under the control of the scanning signal provided by the sixth row scan line G6;

[0287] The third row seventh column sub-pixel P37 is electrically connected with the fifth row scan line G5 and the fifth column data line DL5 respectively, for receiving the data voltage provided by the fifth column data line DL5 under the control of the scanning signal provided by the fifth row scan line G5;

[0288] The third row eighth column sub-pixel P38 is electrically connected with the sixth row scan line G6 and the fifth column data line DL5 respectively, for receiving the data voltage provided by the fifth column data line DL5 under the control of the scanning signal provided by the sixth row scan line G6;

[0289] The third row and the ninth column sub-pixel P39 are electrically connected with the fifth row scan line G5 and the sixth column data line DL6 respectively, for receiving the data voltage provided by the sixth column data line DL6 under the control of the scanning signal provided by the fifth row scan line G5;

[0290] The third row and the tenth column sub-pixel P310 are electrically connected with the sixth row scan line G6 and the sixth column data line DL3 respectively, for receiving the data voltage provided by the sixth column data line DL6 under the control of the scanning signal provided by the sixth row scan line G6;

[0291] The third row and the eleventh column sub-pixel P311 are electrically connected with the fifth row scan line G5 and the seventh column data line DL7 respectively, for receiving the data voltage provided by the seventh column data line DL7 under the control of the scanning signal provided by the fifth row scan line G5;

[0292] The third row and the twelfth column sub-pixel P312 are electrically connected with the sixth row scan line G6 and the seventh column data line DL7 respectively, for receiving the data voltage provided by the seventh column data line DL7 under the control of the scanning signal provided by the sixth row scan line G6;

[0293] The fourth row and the first column sub-pixel P41 are electrically connected with the seventh row scan line G7 and the second column data line DL2 respectively, for receiving the data voltage provided by the second column data line DL2 under the control of the scanning signal provided by the seventh row scan line G7;

[0294] The fourth row and the second column sub-pixel P42 are electrically connected with the eighth row scan line G8 and the second column data line DL2 respectively, for receiving the data voltage provided by the second column data line DL2 under the control of the scanning signal provided by the eighth row scan line G8;

[0295] The fourth row and the third column sub-pixel P43 are electrically connected with the seventh row scan line G7 and the third column data line DL3 respectively, for receiving the data voltage provided by the third column data line DL3 under the control of the scanning signal provided by the seventh row scan line G7;

[0296] The fourth row and the fourth column sub-pixel P44 are electrically connected with the eighth row scan line G8 and the third column data line DL3 respectively, for receiving the data voltage provided by the third column data line DL4 under the control of the scanning signal provided by the eighth row scan line G8;

[0297] The fourth row and the fifth column sub-pixel P45 are electrically connected with the seventh row scan line G7 and the fourth column data line DL4 respectively, for receiving the data voltage provided by the fourth column data line DL4 under the control of the scanning signal provided by the seventh row scan line G7;

[0298] The fourth row and the sixth column sub-pixel P46 is electrically connected with the eighth row scan line G8 and the fourth column data line DL4 respectively, for receiving the data voltage provided by the fourth column data line DL4 under the control of the scanning signal provided by the eighth row scan line G8;

[0299] The fourth row and the seventh column sub-pixel P47 is electrically connected with the seventh row scan line G7 and the fifth column data line DL5 respectively, for receiving the data voltage provided by the fifth column data line DL5 under the control of the scanning signal provided by the seventh row scan line G7;

[0300] The fourth row and the eighth column sub-pixel P48 is electrically connected with the eighth row scan line G8 and the fifth column data line DL5 respectively, for receiving the data voltage provided by the fifth column data line DL5 under the control of the scanning signal provided by the eighth row scan line G8;

[0301] The fourth row and the ninth column sub-pixel P49 is electrically connected with the seventh row scan line G7 and the sixth column data line DL6 respectively, for receiving the data voltage provided by the sixth column data line DL6 under the control of the scanning signal provided by the seventh row scan line G7;

[0302] The fourth row and the tenth column sub-pixel P410 is electrically connected with the eighth row scan line G8 and the sixth column data line DL6 respectively, for receiving the data voltage provided by the sixth column data line DL6 under the control of the scanning signal provided by the eighth row scan line G8;

[0303] The fourth row and the eleventh column sub-pixel P411 is electrically connected with the seventh row scan line G7 and the seventh column data line DL7 respectively, for receiving the data voltage provided by the seventh column data line DL7 under the control of the scanning signal provided by the seventh row scan line G7;

[0304] The fourth row and the twelfth column sub-pixel P412 is electrically connected with the eighth row scan line G8 and the seventh column data line DL7 respectively, for receiving the data voltage provided by the seventh column data line DL7 under the control of the scanning signal provided by the eighth row scan line G8.

[0305] In at least one embodiment of the pixel module shown in FIG. 7A, the first column sub-pixel is a red sub-pixel, the second column sub-pixel is a green sub-pixel, and the third column sub-pixel is a blue sub-pixel; the fourth column sub-pixel is a red sub-pixel, the fifth column sub-pixel is a green sub-pixel, and the sixth column sub-pixel is a blue sub-pixel; the seventh column sub-pixel is a red sub-pixel, the eighth column sub-pixel is a green sub-pixel, and the ninth column sub-pixel is a blue sub-pixel; the tenth column sub-pixel is a red sub-pixel, the eleventh column sub-pixel is a green sub-pixel, and the twelfth column sub-pixel is a blue sub-pixel.

[0306] As shown in FIG. 7B, on the basis of at least one embodiment of the pixel module shown in FIG. 7A, the first row first column sub-pixel includes the first row first column pixel electrode PJ11 and the first row first column thin film transistor T11; the first row second column sub-pixel includes the first row second column pixel electrode PJ12 and the first row second column thin film transistor T12; the first row third column sub-pixel includes the first row third column pixel electrode PJ13 and the first row third column thin film transistor T13; the first row fourth column sub-pixel includes the first row fourth column pixel electrode PJ14 and the first row fourth column thin film transistor T14; the first row fifth column sub-pixel includes the first row fifth column pixel electrode PJ15 and the first row fifth column thin film transistor T15; the first row sixth column sub-pixel includes the first row sixth column pixel electrode PJ16 and the first row sixth column thin film transistor T16; the first row seventh column sub-pixel includes the first row seventh column pixel electrode PJ17 and the first row seventh column thin film transistor T17; the first row eighth column sub-pixel includes the first row eighth column pixel electrode PJ18 and the first row eighth column thin film transistor T18; the first row ninth column sub-pixel includes the first row ninth column pixel electrode PJ19 and the first row ninth column thin film transistor T19; the first row tenth column sub-pixel includes the first row tenth column pixel electrode PJ110 and the first row tenth column thin film transistor T110; the first row eleventh column sub-pixel includes the first row eleventh column pixel electrode PJ111 and the first row eleventh column thin film transistor T111; the first row twelfth column sub-pixel includes the first row twelfth column pixel electrode PJ112 and the first row twelfth column thin film transistor T112;

[0307] The second row first column sub-pixel comprises a second row first column pixel electrode PJ21 and a second row first column thin film transistor T21; the second row second column sub-pixel comprises a second row second column pixel electrode PJ22 and a second row second column thin film transistor T22; the second row third column sub-pixel comprises a second row third column pixel electrode PJ23 and a second row third column thin film transistor T23; the second row fourth column sub-pixel comprises a second row fourth column pixel electrode PJ24 and a second row fourth column thin film transistor T24; the second row fifth column sub-pixel comprises a second row fifth column pixel electrode PJ25 and a second row fifth column thin film transistor T25; the second row sixth column sub-pixel comprises a second row sixth column pixel electrode PJ26 and a second row sixth column thin film transistor T26; the second row seventh column sub-pixel comprises a second row seventh column pixel electrode PJ27 and a second row seventh column thin film transistor T27; the second row eighth column sub-pixel comprises a second row eighth column pixel electrode PJ28 and a second row eighth column thin film transistor T28; the second row ninth column sub-pixel comprises a second row ninth column pixel electrode PJ29 and a second row ninth column thin film transistor T29; the second row tenth column sub-pixel comprises a second row tenth column pixel electrode PJ210 and a second row tenth column thin film transistor T210; the second row eleventh column sub-pixel comprises a second row eleventh column pixel electrode PJ211 and a second row eleventh column thin film transistor T211; the second row twelfth column sub-pixel comprises a second row twelfth column pixel electrode PJ212 and a second row twelfth column thin film transistor T212;

[0308] The third row first column sub-pixel comprises a third row first column pixel electrode PJ31 and a third row first column thin film transistor T31; the third row second column sub-pixel comprises a third row second column pixel electrode PJ32 and a third row second column thin film transistor T32; the third row third column sub-pixel comprises a third row third column pixel electrode PJ33 and a third row third column thin film transistor T33; the third row fourth column sub-pixel comprises a third row fourth column pixel electrode PJ34 and a third row fourth column thin film transistor T34; the third row fifth column sub-pixel comprises a third row fifth column pixel electrode PJ35 and a third row fifth column thin film transistor T35; the third row sixth column sub-pixel comprises a third row sixth column pixel electrode PJ36 and a third row sixth column thin film transistor T36; the third row seventh column sub-pixel comprises a third row seventh column pixel electrode PJ37 and a third row seventh column thin film transistor T37; the third row eighth column sub-pixel comprises a third row eighth column pixel electrode PJ38 and a third row eighth column thin film transistor T38; the third row ninth column sub-pixel comprises a third row ninth column pixel electrode PJ39 and a third row ninth column thin film transistor T39; the third row tenth column sub-pixel comprises a third row tenth column pixel electrode PJ310 and a third row tenth column thin film transistor T310; the third row eleventh column sub-pixel comprises a third row eleventh column pixel electrode PJ311 and a third row eleventh column thin film transistor T311; the third row twelfth column sub-pixel comprises a third row twelfth column pixel electrode PJ312 and a third row twelfth column thin film transistor T312;

[0309] The fourth row first column sub-pixel comprises a fourth row first column pixel electrode PJ41 and a fourth row first column thin film transistor T41; the fourth row second column sub-pixel comprises a fourth row second column pixel electrode PJ42 and a fourth row second column thin film transistor T42; the fourth row third column sub-pixel comprises a fourth row third column pixel electrode PJ43 and a fourth row third column thin film transistor T43; the fourth row fourth column sub-pixel comprises a fourth row fourth column pixel electrode PJ44 and a fourth row fourth column thin film transistor T44; the fourth row fifth column sub-pixel comprises a fourth row fifth column pixel electrode PJ45 and a fourth row fifth column thin film transistor T45; the fourth row sixth column sub-pixel comprises a fourth row sixth column pixel electrode PJ46 and a fourth row sixth column thin film transistor T46; the fourth row seventh column sub-pixel comprises a fourth row seventh column pixel electrode PJ47 and a fourth row seventh column thin film transistor T47; the fourth row eighth column sub-pixel comprises a fourth row eighth column pixel electrode PJ48 and a fourth row eighth column thin film transistor T48; the fourth row ninth column sub-pixel comprises a fourth row ninth column pixel electrode PJ49 and a fourth row ninth column thin film transistor T49; the fourth row tenth column sub-pixel comprises a fourth row tenth column pixel electrode PJ410 and a fourth row tenth column thin film transistor T410; the fourth row eleventh column sub-pixel comprises a fourth row eleventh column pixel electrode PJ411 and a fourth row eleventh column thin film transistor T411; and the fourth row twelfth column sub-pixel comprises a fourth row twelfth column pixel electrode PJ412 and a fourth row twelfth column thin film transistor T412.

[0310] As shown in FIG. 8, in the working process of at least one embodiment of the pixel module shown in FIG. 7A, the display period can comprise a first stage S1, a second stage S2, a third stage S3 and a fourth stage S4 arranged in sequence.

[0311] In the first stage S1, G1 and G3 both provide a high voltage signal, P11 accesses the data voltage on DL1, P13 accesses the data voltage on DL2, P15 accesses the data voltage on DL3, P17 accesses the data voltage on DL4, P19 accesses the data voltage on DL5, and P111 accesses the data voltage on DL6;

[0312] P21 accesses the data voltage on DL1, P23 accesses the data voltage on DL2, P25 accesses the data voltage on DL3, P27 accesses the data voltage on DL4, P29 accesses the data voltage on DL5, and P211 accesses the data voltage on DL6;

[0313] P11 and P21 are both red sub-pixels, P13 and P23 are both blue sub-pixels, P15 and P25 are both green sub-pixels, P17 and P27 are both red sub-pixels, P19 and P29 are both blue sub-pixels, and P111 and P211 are both green sub-pixels, so that there is no color disorder when a monochrome image is displayed.

[0314] In the first stage S1, G2 and G4 provide high voltage signals, P12 and P22 are pre-charged by the data voltage on DL1, P14 and P24 are pre-charged by the data voltage on DL2, P16 and P26 are pre-charged by the data voltage on DL3, P18 and P28 are pre-charged by the data voltage on DL4, P110 and P210 are pre-charged by the data voltage on DL5, P112 and P212 are pre-charged by the data voltage on DL6, so that when the polarity is reversed between adjacent frames, P12, P22, P14, P24, P16, P26, P18, P28, P19, P29, P112 and P212 can be pre-charged with the data voltage of the corresponding polarity, so that in the second stage S2, P12, P22, P14, P24, P16, P26, P18, P28, P19, P29, P112 and P212 can be quickly charged with the data voltage of the polarity;

[0315] In the second stage S2, G2 and G4 provide high voltage signals, P12 accesses the data voltage on DL1, P14 receives the data voltage on DL2, P16 accesses the data voltage on DL3, P18 accesses the data voltage on DL4, P110 accesses the data voltage on DL5, P112 accesses the data voltage on DL6; P22 accesses the data voltage on DL1, P24 accesses the data voltage on DL2, P26 accesses the data voltage on DL3, P28 accesses the data voltage on DL4, P210 accesses the data voltage on DL5, and P212 accesses the data voltage on DL3;

[0316] In the second stage S2, G5 and G7 provide high voltage signals, P31 and P41 are pre-charged by the data voltage on DL2, P33 and P43 are pre-charged by the data voltage on DL3, P35 and P45 are pre-charged by the data voltage on DL4, P37 and P47 are pre-charged by the data voltage on DL5, P39 and P49 are pre-charged by the data voltage on DL6, and P311 and P411 are pre-charged by the data voltage on DL7, so that when the polarity is reversed between adjacent frames, P31, P41, P33, P43, P35, P45, P37, P47, P39, P49, P311 and P411 can be pre-charged with the data voltage of the corresponding polarity, so that in the second stage S2, P31, P41, P33, P43, P35, P45, P37, P47, P39, P49, P311 and P411 can be quickly charged with the data voltage of the polarity;

[0317] In the third stage S3, G5 and G7 provide high voltage signals, P31 and P41 receive data voltage on DL2, P33 and P43 receive data voltage on DL3, P35 and P45 receive data voltage on DL4, P37 and P47 receive data voltage on DL5, P39 and P49 receive data voltage on DL6, P311 and P411 receive data voltage on DL7;

[0318] In the third stage S3, G6 and G8 provide high voltage signals, P32 and P42 are pre-charged by data voltage on DL2, P34 and P44 are pre-charged by data voltage on DL3, P36 and P46 are pre-charged by data voltage on DL4, P38 and P48 are pre-charged by data voltage on DL5, P310 and P410 are pre-charged by data voltage on DL6, P312 and P412 are pre-charged by data voltage on DL7, so that when the polarity is reversed between adjacent frames, P32, P42, P34, P44, P36, P46, P38, P48, P310, P410, P312 and P412 can be pre-charged with data voltage of the corresponding polarity, so that in the second stage S2, P32, P42, P34, P44, P36, P46, P38, P48, P310, P410, P312 and P412 can be quickly charged with data voltage of the polarity;

[0319] In the fourth stage S4, G6 and G8 provide high voltage signals, P32 and P42 receive data voltage on DL2, P34 and P44 receive data voltage on DL3, P36 and P46 receive data voltage on DL4, P38 and P48 receive data voltage on DL5, P310 and P410 receive data voltage on DL6, P312 and P412 receive data voltage on DL7.

[0320] The driving method according to at least one embodiment of the present disclosure is applied to the pixel module described above, and a driving period includes a plurality of driving stages arranged in sequence; the driving method includes:

[0321] In the second 2c-1 stage, the fourth 4c-3 row scan line and the fourth 4c-1 row scan line are turned on, and the sub-pixels electrically connected to the fourth 4c-3 row scan line and the sub-pixels electrically connected to the fourth 4c-1 row scan line receive data voltage on the corresponding data line;

[0322] In the second 2c-1 stage, the fourth 4c-3 row scan line and the fourth 4c-1 row scan line are turned on, and the sub-pixels electrically connected to the fourth 4c-3 row scan line and the sub-pixels electrically connected to the fourth 4c-1 row scan line receive data voltage on the corresponding data line;

[0323] c is a positive integer.

[0324] In at least one embodiment of the present disclosure, the 2c-1 stage is a 2c pre-charge stage; the 2c stage is a 2c+1 pre-charge stage; the driving method further comprises:

[0325] In the 2c-1 stage, the 4c-2 row scanning line and the 4c row scanning line are turned on, and the sub-pixels electrically connected to the 4c-2 row scanning line and the sub-pixels electrically connected to the 4c row scanning line receive data voltages on the corresponding data lines to pre-charge the sub-pixels electrically connected to the 4c-2 row scanning line and the sub-pixels electrically connected to the 4c row scanning line.

[0326] In the 2c stage, the 4c+1 row scanning line and the 4c+3 row scanning line are turned on, and the sub-pixels electrically connected to the 4c-2 row scanning line and the sub-pixels electrically connected to the 4c+1 row scanning line receive data voltages on the corresponding data lines to pre-charge the sub-pixels electrically connected to the 4c+3 row scanning line and the sub-pixels electrically connected to the 4c row scanning line.

[0327] The display device described in the embodiments of the present disclosure comprises the pixel module described above.

[0328] The display device described in at least one embodiment of the present disclosure further comprises a driving module; the driving module comprises eight clock signal lines and a plurality of stages of driving circuits;

[0329] The 8d-7 stage driving circuit is electrically connected to the first clock signal line, the 8d-6 stage driving circuit is electrically connected to the second clock signal line, the 8d-5 stage driving circuit is electrically connected to the third clock signal line, the 8d-4 stage driving circuit is electrically connected to the fourth clock signal line, the 8d-3 stage driving circuit is electrically connected to the fifth clock signal line, the 8d-2 stage driving circuit is electrically connected to the sixth clock signal line, the 8d-1 stage driving circuit is electrically connected to the seventh clock signal line, and the 8d stage driving circuit is electrically connected to the eighth clock signal line; d is a positive integer;

[0330] The driving signal output end of the e stage driving circuit is electrically connected to the input end of the e+4 stage driving circuit, and the driving signal output end of the e+4 stage driving circuit is electrically connected to the reset end of the e stage driving circuit; e is a positive integer.

[0331] As shown in FIG. 9, in at least one embodiment of the present disclosure, the driving module comprises a first stage driving circuit GA1, a second stage driving circuit GA2, a third stage driving circuit GA3, a fourth stage driving circuit GA4, a fifth stage driving circuit GA5, a sixth stage driving circuit GA6, a seventh stage driving circuit GA7, and an eighth stage driving circuit GA8.

[0332] The GA1 is electrically connected with the first clock signal line CLK1, the GA2 is electrically connected with the second clock signal line CLK2, the GA3 is electrically connected with the third clock signal line CLK3, the GA4 is electrically connected with the fourth clock signal line CLK4, the GA5 is electrically connected with the fifth clock signal line CLK5, the GA6 is electrically connected with the sixth clock signal line CLK6, the GA7 is electrically connected with the seventh clock signal line CLK7, and the GA8 is electrically connected with the eighth clock signal line CLK8;

[0333] The driving signal output end of the GA1 is electrically connected with the input end of the GA5, the driving signal output end of the GA2 is electrically connected with the input end of the GA6, the driving signal output end of the GA3 is electrically connected with the input end of the GA7, and the driving signal output end of the GA4 is electrically connected with the input end of the GA8.

[0334] The driving signal output end of the GA5 is electrically connected with the reset end of the GA1, the driving signal output end of the GA6 is electrically connected with the reset end of the GA2, the driving signal output end of the GA7 is electrically connected with the reset end of the GA3, and the driving signal output end of the GA8 is electrically connected with the reset end of the GA4.

[0335] In FIG. 9, the input end is marked as I1, the driving signal output end is marked as OT, the reset end is marked as RST, and the clock signal end is marked as CLK.

[0336] The display device also includes a driving module; the driving module includes twelve clock signal lines and a plurality of driving circuits.

[0337] The 12d-11th driving circuit is electrically connected with the first clock signal line, the 12d-10th driving circuit is electrically connected with the second clock signal line, the 12d-9th driving circuit is electrically connected with the third clock signal line, the 12d-8th driving circuit is electrically connected with the fourth clock signal line, the 12d-7th driving circuit is electrically connected with the fifth clock signal line, the 12d-6th driving circuit is electrically connected with the sixth clock signal line, the 12d-5th driving circuit is electrically connected with the seventh clock signal line, the 12d-4th driving circuit is electrically connected with the eighth clock signal line, the 12d-3rd driving circuit is electrically connected with the ninth clock signal line, the 12d-2nd driving circuit is electrically connected with the tenth clock signal line, the 12d-1st driving circuit is electrically connected with the eleventh clock signal line, and the 12d driving circuit is electrically connected with the twelfth clock signal line; d is a positive integer.

[0338] The driving signal output end of the e-th driving circuit is electrically connected with the input end of the e+4th driving circuit, and the driving signal output end of the e+4th driving circuit is electrically connected with the reset end of the e-th driving circuit; e is a positive integer.

[0339] As shown in FIG. 10, in at least one embodiment of the present disclosure, the driving module includes a first-stage driving circuit GA1, a second-stage driving circuit GA2, a third-stage driving circuit GA3, a fourth-stage driving circuit GA4, a fifth-stage driving circuit GA5, a sixth-stage driving circuit GA6, a seventh-stage driving circuit GA7, an eighth-stage driving circuit GA8, a ninth-stage driving circuit GA9, a tenth-stage driving circuit GA10, an eleventh-stage driving circuit GA11, and a twelfth-stage driving circuit GA12.

[0340] The first-stage driving circuit GA1 is electrically connected with a first clock signal line CLK1, the second-stage driving circuit GA2 is electrically connected with a second clock signal line CLK2, the third-stage driving circuit GA3 is electrically connected with a third clock signal line CLK3, the fourth-stage driving circuit GA4 is electrically connected with a fourth clock signal line CLK4, the fifth-stage driving circuit GA5 is electrically connected with a fifth clock signal line CLK5, the sixth-stage driving circuit GA6 is electrically connected with a sixth clock signal line CLK6, the seventh-stage driving circuit GA7 is electrically connected with a seventh clock signal line CLK7, and the eighth-stage driving circuit GA8 is electrically connected with an eighth clock signal line CLK8; the ninth-stage driving circuit GA9 is electrically connected with a ninth clock signal line CLK9, the tenth-stage driving circuit GA10 is electrically connected with a tenth clock signal line CLK10, the eleventh-stage driving circuit GA11 is electrically connected with an eleventh clock signal line CLK11, and the twelfth-stage driving circuit GA12 is electrically connected with a twelfth clock signal line CLK12.

[0341] The driving signal output end of the first-stage driving circuit GA1 is electrically connected with the input end of the fifth-stage driving circuit GA5, the driving signal output end of the second-stage driving circuit GA2 is electrically connected with the input end of the sixth-stage driving circuit GA6, the driving signal output end of the third-stage driving circuit GA3 is electrically connected with the input end of the seventh-stage driving circuit GA7, and the driving signal output end of the fourth-stage driving circuit GA4 is electrically connected with the input end of the eighth-stage driving circuit GA8; the driving signal output end of the fifth-stage driving circuit GA5 is electrically connected with the input end of the ninth-stage driving circuit GA9, the driving signal output end of the sixth-stage driving circuit GA6 is electrically connected with the input end of the tenth-stage driving circuit GA10, the driving signal output end of the seventh-stage driving circuit GA7 is electrically connected with the input end of the eleventh-stage driving circuit GA11, and the driving signal output end of the eighth-stage driving circuit GA8 is electrically connected with the input end of the twelfth-stage driving circuit GA12.

[0342] The driving signal output end of the fifth-stage driving circuit GA5 is electrically connected with the reset end of the first-stage driving circuit GA1, the driving signal output end of the sixth-stage driving circuit GA6 is electrically connected with the reset end of the second-stage driving circuit GA2, the driving signal output end of the seventh-stage driving circuit GA7 is electrically connected with the reset end of the third-stage driving circuit GA3, and the driving signal output end of the eighth-stage driving circuit GA8 is electrically connected with the reset end of the fourth-stage driving circuit GA4; the driving signal output end of the ninth-stage driving circuit GA9 is electrically connected with the reset end of the fifth-stage driving circuit GA5, the driving signal output end of the tenth-stage driving circuit GA10 is electrically connected with the reset end of the sixth-stage driving circuit GA6, the driving signal output end of the eleventh-stage driving circuit GA11 is electrically connected with the reset end of the seventh-stage driving circuit GA7, and the driving signal output end of the twelfth-stage driving circuit GA12 is electrically connected with the reset end of the eighth-stage driving circuit GA8.

[0343] In FIG. 10, the input end is marked as I1, the driving signal output end is marked as OT, the reset end is marked as RST, and the clock signal end is marked as CLK.

[0344] The display device in at least one embodiment of the present disclosure further comprises a driving module; the driving module comprises sixteen clock signal lines and multiple-stage driving circuits;

[0345] The 16d-15th driving circuit is electrically connected with the first clock signal line, the 16d-14th driving circuit is electrically connected with the second clock signal line, the 16d-13th driving circuit is electrically connected with the third clock signal line, the 16d-12th driving circuit is electrically connected with the fourth clock signal line, the 16d-11th driving circuit is electrically connected with the fifth clock signal line, the 16d-19th driving circuit is electrically connected with the sixth clock signal line, the 16d-9th driving circuit is electrically connected with the seventh clock signal line, the 16d-8th driving circuit is electrically connected with the eighth clock signal line, the 16d-7th driving circuit is electrically connected with the ninth clock signal line, the 16d-6th driving circuit is electrically connected with the tenth clock signal line, the 16d-5th driving circuit is electrically connected with the eleventh clock signal line, the 16d-4th driving circuit is electrically connected with the twelfth clock signal line, the 16d-3th driving circuit is electrically connected with the thirteenth clock signal line, the 16d-2th driving circuit is electrically connected with the fourteenth clock signal line, the 16d-1th driving circuit is electrically connected with the fifteenth clock signal line, and the 16dth driving circuit is electrically connected with the sixteenth clock signal line; d is a positive integer;

[0346] The driving signal output end of the e-th driving circuit is electrically connected with the input end of the e+8-th driving circuit, and the driving signal output end of the e+8-th driving circuit is electrically connected with the reset end of the e-th driving circuit; e is a positive integer.

[0347] As shown in FIG. 11, in at least one embodiment of the present disclosure, the driving module comprises a first driving circuit GA1, a second driving circuit GA2, a third driving circuit GA3, a fourth driving circuit GA4, a fifth driving circuit GA5, a sixth driving circuit GA6, a seventh driving circuit GA7, an eighth driving circuit GA8, a ninth driving circuit GA9, a tenth driving circuit GA10, an eleventh driving circuit GA11, a twelfth driving circuit GA12, a thirteenth driving circuit GA13, a fourteenth driving circuit GA14, a fifteenth driving circuit GA15, and a sixteenth driving circuit GA16.

[0348] The GA1 is electrically connected with the first clock signal line CLK1, the GA2 is electrically connected with the second clock signal line CLK2, the GA3 is electrically connected with the third clock signal line CLK3, the GA4 is electrically connected with the fourth clock signal line CLK4, the GA5 is electrically connected with the fifth clock signal line CLK5, the GA6 is electrically connected with the sixth clock signal line CLK6, the GA7 is electrically connected with the seventh clock signal line CLK7, and the GA8 is electrically connected with the eighth clock signal line CLK8; the GA9 is electrically connected with the ninth clock signal line CLK9, the GA10 is electrically connected with the tenth clock signal line CLK10, the GA11 is electrically connected with the eleventh clock signal line CLK11, and the GA12 is electrically connected with the twelfth clock signal line CLK12; the GA13 is electrically connected with the thirteenth clock signal line CLK13, the GA14 is electrically connected with the fourteenth clock signal line CLK14, the GA15 is electrically connected with the fifteenth clock signal line CLK15, and the GA16 is electrically connected with the sixteenth clock signal line CLK16.

[0349] The driving signal output end of the GA1 is electrically connected with the input end of the GA9, the driving signal output end of the GA2 is electrically connected with the input end of the GA10, the driving signal output end of the GA3 is electrically connected with the input end of the GA11, and the driving signal output end of the GA4 is electrically connected with the input end of the GA12; the driving signal output end of the GA5 is electrically connected with the input end of the GA13, the driving signal output end of the GA6 is electrically connected with the input end of the GA14, the driving signal output end of the GA7 is electrically connected with the input end of the GA15, and the driving signal output end of the GA8 is electrically connected with the input end of the GA16.

[0350] The driving signal output end of the GA9 is electrically connected with the reset end of the GA1, the driving signal output end of the GA10 is electrically connected with the reset end of the GA2, the driving signal output end of the GA11 is electrically connected with the reset end of the GA3, and the driving signal output end of the GA12 is electrically connected with the reset end of the GA4; the driving signal output end of the GA13 is electrically connected with the reset end of the GA5, the driving signal output end of the GA14 is electrically connected with the reset end of the GA6, the driving signal output end of the GA15 is electrically connected with the reset end of the GA7, and the driving signal output end of the GA16 is electrically connected with the reset end of the GA8.

[0351] In FIG. 11, the input end is marked as I1, the driving signal output end is marked as OT, the reset end is marked as RST, and the clock signal end is marked as CLK.

[0352] The above is the preferred embodiment of the present disclosure, and it should be pointed out that, for those skilled in the art, without departing from the principles of the present disclosure, a number of improvements and refinements can be made, which should also be considered as the protection scope of the present disclosure.

Claims

1. A pixel module, comprising a plurality of rows of a plurality of columns of sub-pixels, a plurality of rows of scan lines and a plurality of columns of data lines; Two sub-pixels in the nth row are arranged between the (2n-1)th row of scan lines, the 2nth row of scan lines, the mth column of scan lines and the (m+1)th column of scan lines;n and m are positive integers; The sub-pixels are respectively electrically connected with a row of scan lines and a column of data lines, and are used for receiving a data voltage provided by the data line under the control of a scanning signal provided by the scan line; In the sub-pixels electrically connected with the (2n-1)th row of scan lines and the sub-pixels electrically connected with the (2n+1)th row of scan lines, the sub-pixels electrically connected with the same column of data lines have the same color; In the sub-pixels electrically connected with the 2nth row of scan lines and the sub-pixels electrically connected with the (2n+2)th row of scan lines, the sub-pixels electrically connected with the same column of data lines have the same color.

2. The pixel module of claim 1, wherein, The 6th b-5th column of sub-pixels in the 4th a-3rd row are respectively electrically connected with the 8th a-7th row of scan lines and the 3rd b-2nd column of data lines, and are used for receiving a data voltage provided by the 3rd b-2nd column of data lines under the control of a scanning signal provided by the 8th a-7th row of scan lines; The 6th b-4th column of sub-pixels in the 4th a-3rd row are respectively electrically connected with the 8th a-6th row of scan lines and the 3rd b-2nd column of data lines, and are used for receiving a data voltage provided by the 3rd b-2nd column of data lines under the control of a scanning signal provided by the 8th a-6th row of scan lines; The 6th b-3rd column of sub-pixels in the 4th a-3rd row are respectively electrically connected with the 8th a-6th row of scan lines and the 3rd b-1st column of data lines, and are used for receiving a data voltage provided by the 3rd b-1st column of data lines under the control of a scanning signal provided by the 8th a-6th row of scan lines; The 6th b-2nd column of sub-pixels in the 4th a-3rd row are respectively electrically connected with the 8th a-7th row of scan lines and the 3rd b-1st column of data lines, and are used for receiving a data voltage provided by the 3rd b-1st column of data lines under the control of a scanning signal provided by the 8th a-7th row of scan lines; The 6th b-1st column of sub-pixels in the 4th a-3rd row are respectively electrically connected with the 8th a-6th row of scan lines and the 3rd b column of data lines, and are used for receiving a data voltage provided by the 3rd b column of data lines under the control of a scanning signal provided by the 8th a-6th row of scan lines; The 6th b column of sub-pixels in the 4th a-3rd row are respectively electrically connected with the 8th a-7th row of scan lines and the 3rd b column of data lines, and are used for receiving a data voltage provided by the 3rd b column of data lines under the control of a scanning signal provided by the 8th a-7th row of scan lines; a and b are positive integers.

3. The pixel module of claim 2, wherein, The 6th b-5th column of sub-pixels in the 4th a-2nd row are respectively electrically connected with the 8th a-5th row of scan lines and the 3rd b-2nd column of data lines, and are used for receiving a data voltage provided by the 3rd b-2nd column of data lines under the control of a scanning signal provided by the 8th a-5th row of scan lines; The 6th b-4th column of sub-pixels in the 4th a-2nd row are respectively electrically connected with the 8th a-4th row of scan lines and the 3rd b-2nd column of data lines, and are used for receiving a data voltage provided by the 3rd b-2nd column of data lines under the control of a scanning signal provided by the 8th a-4th row of scan lines. The 6th b-3 column sub-pixel in the 4th a-2 row is electrically connected with the 8th a-4 row scanning line and the 3rd b-1 column data line respectively, for receiving the data voltage provided by the 3rd b-1 column data line under the control of the scanning signal provided by the 8th a-4 row scanning line; The 6th b-2 column sub-pixel in the 4th a-2 row is electrically connected with the 8th a-5 row scanning line and the 3rd b-1 column data line respectively, for receiving the data voltage provided by the 3rd b-1 column data line under the control of the scanning signal provided by the 8th a-5 row scanning line; The 6th b-1 column sub-pixel in the 4th a-2 row is electrically connected with the 8th a-4 row scanning line and the 3rd b column data line respectively, for receiving the data voltage provided by the 3rd b column data line under the control of the scanning signal provided by the 8th a-4 row scanning line; The 6th b column sub-pixel in the 4th a-2 row is electrically connected with the 8th a-5 row scanning line and the 3rd b column data line respectively, for receiving the data voltage provided by the 3rd b column data line under the control of the scanning signal provided by the 8th a-5 row scanning line.

4. The pixel module of claim 3, wherein, The 6th b-5 column sub-pixel in the 4th a-1 row is electrically connected with the 8th a-3 row scanning line and the 3rd b-1 column data line respectively, for receiving the data voltage provided by the 3rd b-1 column data line under the control of the scanning signal provided by the 8th a-3 row scanning line; The 6th b-4 column sub-pixel in the 4th a-1 row is electrically connected with the 8th a-2 row scanning line and the 3rd b-1 column data line respectively, for receiving the data voltage provided by the 3rd b-1 column data line under the control of the scanning signal provided by the 8th a-2 row scanning line; The 6th b-3 column sub-pixel in the 4th a-1 row is electrically connected with the 8th a-2 row scanning line and the 3rd b column data line respectively, for receiving the data voltage provided by the 3rd b column data line under the control of the scanning signal provided by the 8th a-2 row scanning line; The 6th b-2 column sub-pixel in the 4th a-1 row is electrically connected with the 8th a-3 row scanning line and the 3rd b column data line respectively, for receiving the data voltage provided by the 3rd b column data line under the control of the scanning signal provided by the 8th a-3 row scanning line; The 6th b-1 column sub-pixel in the 4th a-1 row is electrically connected with the 8th a-2 row scanning line and the 3rd b+1 column data line respectively, for receiving the data voltage provided by the 3rd b+1 column data line under the control of the scanning signal provided by the 8th a-2 row scanning line; The 6th b column sub-pixel in the 4th a-1 row is electrically connected with the 8th a-3 row scanning line and the 3rd b+1 column data line respectively, for receiving the data voltage provided by the 3rd b+1 column data line under the control of the scanning signal provided by the 8th a-3 row scanning line.

5. The pixel module of claim 4, wherein, The 6th b-5 column sub-pixel in the 4th a row is electrically connected with the 8th a-1 row scanning line and the 3rd b-1 column data line respectively, for receiving the data voltage provided by the 3rd b-1 column data line under the control of the scanning signal provided by the 8th a-1 row scanning line; The 6th b-4 column sub-pixel of the 4th a row is electrically connected with the 8th a row scanning line and the 3rd b-1 column data line respectively, for receiving data voltage provided by the 3rd b-1 column data line under the control of the scanning signal provided by the 8th a row scanning line; The 6th b-3 column sub-pixel of the 4th a row is electrically connected with the 8th a row scanning line and the 3rd b column data line respectively, for receiving data voltage provided by the 3rd b column data line under the control of the scanning signal provided by the 8th a row scanning line; The 6th b-2 column sub-pixel of the 4th a row is electrically connected with the 8th a-1 row scanning line and the 3rd b column data line respectively, for receiving data voltage provided by the 3rd b column data line under the control of the scanning signal provided by the 8th a-1 row scanning line; The 6th b-1 column sub-pixel of the 4th a row is electrically connected with the 8th a row scanning line and the 3rd b+1 column data line respectively, for receiving data voltage provided by the 3rd b+1 column data line under the control of the scanning signal provided by the 8th a row scanning line; The 6th b column sub-pixel of the 4th a row is electrically connected with the 8th a-1 row scanning line and the 3rd b+1 column data line respectively, for receiving data voltage provided by the 3rd b+1 column data line under the control of the scanning signal provided by the 8th a-1 row scanning line.

6. The pixel module of claim 1, wherein, The 6th b-5 column sub-pixel of the 4th a-3 row is electrically connected with the 8th a-7 row scanning line and the 3rd b-2 column data line respectively, for receiving data voltage provided by the 3rd b-2 column data line under the control of the scanning signal provided by the 8th a-7 row scanning line; The 6th b-4 column sub-pixel of the 4th a-3 row is electrically connected with the 8th a-6 row scanning line and the 3rd b-2 column data line respectively, for receiving data voltage provided by the 3rd b-2 column data line under the control of the scanning signal provided by the 8th a-6 row scanning line; The 6th b-3 column sub-pixel of the 4th a-3 row is electrically connected with the 8th a-7 row scanning line and the 3rd b-1 column data line respectively, for receiving data voltage provided by the 3rd b-1 column data line under the control of the scanning signal provided by the 8th a-7 row scanning line; The 6th b-2 column sub-pixel of the 4th a-3 row is electrically connected with the 8th a-6 row scanning line and the 3rd b-1 column data line respectively, for receiving data voltage provided by the 3rd b-1 column data line under the control of the scanning signal provided by the 8th a-6 row scanning line; The 6th b-1 column sub-pixel of the 4th a-3 row is electrically connected with the 8th a-7 row scanning line and the 3rd b column data line respectively, for receiving data voltage provided by the 3rd b column data line under the control of the scanning signal provided by the 8th a-7 row scanning line; The 6th b column sub-pixel of the 4th a-3 row is electrically connected with the 8th a-6 row scanning line and the 3rd b column data line respectively, for receiving data voltage provided by the 3rd b column data line under the control of the scanning signal provided by the 8th a-6 row scanning line; a and b are positive integers.

7. The pixel module of claim 6, wherein, The 6th b-5 column sub-pixel in the 4th a-2 row is electrically connected with the 8th a-5 row scanning line and the 3rd b-2 column data line respectively, for receiving the data voltage provided by the 3rd b-2 column data line under the control of the scanning signal provided by the 8th a-5 row scanning line; The 6th b-4 column sub-pixel in the 4th a-2 row is electrically connected with the 8th a-4 row scanning line and the 3rd b-2 column data line respectively, for receiving the data voltage provided by the 3rd b-2 column data line under the control of the scanning signal provided by the 8th a-4 row scanning line; The 6th b-3 column sub-pixel in the 4th a-2 row is electrically connected with the 8th a-5 row scanning line and the 3rd b-1 column data line respectively, for receiving the data voltage provided by the 3rd b-1 column data line under the control of the scanning signal provided by the 8th a-5 row scanning line; The 6th b-2 column sub-pixel in the 4th a-2 row is electrically connected with the 8th a-4 row scanning line and the 3rd b-1 column data line respectively, for receiving the data voltage provided by the 3rd b-1 column data line under the control of the scanning signal provided by the 8th a-4 row scanning line; The 6th b-1 column sub-pixel in the 4th a-2 row is electrically connected with the 8th a-5 row scanning line and the 3rd b column data line respectively, for receiving the data voltage provided by the 3rd b column data line under the control of the scanning signal provided by the 8th a-5 row scanning line; The 6th b column sub-pixel in the 4th a-2 row is electrically connected with the 8th a-4 row scanning line and the 3rd b column data line respectively, for receiving the data voltage provided by the 3rd b column data line under the control of the scanning signal provided by the 8th a-4 row scanning line.

8. The pixel module of claim 7, wherein, The 6th b-5 column sub-pixel in the 4th a-1 row is electrically connected with the 8th a-3 row scanning line and the 3rd b-1 column data line respectively, for receiving the data voltage provided by the 3rd b-1 column data line under the control of the scanning signal provided by the 8th a-3 row scanning line; The 6th b-4 column sub-pixel in the 4th a-1 row is electrically connected with the 8th a-2 row scanning line and the 3rd b-1 column data line respectively, for receiving the data voltage provided by the 3rd b-1 column data line under the control of the scanning signal provided by the 8th a-2 row scanning line; The 6th b-3 column sub-pixel in the 4th a-1 row is electrically connected with the 8th a-3 row scanning line and the 3rd b column data line respectively, for receiving the data voltage provided by the 3rd b column data line under the control of the scanning signal provided by the 8th a-3 row scanning line; The 6th b-2 column sub-pixel in the 4th a-1 row is electrically connected with the 8th a-2 row scanning line and the 3rd b column data line respectively, for receiving the data voltage provided by the 3rd b column data line under the control of the scanning signal provided by the 8th a-2 row scanning line; The 6th b-1 column sub-pixel in the 4th a-1 row is electrically connected with the 8th a-3 row scanning line and the 3rd b+1 column data line respectively, for receiving the data voltage provided by the 3rd b+1 column data line under the control of the scanning signal provided by the 8th a-3 row scanning line; The sub-pixels in the 6th b-1 column of the 4th a row are respectively electrically connected with the 8th a-1 row of scan lines and the 3rd b-1 column of data lines, and are used for receiving data voltages provided by the 3rd b-1 column of data lines under control of scan signals provided by the 8th a-1 row of scan lines.

9. The pixel module of claim 8, wherein, The sub-pixels in the 6th b-1 column of the 4th a row are respectively electrically connected with the 8th a-1 row of scan lines and the 3rd b-1 column of data lines, and are used for receiving data voltages provided by the 3rd b-1 column of data lines under control of scan signals provided by the 8th a-1 row of scan lines. The sub-pixels in the 6th b-1 column of the 4th a row are respectively electrically connected with the 8th a-1 row of scan lines and the 3rd b-1 column of data lines, and are used for receiving data voltages provided by the 3rd b-1 column of data lines under control of scan signals provided by the 8th a-1 row of scan lines. The sub-pixels in the 6th b-1 column of the 4th a row are respectively electrically connected with the 8th a-1 row of scan lines and the 3rd b-1 column of data lines, and are used for receiving data voltages provided by the 3rd b-1 column of data lines under control of scan signals provided by the 8th a-1 row of scan lines. The sub-pixels in the 6th b-1 column of the 4th a row are respectively electrically connected with the 8th a-1 row of scan lines and the 3rd b-1 column of data lines, and are used for receiving data voltages provided by the 3rd b-1 column of data lines under control of scan signals provided by the 8th a-1 row of scan lines. The sub-pixels in the 6th b-1 column of the 4th a row are respectively electrically connected with the 8th a-1 row of scan lines and the 3rd b-1 column of data lines, and are used for receiving data voltages provided by the 3rd b-1 column of data lines under control of scan signals provided by the 8th a-1 row of scan lines. The sub-pixels in the 6th b-1 column of the 4th a row are respectively electrically connected with the 8th a-1 row of scan lines and the 3rd b-1 column of data lines, and are used for receiving data voltages provided by the 3rd b-1 column of data lines under control of scan signals provided by the 8th a-1 row of scan lines.

10. The pixel module of any one of claims 1 to 9, wherein, The sub-pixels in the 6th b-1 column of the 4th a row are respectively electrically connected with the 8th a-1 row of scan lines and the 3rd b-1 column of data lines, and are used for receiving data voltages provided by the 3rd b-1 column of data lines under control of scan signals provided by the 8th a-1 row of scan lines. The sub-pixels in the 6th b-1 column of the 4th a row are respectively electrically connected with the 8th a-1 row of scan lines and the 3rd b-1 column of data lines, and are used for receiving data voltages provided by the 3rd b-1 column of data lines under control of scan signals provided by the 8th a-1 row of scan lines. The sub-pixels in the 6th b-1 column of the 4th a row are respectively electrically connected with the 8th a-1 row of scan lines and the 3rd b-1 column of data lines, and are used for receiving data voltages provided by the 3rd b-1 column of data lines under control of scan signals provided by the 8th a-1 row of scan lines. The sub-pixels in the 6th b-1 column of the 4th a row are respectively electrically connected with the 8th a-1 row of scan lines and the 3rd b-1 column of data lines, and are used for receiving data voltages provided by the 3rd b-1 column of data lines under control of scan signals provided by the 8th a-1 row of scan lines. The sub-pixels in the 6th b-1 column of the 4th a row are respectively electrically connected with the 8th a-1 row of scan lines and the 3rd b-1 column of data lines, and are used for receiving data voltages provided by the 3rd b-1 column of data lines under control of scan signals provided by the 8th a-1 row of scan lines.

12. The driving method of claim 11, wherein, The sub-pixels in the 6th b-1 column of the 4th a row are respectively electrically connected with the 8th a-1 row of scan lines and the 3rd b-1 column of data lines, and are used for receiving data voltages provided by the 3rd b-1 column of data lines under control of scan signals provided by the 8th a-1 row of scan lines. The sub-pixels in the 6th b-1 column of the 4th a row are respectively electrically connected with the 8th a-1 row of scan lines and the 3rd b-1 column of data lines, and are used for receiving data voltages provided by the 3rd b-1 column of data lines under control of scan signals provided by the 8th a-1 row of scan lines. The sub-pixels in the 6th b-1 column of the 4th a row are respectively electrically connected with the 8th a-1 row of scan lines and the 3rd b-1 column of data lines, and are used for receiving data voltages provided by the 3rd b-1 column of data lines under control of scan signals provided by the 8th a-1 row of scan lines. The sub-pixels in the 6th b-1 column of the 4th a row are respectively electrically connected with the 8th a-1 row of scan lines and the 3rd b-1 column of data lines, and are used for receiving data voltages provided by the 3rd b-1 column of data lines under control of scan signals provided by the 8th a-1 row of scan lines. The sub-pixels in the 6th b-1 column of the 4th a row are respectively electrically connected with the 8th a-1 row of scan lines and the 3rd b-1 column of data lines, and are used for receiving data voltages provided by the 3rd b-1 column of data lines under control of scan signals provided by the 8th a-1 row of scan lines. The sub-pixels in the 6th b-1 column of the 4th a row are respectively electrically connected with the 8th a-1 row of scan lines and the 3rd b-1 column of data lines, and are used for receiving data voltages provided by the 3rd b-1 column of data lines under control of scan signals provided by the 8th a-1 row of scan lines. The sub-pixels in the 6th b-1 column of the 4th a row are respectively electrically connected with the 8th a-1 row of scan lines and the 3rd b-1 column of data lines, and are used for receiving data voltages provided by the 3rd b-1 column of data lines under control of scan signals provided by the 8th a-1 row of scan lines. The sub-pixels in the 6th b-1 column of the 4th a row are respectively electrically connected with the 8th a-1 row of scan lines and the 3rd b-1 column of data lines, and are used for receiving data voltages provided by the 3rd b-1 column of data lines under control of scan signals provided by the 8th a-1 row of scan lines. The sub-pixels in the 6th b-1 column of the 4th a row are respectively electrically connected with the 8th a-1 row of scan lines and the 3rd b-1 column of data lines, and are used for receiving data voltages provided by the 3rd b-1 column of data lines under control of scan signals provided by the 8th a-1 row of scan lines. The sub-pixels in the 6th b-1 column of the 4th a row are respectively electrically connected with the 8th a-1 row of scan lines and the 3rd b-1 column of data lines, and are used for receiving data voltages provided by the 3rd b-1 column of data lines under control of scan signals provided by the 8th a-1 row of scan lines. The sub-pixels in the 6th b-1 column of the 4th a row are respectively electrically connected with the 8th a-1 row of scan lines and the 3rd b-1 column of data lines, and are used for receiving data voltages provided by the 3rd b-1 column In the first 2c-1 stage, the fourth 4c-2 row scanning line and the fourth 4c row scanning line are opened, and the sub-pixels electrically connected with the fourth 4c-2 row scanning line and the sub-pixels electrically connected with the fourth 4c row scanning line receive the data voltage on the corresponding data line to pre-charge the sub-pixels electrically connected with the fourth 4c-2 row scanning line and the sub-pixels electrically connected with the fourth 4c row scanning line. In the second 2c stage, the fourth 4c+1 row scanning line and the fourth 4c+3 row scanning line are opened, and the sub-pixels electrically connected with the fourth 4c-2 row scanning line and the sub-pixels electrically connected with the fourth 4c+1 row scanning line receive the data voltage on the corresponding data line to pre-charge the sub-pixels electrically connected with the fourth 4c+3 row scanning line and the sub-pixels electrically connected with the fourth 4c row scanning line.

13. A display device comprising the pixel module of any one of claims 1 to 10.

14. The display device of claim 13, wherein, Further comprising a driving module; the driving module comprises eight clock signal lines and a plurality of driving circuits; The eighth 8d-7 driving circuit is electrically connected with the first clock signal line, the eighth 8d-6 driving circuit is electrically connected with the second clock signal line, the eighth 8d-5 driving circuit is electrically connected with the third clock signal line, the eighth 8d-4 driving circuit is electrically connected with the fourth clock signal line, the eighth 8d-3 driving circuit is electrically connected with the fifth clock signal line, the eighth 8d-2 driving circuit is electrically connected with the sixth clock signal line, the eighth 8d-1 driving circuit is electrically connected with the seventh clock signal line, and the eighth 8d driving circuit is electrically connected with the eighth clock signal line; d is a positive integer. The driving signal output end of the e-th driving circuit is electrically connected with the input end of the e+4-th driving circuit, and the driving signal output end of the e+4-th driving circuit is electrically connected with the reset end of the e-th driving circuit; e is a positive integer.

15. The display device of claim 13, wherein, Further comprising a driving module; the driving module comprises twelve clock signal lines and a plurality of driving circuits; The twelfth 12d-11 driving circuit is electrically connected with the first clock signal line, the twelfth 12d-10 driving circuit is electrically connected with the second clock signal line, the twelfth 12d-9 driving circuit is electrically connected with the third clock signal line, the twelfth 12d-8 driving circuit is electrically connected with the fourth clock signal line, the twelfth 12d-7 driving circuit is electrically connected with the fifth clock signal line, the twelfth 12d-6 driving circuit is electrically connected with the sixth clock signal line, the twelfth 12d-5 driving circuit is electrically connected with the seventh clock signal line, the twelfth 12d-4 driving circuit is electrically connected with the eighth clock signal line, the twelfth 12d-3 driving circuit is electrically connected with the ninth clock signal line, the twelfth 12d-2 driving circuit is electrically connected with the tenth clock signal line, the twelfth 12d-1 driving circuit is electrically connected with the eleventh clock signal line, and the twelfth 12d driving circuit is electrically connected with the twelfth clock signal line; d is a positive integer. The driving signal output end of the e-th driving circuit is electrically connected with the input end of the e+4-th driving circuit, and the driving signal output end of the e+4-th driving circuit is electrically connected with the reset end of the e-th driving circuit; e is a positive integer.

16. The display device of claim 13, wherein, Further comprising a driving module; the driving module comprises sixteen clock signal lines and a plurality of driving circuits; The 16d-15th-stage driving circuit is electrically connected with the first clock signal line, the 16d-14th-stage driving circuit is electrically connected with the second clock signal line, the 16d-13th-stage driving circuit is electrically connected with the third clock signal line, the 16d-12th-stage driving circuit is electrically connected with the fourth clock signal line, the 16d-11th-stage driving circuit is electrically connected with the fifth clock signal line, the 16d-19th-stage driving circuit is electrically connected with the sixth clock signal line, the 16d-9th-stage driving circuit is electrically connected with the seventh clock signal line, the 16d-8th-stage driving circuit is electrically connected with the eighth clock signal line, the 16d-7th-stage driving circuit is electrically connected with the ninth clock signal line, the 16d-6th-stage driving circuit is electrically connected with the tenth clock signal line, the 16d-5th-stage driving circuit is electrically connected with the eleventh clock signal line, the 16d-4th-stage driving circuit is electrically connected with the twelfth clock signal line, the 16d-3th-stage driving circuit is electrically connected with the thirteenth clock signal line, the 16d-2th-stage driving circuit is electrically connected with the fourteenth clock signal line, the 16d-1th-stage driving circuit is electrically connected with the fifteenth clock signal line, and the 16dth-stage driving circuit is electrically connected with the sixteenth clock signal line; d is a positive integer. The driving signal output end of the e-stage driving circuit is electrically connected with the input end of the e+8-stage driving circuit, and the driving signal output end of the e+8-stage driving circuit is electrically connected with the reset end of the e-stage driving circuit; e is a positive integer.

Images