High-throughput neural signal acquisition and processing device and arrangement method therefor

Abstract

Disclosed in the present invention are a high-throughput neural signal acquisition and processing device and an arrangement method therefor. The high-throughput neural signal acquisition and processing device comprises a front end and a rear end, and the front end comprises a neural signal acquisition module, an FPGA module, and a serializer module; the neural signal acquisition module is used for acquiring a high-throughput raw neural signal; the FPGA module is connected to the neural signal acquisition module, and the FPGA module is used for processing the raw neural signal, and constructing a parallel neural data set on the basis of a processing result and the high-throughput raw neural signal; the serializer module is connected to the FPGA module, and the serializer module is used for converting the parallel neural data set into high-speed serial data; the rear end is connected to the serializer module by means of a wire, and the rear end is used for converting the high-speed serial data into a parallel signal and sending the parallel signal to a PC end. The device can transmit a high-throughput neural signal by means of a relatively light wire, so that the device is more convenient and flexible.

Description

High-throughput neural signal acquisition and processing device and arrangement method thereof TECHNICAL FIELD

[0001] The present application belongs to the technical field of neural signal acquisition and processing, and particularly relates to a high-throughput neural signal acquisition and processing device and an arrangement method thereof. BACKGROUND

[0002] Neural signal acquisition equipment is a tool for recording and analyzing the activity of the nervous system in living organisms, and plays an important role in the field of neuroscience and brain-computer interface. Neural signal acquisition equipment can help scientists understand the structure and function of the nervous system, study the regularity of brain activity, neural conduction mechanism, etc., and provide important data and information for the development of neuroscience.

[0003] In clinical practice, neural signal acquisition equipment can be used to diagnose diseases related to the nervous system, such as epilepsy, Parkinson's disease, etc., to help doctors accurately assess the condition and guide the development of treatment plans. Neural signal acquisition equipment is also applied in neural control interface technology, such as brain-computer interface (BCI) systems, to help disabled people control external devices and improve their quality of life. By recording changes in neural signals, researchers can study neural plasticity and explore the neural basis of cognitive functions such as learning and memory, which is of great significance to education, rehabilitation, and other fields. Therefore, neural signal acquisition equipment plays an important role and significance in scientific research, clinical medicine, engineering technology, and other fields.

[0004] Neural signal acquisition devices are usually composed of a neural signal analog front-end (Headstage), a lead wire, and a neural signal integration unit. The Headstage generally includes amplification, filtering, digitization, etc. units, fixed on the animal's head, transmitted to the neural signal integration unit through the lead wire, and further connected to the computer. Traditional Headstage usually only has recording function, without hardware-level neural signal processing capability, and the function is relatively single.

[0005] The invention patent application with publication number CN113918008A discloses a brain-computer interface system and application method based on source space magnetoencephalographic signal decoding. The system includes a magnetoencephalographic signal acquisition device for wearing on the head of a subject, collecting the subject's magnetoencephalographic signal and sending it to a data acquisition workstation; a data acquisition workstation for synchronously receiving multi-channel magnetoencephalographic signals collected by the magnetoencephalographic signal acquisition device and sending them to a real-time analysis workstation; a real-time analysis workstation for real-time preprocessing, tracing and decoding the received magnetoencephalographic signals, and sending the decoded information to a multi-modal stimulation presentation device and an external controlled device; a multi-modal stimulation presentation device for presenting stimulation information to evoke the subject's brain neural activity or neural feedback signals decoded by the real-time analysis workstation; an external controlled device for processing according to the received decoded signals.

[0006] The wire used for transmitting the brain magnetic signal of the subject to the data collection workstation in the above patent is limited by the weight, and the number of channels of the recorded neural signal is less, generally less than 64 channels. In addition, the neural signal integration unit at the rear end is usually in the form of a special computer, which usually includes a large case, and the power consumption and volume are large. Due to the above defects, the traditional neural signal collection device is not suitable for high-throughput, neural signal processing, and portable scenes.

[0007] Therefore, a portable neural signal collection device is needed, which has a larger throughput of neural signal collection, is more convenient and comfortable to use, and is suitable for free activity scenes. SUMMARY

[0008] The present application provides a high-throughput neural signal collection and processing device, which can transmit high-throughput neural signals through relatively light wires, making the device more convenient and comfortable.

[0009] The present application provides a high-throughput neural signal collection and processing device, which includes a front end and a rear end, the front end includes a neural signal collection module, an FPGA module and a serializer module;

[0010] The neural signal collection module is used for collecting high-throughput raw neural signals;

[0011] The FPGA module is connected with the neural signal collection module, and the FPGA module is used for processing the raw neural signals and constructing a parallel neural data set based on the processing results and the high-throughput raw neural signals;

[0012] The serializer module is connected with the FPGA module, and the serializer module is used for converting the parallel neural data set into high-speed serial data;

[0013] The rear end is connected with the serializer module through a wire, and the rear end is used for converting the high-speed serial data into parallel signals and sending the parallel signals to a PC end.

[0014] Preferably, the serializer module includes a serializer chip, a power / data adjustment unit and a first voltage adjustment unit;

[0015] The serializer chip is connected with the FPGA module, and the serializer chip is used for converting the parallel neural data set into high-speed serial data;

[0016] The power / data adjustment unit is connected with the serializer chip, and the power / data adjustment module is used for sending the high-speed serial data to the rear end through the wire, and is also used for receiving a voltage signal through the wire;

[0017] The first voltage adjustment unit is connected with the power / data adjustment unit, the serializer chip and the FPGA module respectively, and is configured to supply power to the serializer chip and the FPGA module based on the received voltage signal.

[0018] Preferably, the back end comprises a deserializer module and a USB device.

[0019] The deserializer module is connected with the serializer module through wires, and is configured to convert serial data into parallel signals and transmit voltage signals to the serializer module through the wires.

[0020] The USB device is connected with the deserializer module, and is configured to send the parallel signals to a PC end and output voltage signals obtained from the PC end to the deserializer module.

[0021] Preferably, the deserializer module comprises a deserializer chip and a second voltage adjustment unit.

[0022] The deserializer chip is connected with the power / data adjustment unit through wires, and is paired with the serializer chip, and is configured to convert high-speed serial data into parallel signals.

[0023] The second voltage adjustment unit is connected with the USB device, the deserializer chip and the power / data adjustment module respectively, and is configured to supply power to the deserializer chip based on the received voltage signal and transmit voltage signals to the power / data adjustment module through wires.

[0024] Preferably, the neural signal acquisition module comprises a plurality of stacked acquisition chips, each of which is connected with a multi-channel recording electrode, and is configured to receive high-throughput raw neural signals from the multi-channel recording electrode and send the acquired high-throughput raw neural signals to the FPGA module through a standard SPI bus.

[0025] Preferably, the acquisition chip is connected with the multi-channel recording electrode, and is configured to amplify, filter and digitize the acquired electrical signals to obtain high-throughput raw neural signals.

[0026] Preferably, the acquisition chip is further configured to synchronously acquire other data, which includes one or more combinations of acceleration signals, temperature signals and impedance signals.

[0027] Preferably, the FPGA module comprises a neural signal acquisition communication unit, a neural signal processing unit, a logic controller unit and a data parallel path unit.

[0028] The neural signal acquisition communication unit is connected with the neural signal acquisition module, and the neural signal acquisition communication unit is used for receiving high-throughput original neural signals and configuring the neural signal acquisition module;

[0029] The neural signal processing unit is connected with the neural signal acquisition communication unit, and the neural signal processing unit is used for carrying out digital filtering, feature extraction and decoding processing on the high-throughput original neural signals and sending the processing results to the logic controller unit;

[0030] The logic controller unit is connected with the neural signal acquisition communication unit and the neural signal processing unit respectively, and the logic controller unit is used for converting the processing results and the high-throughput original neural signals into parallel neural data sets suitable for the serializer module;

[0031] The data parallel communication unit is connected with the logic controller unit and the serializer module respectively, and the data parallel communication module is used for sending the parallel neural data sets to the serializer module.

[0032] Preferably, the FPGA module further comprises a control instruction communication unit connected with the logic controller unit and the serializer module respectively, and the control instruction communication unit is used for receiving control instructions from the serializer module and sending other data to the serializer module, wherein the other data is non-neural signal data collected by the neural signal acquisition module.

[0033] In another aspect, the application further provides a method for arranging a high-throughput neural signal acquisition and processing device, comprising:

[0034] The neural signal acquisition module, the FPGA module and the serializer module are packaged on a front-end circuit board;

[0035] The deserializer module and the USB device are packaged on a rear-end circuit board;

[0036] The front-end circuit board is arranged on the head of the collected subject, and the neural signal acquisition module in the front-end circuit board is electrically connected with the recording electrode implanted in the brain;

[0037] The serializer module in the front-end circuit board is electrically connected with the deserializer module in the rear-end circuit board through a wire, and the USB device in the rear-end circuit board is electrically connected with a PC end and a power supply respectively.

[0038] Compared with the prior art, the application has the following beneficial effects:

[0039] The FPGA module is used for processing high-throughput original neural signals in the front end to reduce the subsequent operation amount of the PC end and improve the operation efficiency.

[0040] The application can transmit high-flux neural data sets to the rear end through a single cable or fewer cables by arranging a serializer at the front end, converting parallel neural data sets into high-speed serial data through the serializer, achieving high-flux transmission while greatly reducing weight and volume, and making the high-flux neural signal acquisition and processing device convenient and flexible. BRIEF DESCRIPTION OF DRAWINGS

[0041] Fig. 1 is a schematic diagram of a high-flux neural signal acquisition and processing device provided by an embodiment of the application;

[0042] Fig. 2 is a schematic diagram of an FPGA module provided by an embodiment of the application;

[0043] Fig. 3 is a schematic diagram of a serializer module provided by an embodiment of the application;

[0044] Fig. 4 is a schematic diagram of a rear end provided by an embodiment of the application. DETAILED DESCRIPTION

[0045] The application will be further described in detail below with reference to the drawings and embodiments, and it should be pointed out that the following embodiments are intended to facilitate the understanding of the application and do not limit the application in any way.

[0046] To solve the problems of large weight and size, poor convenience, and low flux of the neural signal acquisition and processing device for brain-computer in the prior art, an embodiment of the application adds a serializer module at the front end to convert high-flux parallel neural data sets into high-speed serial data, so that high-flux neural data sets can be sent to the rear end through a single cable, and the high-flux neural data sets are converted into parallel signals by the rear end and sent to the PC end, thereby realizing convenient sending of high-flux neural data sets to the PC end and reducing the weight and size of the neural signal acquisition and processing device.

[0047] An embodiment of the application provides a high-flux neural signal acquisition and processing device, as shown in Fig. 1, which comprises a front end and a rear end. The front end is arranged at the brain position of a detected subject and is connected with recording electrodes implanted in the brain, used for receiving and processing acquired neural signals and converting the neural signals into high-speed serial data to realize convenient transmission.

[0048] The front end provided by an embodiment of the application comprises a neural signal acquisition module, an FPGA module, and a serializer module. The neural signal acquisition module provided by an embodiment of the application is used for continuously acquiring high-flux original neural signals. In the acquisition process, weak electrical signals are amplified, filtered, and digitized to obtain high-flux original neural signals.

[0049] In an embodiment, the neural signal acquisition module is stacked by a plurality of acquisition chips, each of which contains a set of low-noise amplifiers with programmable bandwidth, and the circuit architecture of the acquisition chip combines the amplifiers, filters, 16-bit ADCs and impedance measurements on the acquisition chip, each of which is directly connected to a plurality of recording electrodes of the channel and outputs the acquired high-throughput raw neural signals through a standard SPI bus.

[0050] In an embodiment, the acquisition chip is an RHD2000 electrophysiological amplifier chip.

[0051] The FPGA module is connected to the neural signal acquisition module, and the FPGA module can directly process the acquired high-throughput raw neural signals at the front end to reduce the computing load of the PC end, and convert the processing results and the acquired high-throughput raw neural signals to obtain a parallel neural data set matched with the parallel interface of the serializer module.

[0052] The FPGA module is also used to receive control instructions from the serializer, process the high-throughput neural signals through the control instructions, and send the control instructions to the neural signal acquisition module, and the neural signal acquisition module acquires high-throughput raw neural signals and other data based on the control instructions, the other data including one or a combination of acceleration signals, temperature signals and impedance signals, and the FPGA module sends the received other data to the serializer module.

[0053] In an embodiment, as shown in FIG. 2, the FPGA module includes a neural signal acquisition communication unit, a neural signal processing unit, a logic controller unit and a data parallel path unit.

[0054] The neural signal acquisition communication unit is connected to the neural signal acquisition module, and is used to read the high-throughput raw neural signals and other data through the SPI interface, and send the control instructions to the neural signal acquisition device, and is also used to configure the RHD2000 neural signal acquisition chip of the neural signal acquisition module.

[0055] The neural signal processing unit provided by the embodiment of the present application is connected with the neural signal acquisition communication unit and the logic controller unit, the neural signal processing unit is used for carrying out digital filtering, feature extraction and decoding processing on the high-throughput original neural signal, and the processing result is sent to the logic controller unit, wherein the digital filtering includes low-pass filtering, high-pass filtering and band-stop filtering, the field potential signal is obtained through the low-pass filtering, the high-frequency neural signal is obtained through the high-pass filtering, and the power frequency interference is removed through the band-stop filtering, the feature extraction includes calculating the power spectrum of the signal, calculating the high-order differential signal, calculating the sharp potential signal through the threshold method, calculating the sharp potential band power signal, etc., the decoding utilizes a linear algorithm or a nonlinear algorithm, in an embodiment, the linear algorithm is a Kalman filter or the nonlinear algorithm is a neural network, so as to realize the mapping from the high-throughput neural signal to the decoding target.

[0056] The logic control unit provided by the embodiment of the present application is connected with the neural signal acquisition communication unit and the neural signal processing unit, the logic control unit is used for converting the processing result output by the neural signal processing unit and the high-throughput original neural signal into a parallel neural data set suitable for the serializer module, the parallel neural data set is suitable for the parallel interface of the serializer module, the logic control unit is also used for sending the control instruction received through the control instruction communication unit to the neural signal acquisition communication unit and the neural signal processing unit respectively, and is also used for sending the received other data to the serializer module through the control instruction communication unit.

[0057] The data parallel communication unit provided by the embodiment of the present application is connected with the logic controller unit and the serializer module, the data parallel communication unit is used for sending the parallel neural data set to the serializer module.

[0058] The front end provided by the embodiment of the present application further includes a clock module and a power module, the clock module provides a reference clock for the FPGA. The power module is from the serializer module, and provides power supply for the FPGA circuit.

[0059] The serializer module provided by the embodiment of the present application is connected with the FPGA module, the serializer module is used for converting the parallel neural data set into high-speed serial data, so that the high-throughput neural signal can be sent to the back end through a single cable.

[0060] As shown in FIG. 3, the serializer module provided by the embodiment of the present application includes a serializer chip, a power / data adjustment unit and a first voltage adjustment unit, the serializer chip is connected with the control instruction communication unit and the data parallel communication unit of the FPGA module, the serializer chip is used for converting the parallel neural data set received through the parallel interface into high-speed serial data, and transmitting the high-speed serial data and other data through the corresponding channels of the serial port to the power / data adjustment unit, and is also used for sending the received control instruction to the control instruction communication unit.

[0061] In a specific embodiment, the serializer chip provided by the specific embodiment of the present application adopts a MAX9271 serializer chip, which can drive a 50Ω coaxial cable or a 100Ω shielded twisted pair (STP) cable. The chip can achieve a highly reliable 1.5Gbps data transmission rate (3125 channels of raw neural signals can be transmitted simultaneously according to a 30kHz sampling rate and a 16-bit sampling precision), while providing an additional UART / I 2 C control channel, UART up to 9.6kbps to 1Mbps, I 2 C mode up to 400kbps.

[0062] The power / data adjustment unit provided by the specific embodiment of the present application is connected with the serializer chip and the backend respectively, and is connected with the first voltage adjustment unit. The power / data adjustment unit is used to send control instructions to the serializer chip, receive high-speed serial data, and send the high-speed serial data to the backend through a wire, which is a coaxial cable or a twisted pair cable. The power / data adjustment unit is also used to send a voltage signal of the wire to the first voltage adjustment unit.

[0063] The first voltage adjustment unit provided by the specific embodiment of the present application is connected with the power / data adjustment unit, the serializer chip and the FPGA module respectively. The first voltage adjustment unit is used to supply power to the serializer chip based on the received voltage signal and to the FPGA module through the power module.

[0064] The backend provided by the specific embodiment of the present application is connected with the frontend through a wire. Since the high-speed serial data transmitted by the frontend cannot be directly applied, the specific embodiment of the present application configures a deserializer module in the backend to decode the high-speed serial data into parallel signals and send the parallel signals to a PC end.

[0065] As shown in FIG. 4, the backend provided by the specific embodiment of the present application includes a deserializer module and a USB device.

[0066] The deserializer module is connected with the power / data adjustment unit of the serializer module through a wire. The deserializer module is used to receive serial data and other data, convert the serial data into parallel signals, and send control instructions and voltage signals to the power / data adjustment unit through the wire.

[0067] The deserializer module provided by the embodiment of the application comprises a deserializer chip and a second voltage adjusting unit, wherein the deserializer chip is matched with a serializer chip, is used for converting a high-speed serial signal into a parallel signal, and is used for sending the parallel signal and other received data to a USB device, and is used for sending a received control instruction to a power / data adjusting unit through a wire; the second voltage adjusting unit is connected with the USB device, the deserializer chip and the power / data adjusting module, and is used for supplying power to the deserializer chip based on a received voltage signal and transmitting the voltage signal to the power / data adjusting module through a wire.

[0068] In an embodiment, the deserializer chip provided by the embodiment of the application is a MAX9272 chip matched with a MAX9271.

[0069] The USB device provided by the embodiment of the application comprises a USB controller chip and a USB connector, receives a parallel signal output by the deserializer module, and directly transmits the parallel signal to a PC through a USB interface, wherein the PC is a personal computer in an embodiment.

[0070] The embodiment of the application further provides a layout method of the high-throughput neural signal acquisition and processing device, comprising:

[0071] The neural signal acquisition module, the FPGA module and the serializer module provided by the embodiment of the application are packaged on a front-end circuit board.

[0072] The deserializer module and the USB device provided by the embodiment of the application are packaged on a back-end circuit board.

[0073] The front-end circuit board provided by the embodiment of the application is arranged on a head of a collected subject, and the neural signal acquisition module in the front-end circuit board is electrically connected with a recording electrode implanted in the brain.

[0074] The serializer module in the front-end circuit board is electrically connected with the deserializer module in the back-end circuit board through a wire, and the USB device in the back-end circuit board is electrically connected with an information processing device and a power supply respectively.

[0075] The application adopts a configurable neural signal processing unit based on FPGA, realizes the processing of neural signals on the board, can transmit the original signals and the processed neural signals together, and improves the flexibility of the neural signal acquisition device. At the same time, the high-speed serial signal transmission neural signal can greatly reduce the size of the neural signal acquisition device. The front end of the high-throughput neural signal acquisition and processing device includes a neural signal acquisition module, an FPGA module and a serializer module, which can be packaged on the same small-sized circuit board and placed on the head of the collected main body, electrically connected with the joint of the implanted electrode in the brain, and realizes the miniaturized head-mounted acquisition kit. The rear end of the high-throughput neural signal acquisition and processing device includes a deserializer module and a USB device, which can be packaged on the same small-sized circuit board and electrically connected with the personal computer through the USB interface. The size of the whole circuit is similar to that of a USB flash disk, which can be easily inserted into any personal computer. The front end and the rear end of the high-throughput neural signal acquisition and processing device are connected by coaxial cable or twisted pair, which greatly reduces the size and weight of the transmission line. Taking the twisted pair as an example, in an embodiment, the diameter is only 420 microns, and the weight is only 1 gram per meter, which can reduce the burden of the cable. Further, the wire can be configured with a reverser, which can reduce part of the weight and prevent the wire from being knotted due to the rotation of the collected main body.

[0076] The above embodiments have described the technical solutions and beneficial effects of the application in detail. It should be understood that the above description is only a specific embodiment of the application and is not used to limit the application. Any modification, supplement and equivalent replacement made within the principle range of the application should be included in the protection range of the application.

Claims

1. A high-throughput neural signal acquisition and processing device, characterized in that, The device comprises a front end and a back end, the front end comprises a neural signal acquisition module, an FPGA module and a serializer module; The neural signal acquisition module is used for acquiring high-throughput raw neural signals; The FPGA module is connected with the neural signal acquisition module, and the FPGA module is used for processing the raw neural signals and constructing a parallel neural data set based on the processing result and the high-throughput raw neural signals; The serializer module is connected with the FPGA module, and the serializer module is used for converting the parallel neural data set into high-speed serial data; The back end is connected with the serializer module through wires, and the back end is used for converting the high-speed serial data into parallel signals and sending the parallel signals to a PC end.

2. The high-throughput neural signal acquisition and processing device of claim 1, wherein, The serializer module comprises a serializer chip, a power / data adjustment unit and a first voltage adjustment unit; The serializer chip is connected with the FPGA module, and the serializer chip is used for converting the parallel neural data set into high-speed serial data; The power / data adjustment unit is connected with the serializer chip, and the power / data adjustment unit is used for sending the high-speed serial data to the back end through wires and receiving voltage signals through wires; The first voltage adjustment unit is connected with the power / data adjustment unit, the serializer chip and the FPGA module respectively, and the first voltage adjustment unit is used for supplying power to the serializer chip and the FPGA module based on the received voltage signals.

3. The high-throughput neural signal acquisition and processing device of claims 1 and 2, wherein, The back end comprises a deserializer module and a USB device; The deserializer module is connected with the serializer module through wires, and the deserializer module is used for converting the serial data into parallel signals and transmitting voltage signals to the serializer module through wires; The USB device is connected with the deserializer module, and the USB device is used for sending the parallel signals to the PC end and outputting voltage signals obtained from the PC end to the deserializer module.

4. The high-throughput neural signal acquisition and processing device of claim 3, wherein, The deserializer module comprises a deserializer chip and a second voltage adjustment unit; The deserializer chip is connected with the power / data adjustment unit through wires, and the deserializer chip is paired with the serializer chip, and the deserializer chip is used for converting the high-speed serial data into parallel signals; The second voltage adjustment unit is connected with the USB device, the deserializer chip and the power / data adjustment module respectively, and the second voltage adjustment unit is used for supplying power to the deserializer chip based on the received voltage signals and transmitting voltage signals to the power / data adjustment module through wires.

5. The high-throughput neural signal acquisition and processing device of claim 1, wherein, The neural signal acquisition module comprises a plurality of stacked acquisition chips, each of which is connected with a multi-channel recording electrode, and the acquisition chip is used for receiving high-throughput raw neural signals from the multi-channel recording electrode and sending the acquired high-throughput raw neural signals to the FPGA module through a standard SPI bus.

6. The high-throughput neural signal acquisition and processing device of claim 5, wherein, The acquisition chip is connected with the multi-channel recording electrode, and the acquisition chip is used for amplifying, filtering and digitizing the acquired electrical signals to obtain high-throughput raw neural signals.

7. The high-throughput neural signal acquisition and processing device of claim 5, wherein, The acquisition chip is also used for synchronously acquiring other data, and the other data comprises one or more combinations of acceleration signals, temperature signals and impedance signals.

8. The high-throughput neural signal acquisition and processing device of claim 1, wherein, The FPGA module comprises a neural signal acquisition communication unit, a neural signal processing unit, a logic controller unit and a data parallel channel unit. The neural signal acquisition communication unit is connected with the neural signal acquisition module, and is configured to receive high-throughput raw neural signals and configure the neural signal acquisition module. The neural signal processing unit is connected with the neural signal acquisition communication unit, and is configured to perform digital filtering, feature extraction and decoding processing on the high-throughput raw neural signals, and send the processing results to the logic controller unit. The logic controller unit is connected with the neural signal acquisition communication unit and the neural signal processing unit, and is configured to convert the processing results and the high-throughput raw neural signals into parallel neural data sets suitable for the serializer module. The data parallel communication unit is connected with the logic controller unit and the serializer module, and is configured to send the parallel neural data sets to the serializer module.

9. The high-throughput neural signal acquisition and processing device of claim 8, wherein, The FPGA module further comprises a control instruction communication unit connected with the logic controller unit and the serializer module, and configured to receive control instructions from the serializer module and send other data to the serializer module, wherein the other data is non-neural signal data collected by the neural signal acquisition module.

10. A method of arranging a high-throughput neural signal acquisition and processing device, characterized in that, The neural signal acquisition module, the FPGA module and the serializer module are packaged on a front-end circuit board; The deserializer module and the USB device are packaged on a rear-end circuit board; The front-end circuit board is arranged on the head of the collected subject, and the neural signal acquisition module in the front-end circuit board is electrically connected with the recording electrode implanted in the brain; The serializer module in the front-end circuit board is electrically connected with the deserializer module in the rear-end circuit board through a wire, and the USB device in the rear-end circuit board is electrically connected with the PC end and the power supply, respectively. ​

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