Hybrid-passivated back-contact battery having specific heavily-doped region, manufacturing therefor and use thereof

Abstract

The embodiments of the present disclosure belong to the technical field of hybrid-passivated back-contact batteries, and particularly relate to a hybrid-passivated back-contact battery having a specific heavily-doped region, manufacturing therefor and the use thereof. The battery comprises a first semiconductor layer and a second semiconductor layer; an N-type doped polycrystalline silicon layer is provided with a heavily-doped region, the heavily-doped region being located on the inner side of a first semiconductor opening region and covering a position area where the first semiconductor opening region is located, and the width W1 of the heavily-doped region being greater than the width W2 of the first semiconductor opening region; the ratio of the depth of the heavily-doped region to the thickness of an intrinsic amorphous silicon layer and the thickness of a tunneling oxide layer is 20-100:3-8:1; and the ratio of the surface doping index of a lightly-doped region, the surface doping index of the heavily-doped region and the surface doping index of a P-type doped silicon layer is 1:10-90:10-100. The embodiments of the present disclosure can ameliorate the series resistance of batteries, reduce the contact resistance of emitters and the dark saturation currents of emitter regions, and increase fill factors, short-circuit currents and open-circuit voltages, thus improving conversion efficiency of batteries.

Description

Junction passivated back contact cell with specific heavily doped region and preparation and application

[0001] Cross-reference to related applications

[0002] This application claims priority to the Chinese patent application No. 202410451604.1, filed on April 16, 2024, entitled “Junction passivated back contact cell with specific heavily doped region and preparation and application”, the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The present disclosure belongs to the technical field of junction passivated back contact cell, and particularly relates to a junction passivated back contact cell with specific heavily doped region and preparation and application. BACKGROUND

[0004] Compared with a conventional heterojunction cell, a junction passivated back contact cell is provided in the art, which includes an N-type doped silicon substrate having a light-receiving surface and a back surface, a first semiconductor layer and a second semiconductor layer disposed on the back surface, the second semiconductor layer including an intrinsic silicon layer and a P-type doped silicon layer disposed in sequence along a direction perpendicular to the back surface outward, and the first semiconductor layer including a tunneling oxide layer and an N-type doped polysilicon layer disposed in sequence along a direction perpendicular to the back surface outward. Compared with the conventional heterojunction cell, the junction passivated back contact cell can significantly improve the fill factor FF, the photoelectric conversion efficiency, and the yield, and the preparation method is relatively simple, which can be industrialized and is conducive to improving the production efficiency. In order to further improve the industrial value, the cell conversion efficiency of the junction passivated back contact cell with the new structure needs to be further improved.

[0005] It should be noted that this part of the present disclosure only provides background technology related to the present disclosure, and does not necessarily constitute prior art or public knowledge. SUMMARY

[0006] The purpose of the present disclosure is to overcome the defect that the cell conversion efficiency of the junction passivated back contact cell needs to be further improved in the prior art, and to provide a junction passivated back contact cell with specific heavily doped region and preparation and application. The junction passivated back contact cell can improve the series resistance of the cell without damaging the tunneling polysilicon layer structure of the first semiconductor layer, reduce the emitter contact resistance and the emitter area dark saturation current, improve the fill factor, the short-circuit current and the open-circuit voltage, and thus improve the cell conversion efficiency.

[0007] To achieve the above object, the embodiments of the present disclosure provide a back contact cell with a specific heavily doped region, comprising a silicon wafer with a front surface and a back surface, a first semiconductor layer and a second semiconductor layer arranged alternately on the back surface of the silicon wafer, the second semiconductor layer extending outward at both ends to cover part of the back surface of the adjacent first semiconductor layer, and leaving a first semiconductor opening area on the back surface of the first semiconductor layer without covering the second semiconductor layer, a second semiconductor opening area formed between the adjacent first semiconductor layers, and the second semiconductor opening area arranged in a spaced manner with the first semiconductor opening area, wherein the first semiconductor layer comprises a tunneling oxide layer and an N-type doped polysilicon layer arranged outward in sequence along the silicon wafer, the second semiconductor layer comprises an intrinsic amorphous silicon layer and a P-type doped silicon layer arranged outward in sequence along the silicon wafer, the N-type doped polysilicon layer has a heavily doped region, the heavily doped region is located on the inner side of the first semiconductor opening area and covers the position area of the first semiconductor opening area, the width W1 of the heavily doped region is greater than the width W2 of the first semiconductor opening area, the width W1 of the heavily doped region is 20%-50% of the width of the N-type doped polysilicon layer, the part of the N-type doped polysilicon layer between the outer edge of the heavily doped region and the adjacent outer edge of the corresponding first semiconductor layer is a lightly doped region, the depth of the heavily doped region is 25%-90% of the thickness of the lightly doped region, the ratio of the depth of the heavily doped region to the thickness of the intrinsic amorphous silicon layer and the thickness of the tunneling oxide layer is 20-100:3-8:1, and the ratio of the surface doping index of the lightly doped region to the surface doping index of the heavily doped region and the P-type doped silicon layer is 1:10-90:10-100, wherein the surface doping index refers to the ratio of the effective doping concentration to the thickness of the corresponding doped region or doped layer.

[0008] In some preferred embodiments of the present disclosure, the effective doping concentration of the heavily doped region is 1.4-40 times the effective doping concentration of the lightly doped region.

[0009] In some preferred embodiments of the present disclosure, the depth of the heavily doped region is 30-100 nm, and the effective doping concentration of the heavily doped region is 7×10 19 / cm 3 —5×10 20 / cm 3 .

[0010] In some preferred embodiments of the present disclosure, the width W1 of the heavily doped region is 200-500 μm, and the width W2 of the first semiconductor opening area is 100-300 μm.

[0011] In some preferred embodiments of the present disclosure, the width W3 of the second semiconductor opening area is 300-700 μm.

[0012] In some preferred embodiments of the present disclosure, the light doped region has a thickness of 80-200 nm and an effective doping concentration of 8x10 18 / cm 3 —5x10 19 / cm 3 .

[0013] In some preferred embodiments of the present disclosure, the P-type doped silicon layer has a thickness of 10-15 nm and an effective doping concentration of 5x10 19 / cm 3 —3x10 20 / cm 3 .

[0014] In some preferred embodiments of the present disclosure, the tunneling oxide layer has a thickness of 1-2 nm and the intrinsic amorphous silicon layer has a thickness of 6-8 nm.

[0015] In some preferred embodiments of the present disclosure, a mask layer is provided between the first semiconductor layer and the second semiconductor layer in the region between the first semiconductor opening region and the second semiconductor opening region.

[0016] In some preferred embodiments of the present disclosure, the portion of the silicon wafer at the position of the second semiconductor opening region is a textured surface, and the portion of the silicon wafer at the position corresponding to the first semiconductor layer is a polished surface, and the joint passivated back contact cell further comprises a metal electrode and a conductive film layer arranged on the outer surfaces of the first semiconductor layer and the second semiconductor layer, the metal electrode is arranged on the outer surface of the respective conductive film layer of the second semiconductor opening region and the first semiconductor opening region; a corresponding portion of the conductive film layer at the interface between the textured surface and the polished surface is provided with an isolation groove, and the width WgL of the isolation groove is 30-200 μm.

[0017] Embodiments of the present disclosure provide a preparation method of a joint passivated back contact cell configured to prepare the joint passivated back contact cell with a specific heavily doped region of the first aspect, and the preparation method of the joint passivated back contact cell comprises the following steps:

[0018] S01, providing a silicon wafer;

[0019] S02, forming a first semiconductor layer on the back surface of the silicon wafer, and naturally forming a phosphosilicate glass layer on the back surface;

[0020] S03, performing selective heavy doping treatment on the preset region of the back surface obtained in S02 to form a heavily doped region; the selective heavy doping treatment includes laser doping method;

[0021] S04, removing the phosphosilicate glass layer by acid washing, and forming a first mask layer on the back surface after back washing;

[0022] S05, performing a first opening on the back surface obtained in S04, removing part of the first mask layer and corresponding part of the first semiconductor layer, and forming second semiconductor opening regions arranged alternately; the direction of the first opening is parallel to the direction of the selective heavy doping treatment;

[0023] S06, then performing texturing and cleaning, simultaneously removing the first semiconductor layer in the second semiconductor opening regions, and then removing the remaining first mask layer;

[0024] S07, then sequentially depositing a passivation layer and an anti-reflection layer on the front surface of the silicon wafer, and depositing a second semiconductor layer on the back surface;

[0025] S08, performing a second opening in the position corresponding to the heavy doping region on the back surface obtained in S07, removing the second semiconductor layer, and forming first semiconductor opening regions arranged alternately with the second semiconductor opening regions; the direction of the second opening is parallel to the direction of the selective heavy doping treatment.

[0026] In some preferred embodiments of the present disclosure, the laser doping method uses a flat-top picosecond laser.

[0027] Optionally, the flat-top picosecond laser is a flat-top picosecond green laser or a flat-top picosecond ultraviolet laser.

[0028] Optionally, the conditions of the laser doping method include: the control power is 3kW-20kW, and the frequency is 200kHz-1000kHz.

[0029] In some preferred embodiments of the present disclosure, the preparation method of the joint passivation back contact cell further comprises:

[0030] S09, removing the oxide layer in the first semiconductor opening region by cleaning; then depositing a conductive film layer on the back surface;

[0031] S10, performing a third opening on the conductive film layer between the first semiconductor opening region and the second semiconductor opening region, and forming an isolation groove;

[0032] S11, forming a metal electrode on the back surface obtained in S10.

[0033] Embodiments of the present disclosure provide a cell assembly comprising the joint passivation back contact cell with a specific heavy doping region according to the first aspect. Advantages:

[0034] Embodiments of the present disclosure, through the above technical solutions, especially by arranging a specific heavy doping region on the N-type doped polysilicon layer in the joint passivation interdigital structure, the width, depth and effective doping concentration of the heavy doping region are set in association with other specific layers and in accordance with the aforementioned specific relationship, so that an appropriate lateral n-p junction is formed at the junction of the heavy doping region and the light doping region,+ The high-low junction and the location of the high-low junction are suitable, and the tunneling polycrystalline layer structure does not damage the first semiconductor layer, so that the series resistance of the battery is improved, the emitter contact resistance and the dark saturation current of the emitter region are reduced, the fill factor, the short-circuit current and the open-circuit voltage are improved, and the battery conversion efficiency is improved. In an embodiment, the dark current iRev2 of the battery provided by the embodiment of the present disclosure can be 0.5 A, while the dark current iRev2 in the conventional joint passivation back contact battery electrical performance index is about 10 A. Under the same conditions, if the ratio of the depth of the heavily doped region to the thickness of the intrinsic amorphous silicon layer and the thickness of the tunneling oxide layer is too large, the tunneling polycrystalline layer (i.e. the first semiconductor layer) will be damaged, which will destroy the passivation structure of the battery. If the ratio is too small, the high-low junction cannot be formed in the heavily doped junction region, which will not improve the dark current of the battery. Under the same conditions, if the ratio of the surface doping index of the lightly doped region to the heavily doped region and the P-type doped silicon layer is too large, the battery series resistance will not change due to insufficient heavy doping concentration, which will affect the short-circuit current of the battery. If the ratio is too small, the open-circuit voltage and the fill factor of the battery will not be significantly improved due to insufficient heavy doping depth.

[0035] Furthermore, the embodiment of the present disclosure particularly sets the heavily doped region inside the first semiconductor opening region and covers the location area of the first semiconductor opening region, and the width W1 of the heavily doped region is greater than the width W2 of the first semiconductor opening region and occupies a suitable proportion, which can maximize the reduction of the emitter contact resistance and the improvement of the series resistance of the battery, thereby sufficiently improving the battery conversion efficiency. Under the same conditions, if the width W1 of the heavily doped region is too large in the proportion of the N-type doped polysilicon layer, the heavily / lightly doped junction region cannot be formed due to the overflow of the heavily doped region to the second semiconductor layer, and if the proportion is too small, the heavily doped region is smaller than the first semiconductor opening region, which cannot maximize the effect of improving the series resistance of the battery.

[0036] In the preparation method of the embodiment of the present disclosure, in the joint passivation interdigital structure process, a layer of phosphorus-rich PSG layer naturally formed in the process of forming the first semiconductor layer is used as a doping source. By using laser doping method under high-frequency laser pulse, the phosphorus atoms in the PSG layer are doped into the suitable area of the N-type doped polysilicon layer, so as to achieve the purpose of diffusion promotion of doping atoms, so that the phosphorus atom concentration of the suitable area of the N-type doped polysilicon layer is improved, and the structure of the specific structure setting of the lightly doped region and the heavily doped region is formed. The heavily doped region can obtain the specific relationship with other specific layers, which is beneficial to reducing the contact resistance of the semiconductor, thereby improving the series resistance of the battery, and effectively improving the battery conversion efficiency.

[0037] In the preferred solution, the selective heavy doping treatment adopts a laser doping method, in particular a flat-top picosecond laser, which has appropriate energy and does not damage the N-type doped polysilicon layer, and the heavy doping interface formed is relatively uniform as a whole, which can be inscribed by a flat-top laser (circular or square spot overlap arrangement), and the interface width can be completed by splicing multiple lines; appropriate laser power and frequency are used to make more phosphorus atoms be appropriately doped into the N-type doped polysilicon layer, which is conducive to improving the phosphorus doping concentration of the heavy doping region of the N-type doped polysilicon layer to an appropriate range under the premise of ensuring that the first semiconductor layer (i.e., the tunneling polysilicon layer) is not damaged, thereby effectively improving the cell conversion efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0038] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings needed to be used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some of the embodiments of the present disclosure, and therefore should not be considered as limiting the scope. For those skilled in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.

[0039] FIG. 1 is a structural schematic diagram of a joint passivation back contact cell with a specific heavy doping region according to the present disclosure.

[0040] FIG. 2 is a process flow diagram of the preparation method according to the present disclosure.

[0041] Legend of reference signs 1, silicon wafer, 2, tunneling oxide layer, 3, N-type doped polysilicon layer, 4, heavy doping region, 5, intrinsic amorphous silicon layer, 6, P-type doped amorphous silicon layer, 7, transparent conductive film layer, 8, passivation layer, 9, antireflection layer. DETAILED DESCRIPTION

[0042] In the present disclosure, the terms "first" and "second" are only configured to describe purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with "first" and "second" can explicitly or implicitly include one or more of the features. In the description of the present disclosure, the meaning of "a plurality of" is two or more, unless otherwise explicitly specified.

[0043] In the present disclosure, unless otherwise expressly specified or limited, when a first feature is "above" or "below" a second feature, it may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Furthermore, when a first feature is "above," "above," or "above" a second feature, it may mean that the first feature is directly above or diagonally above the second feature, or simply means that the first feature is at a higher level than the second feature. When a first feature is "below," "below," or "below" a second feature, it may mean that the first feature is directly below or diagonally below the second feature, or simply means that the first feature is at a lower level than the second feature.

[0044] The endpoints and any values ​​of the ranges disclosed herein are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges or values. For numerical ranges, the endpoint values ​​of each range, the endpoint values ​​of each range and the individual point values, and the individual point values ​​can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed herein. Among them, the terms "optional" and "optional" all mean that they may be included or not (or may be present or not).

[0045] In the embodiments of the present disclosure, the front side refers to the light-receiving side of the silicon wafer, and the back side refers to the opposite back side of the light-receiving side. In the embodiments of the present disclosure, the side close to the silicon wafer is generally considered as the inside, and the side far from the silicon wafer is generally considered as the outside.

[0046] The embodiment of the present disclosure provides a combined passivation back contact battery with a specific heavily doped region, comprising a silicon wafer having a front side and a back side, a first semiconductor layer and a second semiconductor layer alternately arranged on the back side of the silicon wafer, the two ends of the second semiconductor layer respectively extending outward to cover the portion of the back side of the adjacent first semiconductor layer, and leaving a first semiconductor opening region on the back side of the first semiconductor layer that does not cover the second semiconductor layer, a second semiconductor opening region is formed between adjacent first semiconductor layers, and the second semiconductor opening region is arranged at intervals from the first semiconductor opening region, wherein the first semiconductor layer comprises a tunneling oxide layer and an N-type doped polysilicon layer, the second semiconductor layer includes an intrinsic amorphous silicon layer and a P-type doped silicon layer arranged in sequence along the silicon wafer outward, the N-type doped polysilicon layer has a heavily doped region, the heavily doped region is located on the inner side of the first semiconductor opening region and covers the area where the first semiconductor opening region is located, and the width W1 of the heavily doped region is greater than the width W2 of the first semiconductor opening region, the width W1 of the heavily doped region is 20%-50% of the width of the N-type doped polysilicon layer, preferably 28%-38%; the portion of the N-type doped polysilicon layer between the outer edge in the width direction of the heavily doped region and the adjacent outer edge of the corresponding first semiconductor layer is a lightly doped region.

[0047] The depth of the heavily doped region is 25%-90% of the thickness of the lightly doped region, preferably 35%-75%, further preferably 60%-75%.

[0048] The ratio of the depth of the heavily doped region to the thickness of the intrinsic amorphous silicon layer to the thickness of the tunneling oxide layer is 20-100:3-8:1, preferably 20-50:3-8:1, further preferably 25-50:4.5-8:1.

[0049] The ratio of the surface doping index of the lightly doped region to the surface doping index of the heavily doped region to the surface doping index of the P-type doped silicon layer is 1:10-90:10-100, preferably 1:10-50:20-100, further preferably 1:10-20:60-85, wherein the surface doping index refers to the ratio of the effective doping concentration to the thickness of the corresponding doped region or doped layer. The unit of the effective doping concentration is / cm 3 , and the unit of the thickness is nm.

[0050] In the embodiments of the present disclosure, it can be understood that the effective doping concentration of the heavily doped region is greater than the effective doping concentration of the lightly doped region. In some preferred embodiments of the present disclosure, the effective doping concentration of the heavily doped region is 1.4-40 times, more preferably 5-30 times, further preferably 5-10 times the effective doping concentration of the lightly doped region. By using the heavily doped region and the lightly doped region with the preferred appropriate doping concentration multiple, an appropriate n + / n high-low junction can be formed at the junction of the heavily doped region and the lightly doped region, which is more conducive to reducing the emitter contact resistance and the dark current of the emitter, thereby improving the conversion efficiency of the cell.

[0051] In some preferred embodiments of the embodiments of the present disclosure, the depth of the heavily doped region is 30-100 nm, preferably 50-100 nm, further preferably 60-100 nm, and the effective doping concentration of the heavily doped region is 7x10 19 / cm 3 -5x10 20 / cm 3 . By using the heavily doped region with the preferred appropriate depth and doping concentration, the formation of the first semiconductor layer and the heavily / lightly doped region can be ensured without being damaged, which is more conducive to improving the series resistance of the cell, thereby improving the conversion efficiency of the cell.

[0052] Optionally in the present disclosure, the heavily doped region is located in the middle region of the N-type doped polysilicon layer.

[0053] In some preferred embodiments of the present disclosure, the width W1 of the heavily doped region is 200-500 μm. A heavily doped region with a suitable width can completely cover the first semiconductor opening region, maximize the improvement of the series resistance of the cell, and thus more favorably improve the conversion efficiency of the cell.

[0054] Preferably, the width W2 of the first semiconductor opening region is 100-300 μm.

[0055] In some preferred embodiments of the present disclosure, the width W3 of the second semiconductor opening region is 300-700 μm.

[0056] In some preferred embodiments of the present disclosure, the thickness of the lightly doped region is 80-200 nm, and the effective doping concentration is 8×10 18 / cm 3 -5×10 19 / cm 3 It can be understood that the N-type doped polysilicon layer is composed of the lightly doped region and the heavily doped region, and the thickness of the lightly doped region is equal to the thickness of the N-type doped polysilicon layer.

[0057] On the basis of satisfying the ratio of the surface doping index of the lightly doped region to the heavily doped region and the P-type doped silicon layer, the thickness and the effective doping concentration of the P-type doped silicon layer can be selected according to actual needs. In some preferred embodiments of the present disclosure, the thickness of the P-type doped silicon layer is 10-15 nm, and the effective doping concentration is 5×10 19 / cm 3 -3×10 20 / cm 3 .

[0058] The P-type doped silicon layer can be doped amorphous silicon or doped microcrystalline silicon.

[0059] On the basis of satisfying the ratio of the depth of the heavily doped region to the thickness of the intrinsic amorphous silicon layer and the thickness of the tunneling oxide layer, the thickness of the intrinsic amorphous silicon layer and the thickness of the tunneling oxide layer can be selected according to actual needs. In some preferred embodiments of the present disclosure, the thickness of the tunneling oxide layer is 1-2 nm, and the thickness of the intrinsic amorphous silicon layer is 6-8 nm.

[0060] In some preferred embodiments of the present disclosure, a mask layer is arranged or not arranged between the first semiconductor layer and the second semiconductor layer in the region between the first semiconductor opening region and the second semiconductor opening region.

[0061] In some preferred embodiments of the present disclosure, the part of the silicon wafer located at the position of the second semiconductor opening region is a textured surface, and the part of the silicon wafer corresponding to the position of the first semiconductor layer is a polished surface.

[0062] Optionally, the joint passivated back contact cell further comprises a metal electrode and a conductive film layer laid on the outer surface of the first semiconductor layer and the second semiconductor layer, the metal electrode is arranged on the outer surface of the respective corresponding conductive film layer of the second semiconductor opening area and the first semiconductor opening area; a corresponding part of the conductive film layer at the interface between the texturing surface and the polishing surface is provided with an isolation groove, and the width WgL of the isolation groove is 30-200 μm.

[0063] Embodiments of the present disclosure can also include other conventional film layers, such as a passivation layer and an anti-reflection layer arranged on the front surface of the silicon wafer, and the types and thicknesses of the passivation layer and the anti-reflection layer can be referred to in the prior art respectively.

[0064] Embodiments of the present disclosure provide a preparation method of a joint passivated back contact cell, which is configured to prepare the joint passivated back contact cell with the specific heavily doped region of the first aspect, and the preparation method of the joint passivated back contact cell comprises the following steps:

[0065] S01, providing a silicon wafer;

[0066] S02, forming a first semiconductor layer on the back surface of the silicon wafer, and simultaneously forming a phosphosilicate glass layer (also referred to as a PSG layer) on the back surface naturally;

[0067] S03, performing selective heavy doping treatment on the preset area of the back surface obtained in S02 to form a heavily doped region; the selective heavy doping treatment includes a laser doping method;

[0068] S04, removing the phosphosilicate glass layer by acid washing, and forming a first mask layer on the back surface after back washing;

[0069] S05, performing first opening on the back surface obtained in S04 to remove part of the first mask layer and the corresponding part of the first semiconductor layer, and forming second semiconductor opening areas arranged alternately; the direction of the first opening is parallel to the direction of the selective heavy doping treatment;

[0070] S06, then performing texturing cleaning to remove the first semiconductor layer in the second semiconductor opening area, and then removing the remaining first mask layer;

[0071] S07, then depositing a passivation layer and an anti-reflection layer on the front surface of the silicon wafer in sequence, and depositing a second semiconductor layer on the back surface;

[0072] S08, performing second opening in the position corresponding to the heavily doped region of the back surface obtained in S07 to remove the second semiconductor layer, and forming first semiconductor opening areas arranged alternately with the second semiconductor opening areas; the direction of the second opening is parallel to the direction of the selective heavy doping treatment.

[0073] Other conventional operations can also be included in S01, for example, double-side polishing and optional cleaning treatment can be included. The silicon wafer is preferably an N-type single crystal silicon wafer. The silicon wafer can be a Czochralski single crystal silicon wafer or a cast single crystal silicon wafer.

[0074] In some preferred embodiments of the present disclosure, the laser doping method adopts a flat-top picosecond laser.

[0075] Optionally, the flat-top picosecond laser is a flat-top picosecond green laser or a flat-top picosecond ultraviolet laser.

[0076] Optionally, the conditions of the laser doping method include that the control power is 3 kW-20 kW and the frequency is 200 kHz-1000 kHz.

[0077] The time of the selective heavy doping treatment in the embodiment S03 of the present disclosure can be as long as to obtain a heavy doping region with a desired depth, for example, can be 2-10 s.

[0078] In the embodiments of the present disclosure, the depth and doping concentration of the heavy doping region can be adjusted by controlling the process conditions of the laser doping method, or can be adjusted by coordinating the thickness and doping concentration of the N-type doped polysilicon layer, as long as a film layer with desired structure parameters is obtained.

[0079] The way of removing the phosphosilicate glass layer in S04 can refer to the prior art, as long as the phosphosilicate glass layer can be removed. It is the prior art and will not be described here.

[0080] The type and thickness of the first mask layer formed in S04 and the method can refer to the prior art, for example, the type can be at least one of silicon nitride, silicon oxide, and silicon oxynitride. For example, the thickness of the first mask layer can be 40-90 nm.

[0081] In the embodiments of the present disclosure, the first opening and the second opening can be formed by laser or mask etching, which can refer to the prior art. It is the prior art and will not be described here.

[0082] In the embodiments of the present disclosure, the deposition of the first semiconductor layer and the second semiconductor layer can refer to the prior art, which will not be described here.

[0083] In some preferred embodiments of the present disclosure, the preparation method of the joint passivated back contact cell further comprises:

[0084] S09, removing the oxide layer in the first semiconductor opening region by cleaning; and then depositing a conductive film layer on the back surface;

[0085] S10, performing a third opening on the conductive film layer between the first semiconductor opening region and the second semiconductor opening region to form an isolation groove.

[0086] S11, forming a metal electrode on the back surface obtained in S10.

[0087] It can be understood that the oxide layer in S09 is formed due to the contact with air after the formation of the first semiconductor opening region, and thus the cleaning process in S09 is required to be completed for removal.

[0088] The preparation method of the joint passivation back contact cell in the embodiments of the present disclosure can also include other conventional required steps, which can be selected according to actual needs.

[0089] The embodiments of the present disclosure provide a battery assembly, which comprises the joint passivation back contact cell with the specific heavily doped region according to the first aspect.

[0090] The embodiments of the present disclosure are described in detail below, which are exemplary and only used to explain the present disclosure, and cannot be understood as a limitation of the present disclosure.

[0091] Embodiment 1

[0092] A joint passivation back contact cell with a specific heavily doped region 4, the structure of which is shown in FIG. 1, and the preparation method thereof is shown in FIG. 2, which comprises:

[0093] S01, polishing both surfaces of a silicon wafer 1;

[0094] S02, sequentially plating a first semiconductor layer on the back surface of the silicon wafer 1, the first semiconductor layer being a tunneling oxide layer 2 and an N-type doped polysilicon layer 3, the thickness of the tunneling oxide layer 2 being 1.5 nm, the thickness of the N-type doped polysilicon layer 3 being 100 nm, and the effective doping concentration being 1×10 19 / cm 3 ; a phosphosilicate glass layer (i.e., PSG layer) is naturally formed on the outer surface of the back surface along with the formation of the N-type doped polysilicon layer 3;

[0095] S03, using a flat-top picosecond green laser to perform selective heavy doping treatment on the middle part of the N-type doped polysilicon layer 3 on the back surface of the silicon wafer 1 to form a heavily doped region 4, and other regions being lightly doped regions. The width W1 of the heavily doped region 4 is 300 μm, W1 being 30% of the width of the N-type doped polysilicon layer, the depth of the heavily doped region 4 being 60 nm, and the effective doping concentration of the heavily doped region 4 being 1×10 20 / cm 3 ;

[0096] The power of the flat-top picosecond green laser is 6 kW, the frequency is 200 kHz, and the processing time is 3.5 s.

[0097] S04, removing the PSG layer by acid washing, and then plating a first mask layer on the back surface after back washing, the first mask layer being silicon nitride with a thickness of 50 nm;

[0098] S05, etching a part of the first semiconductor layer on the back surface of the silicon wafer 1 to form a first opening, removing the first mask layer and the corresponding part of the first semiconductor layer, forming second semiconductor opening areas arranged alternately, the width W3 of the second semiconductor opening area being 500 μm; the etching direction being parallel to the direction of the selective heavy doping treatment;

[0099] S06, texturing and cleaning the silicon wafer 1, forming a pyramid texture on the front surface of the silicon wafer 1 and the second semiconductor opening areas, and simultaneously removing the first semiconductor layer in the second semiconductor opening areas on the back surface of the silicon wafer 1, and then removing the first mask layer;

[0100] S07, depositing a passivation layer 8 (specifically, intrinsic amorphous silicon and N-type doped microcrystalline silicon formed in sequence) and an anti-reflection layer 9 (specifically, silicon nitride) on the front surface of the silicon wafer 1, and depositing a second semiconductor layer on the back surface, the second semiconductor layer being an intrinsic amorphous silicon layer 5 (7 nm thick) and a P-type doped amorphous silicon layer 6; the thickness of the P-type doped amorphous silicon layer 6 being 12.5 nm, and the effective doping concentration being 9×10 19 / cm 3 ;

[0101] S08, etching a part of the second semiconductor layer on the back surface of the silicon wafer 1 to form a second opening, forming first semiconductor opening areas arranged alternately with the second semiconductor opening areas, the etching direction being parallel to the direction of the selective heavy doping treatment, and the etching position being on the position of the selective heavy doping treatment, the width W2 of the formed first semiconductor opening area being 200 μm, and W2

[0102] S09, cleaning the silicon wafer 1, and then depositing a transparent conductive film layer 7 on the back surface of the silicon wafer 1 after removing the oxide layer in the first semiconductor opening area;

[0103] S10, forming a third opening in part of the transparent conductive film layer 7 between the first semiconductor opening area and the second semiconductor opening area by etching to form an isolation groove, the width WgL of the isolation groove being 50 μm, and the isolation groove being formed at the junction of the textured surface and the polished surface;

[0104] S11, printing a main grid line on the back surface of the silicon wafer 1, and connecting the transparent conductive film layer 7 on the first semiconductor opening area and the second semiconductor opening area in series to form a silver paste metal electrode.

[0105] Example 2

[0106] The method of Example 1 is referred to, except that the power of the selective heavy doping treatment in S03 is 4.6 kW, the depth of the obtained heavy doping region is 50 nm, and the effective doping concentration is 3×10 20 / cm3 , the width remains unchanged.

[0107] Example 3

[0108] The method of Example 1 was followed, except that the depth of the heavily doped region was adjusted to 30 nm. Calculations showed that the depth of the heavily doped region was 37.5% of the thickness of the lightly doped region. The ratio of the depth of the heavily doped region to the thickness of the intrinsic amorphous silicon layer and the thickness of the tunneling oxide layer was 20:4.7:1. Furthermore, the ratio of the doping indices of the lightly doped region, the heavily doped region, and the P-type doped silicon layer was 1:26.7:57.6. The process parameters required to meet this requirement for the depth of the heavily doped region were: thinning the N-type doped polysilicon layer to 80 nm.

[0109] Example 4

[0110] The method of Example 1 was followed, except that the depth of the heavily doped region was adjusted to 80 nm. Calculations showed that the depth of the heavily doped region was 59% of the thickness of the lightly doped region. The ratio of the depth of the heavily doped region to the thickness of the intrinsic amorphous silicon layer and the thickness of the tunneling oxide layer was 53.3:4.7:1. Furthermore, the ratio of the doping indices of the lightly doped region, the heavily doped region, and the P-type doped silicon layer was 1:16.9:97.2. The process parameters required to meet this requirement for the depth of the heavily doped region were: increasing the thickness of the N-type doped polysilicon layer to 135 nm.

[0111] Example 5

[0112] The method of Example 1 is followed, except that the effective doping concentration of the heavily doped region is adjusted to 8×10 19 / cm 3 , after calculation, the ratio of the surface doping index of the lightly doped region to the heavily doped region and the P-type doped silicon layer is 1:16.7:90. In order to meet the effective doping concentration of the heavily doped region, the process parameters that need to be adjusted are: reducing the doping concentration of the N-type doped polysilicon layer to 8×10 18 / cm 3 .

[0113] Example 6

[0114] The method of Example 1 is followed, except that the effective doping concentration of the heavily doped region is adjusted to 3×10 20 / cm 3 , it is calculated that the effective doping concentration of the heavily doped region is 10 times that of the lightly doped region, and the ratio of the surface doping index of the lightly doped region to the heavily doped region and the P-type doped silicon layer is 1:16.7:24. To meet the effective doping concentration of the heavily doped region, the process parameters that need to be adjusted are: increasing the doping concentration of the N-type doped polysilicon layer to 3×1019 / cm 3 .

[0115] Example 7

[0116] The method of Example 1 was followed, except that the width Wl of the heavily doped region was adjusted to be greater than the width W2 of the first semiconductor opening region, Wl was 250 μm, and the width Wl of the heavily doped region was calculated to be 25% of the width of the N-type doped polysilicon layer.

[0117] Example 8

[0118] The method of Example 1 was followed, except that the width Wl of the heavily doped region was adjusted to be greater than the width W2 of the first semiconductor opening region, Wl was 400 μm, and the width Wl of the heavily doped region was calculated to be 40% of the width of the N-type doped polysilicon layer.

[0119] Example 9

[0120] The method of Example 1 was followed, except that the thickness of the tunneling oxide layer was adjusted to be 1 nm, and the ratio of the depth of the heavily doped region to the thickness of the tunneling oxide layer was calculated to be 60: 1.

[0121] Example 10

[0122] The method of Example 1 was followed, except that the thickness of the intrinsic amorphous silicon layer was adjusted to be 6 nm, and the ratio of the depth of the heavily doped region to the thickness of the intrinsic amorphous silicon layer, to the thickness of the tunneling oxide layer was calculated to be 40:4: 1.

[0123] Example 11

[0124] The method of Example 1 was followed, except that the thickness of the P-type doped silicon layer was adjusted to be 10 nm, and the effective doping concentration was unchanged, and the ratio of the face doping index of the lightly doped region to the heavily doped region, to the P-type doped silicon layer was calculated to be 1:16.7:90.

[0125] Comparative Example 1

[0126] The method of Example 1 was followed, except that the heavily doped region was not formed, i.e., S03 was not performed, but S04 was performed directly after S02.

[0127] Comparative Example 2

[0128] The method of Example 1 was followed, except that the first semiconductor layer was an intrinsic amorphous silicon layer (6 nm thick) and an N-type doped amorphous silicon layer (110 nm thick, effective doping concentration of 2 x 1019 / cm3). 19 / cm 3 .

[0129] Comparative Example 3

[0130] The method of Example 1 is followed, except that the depth of the heavily doped region is adjusted to 20 nm, calculated to be 40% of the thickness of the lightly doped region, and the ratio of the depth of the heavily doped region to the thickness of the intrinsic amorphous silicon layer to the thickness of the tunneling oxide layer is 13.3:4.7:1; and the ratio of the surface doping index of the lightly doped region to the heavily doped region to the P-type doped silicon layer is 1:25:36. To meet the depth of the heavily doped region, the process parameters need to be adjusted as follows: the thickness of the N-type doped polysilicon layer is thinned to 50 nm.

[0131] Comparative Example 4

[0132] The method of Example 1 is followed, except that the depth of the heavily doped region is adjusted to 95 nm, calculated to be 59% of the thickness of the lightly doped region, and the ratio of the depth of the heavily doped region to the thickness of the intrinsic amorphous silicon layer to the thickness of the tunneling oxide layer is 63.3:4.7:1; and the ratio of the surface doping index of the lightly doped region to the heavily doped region to the P-type doped silicon layer is 1:16.8:115.2. To meet the depth of the heavily doped region, the process parameters need to be adjusted as follows: the thickness of the N-type doped polysilicon layer is increased to 160 nm.

[0133] Comparative Example 5

[0134] The method of Example 1 is followed, except that the width W1 of the heavily doped region is adjusted to be equal to the width W2 of the first semiconductor opening region, W1 = 200 μm, calculated to be 20% of the width of the N-type doped polysilicon layer.

[0135] Test Example

[0136] 1. The performance of the joint passivation back contact cells obtained in the above examples and comparative examples is tested, and the results are shown in Table 1. Among them, the unit of short circuit current I sc is A, the unit of open circuit voltage Voc is V, the unit of fill factor FF is %, and the unit of cell conversion efficiency Eta is %.

[0137] Table 1

[0138] From the above results, it can be seen that, compared with the comparative examples, the embodiment scheme of the present disclosure can improve the series resistance of the cell, reduce the emitter contact resistance and the emitter area dark saturation current, and improve the fill factor, the short circuit current and the open circuit voltage, thereby improving the cell conversion efficiency, without damaging the tunneling polysilicon layer structure of the first semiconductor layer. Further, according to Examples 1 and 3-11, the scheme using the preferred specific layer structure parameters of the present disclosure is more conducive to improving the cell conversion efficiency.

[0139] 2. Taking Examples 1 and 2 as examples, the sheet resistance of the first semiconductor layer before and after the selective heavy doping treatment is tested by a sheet resistance tester, and the results are shown in Table 2. In Table 2, the tunneling polysilicon layer sheet resistance refers to the sheet resistance of the first semiconductor layer before the selective heavy doping treatment, and the selective heavy doping treatment sheet resistance refers to the sheet resistance of the first semiconductor layer after the selective heavy doping treatment.

[0140] Table 2

[0141] As can be seen from Table 2, the sheet resistance of the region after the selective heavy doping treatment is significantly reduced, indicating that an n+ / n high-low junction is effectively formed at the junction of the heavy doping region and the light doping region, and the series resistance of the cell is significantly improved.

[0142] The above describes the preferred embodiments of the present disclosure in detail, but the present disclosure is not limited thereto. Within the technical concept of the present disclosure, various simple modifications can be made to the technical solutions of the present disclosure, including the combination of various technical features in any other suitable manner, and these simple modifications and combinations should also be considered as disclosed by the present disclosure and fall within the protection scope of the present disclosure. Industrial applicability

[0143] The specific heavy doping region is arranged on the N-type doped polysilicon layer in the joint passivation interdigital structure, and the width, depth and effective doping concentration of the heavy doping region are set in association with other specific layers and in accordance with the specific relationship, so that an appropriate lateral n + high-low junction is formed at the junction of the heavy doping region and the light doping region, and the position of the high-low junction is appropriate, which can improve the series resistance of the cell, reduce the emitter contact resistance and the emitter area dark saturation current, improve the fill factor, short-circuit current and open-circuit voltage, and thus improve the cell conversion efficiency without damaging the tunneling polysilicon layer structure of the first semiconductor layer.

Claims

1. A back contact cell with specific heavily doped regions and combined passivation, comprising a silicon wafer having a front side and a back side, first semiconductor layers and second semiconductor layers arranged alternately on the back side of the silicon wafer, the second semiconductor layers extending outwardly at both ends thereof to cover part of the back side of the adjacent first semiconductor layers and leaving first semiconductor open areas on the back side of the first semiconductor layers which are not covered by the second semiconductor layers, second semiconductor open areas being formed between the adjacent first semiconductor layers, the second semiconductor open areas being arranged in a spaced-apart manner with the first semiconductor open areas, wherein, The first semiconductor layer comprises a tunneling oxide layer and an N-type doped polysilicon layer arranged in sequence from the silicon wafer outward, and the second semiconductor layer comprises an intrinsic amorphous silicon layer and a P-type doped silicon layer arranged in sequence from the silicon wafer outward, characterized in that the N-type doped polysilicon layer has a heavily doped region, the heavily doped region is located inside the first semiconductor opening area and covers the position area of the first semiconductor opening area, and the width W1 of the heavily doped region is greater than the width W2 of the first semiconductor opening area, the width W1 of the heavily doped region is 20%-50% of the width of the N-type doped polysilicon layer; the part of the N-type doped polysilicon layer between the width direction outer edge of the heavily doped region and the adjacent outer edge of the first semiconductor layer is a lightly doped region, the depth of the heavily doped region is 25%-90% of the thickness of the lightly doped region, the ratio of the depth of the heavily doped region to the thickness of the intrinsic amorphous silicon layer and the thickness of the tunneling oxide layer is 20-100:3-8:1; and the ratio of the surface doping index of the lightly doped region to the heavily doped region and the P-type doped silicon layer is 1:10-90:10-100, wherein the surface doping index refers to the ratio of the effective doping concentration to the thickness of the corresponding doped region or doped layer.

2. The back contact solar cell with specific heavily doped regions according to claim 1, wherein, The effective doping concentration of the heavily doped region is 1.4-40 times the effective doping concentration of the lightly doped region.

3. Back contact cell with specific heavily doped regions for a combined passivation, according to claim 1 or 2, characterized in that, The depth of the heavily doped region is 30-100 nm, and the effective doping concentration of the heavily doped region is 7x10 19 / cm 3 -5x10 20 / cm 3 .

4. Back contact cell with specific heavily doped regions for a combined passivation, according to claim 1 or 2, characterized in that, The width W1 of the heavily doped region is 200-500μm, and the width W2 of the first semiconductor opening area is 100-300μm; and / or, The width W3 of the second semiconductor opening area is 300-700μm.

5. The back contact solar cell with specific heavily doped regions of claim 1, wherein, The light doped region has a thickness of 80-200 nm and an effective doping concentration of 8 x 1015-5 x 1016 / cm3. 18 / cm 3 ; and 19 / cm 3 ; and and / or, The thickness of the P-type doped silicon layer is 10-15 nm, the effective doping concentration is 5x10 19 / cm 3 3x10 20 / cm 3 .

6. The back contact solar cell with specific heavily doped regions of claim 1, wherein, The thickness of the tunneling oxide layer is 1-2nm, and the thickness of the intrinsic amorphous silicon layer is 6-8nm.

7. The back contact solar cell with specific heavily doped regions of claim 1, wherein, In the area between the first semiconductor opening area and the second semiconductor opening area, a mask layer is arranged or not arranged between the first semiconductor layer and the second semiconductor layer; and / or, The part of the silicon wafer located at the position of the second semiconductor opening area is a textured surface, and the part of the silicon wafer corresponding to the position of the first semiconductor layer is a polished surface, and the joint passivated back contact cell further comprises a metal electrode and a conductive film layer arranged on the outer surfaces of the first semiconductor layer and the second semiconductor layer, the metal electrode is arranged on the outer surface of the respective conductive film layer of the second semiconductor opening area and the first semiconductor opening area, and a corresponding part of the conductive film layer located at the interface between the textured surface and the polished surface is provided with an isolation groove, and the width WgL of the isolation groove is 30-200μm.

8. A method of fabricating a co-passivated back contact cell, characterized by, The configuration is configured to prepare the joint passivated back contact cell with a specific heavily doped region as claimed in any one of claims 1-7, and the preparation method of the joint passivated back contact cell comprises the following steps: S01, providing a silicon wafer; S02, forming a first semiconductor layer on the back surface of the silicon wafer, and naturally forming a phosphosilicate glass layer on the back surface; S03, performing selective heavy doping treatment on the preset area of the back surface obtained in S02 to form a heavily doped region; the selective heavy doping treatment includes laser doping method; S04, removing the phosphosilicate glass layer by acid washing, and forming a first mask layer on the back surface after back washing; S05, performing a first opening on the back surface obtained in S04, removing part of the first mask layer and corresponding part of the first semiconductor layer, and forming second semiconductor opening regions arranged alternately; the direction of the first opening is parallel to the direction of the selective heavy doping treatment; S06, then performing texturing and cleaning, simultaneously removing the first semiconductor layer in the second semiconductor opening regions, and then removing the remaining first mask layer; S07, then depositing a passivation layer and an anti-reflection layer on the front surface of the silicon wafer in sequence, and depositing a second semiconductor layer on the back surface; S08, performing a second opening in the position corresponding to the heavy doping region on the back surface obtained in S07, removing the second semiconductor layer, and forming first semiconductor opening regions arranged alternately with the second semiconductor opening regions; the direction of the second opening is parallel to the direction of the selective heavy doping treatment.

9. The method of producing a co-passivated back contact cell according to claim 8, wherein, The laser doping method adopts a flat-top picosecond laser, which is a flat-top picosecond green laser or a flat-top picosecond ultraviolet laser; the conditions of the laser doping method include: the control power is 3kW-20kW, and the frequency is 200kHz-1000kHz; and / or, The preparation method of the joint passivation back contact cell further includes: S09, removing the oxide layer in the first semiconductor opening region by cleaning; then depositing a conductive film layer on the back surface; S10, performing a third opening on the conductive film layer between the first semiconductor opening region and the second semiconductor opening region, and forming an isolation groove; S11, forming a metal electrode on the back surface obtained in S10.

10. A battery assembly characterized by, It comprises the joint passivation back contact cell with a specific heavy doping region as claimed in any one of claims 1-7.

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