Solar cell sheet, cell assembly and photovoltaic system

Abstract

Provided in the present application are a solar cell sheet (100), a cell assembly (200) and a photovoltaic system (1000). A first doped layer (20) of the solar cell sheet (100) is stacked on a silicon wafer (10), and the first doped layer (20) has several first preset regions (201); second doped layers (30) are stacked on the first preset regions (201) and have a polarity opposite to the polarity of the first doped layer (20); a first passivation film layer (40) is stacked on the second doped layers (30) and the first doped layer (20); and the roughness of surfaces (301) of the second doped layers (30) that are in contact with the first passivation film layer (40) is greater than the roughness of a surface (202) of the first doped layer (20) that is in contact with the first passivation film layer (40), first solder joints (50) are arranged on the first passivation film layer (40), and the orthographic projections of the first solder joints (50) on the first doped layer (20) at least partially overlap the orthographic projections of the second doped layers (30) on the first doped layer (20).

Description

Solar cell, cell assembly and photovoltaic system

[0001] Priority information

[0002] This application claims priority to and the benefit of the filing date of Chinese Patent Application No. 202420798601.0, filed April 17, 2024, and is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The present application relates to the technical field of solar cells, and in particular to a solar cell, a cell assembly and a photovoltaic system. BACKGROUND

[0004] At present, in solar cell pieces (for example, Topcon solar cell pieces, HJT solar cell pieces, back contact solar cell pieces, etc.), a doped layer is arranged, and a fine grid and a main grid are also arranged on the doped layer. The fine grid, which penetrates through the fine grid of the passivation film layer, is in contact with the doped layer to collect current. The main grid is connected with the fine grid to collect the current of the fine grid. When two solar cell pieces are connected, a welding point needs to be arranged on the cell piece to be welded with a solder strip. The welding point is usually arranged on the passivation film layer. However, in the related art, the tensile force between the doped layer below the welding point and the passivation film layer is weak, and the welding point is prone to separation due to insufficient tensile force when welding. SUMMARY

[0005] The present application provides a solar cell, a cell assembly and a photovoltaic system.

[0006] The present application is implemented in the following manner. The solar cell of the present application embodiment comprises:

[0007] a silicon wafer;

[0008] a first doped layer arranged in layers on the silicon wafer, the first doped layer having a plurality of first preset regions;

[0009] a second doped layer arranged in layers on the first preset regions, the polarity of the second doped layer being opposite to the polarity of the first doped layer;

[0010] a first passivation film layer arranged in layers on the second doped layer and the first doped layer, the roughness of the surface of the second doped layer in contact with the first passivation film layer being greater than the roughness of the surface of the first doped layer in contact with the first passivation film layer; and

[0011] a plurality of first welding points arranged on the first passivation film layer, the orthographic projection of the first welding points on the first doped layer at least partially overlapping the orthographic projection of the second doped layer on the first doped layer.

[0012] The application also provides a battery assembly comprising a plurality of the solar cell as described in any one of the above.

[0013] The application also provides a photovoltaic system comprising the battery assembly as described above.

[0014] Additional aspects and advantages of the application will be made apparent by the following description as well as the appended claims. BRIEF DESCRIPTION OF DRAWINGS

[0015] Fig. 1 is a schematic diagram of a module of a photovoltaic system according to an embodiment of the application;

[0016] Fig. 2 is a schematic diagram of a module of a battery assembly according to an embodiment of the application;

[0017] Fig. 3 is a schematic diagram of a structure of a solar cell according to an embodiment of the application;

[0018] Fig. 4 is another schematic diagram of a structure of a solar cell according to an embodiment of the application;

[0019] Fig. 5 is a schematic diagram of a planar structure of a solar cell according to an embodiment of the application;

[0020] Fig. 6 is a schematic diagram of a cross-section of the back contact cell in Fig. 5 along line VI-VI;

[0021] Fig. 7 is another schematic diagram of a cross-section of the back contact cell in Fig. 5 along line VI-VI;

[0022] Fig. 8 is another schematic diagram of a planar structure of a solar cell according to an embodiment of the application;

[0023] Fig. 9 is a schematic diagram of a cross-section of the back contact cell in Fig. 8 along line IX-IX;

[0024] Fig. 10 is a schematic diagram of a cross-section of the back contact cell in Fig. 8 along line XX;

[0025] Fig. 11 is another schematic diagram of a planar structure of a solar cell according to an embodiment of the application.

[0026] DETAILED DESCRIPTION

[0027] In order to make the objects, technical solutions and advantages of the application clearer, the application will be further described in detail below with reference to the drawings and embodiments. The embodiments described below with reference to the drawings are exemplary and are only used to explain the application, and cannot be understood as limiting the application. In addition, it should be understood that the specific embodiments described herein are only used to explain the application and cannot be used to limit the application.

[0028] In the description of the application, it should be understood that the terms "length", "width", "upper", "lower", "top", "bottom", "lateral", "longitudinal" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only used to facilitate the description of the application and simplify the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation to the application.

[0029] In addition, the terms "first", "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the application, the meaning of "a plurality of" is two or more, unless otherwise explicitly specified and limited.

[0030] In the description of the application, it should be noted that unless otherwise explicitly specified and limited, the terms "mounting", "connecting", "connection" should be understood broadly, for example, it can be fixed connection, or detachable connection, or integral connection; it can be mechanical connection, or electrical connection or can communicate with each other; it can be directly connected, or indirectly connected through an intermediate medium, or the internal communication of two elements or the interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the application can be understood according to the specific circumstances.

[0031] In the present application, unless otherwise explicitly specified and limited, the "upper" or "lower" of the first feature to the second feature can include the direct contact of the first and second features, or the indirect contact of the first and second features through another feature between them. Moreover, the "upper", "above" and "above" of the first feature to the second feature include the vertical direction of the first feature above and oblique above the second feature, or only indicate that the horizontal height of the first feature is higher than that of the second feature. The "below", "below" and "below" of the first feature to the second feature include the vertical direction of the first feature below and oblique below the second feature, or only indicate that the horizontal height of the first feature is less than that of the second feature.

[0032] The disclosure below provides many different embodiments or examples for implementing different structures of the application. For the purpose of simplicity, the elements and acts of the various examples will not be shown in their respective figures so as to not obscure the disclosure. It is intended that the embodiments and examples recited herein be considered in a descriptive sense and not for purposes of limitation. Further, many of the constituents of the examples herein can be used interchangeably in different examples. Additionally, the description is presented in terms of particular embodiments, having a battery assembly 200, a solar cell 100, a first doped layer 20, a second doped layer 30, a first passivation layer 40, and a first soldering point 50. These are provided for purposes of example and description, and are not intended to be limiting, unless otherwise specifically stated.

[0033] Referring to FIGS. 1-2, a photovoltaic system 1000 in embodiments of the present application can include a battery assembly 200 in embodiments of the present application, which can include a plurality of cell strings, and each cell string can include a plurality of solar cell pieces 100 in embodiments of the present application. In the present application, the plurality of solar cell pieces 100 in the battery assembly 200 can be connected in series by a solder strip to form a cell string. Each cell string in the battery assembly 200 can be connected in series, in parallel, or in a combination of series and parallel to achieve a current output. For example, the connection between each cell string can be achieved by a bus bar.

[0034] Referring to FIG. 3, the solar cell piece 100 in embodiments of the present application can include a silicon wafer 10, a first doped layer 20, a second doped layer 30, a first passivation layer 40, and a first soldering point 50.

[0035] The first doped layer 20 is laminated on the silicon wafer 10, and the first doped layer 20 has a plurality of first predetermined regions 201. The second doped layer 30 is laminated on the first predetermined regions 201, and the polarity of the second doped layer 30 is opposite to that of the first doped layer 20.

[0036] The first passivation layer 40 is laminated on the second doped layer 30 and the first doped layer 20. Specifically, the first passivation layer 40 can cover the entire first doped layer 20 and the second doped layer 30 (i.e., the first passivation layer 40 covers the second doped layer 30 and the region of the first doped layer 20 that is not covered by the second doped layer 30).

[0037] As shown in FIG. 3, the roughness of the surface 301 of the second doped layer 30 in contact with the first passivation layer 40 is greater than the roughness of the surface 202 of the first doped layer 20 in contact with the first passivation layer 40. The first soldering point 50 is disposed on the first passivation layer 40, and the orthographic projection of the first soldering point 50 on the first doped layer 20 at least partially overlaps the orthographic projection of the second doped layer 30 on the first doped layer 20.

[0038] It should be noted that in the present application, the "orthographic projection" refers to the orthographic projection along the thickness direction of the solar cell 100. In the following, if there is the same description, please refer to the processing solution.

[0039] In the solar cell of the embodiment of the present application, the second doped layer 30 is arranged on the first preset area 201 of the first doped layer 20, the first passivation film layer 40 covers the second doped layer 30, the roughness of the surface 301 of the second doped layer 30 in contact with the first passivation film layer 40 is greater than the roughness of the surface 202 of the first doped layer 20 in contact with the first passivation film layer 40, and the orthographic projection of the first solder joint 50 on the first doped layer 20 at least partially overlaps the orthographic projection of the second doped layer 30 on the first doped layer 20. In this way, by arranging the second doped layer 30 on the first doped layer 20, and the roughness of the surface 301 of the second doped layer 30 in contact with the first passivation film layer 40 is greater than the roughness of the surface 202 of the first doped layer 20 in contact with the first passivation film layer 40, the bonding force between the first passivation film layer 40 and the second doped layer 30 can be greater than the bonding force between the first passivation film layer 40 and the first doped layer 20. Therefore, arranging the first solder joint 50 above the second doped layer 30 (i.e., the orthographic projection of the first solder joint 50 on the first doped layer 20 at least partially overlaps the orthographic projection of the second doped layer 30 on the first doped layer 20) can effectively improve the soldering force of the first solder joint 50 during soldering, thereby effectively preventing the first solder joint 50 from being separated during soldering and improving the reliability of soldering.

[0040] Specifically, in the present application, the solar cell 100 can specifically be a back contact cell, a Topcon solar cell, an HJT solar cell, or other solar cells having a first doped layer 20 and requiring a solder joint to be arranged on the first doped layer 20, and the specific embodiments are not limited herein.

[0041] In the present application, the first doped layer 20 and the second doped layer 30 can each be a P-type doped layer and an N-type doped layer, and only the polarity of the two needs to be opposite. For example, in some embodiments, the first doped layer 20 can be a P-type polysilicon layer, a P-type amorphous silicon layer, or a P-type microcrystalline silicon layer, and the specific embodiments are not limited herein. Similarly, the second doped layer 30 can be an N-type polysilicon layer, an N-type amorphous silicon layer, or an N-type microcrystalline silicon layer, and the specific embodiments are not limited herein.

[0042] In some embodiments, a tunneling oxide layer or an intrinsic amorphous silicon layer (not shown in the figure) can be arranged between the first doped layer 20 and the silicon wafer 10. Specifically, when the solar cell is a Topcon solar cell or a back contact cell, a tunneling oxide layer can be arranged between the first doped layer 20 and the silicon wafer 10, and when the solar cell is an HJT solar cell, an intrinsic amorphous silicon layer can be arranged between the first doped layer 20 and the silicon wafer 10.

[0043] Referring to FIG. 4, in some embodiments, the solar cell 100 can further include a first isolation layer 60, which can be arranged on the first preset area 201 and between the first doped layer 20 and the second doped layer 30.

[0044] In this way, the second doped layer 30 can be separated from the first doped layer 20 by the first isolation layer 60, avoiding direct contact between the two, while also ensuring the passivation effect of the first doped layer 20.

[0045] Of course, it can be understood that, in some embodiments, the first doped layer 20 and the second doped layer 30 can also be separated without the need to arrange the first isolation layer 60, and it is only necessary to arrange the metal grid line in the solar cell 100 that contacts the first doped layer 20 to not contact the second doped layer 30, without limitation.

[0046] In some embodiments, the thickness of the first isolation layer 60 can be greater than 2 nm. In this way, the process difficulty can be greatly increased due to the too small thickness of the first isolation layer 60.

[0047] In addition, in some embodiments, the first isolation layer 60 can include at least one of a silicon oxide film layer, a silicon nitride film layer, an aluminum oxide film layer, a silicon oxynitride film layer, a silicon carbide film layer, and an intrinsic amorphous silicon film layer.

[0048] Specifically, in such embodiments, the first isolation layer 60 can or can not have a tunneling function, and can be an insulating layer or a non-insulating layer, without limitation, and the specific film layer can be selected according to different types of cells.

[0049] For example, when the cell is a Topcon solar cell or a back contact cell, the first isolation layer 60 can be at least one of a silicon oxide film layer, a silicon nitride film layer, an aluminum oxide film layer, a silicon oxynitride film layer, and a silicon carbide film layer. The first isolation layer 60 can have a tunneling function or can not have a tunneling function.

[0050] When the cell is an HJT solar cell, the first isolation layer 60 can be an intrinsic amorphous silicon layer. It can be understood that this is only an exemplary description of the specific selection of the first isolation layer 60, but it cannot be understood as a limitation of the present application.

[0051] As shown in FIGS. 3 and 4, in some embodiments, the orthographic projection of the first solder joint 50 on the first doped layer 20 is completely located within the first preset area 201, that is, in the thickness direction of the solar cell 100, the first solder joint 50 is completely located above the second doped layer 30.

[0052] In this way, the first soldering point 50 is completely located in the first preset area 201, and the entire bottom of the first soldering point 50 has the second doped layer, so that the soldering tension at the first soldering point 50 is maximized, thereby ensuring the reliability of the soldering.

[0053] Specifically, in such embodiments, the area of the first preset area 201 can be preferably just equal to or slightly larger than the area of the orthographic projection of the first soldering point 50.

[0054] Of course, in some embodiments, the orthographic projection area of the first soldering point 50 on the first doped layer 20 can also be larger than the orthographic projection area of the second doped layer 30 on the first doped layer 20 (i.e., the area of the first preset area 201), for example, a single first soldering point 50 can correspond to multiple second doped layers 30, in which case the first soldering point 50 can completely cover the second doped layer 30, in which case the ratio of the area of the second doped layer 30 overlapping the first soldering point 50 to the total area of the first soldering point 50 can be greater than 20% to avoid too small soldering tension.

[0055] In addition, in some embodiments, the first soldering point 50 can be bonded above the first passivation film layer 40, can be partially embedded into the first passivation film layer 40, or can be at least partially pierced through the first passivation film layer 40 to contact the second doped layer 30, when the first soldering point 50 contacts the second doped layer 30, the first doped layer 20 and the second doped layer 30 can be isolated by setting the first isolation layer 60, which is not limited here.

[0056] In some embodiments, the thickness of the second doped layer 30 can be 5nm-400nm.

[0057] In this way, the thickness of the second doped layer 30 can be effectively prevented from being too thin to cause poor tension enhancement effect, and the second doped layer 30 can also be prevented from being too thin to increase the process difficulty, and the second doped layer 30 can also be prevented from being too thick to increase the cost.

[0058] Specifically, the thickness of the second doped layer 30 can be 5nm, 10nm, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, 150nm, 200nm, 250nm, 300nm, 350nm, 400nm, or any value between 5nm and 400nm, which is not limited here.

[0059] In some embodiments, the first passivation film layer 40 can include at least one of a silicon nitride film layer, an aluminum oxide film layer, a silicon oxynitride film layer, an intrinsic amorphous silicon film layer, and a TCO film layer.

[0060] Specifically, in such embodiments, the type of the first passivation film layer 40 can also be selected according to different types of battery pieces, for example, when the battery is a Topcon solar cell and a back contact battery, the first passivation film layer 40 can be at least one of a silicon oxide film layer, a silicon nitride film layer, an aluminum oxide film layer, a silicon oxynitride film layer, and a silicon carbide film layer.

[0061] When the battery is an HJT solar cell, the first passivation film layer 40 can be a TCO film layer, which is not specifically limited here. It can be understood that only the specific selection of the first passivation film layer 40 is exemplarily described here, but it cannot be understood as a limitation of the present application.

[0062] Referring to FIGS. 5-9, in some embodiments, the silicon wafer 10 has opposite first and second surfaces 11 and 12, and the solar cell piece 100 can further include a third doped layer 70, a second passivation film layer 80, and a plurality of second solder points 90. The polarity of the third doped layer 70 is opposite to that of the first doped layer 20.

[0063] As shown in FIGS. 5 and 6, in some embodiments, the first doped layer 20 can be laminated on the first surface 11, the third doped layer 70 can be laminated on the second surface 12, the second passivation film layer 80 can be laminated on the third doped layer 70, and the second solder points 90 can be disposed on the second passivation film layer 80. In such a case, the solar cell piece 100 is a bifacial solar cell piece, for example, a Topcon solar cell, an HJT solar cell, etc.

[0064] Similarly, in the present application, the second passivation film layer 80 can also include at least one of a silicon nitride film layer, an aluminum oxide film layer, a silicon oxynitride film layer, an intrinsic amorphous silicon film layer, and a TCO film layer.

[0065] As shown in FIGS. 8 and 9, in some embodiments, the first doped layer 20 and the third doped layer 70 can also be laminated on the first surface 11, the first passivation film layer 40 can be laminated on the first doped layer 20, the second doped layer 30, and the third doped layer 70, the second solder points 90 can also be disposed on the first passivation film layer 40, and the second passivation film layer 80 can be laminated on the second surface 12. In such a case, the solar cell piece 100 is a back contact battery, the first surface 11 is the back surface of the battery, and the second surface 12 is the front surface of the battery.

[0066] In the embodiments of the present application, in the solar cell 100, the second doped layer 30 can be obtained after the scribe layer is partially removed in the process of forming the third doped layer 70 as mentioned above, and the roughness of the second doped layer 30 can be controlled by controlling the temperature and time of deposition or by etching treatment. Of course, in some embodiments, the second doped layer 30 can also be directly obtained by deposition, and the roughness of the second doped layer 30 can also be controlled by controlling the temperature and time of deposition or by etching treatment, which is not limited in particular herein.

[0067] It can be understood that, when the solar cell 100 is a bifacial solar cell, a plurality of first busbars (not shown in the figure) are arranged on the first passivation layer 40, the first busbars penetrating through the first passivation layer 40 and contacting the first doped layer 20, and a plurality of second busbars (not shown in the figure) are arranged on the second passivation layer 80, the second busbars penetrating through the second passivation layer 80 and contacting the third doped layer 70. In the bifacial solar cell, a first main busbar (not shown in the figure) crossing the first busbar and a second main busbar (not shown in the figure) crossing the second busbar are further arranged. The first soldering point 50 can be arranged on the first main busbar, which can be located on the first passivation layer 40 or partially embedded into the first passivation layer 40 or penetrate through the first passivation layer 40 and contact the second doped layer 30 below the first passivation layer 40, and the first soldering point 50 is used for soldering with a solder ribbon. Similarly, the second soldering point 90 can be arranged on the second main busbar, which can be located on the second passivation layer 80 or partially embedded into the second passivation layer 80 or penetrate through the second passivation layer 80, and the second soldering point 90 is also used for soldering with a solder ribbon.

[0068] When the solar cell 100 is a back contact cell, the first passivation layer 40 is provided with a third busbar (not shown in the figure) and a fourth busbar (not shown in the figure), the third busbar penetrating through the first passivation layer 40 and contacting the first doped layer 20, and the fourth busbar penetrating through the first passivation layer 40 and contacting the third doped layer 70.

[0069] When the solar cell 100 is a back contact cell, the following two cases can be divided:

[0070] The first case is shown in FIG. 8. In some embodiments, on the first surface 11, a plurality of first doped layers 20 and a plurality of third doped layers 70 can be arranged in sequence and alternately along a first direction, and the first doped layers 20 and the third doped layers 70 both extend along a second direction, the second direction and the first direction being crossed, and the two can be the longitudinal direction and the transverse direction of the solar cell 100, respectively. As can be seen from FIG. 8, in the present embodiment, the first doped layer 20 and the third doped layer 70 are continuous doped layers along the second direction, and the two are arranged in sequence and alternately along the first direction.

[0071] In the back contact cell, the main grid can be provided or not provided. When the main grid is provided, it includes a plurality of third main grids (not shown in the figure) and a plurality of fourth main grids (not shown in the figure), the plurality of third main grids and the plurality of fourth main grids are arranged alternately along the second direction, the third sub-grid is connected with the third main grid and is disconnected at the fourth main grid, the fourth sub-grid is connected with the fourth main grid and is disconnected at the third main grid, the first solder joint 50 is provided at the third main grid and is connected with the third main grid, and the second solder joint 90 is provided at the fourth main grid and is connected with the fourth main grid. Along the extension direction of the third main grid, a plurality of first solder joints 50 can be provided, and along the extension direction of the fourth main grid, a plurality of second solder joints 90 can be provided.

[0072] When the main grid is not provided, the first solder joint 50 and the second solder joint 90 can be directly provided in the solder tape covering area of the cell. For example, the first solder joint 50 can be provided at the disconnected position of the third sub-grid, and the second solder joint 90 can be provided at the disconnected position of the fourth sub-grid. In this way, the solder tape can be directly connected with the solder joint without the main grid. It can be understood that in this case, the solder tape welded with the first solder joint 50 can be electrically connected with all the third sub-grids, and the solder tape welded with the second solder joint 90 can be electrically connected with all the fourth sub-grids. Of course, in some embodiments, the third sub-grid and the fourth sub-grid can also not be disconnected, but can be isolated by an insulating glue at the main grid or the solder tape with different polarities. The specific implementation is not limited here.

[0073] Secondly, as shown in FIG. 11, in some embodiments, the first doped layer 20 can include a plurality of first sub-doped layers 21 and a plurality of second sub-doped layers 22, and the third doped layer 70 can include a plurality of third sub-doped layers 71 and a plurality of fourth sub-doped layers 72. The plurality of first sub-doped layers 21 and the plurality of third sub-doped layers 71 are arranged alternately and spaced apart in sequence along the first direction on the first surface 11 and extend along the second direction. The plurality of second sub-doped layers 22 and the plurality of fourth sub-doped layers 72 are arranged alternately and spaced apart in sequence along the second direction on the first surface 11 and extend along the first direction, the first sub-doped layer 21 is disconnected at the fourth sub-doped layer 72 and is in contact with the second sub-doped layer 22, and the third sub-doped layer 71 is disconnected at the second sub-doped layer 22 and is in contact with the fourth sub-doped layer 72. Among them, the second sub-doped layer 22 has a plurality of first preset areas 201, the plurality of first preset areas 201 are spaced apart along the second direction, and the number of the first solder joints 50 can correspond to the number of the first preset areas 201. In this case, the first solder joint 50 can be provided above the second sub-doped layer 22, and the second solder joint 90 can be provided above the fourth sub-doped layer 72.

[0074] Specifically, it is not difficult to understand that the first sub-doped layer 21 and the second sub-doped layer 22 together constitute the comb-shaped first doped layer 20, and the third sub-doped layer 71 and the fourth sub-doped layer 72 together constitute the comb-shaped third doped layer 70. The first sub-doped layer 21 and the second sub-doped layer 22 can be formed by the same process, and the third doped layer 71 and the fourth sub-doped layer 72 can be formed by the same process.

[0075] Further, in such embodiments, in the first direction, the length of the first solder joint 50 is greater than the length of the second doped layer 30, and the ratio between the length of the first solder joint 50 above the second doped layer 30 and the total length of the first solder joint 50 is greater than or equal to 20%.

[0076] In this way, when the length of the first solder joint 50 in the first direction is large, setting the ratio between the length of the first solder joint 50 above the second doped layer 30 (i.e. the length of the orthogonal projection of the first solder joint 50 in the thickness direction overlapping the second doped layer 30) and the total length of the first solder joint 50 to be greater than or equal to 20% can effectively ensure the soldering tension of the first solder joint 50 and avoid insufficient soldering tension.

[0077] Preferably, in such embodiments, in order to ensure the soldering tension of the first solder joint 50, the ratio between the length of the first solder joint 50 above the second doped layer 30 and the total length of the first solder joint 50 is greater than or equal to 50%.

[0078] In some embodiments, the ratio between the area of the orthogonal projection of the second doped layer 30 on the second sub-doped layer 22 and the area of the second sub-doped layer 22 is less than 50%. In this way, it can be avoided that the area of the second doped layer 30 is too large, causing the second doped layer 30 to be more likely to recombine with the second sub-doped layer 22, resulting in large recombination loss.

[0079] Specifically, in such embodiments, the "ratio between the area of the orthogonal projection of the second doped layer 30 on the second sub-doped layer 22 and the area of the second sub-doped layer 22 is less than 50%" can be that the ratio between the area of all second doped layers 30 on a single second sub-doped layer 22 and the area of the single second sub-doped layer 22 is less than 50%, or that the ratio between the sum of the areas of all second doped layers 30 on the entire back contact cell and the sum of the areas of all second sub-doped layers 22 is less than 50%, which is not limited in particular and is preferably the first kind.

[0080] Further, as shown in FIG. 11, in such embodiments, in the first direction, the spacing between two adjacent first solder joints 50 is 3-40 mm.

[0081] Therefore, by setting the interval between the two adjacent first soldering points 50 within the reasonable range, the first soldering points 50 can be substantially within the reasonable interval, and thus there are enough first soldering points 50 on the same second sub-doped layer 22, so as to avoid the occurrence of virtual soldering when soldering the solder ribbon, and the reliability of soldering can be ensured.

[0082] Specifically, in such embodiments, the interval between the two adjacent first soldering points 50 can be, for example, 3 mm, 4 mm, 5 mm, 6 mm, 7 mm, 8 mm, 9 mm, 10 mm, 15 mm, 20 mm, 25 mm, 30 mm, 35 mm, 40 mm, or any value between 3 mm and 40 mm, which is not particularly limited herein.

[0083] As shown in FIGS. 7 and 10, in some embodiments, the third doped layer 70 has a plurality of second preset regions 701, and the solar cell sheet 100 can further include a fourth doped layer 110, which is arranged on the second preset regions 701 in a stacked manner, and the polarity of the fourth doped layer 110 is opposite to that of the third doped layer 70.

[0084] As shown in FIG. 7, when the third doped layer 70 is arranged on the second surface 12 in a stacked manner, the second passivation film layer 80 covers the third doped layer 70 and the fourth doped layer 110, the roughness of the surface 111 of the fourth doped layer 110 in contact with the second passivation film layer 80 is greater than the roughness of the surface 702 of the third doped layer 70 in contact with the second passivation film layer 80, and the orthographic projection of the second soldering point 90 on the third doped layer 70 and the orthographic projection of the fourth doped layer 110 on the third doped layer 70 at least partially overlap.

[0085] As shown in FIG. 10, when the third doped layer 70 is arranged on the first surface 11 in a stacked manner, the first passivation film layer 40 covers the first doped layer 20, the second doped layer 30, the third doped layer 70, and the fourth doped layer 110, the roughness of the surface 111 of the fourth doped layer 110 in contact with the first passivation film layer 40 is greater than the roughness of the surface 702 of the third doped layer 70 in contact with the first passivation film layer 40, and the orthographic projection of the second soldering point 90 on the third doped layer 70 and the orthographic projection of the fourth doped layer 110 on the third doped layer 70 at least partially overlap.

[0086] Therefore, the pulling force of the first soldering point 50 during soldering can be improved, and the pulling force of the second soldering point 90 during soldering can also be effectively improved, so as to effectively avoid the disengagement of the second soldering point 90 during soldering.

[0087] Please refer to FIGS. 7 and 10, in some embodiments, the solar cell sheet 100 can further include a second isolation layer 120, which is arranged on the second preset regions 701 in a stacked manner and between the third doped layer 70 and the fourth doped layer 110.

[0088] In this way, the fourth doped layer 110 can be separated from the third doped layer 70 by the second isolation layer 120, so as to avoid direct contact between the two, and at the same time, the passivation effect of the third doped layer 70 can be ensured.

[0089] Of course, it can be understood that in some embodiments, the third doped layer 70 and the fourth doped layer 110 can also be separated without the second isolation layer 120, which is not limited herein.

[0090] In some embodiments, the thickness of the second isolation layer 120 can be greater than 2 nm. In this way, the process difficulty can be greatly increased due to the too small thickness of the second isolation layer 120.

[0091] In addition, in some embodiments, the second isolation layer 120 can include at least one of a silicon oxide film layer, a silicon nitride film layer, an aluminum oxide film layer, a silicon oxynitride film layer, a silicon carbide film layer, and an intrinsic amorphous silicon film layer.

[0092] Specifically, in such embodiments, the second isolation layer 120 can have a tunneling function or can not have a tunneling function, and can be an insulating layer or a non-insulating layer, which is not limited herein, and the specific film layer can be selected according to different types of battery pieces.

[0093] For example, when the battery is a Topcon solar cell and a back contact cell, the second isolation layer 120 can be at least one of a silicon oxide film layer, a silicon nitride film layer, an aluminum oxide film layer, a silicon oxynitride film layer, and a silicon carbide film layer. The second isolation layer 120 can have a tunneling function or can not have a tunneling function.

[0094] When the battery piece is an HJT solar cell, the second isolation layer 120 can be an intrinsic amorphous silicon layer. It can be understood that the specific selection of the second isolation layer 120 is only exemplarily described herein, but it cannot be understood as a limitation of the present application.

[0095] In some embodiments, the orthographic projection of the second solder point 90 on the third doped layer 70 is completely located in the second preset area 701, that is, in the thickness direction of the solar cell piece 100, the second solder point 90 is completely located above the fourth doped layer 110.

[0096] In this way, the second solder point 90 is completely located in the second preset area 701, and the entire lower portion of the second solder point 90 has the fourth doped layer 110, which can maximize the soldering tension at the second solder point 90, thereby ensuring the reliability of the soldering.

[0097] Specifically, in such embodiments, the area of the second preset region 701 can be preferably just equal to the area of the orthographic projection of the second solder joint 90 or slightly larger than the area of the orthographic projection of the second solder joint 90.

[0098] Of course, in some embodiments, the area of the orthographic projection of the second solder joint 90 on the third doped layer 70 can also be larger than the area of the orthographic projection of the fourth doped layer 110 on the third doped layer 70 (i.e. the area of the second preset region 701), for example, a single second solder joint 90 can correspond to multiple fourth doped layers 110, in which case the second solder joint 90 can completely cover the fourth doped layer 110, in which case the ratio of the area of the fourth doped layer 110 overlapping the second solder joint 90 to the total area of the second solder joint 90 can be greater than 20% to avoid too small soldering tension.

[0099] In some embodiments, the thickness of the fourth doped layer 110 can be 5nm-400nm.

[0100] In this way, it can be effectively avoided that the fourth doped layer 110 is too thin to have a poor tension enhancement effect, it can also be avoided that the fourth doped layer 110 is too thin to increase the process difficulty, and it can also be avoided that the fourth doped layer 110 is too thick to increase the cost.

[0101] Specifically, the thickness of the fourth doped layer 110 can be 5nm, 10nm, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, 150nm, 200nm, 250nm, 300nm, 350nm, 400nm or any value between 5nm and 400nm, which is not particularly limited herein.

[0102] Further, as shown in FIG. 11, in the case that the third doped layer 70 is disposed on the first surface 11 and the first doped layer 20 includes a plurality of first sub-doped layers 21 and a plurality of second sub-doped layers 22, the third doped layer 70 includes a plurality of third sub-doped layers 71 and a plurality of fourth sub-doped layers 72, the second sub-doped layer 22 has a plurality of first preset regions 201, the plurality of first preset regions 201 are disposed at intervals along the second direction, and the number of the first solder joints 50 corresponds to the number of the first preset regions 201. The fourth sub-doped layer 72 has a plurality of second preset regions 701, the plurality of second preset regions 701 are disposed at intervals along the first direction, and the number of the second solder joint 90 pairs corresponds to the number of the second preset regions 701, i.e. in such a case, the fourth doped layer 110 is laminated on the second preset region 701 of the fourth sub-doped layer 72.

[0103] As shown in FIG. 11, in such an embodiment, in the first direction, the length of the second solder joint 90 can be greater than the length of the fourth doped layer 110, and the ratio between the length of the second solder joint 90 above the fourth doped layer 110 and the total length of the second solder joint 90 is greater than or equal to 20%.

[0104] Therefore, when the length of the second solder joint 90 in the first direction is large, setting the ratio between the length of the second solder joint 90 above the fourth doped layer 110 (i.e. the length of the orthogonal projection of the second solder joint 90 in the thickness direction overlapping the fourth doped layer 110) and the total length of the second solder joint 90 to be greater than or equal to 20% can effectively ensure the soldering tensile force of the second solder joint 90 and avoid insufficient soldering tensile force.

[0105] Preferably, in such an embodiment, in order to ensure the soldering tensile force of the second solder joint 90, the ratio between the length of the second solder joint 90 above the fourth doped layer 110 and the total length of the second solder joint 90 is greater than or equal to 50%.

[0106] In some embodiments, the ratio between the orthogonal projection area of the fourth doped layer 110 on the fourth sub-doped layer 72 and the area of the fourth sub-doped layer 72 is less than 50%. Therefore, it can be avoided that the area of the fourth doped layer 110 is too large, which can cause the fourth doped layer 110 to be more likely to be recombined with the fourth sub-doped layer 72, resulting in large recombination loss.

[0107] Specifically, in such an embodiment, the "ratio between the orthogonal projection area of the fourth doped layer 110 on the fourth sub-doped layer 72 and the area of the fourth sub-doped layer 72 is less than 50%" can be that the ratio between the area of all fourth doped layers 110 on a single fourth sub-doped layer 72 and the area of the single fourth sub-doped layer 72 is less than 50%, or the ratio between the sum of the areas of all fourth doped layers 110 on the entire back contact cell and the sum of the areas of all fourth sub-doped layers 72 is less than 50%, which is not limited in particular herein, and is preferably the first kind.

[0108] Further, as shown in FIG. 11, in such an embodiment, in the first direction, the spacing between two adjacent second solder joints 90 is 3-40 mm.

[0109] Therefore, by setting the spacing between two adjacent second solder joints 90 in this reasonable range, the second solder joint 90 can be basically within a reasonable spacing, so that there are enough second solder joints 90 on the same fourth sub-doped layer 72, thereby avoiding virtual welding when welding the solder ribbon, and the reliability of welding can also be ensured.

[0110] In particular, in such embodiments, the spacing between two adjacent second soldering points 90 can be, for example, 3 mm, 4 mm, 5 mm, 6 mm, 7 mm, 8 mm, 9 mm, 10 mm, 15 mm, 20 mm, 25 mm, 30 mm, 35 mm, 40 mm, or any value between 3 mm and 40 mm, in particular without being limited hereto.

[0111] In the description of the present specification, the description of the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Also, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in an appropriate manner.

[0112] Although the embodiments of the present application have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions, and alterations can be made hereto without departing from the principles and spirit of the application, and the scope of the present application is defined by the claims and their equivalents.

Claims

1. A solar cell, characterized by, The solar cell comprises: a silicon wafer; a first doped layer stacked on the silicon wafer, the first doped layer having a plurality of first preset regions; a second doped layer stacked on the first preset regions, the second doped layer having a polarity opposite to that of the first doped layer; a first passivation film layer stacked on the second doped layer and the first doped layer, a surface of the second doped layer in contact with the first passivation film layer having a roughness greater than that of a surface of the first doped layer in contact with the first passivation film layer; and a plurality of first soldering points disposed on the first passivation film layer, a projection of the first soldering points on the first doped layer at least partially overlapping a projection of the second doped layer on the first doped layer. The solar cell further comprises a first isolation layer stacked on the first preset regions and located between the first doped layer and the second doped layer.

2. The solar cell according to claim 1, wherein The first isolation layer has a thickness greater than 2 nm.

3. The solar cell according to claim 2, wherein The first isolation layer comprises at least one of a silicon oxide film layer, a silicon nitride film layer, an aluminum oxide film layer, a silicon oxynitride film layer, a silicon carbide film layer, and an intrinsic amorphous silicon film layer.

4. The solar cell of claim 2, wherein, The projection of the first soldering points on the first doped layer is entirely located within the first preset regions.

5. The solar cell of claim 1, wherein, The second doped layer has a thickness of 5 nm to 400 nm.

6. The solar cell of claim 1, wherein, The first passivation film layer comprises at least one of a silicon nitride film layer, an aluminum oxide film layer, a silicon oxynitride film layer, an intrinsic amorphous silicon film layer, and a TCO film layer.

7. The solar cell of claim 1, wherein, The solar cell further comprises a third doped layer having a polarity opposite to that of the first doped layer, a second passivation film layer, and a plurality of second soldering points.

8. The solar cell of claim 1, wherein, In one embodiment, the first doped layer is stacked on a first surface of the silicon wafer, the third doped layer is stacked on a second surface of the silicon wafer, the second passivation film layer is stacked on the third doped layer, and the second soldering points are disposed on the second passivation film layer. In another embodiment, the first doped layer and the third doped layer are both stacked on the first surface of the silicon wafer, the first passivation film layer is stacked on the first doped layer, the second doped layer, and the third doped layer, the second soldering points are also disposed on the first passivation film layer, and the second passivation film layer is stacked on the second surface of the silicon wafer. In the case where the third doped layer is stacked on the first surface, a plurality of the first doped layers and a plurality of the third doped layers are arranged in a first direction on the first surface, and the first doped layers and the third doped layers both extend in a second direction, the second direction being transverse to the first direction.

9. The solar cell of claim 8, wherein, In the case where the third doped layer is stacked on the first surface, the first doped layer comprises a plurality of first sub-doped layers and a second sub-doped layer, and the third doped layer comprises a plurality of third sub-doped layers and a plurality of fourth sub-doped layers.

10. The solar cell of claim 8, wherein, ​ A plurality of first sub-doped layers and a plurality of third sub-doped layers are arranged on the first surface in sequence and alternately along a first direction and extend along a second direction intersecting the first direction; A plurality of second sub-doped layers and a plurality of fourth sub-doped layers are arranged on the first surface in sequence and alternately along the second direction and extend along the first direction, the first sub-doped layer is disconnected at the fourth sub-doped layer and in contact with the second sub-doped layer, and the third sub-doped layer is disconnected at the second sub-doped layer and in contact with the fourth sub-doped layer; The second sub-doped layer has a plurality of first preset regions arranged in sequence and alternately along the second direction.

11. The solar cell of claim 10, wherein, In the first direction, the length of the first solder joint is greater than the length of the second doped layer, and the ratio between the length of the first solder joint above the second doped layer and the total length of the first solder joint is greater than or equal to 20%.

12. The solar cell of claim 10, wherein, In the first direction, the ratio between the length of the first solder joint above the second doped layer and the total length of the first solder joint is greater than or equal to 50%.

13. The solar cell of claim 10, wherein, The ratio between the area of the second doped layer on the second sub-doped layer and the area of the second sub-doped layer is less than or equal to 50%.

14. The solar cell of claim 10, wherein, In the first direction, the spacing between two adjacent first solder joints is 3-40 mm.

15. The solar cell of claim 8, wherein, The third doped layer has a plurality of second preset regions, and the solar cell further comprises a fourth doped layer stacked on the second preset region, the polarity of the fourth doped layer being opposite to that of the third doped layer; In the case where the third doped layer is stacked on the second surface, the second passivation film layer covers the third doped layer and the fourth doped layer, the roughness of the surface of the fourth doped layer in contact with the second passivation film layer is greater than the roughness of the surface of the third doped layer in contact with the second passivation film layer, and the orthogonal projection of the second solder joint on the third doped layer at least partially overlaps with the orthogonal projection of the fourth doped layer on the third doped layer; In the case where the third doped layer is stacked on the first surface, the first passivation film layer covers the first doped layer, the second doped layer, the third doped layer and the fourth doped layer, the roughness of the surface of the fourth doped layer in contact with the first passivation film layer is greater than the roughness of the surface of the third doped layer in contact with the first passivation film layer, and the orthogonal projection of the second solder joint on the third doped layer at least partially overlaps with the orthogonal projection of the fourth doped layer on the third doped layer.

16. The solar cell of claim 15, wherein, The solar cell wafer further comprises a second isolation layer stacked between the third doped layer and the fourth doped layer on the second preset region.

17. The solar cell of claim 15, wherein, The orthogonal projection area of the second preset region on the silicon wafer is greater than or equal to the orthogonal projection area of the second solder joint on the silicon wafer, and the second solder joint is completely located in the second preset region.

18. The solar cell of claim 15, wherein, In the case that the third doped layer is stacked on the first surface, the first doped layer comprises a plurality of first sub-doped layers and second sub-doped layers, and the third doped layer comprises a plurality of third sub-doped layers and a plurality of fourth sub-doped layers; The plurality of first sub-doped layers and the plurality of third sub-doped layers are arranged in sequence and alternately on the first surface along a first direction and extend along a second direction intersecting the first direction; The plurality of second sub-doped layers and the plurality of fourth sub-doped layers are arranged in sequence and alternately on the first surface along the second direction and extend along the first direction, the first sub-doped layer is disconnected at the fourth sub-doped layer and in contact with the second sub-doped layer, and the third sub-doped layer is disconnected at the second sub-doped layer and in contact with the fourth sub-doped layer; The second sub-doped layer has a plurality of first preset regions arranged in sequence along the first direction, and the fourth sub-doped layer has a plurality of second preset regions arranged in sequence along the first direction.

19. A battery assembly characterized by, The solar cell module comprises a plurality of solar cell pieces according to any one of claims 1-18.

20. A photovoltaic system characterized by, The battery assembly comprises the battery module according to claim 19.

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