System and methods for real-time tracking of a charge neutrality point and determining 2d field-effect transistor transfer characteristics

Abstract

A system (100) and method (300) dynamically track a charge neutrality point (CNP) of graphene field effect transistors (gFETs). The system may include gFETs (108) with a graphene channel (114), a source (110) and signal interface circuitry 136 to apply and / or measure electrical signals, a processor (102), and storage (104). A source and measure module (106) modulates a tracking voltage (Vg), compares Vg with a minimum gate voltage (Vg_min) solved for by fitting a curve to current-voltage pairs, and adjusts Vg by range-finding or fine-tuning voltages based on predetermined criteria for CNP determination. The module includes code for signal control by the processor and a CNP tracking pulse code with step-up and step-down gate voltage pulses. Additionally, it configures transfer characteristic scanning cycle parameters, modulates transfer characteristics scanning gate voltages, measures channel current responses, and determines transfer characteristics of the gFETs.

Description

SYSTEM AND METHODS FOR REAL-TIME TRACKING OF A CHARGE NEUTRALITY POINT AND DETERMINING 2D FIELD-EFFECT TRANSISTOR TRANSFER CHARACTERISTICSFIELD

[0001] The subject matter disclosed herein relates to graphene field effect transistors, and more particularly relates to systems, methods, and computer program products for realtime tracking of a charge neutrality point and determining 2D field effect transistor transfer characteristics.BACKGROUND

[0002] Graphene field-effect transistors (gFETs) represent an important advancement in electronic component technology, leveraging the unique properties of graphene to achieve superior electrical performance. The charge neutrality point (CNP) of a gFET is an electrical characteristic marking a gate voltage (Eg) at which the charge carrier density in a graphene channel of the gFET is neutral, meaning that the concentration of electrons and holes is balanced. At the CNP, the graphene channel exhibits minimal conductivity because it is at its most intrinsic state, with the Fermi level aligning closely with the Dirac point, where the valence and conduction bands meet.

[0003] An important aspect of optimizing graphene FET application involves identifying the CNP. Various existing systems and methods describe identifying the CNP by applying a forward gate voltage sweep (e.g., lowest Vgvalue to highest Vgvalue) and / or reverse gate voltage sweep (e.g., lowest Vgvalue to highest Vgvalue), generating an I-Vg(currentvoltage) curve, also known as a transfer curve. Plotting the I-Vgcurve with channel current on a y-axis and gate voltage on an x-axis allows identification of the CNP as the (x,y) point on the I- Eg curve at which the graphene channel exhibits minimal conductivity.

[0004] In various existing systems, Vgsweeps may be performed using a processor to control and cause a digital -to-analog converter to output the Vgpoints or values on the I-Vgcurve, and the channel current of the gFET is converted to a digital value that is read by the processor as the I points or values on the I-Vscurve or transfer curve.

[0005] Because of the usefulness of being able to determine the CNP of a gFET, where the CNP of a gFET is changing, for example, due to environmental conditions, various existing systems and methods update the determination of the CNP by performing continuous digitized Vgsweeps to generate updated I-Vscurves from which an updated CNP is determined.

[0006] Certain existing systems and methods account for the fact that charge trapping and other factors may cause the results of the forward sweeps to vary from the results of the reverse sweeps by consistently selecting a CNP value determined from only one of the sweep directions or by adjusting a CNP value based on information from both forward sweeps and reverse sweeps.

[0007] Circuits and / or processes such as those disclosed herein for reliably finding and tracking an accurate CNP value of agFET are not found in existing systems. Similarly, existing systems lack circuits and / or processes for using an accurately tracked CNP value of a gFET as a basis for accurately determining transfer characteristics of a gFET that may change due to the presence, absence, and / or concentration of a selected analyte.SUMMARY

[0008] In various implementations, the techniques described herein relate to a system for dynamically tracking a charge neutrality point (CNP) of one or more graphene field effect transistors (gFETs), the system including the one or more graphene field effect transistors (gFETs) each including a graphene channel between a source and a drain; signal interface circuitry configured to apply and / or measure electrical signals for the drain and the source of each gFET and to source and / or measure an electrical signal that serves as a gate voltage for the gFET. In some implementations, the system includes a processor and a non-volatile storage medium.

[0009] The system, in such implementations, further includes a source and measure module configured to modulate a present tracking voltage (Eg) that serves as a gate voltage for the gFET with a CNP tracking pulse code configured according to a set of pulse code parameters for a present tracking cycle of a plurality of CNP tracking cycles for the gFET. The source and measure module is further configured to compare the present tracking voltage (Vg) with a present minimum gate voltage (F _min) solved for by fitting a curve to three currentvoltage pairs on a current-voltage response curve (I-Vgcurve) of the gFET based on channel current responses to the gate voltages applied according to the set of pulse code parameters for the present tracking cycle.

[0010] The excitation measurement module, in some implementations, is further configured to adjust the present tracking voltage Vgby an incremental range finding voltage in response to determining that three current-voltage pairs do not meet one or more criteria indicating that the present tracking voltage is within a predetermined range for determining a CNP voltage for the present tracking cycle using the Fg_min solved for by fitting the curve andto adjust the present tracking voltage , by a fine-tuning voltage in response to determining that three current-voltage pairs meet one or more criteria indicating that the present tracking voltage is within a predetermined range for determining a present CNP voltage for the present tracking cycle using the Vg mjnsolved for by fitting the curve.

[0011] In certain implementations, the source and measure module is further configured to set the present CNP voltage to be the present tracking voltage and set a present CNP current to be the minimum current solved for by fitting the curve, wherein the source and measure module includes: code executable by the processor to cause the signal interface circuitry to apply and / or measure electrical signals for the gate, drain, and source of the one or more gFETs and to control the one or more reference electrodes.

[0012] In some aspects, the techniques described herein relate to a method for dynamically tracking a charge neutrality point (CNP) of a graphene field effect transistor (gFET) including a graphene channel between a source and a drain by iteratively performing a plurality of CNP tracking cycles that include: modulating a present tracking voltage (Vg) to serve as present gate voltages for the gFET with a CNP tracking pulse code configured according to a set of pulse code parameters for a present tracking cycle of a plurality of charge neutrality point tracking cycles for the gFET; comparing the present tracking voltage (Vg) with a present minimum gate voltage (Fg mm) solved for by fitting a curve to three current-voltage pairs on a current-voltage response curve (I-Vgcurve) of the gFET based on channel current responses / stimeasuring current between the source and the drain of the gFET to the present gate voltages applied according to the set of pulse code parameters for the present tracking cycle; adjusting the present tracking voltage Vgby an incremental range finding voltage in response to determining that three current-voltage pairs do not meet one or more predetermined criteria indicating that the present tracking voltage is within a predetermined range for determining a CNP voltage for the present tracking cycle using the Fg min solved for by fitting the curve; adjusting the present tracking voltage , by a fine tuning voltage in response to determining that three current-voltage pairs meet one or more criteria indicating that the present tracking voltage is within the predetermined range for determining a present CNP voltage for the present tracking cycle using the Fg min solved for by fitting the curve; and setting the present CNP voltage to be the present tracking voltage and setting a present CNP current to be a minimum current / sti_min at theg_nnn solved for by fitting the curve.

[0013] In various aspects, the techniques described herein relate to a method, further including: configuring a set of a transfer characteristic (TC) scanning cycle parameters for the gFET including a selected number of TC scanning cycles and gate voltage levels forperforming a set of TC scanning cycles that span a selected TC scanning voltage range for the gFET; modulating a present TC scanning voltage Vgthat serves as a gate voltage for the gFET with a TC scanning pulse code configured according to a set of pulse code parameters for a present TC scanning cycle of the set of TC scanning cycles, wherein a pulse voltage magnitude parameter for pairs of step-up gate voltage pulses and step-down gate voltage pulses is changed by a TC scanning voltage adjustment between pairs so that by modulating the TC scanning voltage over the selected number of gate voltage pulses, the set of TC scanning cycles spans the selected TC scanning voltage range; measuring a present channel current response to the pairs of step-up gate voltage pulses and step-down gate voltage pulses as changed by the TC scanning voltage adjustment for the present TC scanning cycle over the selected number of gate voltage pulses for the set of TC scanning cycles; and determining one or more transfer characteristic parameters of the gFET based on the measurements performed over the set of TC scanning cycles.

[0014] In certain aspects, the techniques described herein relate to a computer program product for dynamically tracking a charge neutrality point (CNP) of a graphene field effect transistor (gFET) including a graphene channel between a source and a drain by iteratively performing a plurality of charge neutrality point tracking cycles, the computer program product including a computer readable storage medium storing code, the code being configured to be executable by a processor to perform operations including: modulating a present tracking voltage (Eg) to serve as present gate voltages for the gFET with a CNP tracking pulse code configured according to a set of pulse code parameters for a present tracking cycle of a plurality of charge neutrality point tracking cycles for the gFET; comparing the present tracking voltage (Eg) with a present minimum gate voltage (Eg min) solved for by fitting a curve to three currentvoltage pairs on a current-voltage response curve (I-Vgcurve) of the gFET based on channel current responses 7sd measuring current between the source and the drain of the gFET to the present gate voltages applied according to the set of pulse code parameters for the present tracking cycle; adjusting the present tracking voltage Vgby an incremental range finding voltage in response to determining that three current-voltage pairs do not meet one or more predetermined criteria indicating that the present tracking voltage is within a predetermined range for determining a CNP voltage for the present tracking cycle using the Fg_min solved for by fitting the curve; adjusting the present tracking voltage Vgby a fine tuning voltage in response to determining that three current-voltage pairs meet one or more criteria indicating that the present tracking voltage is within the predetermined range for determining a present CNP voltage for the present tracking cycle using the Fg_min solved for by fitting the curve; andsetting the present CNP voltage to be the present tracking voltage and setting a present CNP current to be a minimum current 7sd_min at the min solved for by fitting the curve.

[0015] In some aspects, the techniques described herein relate to a computer program product, including further code being configured to be executable by a processor to perform further operations including: configuring a set of a transfer characteristic (TC) scanning cycle parameters for the gFET including a selected number of TC scanning cycles and gate voltage levels for performing a set of TC scanning cycles that span a selected TC scanning voltage range for the gFET; modulating a present TC scanning voltage Vgthat serves as a gate voltage for the gFET with a TC scanning pulse code configured according to a set of pulse code parameters for a present TC scanning cycle of the set of TC scanning cycles, wherein a pulse voltage magnitude parameter for pairs of step-up gate voltage pulses and step-down gate voltage pulses is changed by a TC scanning voltage adjustment between pairs so that by modulating the TC scanning voltage over the selected number of gate voltage pulses, the set of TC scanning cycles spans the selected TC scanning voltage range; measuring a present channel current response to the pairs of step-up gate voltage pulses and step-down gate voltage pulses as changed by the TC scanning voltage adjustment for the present TC scanning cycle over the selected number of gate voltage pulses for the set of TC seaming cycles; and determining one or more transfer characteristic parameters of the gFET based on the measurements performed over the set of TC seaming cycles.BRIEF DESCRIPTION OF THE DRAWINGS

[0016] So that the advantages of the subject matter of the present disclosure will be readily mderstood, a more particular description of the features briefly described above will be rendered by reference to specific examples that are illustrated in the appended drawings. Understanding that these drawings depict only typical examples of the disclosed subject matter and are not therefore to be considered to be limiting to the scope of the claims, the disclosed subject matter will be described and explained with additional specificity and detail through the use of the accompanying drawings, in which:

[0017] FIG. 1 is a schematic block diagram illustrating a system for finding and tracking a CNP voltage of a gFET and performing a modulated pulse code TC scan of the gFET, according to one or more examples of the present disclosure;

[0018] FIG. 2A is a schematic cross-sectional diagram of a fluid-gated gFET in which a system as depicted in FIG. 1 is configured to use digitized gate voltage sweeps for determining a transfer curve or transfer characteristics such as a charge neutrality point wherethe diagram illustrates a potential for cumulative charge effects due to Vssweep time at levels not near a CNP voltage, according to one or more examples of the present disclosure;

[0019] FIG. 2B is a schematic block diagram illustrating the non-Markovian behavior of a channel current response when the system of FIG. 1 is configured to use continuous digitized gate voltage sweeps for determining transfer characteristics, according to one or more examples of the present disclosure;

[0020] FIG. 2C is a schematic block diagram illustrating electric field effects on surface chemistry structure, analyte structure, and reaction kinetics when the system of FIG. 1 is configured to use continuous digitized gate voltage sweep, according to one or more examples of the present disclosure;

[0021] FIG. 3 is a high-level schematic flowchart diagram illustrating a method for tracking a charge neutrality point and determining gFET transfer characteristics, according to one or more examples of the present disclosure;

[0022] FIG. 4 is a working example illustrating selected steps of a method for tracking a charge neutrality point, according to one or more examples of the present disclosure;

[0023] FIG. 5 is a detailed schematic flowchart diagram illustrating a method for tracking a charge neutrality point, according to one or more examples of the present disclosure;

[0024] FIG. 6 is a graph illustrating starting from a tracked CNP and performing a set of modulated Vg pulse code transfer characteristic (TC) scanning cycles over a characterization window, according to one or more examples of the present disclosure;

[0025] FIG. 7 is a graph derived from a working example illustrating starting from a tracked CNP and measuring a set of channel current Is<i responses to the modulated pulse code scanning cycle, according to one or more examples of the present disclosure;

[0026] FIG. 8 is a graph derived from a working example illustrating starting from a tracked CNP and measuring a set of capacitive charging currents for the modulated Vg pulse code scanning cycle, according to one or more examples of the present disclosure;

[0027] FIG. 9A is a set of three graphs derived from a working example illustrating that using modulate gate voltage scans to find and track a CNP and determine transfer characteristics of a gFET results in Markovian responses over various Vg scan rates, directions, and ranges, according to one or more examples of the present disclosure;

[0028] FIG. 9B is a set of graphs of results from a working example illustrating that using modulate gate voltage scans to first find and track a CNP and then using pulsed Vg scans that start from and return to the tracked VCNP enables more accurate determination of transfer characteristics of a gFET, according to one or more examples of the present disclosure;

[0029] FIG. 9C is a working example illustrating that using modulate gate voltage scans to find and track a CNP and determine transfer characteristics of a gFET enables improved characterization window efficiency and reduced impact of an electric field to surface chemistries, according to one or more examples of the present disclosure;

[0030] FIG. 10 is a schematic block diagram illustrating a system for concurrently finding and tracking CNP voltages for multiple fluid-gated gFETs, according to one or more examples of the present disclosure; and

[0031] FIG. 11 is a schematic flowchart diagram illustrating a method for tracking a charge neutrality point and determining transfer characteristics, according to one or more examples of the present disclosure.DETAILED DESCRIPTION

[0032] Disclosure Reading Guidelines

[0033] As will be appreciated by one skilled in the art, aspects of the disclosure may be embodied as a system, method, or program product. Accordingly, examples including implementations / examples may take the form of an entirely hardware implementation, an entirely software implementation (including firmware, resident software, micro-code, etc.), or an implementation combining software and hardware aspects that may all generally be referred to herein as a “circuit,” “module,” or “system.” Furthermore, implementation may take the form of a program product embodied in one or more computer readable storage media and / or devices storing machine-readable code, computer readable code, and / or program code, referred to hereafter as code. The storage media and / or devices may be tangible, non-transitory, and / or non-transmission. In various examples, the storage media and / or devices may not embody signals. In certain examples, the storage devices only employ signals for accessing code.

[0034] Certain of the functional units described in this specification have been labeled as modules, to more particularly emphasize their implementation independence. For example, a module may be implemented as a hardware circuit comprising custom VLSI circuits or gate arrays, off-the-shelf semiconductors such as logic chips, transistors, or other discrete components. A module may also be implemented in programmable hardware devices such as field programmable gate arrays, programmable logic devices, or the like.

[0035] Modules may also be implemented in code and / or software for execution by various types of processors. An identified module of code may, for instance, comprise one or more physical or logical blocks of executable code which may, for instance, be organized as an object, procedure, or function. Nevertheless, the executables of an identified module neednot be physically located together but may comprise disparate instructions stored in different locations which, when joined logically together, comprise the module and achieve the stated purpose for the module.

[0036] Indeed, a module of code may be a single instruction, or many instructions, and may even be distributed over several different code segments, among different programs, and across several memory devices. Similarly, operational data may be identified and illustrated herein within modules and may be embodied in any suitable form and organized within any suitable type of data structure. The operational data may be collected as a single data set or may be distributed over different locations including over different computer readable storage devices. Where a module or portions of a module are implemented in software, the software portions are stored on one or more computer readable storage devices.

[0037] Any combination of one or more computer readable mediums may be utilized. The computer readable medium may be a computer readable storage medium. The computer readable storage medium may be a storage device storing the code. The storage device may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, holographic, micromechanical, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing.

[0038] More specific examples (a non-exhaustive list) of the storage device would include the following: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random-access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this document, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.

[0039] Code for carrying out operations, for example, may be written in any combination of one or more programming languages including an object-oriented programming language such as Python, Ruby, Java, Smalltalk, C++, or the like, and conventional procedural programming languages, such as the “C” programming language, or the like, and / or machine languages such as assembly languages. The code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer, and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network(WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet Service Provider).

[0040] A component, as used herein, comprises a tangible, physical, non-transitory device. For example, a component may be implemented as a hardware logic circuit comprising custom VLSI circuits, gate arrays, or other integrated circuits; off-the-shelf semiconductors such as logic chips, transistors, or other discrete devices; and / or other mechanical or electrical devices. A component may also be implemented in programmable hardware devices such as field programmable gate arrays, programmable array logic, programmable logic devices, or the like. A component may comprise one or more silicon integrated circuit devices (e.g., chips, die, die planes, packages) or other discrete electrical devices, in electrical communication with one or more other components through electrical lines of a printed circuit board (PCB) or the like. Each of the modules described herein, in certain examples, may alternatively be embodied by or implemented as a component.

[0041] A circuit, or circuitry, as used herein, comprises a set of one or more electrical and / or electronic components providing one or more pathways for electrical current. In certain examples, circuitry may include a return pathway for electrical current, so that a circuit is a closed loop. In some examples, however, a set of components that does not include a return pathway for electrical current may be referred to as a circuit or as circuitry (e.g., an open loop). For example, an integrated circuit may be referred to as a circuit or as circuitry regardless of whether the integrated circuit is coupled to ground (as a return pathway for electrical current) or not. In various examples, circuitry may include an integrated circuit, a portion of an integrated circuit, a set of integrated circuits, a set of non-integrated electrical and / or electrical components with or without integrated circuit devices, or the like.

[0042] In one or more examples, a circuit may include custom VLSI circuits, gate arrays, logic circuits, or other integrated circuits; off-the-shelf semiconductors such as logic chips, transistors, or other discrete devices; and / or other mechanical or electrical devices. A circuit may also be implemented as a synthesized circuit in a programmable hardware device such as a field programmable gate array, programmable array logic, programmable logic device, or the like (e.g., as firmware, a netlist, or the like). A circuit may comprise one or more silicon integrated circuit devices (e.g., chips, die, die planes, packages) or other discrete electrical devices, in electrical communication with one or more other components through electrical lines of a printed circuit board (PCB) or the like. Each of the modules described herein, in certain examples, may be embodied by or implemented as a circuit.

[0043] Reference throughout this specification to “one example,” “an example,” or similar language means that a particular feature, structure, or characteristic described in connection with the example is included in at least one example of the present disclosure. Appearances of the phrases “in one example,” “in an example,” and similar language throughout this specification may, but do not necessarily, all refer to the same example. Similarly, the use of the term “implementation” means an implementation having a particular feature, structure, or characteristic described in connection with one or more examples of the present disclosure, however, absent an express correlation to indicate otherwise, an implementation may be associated with one or more examples.

[0044] The described features, structures, advantages, and / or characteristics of the subject matter of the present disclosure may be combined in any suitable manner in one or more examples, including embodiments and / or implementations. In the following description, numerous specific details are provided to impart a thorough understanding of examples of the subject matter of the present disclosure. One skilled in the relevant art will recognize that the subject matter of the present disclosure may be practiced without one or more of the specific features, details, components, materials, and / or methods of a particular example, embodiment, or implementation.

[0045] In other instances, additional features and advantages may be recognized in certain examples, embodiments, and / or implementations that may not be present in all examples, embodiments, or implementations. Further, in some instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the subject matter of the present disclosure. The features and advantages of the subject matter of the present disclosure will become more fully apparent from the following description and appended claims, or may be learned by the practice of the subject matter as set forth hereinafter.

[0046] Aspects of the examples are described below concerning schematic flowchart diagrams and / or schematic block diagrams of methods, apparatuses, systems, and program products according to one or more examples. It will be understood that each block of the schematic flowchart diagrams and / or schematic block diagrams, and combinations of blocks in the schematic flowchart diagrams and / or schematic block diagrams, can be implemented by code. This code may be provided to a processor of a general -purpose computer, special-purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable dataprocessing apparatus, create means for implementing the functions / acts specified in the schematic flowchart diagrams and / or schematic block diagrams block or blocks.

[0047] The code may also be stored in a storage device that can direct a computer, other programmable data processing apparatus, or other devices to function in a particular manner, such that the instructions stored in the storage device produce an article of manufacture including instructions which implement the function / act specified in the schematic flowchart diagrams and / or schematic block diagrams block or blocks.

[0048] The code may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatuses, or other devices to produce a computer implemented process such that the code which executes on the computer or other programmable apparatus provide processes for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0049] The schematic flowchart diagrams and / or schematic block diagrams in the Figures illustrate the architecture, functionality, and operation of possible implementations of apparatuses, systems, methods, and program products according to various examples. In this regard, each block in the schematic flowchart diagrams and / or schematic block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions of the code for implementing the specified logical function(s).

[0050] It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the Figures. For example, two blocks shown in succession may be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. Other steps and methods may be conceived that are equivalent in function, logic, or effect to one or more blocks, or portions thereof, of the illustrated Figures.

[0051] Although various arrow types and line types may be employed in the flowchart and / or block diagrams, they are understood not to limit the scope of the corresponding examples. Indeed, some arrows or other connectors may be used to indicate only the logical flow of the depicted example. For instance, an arrow may indicate a waiting or monitoring period of unspecified duration between enumerated steps of the depicted example. It will also be noted that each block of the block diagrams and / or flowchart diagrams, and combinations of blocks in the block diagrams and / or flowchart diagrams, can be implemented by special purpose hardware -based systems that perform the specified functions or acts, or combinations of special purpose hardware and code.

[0052] The description of elements in each figure may refer to elements of proceeding figures. Like numbers refer to like elements in all figures, including alternate examples of like elements. For example, like numbers may refer to three-digit numbers with different starting digits and the same ending digits.

[0053] As used herein, a list with a conjunction of “and / or” includes any single item in the list or a combination of items in the list. For example, a list of A, B, and / or C includes only A, only B, only C, a combination of A and B, a combination of B and C, a combination of A and C, or a combination of A, B, and C. As used herein, a list using the terminology “one or more of’ includes any single item in the list or a combination of items in the list. For example, one or more of A, B, and C includes only A, only B, only C, a combination of A and B, a combination of B and C, a combination of A and C, or a combination of A, B, and C. As used herein, a list using the terminology “one of’ includes one and only one of any single item in the list. For example, “one of A, B, and C” includes only A, only B, or only C and excludes combinations of A, B, and C. As used herein, “a member selected from the group consisting of A, B, and C,” includes one and only one of A, B, or C, and excludes combinations of A, B, and C. As used herein, “a member selected from the group consisting of A, B, and C and combinations thereof’ includes only A, only B, only C, a combination of A and B, a combination of B and C, a combination of A and C or a combination of A, B, and C.

[0054] Definitions:

[0055] The term “integrated circuit,” as used herein, refers to a plurality of circuits or circuit components formed on a common substrate. For example, an integrated circuit may include a plurality of transistors. As another example, an integrated circuit may include one or more transistors with peripheral components such as resistors, capacitors, voltage regulators, or the like. Although the term “integrated circuit” is sometimes used in the semiconductor industry to refer to digital circuits such as microprocessors with millions or billions of transistors, the term may refer to digital and / or analog circuits, and circuits with as few as two components integrated on the same substrate. Examples of a substrate for an integrated circuit include silicon, silicon oxide, or another non-conductive substrate formed above a silicon wafer or chip, plastics, fiberglass, polymers, glass, or other conductive or non-conductive substances, which may or may not be silicon-based. Some integrated circuits may be manufactured using layered processing similar to integrated circuit processes for silicon chips, applied with any desired modifications to materials other than silicon chips.

[0056] The term “graphene,” as used herein, refers to a very well-known two- dimensional material referring to an allotrope of carbon comprising a single layer of carbonatoms in a hexagonal lattice. A “graphene layer structure,” as used herein, refers to one or more layers of graphene. Accordingly, in the present disclosure, terms such as a graphene device, graphene transistor, graphene sensor, and the like, relate to structures and devices that include a graphene layer structure and may comprise a monolayer of graphene as well as multilayer graphene. A graphene layer structure preferably has from 1 to 10 monolayers of graphene. In many subsequent device applications (e.g., a field-effect transistor, and in particular sensors such as a hall-effect sensor), one monolayer of graphene is particularly preferred. Accordingly, the graphene layer structure is preferably a graphene monolayer. Nevertheless, multilayer graphene may be preferable for certain applications and 2 or 3 layers of graphene may be preferred.

[0057] The terms “two-dimensional field effect transistor” or “2D FET,” as used herein, refer to a transistor where current between source and drain terminals, through one or more channels comprising a 2D nanomaterial such as graphene, molybdenum disulfide, phosphorene, transition metal dichalcogenides, or similar 2D material, can be modulated by events occurrences, or interactions that affect the conductivity of the channel(s). The term “2D FET” may be sometimes used in industry to refer to entirely solid-state devices where the output current of the 2D material channel is modulated via a gate terminal or a body terminal. Certain 2D FETs disclosed herein are fluid-gated, meaning that current through the 2D material channel(s) is modulated or affected by events, occurrences, or interactions within a fluid in contact with the channel(s). For example, an interaction of ions, molecules, or moieties within the fluid, or an interaction between the channel surface and ions, molecules, or moieties within the fluid, may be capable of gating, modulating, or affecting the channel current. The term “2D FET” may be used to refer to such a device in use, with a fluid applied to the surface of the channel, or to the same device before the fluid has been applied.

[0058] The terms “graphene field effect transistor” or “gFET,” as used herein, refer to a 2D FET where current between source and drain terminals, through one or more graphene channels, can be modulated by events occurrences, or interactions that affect the conductivity of the graphene channel(s). Although the term “graphene field effect transistor” is sometimes used in industry to refer to entirely solid-state devices where the output current of the graphene channel is modulated via a gate terminal or a body terminal, the 2D FETs disclosed herein are fluid-gated, meaning that current through the graphene channel(s) is modulated or affected by events, occurrences, or interactions within a fluid in contact with the channel(s). For example, an interaction of ions, molecules, or moieties within the fluid, or an interaction between the channel surface and ions, molecules, or moieties within the fluid, may be capable of gating,modulating, or affecting the channel current (defined below). The term “graphene field effect transistor” may be used to refer to such a device in use, with a fluid applied to the surface of the channel, or to the same device before the fluid has been applied.

[0059] Furthermore, the term “graphene field effect transistor” or “2D FET” may be used without regard to whether current is modulated by an external power source, the interactions of ions, molecules, or moieties within the applied fluid, or a combination of the two. For example, a graphene field effect transistor or 2D FET may be gated by an external voltage applied to the fluid in addition to biochemical interactions occurring in the fluid, but may still be referred to as a “graphene field effect transistor.” In various examples of the present disclosure, the term “graphene field effect transistor” or gFET is used to describe one or more examples including working examples of a 2D FET with a graphene channel. As used herein term macro gFET refers to a gFET with at least one channel dimension greater than 1 mm as compared to a micro gFET which could be used to refer to a gFET with channel dimensions less than 1 mm.

[0060] The terms "charge neutrality point,” “CNP,” “Dirac point,” or “DP” as used herein, may be used to refer to the condition or point at which the gate voltage (Vg) applied to the graphene transistor results in an equal number of electrons and holes within the graphene channel, thereby minimizing the channel current 7sd to its lowest practical value. This point signifies a state of electrical neutrality within the graphene channel, where the conductivity is minimally affected by charge carriers, and the device exhibits an intrinsic semiconductor behavior. The term “CNP” may also be used as a noun modifier with appropriate subscription or prepending. For example, PcNpmay be used to refer to the voltage at the charge neutrality point, 7CNP may be used to refer to the channel current at the charge neutrality point, CNP tracking voltage may be used to refer to a voltage used to help track a CNP, and so forth.

[0061] The CNP is useful for the calibration and operation of graphene-based transistors, serving as a reference point for the tuning of device properties, such as conductivity and charge carrier mobility. It enables the precise control of electronic characteristics of the graphene transistor for various applications, including but not limited to, sensors, switches, and high-frequency electronic devices.

[0062] The CNP can be determined experimentally by measuring the channel current (e.g., denoted “7” “7Sd,” or “Ids”) as a function of the gate voltage (Fg) and identifying the gate voltage value at which the channel current reaches its minimum. The channel current at FCNP may be denoted 7CNP. This measurement is typically performed under controlled environmental conditions to ensure the accuracy and repeatability of the CNP determination.

[0063] The term “true” as applied to various CNP-related values such as the charge neutrality point voltage FCNP as used herein refers to enhanced accuracy CNP values for which errors brought about by non-Markovian cumulative effects of slow charges and shifts in the CNP value due to accumulation of slow charges near the gFET channel are substantially diminished by using modulated Vgpulse code seaming for find FCNP and to track FCNP to be used as a baseline voltage for performing pulsed code transfer characteristic scans across a characterization window that may be a full range or a subset range of gate voltages Vgfor the gFET. Once a true FCNP value is determined, other true or enhanced accuracy values may be determined, for example, for parameters such as FCNP, or transconductance, gm, which is defined as the ratio of the change in the output current of the transistor to the change in the input voltage (typically the gate voltage, Vgthat causes it, and the accuracy of gmis affected by the accurate determination of FCNP. Other parameters related to FCNP may also be determined with enhanced accuracy.

[0064] In some circumstances, systems and methods described herein concerning gFETs may also apply to 2D FETs that can be implemented with channels formed or patterned in 2D materials other than graphene consistent with the present disclosure. Of particular note are 2D FETs that may exhibit a charge neutrality point (CNP) (defined below) substantially similar to that of gFETs. Some notable examples include transition metal dichalcogenides (TMDCs) FETs, black phosphorus (phosphorene) FETs, Boron nitride (h-BN) encapsulated 2D FETs, silicene FETs, germanene FETs, and so forth. TMDCs such as M0S2, WS2, MoSe2, and WSe2, and combinations thereof, are semiconducting 2D materials that have been widely studied for their potential in FETs. 2D FETs with channel material other than graphene may require adjustments to some of the method steps based on the shape of the transfer curves, such as, adjustment to curve fitting approaches for determining a Vg minfor range find or tracking.

[0065] Black phosphorus, or phosphorene, is another 2D material that has beneficial semiconducting properties, including an adjustable bandgap based on the number of layers. Phosphorene FETs can exhibit a CNP and possess high carrier mobility and on / off ratios, making them suitable for various electronic applications. While hexagonal boron nitride (h- BN) itself is an insulator, it may be used in conjunction with other 2D materials like graphene or TMDCs to create heterostructures. These devices can also exhibit a CNP, with h-BN serving to improve the device's overall performance by providing a cleaner, more controlled interface than SiO2 substrates. Silicene and germanene are silicon and germanium analogs of graphene, respectively which are 2D materials with a honeycomb lattice structure that may exhibit a CNP.These materials may possess a mixed sp2and sp3hybridization, leading to a small bandgap suitable for operating with a CNP.

[0066] The term “gate voltage” denoted in electrical notation herein as “Kg” and variations thereof may refer to the electrical potential applied to the gate electrode of a graphene transistor, capable of modulating the charge carrier density within the graphene channel. In the case of so-called fluid-gated gFETs, the gate electrode may be a single reference electrode that sources and / or measures a gate voltage Vgof a fluid on or above the graphene channel, and thereby the fluid serves as a gate for the graphene channel. In some implementations multiple and in some cases independently controlled reference electrodes may be used for sourcing and / or measuring Vg. In certain implementations, a separate reference electrode or counter electrode may be used for sourcing Eg to the fluid than a reference electrode used for measuring the Vsat the fluid.

[0067] The term "channel current," as used herein, refers to the electric current that flows through the "channel" of a transistor. Specifically, in the context of a graphene-based field-effect transistor (gFET), the channel is formed by a graphene sheet. The channel current is denoted by the electrical notation 7, or in some contexts Is<i or Ids where the subscripts ‘s’ and ‘d’ refer to the "source" and "drain" terminals or electrodes of the FET, respectively. By convention, a direction of the current flow, whether from drain to source or source to drain, may be indicated by the order of these subscripts, but the operational principles remain consistent regardless of directionality. Accordingly, the present disclosure uses the electrical notation Ad as a short form of the term channel current that can be used with or without the words “channel current” preceding the “Ad” without regard to the direction of the current flow, unless otherwise clear from the context. The inclusion of further subscript notations such as numbers, letters, or symbols, as in / sti-. Ad-, Ado, Adi, andstishould be understood to refer to a specific channel current response distinguished by the respective further notations.

[0068] The term “output signal” as used herein, refers to a measurable or detectable electrical signal from an integrated circuit, a 2D FET, such as a gFET, or an array of gFETs or other 2D FETs, or to a result that can be calculated based on the measurable or detectable signal. For example, an output signal may be a voltage at one or more terminals of an integrated circuit, a current at one or more integrated circuits, a capacitance, inductance, or resistance (calculated based on applied and measured voltages and currents), a complex-valued impedance, a complex impedance spectrum, an electrochemical impedance spectrum, a threshold voltage, a transfer curve, a Dirac voltage, a power spectral density, one or more network parameters (such as S-parameters or h-parameters), or the like.

[0069] The term “excitation condition,” as used herein, refers to a physical, electrical, or chemical condition applied to an integrated circuit, a gFET or other 2D FET, or an array of gFETs or other 2D FETs, or to a sample for measurement by an integrated circuit, a gFET or other 2D FETs, or an array of gFETs or other 2D FETs. Excitation conditions may affect ions, molecules, or moieties in the fluid applied to gFETs or other 2D FETs, which in turn may affect one or more output signals from the 2D FET. For example, excitation conditions may include voltages, currents, frequencies, amplitudes, phases, or waveforms of electrical signals applied to a graphene field effect transistor, one or more temperatures, one or more fluid flow rates, one or more wavelengths of electromagnetic radiation, or the like.

[0070] The term “distance,” as used herein regarding a distance from the surface of a channel in a biologically gated transistor, refers to a distance between a point (e.g., in the sample fluid), and the closest point of the channel surface to that point. For example, the distance from the surface of the channel to a point directly above the channel in the sample fluid is the distance between a point on the channel surface to the point in the sample fluid along a line that is normal (perpendicular) to the channel surface.

[0071] The term “bias” as used herein refers to an electrical signal or waveform applied to an electrode or terminal of a 2D FET, such as a conductive source, a conductive drain, a counter electrode, or another electrode. It should be noted that the counter electrode is configured to apply a biasing voltage to a fluid that serves as a gate in 2D FETs as disclosed herein. However, 2D FETs as described herein do not have a metalized gate electrode positioned above or below the channel which is why 2D FETs as disclosed herein are referred to as fluid-gated. The term “programmable bias” is used to refer to a bias that is capable of being changed, varied, or modulated by the circuitry that applies the bias. Examples of programmable biases include a constant voltage or current selected by bias circuitry, a square wave, a sine wave, a more complicated waveform such as a sum of sine waves of various amplitudes, frequencies, and phases (possibly also including a zero-frequency or DC offset component), or the like.

[0072] The terms “target” or “target substance” as used herein, refers to a chemical or biological substance that is of interest in an assay using an integrated circuit, a 2D FET, or an array of 2D FETs as one or more sensing elements. “Direct or indirect target substance signal measurement” is used to refer to measuring one or more signals (e.g., output signals from a 2D FET array) that pertain to a target. Measurement and analysis of such signals may determine a parameter such as the presence, absence, or concentration of the target substance in a fluid.Examples of targets include ions, small molecules, chemical compounds, proteins, bacteria, viruses, cells, nucleic acid molecules, and the like.

[0073] Technology Overview and Introduction

[0074] In the following introduction, various technology aspects developed and / or tested by the authors of the present disclosure that relate to gFETs, tracking of the charge neutrality point of a gFET, and performing modulated Vgpulse code scans of gFETs to determine transfer characteristics of a selected gFET operating in a dynamic environment are introduced. In the description of the individual figures, it should be noted that the aspects disclosed herein can be generally applicable to the individual examples described concerning various of the Figures and that the structures and processes disclosed concerning each of the individual examples may be implemented in a wide range of combinations with aspects of other examples.

[0075] FIG. 1 is a schematic block diagram illustrating a system 100 for CNP tracking 302 which includes range finding and fine-tuning tracking of a CNP for a gFET 108 and for performing a modulated pulse code transfer characteristic scan 308 of the gFET, according to one or more examples of the present disclosure.

[0076] The Dirac point, or charge neutrality point (abbreviated CNP as set forth above), is an important and useful parameter in the operation of various types of gFETs. This point represents the gate voltage at which the graphene's charge carrier density is minimized, and the material behaves as a true semimetal or gapless semiconductor. At the CNP, the conductivity of graphene reaches a minimum because it transitions between n-type and p-type behavior, depending on the gate voltage applied.

[0077] The structures and functions of the system 100 and the method 300 to perform CNP tracking 302 (which may include range finding 304 and tracking 306 the CNP with finetuning) represent a significant improvement to the field of graphene -based electronics and can be highly beneficial for several reasons. Among multiple beneficial reasons is that CNP tracking and the techniques used of CNP track, enhance the ability to perform modulated Vgpulse code transfer characteristic scans 308 that can have greater accuracy and efficiency for determining transfer characteristics that may be changing due to changing conditions to which the gFET 108 is undergoing or being subjected.

[0078] In various examples, the system 100 includes one or more gFETs 108. Several types of gFETs 108 may be included in the system 100. The depicted gFETs 108 (e.g., 108a, 108b, 108c) each include a graphene channel 114 between a source 110 and a drain 112. The graphene channel 114 is disposed above a substrate 122 which may be a dielectric substancesuch as sapphire, silicon dioxide, or other substrates. The graphene channel 114 may be deposited or grown directly on the substrate 122 or may be grown on a growth substrate and transferred to the substrate 122 before being patterned as a graphene channel 114.

[0079] Some gFETs may be fluid-gated gFETs such as the fluid-gated gFET 108a and the fluid-gated gFET 108b in which the gating function of the fluid-gated gFETs 108a, 108b is provided by a fluid 116 through which one or more reference electrodes 126 apply and / or measure a voltage of the fluid relative to an effective ground voltage as the gate voltage Vgat any point in time for the gFET.

[0080] In various examples, a passivation layer or insulating layer 124 covers the source 110 and the drain 112 and a small portion of the graphene channel 114 near the junctions of the graphene channel 114 with the source 110 and the drain 112 so that the source 110 and the drain are insulated from the fluid 116 covering the graphene channel 114.

[0081] In various implementations, the system 100 may include a processor 102, storage 104 such as nonvolatile storage media, and a source and measure module 106, which in certain implementations may be configured to operate in a modulated Vgpulse code mode 132 and / or a continuous digitized Vgsweep mode 130. In some implementations, the system 100 may further include an analysis module 134.

[0082] In certain implementations, the system 100 includes signal interface circuitry 136 (e.g., 136a) which may include one or more digital to analog converters or DACs 138athat supply the source to drain voltage Fsd or drain to source voltage Eds. In some implementations, the signal interface circuitry 136a includes a DAC 142a that outputs a voltage Vgto a transimpedance amplifier or TIA 146a that includes an analog terminal electrically coupled to a reference electrode 126. The processor 102 may digitally program an output ofthe DAC 142a to output the gate voltage provided by the TIA 146a to the reference electrode 126.

[0083] In various implementations, the signal interface circuitry 136a includes one or more additional TIAs 147a, 147b that respectively communicate output signals derived from channel currents ofthe gFETs 108a, 108b to ADCs 140a, 140b where the values for the channel currents may be read by the processor 102.

[0084] In certain implementations, the system 100 includes signal interface circuitry 136c which may include one or more digital to analog converters or DACs 138c that supply the source to drain voltage lAi or drain to source voltage Eds. In some implementations, the signal interface circuitry 136c includes a DAC 142c that outputs a voltage Vgto a transimpedance amplifier or TIA 146c that includes an analog terminal electrically coupled toa gate 118. The processor 102 may digitally program an output of the DAC 142c to output the gate voltage provided by the TIA 146c to the gate 118.

[0085] In some implementations, the fluid 116 has a liquid form. In other implementations, the fluid has a gaseous form. The fluid-gated gFETs 108a, 108b may be used as biosensor elements or chemical sensor elements for determining characteristics of substances in liquid or gas form based on the way they influence the behavior of the fluid-gated gFETs 108a, 108b.

[0086] In certain examples, one or more gFETs 108 included in the system 100 may be referred herein to as a solid-state-gated gFETs 108c. As used herein, the term “solid-state-gated gFET” refers to a gFET in which a gate dielectric 120 between a gate 118 at a gate voltage Vgand a graphene channel 114 is formed in a solid-state material in contrast to the fluid-gated gFETs 108a, 108b which supply the gate voltage by biasing the fluid 116.

[0087] In FIG. 1, the solid-state-gated gFET 108c is depicted as atop-gated gFET. Topgated gFETs feature a gate dielectric and gate electrode layered directly on top of the graphene channel. The top-gate configuration allows for better control over the channel's charge carriers compared to back-gated gFETs, leading to improved device performance in terms of on / off ratio and transconductance. However, other types of solid-state-gated gFETs 108c may beneficially utilize the system 100 for CNP tracking 302 and modulated Vgpulse code transfer characteristic scan 308. Other types of solid-state-gated gFETs 108c may include back-gated gFETs, dual -gated gFETs, RF gFETs, flexible gFETs, valleytronics 2D FETs, and / or spintronic gFETs.

[0088] In back-gated gFETs, the gate electrode is located on the opposite side of the substrate from the graphene channel. This configuration is simpler and more common in research settings due to easier fabrication. However, it typically offers less effective electrostatic control over the graphene channel than top-gated configurations. Dual-gated gFETs incorporate both top and back gates, allowing for more precise control of the charge carrier density in the graphene channel. A dual -gated configuration enables the investigation of complex phenomena such as bandgap opening and ambipolar transport in graphene. RF gFETs or radio frequency gFETs are designed for high-frequency applications, leveraging graphene's high carrier mobility. RF gFETs can operate at frequencies in the gigahertz range, making them suitable for wireless communication and radar applications. Flexible gFETs utilize the inherent flexibility of graphene to build gFETs on flexible substrates. Flexible gFETs may be used in flexible electronics and wearable devices, offering robust performance evenwhen bent or stretched. Spintronic gFETs exploit the spin of electrons in addition to their charge which could offer advantages in terms of data storage density and energy efficiency.

[0089] Each type of gFET utilizes the unique properties of 2D nanomaterials such as graphene, including, for example, high carrier mobility, flexibility, and conductivity, to fulfill specific roles in various applications, from high-frequency communication to sensitive biosensing.

[0090] A more detailed example of the functions performed by the processor 102, source and measure module 106 when operating in a modulated , pulse code mode 132, and the signal interface circuitry 136a, 136c is described below concerning the example method 500 depicted in Figure 5. Therefore, as the following section describes various functions included in various implementations of the system 100, it may be helpful to refer to the description of example method 500 depicted in Figure 5.

[0091] In various examples, the system 100 includes one or more gFETs, such as fluidgated gFETs 108a, 108b, or solid-state-gated gFETs 108c, each with a graphene channel 114 between a source 110 and a drain 112. In such instances, the system 100 further includes signal interface circuitry 136a, 136c configured to apply and / or measure electrical signals for the drain and the source of each gFET and to apply and / or measure a signal that serves as a gate voltage Vgfor the gFET.

[0092] It may be noted that the signal interface circuitry 136 (e.g., 136a and / or 136b) may be implemented as circuits in one or more integrated circuit (IC) chips. Such ICs or chips may be separate from or the same as ICs or chips on which the gFETs are implemented. The signal interface circuitry 136 (e.g., 136a, 136b) may also be implemented as printed circuit board assemblies, electronic modules, or electronic instruments.

[0093] The system 100, in some examples, includes digital circuits or devices such as a processor 102 and a storage 104 which is a non-transitory storage medium. As with the signal interface circuitry, the digital circuits or devices may be implemented as integrated circuits or as printed circuit board assemblies, electronic modules, or using embedded or standard computers.

[0094] In certain instances, the system 100 includes a source and measure module 106 configured to modulate a present tracking voltage (Vg) that serves as a gate voltage , for the gFET with a CNP tracking pulse code configured according to a set of pulse code parameters for a present tracking cycle of a set of CNP tracking cycles for the gFET.

[0095] In this context, of CNP tracking 302 and transfer characteristic scanning 308, the term “pulse code” may be used to refer to a format or configuration for a series of pulsesover a predetermined number of periods. Some pulse codes may be configured to modulate a gate voltage with a pair of square wave type pulses with relatively small amplitudes (e.g., 2m V) and pulse widths (e.g., 20ms) consisting of a step-up pulse and a step-down pulse with time periods before and / or after each such pulse where the gate voltage returns to a baseline value for a given tracking cycle, such as depicted in graphs 400, 404 and 406 of FIG. 1 or as depicted in the modulating 502 box of FIG. 5. These pulse code configurations are merely examples and any number or combination pulse shapes, pulse widths, duty cycles, number of pulses, order of step-up pulses and step-down pulses may be configured consistent with the systems and method.

[0096] It may be noted that the term “pulse code” as used herein is different from the term “pulse code modulation” or PCM which is widely used for digitally representing analog communications or audio signals.

[0097] Moreover, the pulse codes used for transfer characteristic scanning 308 of the one or more gFETs 108, can be configured with any of the aforementioned parameters including for example, different step-up gate voltage and step-down gate voltage pulse amplitudes, so as to span a range of gate voltage amplitudes for a selected scanning or characterization window 162 as shown in FIG. 1 and described in more detail concerning window 604 depicted in graph 600 of FIG. 6.

[0098] In the case of the fluid-gated gFETs 108a, and 108b, modulation of a gate voltage Eg may be performed by configuring a pulse code, such as the CNP tracking pulse code to supply a set of pulse code parameters to the DAC 142a which outputs a signal to the TIA 146a that drives a reference electrode 126. In some instances, a first reference electrode 126a (not shown) is used to read the present tracking voltage Vg, and a second reference electrode 126b (not shown) or counter electrode is used to bias the electrolytic fluid (e.g., liquid or gas).

[0099] In some implementations, the source and measure module 106 is configured to measure and compare the present tracking voltage (Vg) with a present minimum gate voltage (Fg_min) solved for by fitting a curve to three current-voltage pairs on a current-voltage response curve (I-Vgcurve) of the gFET based on channel current responses to the gate voltages applied according to the set of pulse code parameters for the present tracking cycle.

[0100] In certain cases, the source and measure module 106 is configured to adjust the present tracking voltage Vgby an incremental range finding voltage in response to determining that three current-voltage pairs do not meet one or more criteria indicating that the present tracking voltage is within predetermined range for determining a CNP voltage for the present tracking cycle using the f / .jnin solved for by fitting the curve.

[0101] On the other hand, the source and measure module 106 is configured to adjust the present tracking voltage Vgby a fine-tuning voltage in response to determining that three current-voltage pairs meet one or more criteria indicating that the present tracking voltage is within a predetermined range for determining a present CNP voltage for the present tracking cycle using the ly min solved for by fitting the curve. Moreover, in various implementations, the source and measure module 106 is configured to set the present CNP voltage to be the present tracking voltage and set a present CNP current to be the minimum current solved for by fitting the curve. In various implementations, the source and measure module 106 includes code executable by the processor 102 to cause the signal interface circuitry 136a, 136c to apply and / or measure electrical signals for the fluid 116 or gate 118, the drain 112, and the source 110 of the one or more gFETs 108 and to control the one or more reference electrodes 126.

[0102] In some implementations, the CNP tracking pulse code is configured to include one or more step-up gate voltage pulses (Iy+ Vg) and one or more step-down gate voltage pulses (Fg-AVg). A more detailed example of a method 500 is depicted and described in relation to FIG. 5 and the individual steps or actions of the method may be configured in different combinations to perform the intended functions.

[0103] In various implementations, the source and measure module 106 in various implementations, is further configured to determine three average channel current responses. For example, the three average channel current responses may include: a first average channel current response (Ado) as an average of channel currents measured in response to unmodulated present tracking voltages included in the pulse code; a second average channel current response (Ad-) as an average of channel currents in response to the one or more step-up gate voltage pulses plus the first average channel current response (Ado) minus an average of the channel current responses to the unmodulated tracking gate voltages immediately before and after the one or more step-up gate voltage pulses; and a third average channel current response (Ad-) as an average of channel currents in response to the one or more step-down gate voltage pulses plus the first average channel current response (Ado) minus an average of the current responses to the unmodulated tracking gate voltages immediately before and after the one or more stepdown gate voltage pulses. In other implementations, such averaging is omitted, and fitting points of the I-V transfer curve to a parabolic curve as described below is performed using channel current responses without averaging.

[0104] In certain implementations, the source and measure module 106 is further configured to perform the curve fit as a parabolic curve fit, wherein the three current-voltage pairs consist of: a value of the first average channel current response (Ado) and the value of thepresent tracking voltage Vg(7Sdo, F ); a value of the second average channel current response (7Sd+) and the average value of the one or more step-up gate voltage pulses ( / sti-. avg(I ,+AVg)): a value of the third average channel current response (7Sd-) and the average value of the one or more step-down gate voltage pulses (Ad-, avg(Fg-AVg)). In such cases, the source and measure module 106 is configured to solve for F min and Ad min using the parabolic curve fit to the three current-voltage pairs.

[0105] Graph 408 of FIG. 1 depicts channel current responses to modulation of a present tracking voltage with a gate voltage pulse code (depicted in graph 404) in which performing a curve fit of the channel current-voltage pairs to a parabolic curve results in a Kg_min that indicates that the present tracking Vgis not within a predetermined threshold for switching from performing range finding 304 to performing tracking 306 a CNP with finetuning (e.g., locked and tracking).

[0106] Graph 410 of FIG. 1 depicts channel current responses to modulation of a present tracking voltage with a gate voltage pulse code (depicted in graph 406) in which performing a curve fit of the channel current-voltage pairs to a parabolic curve results in a Fg_min that indicates that the present tracking Vgis within a predetermined threshold for switching from performing range finding 304 to performing tracking 306 with fine-tuning (e.g., locked and tracking). Additional details concerning the structures and / or functions related to the CNP range finding graph 404, the VCNP tracking graph 406, and the curve fitting graphs 408, and 410 to determine whether to continue range finding by performing a coarse adjustment or to commence VCNP tracking with fine-tuning adjustments are provided below concerning FIG. 3, FIG. 4., and FIG. 5.

[0107] In some implementations, for the one or more gFETs 108 that are fluid-gated gFETs 108a, 108b: the incremental range finding voltage is configured within the range of from about 10 mV to about 18 mV and the fine-tuning voltage is configured as a difference between Fg_min and the present tracking voltage Vswith a magnitude in a range of from about 0 mV to about 0.5 mV.

[0108] In certain example implementations, for one or more gFETs 108 that are fluidgated gFETs 108a, 108b: the source and measure module 106 is further configured to determine that the present tracking voltage Vgis within the predetermined range for determining a present CNP voltage for the present tracking cycle using the Vg_min solved for by fitting the curve based on an absolute value of the present tracking voltage Vgminus the value of Vg_minsolved for by fitting the curve being less than 10 mV. As noted above, other examples using other values may be implemented using the principles provided in this disclosure.

[0109] In various implementations, for the one or more gFETs that are solid-state-gated gFETs: with the channel of the gFET being separated from a metal gate electrode by a solid- state gate dielectric: the incremental range finding voltage is configured within the range of from about 100 mV to 1000 mV, based on a thickness of the solid-state gate dielectric; and the fine-tuning voltage is configured as a difference between Vg_min and the present tracking voltage Vg with a magnitude based on a thickness of the solid-state gate dielectric. In some implementations, such values may be adjusted to account for the operating characteristic of the particular gFET being used.

[0110] In some implementations for the one or more gFETs that are solid-state-gated gFETs with the channel of the gFET being separated from a metal gate electrode by a solid- state gate dielectric, the source and measure module is further configured to determine that the present tracking voltage is within the predetermined range for determining a present CNP voltage for the present tracking cycle using the Fg_min solved for by fitting the curve based on an absolute value of the present tracking voltage Vgminus the value of Fg_min solved for by fitting the curve is within from about 2% to about 5% of a non-zero optimal gate voltage for maximum channel conductance.

[0111] In other words, because gFETs are ambipolar there may be different gate voltages for maximum conductance in the n-region and the p-region of the transfer curve. Therefore, the term “optimal gate voltage” for maximum channel conductance is intended to refer to a non-zero voltage range in which the threshold for determining that the parabolic curve fit of the I-V curve is sufficient to switch from performing range-finding to performing CNP tracking using fine-tuning is not a fixed threshold such as 10 mV as determined empirically for certain fluid-gated gFETs but is instead a fraction of the effective “turn on” voltage for the solid-state -gated gFET 108c taking into account that the effective “turn on” value varies based on the effective dielectric thickness which takes into account physical thickness and dielectric constant of a gate dielectric 120.

[0112] In certain examples, the source and measure module 106 is further configured to determine a direction of an adjustment of the tracking gate voltage for a next CNP tracking cycle by an incremental range finding voltage to be: an increase in tracking gate voltage in response to the second average channel current response related to the one or more step-down gate voltage pulses being lower than the first average channel current response related to the one or more step-up gate voltage pulses; and a decrease in tracking gate voltage in response to the second average channel current response related to the one or more step-down gate voltage pulses being higher than the first average channel current response related to the one or morestep-up gate voltage pulses. In other words, an expression based on the channel current responses (which may or may not be averaged depending on the implementation) is used to determine whether the gate voltage should be adjusted up or down.

[0113] For example, graph 400 shows that the present tracking voltage in the range finding graph 404 is well below the VCNP SO the incremental range finding voltage should be increased. Referring for example to a fluid-gated gFET, one example of a suitable expression to perform this direction-determining function may be expressed, for example, as Vg= Vg- ((Ad - - Ad-) |Ad+ - Ad-i )* 10 mV) where the next cycle track gate voltage I (n+i) = present tracking voltage F (n) - [ (( / sd + - Ad-) / |Aa + - Ad -| )] times an incremental range finding voltage e.g., 10 mV) where the expression in square brackets is the increasing or decreasing voltage directiondetermining portion of the expression.

[0114] In some implementations, the source and measure module 106 is further configured to configure a set of transfer characteristic (TC) scanning cycle parameters for the gFET comprising a selected number of TC scanning cycles and gate voltage levels for performing a set of TC scanning cycles that span a selected TC scanning voltage range for the gFET. In such implementations, the source and measure module 106 is also configured to modulate a present TC scanning voltage Vgthat serves as a gate voltage for the gFET with a TC scanning pulse code configured according to a set of pulse code parameters for a present TC scanning cycle of the setofTC scanning cycles, where a pulse voltage magnitude parameter for pairs of step-up gate voltage pulses and step-down gate voltage pulses is changed by a TC scanning voltage adjustment between pairs so that by modulating the TC scanning voltage over the selected number of gate voltage pulses, the set of TC scanning cycles spans the selected TC scanning voltage range.

[0115] In other words, referring again to the method 300 depicted in FIG. 1, after the present tracking voltage Vgis locked and tracking using fine-tuning based on the parabolic curve fit to adjust or set the next Vgto be the present VCNP solved for using the minimum point of the parabolic curve fit, the system 100 and method 300 are ready to begin performing a modulated Vgpulse code excitation scan of the one or more gFETs 108 as depicted in graph 600. Additional details are provided below concerning FIG. 5, FIG., 6.

[0116] In various examples, the source and measure module 106 is further configured to measure a present channel current response to the pairs of step-up gate voltage pulses and step-down gate voltage pulses as changed by the TC scanning voltage adjustment for the present TC scanning cycle over the selected number of gate voltage pulses for the set of TC scanning cycles and to determine one or more transfer characteristic parameters of the gFETbased on the measurements performed over the set of TC scanning cycles. The graph 700 depicts a transfer curve 220 for a gFET measured using continuous digitized Vg sweeps 130 which exhibit asymmetries or errors due to non-Markovian responses. By contrast, in the transfer curve 702 determined by performing modulated Vg pulse code scans over a characterization window 162, no asymmetries or errors due to non-Markovian response or lack on CNP tracking are observed. Further details are provided below concerning FIG. 5 and FIG. 7.

[0117] Similarly in the graph 906b, in the transconductance plot 222 similar asymmetries or errors are observed where no CNP tracking occurred and where continuous digitized Vg sweeps were used. In the transconductance plot 913 depicted in graph 906b, no asymmetries or errors due to non-Markovian responses or lack of CNP tracking are observed. Further details are provided below concerning FIGs. 9a, 9b, and 9c.

[0118] In some examples, the system 100 includes an analysis module 134 that is configured to analyze 316 parameters of the transfer characteristics that are affected by an interaction of a target with an environment adjacent to the channel of the gFET.

[0119] For example, with fluid-gated gFETs 108a, and 108b, interactions with certain analytes 918 influence the transfer characteristics of the gFET 908a as depicted in FIG. 9C. Accordingly the analysis module 134 can measure and compare the transfer characteristics to analyze the target analytes, for example, to determine a presence or concentration of a selected analyte or to detect an interaction, or a reaction rate, of an analyte with a surface chemistry 916.

[0120] By minimizing the non-Markovian behavior exhibited in systems using continuous Vgsweeps to determine transfer characteristics, and by tracking the CNP and returning the TC scanning gate voltage to the most recently determined VCNP, the accuracy and / or precision of the analysis is substantially improved based on the fact that the accuracy and / or precision of the measurement used for performing the analysis are significantly improved.

[0121] To better understand the nature and scope of these improvements, it may be useful to compare and contrast the continuous digitized Vgsweep mode 130 (typically used in existing gFET -based systems) for determining gFET transfer curves with the modulated Vgpulse code mode 132 disclosed herein and to review the type of problems in existing systems and method to be solved using the systems and methods disclosed herein. To make this comparison, sections of the detailed description of FIGs. 2A, 2B, and 2C, address examples of certain problems with the continuous digitized Vgsweep mode 130 (typically used in existinggFET-based systems) and later sections describing FIGs. 9A, 9B, and 9C show how the systems and methods described in connection with FIG. 1, FIGs. 3-8 and FIGs. 10-11 provide innovative solutions for tracking a charge neutrality point and determining gFET transfer characteristics, thereby significantly improving a broad range of gFET-based applications and technologies.

[0122] FIG. 2A is a schematic cross-sectional diagram of a fluid-gated gFET 208a in which a system as depicted in FIG. 1 is configured to use digitized gate voltage sweeps for determining a transfer curve or transfer characteristics such as a charge neutrality point where the diagram illustrates a potential for cumulative charge effects due to Vgsweep time at levels not near VCNP.

[0123] The intrinsic response time of gFETs is quite fast, for gFETs with relatively large channel dimensions on a millimeter scale which are sometimes referred to herein as macro gFETs as well as for gFETs with submillimeter dimensions sometimes referred to herein as micro gFETs, the response time is fast and RC time constants for such gFETs are typically sub-millisecond. The RC time constant in graphene FETs is a measure of the device's intrinsic response time to electrical signals, influenced by its internal resistance and capacitance. A lower RC time constant signifies faster response times. However, as further explained in more detail below concerning FIG. 2B, using continuous digitized gate voltage sweeps to find the CNP of a gFET can result in inaccuracies that vary based on sweep rate.

[0124] In a fluid-gated gFET, the gate electrode is replaced by an electrolyte solution, and gating is achieved by applying a voltage across the electrolyte, inducing charges in the graphene channel. The ions in the electrolyte rearrange themselves near the graphene surface, with cations and anions separating to form two layers: one layer of ions adsorbed directly on the graphene surface and another of opposite charge just a bit further away in the electrolyte. This separation creates an electric double layer.

[0125] Double-layer ions in the context of a fluid-gated gFET refer to the ions present in the electrolyte that form an electric double layer (EDL) at the interface between the electrolyte and the graphene channel of the gFET. This electric double layer acts like a nanoscale capacitor. The capacitance of this EDL is high, allowing for efficient charge induction in the graphene channel with relatively low applied gate voltages. Ions in the fluid can move about and act as relatively fast-reacting charges. This mechanism enables the modulation of the graphene's conductivity, allowing the gFET to operate as a transistor. The EDL plays a crucial role in the sensitivity and performance of the gFET, especially in applications like biosensors, where the detection mechanism often involves charge modulationthrough the binding of target molecules to the graphene surface, affecting the local ionic distribution and, consequently, the device's conductance.

[0126] When operating at the CNP, the graphene channel in a gFET is electrically neutral, implying minimal interaction with external charges. However, in a fluid-gated gFET configuration, such as system 100, using a fluid-gated gFET 208a, where the system is configured to use digitized gate voltage sweeps to determine transfer characteristics, including the voltage at the charge neutrality point FCNP. At most points in the forward sweeps and the reverse sweeps, the gate voltage Vgsourced and measured deviates significantly from FCNP. The more prolonged and the further the gate voltage Vgnear the channel remains from the VCNP, the more significant the accumulation of slow charges 207 near the interface of the graphene channel 214 and the substrate 222.

[0127] FIG. 2B is a schematic block diagram illustrating the non-Markovian behavior of a channel current response when the system of FIG. 1 is configured to use continuous digitized gate voltage sweep mode 130 for determining a transfer curve, according to one or more examples of the present disclosure.

[0128] In the present context, the word “digitized” refers to the feature that generally the gate voltage bias value is changed by sending a digital value for the gate voltage to be applied to a DAC such as the DAC 142a depicted in FIG. 1. The word “continuous” refers to the feature that in this mode, the values from analog output of a DAC are updated from point- to-point but the gate voltage is not a pulsed voltage that returns to a starting or baseline voltage Vo but continues to be digitally increased or decreased monotonically until a sweep in the opposite direction occurs. Because such continuous digitized gate voltage sweeps are representative of the process used to determine I-Vstransfer curves for gFETs in existing systems, in this context, this , sweep configuration is helpful to illustrate problems found in existing systems.

[0129] For example, existing techniques fortracking a Dirac point or CNP suffer from various problems. Tracking a CNP using continuous digitized gate voltage sweeps (also referred to as Vgsweeps) generally requires that the CNP voltage (also referred to as the Dirac point voltage or FDP) be determined after each sweep from a measured transfer curve. This Vgsweep-based method suffers from the measured VCNP varying significantly depending on sweep direction, sweep speed, and sweep range.

[0130] Identifying the CNP by applying a forward gate voltage sweep (e.g., lowest , value to highest Vgvalue) and / or reverse gate voltage sweep (e.g., lowest Vgvalue to highest Vgvalue), requires generating data corresponding to an I-Vg(current-voltage) curve (alsoknown as a transfer curve) which may be visualized as a graph with channel current on a y- axis and gate voltage on an x-axis. For each sweep, identification of the CNP is performed by determining the (x,y) point on the I-Vgcurve at which the graphene channel exhibits minimal conductivity, e.g., the channel current is lowest. For some transfer curves, the y-axis represents the conductance of the gFET rather than the current response which is a useful alternative since a channel current response e.g., 7sd is proportional to conductance.

[0131] The graph 202 depicted in FIG. 2B illustrates results of empirical tests in which data corresponding to transfer curves 204, 206, and 208 is captured and depicted with the y- axis values showing the conductance of a fluid-gated gFET as digitized gate voltage sweeps (e.g., forward sweeps (denoted by the letter ‘F’ and an arrow pointing towards higher values of the gate voltage Vg), and reverse sweeps (denoted by the letter ‘R’ and an arrow pointing towards a lower values of the gate voltage Vg) of the gate voltage Vgapplied to the fluid that covers the channel.

[0132] As can be seen in a transfer curve 204 generated with a Vgsweep with a relatively low sweep rate of 0.024V / s which gives the slow charges 207 relatively more time to reach a new equilibrium at each measured Vgpoint. As can be seen in transfer curve 204, there are some relatively small voltage differences (e.g., about 15 mV) between the lowest current point of the forward sweep portion of the transfer curve 204 and the reverse sweep portion of the transfer curve. These are types of non-Markovian effects meaning that future states of the transfer curve values (e.g., gate voltages and channel current responses depend not only on the present state but also on the cumulative prior effects of slow charges in the system. This characteristic often leads to more complex behaviors and correlations over time, as past charge states due to charges that are not intended to be a material focus of finding or tracking the CNP can influence present and future outcomes. This in turn means that errors in determining the correct value for CNP can lead to analysis errors where the analysis uses the CNP value as a substantive input.

[0133] In existing systems, the gate voltage corresponding to one or the other of these lowest current points on the I-Vgcurve would likely be considered the charge neutrality point voltage VCNP. However, an error in the value of the charge neutrality point voltage VCNP can be observed because even though the slow charges have had time to rearrange and settle reducing the apparent voltage differences between the forward sweep portion of the transfer curve and the reverse sweep portion of the transfer curve, the rearranged slow charges 207 still affect the measured values of Vgand the corresponding channel current response I A which to a certain extent may mask the scope of the problem. This masking effect may be because the apparentcumulative effect of the slow charges on the relative forward sweeps and reserve sweeps is less visible. Furthermore, using a low sweep rate takes more time to gather data, and the gFET usefulness (e.g., as a sensing device for target interactions that affect the liquid-gate voltage measured near the channels) is severely hampered by having to use a slow sweep rate.

[0134] Higher Vgsweep rates could be used and are included in the test results depicted in FIG. 2B. The transfer curve 208 was acquired using a sweep rate of 7.6 V / s. Because the Vgsweep rate is higher, some of the slow charges 207 do not have time to react or accumulate. However, as can be seen in the topmost transfer curve 208 there is a somewhat greater voltage difference (about 81 mV) between the lowest current point of the forward sweep portion of the transfer curve 208 and a corresponding point from the reverse sweep portion of the transfer curve. For any gFET, using the Vgsweep method of generating an I-Vscurve, can have an error effect and it is difficult to predict the degree to which a particular gFET will be affected by slow charges 207.

[0135] This non-Markovian behavior is even more apparent in the transfer curve 206 which is denoted as having a mid-range Vgsweep rate of 1. 1 V / s, which leads to an even greater voltage difference (about 121 mV) between the lowest current point of the forward sweep portion of the transfer curve 206 and a corresponding point from the reverse sweep portion of the transfer curve.

[0136] To reiterate, the extent to which the CNP determined using continuous digitized gates voltage sweep has errors depends on the Vgsweep rates, Vgsweep direction, and Vgsweep range which includes a dependency on how far the starting voltage Vo and other gate voltages measured for each Vgsweep are from the “true” CNP voltage.

[0137] Accordingly, it can be seen from these results that using continuous digitized gate voltage sweeps at low, mid-range, or relatively high but still practicable gate voltage sweep rates, can result in errors that can potentially confound or mask the results of any transfer characteristic determination related to fast charge effects of chemical or biological interactions between surface chemistries near the graphene channel and target analytes. Similar charge effects may also influence non-sensor applications of gFETs based on the same similar effect of slow charges in such devices.

[0138] Further details about how a CNP voltage can be found and tracked and how a tracked CNP voltage can be used to perform a transfer characteristic scan for the gFET that can be more accurate and precise than determining transfer characteristics using continuous digitated gate voltage sweeps are provided below with respect FIGs. 3-8.

[0139] FIG. 2C is a schematic block diagram illustrating the electric field effect on surface chemistry structure, analyte structure, and reaction kinetics when the system of FIG. 1 is configured to use continuous digitized gate voltage sweeps, according to one or more examples of the present disclosure.

[0140] In addition to the non-Markovian behavior and potential errors in transfer curve values and transfer characteristics derived from such values which are sweep rate dependent, there is another potential concern when using continuous digitized Vgsweeps to determine transfer curves and transfer characteristics such as VCNP.

[0141] The application of continuous digitized gate voltage (Vg) sweeps in the system of FIG 1 can significantly influence the structures of the surface chemistries 216 and analytes 218. The electric fields 224 generated by these sweeps can cause alterations in the molecular configuration of the analytes 218, affecting the reaction kinetics. Using a simplified model, the electric field E(t) for a given point in time can be related to the charge density o on the graphene by o = C-Egs(t) where C is a capacitance per unit area of the graphene channel with the electrolytic fluid acting as the dielectric. A capacitance C can be expressed as C= soar where so is the vacuum permittivity, 8ris the relative permittivity of the electrolytic fluid, and d is the effective thickness of the electrolyte layer.

[0142] Simplifying, an electric field Ez(t) in the direction perpendicular to the graphene channel, considering the channel is at Z=0, may be written as Ez(t) = o / 8o8r= C-Egs(t) / 8o8r= Egs(t) / d. A channel bias voltage Esa or Eds may be used to determine a difference between the gate voltage near the channel and the channel bias voltage.

[0143] For some fluid-gated gFETs such as gFETs in which the graphene is directly deposited or grown on a sapphire wafer, a CNP voltage in a typical buffer fluid may also be in a similar range to the channel bias voltage such that at the CNP the magnitude or strength of the electric field will be relatively low because the CNP voltage is close to the channel bias voltage. Regardless of where the CNP voltage is determined to be, where continuous digitized gate voltage sweeps are used to find the CNP and to determine transfer curves and / or transfer characteristics, most of the points on the 7Sd-Egscurve will apply an electric field Ez(t) that is strongest near the graphene channel 214.

[0144] This is particularly relevant when the analytes 218 are sensitive to electric fields, as the induced changes could lead to different interaction rates or pathways. For instance, the alignment of polar molecules may be influenced by the electric field 224, which in turn may affect how these molecules interact with the surface chemistries 216 with each other. As aresult, the observed transfer curves and characteristics could be reflective not only of the intrinsic properties of the analytes but also of the effects of the electric field on the analytes.

[0145] Moreover, the reaction kinetics can be altered by the electric field effects on the surface chemistry. For example, the electric field could enhance or inhibit the adsorption of analytes on the sensor surface, which would change the rate at which reactions occur. This could lead to a variation in the sensitivity and selectivity of the sensor, as the electric field might change the energy landscape of the surface reactions. In the context of the system of FIG 1, this means that the transfer curves and characteristics derived from continuous digitized Vgsweeps might not be solely indicative of the analyte concentration but also may also be indicative of the electric field influence on the reaction kinetics.

[0146] Furthermore, to determine a transfer curve 220, CNP, a transconductance curve 228 or the first derivative of the transfer curve 220 and other transfer characteristics, in systems that use continuous digitized gate voltage Vgsweeps, a characterization window 226 typically spans a full range of gate voltages Vgfor both forward and reverse Vgsweeps to characterize target analyte based on changes in VCNP, gm and other derived parameters such as effective layer capacitance, effective layer porosity, and so forth. Spanning the full range of gate voltages Vgfor both forward and reverse Vgsweeps means that even if only a portion of the transfer curve is needed to analyze the effects of the analytes 218 on the transfer characteristics of interest, the magnitude and duration of the electric fields applied for each digitized Vgpoint in the spanned range has the potential to detrimentally influence the surface chemistry structure, the analyte structure, and / or the reaction kinetics of interest.

[0147] Thus, the examples depicted and described concerning FIGs. 2A, 2B, and 2C reinforce the assessment of the inventor of the present disclosure that the aforementioned shortcomings and problems with existing systems, namely non-Markovian results, lack of CNP tracking, and generation of electric fields detrimental to certain sensing measurements, can be innovatively solved or addressed by the systems, methods, and computer program products for tracking a charge neutrality point and determining gFET transfer characteristics as disclosed herein.

[0148] Referring now to FIG. 3 and FIG 4, these two figures describe and provide empirical results from a working example of how the systems, methods, and computer program products for tracking a charge neutrality point, determining gFET transfer characteristics, and analyzing affected transfer characteristics may be implemented.

[0149] FIG. 3 is a high-level schematic flowchart diagram illustrating a method 300 for tracking a charge neutrality point and determining gFET transfer characteristics, according to one or more examples of the present disclosure.

[0150] FIG. 4 is a working example illustrating graphs for selected steps of the method for tracking the charge neutrality point, according to one or more examples of the present disclosure.

[0151] In Figure 3, a method 300 is depicted as having three phases: a first phase for CNP tracking 302, a second phase for performing a pulsed transfer characteristic scan 308, and a third phase for analysis 314.

[0152] In various examples, the CNP tracking 302 begins with an action of performing 304 range finding of a CNP. When beginning the method 300, in some circumstances, a present tracking voltage serves as a gate voltage , for the gFET, and a CNP tracking pulse code is configured according to a set of pulse code parameters for a present tracking cycle of a plurality of charge neutrality point tracking cycles for the gFET.

[0153] These aspects of the method 300 can be visualized in FIG. 4. An overview graph 400 of measurements of a present tracking voltage Vgthat serves as a gate voltage for the gFET shows that from 0 to about 13 seconds, the system and method 300 are performing range finding 304, 404. An enlarged graph 404 taken from graph 400, shows that as part of the rangefinding phase, the present tracking voltage Vgwas modulated according to a CNP tracking pulse code (which in this example included a step-up gate voltage pulse and a step-down gate voltage pulse).

[0154] The method 300 continues to perform 304 range finding, during which, in certain examples, it compares the present tracking voltage (Vg) with a present minimum gate voltage (I min) solved for by fitting a curve (shown in graph 408 in FIG. 4 ) to three currentvoltage pairs on a current-voltage response curve (I-Vgcurve) of the gFET based on channel current responses 7sd measuring current between the source and the drain of the gFET to the present gate voltages applied according to the set of pulse code parameters for the present tracking cycle. As depicted by the arrow at the lower right comer of graph 408, the Eg_min solved for by fitting the curve is far out of a predetermined range and does not meet one or more predetermined criteria indicating that the present tracking voltage is within a predetermined range for determining a CNP voltage for the present tracking cycle using the Eg min solved for by fitting the curve.

[0155] It should be noted that the E ™ (denoted in graphs 408 and 410 of FIG. 4 by a triangle symbol) is not one of the three gate voltages of the points on the current but is rathersolved for by treating the three (7Sd, F ) current-voltage pairs as points on a parabolic curve and then solving for the Vgvalue at the lowest current 7sd point on the parabolic curve. In graph 408, the I min solved for by fitting the curve is far out of a predetermined range and does not meet one or more predetermined criteria indicating that the present tracking voltage is within a predetermined range for determining a CNP voltage for the present tracking cycle using the I min solved for by fitting the curve, so the method 300 continues to perform 304 range finding, e.g., by making coarse adjustments that in this case include increasing the tracking gate voltage by incremental range finding voltage, such as 10 mV. The incremental range finding voltage may be empirically determined but the incremental range finding voltage should not be so large that the increase or decrease significantly overshoots the actual present CNP voltage which could result in delays or failures to converge on the actual present CNP voltage.

[0156] As can be seen in the graph 410 of FIG. 4, when the three voltage-current pairs determined from the present tracking voltage Vgmodulated by the step-up and step-down pulses depicted in the graph 406 for points of I-Vgcurve that, when fit to a parabolic curve, can be used to determine a F _minon the I-Vgcurve based on the fit of the I-Vgcurve to the parabolic curve. A numerical threshold for certain fluid-gated gFETs is useful where when the baseline or unmodulated present tracking voltage is within about 10 mV of the min determined by solving for a minimum point on the parabolic curve fit to the measured current-voltage pair points on the I-Vgor transfer curve, then the method 300 continues and includes tracking 306 a CNP voltage, e.g., by adjusting the present tracking voltage Vgby a fine-tuning voltage in response to determining that three current-voltage pairs meet one or more criteria indicating that the present tracking voltage is within the predetermined range for determining a present CNP voltage for the present tracking cycle using the min solved for by fitting the curve.

[0157] When the FcNphas been thus determined, the next tracking gate voltage Vg(n+i) for the next CNP tracking cycle is set to the FCNP determined for the present CNP tracking cycle, e.g., Vg(n+i) = FCNP(II) where ‘n’ denotes the present CNP tracking cycle.

[0158] Using continuous digitized Vgsweep mode, such as is done in existing systems, typically takes about 3 seconds to update the value of FCNP.

[0159] By contrast, in some implementations, the modulated Vgpulse code mode as depicted takes only 500 ms and can take as little as 100 ms or even faster with custom circuitry to update the value of FCNP after the range finding mode has been completed. This means that with a fluid-gated gFET, using the modulated Vg pulse code mode can enable enhanced accuracy real-time tracking and updating of new FCNP values much faster can be done with than existing systems.

[0160] FIG. 5 is a detailed schematic flowchart diagram illustrating a method 500 for tracking a charge neutrality point, according to one or more examples of the present disclosure.

[0161] In various examples, the method 500 for dynamically tracking a charge neutrality point (CNP) of a graphene field effect transistor (gFET) that includes a graphene channel between a source and a drain by iteratively performing a plurality of charge neutrality point tracking cycles.

[0162] The method 500 includes, in certain implementations, modulating 502 a present tracking voltage (Vg) to serve as present gate voltages for the gFET with a CNP tracking pulse code configured according to a set of pulse code parameters for a present tracking cycle of a plurality of charge neutrality point tracking cycles for the gFET.

[0163] For example, as depicted in FIG. 5., pulse code parameters 501 may be configured to have five time periods T1-T5 per tracking cycle. In the first period Tl, the present tracking voltage Vgis applied as a gate voltage for the gFET. At period T2, the present tracking voltage is modulated by a step-up pulse 503b expressed as Vg+ Vgwhere A Vgis a small amplitude pulse of, for example, 2mV. In the example, the third value of the pulse code is a return to the present tracking voltage Vg503c. At the fourth time period T4, the pulse code modulates the present tracking voltage with a pulse in the opposite direction (in this case a step-down pulse 503d expressed as Vg- Vg. At the fifth period T5, the value of the pulse code is a return to the present tracking voltage Vg503c.

[0164] A simpler set of pulse code parameters could be configured with only three time periods T1-T3 where in the first period Tl present tracking voltage is modulated by a step-up pulse expressed as Vg+ Vgwhere A 12 is a small amplitude pulse of, for example, 2mV. At time period T2, the pulse code modulates the present tracking voltage with a step-down pulse expressed as Vg- Vg. and at time period T3, the present tracking voltage is sourced to the present tracking voltage Vg before modulation.

[0165] It should be noted that a wide range of pulse code parameters and pulse code configurations may be configured consistent with the systems and methods disclosed herein and may include various ranges or combinations of pulse shapes, pulse widths, duty cycles, number of pulses, order of step-up pulses and step-down pulses, and so forth.

[0166] In various implementations, the method 500 includes measuring 504 gFET channel current responses to the pulse gFET gate voltages for a present tracking cycle.

[0167] The method 500, in some implementations, includes deriving 506 average channel current responses to the gate voltage pulses for a present tracking cycle. In certain implementations, the averaging is omitted and the three points used for fitting to the curve arethe voltages for an unmodulated present tracking voltage Vg, a step-up pulse, and a step-down pulse and with corresponding channel current responses results from each applied gate voltage measured after a short period for settling.

[0168] The method 500 continues and includes performing 508 a curve fit of the transfer curve values resulting from the pulse gFET gate voltages and solving for a Fg_min using results of the parabolic or quadratic curve fit. Various algebraic or numerical methods and tools for fitting a parabolic curve to the three pairs of current-voltage points are available to a skilled artisan. Once a quadratic equation for the curve is determined, a minimum point may be determined by taking a first derivative of the quadratic equation, setting the derivative equation equal to zero, and solving for Vg, one can determine ly min. i.e., the value of Vgat the minimum point of the parabolic curve.

[0169] Transfer curves 509a, and 509c in FIG. 5 are empirically determined transfer curves respectively generated using a fluid-gated gFET and a solid-state-gated gFET. Also depicted are parabolic curves 51 la, and 511c which fit the points of the transfer curves 509a, and 509c near the minimum. It may be noted that the curvature of the parabolic curve matches the curvature of the transfer curve near the minimum current values but farther from the minimum curve point the two curves begin to diverge.

[0170] The method 500 continues and includes determining 510 whether I ,_inillsolved for using the parabolic curve fit to the three pairs of current-voltage points is within a predetermined range of the present tracking voltage to be suitable for using the parabolic curve fit to determine the value of FCNP for the present CNP tracking cycle.

[0171] If not, then the method 500 includes adjusting 512 the present tracking voltage by increasing or decreasing it by an incremental range finding voltage (e.g., a coarse adjustment) where the direction of the adjustment is determined as described above concerning Figure 1.

[0172] If yes, then the method includes determining 516 whether the IT ,,,,,, solved for using the parabolic curve fit is close enough to the present tracking voltage (e.g., within 0.5 mV) to track FCNP. The method further includes setting 518 a present CNP voltage FcNP(n) to be the solved for using the parabolic curve fit and setting the present CNP current to be a minimum current Ad min at the IV ,,,,,, solved for by fitting the curve.

[0173] The method 500 continues and includes setting a tracking voltage Fg(n+i) for a next tracking cycle to be FCNP(II).

[0174] In certain implementations, the method 500 further includes outputting 514 best available CNP parameter values for the present tracking cycle. In some circumstances, suchvalues will not yet have been in the locked and tracked phase but will generally be better estimates of the final CNP parameter values than those determined in the prior tracking cycle even if still performing range finding.

[0175] The method 500 may be performed using the system 100 and components and functions thereof as depicted and described above concerning FIG. 1, FIG. 3, and FIG. 4. The method may also be implemented in the form of a computer program product configured to be executed by a processor.

[0176] It should be reiterated that the examples disclosed herein are intended to be illustrative and may be adjusted or modified by a person skilled in the art based on the principle and teaching of the present disclosure while still achieving significant improvements over existing systems and methods.

[0177] FIG. 6 is a graph 600 illustrating starting from a tracked charge neutrality point 602 and performing a set of modulated Vgpulse code transfer characteristic (TC) scanning cycles over a characterization window 604, according to one or more examples of the present disclosure.

[0178] In the graph 600, the characterization window 604 is selected to span the full range of gate voltages that would typically be performed using a digitized Vgsweep mode. However, with the modulated Vgpulse code mode, there is no need to perform forward and backward scans since using the modulated Vgpulse code mode and returning to a tracked FCNP value after each pulse minimizes the non-Markovian behavior errors described and depicted in connections FIGs. 2A, 2B, and 2C.

[0179] An enlarged graph 606 shows a more detailed view of a present TC scanning voltage 17(578.4ms) being modulated with a step-up gate voltage pulse, returning to FCNP for a period, and then at 583.2 ms, the TC scanning voltageg(583.2 ms) is modulated with a stepdown gate voltage pulse to 435.168 mV and the pulse code continues until the amplitudes of the step-up and step-down Vgpulses span a selected characterization window of Vgvoltages for which pulse code modulations are performed and for which channel current responses are measured.

[0180] Additional details about these improvements are described below with respect to FIGs. 9A, 9B, and 9C. In the example depicted in FIG. 6, to provide a comparison over a complete transfer curve range, the total Vgrange in the characterization window is intended to be similar to the voltage range that would be spanned using the continuous digitized Vgsweep mode to determine an I-Vgcurve. However, as illustrated with respect to Figure 9C, using themodulate Vgpulse code mode disclosed herein may enable a useful analysis to be performed with a smaller range of TC scanning voltages in the characterization window.

[0181] FIG. 7 is a graph 700 derived from a working example illustrating starting from a tracked charge neutrality point and measuring a set of channel current 7sd responses 702 to the modulated Vgpulse code TC scan or scanning cycle, according to one or more examples of the present disclosure.

[0182] The graph 706 shows an enlarged view of a subset 704 of channel current responses Ad for TC scanning gate voltage pulses modulated as depicted in FIG. 6. Notably, in the depicted example, since the step-down voltage pulses are closer to the FCNP, the channel current responses are lower forthe step-down voltage pulses than for the step-up voltage pulses.

[0183] More significantly, by contrast with the continuous digitized Vgsweep mode where during the vast majority of the sweep time, the gate voltage Vgis far from the best available indicated FCNP value, with the modulated Vgpulse code TC scanning mode, for the vast majority of the total TC scanning time, the TC scanning voltage Fg(n) for any TC scanning cycle ‘n” is maintained at the tracked FcNPwith only short pulses that are largely immune to non- Markovian effects of slow charges as described with respect to FIG. 1.

[0184] FIG. 8 is a graph 800 derived from a working example illustrating starting from a tracked charge neutrality point and measuring a set of capacitive charging currents for the modulated Vgpulse code scanning cycle, according to one or more examples of the present disclosure.

[0185] As indicated with respect to FIGs. 6 and 7, prior to beginning the set of TC scanning cycles, a baseline voltage F off referred to in this context as a present TC scanning voltage may be set equal to the tracked FCNP value determined by one or more CNP tracking cycles.

[0186] Igis a capacitive charging current, rather than a gate leakage current. A potential impact of Igon measured pulsed transfer characteristics may minimized by minimizing gFET size and / or increasing a width to length ratio W / L of the graphene channel of the gFET.

[0187] FIG. 9 A is a set of three graphs 902a, 904a, and 906a derived from a working example illustrating that using modulated gate voltage scans to find and track a CNP and determine transfer characteristics of a gFET results in Markovian responses over various Vgscan rates, directions, and ranges. Each / stiand Igpoint is measured for the corresponding Vgpulse when Vgl / ,_orr where l<,_orr refers to the unmodulated periods of the present TC scanning voltage. The channel current responses are measured in response to the step-up pulses and step-down pulses of different amplitudes that span the range of gate voltages Vgneeded to span the range of voltages for a selected characterization window for the present TC scanning cycle.

[0188] As noted in the caption above the graphs, using a modulated Vgpulse code scan enables Markovian responses over various Vgscan rates, directions, and ranges free from the errors caused by delayed or cumulative effects of slow charges. Furthermore, there is no need for forward or backward scans.

[0189] Additionally, empirical evidence from working examples using fluid-gated gFET indicates that the system and method disclosure herein may be used to track FCNP accuracy and precision down to -0.05 mV. Additionally, the system and methods disclosed herein enabled measuring real CNP and related parameters in real-time with a time resolution as rapid as ~0.5s per point, which may be improved to -0. Is per point or even less with the use of custom electronics.

[0190] Real-time tracking of FCNP of a gFET with enhanced accuracy offers several advantages, particularly for applications where device performance and stability are critical. In various implementations, real-time tracking of a CNP with enhanced accuracy offers multiple benefits.

[0191] Improved Device Performance: The performance of a gFET is highly sensitive to the exact gate voltage applied relative to its FCNP. By accurately tracking FCNP in real-time, it's possible to operate the device at an optimal point where the transconductance (gm) is maximized. This ensures that the transistor operates efficiently, with higher speed and sensitivity.

[0192] Enhanced Sensing Capabilities: in certain implementations, gFETs are particularly suitable for sensor applications due to their high sensitivity to changes in their environment, such as pH changes, biological molecules presence, or gas detection. Precise realtime tracking of FCNP allows the device to maintain its optimal sensitivity and selectivity, improving the reliability and accuracy of the sensors.

[0193] Adaptive Control and Tuning: Environmental factors like temperature, humidity, or mechanical stress can shift the FCNP. Real-time monitoring allows for adaptive control systems to dynamically adjust the gate voltage to compensate for these shifts, maintaining the device's performance stability over time.

[0194] Reduced Noise and Error in Measurements: Accurate tracking of FCNP reduces errors associated with charge carrier inhomogeneity and minimizes electronic noise in the measurements. This is particularly important in precision applications such as quantum computing and ultra-sensitive electronic measurements.

[0195] Increased Longevity and Reliability: By operating the gFET closer to its optimal point and avoiding regions near the CNP where performance may degrade, the longevity and reliability of the device can be enhanced. This is crucial for applications where long-term stability is required, such as in integrated circuits for communication devices.

[0196] Facilitation of Scalable Fabrication: In manufacturing environments, real-time FCNP tracking may facilitate the scalable fabrication of uniform and reliable gFET devices, as it allows for immediate corrections during the device tuning process, ensuring that each transistor meets its performance specifications.

[0197] Overall, the ability to track ECNP accurately and in real-time is a significant advantage in optimizing the operation and extending the application range of graphene and similar 2D channel material -based electronics.

[0198] FIG. 9B is a set of graphs of results from a working example illustrating that using modulated gate voltage scans to first find and track a CNP and then using pulsed Vgscans that start from and return to the tracked ECNP enables more accurate determination of transfer characteristics of a gFET, according to one or more examples of the present disclosure.

[0199] As discussed with respect to FIGs. 2A and 2B, using continuous digitized Vgsweeps as are used in existing systems to determine transfer characteristics of a gFET is problematic due in significant part to cumulative effects of slow charges such as charge traps, dipoles, and so forth on the effective gate voltage. Moreover, continuous digitized Vgsweeps suffer from errors and inaccuracies that are dependent upon the Vgscan rates, directions, and ranges.

[0200] Using modulated Vgscans that apply very short pulses as gate voltages can help minimize the detrimental effects of slow charges.

[0201] Surprisingly, as the results provided in the graphs 902b, 904b, and 906b in FIG 9B demonstrate, merely replacing continuous digitized Vgsweeps with pulsed Vgscans to determine transfer characteristics can still result in significant errors and inaccuracies.

[0202] The center graph 904b of FIG. 9B depicts an Ad-Eg transfer curve plotted with short-dashed lines generated using a continuous digitized Vgsweep mode as is typically done in existing systems and methods. Also plotted are five Ad-Egtransfer curves generated using modulated Vgpulse code scans in which the unmodulated or baseline voltage level (referred to as a Eg_off) of the TC scanning voltage is configured at five different voltage levels OmV, 150mV, 325mV and 500mv and 650mV. All other pulse code parameters such as number of pulses, pulse amplitude, pulse order, pulse duty cycle, and so forth for the TC scanning voltage are identical.

[0203] For the particular fluid-gated gFET and test conditions used in this example, the “true” FCNP determined and tracked using the systems and methods of the present disclosure is 325 mV. For each of the graphs 902b, 904b, and 906, the curves of the scans in which the unmodulated voltage level of the TC scanning voltage is configured to be set at the tracked FcNPof 325mV are referenced respectively as 908b, 910b, and 912b.

[0204] As may be observed in graph 904b, the I-Vstransfer curve plotted with short- dashed lines generated using a continuous digitized Vgsweep mode appears to have a lowest current point of the curve near the FCNP at 325mV whereas the I-Vstransfer curves generated using unmodulated TC scanning voltages (e.g., Fg_off) values of OmV and 150mV have a low point of the curve that is shifted to right which would result in an inaccurate FCNP values being determined to be at about 525mV and 450mV respectively.

[0205] The 7sd-Fgtransfer curves generated using unmodulated TC scanning voltages (e.g., Fg_off) values of 500mV and 650mV are shifted to the left leading to a determination of FCNP voltage values that are too low.

[0206] Therefore, merely using modulated Vgpulse code scanning to derive I-Vgtransfer curves and to determine other transfer characteristics of the gFET still results in errors and inaccuracies that can materially affect the accuracy of any analysis based on such transfer characteristics.

[0207] Beneficially, by configuring the parameters of the TC scanning pulse code to set the value of the unmodulated TC scanning voltage (Fg_off) to be a tracked FCNP value determined before each set of TC scanning cycles, the transfer characteristics determined by the TC scanning cycles will have accurate values for FCNP as well as for other transfer characteristics.

[0208] The improved accuracy of the disclosed systems and methods for TC scanning with the unmodulated TC scanning voltage set to a tracked FCNP value is further illustrated in the graph 906b.

[0209] The graph 906b shows a comparison of transconductance (gm) curves for the gFET generated using the continuous Vgsweep mode and using each of the unmodulated TC scanning voltage values.

[0210] Transconductance is an important transfer characteristic for gFET applications and indicates the slope of the I-Vgcurve across the range of Vgvalues. For example, in fluid gate gFETs, transconductance can be used to indicate the capacitance of a substance which can be used to determine a relative thickness and / or relative porosity of the substance in the fluid above the gFET channel.

[0211] As may be observed in graph 906b, the gmcurve generated using the continuous Vgsweep method has maximum gm(e.g., slope) values of about ± 1.75 which is significantly higher than the gmcurve 913b generated with the unmodulated TC scanning voltage set to the tracked FCNP value of 325 mV.

[0212] The gmcurves generated with the unmodulated TC scanning voltage set to a voltage level other than the FCNP also have maximum slope values that are noticeably higher than the gmcurve 912b generated with the unmodulated TC scanning voltage set to the tracked FCNP value of 325 mV. Moreover, these other gmcurves have a gmvalue of zero at Vgvalues shifted to the left or the right of the accurate CNP value of 325mV where the gmcurve value should be zero.

[0213] Thus, it can be demonstrated from these empirical results that by using modulated Vgpulse code scans to first find and track CNP which is then configured as the value of the unmodulated TC scanning voltage, the accuracy of transfer characteristics of a gFET is significantly enhanced.

[0214] FIG. 9C is a working example illustrating that using modulated Vg pulse code scans to find and track VCNP and determine transfer characteristics of a gFET enables improved characterization window efficiency and reduced impact of an electric field to surface chemistries, according to one or more examples of the present disclosure.

[0215] As noted with respect to FIG. 2C, because using continuous digitized Vgsweeps to generate transfer curves and determine transfer characteristics for a gFET as performed in existing systems leads to increased duration and magnitude of electric fields generated near the surface of the graphene channel of the gFET which in turn may detrimentally impact surface chemistry structure, analyte structure, and / or reaction kinetics.

[0216] Beneficially, the disclosed systems and methods for performing modulated Vgpulse code TC scanning returns to the unmodulated Vgscanning voltage which is at or near the tracked FCNP for most of the time scanning is being performed. This minimizes the overall duration of potentially detrimental electric field effects.

[0217] Furthermore, because FCNP tracking can be performed before each set of TC scanning cycles, a narrow characterization window can be configured that does not require a range of Vgvoltages to span the complete operation range of the Vgvalues for the gFET but instead merely spans a smaller range of Vgvoltages from slightly below (e.g., tens to hundreds of millivolts below FCNP) to slightly above FCNP (e.g., tens to hundreds of millivolts above FCNP).

[0218] This narrower characterization window minimizes the number of pulses required per set of scanning cycles to span the Vgrange in the window. The amplitude of the required pulse is also minimized since pulses with larger voltage amplitude to determine the outer values of the transfer curves are not required.

[0219] Accordingly, the total duration and amplitude of electric fields produced by generating the transfer curves are significantly minimized and the potentially adverse effects of such fields are also minimized.

[0220] FIG. 10 is a schematic block diagram illustrating a system 1000 for concurrently finding and tracking CNP voltages for multiple fluid-gated gFETs, according to one or more examples of the present disclosure.

[0221] As demonstrated by the above examples, the systems and methods disclosed herein can greatly improve the accuracy, precision, and / or reproducibility of measurement of transfer characteristics of a gFET and of analyses based thereon.

[0222] In various applications, using multiple gFET concurrently can enable the measurement and analysis of multiple analytes under the same or similar environmental conditions.

[0223] Accordingly, a system 1000 depicted in FIG. 10 can be used with the disclosed methods to concurrently track CNP for multiple gFETs.

[0224] The system 1000 and components 1002-1046 thereof are substantially similar to the system 100 and component with similar numbering depicted in FIG. 1 with two modification options for enabling concurrent FCNP tracking.

[0225] With both options, instead of the gFETs 1008a, and 1008b being connected to a common source 1010 or to a common drain 1012, each has an individually supplied source or drain voltage provided by the signal interface circuitry 1036 which includes separate DACs 1038a, 1038b and TIAs 1036a, 1036b to separately apply and / or measure the individual sources and drains of the respective gFETs 1008a, 1008b.

[0226] A tracking voltage Vgis set to an average of the FCNP values for all gFETs. FCNP is tracked for all gFET concurrently by pulsing Fa® and Fs® (where ‘i’ refers to the number for a first gFET or gFET 2) while maintaining Fd® = Fs® + Fsd. The present FCNP® is calculated as Vg- FS(i).

[0227] Another implementation is similar but uses voltage adders to sum FS(i> + Fsa and to sum FS(2)+ FSd. The CNP voltages are then calculated as FCNP(1)= Vg-Fs®.

[0228] FIG. 11 is a schematic flowchart diagram illustrating a method 1100 for tracking a charge neutrality point and determining transfer characteristics, according to one or more examples of the present disclosure.

[0229] The method 1100 includes steps that are substantially similar to those described above with respect to the method 300 and the method 500. In various examples, the method 1100 begins and includes modulating 1102 a present tracking voltage (Vg) to serve as present gate voltages for the gFET with a CNP tracking pulse code configured according to a set of pulse code parameters for a present tracking cycle of a plurality of charge neutrality point tracking cycles for the gFET.

[0230] In some examples, the method 1100 continues and includes comparing 1104 the present tracking voltage (Fg) with a present minimum gate voltage (F mm) solved for by fitting a curve to three current-voltage pairs on a current-voltage response curve (I-Vgcurve) of the gFET based on channel current responses 7Sd measuring current between the source and the drain of the gFET to the present gate voltages applied according to the set of pulse code parameters for the present tracking cycle.

[0231] The method 1100 continues and, in certain examples, includes adjusting 1106 the present tracking voltage Vgby an incremental range finding voltage in response to determining that three current-voltage pairs do not meet one or more predetermined criteria indicating that the present tracking voltage is within a predetermined range for determining a CNP voltage for the present tracking cycle using the 14_miIIsolved for by fitting the curve.

[0232] In various examples, the method 1100 further includes adjusting 1108 the present tracking voltage Vgby a fine-tuning voltage in response to determining that three current-voltage pairs meet one or more criteria indicating that the present tracking voltage is within the predetermined range for determining a present CNP voltage for the present tracking cycle using the I min solved for by fitting the curve.

[0233] In some examples, the method 1100 includes setting 1110 the present CNP voltage to be the present tracking voltage and setting a present CNP current to be a minimum current / sd_min at the Fg_min solved for by fitting the curve.

[0234] At this point, FCNP is tracked and modulated Vgpulse code scanning can be performed using the tracked value of FCNP as the unmodulated TC scanning voltage or Vg_o& using the following steps,

[0235] The method 1100, includes in various examples, configuring 1112 a set of transfer characteristic (TC) scanning cycle parameters for the gFET comprising a selectednumber of TC scanning cycles and gate voltage levels for performing a set of TC scanning cycles that span a selected TC scanning voltage range for the gFET.

[0236] In certain examples, the method 1100 further includes modulating 1114 a present TC scanning voltage Vgthat serves as a gate voltage for the gFET with a TC scanning pulse code configured according to a set of pulse code parameters for a present TC scanning cycle of the set of TC scanning cycles, wherein a pulse voltage magnitude parameter for pairs of step-up gate voltage pulses and step-down gate voltage pulses is changed by a TC scanning voltage adjustment between pairs so that by modulating the TC scanning voltage over the selected number of gate voltage pulses, the set of TC scanning cycles spans the selected TC scanning voltage range.

[0237] In some examples, the method 1100 continues and includes measuring 1116 a present channel current response to the pairs of step-up gate voltage pulses and step-down gate voltage pulses as changed by the TC seaming voltage adjustment for the present TC scanning cycle over the selected number of gate voltage pulses for the set of TC scanning cycles.

[0238] The method 1100 continues and includes, in various examples, determining 1118 one or more transfer characteristic parameters of the gFET based on the measurements performed over the set of TC seaming cycles.

[0239] In certain examples, the method 1100 further includes analyzing 1120 the one or more transfer characteristic parameters of the gFET to characterize one or more interactions of a chemical or biological substance with the gFET.

[0240] The method 1100 may be performed using the system 100 (or the system 1000 with modifications indicated) and components and fmetions thereof as depicted and described above with respect to FIG. 1, FIGs. 3-5, 6-8, 9C, and 10. FIG. 4. The method 1100 may also be implemented in the form of a computer program product configured to be executed by a processor.

[0241] It should be reiterated that the examples disclosed herein are intended to be illustrative and may be adjusted or modified by a person skilled in the art based on the principle and teaching of the present disclosure while still achieving significant improvements over existing systems and methods.

[0242] Examples may be practiced in other specific forms. The described examples are to be considered in all respects only as illustrative and not restrictive. The scope of the invention is, therefore, indicated by the appended claims rather than by the foregoing description. All changes that come within the meaning and range of equivalency of the claims are to be embraced within their scope.

[0243] Various implementations and / or embodiments of the present disclosure are described in the following clauses:

[0244] Various modifications to the implementations described in this disclosure may be readily apparent to persons having ordinary skill in the art, and the generic principles defined herein may be applied to other implementations without departing from the scope of this disclosure. Thus, the claims are not intended to be limited to the implementations shown herein but are to be accorded the widest scope consistent with this disclosure, the principles, and the novel features disclosed herein.

[0245] Additionally, various features that are described in this specification in the context of separate implementations also can be implemented in combination in a single implementation. Conversely, various features that are described in the context of a single implementation also can be implemented in multiple implementations separately or in any suitable subcombination. As such, although features may be described above as acting in particular combinations, and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.

[0246] Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. Further, the drawings may schematically depict one more example processes in the form of a flowchart or flow diagram. However, other operations that are not depicted can be incorporated in the example processes that are schematically illustrated. For example, one or more additional operations can be performed before, after, simultaneously, or between any of the illustrated operations. In some circumstances, multitasking and parallel processing may be advantageous. Moreover, the separation of various system components in the implementations described above should not be understood as requiring such separation in all implementations.

Claims

CLAIMSWhat is claimed is:

1. A system for dynamically tracking a charge neutrality point (CNP) of one or more graphene field effect transistors (gFETs), the system comprising: the one or more graphene field effect transistors (gFETs) each comprising a graphene channel between a source and a drain; signal interface circuitry configured to apply and / or measure electrical signals for the drain and the source of each gFET and to apply and / or measure a signal that serves as a gate voltage for the gFET; a processor and a non-volatile storage medium; and a source and measure module configured to: modulate a present tracking voltage (Vg) that serves as a gate voltage for the gFET with a CNP tracking pulse code configured according to a set of pulse code parameters for a present tracking cycle of a set of charge neutrality point tracking cycles for the gFET; measure and compare the present tracking voltage (Fg) with a present minimum gate voltage (T / , ,,,,,,) solved for by fitting a curve to three current-voltage pairs on a current-voltage response curve (I-Vscurve) of the gFET based on channel current responses to the gate voltages applied according to the set of pulse code parameters for the present tracking cycle; adjust the present tracking voltage Vgby an incremental range finding voltage in response to determining that three current-voltage pairs do not meet one or more criteria indicating that the present tracking voltage is within predetermined range for determining a CNP voltage for the present tracking cycle using the l / ,_millsolved for by fitting the curve; adjust the present tracking voltage Vgby a fine tuning voltage in response to determining that three current-voltage pairs meet one or more criteria indicating that the presenttracking voltage is within predetermined range for determining a present CNP voltage for the present tracking cycle using the F _minsolved for by fitting the curve; and set the present CNP voltage to be the present tracking voltage and set a present CNP current to be a minimum current solved for by fitting the curve, wherein the source and measure module comprises code executable by the processor to cause the signal interface circuitry to source and / or measure electrical signals for the gate, drain, and source of the one or more gFETs.

2. The system of claim 1, wherein the CNP tracking pulse code is configured to include one or more step-up gate voltage pulses ( I / ,+ Vg) and one or more step-down gate voltage pulses (Fg-AVg).

3. The system of claim 2, wherein the source and measure module is further configured to determine: a first average channel current response (7Sdo) as an average of channel currents measured in response to unmodulated present tracking voltages included in the pulse code; a second average channel current response (7Sd+) as an average of channel currents in response to the one or more step-up gate voltage pulses plus the first average channel current response (4do) minus an average of the channel current responses to the unmodulated tracking gate voltages immediately before and after the one or more step-up gate voltage pulses; and a third average channel current response ( / sti-) as an average of channel currents in response to the one or more step-down gate voltage pulses plus the first average channel current response (4do) minus an average of the current responses to the unmodulated tracking gate voltages immediately before and after the one or more step-down gate voltage pulses.

4. The system of claim 3, wherein the source and measure module is further configured to: perform the curve fit as a parabolic curve fit, wherein the three current-voltage pairs consist of: a value of the first average channel current response (7Sdo) and the value of the present tracking voltage Vg(7Sdo, Eg);a value of the second average channel current response (7Sd+) and the average value of the one or more step-up gate voltage pulses (7Sd+, avg(Eg+AVg)); and a value of the third average channel current response (Ad-) and the average value of the one or more step-down gate voltage pulses (Ad-, avg(Kg-AVg)); and solve forg-min and Ad min using the parabolic curve fit to the three current-voltage pairs.

5. The system of claim 1 , wherein for the one or more gFETs that are fluid gated gFETs: the incremental range finding voltage is configured within the range of from about10 mV to about 18 mV; and the fine tuning voltage is configured as a difference between E _mm and the present tracking voltage Eg with a magnitude in a range of from about 0 mV to about 0.5 mV.

6. The system of claim 1, wherein for the one or more gFETs that are fluid gated gFETs the source and measure module is further configured to determine that the present tracking voltage is within the predetermined range for determining a present CNP voltage for the present tracking cycle using theg-min solved for by fitting the curve based on an absolute value of the present tracking voltage Vgminus the value ofg-min solved for by fitting the curve being less than 10 mV.

7. The system of claim 1, wherein for the one or more gFETs that are solid-state-gated gFETs: with the channel of the gFET being separated from a metal gate electrode by a solid-state gate dielectric: the incremental range finding voltage is configured within a range of from about 100 mV to 1000 mV, based on a thickness of the solid-state gate dielectric; and the fine tuning voltage is configured as a difference between Eg_mm and the present tracking voltage Eg with a magnitude based on a thickness of the solid- state gate dielectric.

8. The system of claim 1, wherein for the one or more gFETs that are solid-state-gated gFETs with the channel of the gFET being separated from a metal gate electrode by asolid-state gate dielectric, the source and measure module is further configured to determine that the present tracking voltage is within the predetermined range for determining a present CNP voltage for the present tracking cycle using the min solved for by fitting the curve based on an absolute value of the present tracking voltage Vgminus the value of I min solved for by fitting the curve is within from about 2% to about 5% of a non-zero optimal gate voltage for maximum channel conductance.

9. The system of claim 4, wherein the source and measure module is further configured to determine a direction of an adjustment of the tracking gate voltage for a next CNP tracking cycle by an incremental range finding voltage to be: an increase in tracking gate voltage in response to the second average channel current response related to the one or more step-down gate voltage pulses being lower than the first average channel current response related to the one or more step-up gate voltage pulses; and a decrease in tracking gate voltage in response to the second average channel current response related to the one or more step-down gate voltage pulses being higher than the first average channel current response related to the one or more step-up gate voltage pulses.

10. The system of any of claims 1 to 9, wherein the source and measure module is further configured to: configure a set of a transfer characteristic (TC) scanning cycle parameters for the gFET comprising a selected number of TC scanning cycles and gate voltage levels for performing a set of TC scanning cycles that span a selected TC scanning voltage range for the gFET ; modulate a present TC scanning voltage IT that serves as a gate voltage for the gFET with a TC scanning pulse code configured according to a set of pulse code parameters for a present TC scanning cycle of the set of TC scanning cycles, wherein a pulse voltage magnitude parameter for pairs of step-up gate voltage pulses and step-down gate voltage pulses is changed by a TC scanning voltage adjustment between pairs so that by modulating the TC scanning voltage over the selected number of gate voltage pulses,the set of TC scanning cycles spans the selected TC scanning voltage range; measure a present channel current response to the pairs of step-up gate voltage pulses and step-down gate voltage pulses as changed by the TC scanning voltage adjustment for the present TC scanning cycle over the selected number of gate voltage pulses for the set of TC scanning cycles; and determine one or more transfer characteristic parameters of the gFET based on the measurements performed over the set of TC scanning cycles.

11. The system of any of claim 10, wherein the source and measure module is further configured to: determine a tracked CNP voltage ( Fg_trk ) that meets predetermined criteria for locking and tracking the tracked CNP voltage N_trk by performing the CNP tracking cycles; and set a present TC scanning voltage to be the tracked CNP voltage as the gate voltage to be modulated by the TC scanning voltage adjustment so that between step-up gate voltage pulses and step-down gate voltage pulses, the TC scanning voltage returns to the tracked CNP voltage.

12. The system of any of claim 11, wherein the source and measure module is further configured to: limit a TC scanning voltage range for the set of TC scanning cycles to a selected characterization window that scans less than a full transfer curve of the gFET, wherein the TC scanning voltage window includes the tracked CNP voltage between a minimum TC scanning voltage on a first side and a maximum TC scanning voltage on a second side with sufficient scanned data points to determine a slope on a selected portion of the transfer curve to either side of the tracked CNP voltage.

13. The system of any of claims 1-12, further comprising an analysis module configured to analyze parameters of transfer characteristics that are affected by an interaction of a target with an environment adjacent to the channel of the gFET.

14. A method for dynamically tracking a charge neutrality point (CNP) of a graphene field effect transistor (gFET) comprising a graphene channel between a source and a drainby iteratively performing a plurality of charge neutrality point tracking cycles that comprise: modulating a present tracking voltage (Vg) to serve as present gate voltages for the gFET with a CNP tracking pulse code configured according to a set of pulse code parameters for a present tracking cycle of a plurality of charge neutrality point tracking cycles for the gFET; comparing the present tracking voltage (Fg) with a present minimum gate voltage (F min) solved for by fitting a curve to three current-voltage pairs on a current-voltage response curve (I-Vgcurve) of the gFET based on channel current responses Ad measuring current between the source and the drain of the gFET to the present gate voltages applied according to the set of pulse code parameters for the present tracking cycle; adjusting the present tracking voltage Igby an incremental range finding voltage in response to determining that three current-voltage pairs do not meet one or more predetermined criteria indicating that the present tracking voltage is within a predetermined range for determining a CNP voltage for the present tracking cycle using the solved for by fitting the curve;adjusting the present tracking voltage Vgby a fine tuning voltage in response to determining that three current-voltage pairs meet one or more criteria indicating that the present tracking voltage is within the predetermined range for determining a present CNP voltage for the present tracking cycle using the solved for by fitting the curve; andsetting the present CNP voltage to be the present tracking voltage and setting a present CNP current to be a minimum current d min at the Fg min solved for by fitting the curve.

15. The method of claim 14, further comprising configuring the CNP tracking pulse code to include one or more step-up gate voltage pulses ( Pg+AVg) and one or more step-down gate voltage pulses (Pg-AVg).

16. The method of claim 15, further comprising configuring a tracking gate voltage magnitude parameter for the one or more step-up gate voltage pulses ( Ig+AVg) and the one or more step-down gate voltage pulses (Ig-AVg) based on an effectivedielectric thickness of a fluidic or solid-state substance between a gate electrode and a channel of the gFET.

17. The method of claim 15, further comprising configuring the CNP tracking pulse code to include one or more time periods for applying an unmodulated present tracking voltage Vgbefore or after the one or more step-up gate voltage pulses ( lg+AVg) and the one or more step-down gate voltage pulses (fg-AVg).

18. The method of claim 15, further comprising configuring the pulse code with a consistent modulation order for the one or more step-up gate voltage pulses ( fg+AVg) and the one or more step-down gate voltage pulses ( Ig+AVg) for charge neutrality point (CNP) tracking cycles for a selected application.

19. The method of claim 16, further comprising determining: a first average channel current response (Ado) as an average of channel currents measured in response to unmodulated present tracking voltages included in the pulse code; a second average channel current response (Ad+) as an average of channel currents in response to the one or more step-up gate voltage pulses plus the first average channel current response (Ado) minus an average of the channel current responses to the unmodulated tracking gate voltages immediately before and after the one or more step-up gate voltage pulses; and a third average channel current response (Ad-) as an average of channel currents in response to the one or more step-down gate voltage pulses plus the first average channel current response (Ado) minus an average of the current responses to the unmodulated tracking gate voltages immediately before and after the one or more step-down gate voltage pulses.

20. The method of claim 19, further comprising: performing the curve fit as a parabolic curve fit, wherein the three current-voltage pairs consist of: a value of the first average channel current response (Ado) and the value of the present tracking voltage Vg(Ado, l );a value of the second average channel current response (7Sd+) and the average value of the one or more step-up gate voltage pulses (7Sd+, avg(I ,+AVg)): and a value of the third average channel current response (7Sd-) and the average value of the one or more step-down gate voltage pulses (7^-, avg(Kg-AVg)); and solving for Ig min and / sd_min using the parabolic curve fit to the three currentvoltage pairs.

21. The method of claim 14, further comprising configuring the incremental range finding voltage and the fine tuning voltage based on a gate configuration of the gFET, wherein a fluid gated gFET is configured with: the incremental range finding voltage in the range of from about 10 mV to about 18 mV; and the fine tuning voltage in the range of from about 0.3 mV to about 0.5 mV.

22. The method of claim 14, further comprising configuring the incremental range finding voltage and the fine tuning voltage for a gFET with the channel of the gFET being separated from a metal gate electrode by a solid-state gate dielectric: an incremental range finding voltage magnitude in a range of 100 mV to 1000 mV and related to a thickness of the solid-state gate dielectric; and a fine tuning voltage magnitude in the range of from about 1 mV to about 10 mV and related to a thickness of the solid-state gate dielectric.

23. The method of claim 14, further comprising determining, for a fluid gated gFET, that the present tracking voltage is within the predetermined range for determining a present CNP voltage for the present tracking cycle using the solved for by fitting thecurve based on an absolute value of the present tracking voltage Vgminus the value of Eg min solved for by fitting the curve being less than 10 mV.

24. The method of claim 14, further comprising determining, for a gFET with the channel of the gFET being separated from a metal gate electrode by a solid-state gate dielectric, that the present tracking voltage is within the predetermined range for determining a present CNP voltage for the present tracking cycle using the Fg_min solved for by fitting the curve based on an absolute value of the present tracking voltage Vgminusthe value of min solved for by fitting the curve is within from about 2% to about 5% of a non-zero optimal gate voltage for maximum channel conductance.

25. The method of claim 19, further comprising determining a direction of an adjustment of the tracking gate voltage for a next CNP tracking cycle by an incremental range finding voltage to be: an increase in tracking gate voltage in response to the second average channel current response related to the one or more step-down gate voltage pulses being lower than the first average channel current response related to the one or more step-up gate voltage pulses; and a decrease in tracking gate voltage in response to the second average channel current response related to the one or more step-down gate voltage pulses being higher than the first average channel current response related to the one or more step-up gate voltage pulses.

26. The method of any of claims 14-25, further comprising: configuring a set of a transfer characteristic (TC) scanning cycle parameters for the gFET comprising a selected number of TC scanning cycles and gate voltage levels for performing a set of TC scanning cycles that span a selected TC scanning voltage range for the gFET ; modulating a present TC scanning voltage fj, that serves as a gate voltage for the gFET with a TC scanning pulse code configured according to a set of pulse code parameters for a present TC scanning cycle of the set of TC scanning cycles, wherein a pulse voltage magnitude parameter for pairs of step-up gate voltage pulses and step-down gate voltage pulses is changed by a TC scanning voltage adjustment between pairs so that by modulating the TC scanning voltage over the selected number of gate voltage pulses, the set of TC scanning cycles spans the selected TC scanning voltage range; measuring a present channel current response to the pairs of step-up gate voltage pulses and step-down gate voltage pulses as changed by the TC scanning voltage adjustment for the present TC scanning cycle over the selected number of gate voltage pulses for the set of TC scanning cycles; anddetermining one or more transfer characteristic parameters of the gFET based on the measurements performed over the set of TC scanning cycles.

27. The method of claim 26, further comprising: determining a tracked CNP voltage (F _trk) that meets predetermined criteria for locking and tracking the tracked CNP voltage Fg_trk by performing the CNP tracking cycles; and setting a present TC scanning voltage to be the tracked CNP voltage as the gate voltage to be modulated by the TC scanning voltage adjustment so that between step-up gate voltage pulses and step-down gate voltage pulses, the TC scanning voltage returns to the tracked CNP voltage.

28. The method of claim 26, further comprising: limiting a TC scanning voltage range for the set of TC seaming cycles to a selected characterization window that scans less than a full transfer curve of the gFET, wherein the TC scanning voltage window includes the tracked CNP voltage between a minimum TC scanning voltage on a first side and a maximum TC scanning voltage on a second side with sufficient seamed data points to determine a slope on a selected portion of the transfer curve to either side of the tracked CNP voltage.

29. A computer program product for dynamically tracking a charge neutrality point (CNP) of a graphene field effect transistor (gFET) comprising a graphene charnel between a source and a drain by iteratively performing a plurality of CNP tracking cycles, the computer program product comprising a computer readable storage medium storing code, the code being configured to be executable by a processor to perform operations comprising: modulating a present tracking voltage (17) to serve as present gate voltages for the gFET with a CNP tracking pulse code configured according to a set of pulse code parameters for a present tracking cycle of a plurality of CNP tracking cycles for the gFET; comparing the present tracking voltage (Vg) with a present minimum gate voltage (F min) solved for by fitting a curve to three current-voltage pairs on a current-voltage response curve (I-Vgcurve) of the gFET based on channel current responses 7sd measuring current between the source and the drainof the gFET to the present gate voltages applied according to the set of pulse code parameters for the present tracking cycle; adjusting the present tracking voltage IC by an incremental range finding voltage in response to determining that three current-voltage pairs do not meet one or more predetermined criteria indicating that the present tracking voltage is within a predetermined range for determining a CNP voltage for the present tracking cycle using the ly, ,,,,,, solved for by fitting the curve; adjusting the present tracking voltage Vgby a fine-tuning voltage in response to determining that three current-voltage pairs meet one or more criteria indicating that the present tracking voltage is within the predetermined range for determining a present CNP voltage for the present tracking cycle using the ly, ,,,,,, solved for by fitting the curve; and setting the present CNP voltage to be the present tracking voltage and setting a present CNP current to be a minimum current / sd_min at the ly, ,,,,,, solved for by fitting the curve.

30. The computer program product of claim 29, comprising further code being configured to be executable by a processor to perform further operations comprising: configuring a set of a transfer characteristic (TC) scanning cycle parameters for the gFET comprising a selected number of TC scanning cycles and gate voltage levels for performing a set of TC scanning cycles that span a selected TC scanning voltage range for the gFET ; modulating a present TC scanning voltage Vgthat serves as a gate voltage for the gFET with a TC scanning pulse code configured according to a set of pulse code parameters for a present TC scanning cycle of the set of TC scanning cycles, wherein a pulse voltage magnitude parameter for pairs of step-up gate voltage pulses and step-down gate voltage pulses is changed by a TC scanning voltage adjustment between pairs so that by modulating the TC scanning voltage over the selected number of gate voltage pulses, the set of TC scanning cycles spans the selected TC scanning voltage range; measuring a present channel current response to the pairs of step-up gate voltage pulses and step-down gate voltage pulses as changed by the TC scanningvoltage adjustment for the present TC scanning cycle over the selected number of gate voltage pulses for the set of TC scanning cycles; and determining one or more transfer characteristic parameters of the gFET based on the measurements performed over the set of TC scanning cycles.

Images