Semiconductor storage device

Abstract

An SRAM cell is provided with an active region (N2) in which a drive transistor (PD1) is formed and an active region (N3) in which a drive transistor (PD2) is formed. Power supply wirings (12, 13) for supplying a power supply voltage VSS are formed in a back wiring layer. A portion serving as a source of the drive transistor (PD1) is connected to the power supply wiring (12) via a via (91) provided at a position overlapping the power supply wiring (12) in a plan view. A portion serving as a source of the drive transistor (PD2) is connected to the power supply wiring (13) via a via (92) provided at a position overlapping the power supply wiring (13) in a plan view.

Description

semiconductor memory device

[0001] The present disclosure relates to a semiconductor memory device equipped with a nanosheet FET (Field Effect Transistor), and in particular to a layout structure of a two-port SRAM (Static Random Access Memory) cell (hereinafter, also referred to simply as a cell, as appropriate) using a nanosheet FET.

[0002] SRAMs are widely used in semiconductor integrated circuits, and include dual-port SRAMs that have two ports for reading and writing data.

[0003] Furthermore, transistors, which are fundamental components of LSIs, have achieved improved integration density, reduced operating voltages, and improved operating speeds through the reduction of gate length (scaling). However, in recent years, excessive scaling has led to problems with off-state current and the resulting significant increase in power consumption. To solve this problem, three-dimensional transistors, which change the transistor structure from the conventional planar type to a three-dimensional type, have been actively researched. Nanosheet FETs are one type of three-dimensional transistor that has attracted attention.

[0004] Patent Document 1 discloses an SRAM cell that uses a fork sheet transistor, which is a nanosheet FET and has a gate electrode in a fork shape, in order to reduce the area of ​​a semiconductor memory device.

[0005] International Publication No. 2021 / 153169

[0006] In the technology of Patent Document 1, the bit lines and power supply lines are provided in the same wiring layer, so the wiring width of the bit lines cannot be increased. This increases the wiring resistance of the bit lines and reduces the operating speed of the semiconductor memory device. Furthermore, since the bit lines and power supply lines are provided in the same wiring layer, the wiring width of the power supply lines cannot be increased. This increases the wiring resistance of the power supply lines and increases the power supply voltage drop, reducing the operating speed and stability of the semiconductor memory device. Furthermore, the distance between the bit lines and power supply lines is short, so parasitic capacitance increases and the operating speed of the semiconductor memory device is reduced.

[0007] The present disclosure aims to improve the operating speed of a semiconductor memory device in a layout structure of an SRAM cell.

[0008] In a first aspect of the present disclosure, there is provided a semiconductor memory device including an SRAM cell, the SRAM cell comprising a first transistor having a source connected to a first power supply that supplies a first power supply voltage, a drain connected to a first node, and a gate connected to a second node; a second transistor having a source connected to the first power supply, a drain connected to the second node, and a gate connected to the first node; a third transistor having a source connected to a first bit line, a drain connected to the first node, and a gate connected to a first word line; and a second bit line having a source connected to a second word line that forms a first complementary bit line pair with the first bit line. a fourth transistor having a source connected to a third bit line, a drain connected to the first node, and a gate connected to the first word line; a fifth transistor having a source connected to a third bit line, a drain connected to the first node, and a gate connected to the second word line; a sixth transistor having a source connected to a fourth bit line forming a second complementary bit line pair with the third bit line, a drain connected to the second node, and a gate connected to the second word line; and a sixth transistor having a source connected to a second power supply supplying a second power supply voltage different from the first power supply voltage, a drain connected to the first node, and a gate connected to the second node. a seventh transistor connected at its source to the second power supply, its drain to the second node, and its gate to the first node, wherein the SRAM cell comprises a first active region constituting the channel, source, and drain of the third transistor, the channel of which comprises a third nanosheet extending in a first direction, and a channel, source, and drain of the fifth transistor, the channel of which comprises the fifth nanosheet extending in the first direction; a second active region constituting the channel, source, and drain of the seventh transistor, the channel of which comprises a seventh nanosheet extending in the first direction; a third active region constituting the channel, source, and drain of the eighth transistor, the channel of which comprises an eighth nanosheet extending in the first direction; a fourth active region constituting the channel, source, and drain of the fourth transistor, the channel of which comprises the fourth nanosheet extending in the first direction, and a channel, source, and drain of the sixth transistor, the channel of which comprisesa fourth active region including a sixth nanosheet extending in the first direction; a fifth active region constituting the channel, source, and drain of the first transistor and including the first nanosheet extending in the first direction as the channel; a sixth active region constituting the channel, source, and drain of the second transistor and including the second nanosheet extending in the first direction as the channel; first to eighth gate wirings surrounding the first to eighth nanosheets in a second direction perpendicular to the first direction and in a depth direction perpendicular to the first and second directions, respectively; first and second power supply wirings formed in a back wiring layer on the back side of the first to eighth transistors, extending in the first direction, and supplying the second power supply voltage; a first via formed in a region where a region that will become the source of the seventh transistor overlaps with the first power supply wiring and connects the source of the seventh transistor in the second active region to the first power supply wiring; and a second via formed in a region where a region that will become the source of the eighth transistor overlaps with the first power supply wiring and connects the source of the eighth transistor in the third active region to the second power supply wiring, wherein the first, third, fifth, and eighth nanosheets have first-side surfaces, which are one side in the second direction, exposed from the first, third, fifth, and eighth gate wirings, respectively, and the second, fourth, sixth, and seventh nanosheets have second-side surfaces, which are the other side in the second direction, exposed from the second, fourth, sixth, and seventh gate wirings, respectively.

[0009] According to the present disclosure, first and second power supply wirings for supplying a second power supply voltage are formed in a backside wiring layer. This allows the wiring width of the bit lines to be increased. Therefore, the wiring resistance of the bit lines can be reduced, thereby improving the operating speed of the semiconductor memory device. Furthermore, the wiring width of the first and second power supply wirings can be increased. Therefore, the wiring resistance of the power supply wiring can be reduced, and a power supply voltage drop can be reduced, thereby improving the operating speed and stability of the semiconductor memory device. Furthermore, since the bit lines and the power supply wirings are formed in different wiring layers, the distance between the bit lines and the power supply wirings can be increased. Therefore, the parasitic capacitance between the bit lines and the power supply wirings can be reduced, thereby improving the operating speed of the semiconductor memory device.

[0010] A second aspect of the present disclosure is a semiconductor memory device including an SRAM cell, the SRAM cell comprising a first transistor having a source connected to a first power supply that supplies a first power supply voltage, a drain connected to a first node, and a gate connected to a second node; a second transistor having a source connected to the first power supply, a drain connected to the second node, and a gate connected to the first node; a third transistor having a source connected to a first bit line, a drain connected to the first node, and a gate connected to a first word line; and a second bit line having a source connected to a second word line that forms a first complementary bit line pair with the first bit line. a fourth transistor having a source connected to a third bit line, a drain connected to the first node, and a gate connected to the first word line; a fifth transistor having a source connected to a third bit line, a drain connected to the first node, and a gate connected to the second word line; a sixth transistor having a source connected to a fourth bit line forming a second complementary bit line pair with the third bit line, a drain connected to the second node, and a gate connected to the second word line; a sixth transistor having a source connected to a second power supply that supplies a second power supply voltage different from the first power supply voltage, a drain connected to the first node, and a gate connected to the second node; and an eighth transistor having a source connected to the second power supply, a drain connected to the second node, and a gate connected to the first node, wherein the seventh transistor includes a ninth transistor and a tenth transistor, and the eighth transistor includes an eleventh transistor and a twelfth transistor. The SRAM cell includes a first active region constituting the channel, source, and drain of the fifth transistor, the channel including a fifth nanosheet extending in a first direction, and the channel, source, and drain of the ninth transistor, the channel including a ninth nanosheet extending in the first direction; a second active region constituting the channel, source, and drain of the third transistor, the channel including a third nanosheet extending in the first direction, and the channel, source, and drain of the tenth transistor, the channel including a tenth nanosheet extending in the first direction; and a channel, source, and drain of the sixth transistor, the channel includinga third active region constituting the channel, source, and drain of the eleventh transistor and including the sixth nanosheet extending in the first direction, and the eleventh nanosheet extending in the first direction as the channel; a fourth active region constituting the channel, source, and drain of the fourth transistor and including the fourth nanosheet extending in the first direction as the channel; and a twelfth nanosheet extending in the first direction as the channel; a fifth active region constituting the channel, source, and drain of the first transistor and including the first nanosheet extending in the first direction as the channel; a sixth active region constituting the channel, source, and drain of the second transistor and including the second nanosheet extending in the first direction as the channel; and first to sixth and ninth to twelfth gates surrounding the first to sixth and ninth to twelfth nanosheets in a second direction perpendicular to the first direction and in a depth direction perpendicular to the first and second directions, respectively. a first via connecting the source of the ninth transistor in the first active region to the first power supply wiring and a second via connecting the source of the tenth transistor in the second active region to the first power supply wiring, the first via being formed in a back wiring layer on the back side of the first to sixth and ninth to twelfth transistors and extending in the first direction, the first and second power supply wirings supplying the second power supply voltage and formed in a region where a region to be the source of the ninth transistor in the first active region overlaps with the first power supply wiring; a first via connecting the source of the ninth transistor in the first active region to the first power supply wiring and formed in a region where a region to be the source of the tenth transistor in the second active region overlaps with the first power supply wiring; a second via connecting the source of the tenth transistor in the second active region to the first power supply wiring and formed in a region where a region to be the source of the eleventh transistor in the third active region overlaps with the second power supply wiring;and at least one fourth via connecting the source of the twelfth transistor in the fourth active region to the second power supply wiring, wherein the first, fifth, sixth, ninth, and eleventh nanosheets have first-side surfaces, which are one side in the second direction, exposed from the first, fifth, sixth, ninth, and eleventh gate wirings, respectively, and the second, third, fourth, tenth, and twelfth nanosheets have second-side surfaces, which are the other side in the second direction, exposed from the second, third, fourth, tenth, and twelfth gate wirings, respectively.

[0011] According to the present disclosure, first and second power supply wirings for supplying a second power supply voltage are formed in a backside wiring layer. This allows the wiring width of the bit lines to be increased. Therefore, the wiring resistance of the bit lines can be reduced, thereby improving the operating speed of the semiconductor memory device. Furthermore, the wiring width of the first and second power supply wirings can be increased. Therefore, the wiring resistance of the power supply wiring can be reduced, and a power supply voltage drop can be reduced, thereby improving the operating speed and stability of the semiconductor memory device. Furthermore, since the bit lines and the power supply wirings are formed in different wiring layers, the distance between the bit lines and the power supply wirings can be increased. Therefore, the parasitic capacitance between the bit lines and the power supply wirings can be reduced, thereby improving the operating speed of the semiconductor memory device.

[0012] A third aspect of the present disclosure is a semiconductor memory device including an SRAM cell, the SRAM cell comprising: a first transistor having a source connected to a first power supply that supplies a first power supply voltage, a drain connected to a first node, and a gate connected to a second node; a second transistor having a source connected to the first power supply, a drain connected to the second node, and a gate connected to the first node; a third transistor having a source connected to a first bit line, a drain connected to the first node, and a gate connected to a first word line; and a third transistor having a source connected to the first bit line and a first complementary bit line pair. a fourth transistor having a drain connected to the second node and a gate connected to the first word line, a fifth transistor having a source connected to the third bit line, a drain connected to the first node and a gate connected to the second word line, a sixth transistor having a source connected to the fourth bit line forming a second complementary bit line pair with the third bit line, a drain connected to the second node and a gate connected to the second word line, and a sixth transistor having a source connected to a second power supply that supplies a second power supply voltage different from the first power supply voltage, a drain connected to the first node and a gate connected to the second word line. the seventh transistor includes a ninth transistor and a tenth transistor, and the eighth transistor includes an eleventh transistor and a twelfth transistor; the first bit line is formed in a back wiring layer on the back side of the first to sixth and ninth to twelfth transistors and includes a first wiring extending in a first direction; the second bit line is formed in the back wiring layer and includes a second wiring extending in the first direction; the third bit line is formed in the back wiring layer and includes a third wiring extending in the first direction; the fourth bit line is formed in the back wiring layer and includes a fourth wiring extending in the first direction; the SRAM cell constitutes a channel, a source, and a drain of the fifth transistor, the channel of which includes a fifth nanosheet extending in the first direction, and the channel of the ninth transistor includes a fifth nanosheet extending in the first direction.a first active region including a ninth nanosheet extending in the first direction; a second active region forming the channel, source, and drain of the third transistor, the channel including the third nanosheet extending in the first direction, and the channel, source, and drain of the tenth transistor, the channel including the tenth nanosheet extending in the first direction; a third active region forming the channel, source, and drain of the sixth transistor, the channel including the sixth nanosheet extending in the first direction, and the channel, source, and drain of the eleventh transistor, the channel including the eleventh nanosheet extending in the first direction; a fourth active region forming the channel, source, and drain of the fourth transistor, the channel including the fourth nanosheet extending in the first direction, and the channel, source, and drain of the twelfth transistor, the channel including the twelfth nanosheet extending in the first direction; a fifth active region including a first nanosheet extending in the first direction as the channel, constituting the channel, source, and drain of the second transistor; a sixth active region including a second nanosheet extending in the first direction as the channel; first to sixth and ninth to twelfth gate wirings surrounding the first to sixth and ninth to twelfth nanosheets in a second direction perpendicular to the first direction and in a depth direction perpendicular to the first and second directions, respectively; a first via connecting the source of the third transistor to the first wiring in the second active region, formed in a region where the source of the fourth transistor to the second wiring overlaps in the fourth active region; a second via connecting the source of the fourth transistor to the second wiring in the fourth active region, formed in a region where the source of the fifth transistor to the third wiring overlaps in the first active region;The semiconductor device includes a third via that connects the source of the fifth transistor in the first active region to the third wiring, and a fourth via that is formed in a region where a region that becomes the source of the sixth transistor in the third active region overlaps with the fourth wiring and connects the source of the sixth transistor in the third active region to the fourth wiring, wherein the first, fifth, sixth, ninth, and eleventh nanosheets have first side surfaces, which are one side in the second direction, exposed from the first, fifth, sixth, ninth, and eleventh gate wirings, respectively, and the second, third, fourth, tenth, and twelfth nanosheets have second side surfaces, which are the other side in the second direction, exposed from the second, third, fourth, tenth, and twelfth gate wirings, respectively.

[0013] According to the present disclosure, first to fourth wirings corresponding to the first to fourth bit lines, respectively, are formed in the back wiring layer. This allows the wiring width of the bit lines to be increased. Therefore, the wiring resistance of the bit lines can be reduced, thereby improving the operating speed of the semiconductor memory device. Furthermore, the wiring width of the power supply wiring can be increased. Therefore, the wiring resistance of the power supply wiring can be reduced, and power supply voltage drops can be reduced, thereby improving the operating speed and stability of the semiconductor memory device. Furthermore, since the bit lines and the power supply wiring are formed in different wiring layers, the distance between the bit lines and the power supply wiring can be increased. Therefore, the parasitic capacitance between the bit lines and the power supply wiring can be reduced, thereby improving the operating speed of the semiconductor memory device.

[0014] According to the present disclosure, the operating speed of a semiconductor memory device can be improved in a layout structure of an SRAM cell.

[0015] 1 is a plan view showing an example of a layout structure of an SRAM cell according to the first embodiment. FIG. 2 is a cross-sectional view showing an example of a layout structure of an SRAM cell according to the first embodiment. FIG. 3 is a circuit diagram showing a configuration of an SRAM cell according to the first embodiment. FIG. 4 is another configuration example of a semiconductor integrated circuit device according to the first embodiment. FIG. 5 is a plan view showing another example of a layout structure of an SRAM cell according to the first embodiment. FIG. 6 is a plan view showing another example of a layout structure of an SRAM cell according to the first embodiment. FIG. 7 is a plan view showing another example of a layout structure of an SRAM cell according to the first embodiment. FIG. 8 is a plan view showing another example of a layout structure of an SRAM cell according to the first embodiment. FIG. 9 is a plan view showing another example of a layout structure of an SRAM cell according to the first embodiment. FIG. 10 is a plan view showing another example of a layout structure of an SRAM cell according to the first embodiment. FIG. 10 is a plan view showing another example of the layout structure of the SRAM cell according to the second embodiment.

[0016] Hereinafter, embodiments will be described with reference to the drawings. In the following embodiments, a semiconductor memory device includes a plurality of SRAM cells, and at least some of the plurality of SRAM cells include fork sheet transistors, which are nanosheet FETs and have fork-shaped gate electrodes. A nanosheet FET is a FET that uses a thin sheet (nanosheet) through which current flows. The nanosheet is formed of, for example, silicon. In the semiconductor memory device, some of the nanosheet FETs are fork sheet FETs with fork-shaped gate electrodes.

[0017] In this specification, "VDD" and "VSS" refer to the power supply voltage or the power supply itself. In this specification, expressions such as "same wiring width" that mean the same width, etc., are considered to include the range of manufacturing variations.

[0018] (First Embodiment) (Configuration of SRAM Cell) Figures 1 to 3 show an example of the layout structure of an SRAM cell according to the first embodiment, with Figures 1(a) and 1(b) being plan views, and Figures 2(a) to 2(c) and 3(a) and 3(b) being cross-sectional views in the horizontal direction in a plan view. Specifically, Figure 1(a) shows the upper part of the cell, which is the M1 and M2 wiring layers, and Figure 1(b) shows the lower part of the cell, which is a layer below the M1 and M2 wiring layers and includes a nanosheet FET. Figure 2(a) is a cross-section along line X1-X1', Figure 2(b) is a cross-section along line X2-X2', Figure 2(c) is a cross-section along line X3-X3', Figure 3(a) is a cross-section along line X4-X4', and Figure 3(b) is a cross-section along line X5-X5'.

[0019] In the following description, in plan views such as Figure 1, the vertical direction of the drawing is the Y direction (first direction), the horizontal direction of the drawing is the X direction (second direction), and the direction perpendicular to the substrate surface is the Z direction (depth direction).

[0020] 4 is a circuit diagram showing the configuration of a two-port SRAM cell according to the first embodiment. As shown in FIG. 4, the two-port SRAM cell according to this embodiment has a two-port SRAM cell circuit made up of load transistors PU1 and PU2, drive transistors PD1 and PD2, and access transistors PG1 to PG4. The load transistors PU1 and PU2 are P-type FETs, and the drive transistors PD1 and PD2 and the access transistors PG1 to PG4 are N-type FETs.

[0021] The load transistor PU1 is provided between the power supply VDD and a first node NA, and the drive transistor PD1 is provided between the first node NA and a power supply VSS. The gates of the load transistor PU1 and the drive transistor PD1 are connected to a second node NB, and they form an inverter INV1. The load transistor PU2 is provided between the power supply VDD and the second node NB, and the drive transistor PD2 is provided between the second node NB and the power supply VSS. The gates of the load transistor PU2 and the drive transistor PD2 are connected to the first node NA, and they form an inverter INV2. In other words, the output of one inverter is connected to the input of the other inverter, thereby forming a latch.

[0022] The access transistor PG1 is provided between the first bit line BLA and the first node NA, and its gate is connected to the first word line WLA. The access transistor PG2 is provided between the second bit line BLAX and the second node NB, and its gate is connected to the first word line WLA. The access transistor PG3 is provided between the third bit line BLB and the first node NA, and its gate is connected to the second word line WLB. The access transistor PG4 is provided between the fourth bit line BLBX and the second node NB, and its gate is connected to the second word line WLB. The first and second bit lines BLA and BLAX form a first complementary bit line pair, and the third and fourth bit lines BLB and BLBX form a second complementary bit line pair.

[0023] In a two-port SRAM cell circuit, when the first and second bit lines BLA, BLAX constituting a first complementary bit line pair are driven to a high level and a low level, respectively, and the first word line WLA is driven to a high level, a high level is written to the first node NA and a low level is written to the second node NB. On the other hand, when the first and second bit lines BLA, BLAX are driven to a low level and a high level, respectively, and the first word line WLA is driven to a high level, a low level is written to the first node NA and a high level is written to the second node NB. Then, when the first word line WLA is driven to a low level while data is written to the first and second nodes NA, NB, the latch state is established and the data written to the first and second nodes NA, NB is held.

[0024] Furthermore, when the first and second bit lines BLA, BLAX are precharged to a high level and the first word line WLA is driven to a high level, the states of the first and second bit lines BLA, BLAX are determined according to the data written to the first and second nodes NA, NB, making it possible to read data from the SRAM cell. Specifically, when the first node NA is at a high level and the second node NB is at a low level, the first bit line BLA is held at a high level and the second bit line BLAX is discharged to a low level. On the other hand, when the first node NA is at a low level and the second node NB is at a high level, the first bit line BLA is discharged to a low level and the second bit line BLAX is held at a high level.

[0025] Furthermore, when the third and fourth bit lines BLB, BLBX constituting the second complementary bit line pair are driven to a high level and a low level, respectively, and the second word line WLB is driven to a high level, a high level is written to the first node NA and a low level is written to the second node NB. On the other hand, when the third and fourth bit lines BLB, BLBX are driven to a low level and a high level, respectively, and the second word line WLB is driven to a high level, a low level is written to the first node NA and a high level is written to the second node NB. Then, when the second word line WLB is driven to a low level while data is written to the first and second nodes NA, NB, the latch state is established and the data written to the first and second nodes NA, NB is held.

[0026] Furthermore, when the third and fourth bit lines BLB, BLBX are precharged to a high level in advance and the second word line WLB is driven to a high level, the states of the third and fourth bit lines BLB, BLBX are determined according to the data written to the first and second nodes NA, NB, making it possible to read data from the SRAM cell. Specifically, when the first node NA is at a high level and the second node NB is at a low level, the third bit line BLB is held at a high level and the fourth bit line BLBX is discharged to a low level. On the other hand, when the first node NA is at a low level and the second node NB is at a high level, the third bit line BLB is discharged to a low level and the fourth bit line BLBX is held at a high level.

[0027] As described above, the two-port SRAM cell has the functions of writing data to, retaining data, and reading data from the SRAM cell by controlling the first and second bit lines BLA, BLAX and the first word line WLA. Also, the two-port SRAM cell has the functions of writing data to, retaining data, and reading data from the SRAM cell by controlling the third and fourth bit lines BLB, BLBX and the second word line WLB.

[0028] In the following description, the dashed lines running vertically and horizontally in plan views such as FIG. 1 and the dashed lines running vertically in cross-sectional views such as FIG. 2 indicate grids used for component placement during design. The grids are arranged at equal intervals in the X direction and at equal intervals in the Y direction. The grid spacing may be the same or different in the X and Y directions. The grid spacing may also be different for each layer. Furthermore, each component does not necessarily have to be arranged on a grid.

[0029] 1 and other plan views, the dotted lines surrounding the cells indicate the cell frame (outer edge of the SRAM cell) of the SRAM cell. The SRAM cell is arranged so that the cell frame is in contact with the cell frame of an adjacent cell in the X or Y direction.

[0030] 1 and the like, an SRAM cell is arranged on each side of the SRAM cell in the X direction, with the SRAM cell inverted in the X direction, and an SRAM cell is arranged on each side of the SRAM cell in the Y direction, with the SRAM cell inverted in the Y direction.

[0031] 1B, a BM0 (Backside Metal 0) wiring layer is formed on the back surface of the semiconductor chip on which the transistors are formed. The BM0 wiring layer corresponds to the back surface wiring layer.

[0032] The BM0 wiring layer is formed with power supply wirings 11 to 13 that extend in the Y direction from the top to the bottom of the cell in the drawing. Power supply wiring 11 is formed in the center of the cell in the X direction and supplies power supply voltage VDD. Power supply wiring 12 is formed at the left end of the cell in the X direction and supplies power supply voltage VSS. Power supply wiring 13 is formed at the right end of the cell in the X direction and supplies power supply voltage VSS. Power supply wiring 12 is shared with other cells arranged on the left side of the drawing. Power supply wiring 13 is shared with other cells arranged on the right side of the drawing.

[0033] A plurality of active regions constituting the channel, source, and drain of the N-type transistor are formed in an N-type transistor region on a P-type substrate (PSub) (not shown). Specifically, active regions N1 to N4 are formed in the N-type transistor region. Active regions N1 and N2 overlap with power supply wiring 12 in a plan view. Active regions N3 and N4 overlap with power supply wiring 13 in a plan view.

[0034] In the N-type transistor region, access transistors PG1 to PG4 and drive transistors PD1 and PD2 are formed. The access transistors PG3 and PG1, the drive transistors PD1 and PD2, and the access transistors PG4 and PG2 each have a channel structure of three overlapping sheets in a plan view, and each have nanosheets 21 to 26 extending in the Y direction.

[0035] In the active region N2, the portion that becomes the source of the drive transistor PD1 is connected to the power supply wiring 12 through a via 91 that is provided at a position that overlaps the power supply wiring 12 in a plan view. In the active region N3, the portion that becomes the source of the drive transistor PD2 is connected to the power supply wiring 13 through a via 92 that is provided at a position that overlaps the power supply wiring 13 in a plan view.

[0036] A plurality of active regions constituting the channel, source, and drain of the P-type transistor are formed in a P-type transistor region on an N-type well (NWell) (not shown). Specifically, active regions P1 and P2 are formed in the P-type transistor region. The active regions P1 and P2 overlap with the power supply wiring 11 in a plan view.

[0037] In the P-type transistor region, load transistors PU1 and PU2 are formed. The load transistors PU1 and PU2 have channels formed of nanosheets 27 and 28, respectively, each of which has a three-sheet structure overlapping in a plan view and extends in the Y direction.

[0038] The width in the X direction of nanosheets 21, 22, 25, and 26 is twice the width in the X direction of nanosheets 27 and 28. The width in the X direction of nanosheets 23 and 24 is four times the width in the X direction of nanosheets 27 and 28.

[0039] In the active region P1, the portion that becomes the source of the load transistor PU1 is connected to the power supply wiring 11 through a via 93 that is provided at a position that overlaps the power supply wiring 11 in a planar view. In the active region P2, the portion that becomes the source of the load transistor PU2 is connected to the power supply wiring 11 through a via 94 that is provided at a position that overlaps the power supply wiring 11 in a planar view.

[0040] In the active region, the portions that become the source and drain on both sides of the nanosheet are formed, for example, by epitaxial growth from the nanosheet.

[0041] Gate wirings (Gate) 31 to 38 are formed extending in the X direction. The gate wiring 31 overlaps with the nanosheet 21 in a planar view. The gate wiring 33 overlaps with the nanosheets 28 and 24 in a planar view. The gate wiring 34 overlaps with the nanosheet 25 in a planar view. The gate wiring 35 overlaps with the nanosheet 22 in a planar view. The gate wiring 36 overlaps with the nanosheets 23 and 27 in a planar view. The gate wiring 38 overlaps with the nanosheet 26 in a planar view. The gate wiring 31 corresponds to the gate of the access transistor PG3. The gate wiring 33 corresponds to the gates of the load transistor PU2 and the drive transistor PD2. The gate wiring 34 corresponds to the gate of the access transistor PG4. The gate wiring 35 corresponds to the gate of the access transistor PG1. The gate wiring 36 corresponds to the gates of the drive transistor PD1 and the load transistor PU1. The gate wiring 38 corresponds to the gate of the access transistor PG2.

[0042] As shown in Figures 2(b) and 3(a), nanosheets 21 to 28 are each covered by the gate wiring so that a portion of their outer peripheries is exposed. Specifically, nanosheets 21, 22, 24, and 27 have their right-hand surfaces in the X direction exposed from gate wirings 31, 35, 33, and 36, respectively, and their left-hand surfaces in the X direction covered by gate wirings 31, 35, 33, and 36, respectively. Nanosheets 23, 25, 26, and 28 have their left-hand surfaces in the X direction exposed from gate wirings 36, 34, 38, and 33, respectively, and their right-hand surfaces in the X direction covered by gate wirings 36, 34, 38, and 33, respectively. That is, nanosheets 22 (21) and 23 have their opposing surfaces in the X direction exposed from gate wirings 35 (31) and 36, respectively. The surfaces of the nanosheets 24, 25 (26) that face each other in the X direction are exposed from the gate wirings 33, 34 (38), respectively. The surfaces of the nanosheets 27, 28 that face each other in the X direction are exposed from the gate wirings 36, 33, respectively.

[0043] The gate wirings 32 and 33 are connected via a bridge portion 40a extending in the X direction, and the gate wirings 36 and 37 are connected via a bridge portion 40b extending in the X direction.

[0044] The local interconnect layer has local interconnects (LI) 41 to 50 extending in the X direction. The local interconnect 41 is connected to a portion that will become the source of the access transistor PG3 in the active region N1. The local interconnect 42 is connected to a portion that will become the source of the load transistor PU2 in the active region P2. The local interconnect 43 is connected to a portion that will become the source of the drive transistor PD2 in the active region N3. The local interconnect 44 is connected to a portion that will become the source of the access transistor PG4 in the active region N4. The local interconnect 45 is connected to a portion that will become the drain of the access transistor PG3 in the active region N1, a portion that will become the drain of the access transistor PG1 in the active region N1, a portion that will become the drain of the drive transistor PD1 in the active region N2, and a portion that will become the drain of the load transistor PU1 in the active region P1. Local interconnection 46 is connected to the drain of load transistor PU2 in active region P2, the drain of drive transistor PD2 in active region N3, the drain of access transistor PG4 in active region N4, and the drain of access transistor PG2 in active region N4. Local interconnection 47 is connected to the source of access transistor PG1 in active region N1. Local interconnection 48 is connected to the source of drive transistor PD1 in active region N2. Local interconnection 49 is connected to the source of load transistor PU1 in active region P1. Local interconnection 50 is connected to the source of access transistor PG2 in active region N4.

[0045] The local wiring 45 is connected to the gate wiring 32 via a shared contact 51. The local wiring 46 is connected to the gate wiring 37 via a shared contact 52. The gate wirings 32 and 33, the bridge portion 40 a, the local wiring 45, and the shared contact 51 correspond to a first node NA. The gate wirings 36 and 37, the bridge portion 40 b, the local wiring 46, and the shared contact 52 correspond to a second node NB.

[0046] As shown in FIG. 1A, wires 61 to 64 extending in the Y direction from the top to the bottom of the cell are formed in the M1 wiring layer, which is a metal wiring layer above the local wiring layer. Wires 65 to 68 are also formed. Wires 61 to 64 correspond to the first bit line BLA, the third bit line BLB, the second bit line BLAX, and the fourth bit line BLBX, respectively. Wire 61 overlaps with active region N1 and power supply wiring 12 in a planar view. Wire 62 overlaps with active region N2 and power supply wiring 12 in a planar view. Wire 63 overlaps with active region N3 and power supply wiring 13 in a planar view. Wire 64 overlaps with active region N4 and power supply wiring 13 in a planar view.

[0047] The wiring 61 is connected to the local wiring 47 through a via 53. The wiring 62 is connected to the local wiring 41 through a via 54. The wiring 63 is connected to the local wiring 50 through a via 55. The wiring 64 is connected to the local wiring 44 through a via 56.

[0048] Wirings 71 and 72 extending in the X direction from the left to the right of the cell in the drawing are formed in the M2 wiring layer, which is an upper layer of the M1 wiring layer. Wirings 71 and 72 correspond to the first word line WLA and the second word line WLB, respectively. Wiring 71 is connected to gate wiring 35 via via 81, wiring 65, and via 57. Wiring 71 is connected to gate wiring 38 via via 82, wiring 66, and via 58. Wiring 72 is connected to gate wiring 31 via via 83, wiring 67, and via 59. Wiring 72 is connected to gate wiring 34 via via 84, wiring 68, and via 60.

[0049] With the above configuration, a power supply wiring 11 that supplies a power supply voltage VDD and power supply wirings 12 and 13 that supply a power supply voltage VSS are formed in the BM0 wiring layer, which is a wiring layer on the back surface of the transistor. Wirings 61, 62, 63, and 64 corresponding to the first bit line BLA, the third bit line BLB, the second bit line BLAX, and the fourth bit line BLBX, respectively, are formed in the M1 wiring layer, which is a metal wiring layer above the transistor. As a result, the wiring formed in the M1 wiring layer is limited to bit lines, allowing the wiring widths of the wirings 61 to 64 to be increased. Therefore, the wiring resistance of the bit lines can be reduced, thereby improving the operating speed of the semiconductor memory device. Furthermore, since the wiring formed in the BM0 wiring layer is limited to power supply wirings that supply power supply voltages VDD and VSS, the wiring widths of the power supply wirings 11 to 13 can be increased. Therefore, the wiring resistance of the power supply wiring can be reduced, and power supply voltage drops can be suppressed, thereby improving the operating speed and stability of the semiconductor memory device. Furthermore, because the bit lines and the power supply lines are formed in different wiring layers, the distance between the bit lines and the power supply lines can be increased. Therefore, the parasitic capacitance between the bit lines and the power supply lines can be reduced, thereby improving the operating speed of the semiconductor memory device. Furthermore, by increasing the wiring width of the power supply lines 11 to 13, the wiring resistance of the lines supplying the power supply voltages VDD and VSS can be reduced, improving the stability of operation, particularly the retention characteristics (static noise margin) of the SRAM cells.

[0050] Furthermore, the power supply wirings 12 and 13 formed in the BM0 wiring layer and supplying the power supply voltage VSS are arranged at the left and right ends of the cell in the X direction in the drawing, respectively, and are shared with the cells arranged on the left and right sides of the drawing, respectively. This allows the power supply wiring that supplies the power supply voltage VSS to be strengthened, thereby improving the operating speed of the semiconductor memory device. Note that in FIG. 1, the power supply wirings 12 and 13 do not necessarily have to be arranged at the left and right ends of the drawing in the X direction.

[0051] Furthermore, the surfaces of the nanosheets 22 (21) and 23 facing each other in the X direction are exposed from the gate wirings 35 (31) and 36, respectively. The surfaces of the nanosheets 24 and 25 (26) facing each other in the X direction are exposed from the gate wirings 33 and 34 (38), respectively. The surfaces of the nanosheets 27 and 28 facing each other in the X direction are exposed from the gate wirings 36 and 33, respectively. This makes it possible to reduce the distance d1 in the X direction between the access transistor PG1 (PG3) and the drive transistor PD1, the distance d1 in the X direction between the load transistors PU1 and PU2, and the distance d1 in the X direction between the drive transistor PD2 and the access transistor PG4 (PG2). This allows the area of ​​the semiconductor memory device to be reduced.

[0052] (Another Configuration Example) Fig. 5(a) shows another configuration example of the semiconductor integrated circuit device according to the first embodiment. The semiconductor integrated circuit device 100 shown in Fig. 5(a) is configured by stacking a first semiconductor chip 101 (chip A) and a second semiconductor chip 102 (chip B). Chip A has the above-mentioned SRAM cells and the like arranged therein. Chip B has power supply wiring formed in a wiring layer provided on its surface. Chip B is attached to the back side of chip A using bumps and the like.

[0053] 5B shows a cross section of the SRAM cell of FIG. 1 taken along line X1-X1' in this configuration example. As shown in FIG. 5B, a power supply wiring 11 that supplies VDD and power supply wirings 12 and 13 that supply VSS are formed in a wiring layer provided on the surface of chip B. Power supply wiring 11 is connected to active region P2 of chip A via via 94. Power supply wiring 13 is connected to active region N3 of chip A via via 92. Although not shown in the figure, power supply wiring 12 is connected to active region N2 of chip A via via 91. Power supply wiring 11 is connected to active region P1 of chip A via via 93.

[0054] 6A and 6B are plan views showing another example of the layout structure of the SRAM cell according to the first embodiment. Specifically, Fig. 6A shows the upper part of the cell, and Fig. 6B shows the lower part of the cell.

[0055] 6, compared to FIG. 1, power supply wirings 69 and 70 extending in the Y direction from the top to the bottom of the cell in the drawing are formed in the M1 wiring layer.

[0056] Specifically, the power supply wiring 69 is formed between the wirings 61 and 62 and supplies the power supply voltage VSS. The power supply wiring 70 is formed between the wirings 63 and 64 and supplies the power supply voltage VSS.

[0057] The power supply wiring 69 is connected to the portion of the active region N2 that will become the source of the drive transistor PD1 through the via 60a and the local wiring 48. The power supply wiring 70 is connected to the portion of the active region N3 that will become the source of the drive transistor PD2 through the via 60b and the local wiring 43.

[0058] 6, power supply wiring 69 that supplies power supply voltage VSS suppresses crosstalk noise between wirings 61 and 62 that correspond to the first bit line BLA and the third bit line BLB, respectively. Also, power supply wiring 70 that supplies power supply voltage VSS suppresses crosstalk noise between wirings 63 and 64 that correspond to the second bit line BLAX and the fourth bit line BLBX, respectively. This makes it possible to stabilize the operation of the semiconductor memory device.

[0059] Furthermore, the power supply voltage VSS supplied to the SRAM cells can be strengthened by the power supply wirings 69 and 70. This makes it possible to improve the operating speed of the semiconductor memory device.

[0060] In addition, the same effects as those in FIG. 1 can be obtained.

[0061] 7A and 7B are plan views showing another example of the layout structure of the SRAM cell according to the first embodiment. Specifically, Fig. 7A shows the upper part of the cell, and Fig. 7B shows the lower part of the cell.

[0062] 7, compared to FIG. 1, power supply wiring 70a extending in the Y direction from the top to the bottom of the cell in the drawing is formed in the M1 wiring layer.

[0063] Specifically, the power supply wiring 70a is formed between the wirings 62 and 63 and supplies the power supply voltage VDD. The power supply wiring 70a is connected to the portion that will become the source of the load transistor PU1 in the active region P1 through the via 60c and the local wiring 49. The power supply wiring 70a is connected to the portion that will become the source of the load transistor PU2 in the active region P2 through the via 60d and the local wiring 42.

[0064] 7, the power supply voltage VDD supplied to the SRAM cells can be strengthened by the power supply wiring 70a that supplies the power supply voltage VDD, thereby improving the stability of the operation of the semiconductor memory device.

[0065] In addition, the same effects as those in FIG. 1 can be obtained.

[0066] In this modification, the power supply wiring 11 in the BM0 wiring layer that supplies the power supply voltage VDD may be omitted.

[0067] 8A and 8B are plan views showing another example of the layout structure of the SRAM cell according to the first embodiment. Specifically, Fig. 8A shows the upper part of the cell, and Fig. 8B shows the lower part of the cell.

[0068] 8, compared to FIG. 1, the wires 62 and 64 in the M1 wiring layer are omitted, and wires 14 and 15 extending in the Y direction across the upper and lower ends of the cell in the drawing are formed in the BM0 wiring layer.

[0069] Specifically, the wiring 14 is formed on the left side of the power supply wiring 12 in the drawing. The wiring 15 is formed on the right side of the power supply wiring 13 in the drawing. The wirings 14 and 15 correspond to the third bit line BLB and the fourth bit line BLBX, respectively.

[0070] In a plan view, the wiring 14 overlaps with the active region N1 and the wiring 61. In a plan view, the wiring 15 overlaps with the active region N4 and the wiring 63. The wiring 14 is connected to a portion of the active region N1 that will become the source of the access transistor PG3 through a via 95 provided at a position where the wiring 14 and the wiring 63 overlap in a plan view. The wiring 15 is connected to a portion of the active region N4 that will become the source of the access transistor PG4 through a via 96 provided at a position where the wiring 14 and the wiring 63 overlap in a plan view.

[0071] 8, wirings 14 and 15 corresponding to the third bit line BLB and the fourth bit line BLBX, respectively, are formed in the BM0 wiring layer. Wirings 61 and 63 corresponding to the first bit line BLA and the second bit line BLAX, respectively, are formed in the M1 wiring layer. As a result, the wirings corresponding to the third bit line BLB and the fourth bit line BLBX and the wirings corresponding to the first bit line BLA and the second bit line BLAX are formed in different wiring layers, thereby suppressing crosstalk noise between the third bit line BLB and the fourth bit line BLBX and the first bit line BLA and the second bit line BLAX. This allows for stable operation of the semiconductor memory device.

[0072] In addition, the same effects as those in FIG. 1 can be obtained.

[0073] Note that power supply wiring for supplying at least one of the power supply voltages VDD and VSS may be formed in the M1 wiring layer. In this case, among the power supply wirings 11 to 13 formed in the BM0 wiring layer, the power supply wiring corresponding to the power supply wiring formed in the M1 wiring layer may be omitted.

[0074] 9A and 9B are plan views showing another example of the layout structure of the SRAM cell according to the first embodiment. Specifically, Fig. 9A shows the upper part of the cell, and Fig. 9B shows the lower part of the cell.

[0075] In FIG. 9, compared to FIG. 1, the surfaces of the nanosheets 21 to 28 opposite to the X direction are exposed from the gate wiring.

[0076] As shown in FIG. 9B , the gate wiring 31 overlaps the nanosheet 21 in a planar view. The gate wiring 32 overlaps the nanosheet 28 in a planar view. The gate wiring 33 overlaps the nanosheet 24 in a planar view. The gate wiring 34 overlaps the nanosheet 25 in a planar view. The gate wiring 35 overlaps the nanosheet 22 in a planar view. The gate wiring 36 overlaps the nanosheet 23 in a planar view. The gate wiring 37 overlaps the nanosheet 27 in a planar view. The gate wiring 38 overlaps the nanosheet 26 in a planar view. The gate wiring 31 corresponds to the gate of the access transistor PG3. The gate wiring 32 corresponds to the gate of the load transistor PU2. The gate wiring 33 corresponds to the gate of the drive transistor PD2. The gate wiring 34 corresponds to the gate of the access transistor PG4. The gate wiring 35 corresponds to the gate of the access transistor PG1. The gate wiring 36 corresponds to the gate of the drive transistor PD1. The gate wiring 37 corresponds to the gate of the load transistor PU1, and the gate wiring 38 corresponds to the gate of the access transistor PG2.

[0077] Nanosheets 21 to 28 are each covered by the gate wiring so that a portion of their outer peripheries is exposed. Specifically, nanosheets 23, 25, 26, and 28 have their right-hand surfaces in the X direction exposed from gate wirings 36, 34, 38, and 32, respectively, and their left-hand surfaces in the X direction covered by gate wirings 36, 34, 38, and 32, respectively. Nanosheets 21, 22, 24, and 27 have their left-hand surfaces in the X direction exposed from gate wirings 31, 35, 33, and 37, respectively, and their right-hand surfaces in the X direction covered by gate wirings 31, 35, 33, and 37, respectively. That is, nanosheets 23 and 27 have their opposing surfaces exposed from gate wirings 36 and 37, respectively, in the X direction. Nanosheets 24 and 28 have their opposing surfaces exposed from gate wirings 33 and 32, respectively, in the X direction.

[0078] Nanosheets 21 and 22 are arranged close to the cell boundary on the left side of the drawing. Nanosheets 25 and 26 are arranged close to the cell boundary on the right side of the drawing. In the SRAM cell of FIG. 9 , SRAM cells inverted in the X direction are arranged on both the left and right sides of the drawing. That is, in the SRAM cells arranged in the X direction, the surfaces of nanosheets 21 facing each other in the X direction are exposed from gate wiring 31. Similarly, the surfaces of nanosheets 22 facing each other in the X direction are exposed from gate wiring 35. The surfaces of nanosheets 25 facing each other in the X direction are exposed from gate wiring 34. The surfaces of nanosheets 26 facing each other in the X direction are exposed from gate wiring 38.

[0079] Gate wirings 32 and 33 are connected via bridge portion 40c extending in the X direction. Gate wirings 36 and 37 are connected via bridge portion 40d extending in the X direction. Gate wirings 31 and 35 are connected to gate wirings 31 and 35 located on the left side of the SRAM cell in the drawing via bridge portions 40e and 40f extending in the X direction, respectively. Gate wirings 34 and 38 are connected to gate wirings 34 and 38 located on the right side of the SRAM cell in the drawing via bridge portions 40g and 40h extending in the X direction, respectively.

[0080] Wiring 71 corresponding to first word line WLA is connected to gate wiring 35 via via 81, wiring 65, via 57, and bridge portion 40f. Wiring 71 is connected to gate wiring 38 via via 82, wiring 66, via 58, and bridge portion 40h. Wiring 72 corresponding to second word line WLB is connected to gate wiring 31 via via 83, wiring 67, via 59, and bridge portion 40e. Wiring 72 is connected to gate wiring 34 via via 84, wiring 68, via 60, and bridge portion 40g.

[0081] 9 , the surfaces of the nanosheets 23 and 27 that face each other in the X direction are exposed from the gate wirings 36 and 37, respectively. The surfaces of the nanosheets 24 and 28 that face each other in the X direction are exposed from the gate wirings 33 and 32, respectively. This makes it possible to reduce the distance d1 in the X direction between the drive transistor PD1 and the load transistor PU1, and the distance d1 in the X direction between the load transistor PU2 and the drive transistor PD2.

[0082] Furthermore, in the SRAM cells aligned in the X direction, the surfaces of the nanosheets 21 facing each other in the X direction are exposed from the gate wiring 31. The surfaces of the nanosheets 22 facing each other in the X direction are exposed from the gate wiring 35. The surfaces of the nanosheets 25 facing each other in the X direction are exposed from the gate wiring 34. The surfaces of the nanosheets 26 facing each other in the X direction are exposed from the gate wiring 38. This allows the distance d1 in the X direction between the access transistors PG3, the distance d1 in the X direction between the access transistors PG1, the distance d1 in the X direction between the access transistors PG4, and the distance d1 in the X direction between the access transistors PG2 to be reduced in the SRAM cells aligned in the X direction. This allows the area of ​​the semiconductor memory device to be reduced.

[0083] In addition, the same effects as those in FIG. 1 can be obtained.

[0084] 10A and 10B are plan views showing another example of the layout structure of the SRAM cell according to the first embodiment. Specifically, Fig. 10A shows the upper part of the cell, and Fig. 10B shows the lower part of the cell.

[0085] 10, compared to FIG. 9, power supply wirings 69 and 70 extending in the Y direction from the top to the bottom of the cell in the drawing are formed in the M1 wiring layer.

[0086] Specifically, the power supply wiring 69 is formed between the wirings 61 and 62 and supplies the power supply voltage VSS. The power supply wiring 70 is formed between the wirings 63 and 64 and supplies the power supply voltage VSS.

[0087] The power supply wiring 69 is connected to the portion of the active region N2 that will become the source of the drive transistor PD1 through the via 60a and the local wiring 48. The power supply wiring 70 is connected to the portion of the active region N3 that will become the source of the drive transistor PD2 through the via 60b and the local wiring 43.

[0088] 10, power supply wiring 69 that supplies power supply voltage VSS suppresses crosstalk noise between wirings 61 and 62 that correspond to the first bit line BLA and the third bit line BLB, respectively. Also, power supply wiring 70 that supplies power supply voltage VSS suppresses crosstalk noise between wirings 63 and 64 that correspond to the second bit line BLAX and the fourth bit line BLBX, respectively. This makes it possible to stabilize the operation of the semiconductor memory device.

[0089] Furthermore, the power supply voltage VSS supplied to the SRAM cells can be strengthened by the power supply wirings 69 and 70. This makes it possible to improve the operating speed of the semiconductor memory device.

[0090] In addition, the same effects as those in FIG. 9 can be obtained.

[0091] 11A and 11B are plan views showing another example of the layout structure of the SRAM cell according to the first embodiment. Specifically, Fig. 11A shows the upper part of the cell, and Fig. 11B shows the lower part of the cell.

[0092] 11, compared to FIG. 9, power supply wiring 70a extending in the Y direction from the top to the bottom of the cell in the drawing is formed in the M1 wiring layer.

[0093] Specifically, the power supply wiring 70a is formed between the wirings 62 and 63 and supplies the power supply voltage VDD. The power supply wiring 70a is connected to the portion that will become the source of the load transistor PU1 in the active region P1 through the via 60c and the local wiring 49. The power supply wiring 70a is connected to the portion that will become the source of the load transistor PU2 in the active region P2 through the via 60d and the local wiring 42.

[0094] 11, the power supply voltage VDD supplied to the SRAM cells can be strengthened by the power supply wiring 70a that supplies the power supply voltage VDD, thereby improving the stability of the operation of the semiconductor memory device.

[0095] In addition, the same effects as those in FIG. 9 can be obtained.

[0096] In this modification, the power supply wiring 11 in the BM0 wiring layer that supplies the power supply voltage VDD may be omitted.

[0097] 12A and 12B are plan views showing another example of the layout structure of the SRAM cell according to the first embodiment. Specifically, Fig. 12A shows the upper part of the cell, and Fig. 12B shows the lower part of the cell.

[0098] 12, compared to FIG. 9, the wires 62 and 64 in the M1 wiring layer are omitted, and wires 14 and 15 extending in the Y direction across the upper and lower ends of the cell in the drawing are formed in the BM0 wiring layer.

[0099] Specifically, the wiring 14 is formed on the left side of the power supply wiring 12 in the drawing. The wiring 15 is formed on the right side of the power supply wiring 13 in the drawing. The wirings 14 and 15 correspond to the third bit line BLB and the fourth bit line BLBX, respectively.

[0100] In a plan view, the wiring 14 overlaps with the active region N1 and the wiring 61. In a plan view, the wiring 15 overlaps with the active region N4 and the wiring 63. The wiring 14 is connected to a portion of the active region N1 that will become the source of the access transistor PG3 through a via 95 provided at a position where the wiring 14 and the wiring 63 overlap in a plan view. The wiring 15 is connected to a portion of the active region N4 that will become the source of the access transistor PG4 through a via 96 provided at a position where the wiring 14 and the wiring 63 overlap in a plan view.

[0101] 12 , wirings 14 and 15 corresponding to the third bit line BLB and the fourth bit line BLBX, respectively, are formed in the BM0 wiring layer. Wirings 61 and 63 corresponding to the first bit line BLA and the second bit line BLAX, respectively, are formed in the M1 wiring layer. As a result, the wirings corresponding to the third bit line BLB and the fourth bit line BLBX and the wirings corresponding to the first bit line BLA and the second bit line BLAX are formed in different wiring layers, thereby suppressing crosstalk noise between the third bit line BLB and the fourth bit line BLBX and the first bit line BLA and the second bit line BLAX. This allows for stable operation of the semiconductor memory device.

[0102] In addition, the same effects as those in FIG. 9 can be obtained.

[0103] Note that power supply wiring for supplying at least one of the power supply voltages VDD and VSS may be formed in the M1 wiring layer. In this case, among the power supply wirings 11 to 13 formed in the BM0 wiring layer, the power supply wiring corresponding to the power supply wiring formed in the M1 wiring layer may be omitted.

[0104] 13A and 13B are plan views showing an example of a layout structure of an SRAM cell according to a second embodiment. Specifically, Fig. 13A shows the upper part of the cell, and Fig. 13B shows the lower part of the cell.

[0105] 13, the drive transistors PD1 and PD2 are each composed of two nanosheet FETs. Specifically, the drive transistor PD1 is composed of transistors PD11 and PD12. The drive transistor PD2 is composed of transistors PD21 and PD22.

[0106] As shown in FIG. 13B, power supply wiring 111-113 are formed in the BM0 wiring layer, extending in the Y direction from the top to the bottom of the cell in the drawing. Power supply wiring 111 is formed in the center of the cell in the X direction and supplies a power supply voltage VDD. Power supply wiring 112 is formed at the left end of the cell in the X direction and supplies a power supply voltage VSS. Power supply wiring 113 is formed at the right end of the cell in the X direction and supplies a power supply voltage VSS. Power supply wiring 112 is shared with other cells arranged on the left side of the drawing. Power supply wiring 113 is shared with other cells arranged on the right side of the drawing.

[0107] Active regions N5 to N8 are formed in the N-type transistor region. The active regions N5 and N6 overlap with the power supply wiring 112 in plan view. The active regions N7 and N8 overlap with the power supply wiring 113 in plan view.

[0108] In the N-type transistor region, access transistors PG1 to PG4 and transistors PD11, PD12, PD21, and PD22 are formed. Access transistor PG3, transistor PD11, access transistor PG1, transistor PD12, transistor PD21, access transistor PG4, transistor PD22, and access transistor PG2 each have nanosheets 121 to 128 extending in the Y direction.

[0109] In active region N5, the portion that becomes the source of transistor PD11 is connected to power supply wiring 112 via via 191 that is provided at a position that overlaps with power supply wiring 112 in a planar view. In active region N6, the portion that becomes the source of transistor PD12 is connected to power supply wiring 112 via via 192 that is provided at a position that overlaps with power supply wiring 112 in a planar view. In active region N7, the portion that becomes the source of transistor PD21 is connected to power supply wiring 113 via via 193 that is provided at a position that overlaps with power supply wiring 113 in a planar view. In active region N8, the portion that becomes the source of transistor PD22 is connected to power supply wiring 113 via via 194 that is provided at a position that overlaps with power supply wiring 113 in a planar view.

[0110] Active regions P3 and P4 are formed in the P-type transistor region. The active regions P3 and P4 overlap with the power supply wiring 111 in plan view.

[0111] In the P-type transistor region, load transistors PU1 and PU2 are formed. The load transistors PU1 and PU2 have nanosheets 129 and 130, respectively, that extend in the Y direction.

[0112] The width of the nanosheets 121 to 128 in the X direction is twice the width of the nanosheets 129 and 130 in the X direction.

[0113] In the active region P3, the portion that becomes the source of the load transistor PU1 is connected to the power supply wiring 111 through a via 195 that is provided at a position that overlaps the power supply wiring 111 in a plan view. In the active region P4, the portion that becomes the source of the load transistor PU2 is connected to the power supply wiring 111 through a via 196 that is provided at a position that overlaps the power supply wiring 111 in a plan view.

[0114] Gate wiring 131 to 140 are formed extending in the X direction. Gate wiring 131 overlaps with nanosheet 121 in a planar view. Gate wiring 132 overlaps with nanosheet 123 in a planar view. Gate wiring 134 overlaps with nanosheets 130 and 125 in a planar view. Gate wiring 135 overlaps with nanosheet 127 in a planar view. Gate wiring 136 overlaps with nanosheet 122 in a planar view. Gate wiring 137 overlaps with nanosheets 124 and 129 in a planar view. Gate wiring 139 overlaps with nanosheet 126 in a planar view. Gate wiring 140 overlaps with nanosheet 128 in a planar view. Gate wiring 131 corresponds to the gate of access transistor PG3. Gate wiring 132 corresponds to the gate of access transistor PG1. Gate wiring 134 corresponds to the gates of load transistor PU2 and transistor PD21. Gate wiring 135 corresponds to the gate of transistor PD22. Gate wiring 136 corresponds to the gate of transistor PD11. Gate wiring 137 corresponds to the gates of transistor PD12 and load transistor PU1. Gate wiring 139 corresponds to the gate of access transistor PG4. Gate wiring 140 corresponds to the gate of access transistor PG2.

[0115] Nanosheets 121 to 130 are each covered by the gate wiring so that a portion of their outer peripheries is exposed. Specifically, nanosheets 121, 122, 125, 126, and 129 have their right-hand surfaces in the X direction exposed from gate wirings 131, 136, 134, 139, and 137, respectively, and their left-hand surfaces in the X direction covered by gate wirings 131, 136, 134, 139, and 137, respectively. Nanosheets 123, 124, 127, 128, and 130 have their left-hand surfaces in the X direction exposed from gate wirings 132, 137, 135, 140, and 134, respectively, and their right-hand surfaces in the X direction covered by gate wirings 132, 137, 135, 140, and 134, respectively. That is, the surfaces of the nanosheets 121 and 123 that face each other in the X direction are exposed from the gate wirings 131 and 132, respectively. The surfaces of the nanosheets 122 and 124 that face each other in the X direction are exposed from the gate wirings 136 and 137, respectively. The surfaces of the nanosheets 125 and 127 that face each other in the X direction are exposed from the gate wirings 134 and 135, respectively. The surfaces of the nanosheets 126 and 128 that face each other in the X direction are exposed from the gate wirings 139 and 140, respectively. The surfaces of the nanosheets 129 and 130 that face each other in the X direction are exposed from the gate wirings 137 and 134, respectively.

[0116] The gate wirings 133 and 134 are connected via a bridge portion 140a extending in the X direction. The gate wirings 134 and 135 are connected via a bridge portion 140b extending in the X direction. The gate wirings 136 and 137 are connected via a bridge portion 140c extending in the X direction. The gate wirings 137 and 138 are connected via a bridge portion 140d extending in the X direction.

[0117] Local interconnects 141 to 150 extending in the X direction are formed in the local interconnect layer. Local interconnect 141 is connected to a portion that will become the source of access transistor PG3 in active region N5. Local interconnect 142 is connected to a portion that will become the source of access transistor PG1 in active region N6. Local interconnect 143 is connected to a portion that will become the source of load transistor PU2 in active region P4. Local interconnect 144 is connected to a portion that will become the source of transistor PD21 in active region N7 and a portion that will become the source of transistor PD22 in active region N8. Local interconnect 145 is connected to a portion that will become the drain of access transistor PG3 in active region N5, a portion that will become the drain of transistor PD11 in active region N5, a portion that will become the drain of access transistor PG1 in active region N6, a portion that will become the drain of transistor PD12 in active region N6, and a portion that will become the drain of load transistor PU1 in active region P3. Local interconnect 146 is connected to the drain of load transistor PU2 in active region P4, the drain of transistor PD21 in active region N7, the drain of access transistor PG4 in active region N7, the drain of transistor PD22 in active region N8, and the drain of access transistor PG2 in active region N8. Local interconnect 147 is connected to the source of transistor PD11 in active region N5 and the source of transistor PD12 in active region N6. Local interconnect 148 is connected to the source of load transistor PU1 in active region P3. Local interconnect 149 is connected to the source of access transistor PG4 in active region N7. Local interconnect 150 is connected to the source of access transistor PG2 in active region N8.

[0118] Local wiring 145 is connected to gate wiring 133 via shared contact 151. Local wiring 146 is connected to gate wiring 138 via shared contact 152. Gate wirings 133 to 135, bridge portions 140a and 140b, local wiring 145, and shared contact 151 correspond to a first node NA. Gate wirings 136 to 138, bridge portions 140c and 140d, local wiring 146, and shared contact 152 correspond to a second node NB.

[0119] As shown in FIG. 13A, wirings 161 to 164 are formed in the M1 wiring layer, extending in the Y direction from the top to the bottom of the cell in the drawing. Wirings 165 to 168 are also formed. Wirings 161 to 164 correspond to the first bit line BLA, the third bit line BLB, the second bit line BLAX, and the fourth bit line BLBX, respectively. Wiring 161 overlaps with active region N6 and power supply wiring 112 in a planar view. Wiring 162 overlaps with active region N5 and power supply wiring 112 in a planar view. Wiring 163 overlaps with active region N8 and power supply wiring 113 in a planar view. Wiring 164 overlaps with active region N7 and power supply wiring 113 in a planar view.

[0120] The wiring 161 is connected to the local wiring 142 through a via 153. The wiring 162 is connected to the local wiring 141 through a via 154. The wiring 163 is connected to the local wiring 150 through a via 155. The wiring 164 is connected to the local wiring 149 through a via 156.

[0121] Wirings 171 and 172 are formed in the M2 wiring layer, extending in the X direction from the left to the right ends of the cell in the drawing. Wirings 171 and 172 correspond to the first word line WLA and the second word line WLB, respectively. Wiring 171 is connected to gate wiring 132 via via 181, wiring 165, and via 157. Wiring 171 is connected to gate wiring 140 via via 182, wiring 166, and via 158. Wiring 172 is connected to gate wiring 131 via via 183, wiring 167, and via 159. Wiring 172 is connected to gate wiring 139 via via 184, wiring 168, and via 160.

[0122] With the above configuration, a power supply wiring 111 that supplies a power supply voltage VDD and power supply wirings 112 and 113 that supply a power supply voltage VSS are formed in the BM0 wiring layer, which is a wiring layer on the back surface of the transistor. Wirings 161, 163, 162, and 164 corresponding to the first bit line BLA, the second bit line BLAX, the third bit line BLB, and the fourth bit line BLBX, respectively, are formed in the M1 wiring layer, which is a metal wiring layer above the transistor. As a result, the wiring formed in the M1 wiring layer is limited to bit lines, so the wiring width of the wirings 161 to 164 can be increased. Therefore, the wiring resistance of the bit lines can be reduced, thereby improving the operating speed of the semiconductor memory device. Furthermore, since the wiring formed in the BM0 wiring layer is limited to power supply wirings that supply power supply voltages VDD and VSS, the wiring width of the power supply wirings 111 to 113 can be increased. Therefore, the wiring resistance of the power supply wiring can be reduced, and a power supply voltage drop can be suppressed, thereby improving the operating speed and stability of the semiconductor memory device. Furthermore, because the bit lines and the power supply lines are formed in different wiring layers, the distance between the bit lines and the power supply lines can be increased. Therefore, the parasitic capacitance between the bit lines and the power supply lines can be reduced, thereby improving the operating speed of the semiconductor memory device. Furthermore, by increasing the wiring width of the power supply lines 111 to 113, the wiring resistance of the lines supplying the power supply voltages VDD and VSS can be reduced, improving the stability of operation, particularly the retention characteristics (static noise margin) of the SRAM cells.

[0123] Furthermore, power supply wiring 112, 113 formed in the BM0 wiring layer and supplying the power supply voltage VSS are arranged at the left and right ends of the cell in the X direction in the drawing, respectively, and are shared with the cells arranged on the left and right sides of the drawing, respectively. This allows the power supply wiring supplying the power supply voltage VSS to be strengthened, thereby improving the operating speed of the semiconductor memory device. Note that in Figure 13, the power supply wiring 112, 113 do not necessarily have to be arranged at the left and right ends of the drawing in the X direction.

[0124] Furthermore, the surfaces of the nanosheets 121 and 123 that face each other in the X direction are exposed from the gate wirings 131 and 132, respectively. The surfaces of the nanosheets 122 and 124 that face each other in the X direction are exposed from the gate wirings 136 and 137, respectively. The surfaces of the nanosheets 125 and 127 that face each other in the X direction are exposed from the gate wirings 134 and 135, respectively. The surfaces of the nanosheets 126 and 128 that face each other in the X direction are exposed from the gate wirings 139 and 140, respectively. The surfaces of the nanosheets 129 and 130 that face each other in the X direction are exposed from the gate wirings 137 and 134, respectively. This reduces the distance d1 in the X direction between the access transistors PG1 and PG3, the distance d1 in the X direction between the transistors PD11 and PD12, the distance d1 in the X direction between the transistors PD21 and PD22, the distance d1 in the X direction between the access transistors PG2 and PG4, and the distance d1 in the X direction between the load transistors PU1 and PU2, thereby reducing the area of ​​the semiconductor memory device.

[0125] 14A and 14B are plan views showing another example of the layout structure of the SRAM cell according to the second embodiment. Specifically, Fig. 14A shows the upper part of the cell, and Fig. 14B shows the lower part of the cell.

[0126] 14, compared to FIG. 13, power supply wirings 170a and 170b extending in the Y direction from the top to the bottom of the cell in the drawing are formed in the M1 wiring layer instead of wirings 161 and 163. Also, wirings 114 and 115 extending in the Y direction from the top to the bottom of the cell in the drawing are formed in the BM0 wiring layer.

[0127] 14B, the wiring 114 is formed between the power supply wirings 111 and 112. The wiring 115 is formed on the right side of the power supply wiring 113 in the drawing. The wirings 114 and 115 correspond to the first bit line BLA and the second bit line BLAX, respectively.

[0128] The wiring 114 overlaps with the active region N6 in a planar view. The wiring 115 overlaps with the active region N8 in a planar view. The wiring 114 is connected to a portion of the active region N6 that will become the source of the access transistor PG1 through a via 197 provided at a position where the wiring 114 overlaps with the active region N8 in a planar view. The wiring 115 is connected to a portion of the active region N8 that will become the source of the access transistor PG2 through a via 198 provided at a position where the wiring 114 overlaps with the active region N8 in a planar view.

[0129] 14A, power supply wiring 170a is formed between wiring 162 and wiring 164. Power supply wiring 170b is formed to the right of wiring 164 in the X direction in the drawing. Power supply wirings 170a and 170b supply power supply voltage VSS. Power supply wiring 170a overlaps with active region N6 and wiring 114 in a plan view. Power supply wiring 170b overlaps with active region N8 and wiring 115 in a plan view.

[0130] Power supply wiring 170a is connected to the portion that will become the source of transistor PD11 in active region N5 and the portion that will become the source of transistor PD12 in active region N6 via via 160a and local wiring 147. Power supply wiring 170b is connected to the portion that will become the source of transistor PD21 in active region N7 and the portion that will become the source of transistor PD22 in active region N8 via via 160b and local wiring 144.

[0131] 14 , wirings 114 and 115 corresponding to the first bit line BLA and the second bit line BLAX, respectively, are formed in the BM0 wiring layer. Wirings 162 and 164 corresponding to the third bit line BLB and the fourth bit line BLBX, respectively, are formed in the M1 wiring layer. As a result, the wirings corresponding to the third bit line BLB and the fourth bit line BLBX and the wirings corresponding to the first bit line BLA and the second bit line BLAX are formed in different wiring layers, thereby suppressing crosstalk noise between the third bit line BLB and the fourth bit line BLBX and the first bit line BLA and the second bit line BLAX. This allows for stable operation of the semiconductor memory device.

[0132] In addition, the same effects as those in FIG. 13 can be obtained.

[0133] 15A and 15B are plan views showing another example of the layout structure of the SRAM cell according to the second embodiment. Specifically, Fig. 15A shows the upper part of the cell, and Fig. 15B shows the lower part of the cell.

[0134] 15, compared to FIG. 14, in the M1 wiring layer, power supply wirings 170c and 170d extending in the Y direction from the top to the bottom of the cell in the drawing are formed instead of the wirings 162 and 164. Also, in the BM0 wiring layer, wirings 116 and 117 extending in the Y direction from the top to the bottom of the cell in the drawing are formed instead of the power supply wirings 112 and 113.

[0135] 15B, the wiring 116 is formed on the left side of the wiring 114 in the drawing. The wiring 117 is formed between the power supply wiring 111 and the wiring 115. The wirings 116 and 117 correspond to the third bit line BLB and the fourth bit line BLBX, respectively.

[0136] The wiring 116 overlaps with the active region N5 in a planar view. The wiring 117 overlaps with the active region N7 in a planar view. The wiring 116 is connected to a portion of the active region N5 that will become the source of the access transistor PG3 through a via 199 provided at a position where the wiring 116 and the active region N7 overlap in a planar view. The wiring 117 is connected to a portion of the active region N7 that will become the source of the access transistor PG4 through a via 200 provided at a position where the wiring 116 and the active region N7 overlap in a planar view.

[0137] 15A, power supply wiring 170c is formed on the left side of power supply wiring 170a in the X direction. Power supply wiring 170d is formed between power supply wiring 170a and 170b. Power supply wiring 170c and 170d supply power supply voltage VSS. Power supply wiring 170c overlaps with active region N5 and wiring 116 in a plan view. Power supply wiring 170d overlaps with active region N7 and wiring 117 in a plan view.

[0138] Power supply wiring 170c is connected to the portion that will become the source of transistor PD11 in active region N5 and the portion that will become the source of transistor PD12 in active region N6 via via 160c and local wiring 147. Power supply wiring 170d is connected to the portion that will become the source of transistor PD21 in active region N7 and the portion that will become the source of transistor PD22 in active region N8 via via 160d and local wiring 144.

[0139] In Figure 15, wirings 114, 115, 116, and 117 corresponding to the first bit line BLA, the second bit line BLAX, the third bit line BLB, and the fourth bit line BLBX, respectively, and a power supply wiring 111 that supplies a power supply voltage VDD are formed in the BM0 wiring layer, and power supply wirings 170a to 170d that supply a power supply voltage VSS are formed in the M1 wiring layer, so that the same effect as in Figure 13 can be obtained.

[0140] 16A and 16B are plan views showing another example of the layout structure of the SRAM cell according to the second embodiment. Specifically, Fig. 16A shows the upper part of the cell, and Fig. 16B shows the lower part of the cell.

[0141] In FIG. 16, compared to FIG. 13, the surfaces of the nanosheets 121 to 128 opposite to the X direction are exposed from the gate wiring.

[0142] As shown in FIG. 16( b), the gate wiring 131 overlaps the nanosheet 121 in a planar view. The gate wiring 132 overlaps the nanosheet 123 in a planar view. The gate wiring 133 overlaps the nanosheet 130 in a planar view. The gate wiring 134 overlaps the nanosheets 125 and 127 in a planar view. The gate wiring 135 overlaps the nanosheets 122 and 124 in a planar view. The gate wiring 136 overlaps the nanosheet 129 in a planar view. The gate wiring 137 overlaps the nanosheet 126 in a planar view. The gate wiring 138 overlaps the nanosheet 128 in a planar view. The gate wiring 131 corresponds to the gate of the access transistor PG3. The gate wiring 132 corresponds to the gate of the access transistor PG1. The gate wiring 133 corresponds to the gate of the load transistor PU2. The gate wiring 134 corresponds to the gates of the transistors PD21 and PD22. The gate wiring 135 corresponds to the gates of the transistors PD11 and PD12. The gate wiring 136 corresponds to the gate of the load transistor PU1. The gate wiring 137 corresponds to the gate of the access transistor PG4. The gate wiring 138 corresponds to the gate of the access transistor PG2.

[0143] Nanosheets 121 to 130 are each covered by the gate wiring so that a portion of their outer peripheries is exposed. Specifically, nanosheets 123, 124, 127, 128, and 130 have their right-hand surfaces in the X direction exposed from gate wirings 132, 135, 134, 138, and 133, respectively, and their left-hand surfaces in the X direction covered by gate wirings 132, 135, 134, 138, and 133, respectively. Nanosheets 121, 122, 125, 126, and 129 have their left-hand surfaces in the X direction exposed from gate wirings 131, 135, 134, 137, and 136, respectively, and their right-hand surfaces in the X direction covered by gate wirings 131, 135, 134, 137, and 136, respectively. That is, the surfaces of the nanosheets 124 (123) and 129 that face each other in the X direction are exposed from the gate wirings 135 (132) and 136, respectively. The surfaces of the nanosheets 125 (126) and 130 that face each other in the X direction are exposed from the gate wirings 134 (137) and 133, respectively.

[0144] Nanosheets 121 and 122 are arranged close to the cell boundary on the left side of the drawing. Nanosheets 127 and 128 are arranged close to the cell boundary on the right side of the drawing. In the SRAM cell of FIG. 16 , SRAM cells inverted in the X direction are arranged on both the left and right sides of the drawing. That is, in the SRAM cells arranged in the X direction, the surfaces of nanosheets 121 facing each other in the X direction are exposed from gate wiring 131. Similarly, the surfaces of nanosheets 122 facing each other in the X direction are exposed from gate wiring 135. The surfaces of nanosheets 127 facing each other in the X direction are exposed from gate wiring 134. The surfaces of nanosheets 128 facing each other in the X direction are exposed from gate wiring 138.

[0145] Gate wirings 133 and 134 are connected via a bridge portion 140e extending in the X direction. Gate wirings 135 and 136 are connected via a bridge portion 140f extending in the X direction. Gate wiring 131 is connected to gate wiring 131 arranged on the left side of the SRAM cell in the drawing via a bridge portion 140g extending in the X direction. Gate wiring 138 is connected to gate wiring 138 arranged on the right side of the SRAM cell in the drawing via a bridge portion 140h extending in the X direction.

[0146] Wiring 171 corresponding to first word line WLA is connected to gate wiring 132 via via 181, wiring 165, and via 157. Wiring 171 is connected to gate wiring 138 via via 182, wiring 166, via 158, and bridge portion 140h. Wiring 172 corresponding to second word line WLB is connected to gate wiring 131 via via 183, wiring 167, via 159, and bridge portion 140g. Wiring 172 is connected to gate wiring 137 via via 184, wiring 168, and via 160.

[0147] In the configuration of FIG. 16 , the surfaces of the nanosheets 124 (123) and 129 that face each other in the X direction are exposed from the gate wirings 135 (132) and 136, respectively. The surfaces of the nanosheets 125 (126) and 130 that face each other in the X direction are exposed from the gate wirings 134 (137) and 133, respectively. This reduces the distance d1 in the X direction between the access transistor PG1 (transistor PD12) and the load transistor PU1, and the distance d1 in the X direction between the load transistor PU2 and the transistor PD21 (access transistor PG4). This allows the area of ​​the semiconductor memory device to be reduced.

[0148] Furthermore, in the SRAM cells aligned in the X direction, the surfaces of the nanosheets 121 facing each other in the X direction are exposed from the gate wiring 131. The surfaces of the nanosheets 122 facing each other in the X direction are exposed from the gate wiring 135. The surfaces of the nanosheets 127 facing each other in the X direction are exposed from the gate wiring 134. The surfaces of the nanosheets 128 facing each other in the X direction are exposed from the gate wiring 138. This allows the distance d1 in the X direction between the access transistors PG3, the distance d1 in the X direction between the transistors PD11, the distance d1 in the X direction between the transistors PD22, and the distance d1 in the X direction between the access transistors PG2 to be reduced in the SRAM cells aligned in the X direction. This allows the area of ​​the semiconductor memory device to be reduced.

[0149] In addition, the same effects as those in FIG. 13 can be obtained.

[0150] 17A and 17B are plan views showing another example of the layout structure of the SRAM cell according to the second embodiment. Specifically, Fig. 17A shows the upper part of the cell, and Fig. 17B shows the lower part of the cell.

[0151] 17, compared to FIG. 16, power supply wirings 170a and 170b extending in the Y direction from the top to the bottom of the cell in the drawing are formed in the M1 wiring layer instead of wirings 161 and 163. Also, wirings 114 and 115 extending in the Y direction from the top to the bottom of the cell in the drawing are formed in the BM0 wiring layer.

[0152] 17B, ​​the wiring 114 is formed between the power supply wirings 111 and 112. The wiring 115 is formed on the right side of the power supply wiring 113 in the drawing. The wirings 114 and 115 correspond to the first bit line BLA and the second bit line BLAX, respectively.

[0153] The wiring 114 overlaps with the active region N6 in a planar view. The wiring 115 overlaps with the active region N8 in a planar view. The wiring 114 is connected to a portion of the active region N6 that will become the source of the access transistor PG1 through a via 197 provided at a position where the wiring 114 overlaps with the active region N8 in a planar view. The wiring 115 is connected to a portion of the active region N8 that will become the source of the access transistor PG2 through a via 198 provided at a position where the wiring 114 overlaps with the active region N8 in a planar view.

[0154] 17A, power supply wiring 170a is formed between wiring 162 and wiring 164. Power supply wiring 170b is formed to the right of wiring 164 in the X direction in the drawing. Power supply wirings 170a and 170b supply power supply voltage VSS. Power supply wiring 170a overlaps with active region N6 and wiring 114 in a plan view. Power supply wiring 170b overlaps with active region N8 and wiring 115 in a plan view.

[0155] The power supply wiring 170b is connected via a via 160b and a local wiring 144 to a portion that serves as the source of the transistor PD21 in the active region N7 and a portion that serves as the source of the transistor PD22 in the active region N8.

[0156] 17 , wirings 114 and 115 corresponding to the first bit line BLA and the second bit line BLAX, respectively, are formed in the BM0 wiring layer. Wirings 162 and 164 corresponding to the third bit line BLB and the fourth bit line BLBX, respectively, are formed in the M1 wiring layer. As a result, the wirings corresponding to the third bit line BLB and the fourth bit line BLBX and the wirings corresponding to the first bit line BLA and the second bit line BLAX are formed in different wiring layers, thereby suppressing crosstalk noise between the third bit line BLB and the fourth bit line BLBX and the first bit line BLA and the second bit line BLAX. This allows for stable operation of the semiconductor memory device.

[0157] In addition, the same effects as those in FIG. 16 can be obtained.

[0158] 18A and 18B are plan views showing another example of the layout structure of the SRAM cell according to the second embodiment. Specifically, Fig. 18A shows the upper part of the cell, and Fig. 18B shows the lower part of the cell.

[0159] 18, compared to FIG. 17, in the M1 wiring layer, power supply wirings 170c and 170d extending in the Y direction from the top to the bottom of the cell in the drawing are formed instead of the wirings 162 and 164. Also, in the BM0 wiring layer, power supply wirings 116 and 117 extending in the Y direction from the top to the bottom of the cell in the drawing are formed instead of the power supply wirings 112 and 113.

[0160] 18B, the wiring 116 is formed on the left side of the wiring 114 in the drawing. The wiring 117 is formed between the power supply wiring 111 and the wiring 115. The wirings 116 and 117 correspond to the third bit line BLB and the fourth bit line BLBX, respectively.

[0161] The wiring 116 overlaps with the active region N5 in a planar view. The wiring 117 overlaps with the active region N7 in a planar view. The wiring 116 is connected to a portion of the active region N5 that will become the source of the access transistor PG3 through a via 199 provided at a position where the wiring 116 and the active region N7 overlap in a planar view. The wiring 117 is connected to a portion of the active region N7 that will become the source of the access transistor PG4 through a via 200 provided at a position where the wiring 116 and the active region N7 overlap in a planar view.

[0162] 18A, power supply wiring 170c is formed on the left side of power supply wiring 170a in the X direction. Power supply wiring 170d is formed between power supply wiring 170a and 170b. Power supply wiring 170c and 170d supply power supply voltage VSS. Power supply wiring 170c overlaps with active region N5 and wiring 116 in a plan view. Power supply wiring 170d overlaps with active region N7 and wiring 117 in a plan view.

[0163] The power supply wiring 170c is connected via a via 160c and a local wiring 147 to a portion in the active region N5 that serves as the source of the transistor PD11 and a portion in the active region N6 that serves as the source of the transistor PD12.

[0164] In Figure 18, wirings 114, 115, 116, and 117 corresponding to the first bit line BLA, the second bit line BLAX, the third bit line BLB, and the fourth bit line BLBX, respectively, and a power supply wiring 111 that supplies a power supply voltage VDD are formed in the BM0 wiring layer, and power supply wirings 170a to 170d that supply a power supply voltage VSS are formed in the M1 wiring layer, so that the same effect as in Figure 16 can be obtained.

[0165] In the above-described embodiments and variants, each transistor has three nanosheets, but some or all of the transistors may have one, two, or four or more nanosheets.

[0166] In addition, in the above-described embodiments and modifications, the cross-sectional shape of the nanosheet is rectangular, but this is not limited to this and may be, for example, square, circular, elliptical, or the like.

[0167] In the first embodiment and the modified examples described above, the X-direction width of nanosheets 21, 22, 25, and 26 is twice the X-direction width of nanosheets 27 and 28, and the X-direction width of nanosheets 23 and 24 is four times the X-direction width of nanosheets 27 and 28, but this is not limitative. The X-direction width of each of nanosheets 21 to 28 may be determined taking into consideration the operational stability of the SRAM circuit, etc.

[0168] In the second embodiment and the modified example described above, the width in the X direction of the nanosheets 121 to 128 is twice the width in the X direction of the nanosheets 129 and 130, but this is not limited to this. The width in the X direction of each of the nanosheets 121 to 130 may be determined taking into consideration the operational stability of the SRAM circuit, etc.

[0169] In addition, in each of the above-described embodiments and modifications, the shared contacts 51, 52, 151, 152 may be manufactured in the same process as the contacts (gate-contacts) and local wiring, or may be manufactured in a separate process.

[0170] Furthermore, in each of the above-described embodiments and variations, the power supply that supplies the power supply voltage VDD to the sources of the load transistors PU1 and PU2 is not limited to a power supply supplied from outside the semiconductor integrated circuit, but may be a power supply generated inside the semiconductor integrated circuit or a power supply generated inside the semiconductor memory device.

[0171] In the present disclosure, the operating speed of a semiconductor memory device is improved in a layout structure of an SRAM cell in which wiring is provided on the back side of a transistor.

[0172] 11 to 13, 69, 70, 70a, 111 to 113, 169, 170a to 170d Power supply wiring 91 to 96, 191 to 200 Vias 21 to 28, 121 to 130 Nanosheets 31 to 38, 131 to 140 Gate wiring 40a to 40h, 140a to 140h Bridge section 14, 15, 61 to 64, 71, 72, 161 to 164, 114 to 117, 171, 172 Wiring N1 to N8, P1 to P4 Active area PU1, PU2 Load transistor PD1, PD2 Drive transistor PD11, PD12, PD21, PD22 Transistor PG1 to PG4 Access transistor BLA First bit line BLAX Second bit line BLB Third bit line BLBX 4th bit line WLA 1st word line WLB 2nd word line

Claims

1. A semiconductor memory device including an SRAM cell, wherein the SRAM cell comprises: a first transistor having a source connected to a first power supply that supplies a first power supply voltage, a drain connected to a first node, and a gate connected to a second node; a second transistor having a source connected to the first power supply, a drain connected to the second node, and a gate connected to the first node; a third transistor having a source connected to a first bit line, a drain connected to the first node, and a gate connected to a first word line; a fourth transistor having a source connected to a second bit line that forms a first complementary bit line pair with the first bit line, a drain connected to the second node, and a gate connected to the first word line; a fifth transistor having a source connected to the third bit line, a drain connected to the first node, and a gate connected to the second word line; and a sixth transistor having a source connected to a fourth bit line that forms a second complementary bit line pair with the third bit line, a drain connected to the second node, and a gate connected to the second word line. a seventh transistor having a source connected to a second power supply that supplies a second power supply voltage different from the first power supply voltage, a drain connected to the first node, and a gate connected to the second node; and an eighth transistor having a source connected to the second power supply, a drain connected to the second node, and a gate connected to the first node, wherein the SRAM cell comprises: a first active region constituting the channel, source, and drain of the third transistor, the channel including a third nanosheet extending in a first direction, and constituting the channel, source, and drain of the fifth transistor, the channel including a fifth nanosheet extending in the first direction; a second active region constituting the channel, source, and drain of the seventh transistor, the channel including a seventh nanosheet extending in the first direction; and a third active region constituting the channel, source, and drain of the eighth transistor, the channel including an eighth nanosheet extending in the first direction.a fourth active region constituting the channel, source, and drain of the fourth transistor, the channel being a fourth nanosheet extending in the first direction, and a sixth nanosheet constituting the channel, source, and drain of the sixth transistor, the channel being extended in the first direction; a fifth active region constituting the channel, source, and drain of the first transistor, the channel being a first nanosheet extending in the first direction; a sixth active region constituting the channel, source, and drain of the second transistor, the channel being a second nanosheet extending in the first direction; first to eighth gate wirings surrounding the first to eighth nanosheets in a second direction perpendicular to the first direction and in a depth direction perpendicular to the first and second directions, respectively; first and second power supply wirings formed in a back wiring layer on the back side of the first to eighth transistors, extending in the first direction, and supplying the second power supply voltage; a first via formed in a region where a region that will become the source of the seventh transistor in the second active region overlaps with the first power supply wiring, connecting the source of the seventh transistor in the second active region with the first power supply wiring; and a second via formed in a region where a region that will become the source of the eighth transistor in the third active region overlaps with the second power supply wiring, connecting the source of the eighth transistor in the third active region with the second power supply wiring; wherein the first, third, fifth, and eighth nanosheets have first-side surfaces, which are one side in the second direction, exposed from the first, third, fifth, and eighth gate wirings, respectively; and the second, fourth, sixth, and seventh nanosheets have second-side surfaces, which are the other side in the second direction, exposed from the second, fourth, sixth, and seventh gate wirings, respectively.

2. A semiconductor memory device according to claim 1, wherein the third and fifth nanosheets are arranged side by side in the first direction, and the fourth and sixth nanosheets are arranged side by side in the first direction.

3. A semiconductor memory device according to claim 1, wherein the SRAM cell comprises: a third power supply wiring formed in the backside wiring layer, extending in the first direction, and supplying the first power supply voltage; a third via formed in a region in the fifth active region where a region serving as the source of the first transistor overlaps with the third power supply wiring, connecting the source of the first transistor in the fifth active region with the third power supply wiring; and a fourth via formed in a region in the sixth active region where a region serving as the source of the second transistor overlaps with the third power supply wiring, connecting the source of the second transistor in the sixth active region with the third power supply wiring.

4. A semiconductor memory device according to claim 1, wherein the first power supply wiring overlaps with the first active region in a plan view.

5. A semiconductor memory device according to claim 1, wherein the first bit line is formed in a metal wiring layer above the first to eighth transistors and includes a first wiring extending in the first direction; the second bit line is formed in the metal wiring layer and includes a second wiring extending in the first direction; the third bit line is formed in the metal wiring layer and includes a third wiring extending in the first direction; and the fourth bit line is formed in the metal wiring layer and includes a fourth wiring extending in the first direction.

6. A semiconductor memory device according to claim 5, wherein a fourth power supply wiring extending in the first direction and supplying the second power supply voltage is formed in the metal wiring layer between the first wiring and the third wiring, and a fifth power supply wiring extending in the first direction and supplying the second power supply voltage is formed in the metal wiring layer between the second wiring and the fourth wiring.

7. A semiconductor memory device according to claim 1, wherein a sixth power supply wiring extending in the first direction and supplying the first power supply voltage is formed in a metal wiring layer above the first to eighth transistors, and the sixth power supply wiring is connected to the source of the first transistor and the source of the second transistor.

8. A semiconductor memory device according to claim 1, wherein the third bit line is formed in the backside wiring layer, extends in the first direction, and includes a fifth wiring that overlaps the first active region in a planar view; the fourth bit line is formed in the backside wiring layer, extends in the first direction, and includes a sixth wiring that overlaps the fourth active region in a planar view; and the SRAM cell comprises: a fifth via formed in a region in the first active region where a region that becomes the source of the fifth transistor overlaps with the fifth wiring, connecting the source of the fifth transistor in the first active region to the fifth wiring; and a sixth via formed in a region in the fourth active region where a region that becomes the source of the sixth transistor overlaps with the sixth wiring, connecting the source of the sixth transistor in the fourth active region to the sixth wiring.

9. A semiconductor memory device including an SRAM cell, wherein the SRAM cell comprises: a first transistor having a source connected to a first power supply that supplies a first power supply voltage, a drain connected to a first node, and a gate connected to a second node; a second transistor having a source connected to the first power supply, a drain connected to the second node, and a gate connected to the first node; a third transistor having a source connected to a first bit line, a drain connected to the first node, and a gate connected to a first word line; a fourth transistor having a source connected to a second bit line that forms a first complementary bit line pair with the first bit line, a drain connected to the second node, and a gate connected to the first word line; a fifth transistor having a source connected to the third bit line, a drain connected to the first node, and a gate connected to the second word line; and a sixth transistor having a source connected to a fourth bit line that forms a second complementary bit line pair with the third bit line, a drain connected to the second node, and a gate connected to the second word line. the SRAM cell comprises: a seventh transistor having a source connected to a second power supply that supplies a second power supply voltage different from the first power supply voltage, a drain connected to the first node, and a gate connected to the second node; and an eighth transistor having a source connected to the second power supply, a drain connected to the second node, and a gate connected to the first node, wherein the seventh transistor includes a ninth transistor and a tenth transistor; and the eighth transistor includes an eleventh transistor and a twelfth transistor; the SRAM cell comprises: a first active region constituting the channel, source, and drain of the fifth transistor, the channel being a fifth nanosheet extending in a first direction, and constituting the channel, source, and drain of the ninth transistor, the channel being a ninth nanosheet extending in the first direction; a second active region constituting the channel, source, and drain of the third transistor, the channel being a third nanosheet extending in the first direction, and constituting the channel, source, and drain of the tenth transistor, the channel being a tenth nanosheet extending in the first direction;a third active region constituting the channel, source, and drain of the sixth transistor, the channel being a sixth nanosheet extending in the first direction, and constituting the channel, source, and drain of the eleventh transistor, the channel being an eleventh nanosheet extending in the first direction; a fourth active region constituting the channel, source, and drain of the fourth transistor, the channel being a fourth nanosheet extending in the first direction, and constituting the channel, source, and drain of the twelfth transistor, the channel being a twelfth nanosheet extending in the first direction; a fifth active region constituting the channel, source, and drain of the first transistor, the channel being a first nanosheet extending in the first direction; a sixth active region constituting the channel, source, and drain of the second transistor, the channel being a second nanosheet extending in the first direction; first to sixth and ninth to twelfth gate wirings surrounding the first to sixth and ninth to twelfth nanosheets in a second direction perpendicular to the first direction and in a depth direction perpendicular to the first and second directions, respectively; first and second power supply wirings formed in a back wiring layer on the back side of the first to sixth and ninth to twelfth transistors, extending in the first direction, and supplying the second power supply voltage; at least one of a first via formed in a region where a region serving as a source of the ninth transistor in the first active region overlaps with the first power supply wiring, connecting the source of the ninth transistor in the first active region with the first power supply wiring, and a second via formed in a region where a region serving as a source of the tenth transistor in the second active region overlaps with the first power supply wiring,a third via formed in a region in the third active region where a region serving as a source of the eleventh transistor overlaps with the second power supply wiring, connecting the source of the eleventh transistor in the third active region with the second power supply wiring, and a fourth via formed in a region in the fourth active region where a region serving as a source of the twelfth transistor overlaps with the second power supply wiring, connecting the source of the twelfth transistor in the fourth active region with the second power supply wiring; wherein the first, fifth, sixth, ninth, and eleventh nanosheets have first side surfaces, which are one side in the second direction, exposed from the first, fifth, sixth, ninth, and eleventh gate wirings, respectively; and the second, third, fourth, tenth, and twelfth nanosheets have second side surfaces, which are the other side in the second direction, exposed from the second, third, fourth, tenth, and twelfth gate wirings, respectively.

10. A semiconductor memory device according to claim 9, wherein the fifth and ninth nanosheets are arranged side by side in the first direction, the third and tenth nanosheets are arranged side by side in the first direction, the sixth and eleventh nanosheets are arranged side by side in the first direction, and the fourth and twelfth nanosheets are arranged side by side in the first direction.

11. A semiconductor memory device according to claim 9, wherein the SRAM cell comprises: a third power supply wiring formed in the back wiring layer, extending in the first direction, and supplying the first power supply voltage; a fifth via formed in a region in the fifth active region where a region serving as the source of the first transistor overlaps with the third power supply wiring, connecting the source of the first transistor in the fifth active region to the third power supply wiring; and a sixth via formed in a region in the sixth active region where a region serving as the source of the second transistor overlaps with the third power supply wiring, connecting the source of the second transistor in the sixth active region to the third power supply wiring.

12. A semiconductor memory device according to claim 9, wherein the SRAM cell comprises the first and second vias.

13. A semiconductor memory device according to claim 9, wherein the first bit line is formed in a metal wiring layer above the first to eighth transistors and includes a first wiring extending in the first direction; the second bit line is formed in the metal wiring layer and includes a second wiring extending in the first direction; the third bit line is formed in the metal wiring layer and includes a third wiring extending in the first direction; and the fourth bit line is formed in the metal wiring layer and includes a fourth wiring extending in the first direction.

14. A semiconductor memory device according to claim 9, wherein the first bit line is formed in the backside wiring layer, extends in the first direction, and includes a fifth wiring that overlaps the second active region in a planar view; the second bit line is formed in the backside wiring layer, extends in the first direction, and includes a sixth wiring that overlaps the fourth active region in a planar view; and the SRAM cell comprises: a seventh via that is formed in a region in the second active region where a region that becomes the source of the third transistor overlaps with the fifth wiring, and that connects the source of the third transistor in the second active region to the fifth wiring; and an eighth via that is formed in a region in the fourth active region where a region that becomes the source of the fourth transistor overlaps with the sixth wiring, and that connects the source of the fourth transistor in the fourth active region to the sixth wiring.

15. A semiconductor memory device according to claim 9, wherein the SRAM cell is formed in a metal wiring layer above the first to eighth transistors, extends in the first direction, and includes a fourth power supply wiring that supplies the second power supply voltage, and the fourth power supply wiring is connected to the source of the twelfth transistor.

16. A semiconductor memory device including an SRAM cell, wherein the SRAM cell comprises: a first transistor having a source connected to a first power supply that supplies a first power supply voltage, a drain connected to a first node, and a gate connected to a second node; a second transistor having a source connected to the first power supply, a drain connected to the second node, and a gate connected to the first node; a third transistor having a source connected to a first bit line, a drain connected to the first node, and a gate connected to a first word line; a fourth transistor having a source connected to a second bit line that forms a first complementary bit line pair with the first bit line, a drain connected to the second node, and a gate connected to the first word line; a fifth transistor having a source connected to the third bit line, a drain connected to the first node, and a gate connected to the second word line; and a sixth transistor having a source connected to a fourth bit line that forms a second complementary bit line pair with the third bit line, a drain connected to the second node, and a gate connected to the second word line. a seventh transistor having a source connected to a second power supply that supplies a second power supply voltage different from the first power supply voltage, a drain connected to the first node, and a gate connected to the second node; and an eighth transistor having a source connected to the second power supply, a drain connected to the second node, and a gate connected to the first node, wherein the seventh transistor includes a ninth transistor and a tenth transistor, and the eighth transistor includes an eleventh transistor and a twelfth transistor, wherein the first bit line is formed in a back wiring layer on the back side of the first to sixth and ninth to twelfth transistors and includes a first wiring extending in a first direction, the second bit line is formed in the back wiring layer and includes a second wiring extending in the first direction, the third bit line is formed in the back wiring layer and includes a third wiring extending in the first direction, and the fourth bit line is formed in the back wiring layer and includes a fourth wiring extending in the first direction, and the SRAM cell comprises:a first active region constituting the channel, source, and drain of the fifth transistor, the channel being a fifth nanosheet extending in the first direction, and constituting the channel, source, and drain of the ninth transistor, the channel being a ninth nanosheet extending in the first direction; a second active region constituting the channel, source, and drain of the third transistor, the channel being a third nanosheet extending in the first direction, and constituting the channel, source, and drain of the tenth transistor, the channel being a tenth nanosheet extending in the first direction; a third active region constituting the channel, source, and drain of the sixth transistor, the channel being a sixth nanosheet extending in the first direction, and constituting the channel, source, and drain of the eleventh transistor, the channel being an eleventh nanosheet extending in the first direction; a fourth active region constituting the channel, source, and drain of the fourth transistor, the channel being a fourth nanosheet extending in the first direction, and a twelfth nanosheet constituting the channel, source, and drain of the twelfth transistor, the channel being extended in the first direction; a fifth active region constituting the channel, source, and drain of the first transistor, the channel being a first nanosheet extending in the first direction; a sixth active region constituting the channel, source, and drain of the second transistor, the channel being a second nanosheet extending in the first direction; first to sixth and ninth to twelfth gate wirings surrounding the first to sixth and ninth to twelfth nanosheets in a second direction perpendicular to the first direction and in a depth direction perpendicular to the first and second directions, respectively; a first via formed in a region in the second active region where a region serving as the source of the third transistor overlaps with the first wiring, and connecting the source of the third transistor in the second active region to the first wiring;a second via formed in a region in the fourth active region where a region that will become the source of the fourth transistor and the second wiring overlap, connecting the source of the fourth transistor in the fourth active region and the second wiring; a third via formed in a region in the first active region where a region that will become the source of the fifth transistor and the third wiring overlap, connecting the source of the fifth transistor in the first active region and the third wiring; and a fourth via formed in a region in the third active region where a region that will become the source of the sixth transistor and the fourth wiring overlap, connecting the source of the sixth transistor in the third active region and the fourth wiring; wherein a first side surface of the first, fifth, sixth, ninth and eleventh nanosheets, which is one side in the second direction, is exposed from the first, fifth, sixth, ninth and eleventh gate wirings, respectively; A semiconductor memory device, wherein the second, third, fourth, tenth, and twelfth nanosheets have second-side surfaces, which are the other side in the second direction, exposed from the second, third, fourth, tenth, and twelfth gate wirings, respectively.

17. A semiconductor memory device according to claim 16, wherein the fifth and ninth nanosheets are arranged side by side in the first direction, the third and tenth nanosheets are arranged side by side in the first direction, the sixth and eleventh nanosheets are arranged side by side in the first direction, and the fourth and twelfth nanosheets are arranged side by side in the first direction.

18. A semiconductor memory device according to claim 16, wherein the SRAM cell comprises: a first power supply wiring formed in the back wiring layer, extending in the first direction, and connected to supply the first power supply voltage; a fifth via formed in a region where a region serving as the source of the first transistor in the fifth active region overlaps with the first power supply wiring, connecting the source of the first transistor in the fifth active region to the first power supply wiring; and a sixth via formed in a region where a region serving as the source of the second transistor in the sixth active region overlaps with the first power supply wiring, connecting the source of the second transistor in the sixth active region to the first power supply wiring.

19. A semiconductor memory device according to claim 16, wherein second and third power supply wirings extending in the first direction and supplying the first power supply voltage are formed in a metal wiring layer above the first to eighth transistors, the second power supply wiring is connected to the source of the ninth transistor and the source of the tenth transistor, and the third power supply wiring is connected to the source of the eleventh transistor and the source of the twelfth transistor.

Images