Semiconductor memory device

Abstract

According to the present invention, SRAM cell is provided with active regions (N1, N2). Power supply wires (12, 13) for supplying power supply voltage VSS are formed in a first back surface wiring layer. A portion serving as a source of a drive transistor (PD1) in the active region (N2) is connected to the power supply wire (12) via a via (91) provided at a position overlapping the power supply wire (12) in plan view. A portion serving as a source of a drive transistor (PD2) in the active region (N1) is connected to the power supply wire (13) via a via (92) provided at a position overlapping the power supply wire (13) in plan view.

Description

semiconductor memory device

[0001] The present disclosure relates to a semiconductor memory device including a nanosheet FET (Field Effect Transistor), and in particular to a layout structure of an SRAM (Static Random Access Memory) cell (hereinafter also simply referred to as a cell, as appropriate).

[0002] SRAMs are widely used in semiconductor integrated circuits.

[0003] Furthermore, transistors, which are fundamental components of LSIs, have achieved improved integration density, reduced operating voltages, and improved operating speeds through the reduction of gate length (scaling). However, in recent years, excessive scaling has led to problems with off-state current and the resulting significant increase in power consumption. To solve this problem, three-dimensional transistors, which change the transistor structure from the conventional planar type to a three-dimensional type, have been actively researched. Nanosheet FETs are one type of three-dimensional transistor that has attracted attention.

[0004] Patent Document 1 discloses an SRAM cell that uses a fork sheet transistor, which is a nanosheet FET and has a gate electrode in a fork shape, in order to reduce the area of ​​a semiconductor memory device.

[0005] International Publication No. 2021 / 166645

[0006] In the technology of Patent Document 1, the bit lines and power supply lines are provided separately in the buried wiring layer and the upper wiring layer, thereby increasing the wiring width of the wiring provided in the upper wiring layer, but the wiring in the buried wiring layer cannot be provided overlapping with the transistor (nanosheet). Therefore, the wiring width of the wiring formed in the buried wiring layer cannot be increased, so the wiring resistance of the wiring increases and the operating speed of the semiconductor memory device decreases.

[0007] The present disclosure aims to improve the operating speed of a semiconductor memory device in a layout structure of an SRAM cell.

[0008] In a first aspect of the present disclosure, there is provided a semiconductor memory device including an SRAM cell, the SRAM cell comprising: a first transistor having a source connected to a first power supply that supplies a first power supply voltage, a drain connected to a first node, and a gate connected to a second node; a second transistor having a source connected to the first power supply, a drain connected to the second node, and a gate connected to the first node; a third transistor having a source connected to a second power supply that supplies a second power supply voltage different from the first power supply voltage, a drain connected to the first node, and a gate connected to the second node; a fourth transistor having a drain connected to the second node and a gate connected to the first node; a fifth transistor having a source connected to a first bit line, a drain connected to the first node, and a gate connected to a word line; and a sixth transistor having a source connected to a second bit line forming a complementary bit line pair with the first bit line, a drain connected to the second node, and a gate connected to the word line, and the SRAM cell includes a fourth nano-channel transistor that forms a channel, a source, and a drain of the fourth transistor, the channel extending in a first direction. a first active region constituting the channel, source, and drain of the sixth transistor, the channel including the sixth nanosheet extending in the first direction as the channel; a second active region constituting the channel, source, and drain of the third transistor, the channel including the third nanosheet extending in the first direction as the channel; and a second active region constituting the channel, source, and drain of the fifth transistor, the channel including the fifth nanosheet extending in the first direction as the channel; a third active region constituting the channel, source, and drain of the first transistor, the channel including the first nanosheet extending in the first direction as the channel; a fourth active region constituting the channel, source, and drain of the second transistor, the channel including the second nanosheet extending in the first direction as the channel; first to sixth gate wirings surrounding the first to sixth nanosheets in a second direction perpendicular to the first direction and in a depth direction perpendicular to the first and second directions, respectively; andthe first, fourth, and sixth nanosheets have first and second power supply wirings extending in the first direction and supplying the second power supply voltage; a first via formed in a region where a region in the first active region that becomes the source of the fourth transistor overlaps with the first power supply wiring and connecting the source of the fourth transistor in the first active region to the first power supply wiring; and a second via formed in a region where a region in the second active region that becomes the source of the third transistor overlaps with the second power supply wiring and connecting the source of the third transistor in the second active region to the second power supply wiring, wherein the first, fourth, and sixth nanosheets have first-side surfaces, which are one side in the second direction, exposed from the first, fourth, and sixth gate wirings, respectively, and the second, third, and fifth nanosheets have second-side surfaces, which are the other side in the second direction, exposed from the second, third, and fifth gate wirings, respectively.

[0009] According to the present disclosure, first and second power supply wirings for supplying a second power supply voltage are formed in the first back wiring layer. This allows the wiring width of the bit lines to be increased. Therefore, the wiring resistance of the bit lines can be reduced, thereby improving the operating speed of the semiconductor memory device. Furthermore, the active region and the power supply wiring can be arranged to overlap, allowing the wiring widths of the first and second power supply wirings to be increased. Therefore, the wiring resistance of the power supply wiring can be reduced, and power supply voltage drops can be suppressed, thereby improving the operating speed and stability of the semiconductor memory device.

[0010] A second aspect of the present disclosure is a semiconductor memory device including an SRAM cell, wherein the SRAM cell includes a first transistor having a source connected to a first power supply that supplies a first power supply voltage, a drain connected to a first node, and a gate connected to a second node; a second transistor having a source connected to the first power supply, a drain connected to the second node, and a gate connected to the first node; a third transistor having a source connected to a second power supply that supplies a second power supply voltage different from the first power supply voltage, a drain connected to the first node, and a gate connected to the second node; a fourth transistor having a drain connected to the second node and a gate connected to the first node, a fifth transistor having a source connected to a first bit line, a drain connected to the first node, and a gate connected to a word line, and a sixth transistor having a source connected to a second bit line forming a complementary bit line pair with the first bit line, a drain connected to the second node, and a gate connected to the word line, the first bit line being formed in a first back wiring layer on the back side of the first to sixth transistors and including a first wiring extending in a first direction, the SRAM cell includes a first active region constituting the channel, source, and drain of the fourth transistor, the channel of which is a fourth nanosheet extending in the first direction, and a sixth nanosheet constituting the channel, source, and drain of the sixth transistor, the channel of which is a sixth nanosheet extending in the first direction; a second active region constituting the channel, source, and drain of the third transistor, the channel of which is a third nanosheet extending in the first direction, and a fifth nanosheet constituting the channel, source, and drain of the fifth transistor, the channel of which is a fifth nanosheet extending in the first direction; a third active region constituting the channel, source, and drain of the first transistor, the channel of which is a first nanosheet extending in the first direction; and a fourth active region constituting the channel, source, and drain of the second transistor, the channel of which is a second nanosheet extending in the first direction.the first to sixth gate wirings surrounding the first to sixth nanosheets in a second direction perpendicular to the first direction and in a depth direction perpendicular to the first and second directions, respectively; a first via formed in a region where a region serving as a source of the sixth transistor in the first active region overlaps with the second wiring and connecting the source of the sixth transistor in the first active region with the second wiring; and a second via formed in a region where a region serving as a source of the fifth transistor in the second active region overlaps with the first wiring and connecting the source of the fifth transistor in the second active region with the second wiring, wherein the first, fourth, and sixth nanosheets have first-side surfaces, which are one side in the second direction, exposed from the first, fourth, and sixth gate wirings, respectively, and the second, third, and fifth nanosheets have second-side surfaces, which are the other side in the second direction, exposed from the second, third, and fifth gate wirings, respectively.

[0011] According to the present disclosure, first and second wirings corresponding to the first and second bit lines, respectively, are formed in the backside wiring layer. Furthermore, the active region and the bit lines can be arranged to overlap. This allows the wiring width of the bit lines to be increased. Therefore, the wiring resistance of the bit lines can be reduced, thereby improving the operating speed of the semiconductor memory device. Furthermore, the wiring width of the power supply wiring can be increased. Therefore, the wiring resistance of the power supply wiring can be reduced, and power supply voltage drops can be suppressed, thereby improving the operating speed and operational stability of the semiconductor memory device.

[0012] According to the present disclosure, the operating speed of a semiconductor memory device can be improved in a layout structure of an SRAM cell.

[0013] 1 is a plan view showing an example of a layout structure of an SRAM cell according to the first embodiment. 2 is a cross-sectional view showing an example of a layout structure of an SRAM cell according to the first embodiment. 3 is a cross-sectional view showing an example of a layout structure of an SRAM cell according to the first embodiment. 4 is a circuit diagram showing a configuration of an SRAM cell according to the first embodiment. 5 is another configuration example of a semiconductor integrated circuit device according to the first embodiment. 6 is a plan view showing another example of a layout structure of an SRAM cell according to the first embodiment. 7 is a plan view showing another example of a layout structure of an SRAM cell according to the first embodiment. 8 is a plan view showing another example of a layout structure of an SRAM cell according to the first embodiment. 9 is a plan view showing another example of a layout structure of an SRAM cell according to the first embodiment. 10 is a plan view showing another example of a layout structure of an SRAM cell according to the first embodiment. 11 is a plan view showing another example of a layout structure of an SRAM cell according to the first embodiment. 12 is a plan view showing another example of a layout structure of an SRAM cell according to the first embodiment. 13 is a plan view showing another example of a layout structure of an SRAM cell according to the first embodiment.

[0014] Hereinafter, embodiments will be described with reference to the drawings. In the following embodiments, a semiconductor memory device includes a plurality of SRAM cells, and at least some of the plurality of SRAM cells include fork sheet transistors, which are nanosheet FETs and have fork-shaped gate electrodes. A nanosheet FET is a FET that uses a thin sheet (nanosheet) through which current flows. The nanosheet is formed of, for example, silicon. In the semiconductor memory device, some of the nanosheet FETs are fork sheet FETs with fork-shaped gate electrodes.

[0015] In this specification, "VDD" and "VSS" refer to the power supply voltage or the power supply itself. In this specification, expressions such as "same wiring width" that mean the same width, etc., are considered to include the range of manufacturing variations.

[0016] (First Embodiment) (Configuration of SRAM Cell) Figures 1 to 3 show an example of the layout structure of an SRAM cell according to the first embodiment, with Figures 1(a) and 1(b) being plan views, and Figures 2(a) to 2(c) and 3(a) and 3(b) being cross-sectional views in the horizontal direction in a plan view. Specifically, Figure 1(a) shows the upper part of the cell, which is the M1 and M2 wiring layers, and Figure 1(b) shows the lower part of the cell, which is a layer below the M1 and M2 wiring layers and includes a nanosheet FET. Figure 2(a) is a cross-section along line X1-X1', Figure 2(b) is a cross-section along line X2-X2', Figure 2(c) is a cross-section along line X3-X3', Figure 3(a) is a cross-section along line X4-X4', and Figure 3(b) is a cross-section along line X5-X5'.

[0017] In the following description, in plan views such as Figure 1, the vertical direction of the drawing is the Y direction (first direction), the horizontal direction of the drawing is the X direction (second direction), and the direction perpendicular to the substrate surface is the Z direction (depth direction).

[0018] 4 is a circuit diagram showing the configuration of an SRAM cell according to the first embodiment. As shown in FIG. 4, the SRAM cell includes an SRAM circuit made up of load transistors PU1 and PU2, drive transistors PD1 and PD2, and access transistors PG1 and PG2. The load transistors PU1 and PU2 are P-type FETs, and the drive transistors PD1 and PD2 and the access transistors PG1 and PG2 are N-type FETs.

[0019] The load transistor PU1 is provided between the power supply VDD and a first node NA, and the drive transistor PD1 is provided between the first node NA and a power supply VSS. The gates of the load transistor PU1 and the drive transistor PD1 are connected to a second node NB, and they form an inverter INV1. The load transistor PU2 is provided between the power supply VDD and the second node NB, and the drive transistor PD2 is provided between the second node NB and the power supply VSS. The gates of the load transistor PU2 and the drive transistor PD2 are connected to the first node NA, and they form an inverter INV2. In other words, the output of one inverter is connected to the input of the other inverter, thereby forming a latch.

[0020] The access transistor PG1 is provided between the bit line BL and a first node NA, and has its gate connected to the word line WL. The access transistor PG2 is provided between the bit line BLB and a second node NB, and has its gate connected to the word line WL. The bit lines BL and BLB form a complementary bit line pair.

[0021] In an SRAM circuit, when the bit lines BL and BLB constituting a complementary bit line pair are driven to a high level and a low level, respectively, and the word line WL is driven to a high level, a high level is written to the first node NA and a low level is written to the second node NB. On the other hand, when the bit lines BL and BLB are driven to a low level and a high level, respectively, and the word line WL is driven to a high level, a low level is written to the first node NA and a high level is written to the second node NB. Then, when the word line WL is driven to a low level while data is written to the first and second nodes NA and NB, respectively, the latch state is established and the data written to the first and second nodes NA and NB is held.

[0022] Furthermore, when the bit lines BL and BLB are precharged to a high level and the word line WL is driven to a high level, the states of the bit lines BL and BLB are determined according to the data written to the first and second nodes NA and NB, respectively, and data can be read from the SRAM cell. Specifically, when the first node NA is at a high level and the second node NB is at a low level, the bit line BL is held at a high level and the bit line BLB is discharged to a low level. On the other hand, when the first node NA is at a low level and the second node NB is at a high level, the bit line BL is discharged to a low level and the bit line BLB is held at a high level.

[0023] As described above, the SRAM cell has the functions of writing data to the SRAM cell, holding data, and reading data from the SRAM cell by controlling the bit lines BL, BLB and word lines WL.

[0024] In the following description, the dashed lines running vertically and horizontally in plan views such as FIG. 1 and the dashed lines running vertically in cross-sectional views such as FIG. 2 indicate grids used for component placement during design. The grids are arranged at equal intervals in the X direction and at equal intervals in the Y direction. The grid spacing may be the same or different in the X and Y directions. The grid spacing may also be different for each layer. Furthermore, each component does not necessarily have to be arranged on a grid.

[0025] 1 and other plan views, the dotted lines surrounding the cells indicate the cell frame (outer edge of the SRAM cell) of the SRAM cell. The SRAM cell is arranged so that the cell frame is in contact with the cell frame of an adjacent cell in the X or Y direction.

[0026] 1 and the like, an SRAM cell is arranged on each side of the SRAM cell in the X direction, with the SRAM cell inverted in the X direction, and an SRAM cell is arranged on each side of the SRAM cell in the Y direction, with the SRAM cell inverted in the Y direction.

[0027] As shown in Figure 1B, the backside of the semiconductor chip on which the transistors are formed has wiring layers, BM0 (Backside Metal 0) and BM1 (Backside Metal 1). The BM1 wiring layer is located below the BM0 wiring layer, i.e., farther from the transistors. The BM0 wiring layer corresponds to the first backside wiring layer, and the BM1 wiring layer corresponds to the second backside wiring layer.

[0028] The BM0 wiring layer is formed with power supply wirings 11 to 13 that extend in the Y direction from the top to the bottom of the cell in the drawing. Power supply wiring 11 is formed in the center of the cell in the X direction in the drawing and supplies a power supply voltage VDD. Power supply wiring 12 is formed at the left end of the cell in the X direction in the drawing and supplies a power supply voltage VSS. Power supply wiring 13 is formed at the right end of the cell in the X direction in the drawing and supplies a power supply voltage VSS. Power supply wiring 12 is shared with other cells arranged on the left side of the drawing. Power supply wiring 13 is shared with other cells arranged on the right side of the drawing.

[0029] The BM1 wiring layer is formed with a power supply wiring 121 extending in the X direction from both the left and right ends of the cell in the drawing. The power supply wiring 121 supplies a power supply voltage VSS. The power supply wiring 121 is connected to the power supply wiring 12 through a via 131 and to the power supply wiring 13 through a via 132.

[0030] A plurality of active regions constituting the channel, source, and drain of the N-type transistor are formed in an N-type transistor region on a P-type substrate (PSub) (not shown). Specifically, active regions N1 and N2 are formed in the N-type transistor region. In plan view, active region N1 overlaps with power supply wiring 12. In plan view, active region N2 overlaps with power supply wiring 13.

[0031] In the N-type transistor region, access transistors PG1 and PG2 and drive transistors PD1 and PD2 are formed. The access transistor PG2, the drive transistors PD2 and PD1, and the access transistor PG1 each have a channel structure of three overlapping sheets in a plan view, and each have nanosheets 21 to 24 extending in the Y direction.

[0032] In the active region N1, the portion that becomes the source of the drive transistor PD2 is connected to the power supply wiring 12 through a via 91 that is provided at a position that overlaps the power supply wiring 12 in a plan view. In the active region N2, the portion that becomes the source of the drive transistor PD1 is connected to the power supply wiring 13 through a via 92 that is provided at a position that overlaps the power supply wiring 13 in a plan view.

[0033] A plurality of active regions constituting the channel, source, and drain of the P-type transistor are formed in a P-type transistor region on an N-type well (NWell) (not shown). Specifically, active regions P1 and P2 are formed in the P-type transistor region. The active regions P1 and P2 overlap with the power supply wiring 11 in a plan view.

[0034] In the P-type transistor region, load transistors PU1 and PU2 are formed. The load transistors PU1 and PU2 have channels formed of three overlapping sheets in a plan view, and have nanosheets 25 and 26 extending in the Y direction, respectively. In other words, the load transistors PU1 and PU2 are nanosheet FETs.

[0035] The width of the nanosheets 21 to 24 in the X direction is twice the width of the nanosheets 25 and 26 in the X direction.

[0036] In the active region P1, the portion that becomes the source of the load transistor PU1 is connected to the power supply wiring 11 through a via 93 that is provided at a position that overlaps the power supply wiring 11 in a planar view. In the active region P2, the portion that becomes the source of the load transistor PU2 is connected to the power supply wiring 11 through a via 94 that is provided at a position that overlaps the power supply wiring 11 in a planar view.

[0037] In the active region, the portions that become the source and drain on both sides of the nanosheet are formed, for example, by epitaxial growth from the nanosheet.

[0038] Gate wirings (Gate) 31 to 36 are formed extending in the X direction. The gate wiring 31 overlaps with the nanosheet 21 in a planar view. The gate wiring 32 overlaps with the nanosheet 25 in a planar view. The gate wiring 33 overlaps with the nanosheet 23 in a planar view. The gate wiring 34 overlaps with the nanosheet 22 in a planar view. The gate wiring 35 overlaps with the nanosheet 26 in a planar view. The gate wiring 36 overlaps with the nanosheet 24 in a planar view. The gate wiring 31 corresponds to the gate of the access transistor PG2. The gate wiring 32 corresponds to the gate of the load transistor PU1. The gate wiring 33 corresponds to the gate of the drive transistor PD1. The gate wiring 34 corresponds to the gate of the drive transistor PD2. The gate wiring 35 corresponds to the gate of the load transistor PU2. The gate wiring 36 corresponds to the gate of the access transistor PG1.

[0039] As shown in Figures 2(b) and 3(a), nanosheets 21 to 26 are each covered by the gate wiring so that a portion of their outer peripheries is exposed. Specifically, nanosheets 21, 22, and 25 have their right-hand surfaces in the X direction exposed from gate wirings 31, 34, and 32, respectively, and their left-hand surfaces in the X direction covered by gate wirings 31, 34, and 32, respectively. Nanosheets 23, 24, and 26 have their left-hand surfaces in the X direction exposed from gate wirings 33, 36, and 35, respectively, and their right-hand surfaces in the X direction covered by gate wirings 33, 36, and 35, respectively. That is, nanosheets 22 (21) and 26 have their opposing surfaces in the X direction exposed from gate wirings 34 (31) and 35, respectively. Nanosheets 25 and 23 (24) have their opposing surfaces in the X direction exposed from gate wirings 32 and 33 (36), respectively.

[0040] The gate wirings 32 and 33 are connected via a bridge portion 40a extending in the X direction, and the gate wirings 34 and 35 are connected via a bridge portion 40b extending in the X direction.

[0041] The local interconnect layer is formed with local interconnects (LI) 41 to 48 extending in the X direction. The local interconnect 41 is connected to a portion that serves as the source of the access transistor PG2 in the active region N1. The local interconnect 42 is connected to a portion that serves as the source of the load transistor PU1 in the active region P1. The local interconnect 43 is connected to a portion that serves as the source of the drive transistor PD1 in the active region N2. The local interconnect 44 is connected to a portion that serves as the drain of the access transistor PG2 in the active region N1, a portion that serves as the drain of the drive transistor PD2 in the active region N1, and a portion that serves as the drain of the load transistor PU2 in the active region P2. The local interconnect 45 is connected to a portion that serves as the drain of the load transistor PU1 in the active region P1, a portion that serves as the drain of the drive transistor PD1 in the active region N2, and a portion that serves as the drain of the access transistor PG1 in the active region N2. The local interconnect 46 is connected to a portion that serves as the source of the drive transistor PD2 in the active region N1. The local wiring 47 is connected to a portion that will become the source of the load transistor PU2 in the active region P2, and the local wiring 48 is connected to a portion that will become the source of the access transistor PG1 in the active region N2.

[0042] The local wiring 44 is connected to the gate wiring 32 via a shared contact 51. The local wiring 45 is connected to the gate wiring 35 via a shared contact 52. The gate wirings 34 and 35, the bridge portion 40b, the local wiring 45, and the shared contact 52 correspond to a first node NA. The gate wirings 32 and 33, the bridge portion 40a, the local wiring 44, and the shared contact 51 correspond to a second node NB.

[0043] As shown in FIG. 1A, wires 61 and 62 extending in the Y direction from the top to the bottom of the cell are formed in the M1 wiring layer, which is a metal wiring layer above the local wiring layer. Wires 63 and 64 are also formed. Wires 61 and 62 correspond to bit lines BLB and BL, respectively. Wire 61 overlaps with active region N1 and power supply wiring 12 in a plan view. Wire 62 overlaps with active region N2 and power supply wiring 13 in a plan view.

[0044] The wiring 61 is connected to the local wiring 41 through a via 53. The wiring 62 is connected to the local wiring 48 through a via 54.

[0045] In the M2 wiring layer, which is a layer above the M1 wiring layer, a wiring 71 and power supply wirings 72 and 73 are formed, which extend in the X direction from the left to the right ends of the cell in the drawing. The wiring 71 is formed in the center of the cell in the Y direction in the drawing and corresponds to the word line WL. The power supply wiring 72 is formed at the upper end of the cell in the Y direction in the drawing and supplies the power supply voltage VSS. The power supply wiring 73 is formed at the lower end of the cell in the Y direction in the drawing and supplies the power supply voltage VSS. The power supply wiring 72 is shared with other cells arranged above the drawing. The power supply wiring 73 is shared with other cells arranged below the drawing.

[0046] The wiring 71 is connected to the gate wiring 31 through a via 81, a wiring 63, and a via 55. The wiring 71 is connected to the gate wiring 36 through a via 82, a wiring 64, and a via 56.

[0047] With the above configuration, a power supply wiring 11 that supplies a power supply voltage VDD and power supply wirings 12 and 13 that supply a power supply voltage VSS are formed in the BM0 wiring layer, which is a wiring layer on the back surface of the transistor. Wirings 61 and 62 corresponding to the bit lines BLB and BL, respectively, are formed in the M1 wiring layer, which is a metal wiring layer above the transistor. As a result, the only wiring formed in the BM0 wiring layer is the power supply wiring that supplies the power supply voltages VDD and VSS. Therefore, the wiring width of the power supply wirings 11 to 13 that supply the power supply voltages VDD and VSS formed in the BM0 wiring layer can be increased, thereby reducing the wiring resistance of the power supply wiring. Furthermore, the power supply wiring 11 overlaps the active regions P1 and P2 in a planar view and is connected to each other by vias 93 and 94 provided in the overlapping region. The power supply wiring 12 overlaps the active region N1 in a planar view and is connected to each other by a via 91 provided in the overlapping region. The power supply wiring 13 overlaps the active region N2 in plan view and is connected to the active region N2 by a via 92 provided in the overlapping region. Therefore, since the active region and the power supply wiring can be arranged overlapping, the wiring width of the power supply wirings 11 to 13 that supply the power supply voltages VDD and VSS can be increased, and the wiring resistance of the power supply wiring can be reduced. This can improve the operating speed and stability of the semiconductor memory device. Furthermore, since it is not necessary to form the power supply wirings that supply the power supply voltages VDD and VSS in the M1 wiring layer, the wiring width of the wirings 61 and 62 corresponding to the bit lines BLB and BL, respectively, can be increased. This reduces the wiring resistance of the bit lines, and therefore the operating speed of the semiconductor memory device can be improved. Furthermore, by increasing the wiring width of the power supply wirings 11 to 13, the wiring resistance of the wirings that supply the power supply voltages VDD and VSS can be reduced, and therefore the operating stability, particularly the retention characteristics (static noise margin) of the SRAM cells, can be improved.

[0048] Furthermore, the power supply wirings 12 and 13 formed in the BM0 wiring layer and supplying the power supply voltage VSS are respectively arranged at the left and right ends of the cell in the X direction of the drawing, and are shared with the cells arranged on the left and right sides of the drawing. This allows the power supply wiring that supplies the power supply voltage VSS to be strengthened, thereby improving the operational stability and operating speed of the semiconductor memory device. Note that in FIG. 1, the power supply wirings 12 and 13 do not necessarily have to be arranged at the left and right ends of the drawing in the X direction.

[0049] Furthermore, the surfaces of the nanosheets 22 (21) and 26 that face each other in the X direction are exposed from the gate wirings 34 (31) and 35, respectively. The surfaces of the nanosheets 25 and 23 (24) that face each other in the X direction are exposed from the gate wirings 32 and 33 (36), respectively. This reduces the distance d1 in the X direction between the drive transistor PD2 (access transistor PG2) and the load transistor PU2, and the distance d1 in the X direction between the load transistor PU1 and the drive transistor PD1 (access transistor PG1). This allows the area of ​​the semiconductor memory device to be reduced.

[0050] (Another Configuration Example) Fig. 5(a) shows another configuration example of the semiconductor integrated circuit device according to the first embodiment. The semiconductor integrated circuit device 100 shown in Fig. 5(a) is configured by stacking a first semiconductor chip 101 (chip A) and a second semiconductor chip 102 (chip B). Chip A has the above-mentioned SRAM cells and the like arranged therein. Chip B has power supply wiring formed in a wiring layer provided on its surface. Chip B is attached to the back side of chip A using bumps and the like.

[0051] 5B shows a cross section of the SRAM cell of FIG. 1 taken along line X1-X1' in this configuration example. As shown in FIG. 5B, a power supply wiring 11 that supplies VDD and power supply wirings 12 and 13 that supply VSS are formed in a wiring layer provided on the surface of chip B. Power supply wiring 11 is connected to active region P1 of chip A via via 93. Power supply wiring 13 is connected to active region N2 of chip A via via 92. Although not shown in the figure, power supply wiring 12 is connected to active region N1 of chip A via via 91. Power supply wiring 11 is connected to active region P2 of chip A via via 94.

[0052] (Modification 1) Fig. 6 is a plan view showing another example of the layout structure of the SRAM cell according to the first embodiment. Specifically, Fig. 6 shows the lower part of the cell. Note that the upper part of the cell in Fig. 6 is the same as Fig. 1(a).

[0053] 6, compared to FIG. 1, in place of the power supply wiring 121, a power supply wiring 122 extending in the X direction from both the left and right ends of the cell is formed in the BM1 wiring layer.

[0054] The power supply wiring 122 is formed in the center of the cell in the Y direction in the drawing, and supplies the power supply voltage VDD. The power supply wiring 122 is connected to the power supply wiring 11 through a via 133.

[0055] 6 makes it possible to strengthen the power supply voltage VDD supplied to the SRAM cells, and also to obtain the same effects as those in FIG.

[0056] (Modification 2) Fig. 7 is a plan view showing another example of the layout structure of the SRAM cell according to the first embodiment. Specifically, Fig. 7 shows the lower part of the cell. Note that the upper part of the cell in Fig. 7 is the same as Fig. 1(a).

[0057] 7, compared to FIG. 1, power supply wiring 123 and 124 extending in the X direction from both the left and right ends of the cell are formed in the BM1 wiring layer instead of the power supply wiring 121.

[0058] The power supply wiring 123 is formed at the upper end of the cell in the Y direction in the drawing, and supplies the power supply voltage VDD. The power supply wiring 123 is connected to the power supply wiring 11 through a via 134.

[0059] The power supply wiring 124 is formed at the bottom end of the cell in the Y direction in the drawing, and supplies the power supply voltage VSS. The power supply wiring 124 is connected to the power supply wiring 12 through a via 135, and is connected to the power supply wiring 13 through a via 136.

[0060] 7 makes it possible to strengthen the power supply voltages VDD and VSS supplied to the SRAM cells, and also to obtain the same effects as those in FIG.

[0061] 8A and 8B are plan views showing another example of the layout structure of the SRAM cell according to the first embodiment. Specifically, Fig. 8A shows the lower part of the cell, and Fig. 8B shows the upper part of the cell.

[0062] In FIG. 8, compared to FIG. 1, a power supply wiring 65 extending in the Y direction from both the upper and lower ends of the cell is formed in the M1 wiring layer.

[0063] The power supply wiring 65 is formed between the wirings 61 and 62 and supplies a power supply voltage VDD. The power supply wiring 65 overlaps with the power supply wiring 11 and the active regions P1 and P2 in plan view.

[0064] The power supply wiring 65 is connected to the portion that will become the source of the load transistor PU1 in the active region P1 through the via 57 and the local wiring 42. The power supply wiring 65 is connected to the portion that will become the source of the load transistor PU2 in the active region P2 through the via 58 and the local wiring 47.

[0065] 8, the power supply line 65 that supplies the power supply voltage VDD suppresses crosstalk noise between the lines 61 and 62 that correspond to the bit lines BLB and BL, respectively, thereby stabilizing the operation of the semiconductor memory device.

[0066] Furthermore, the power supply voltage VDD supplied to the SRAM cells can be strengthened by the power supply wiring 65. This makes it possible to improve the operating speed of the semiconductor memory device.

[0067] In addition, the same effects as those in FIG. 1 can be obtained.

[0068] In FIG. 8, the power supply wiring 11 formed in the BM0 wiring layer for supplying the power supply voltage VDD may be omitted.

[0069] 9A and 9B are plan views showing another example of the layout structure of the SRAM cell according to the first embodiment. Specifically, Fig. 9A shows the upper part of the cell, and Fig. 9B shows the lower part of the cell.

[0070] In FIG. 9, compared to FIG. 1, the surfaces of the nanosheets 21 to 26 opposite to the X direction are exposed from the gate wiring.

[0071] As shown in FIG. 9B, the gate wiring 31 overlaps with the nanosheet 21 in a planar view. The gate wiring 33 overlaps with the nanosheets 25 and 23 in a planar view. The gate wiring 34 overlaps with the nanosheets 22 and 26 in a planar view. The gate wiring 36 overlaps with the nanosheet 24 in a planar view. The gate wiring 31 corresponds to the gate of the access transistor PG2. The gate wiring 33 corresponds to the gates of the load transistor PU1 and the drive transistor PD1. The gate wiring 34 corresponds to the gates of the drive transistor PD2 and the load transistor PU2. The gate wiring 36 corresponds to the gate of the access transistor PG1.

[0072] Nanosheets 21 to 26 are each covered by the gate wiring so that a portion of their outer peripheries is exposed. Specifically, nanosheets 23, 24, and 26 have their right-hand surfaces in the X direction exposed from gate wirings 33, 36, and 34, respectively, and their left-hand surfaces in the X direction covered by gate wirings 33, 36, and 34, respectively. Nanosheets 21, 22, and 25 have their left-hand surfaces in the X direction exposed from gate wirings 31, 34, and 33, respectively, and their right-hand surfaces in the X direction covered by gate wirings 31, 34, and 33, respectively. That is, nanosheets 25 and 26 have their surfaces facing each other in the X direction exposed from gate wirings 33 and 34, respectively.

[0073] Nanosheets 21 and 22 are arranged close to the cell boundary on the left side of the drawing. Nanosheets 23 and 24 are arranged close to the cell boundary on the right side of the drawing. In the SRAM cell of FIG. 9 , SRAM cells inverted in the X direction are arranged on both the left and right sides of the drawing. That is, in the SRAM cells arranged in the X direction, the surfaces of nanosheets 21 facing each other in the X direction are exposed from gate wiring 31. Similarly, the surfaces of nanosheets 22 facing each other in the X direction are exposed from gate wiring 34. The surfaces of nanosheets 23 facing each other in the X direction are exposed from gate wiring 33. The surfaces of nanosheets 24 facing each other in the X direction are exposed from gate wiring 36.

[0074] Gate wirings 32 and 33 are connected via a bridge portion 40c extending in the X direction. Gate wirings 34 and 35 are connected via a bridge portion 40d extending in the X direction. Gate wiring 31 is connected to gate wiring 31 located on the left side of the SRAM cell in the drawing via a bridge portion 40e extending in the X direction. Gate wiring 36 is connected to gate wiring 36 located on the right side of the SRAM cell in the drawing via a bridge portion 40f extending in the X direction.

[0075] The wiring 71 corresponding to the word line WL is connected to the gate wiring 31 through the via 81, the wiring 63, the via 55, and the bridge portion 40e. The wiring 71 is connected to the gate wiring 36 through the via 82, the wiring 64, the via 56, and the bridge portion 40f.

[0076] 9, the surfaces of the nanosheets 25 and 26 that face each other in the X direction are exposed from the gate wirings 33 and 34. This makes it possible to reduce the distance d1 in the X direction between the load transistors PU1 and PU2.

[0077] Furthermore, in the SRAM cells aligned in the X direction, the surfaces of the nanosheets 21 facing each other in the X direction are exposed from the gate wiring 31. Similarly, the surfaces of the nanosheets 22 facing each other in the X direction are exposed from the gate wiring 34. The surfaces of the nanosheets 23 facing each other in the X direction are exposed from the gate wiring 33. The surfaces of the nanosheets 24 facing each other in the X direction are exposed from the gate wiring 36. This allows the distance d1 in the X direction between the access transistors PG2, the distance d1 in the X direction between the drive transistors PD2, the distance d1 in the X direction between the drive transistors PD1, and the distance d1 in the X direction between the access transistors PG1 to be reduced in the SRAM cells aligned in the X direction. This allows the area of ​​the semiconductor memory device to be reduced.

[0078] In addition, the same effects as those in FIG. 1 can be obtained.

[0079] (Variation 5) Fig. 10 is a plan view showing another example of the layout structure of the SRAM cell according to the first embodiment. Specifically, Fig. 10 shows the lower part of the cell. Note that the upper part of the cell in Fig. 10 is the same as Fig. 9(a).

[0080] 10, compared to FIG. 9, in place of the power supply wiring 121, a power supply wiring 122 extending in the X direction from both the left and right ends of the cell is formed in the BM1 wiring layer.

[0081] The power supply wiring 122 is formed in the center of the cell in the Y direction in the drawing, and supplies the power supply voltage VDD. The power supply wiring 122 is connected to the power supply wiring 11 through a via 133.

[0082] 10 makes it possible to strengthen the power supply voltage VDD supplied to the SRAM cells, and also to obtain the same effects as those in FIG.

[0083] (Variation 6) Fig. 11 is a plan view showing another example of the layout structure of the SRAM cell according to the first embodiment. Specifically, Fig. 11 shows the lower part of the cell. Note that the upper part of the cell in Fig. 11 is the same as Fig. 9(a).

[0084] 11, in comparison with FIG. 1, power supply wiring 123 and 124 extending in the X direction from both the left and right ends of the cell are formed in the BM1 wiring layer instead of the power supply wiring 121.

[0085] The power supply wiring 123 is formed at the upper end of the cell in the Y direction in the drawing, and supplies the power supply voltage VDD. The power supply wiring 123 is connected to the power supply wiring 11 through a via 134.

[0086] The power supply wiring 124 is formed at the bottom end of the cell in the Y direction in the drawing, and supplies the power supply voltage VSS. The power supply wiring 124 is connected to the power supply wiring 12 through a via 135, and is connected to the power supply wiring 13 through a via 136.

[0087] 11, the power supply voltages VDD and VSS supplied to the SRAM cells can be strengthened, and other effects similar to those of FIG.

[0088] 12A and 12B are plan views showing another example of the layout structure of the SRAM cell according to the first embodiment. Specifically, Fig. 12A shows the lower part of the cell, and Fig. 12B shows the upper part of the cell.

[0089] 12, compared to FIG. 9, power supply wiring 65 extending in the Y direction from both the upper and lower ends of the cell is formed in the M1 wiring layer.

[0090] The power supply wiring 65 is formed between the wirings 61 and 62 and supplies a power supply voltage VDD. The power supply wiring 65 overlaps with the power supply wiring 11 and the active regions P1 and P2 in plan view.

[0091] The power supply wiring 65 is connected to the portion that will become the source of the load transistor PU1 in the active region P1 through the via 57 and the local wiring 42. The power supply wiring 65 is connected to the portion that will become the source of the load transistor PU2 in the active region P2 through the via 58 and the local wiring 47.

[0092] 12, the power supply line 65 that supplies the power supply voltage VDD suppresses crosstalk noise between the lines 61 and 62 that correspond to the bit lines BLB and BL, respectively, thereby stabilizing the operation of the semiconductor memory device.

[0093] Furthermore, the power supply voltage VDD supplied to the SRAM cells can be strengthened by the power supply wiring 65. This makes it possible to improve the stability and speed of the operation of the semiconductor memory device.

[0094] In addition, the same effects as those in FIG. 9 can be obtained.

[0095] In FIG. 12, the power supply wiring 11 formed in the BM0 wiring layer for supplying the power supply voltage VDD may be omitted.

[0096] 13A and 13B are plan views showing an example of a layout structure of an SRAM cell according to a second embodiment. Specifically, Fig. 13A shows the upper part of the cell, and Fig. 13B shows the lower part of the cell.

[0097] In FIG. 13, wirings corresponding to bit lines are formed in the BM0 wiring layer, and power supply wirings are formed in the M1 wiring layer.

[0098] 13B, the BM0 wiring layer is formed with wirings 211 and 212 extending in the Y direction from the top to the bottom of the cell in the drawing. The wirings 211 and 212 correspond to the bit lines BLB and BL, respectively.

[0099] Active regions N3 and N4 are formed in the N-type transistor region. The active region N3 overlaps with the wiring 211 in plan view. The active region N4 overlaps with the wiring 212 in plan view.

[0100] In the N-type transistor region, access transistors PG1 and PG2 and drive transistors PD1 and PD2 are formed. The access transistor PG2, the drive transistors PD2 and PD1, and the access transistor PG1 each have nanosheets 221 to 224 extending in the Y direction.

[0101] In the active region N3, the portion that becomes the source of the access transistor PG2 is connected to the wiring 211 through a via 291 that is provided at a position that overlaps the wiring 211 in a plan view. In the active region N4, the portion that becomes the source of the access transistor PG1 is connected to the wiring 212 through a via 292 that is provided at a position that overlaps the wiring 212 in a plan view.

[0102] In the P-type transistor region, active regions P3 and P4 are formed.

[0103] In the P-type transistor region, load transistors PU1 and PU2 are formed. The load transistors PU1 and PU2 have nanosheets 225 and 226, respectively, that extend in the Y direction.

[0104] The width of the nanosheets 221 to 224 in the X direction is twice the width of the nanosheets 225 and 226 in the X direction.

[0105] Gate wirings 231 to 236 are formed extending in the X direction. The gate wiring 231 overlaps with the nanosheet 221 in a planar view. The gate wiring 232 overlaps with the nanosheet 225 in a planar view. The gate wiring 233 overlaps with the nanosheet 223 in a planar view. The gate wiring 234 overlaps with the nanosheet 222 in a planar view. The gate wiring 235 overlaps with the nanosheet 226 in a planar view. The gate wiring 236 overlaps with the nanosheet 224 in a planar view. The gate wiring 231 corresponds to the gate of the access transistor PG2. The gate wiring 232 corresponds to the gate of the load transistor PU1. The gate wiring 233 corresponds to the gate of the drive transistor PD1. The gate wiring 234 corresponds to the gate of the drive transistor PD2. The gate wiring 235 corresponds to the gate of the load transistor PU2. The gate wiring 236 corresponds to the gate of the access transistor PG1.

[0106] The nanosheets 221 to 226 are each covered by the gate wiring so that a portion of their outer peripheries is exposed. Specifically, the nanosheets 221, 222, and 225 have their right-hand surfaces in the X direction exposed from the gate wirings 231, 234, and 232, respectively, and their left-hand surfaces in the X direction covered by the gate wirings 231, 234, and 232, respectively. The nanosheets 223, 224, and 226 have their left-hand surfaces in the X direction exposed from the gate wirings 233, 236, and 235, respectively, and their right-hand surfaces in the X direction covered by the gate wirings 233, 236, and 235, respectively. That is, the nanosheets 222 (221) and 226 have their surfaces facing each other in the X direction exposed from the gate wirings 234 (231) and 235, respectively. The surfaces of the nanosheets 225, 223 (224) that face each other in the X direction are exposed from the gate wirings 232, 233 (236), respectively.

[0107] The gate wirings 232 and 233 are connected via a bridge portion 240a extending in the X direction. The gate wirings 234 and 235 are connected via a bridge portion 240b extending in the X direction.

[0108] Local interconnects 241 to 248 extending in the X direction are formed in the local interconnect layer. Local interconnect 241 is connected to a portion that serves as the source of access transistor PG2 in active region N3. Local interconnect 242 is connected to a portion that serves as the source of load transistor PU1 in active region P3. Local interconnect 243 is connected to a portion that serves as the source of drive transistor PD1 in active region N4. Local interconnect 244 is connected to a portion that serves as the drain of access transistor PG2 in active region N3, a portion that serves as the drain of drive transistor PD2 in active region N3, and a portion that serves as the drain of load transistor PU2 in active region P4. Local interconnect 245 is connected to a portion that serves as the drain of load transistor PU1 in active region P3, a portion that serves as the drain of drive transistor PD1 in active region N4, and a portion that serves as the drain of access transistor PG1 in active region N4. Local interconnect 246 is connected to a portion that serves as the source of drive transistor PD2 in active region N3. The local wiring 247 is connected to a portion that will become the source of the load transistor PU2 in the active region P4, and the local wiring 248 is connected to a portion that will become the source of the access transistor PG1 in the active region N4.

[0109] Local wiring 244 is connected to gate wiring 232 via shared contact 251. Local wiring 245 is connected to gate wiring 235 via shared contact 252. Gate wirings 234 and 235, bridge portion 240b, local wiring 245, and shared contact 252 correspond to a first node NA. Gate wirings 232 and 233, bridge portion 240a, local wiring 244, and shared contact 251 correspond to a second node NB.

[0110] As shown in FIG. 13A, power supply wiring 261-263 extending in the Y direction from the top to the bottom of the cell in the drawing are formed in the M1 wiring layer. Wiring 264 and 265 are also formed. Power supply wiring 261 supplies a power supply voltage VDD. Power supply wiring 262 and 263 supply a power supply voltage VSS. Power supply wiring 261 overlaps with active regions P3 and P4 in a planar view. Power supply wiring 262 overlaps with active region N3 and wiring 211 in a planar view. Power supply wiring 263 overlaps with active region N4 and wiring 212 in a planar view.

[0111] The power supply wiring 261 is connected to the local wiring 242 through a via 253. The power supply wiring 261 is connected to the local wiring 247 through a via 254. The power supply wiring 262 is connected to the local wiring 246 through a via 255. The power supply wiring 263 is connected to the local wiring 243 through a via 256.

[0112] In the M2 wiring layer, a wiring 271 extending in the X direction from the left to the right ends of the cell in the drawing and power supply wirings 272 and 273 are formed. The wiring 271 is formed in the center of the cell in the Y direction in the drawing and corresponds to the word line WL. The power supply wiring 272 is formed at the upper end of the cell in the Y direction in the drawing and supplies the power supply voltage VSS. The power supply wiring 273 is formed at the lower end of the cell in the Y direction in the drawing and supplies the power supply voltage VSS. The power supply wiring 272 is shared with other cells arranged above in the drawing. The power supply wiring 273 is shared with other cells arranged below in the drawing.

[0113] Wiring 271 is connected to gate wiring 231 via via 281, wiring 264, and via 257. Wiring 271 is connected to gate wiring 236 via via 282, wiring 265, and via 258. Power supply wiring 272 is connected to power supply wiring 262 via via 283, and is connected to power supply wiring 263 via via 284. Power supply wiring 273 is connected to power supply wiring 262 via via 285, and is connected to power supply wiring 263 via via 286.

[0114] With the above configuration, wirings 211 and 212 corresponding to the bit lines BLB and BL, respectively, are formed in the BM0 wiring layer, which is the wiring layer on the back surface of the transistor. A power supply wiring 261 that supplies a power supply voltage VDD and power supply wirings 262 and 263 that supply a power supply voltage VSS are formed in the M1 wiring layer, which is the metal wiring layer above the transistor. As a result, the only wirings formed in the BM0 wiring layer are the bit lines BLB and BL. Therefore, the wiring widths of the wirings 211 and 212 corresponding to the bit lines BLB and BL, respectively, formed in the BM0 wiring layer can be increased, thereby reducing the wiring resistance of the bit lines. Furthermore, the wiring 211 overlaps the active region N3 in a planar view and is connected to each other by a via 291 provided in the overlapping region. The wiring 212 overlaps the active region N4 in a planar view and is connected to each other by a via 292 provided in the overlapping region. Therefore, since the active region and the bit lines can be arranged to overlap, the wiring widths of the lines 211 and 212 corresponding to the bit lines BLB and BL, respectively, can be increased, thereby reducing the wiring resistance of the bit lines. This improves the operating speed of the semiconductor memory device. Furthermore, since it is no longer necessary to form lines corresponding to the bit lines BLB and BL in the M1 wiring layer, the wiring widths of the power supply line 261 that supplies the power supply voltage VDD and the power supply lines 262 and 263 that supply the power supply voltage VSS in the M1 wiring layer can be increased. This reduces the wiring resistance of the power supply lines, thereby suppressing fluctuations in the power supply voltage and improving the operating speed and stability of the semiconductor memory device. Furthermore, increasing the wiring widths of the power supply lines 261 to 263 reduces the wiring resistance of the lines that supply the power supply voltages VDD and VSS, thereby improving the operating stability, particularly the retention characteristics (static noise margin) of the SRAM cells.

[0115] Furthermore, the surfaces of the nanosheets 222 (221) and 226 that face each other in the X direction are exposed from the gate wirings 234 (231) and 235, respectively. The surfaces of the nanosheets 225 and 223 (224) that face each other in the X direction are exposed from the gate wirings 232 and 233 (236), respectively. This reduces the distance d1 in the X direction between the drive transistor PD2 (access transistor PG2) and the load transistor PU2, and the distance d1 in the X direction between the load transistor PU1 and the drive transistor PD1 (access transistor PG1). This allows the area of ​​the semiconductor memory device to be reduced.

[0116] 14A and 14B are plan views showing another example of the layout structure of the SRAM cell according to the second embodiment. Specifically, Fig. 14A shows the upper part of the cell, and Fig. 14B shows the lower part of the cell.

[0117] In FIG. 14, compared to FIG. 13, a power supply wiring 213 extending in the Y direction from both the upper and lower ends of the cell is formed in the BM0 wiring layer.

[0118] The power supply wiring 213 is formed between the wirings 211 and 212 and supplies a power supply voltage VDD. The power supply wiring 213 overlaps with the power supply wiring 261 and the active regions P3 and P4 in a planar view. The power supply wiring 213 is connected to a portion of the active region P3 that will become the source of the load transistor PU1 via a via 293 provided at a position where the power supply wiring 213 overlaps with the active region P3 and P4 in a planar view. The power supply wiring 213 is connected to a portion of the active region P4 that will become the source of the load transistor PU2 via a via 294 provided at a position where the power supply wiring 213 overlaps with the active region P3 and P4 in a planar view.

[0119] 14, the power supply wiring 213 that supplies the power supply voltage VDD suppresses crosstalk noise between the wirings 211 and 212 that correspond to the bit lines BLB and BL, respectively, thereby stabilizing the operation of the semiconductor memory device.

[0120] Furthermore, the power supply voltage VDD supplied to the SRAM cells can be strengthened by the power supply wiring 213. This makes it possible to improve the stability and speed of the operation of the semiconductor memory device.

[0121] In addition, the same effects as those in FIG. 13 can be obtained.

[0122] In FIG. 14, the power supply wiring 261 formed in the M1 wiring layer for supplying the power supply voltage VDD may be omitted.

[0123] 15A and 15B are plan views showing another example of the layout structure of the SRAM cell according to the second embodiment. Specifically, Fig. 15A shows the upper part of the cell, and Fig. 15B shows the lower part of the cell.

[0124] In FIG. 15, compared to FIG. 13, the surfaces of the nanosheets 221 to 226 opposite to the X direction are exposed from the gate wiring.

[0125] As shown in FIG. 15( b), the gate wiring 231 overlaps with the nanosheet 221 in a planar view. The gate wiring 233 overlaps with the nanosheets 225 and 223 in a planar view. The gate wiring 234 overlaps with the nanosheets 222 and 226 in a planar view. The gate wiring 236 overlaps with the nanosheet 224 in a planar view. The gate wiring 231 corresponds to the gate of the access transistor PG2. The gate wiring 233 corresponds to the gates of the load transistor PU1 and the drive transistor PD1. The gate wiring 234 corresponds to the gates of the drive transistor PD2 and the load transistor PU2. The gate wiring 236 corresponds to the gate of the access transistor PG1.

[0126] Nanosheets 221 to 226 are each covered by the gate wiring so that a portion of their outer peripheries is exposed. Specifically, nanosheets 223, 224, and 226 have their right-hand surfaces in the X direction exposed from gate wirings 233, 236, and 234, respectively, and their left-hand surfaces in the X direction covered by gate wirings 233, 236, and 234, respectively. Nanosheets 221, 222, and 225 have their left-hand surfaces in the X direction exposed from gate wirings 231, 234, and 233, respectively, and their right-hand surfaces in the X direction covered by gate wirings 231, 234, and 233, respectively. That is, nanosheets 225 and 226 have their surfaces facing each other in the X direction exposed from gate wirings 233 and 234, respectively.

[0127] Nanosheets 221 and 222 are arranged close to the cell boundary on the left side of the drawing. Nanosheets 223 and 224 are arranged close to the cell boundary on the right side of the drawing. In the SRAM cell of FIG. 15 , SRAM cells inverted in the X direction are arranged on both the left and right sides of the drawing. That is, in the SRAM cells arranged in the X direction, the surfaces of nanosheets 221 facing each other in the X direction are exposed from gate wiring 231. Similarly, the surfaces of nanosheets 222 facing each other in the X direction are exposed from gate wiring 234. The surfaces of nanosheets 223 facing each other in the X direction are exposed from gate wiring 233. The surfaces of nanosheets 224 facing each other in the X direction are exposed from gate wiring 236.

[0128] Gate wirings 232 and 233 are connected via bridge portion 240c extending in the X direction. Gate wirings 234 and 235 are connected via bridge portion 240d extending in the X direction. Gate wiring 231 is connected to gate wiring 231 located on the left side of the SRAM cell in the drawing via bridge portion 240e extending in the X direction. Gate wiring 236 is connected to gate wiring 236 located on the right side of the SRAM cell in the drawing via bridge portion 240f extending in the X direction.

[0129] The wiring 271 corresponding to the word line WL is connected to the gate wiring 231 through a via 281, a wiring 264, a via 257, and a bridge portion 240e. The wiring 271 is connected to the gate wiring 236 through a via 282, a wiring 265, a via 258, and a bridge portion 240f.

[0130] 15, the surfaces of the nanosheets 225 and 226 that face each other in the X direction are exposed from the gate wirings 233 and 234. This makes it possible to reduce the distance d1 in the X direction between the load transistors PU1 and PU2.

[0131] Furthermore, in the SRAM cells aligned in the X direction, the surfaces of the nanosheets 221 facing each other in the X direction are exposed from the gate wiring 231. Similarly, the surfaces of the nanosheets 222 facing each other in the X direction are exposed from the gate wiring 234. The surfaces of the nanosheets 223 facing each other in the X direction are exposed from the gate wiring 233. The surfaces of the nanosheets 224 facing each other in the X direction are exposed from the gate wiring 236. This makes it possible to reduce the distance d1 in the X direction between the access transistors PG2, the distance d1 in the X direction between the drive transistors PD2, the distance d1 in the X direction between the drive transistors PD1, and the distance d1 in the X direction between the access transistors PG1 in the SRAM cells aligned in the X direction. This allows for a reduction in the area of ​​the semiconductor memory device.

[0132] In addition, the same effects as those in FIG. 13 can be obtained.

[0133] 16A and 16B are plan views showing another example of the layout structure of the SRAM cell according to the second embodiment. Specifically, Fig. 16A shows the upper part of the cell, and Fig. 16B shows the lower part of the cell.

[0134] In FIG. 16, compared to FIG. 15, a power supply wiring 213 extending in the Y direction from both the upper and lower ends of the cell is formed in the BM0 wiring layer.

[0135] The power supply wiring 213 is formed between the wirings 211 and 212 and supplies a power supply voltage VDD. The power supply wiring 213 overlaps with the power supply wiring 261 and the active regions P3 and P4 in a planar view. The power supply wiring 213 is connected to a portion of the active region P3 that will become the source of the load transistor PU1 via a via 293 provided at a position where the power supply wiring 213 overlaps with the active region P3 and P4 in a planar view. The power supply wiring 213 is connected to a portion of the active region P4 that will become the source of the load transistor PU2 via a via 294 provided at a position where the power supply wiring 213 overlaps with the active region P3 and P4 in a planar view.

[0136] 16, the power supply wiring 213 that supplies the power supply voltage VDD suppresses crosstalk noise between the wirings 211 and 212 that correspond to the bit lines BLB and BL, respectively, thereby stabilizing the operation of the semiconductor memory device.

[0137] Furthermore, the power supply voltage VDD supplied to the SRAM cells can be strengthened by the power supply wiring 213. This improves the operational stability and operating speed of the semiconductor memory device.

[0138] In addition, the same effects as those in FIG. 15 can be obtained.

[0139] In FIG. 16, the power supply wiring 261 formed in the M1 wiring layer for supplying the power supply voltage VDD may be omitted.

[0140] In the above-described embodiments and variants, each transistor has three nanosheets, but some or all of the transistors may have one, two, or four or more nanosheets.

[0141] In addition, in the above-described embodiments and modifications, the cross-sectional shape of the nanosheet is rectangular, but this is not limited to this and may be, for example, square, circular, elliptical, or the like.

[0142] In the first embodiment and the modified example described above, the width in the X direction of the nanosheets 21 to 24 is twice the width in the X direction of the nanosheets 25 and 26, but this is not limited to this. The width in the X direction of each of the nanosheets 21 to 26 may be determined taking into consideration the operational stability of the SRAM circuit, etc.

[0143] In the second embodiment and the modified example described above, the width in the X direction of the nanosheets 221 to 224 is twice the width in the X direction of the nanosheets 225 and 226, but this is not limited to this. The width in the X direction of each of the nanosheets 221 to 226 may be determined taking into consideration the operational stability of the SRAM circuit, etc.

[0144] In addition, in each of the above-described embodiments and modifications, the shared contacts 51, 52, 251, 252 may be manufactured in the same process as the contacts (gate-contacts) and local wiring, or may be manufactured in a separate process.

[0145] Furthermore, in each of the above-described embodiments and variations, the power supply that supplies the power supply voltage VDD to the sources of the load transistors PU1 and PU2 is not limited to a power supply supplied from outside the semiconductor integrated circuit, but may be a power supply generated inside the semiconductor integrated circuit or a power supply generated inside the semiconductor memory device.

[0146] In the present disclosure, the operating speed of a semiconductor memory device is improved in a layout structure of an SRAM cell.

[0147] 11-13, 65, 72, 73, 121-123, 213, 261-263, 272, 273 Power supply wiring 91-94, 291-294 Vias 21-26, 221-226 Nanosheets 31-36, 231-236 Gate wiring 40a-40f, 240a-240f Bridge section 61, 62, 211, 212 Wiring PU1, PU2 Load transistor PD1, PD2 Drive transistor PG1, PG2 Access transistor BL, BLB Bit line WL Word line

Claims

1. A semiconductor memory device including an SRAM cell, wherein the SRAM cell comprises: a first transistor having a source connected to a first power supply that supplies a first power supply voltage, a drain connected to a first node, and a gate connected to a second node; a second transistor having a source connected to the first power supply, a drain connected to the second node, and a gate connected to the first node; a third transistor having a source connected to a second power supply that supplies a second power supply voltage different from the first power supply voltage, a drain connected to the first node, and a gate connected to the second node; a fourth transistor having a source connected to the second power supply, a drain connected to the second node, and a gate connected to the first node; a fifth transistor having a source connected to a first bit line, a drain connected to the first node, and a gate connected to a word line; and a sixth transistor having a source connected to a second bit line that forms a complementary bit line pair with the first bit line, a drain connected to the second node, and a gate connected to the word line, wherein the SRAM cell comprises: a first active region constituting the channel, source, and drain of the fourth transistor, the channel being a fourth nanosheet extending in a first direction, and constituting the channel, source, and drain of the sixth transistor, the channel being a sixth nanosheet extending in the first direction; a second active region constituting the channel, source, and drain of the third transistor, the channel being a third nanosheet extending in the first direction, and constituting the channel, source, and drain of the fifth transistor, the channel being a fifth nanosheet extending in the first direction; a third active region constituting the channel, source, and drain of the first transistor, the channel being a first nanosheet extending in the first direction; a fourth active region constituting the channel, source, and drain of the second transistor, the channel being a second nanosheet extending in the first direction; first to sixth gate wirings surrounding the first to sixth nanosheets in a second direction perpendicular to the first direction and in a depth direction perpendicular to the first and second directions, respectively;a first via formed in a region where a region that becomes a source of the fourth transistor in the first active region overlaps with the first power supply wiring, connecting the source of the fourth transistor in the first active region with the first power supply wiring; and a second via formed in a region where a region that becomes a source of the third transistor in the second active region overlaps with the second power supply wiring, connecting the source of the third transistor in the second active region with the second power supply wiring; wherein the first, fourth, and sixth nanosheets have first-side surfaces that are one side in the second direction and are exposed from the first, fourth, and sixth gate wirings, respectively; and the second, third, and fifth nanosheets have second-side surfaces that are the other side in the second direction and are exposed from the second, third, and fifth gate wirings, respectively.

2. A semiconductor memory device according to claim 1, wherein the SRAM cell is formed in a second back wiring layer below the first back wiring layer, extends in the second direction, and includes a third power supply wiring for supplying the second power supply voltage, the third power supply wiring being connected to the first and second power supply wirings.

3. A semiconductor memory device according to claim 1, wherein the SRAM cell comprises: a fourth power supply wiring formed in the first backside wiring layer, extending in the first direction, and supplying the first power supply voltage; a third via formed in a region in the third active region where a region serving as the source of the first transistor overlaps with the fourth power supply wiring, connecting the source of the first transistor in the third active region with the fourth power supply wiring; and a fourth via formed in a region in the fourth active region where a region serving as the source of the second transistor overlaps with the fourth power supply wiring, connecting the source of the second transistor in the fourth active region with the fourth power supply wiring.

4. A semiconductor memory device according to claim 3, wherein the SRAM cell is formed in a second back wiring layer below the first back wiring layer, extends in the second direction, and includes a fifth power supply wiring for supplying the first power supply voltage, the fifth power supply wiring being connected to the fourth power supply wiring.

5. A semiconductor memory device according to claim 3, wherein the SRAM cell comprises: a third power supply wiring formed in a second back wiring layer below the first back wiring layer, extending in the second direction, and supplying the second power supply voltage; and a fifth power supply wiring formed in the second back wiring layer, extending in the second direction, and supplying the first power supply voltage, wherein the third power supply wiring is formed at one end of the SRAM cell in the first direction and is connected to the first and second power supply wirings; and the fifth power supply wiring is formed at the other end of the SRAM cell in the first direction and is connected to the fourth power supply wiring.

6. A semiconductor memory device according to claim 1, wherein a sixth power supply wiring extending in the first direction and supplying the first power supply voltage is formed in a metal wiring layer above the first to sixth transistors, and the sixth power supply wiring is connected to the source of the first transistor and the source of the second transistor.

7. A semiconductor memory device according to claim 1, wherein the SRAM cell comprises: a fourth power supply wiring formed in the first backside wiring layer, extending in the first direction and supplying the first power supply voltage; a third via formed in a region in the third active region where a region serving as the source of the first transistor overlaps with the fourth power supply wiring and connecting the source of the first transistor in the third active region to the fourth power supply wiring; and a fourth via formed in a region in the fourth active region where a region serving as the source of the second transistor overlaps with the fourth power supply wiring and connecting the source of the second transistor in the fourth active region to the fourth power supply wiring; and a sixth power supply wiring extending in the first direction and supplying the first power supply voltage is formed in a metal wiring layer above the first to sixth transistors, and the sixth power supply wiring is connected to the source of the first transistor and the source of the second transistor.

8. A semiconductor memory device according to claim 1, wherein the first bit line is formed in a metal wiring layer above the first to sixth transistors and includes a first wiring extending in the first direction, and the second bit line is formed in the metal wiring layer and includes a second wiring extending in the first direction.

9. A semiconductor memory device according to claim 1, wherein the fourth and sixth nanosheets are arranged side by side in the first direction, and the third and fifth nanosheets are arranged side by side in the first direction.

10. A semiconductor memory device according to claim 1, wherein the first, third and sixth nanosheets are formed in the second direction in the order of the sixth, first and third nanosheets, and the second, fourth and fifth nanosheets are formed in the second direction in the order of the fourth, second and fifth nanosheets.

11. A semiconductor memory device including an SRAM cell, wherein the SRAM cell comprises: a first transistor having a source connected to a first power supply that supplies a first power supply voltage, a drain connected to a first node, and a gate connected to a second node; a second transistor having a source connected to the first power supply, a drain connected to the second node, and a gate connected to the first node; a third transistor having a source connected to a second power supply that supplies a second power supply voltage different from the first power supply voltage, a drain connected to the first node, and a gate connected to the second node; a fourth transistor having a source connected to the second power supply, a drain connected to the second node, and a gate connected to the first node; a fifth transistor having a source connected to a first bit line, a drain connected to the first node, and a gate connected to a word line; and a sixth transistor having a source connected to a second bit line that forms a complementary bit line pair with the first bit line, a drain connected to the second node, and a gate connected to the word line, the first bit line is formed in a first back wiring layer on the back side of the first to sixth transistors and includes a first wiring extending in a first direction; the second bit line is formed in the first back wiring layer and includes a second wiring extending in the first direction; the SRAM cell comprises: a first active region constituting the channel, source, and drain of the fourth transistor, the channel including a fourth nanosheet extending in the first direction as the channel, and a sixth nanosheet constituting the channel, source, and drain of the sixth transistor, the channel including a sixth nanosheet extending in the first direction as the channel; a second active region constituting the channel, source, and drain of the third transistor, the channel including a third nanosheet extending in the first direction as the channel, and a fifth nanosheet extending in the first direction as the channel; and a third active region constituting the channel, source, and drain of the first transistor, the channel including a first nanosheet extending in the first direction as the channel.a fourth active region constituting the channel, source, and drain of the second transistor, the channel including a second nanosheet extending in the first direction; first to sixth gate wirings surrounding the first to sixth nanosheets in a second direction perpendicular to the first direction and in a depth direction perpendicular to the first and second directions, respectively; a first via formed in a region in the first active region where a region serving as the source of the sixth transistor and the second wiring overlap, connecting the source of the sixth transistor in the first active region to the second wiring; and a second via formed in a region in the second active region where a region serving as the source of the fifth transistor and the first wiring overlap, connecting the source of the fifth transistor in the second active region to the first wiring, wherein the first, fourth, and sixth nanosheets have first side surfaces, which are one side in the second direction, exposed from the first, fourth, and sixth gate wirings, The second, third and fifth nanosheets have second-side surfaces, which are the other side in the second direction, exposed from the second, third and fifth gate wirings, respectively.

12. A semiconductor memory device according to claim 11, wherein first and second power supply wirings extending in the first direction and supplying the second power supply voltage are formed in a metal wiring layer above the first to sixth transistors, the first power supply wiring being connected to the source of the third transistor, and the second power supply wiring being connected to the source of the fourth transistor.

13. A semiconductor memory device according to claim 11, wherein a third power supply wiring extending in the first direction and supplying the first power supply voltage is formed in a metal wiring layer above the first to sixth transistors, and the third power supply wiring is connected to the source of the first transistor and the source of the second transistor.

14. A semiconductor memory device according to claim 11, wherein the SRAM cell comprises: a fourth power supply wiring formed in the first backside wiring layer, extending in the first direction, and supplying the first power supply voltage; a third via formed in a region in the third active region where a region serving as the source of the first transistor overlaps with the fourth power supply wiring, connecting the source of the first transistor in the third active region with the fourth power supply wiring; and a fourth via formed in a region in the fourth active region where a region serving as the source of the second transistor overlaps with the fourth power supply wiring, connecting the source of the second transistor in the fourth active region with the fourth power supply wiring.

15. A semiconductor memory device according to claim 11, wherein a third power supply wiring extending in the first direction and supplying the first power supply voltage is formed in a metal wiring layer above the first to sixth transistors, the third power supply wiring being connected to the source of the first transistor and the source of the second transistor; and the SRAM cell comprises: a fourth power supply wiring formed in the first backside wiring layer, extending in the first direction and supplying the first power supply voltage; a third via formed in a region in the third active region where the region serving as the source of the first transistor overlaps with the fourth power supply wiring, connecting the source of the first transistor in the third active region with the fourth power supply wiring; and a fourth via formed in a region in the fourth active region where the region serving as the source of the second transistor overlaps with the fourth power supply wiring, connecting the source of the second transistor in the fourth active region with the fourth power supply wiring.

16. A semiconductor memory device according to claim 11, wherein the fourth and sixth nanosheets are arranged side by side in the first direction, and the third and fifth nanosheets are arranged side by side in the first direction.

17. A semiconductor memory device according to claim 11, wherein the first, third and sixth nanosheets are formed in the second direction in the order of the sixth, first and third nanosheets, and the second, fourth and fifth nanosheets are formed in the second direction in the order of the fourth, second and fifth nanosheets.

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