Display device and display system

Abstract

The present invention provides a display device and a display system capable of reducing deterioration in image quality as compared with a prior art. A display device (3) for modulating and projecting light from a light source (39) on the basis of an inputted input signal includes a first arithmetic circuit (31) for executing a first dithering process on an input signal (Sin) and generating and outputting a first signal (S1); a second arithmetic circuit (32) for executing a second dithering process on the first signal and generating and outputting a second signal (S2); a light source for generating light; and a digital mirror device (DMD) (40) for modulating the light from the light source on the basis of the second signal and generating video light.

Description

Display device and display system

[0001] The present disclosure relates to a display device and a display system.

[0002] Conventionally, dithering has been used as a method for displaying gradations beyond those limited by hardware resources or software constraints. For example, Patent Document 1 discloses an image processing device that uses dithering to display good halftone images by preventing the generation of patterns with high resolution that are visually perceived by humans, such as fixed patterns.

[0003] Japanese Patent Application Laid-Open No. 2003-338929

[0004] Applying dithering to increase the tonal range can result in a decrease in image quality.

[0005] An object of the present disclosure is to provide a display device and a display system that can reduce degradation in image quality compared to conventional techniques.

[0006] A display device according to one aspect of the present disclosure is a display device that modulates and projects light from a light source based on an input signal, and is characterized by comprising: a first arithmetic circuit that performs a first dithering process on the input signal to generate and output a first signal; a second arithmetic circuit that performs a second dithering process on the first signal to generate and output a second signal; the light source that generates light; and a digital mirror device (DMD) that modulates the light from the light source based on the second signal to generate image light.

[0007] According to the present disclosure, it is possible to provide a display device and a display system that can reduce degradation in image quality compared to conventional techniques.

[0008] 8C 。 Schematic diagram of a display system according to an embodiment. Schematic diagram of a control device according to an embodiment. Schematic diagram of a display device according to an embodiment. A diagram showing the signal level of pixels in the Nth frame of an input signal received from the control device. A diagram showing the signal levels of pixels in multiple sub-frames corresponding to the Nth frame in a signal after dithering processing. A diagram showing the signal levels of pixels in the Nth frame perceived by the eye when viewing an image projected with the signal shown in FIG. 4B. A flowchart showing an example of processing executed by a first arithmetic circuit. A flowchart showing an example of processing executed by a second arithmetic circuit. A block diagram showing the flow of signals in a display device according to an embodiment. A diagram showing the signal level of pixels in the Nth frame of an input signal. A diagram showing the signal levels of pixels in multiple sub-frames in a first signal corresponding to the Nth frame of the input signal. A diagram showing the signal levels of pixels in multiple sub-subframes in a second signal corresponding to the Nth frame of the input signal. A diagram showing the signal levels of pixels in multiple sub-frames obtained by time-integrating an image projected based on the second signal shown in FIG. 8C. A diagram showing the signal levels of pixels in the Nth frame that can be perceived by the human eye when viewing the image shown in FIG. 8D. A diagram showing the signal levels of pixels in the Nth frame of an input signal. 9C , a diagram showing pixel signal levels of a plurality of subframes in a first signal corresponding to the Nth frame in the input signal; a diagram showing pixel signal levels of a plurality of subframes obtained by time-integrating an image projected based on the generated second signal; a diagram showing pixel signal levels of the Nth frame that can be recognized by the human eye when the image shown in FIG. 9C is viewed by the human eye; a diagram showing pixel signal levels of the Nth frame and the N+1th frame in the input signal; a diagram showing pixel signal levels of the Nth frame and the N+1th frame in the first signal; a diagram showing pixel signal levels of the Nth frame and the N+1th frame obtained by time-integrating an image projected based on the generated second signal; a diagram showing pixel signal levels of the kth frame that can be recognized by the human eye when the image shown in FIG. 10C is viewed by the human eye; a diagram showing pixel signal levels of the Nth frame in the input signal; a diagram showing pixel signal levels of the Nth frame in the first signal; a diagram showing pixel signal levels of the Nth frame in the Nth frameFig. 11D is a diagram showing the signal levels of pixels in the Nth frame that can be recognized when the image shown in Fig. 11C is viewed by the human eye. Fig. 11D is a schematic diagram of a display device according to a modified example.

[0009] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. However, the configurations described below are merely examples of the present disclosure, and the present disclosure is not limited to the following embodiments. The technology in the present disclosure is not limited to these embodiments, and various modifications, substitutions, additions, omissions, etc. are possible depending on the design, etc., as long as they do not deviate from the technical concept of the present disclosure.

[0010] Although the present disclosure has been fully described in connection with the preferred embodiments with reference to the accompanying drawings, various changes and modifications will be apparent to those skilled in the art, and such changes and modifications are to be understood as included within the scope of the present disclosure as defined by the appended claims unless they depart therefrom.

[0011] In the present disclosure, when describing comparative examples or modified examples, differences from the embodiments will be mainly described. In this case, components in the comparative examples or modified examples that are the same as or equivalent to those in the embodiments will be described using the same reference numerals. Furthermore, descriptions that overlap with the embodiments may be omitted in the comparative examples or modified examples.

[0012] Conventionally, in display devices, when the number of gradations that can be processed by the display device's arithmetic circuit is limited due to hardware resource or software constraints, dithering has been used as a method for displaying gradations greater than or equal to the number of gradations that can be processed. For example, when the number of bits that can be output as an output signal from the display device's arithmetic circuit is limited, the arithmetic circuit can achieve gradations greater than the number of bits that can be output by dithering, by processing the signal at a higher frequency while reducing the number of bits compared to the input signal. However, when dithering is applied to a display signal to increase gradations, the dithering may cause degradation of the image quality of the projected image. For example, when a person views the projected image, flickering may be noticeable in the projected image due to temporal dithering. Hereinafter, flickering in the projected image is also referred to as dither noise. In the present disclosure, degradation of image quality may include the occurrence of dither noise. Furthermore, in the present disclosure, dither noise may include the occurrence of a predetermined pattern in the projected image due to dithering.

[0013] Dither noise can be reduced by subdividing the dithering pattern or by using feedback control to evaluate the dither noise. However, subdividing the pattern or using feedback control can increase costs and processing time due to increased processing load. Dither noise can also be reduced by changing the content of the dithering process. However, due to limitations in hardware resources or software, it may be difficult to change the content (e.g., pattern, number of bits, frequency, etc.) of the dithering process performed by the arithmetic circuit to generate an output signal corresponding to the image projected from the optical mechanism.

[0014] A display device according to the present disclosure includes a first arithmetic circuit and a second arithmetic circuit. The first arithmetic circuit performs a first dithering process on an input signal to generate a first signal. The second arithmetic circuit performs a second dithering process on the first signal to generate a second signal. The display device then modulates light from a light source based on the second signal to generate image light and project an image.

[0015] In this way, the display device according to the present disclosure can perform different dithering processes using two arithmetic circuits. Even if the second arithmetic circuit can only perform a specific dithering process due to hardware resource or software constraints, the display device can include additional dithering processes in the projected image by performing a dithering process using the first arithmetic circuit. Therefore, the display device can reduce the occurrence of dithering noise by performing a different dithering process in response to the dithering noise that may be generated by performing the specific dithering process. Performing two dithering processes using two arithmetic circuits is less costly than using pattern subdivision or feedback control, and can also reduce the processing load. Therefore, the display device according to the present disclosure can reduce degradation in the image quality of the projected image while suppressing increases in cost or processing time.

[0016] (Embodiment) [1-1. Configuration] A display system 1 according to an embodiment of the present disclosure will be described with reference to FIG. 1. FIG. 1 is a schematic diagram of the display system 1 according to an embodiment of the present disclosure. The display system 1 includes a control device 2 and a display device 3. The control device 2 is, for example, an information processing device such as a computer. The display device 3 is, for example, a DLP projector. The display device 3 may be a one-chip DLP projector or a three-chip DLP projector. The control device 2 and the display device 3 are connected via a cable 4. The display device 3 displays an image by projecting a video signal received from the control device 2 via the cable 4 onto a screen 5.

[0017] The control device 2 can transmit a control signal to the display device 3 via the cable 4. The control signal may include a signal for controlling the display device 3. The control device 2 may also transmit an audio signal to the display device 3 via the cable 4. Furthermore, the display device 3 can transmit a control signal to the control device 2 via the cable 4. The control signal may include a resolution and a frame rate that the display device 3 can display. For example, the cable 4 complies with standards such as HDMI (High-Definition Multimedia Interface) (registered trademark) and SDI (Serial Digital Interface).

[0018] 2 is a schematic diagram of a control device 2 according to an embodiment of the present disclosure. The control device 2 includes an arithmetic circuit 21, a storage device 22, an input / output device 23, a communication circuit 24, a receiving circuit 25, and a transmitting circuit 26.

[0019] The arithmetic circuit 21 controls the overall operation of the control device 2. The arithmetic circuit 21 may be configured to realize a predetermined function through cooperation between hardware resources and software, or may be configured to realize a predetermined function using a dedicated hardware circuit.

[0020] As an example of the former, the arithmetic circuit 21 includes a general-purpose processor such as a CPU or MPU that executes a program to achieve predetermined processing or functions. The arithmetic circuit 21 is configured to be able to communicate with the storage device 22. The arithmetic circuit 21 reads and executes arithmetic programs stored in the storage device 22, thereby achieving various functions in the control device 2. As an example of the latter, the arithmetic circuit 21 includes an FPGA or an ASIC. As can be understood from the above, the arithmetic circuit 21 can be achieved using a semiconductor integrated circuit such as a CPU, MPU, GPU, FPGA, DSP, or ASIC.

[0021] The storage device 22 is a storage medium capable of storing various information. The information includes programs and data. For example, the storage device 22 stores an arithmetic program for implementing various functions according to the present embodiment. The storage device 22 is realized, for example, by a volatile or non-volatile semiconductor memory such as a DRAM, an SRAM, or a flash memory, an SSD, an HDD, or other storage device, or an appropriate combination thereof. The data includes, for example, content such as video.

[0022] The input / output device 23 functions as an input device for inputting information from a user and as an output device for outputting information to a user. The input / output device 23 includes one or more human-machine interface devices. The human-machine interface devices include input devices such as a keyboard, a pointing device (a mouse, a trackball, etc.), and a touchpad, and output devices such as a display and a speaker. The human-machine interface devices also include input / output devices such as a display (e.g., a liquid crystal panel or an organic EL panel) equipped with an in-cell touch panel.

[0023] The communication circuit 24 is a communication interface device for connecting to other devices or systems via a communication line, either wired or wirelessly. The communication interface device is capable of performing communication in accordance with wired communication standards such as USB (registered trademark) or Ethernet (registered trademark). The communication interface device is also capable of performing communication in accordance with wireless communication standards such as Wi-Fi (registered trademark), Bluetooth (registered trademark), and mobile phone lines.

[0024] The receiving circuit 25 is an interface device configured to receive data from an external device (not shown). The transmitting circuit 26 is an interface device that enables data transmission to an external device (e.g., the display device 3). The control device 2 can receive and transmit video signals, audio signals, and control signals from and to the external device using the receiving circuit 25 and the transmitting circuit 26. As described above, data communication with external devices such as the display device 3 complies with standards such as HDMI and SDI. The arithmetic circuit 21 can transmit video signals, audio signals, and control signals to the display device 3 via the transmitting circuit 26.

[0025] 3 is a schematic diagram of a display device 3 according to an embodiment of the present disclosure. The display device 3 includes a first arithmetic circuit 31, a second arithmetic circuit 32, a storage device 33, an input / output device 34, a communication circuit 35, a receiving circuit 36, a transmitting circuit 37, and an optical mechanism 38. The first arithmetic circuit 31, the storage device 33, the input / output device 34, the communication circuit 35, the receiving circuit 36, and the transmitting circuit 37 can be realized by the same specific means as the arithmetic circuit 21, the storage device 22, the input / output device 23, the communication circuit 24, the receiving circuit 25, and the transmitting circuit 26 described above.

[0026] The first arithmetic circuit 31 has a function of applying predetermined dithering to the signal received from the control device 2. The first arithmetic circuit 31 may control the overall operation of the display device 3. The display device 3 may further include an arithmetic circuit that controls the overall operation of the display device 3. The first arithmetic circuit 31 can be realized by the same specific means as the arithmetic circuit 21.

[0027] The second arithmetic circuit 32 has a function of applying a specific dithering to the signal acquired from the first arithmetic circuit 31, which is different from the dithering performed by the first arithmetic circuit 31. The second arithmetic circuit 32 may realize a predetermined function using a dedicated hardware circuit. The second arithmetic circuit 32 may be, for example, an ASIC.

[0028] The optical mechanism 38 is a mechanism for displaying an image. The optical mechanism 38 includes a light source 39 that generates light, such as a laser diode, an LED, or a lamp, and an optical unit 40. The optical unit 40 may include multiple optical elements. The optical unit 40 includes a light modulation element that modulates light emitted from the light source, an arithmetic circuit that drives the light modulation element, and a projection lens system that guides the image light modulated by the light modulation element to the projection surface. In this embodiment, the optical unit 40 includes a digital mirror device (DMD) as the light modulation element. The display device 3 displays an image on the screen 5 by modulating light from the light source 39 using the optical unit 40 (specifically, the DMD) based on a video signal input from the control device 2 and projecting the modulated light.

[0029] In this embodiment, when the display device 3 receives a video signal as an input signal, the first arithmetic circuit 31 is configured to perform a first dithering process (details of which will be described later) on the input signal. The display device 3 is also configured to further perform a second dithering process (details of which will be described later) on the input signal that has already undergone the first dithering process. The first arithmetic circuit 31 is configured to perform the first dithering process on the input signal to generate a first signal, and output the first signal to the second arithmetic circuit 32. The second arithmetic circuit 32 is also configured to perform a second dithering process, different from the first dithering process, on the first signal to output a second signal to the optical unit 40. The optical unit 40 operates multiple mirror panels included in the DMD based on the received second signal, modulating and projecting light from the light source 39.

[0030] [1-2. Operation] Before describing the outline of the operation of the display system 1 according to this embodiment, the outline of the operation of a display system according to a comparative example will be described, and then the outline of the operation of the display system 1 according to this embodiment will be described. Figures 4A to 4C are diagrams showing changes in pixel signal levels in an example of display processing according to the comparative example. The signal level indicates, for example, luminance information of the pixel.

[0031] The display process according to the comparative example is executed by a single arithmetic circuit included in the display device, and represents a process that can be executed when the arithmetic circuit can output only a 1-bit signal in response to a 2-bit input signal.

[0032] Fig. 4A is a diagram showing pixel signal levels of the Nth frame of the input signal Sin received from the control device 2. Fig. 4B is a diagram showing pixel signal levels of a plurality of subframes corresponding to the Nth frame in a signal after dithering processing. Fig. 4C is a diagram showing pixel signal levels of the Nth frame recognized when viewing an image projected with the signal shown in Fig. 4B.

[0033] 4A to 4C, the arithmetic circuit performs dithering on each pixel arranged in a 4 x 4 matrix. In the example shown in Fig. 4A, the signal level of each pixel in the Nth frame of the input signal is 3. The input signal is 2 bits and 60 Hz.

[0034] The arithmetic circuit performs a dithering process on the input signal to convert it into a 1-bit, 240 Hz output signal. For example, the arithmetic circuit generates four subframes, i.e., the m, m+1, m+2, and m+3 subframes, based on the Nth frame, as shown in FIG. 4B . As shown in FIG. 4B , the signal level of each pixel in the m to m+3 subframes of the output signal is 0 or 1. The mth subframe of the output signal is generated such that the signal level of the bottom left pixel in the 2×2 matrix is ​​0. The m+1 subframe of the output signal is generated such that the signal level of the bottom right pixel in the matrix is ​​0. The m+2 subframe of the output signal is generated such that the signal level of the top right pixel in the matrix is ​​0. The m+3 subframe of the output signal is generated such that the signal level of the top left pixel in the matrix is ​​0.

[0035] The arithmetic circuit included in optical unit 40 drives the DMD based on the output signal shown in Figure 4B and projects an image corresponding to the output signal onto a screen. The arithmetic circuit projects an image corresponding to the 1-bit, 240 Hz output signal. When viewed by the human eye, the image projected based on the output signal is time-integrated, and an image equivalent to 2-bit and 60 Hz can be perceived.

[0036] Thus, even if a display device can only output a 1-bit signal, the display device according to the comparative example can project an image equivalent to 2 bits by performing a dithering process on the input signal. In other words, the display device can expand the gradation of the projected image by performing a dithering process. However, an image projected by the display device shown in the comparative example may have dither noise due to adjustment of pixel signal levels based on the dithering process. The dither noise can be reduced by changing the processing content of the dithering process. However, if hardware resource or software constraints make it difficult to change the dithering process performed by the arithmetic circuit to generate an output signal corresponding to the image projected from the optical mechanism, it is difficult for the display device to reduce the dither noise.

[0037] The display device 3 according to this embodiment includes a first arithmetic circuit 31 and a second arithmetic circuit 32, and thus can perform multiple dithering processes. That is, the display device 3 can perform a second dithering process that generates a signal corresponding to an image projected from the optical mechanism 38, and a first dithering process that is different from the second dithering process. Therefore, the display device 3 can further perform any dithering process on the input signal. Even if the second dithering process is subject to constraints due to hardware resources, etc., the display device 3 can reduce dither noise in the projected image by applying dithering corresponding to the dither noise expected in the second dithering process as the first dithering process. For example, if applying only the second dithering process is expected to cause flicker in the projected image, the display device 3 can reduce the occurrence of flicker in the projected image by adding temporal dithering as the first dithering process.

[0038] 5 is a flowchart illustrating an example of processing executed by the first arithmetic circuit 31. When the arithmetic circuit 21 of the control device 2 outputs the input signal Sin to the display device 3, the first arithmetic circuit 31 of the display device 3 receives the input signal Sin through the receiving circuit 36 ​​(S10). Next, the first arithmetic circuit 31 performs a first dithering process on the input signal Sin to generate a first signal S1 (S12). After generating the first signal S1, the first arithmetic circuit 31 outputs the first signal S1 to the second arithmetic circuit 32 (S14). The first arithmetic circuit 31 may be configured to perform the first dithering process after completing reception of the input signal Sin and output the first signal S1. The first arithmetic circuit 31 may be configured to perform the first dithering process each time it receives one or more frames of the input signal Sin and sequentially output one or more frames (or subframes) of the generated first signal S1.

[0039] 6 is a flowchart illustrating an example of processing executed by the second arithmetic circuit 32. When the first arithmetic circuit 31 outputs the first signal S1, the second arithmetic circuit 32 receives the first signal S1 (S20). Next, the second arithmetic circuit 32 performs a second dithering process on the first signal S1 to generate a second signal S2 (S22). After generating the second signal S2, the second arithmetic circuit 32 outputs the second signal S2 to the optical unit 40 (S24). The second arithmetic circuit 32 may be configured to perform the second dithering process after completing reception of the first signal S1 and output the second signal S2. The second arithmetic circuit 32 may be configured to perform the second dithering process each time it receives one or more frames (or subframes) of the first signal S1, and sequentially output one or more frames (or subframes) of the generated second signal S2.

[0040] 7 is a block diagram showing the flow of each signal in the display device 3 according to this embodiment. As shown in FIG. 7, the first arithmetic circuit 31 performs a first dithering process on the input signal Sin and outputs a first signal S1 to the second arithmetic circuit 32. The second arithmetic circuit 32 performs a second dithering process on the input second signal and outputs a second signal S2 to the optical unit 40. The arithmetic circuit of the optical unit 40 drives the DMD based on the second signal, modulates light from the light source, and generates and projects image light.

[0041] 8A to 8E are diagrams showing changes in pixel signal levels in an example of a display process according to this embodiment.

[0042] As described above, the display process according to this embodiment is executed by the first arithmetic circuit 31 and the second arithmetic circuit 32. The display process according to the example shown in Fig. 8 indicates a process executed when the second arithmetic circuit 32 can output only a 1-bit signal in response to a 2-bit input signal Sin.

[0043] Fig. 8A is a diagram showing the signal levels of pixels in the Nth frame of the input signal Sin received from the control device 2. Fig. 8B is a diagram showing the signal levels of pixels in multiple subframes corresponding to the Nth frame in the signal after the first dithering process has been performed by the first arithmetic circuit 31. That is, Fig. 8B is a diagram showing the signal levels of pixels in multiple subframes in the first signal S1 corresponding to the Nth frame of the input signal Sin.

[0044] FIG. 8C is a diagram showing pixel signal levels of multiple sub-subframes corresponding to the Nth frame in the signal after the second dithering process is performed by the second arithmetic circuit 32. That is, FIG. 8C is a diagram showing pixel signal levels of multiple sub-subframes in the second signal S2 corresponding to the Nth frame of the input signal Sin. FIG. 8C is also a diagram showing pixel signal levels of multiple sub-subframes in the second signal S2 corresponding to the mth subframe and the (m+1)th subframe of the first signal S1, respectively. FIG. 8D is a diagram showing pixel signal levels of the mth subframe and the (m+1)th subframe obtained by time-integrating the image projected from the optical unit 40 based on the second signal S2 shown in FIG. 8C. FIG. 8E is a diagram showing pixel signal levels of the Nth frame that can be perceived by the human eye when viewing the image projected from the optical unit 40 based on the second signal S2 shown in FIG. 8C. FIG. 8E is also a diagram showing pixel signal levels of the Nth frame that can be perceived by the human eye when viewing the image shown in FIG. 8D.

[0045] 8A to 8E, the first arithmetic circuit 31 performs the first dithering process on each pixel arranged in a 4 × 4 matrix. In the example shown in Fig. 8A, the signal level of each pixel in the Nth frame of the input signal Sin is 3. The input signal Sin is 2 bits and 60 Hz.

[0046] The first arithmetic circuit 31 performs a first dithering process on the input signal Sin to generate a 2-bit, 120 Hz first signal S1 by applying a predetermined dithering to the input signal Sin ( FIG. 8B ). In this embodiment, the first arithmetic circuit 31 performs the first dithering process on the input signal Sin at 2 bits and 120 Hz. For example, based on the Nth frame of the input signal Sin, the first arithmetic circuit 31 generates two subframes, the mth subframe and the (m+1)th subframe, by correcting the signal level of the Nth frame.

[0047] Since the signal level of each pixel in the Nth frame of the input signal Sin is 3, as shown in Fig. 8B, the signal levels of each pixel in the mth and (m+1)th subframes of the first signal S1 are set to 2 or 4 so that the average is 3. The mth subframe of the first signal S1 is generated so that nearby pixels, specifically pixels adjacent to each other vertically or horizontally, have different signal levels. For pixels displayed at the same position, the signal level of the pixel in the (m+1)th subframe is generated so that it is different from the signal level of the pixel in the mth subframe.

[0048] In this way, the first arithmetic circuit 31 generates each subframe of the first signal S1 based on each frame of the received input signal Sin and outputs it to the second arithmetic circuit 32. In this embodiment, the Nth frame of the input signal Sin etc. corresponds to the mth subframe and the (m+1)th subframe of the first signal S1 etc.

[0049] The second calculation circuit 32 performs a second dithering process on the first signal S1 to generate a 1-bit, 480 Hz second signal S2 by applying a specific dithering to the first signal S1 ( FIG. 8C ). In this embodiment, the second calculation circuit 32 performs the second dithering process on the first signal S1 at 1 bit and 480 Hz. In this manner, the second calculation circuit 32 performs the second dithering process on the first signal S1 with a smaller number of bits and a higher frequency than the first signal S1. For example, the second calculation circuit 32 generates four sub-subframes, i.e., the i+1th, i+2th, and i+3th sub-subframes, based on the m-th frame of the first signal S1. Furthermore, for example, the second calculation circuit 32 generates four sub-subframes, i.e., the j-th, j+1th, j+2nd, and j+3rd sub-subframes, based on the m+1th frame of the first signal S1.

[0050] In this embodiment, the second arithmetic circuit 32 cannot output a 2-bit signal, but has the capability to output a 1-bit signal. Therefore, the second arithmetic circuit 32 performs a second dithering process to generate and output a second signal S2 having gradation equivalent to 2 bits based on the first signal S1. A predetermined dithering process related to the first dithering process is applied to the first signal S1. Therefore, the second signal S2 output from the second arithmetic circuit 32 shown in FIG. 8C includes information about the predetermined dithering process related to the first dithering process.

[0051] The signal level of each pixel in the m-th subframe of the first signal S1 is 2 or 4. For example, the signal levels of each pixel in the i-th to (i+3)-th sub-subframes of the second signal S2, which are displayed in the same position as the pixel whose signal level is 2 in the first signal S1, alternate between 1 and 0 per bit. For example, the signal levels of each pixel in the i-th to (i+3)-th sub-subframes of the second signal S2, which are displayed in the same position as the pixel whose signal level is 4 in the first signal S1, alternate between 1 and 0 per bit. By generating the second signal S2 in this manner, each sub-subframe of the second signal S2 contains one bit of signal level information, but combining four sub-subframes can hold signal level information equivalent to two bits.

[0052] The signal level of each pixel in the m+1-th subframe of the first signal S1 is 2 or 4. For example, the signal levels of each pixel in the j-th to j+3-th sub-subframes of the second signal S2, which are displayed in the same position as a pixel with a signal level of 2 in the first signal S1, alternate between 1 and 0 per bit. For example, the signal levels of each pixel in the j-th to j+3-th sub-subframes of the second signal S2, which are displayed in the same position as a pixel with a signal level of 4 in the first signal S1, alternate between 1 and 0 per bit. Furthermore, for each pixel displayed in the same position, the signal level of the pixel in the j+1-th sub-subframe is generated to be different from the signal level of the pixel in the i+1-th sub-subframe. For each pixel displayed in the same position, the signal level of the pixel in the j+3-th sub-subframe is generated to be different from the signal level of the pixel in the i+3-th sub-subframe.

[0053] FIG. 8C also shows pixel signal levels for the i to i+3 sub-subframes and the j to j+3 sub-subframes in the image projected by the optical unit 40 based on the second signal S2. As described above, the i to i+3 sub-subframes projected by the display device 3 correspond to the m subframe in the image shown in FIG. 8D when integrated over time. The j to j+3 sub-subframes projected by the display device 3 correspond to the m+1 subframe in the image shown in FIG. 8D when integrated over time. The m and m+1 sub-frames of the image projected by the display device 3 have the same number of bits and frequency as the first signal S1. Even if the second signal S2 contains one-bit signal level information, the image projected based on the second signal S2 can have a signal level equivalent to two bits by combining four sub-subframes through time integration. In this way, the display device 3 can project an image having two bits of information using the second dithering process, even if the second arithmetic circuit 32 cannot output a two-bit signal due to hardware or software limitations.

[0054] When a human visually views the image shown in FIG. 8D , the image is integrated over time and perceived as shown in FIG. 8E . Specifically, the 2-bit, 120 Hz image shown in FIG. 8D may be perceived by a human as the 2-bit, 60 Hz image shown in FIG. 8E . Because the image projected based on the second signal S2 includes the predetermined dithering applied in the first dithering process, dither noise that may occur in the image can be reduced by the predetermined dithering. For example, in this embodiment, the first dithering process includes temporal dithering, so the display device 3 can project an image in which the flicker that may occur when only the second dithering process is performed is corrected so that it is not noticeable.

[0055] In this way, the first arithmetic circuit 31 generates, in the first signal S1, a plurality of subframes corresponding to a first frame of the plurality of frames of the input signal Sin through the first dithering process. The first arithmetic circuit 31 corrects the signal level of at least one first region of the DMD in the first subframe of the plurality of subframes to a signal level higher than the signal level in the first frame. The first arithmetic circuit 31 corrects the signal level of the at least one first region in a second subframe of the plurality of subframes, different from the first subframe, to a signal level lower than the signal level in the first frame. Therefore, the display device 3 can apply temporal dithering as the first dithering process to the input signal Sin using the first arithmetic circuit 31, which is different from the second arithmetic circuit 32.

[0056] The display device 3 according to this embodiment executes a first dithering process using the first arithmetic circuit 31 and further executes a second dithering process using the second arithmetic circuit 32. Therefore, compared to when only the second dithering process is executed, a separate dithering is applied to the projected image to be displayed, and the display device 3 can reduce dither noise that may be noticeable when a human views the projected image. Even if the functionality of the second dithering process executed by the second arithmetic circuit 32 is limited by hardware resources or software, the display device 3 can reduce dither noise while suppressing increases in cost or processing time. In this way, the display device 3 can reduce the occurrence of dither noise that may be generated by dithering to suppress degradation of image quality due to limitations on hardware resources, etc., by adding additional dithering in accordance with the dithering.

[0057] In this embodiment, the at least one first region may represent, for example, at least one first mirror panel among a plurality of mirror panels included in the DMD, and may correspond to, for example, at least one first pixel projected by the first mirror panel among a plurality of mirror panels included in the DMD, or may correspond to, for example, at least one first pixel in the input signal Sin or the first signal S1.

[0058] 9A to 9D are diagrams showing changes in pixel signal levels in another example of the display processing according to this embodiment. The display processing according to this example shows processing that is executed when the second arithmetic circuit 32 can output only an 8-bit signal for a 10-bit input signal Sin.

[0059] FIG. 9A is a diagram showing the signal levels of pixels in the Nth frame of the input signal Sin received from the control device 2. FIG. 9B is a diagram showing the shift amounts of signal levels of pixels in multiple subframes corresponding to the Nth frame in the signal after the first dithering process has been performed by the first arithmetic circuit 31. That is, FIG. 9B is a diagram showing the difference between the signal levels of pixels in the Nth frame of the input signal Sin and the signal levels of pixels in the multiple subframes in the first signal S1. FIG. 9C is a diagram showing the signal levels of pixels in multiple subframes corresponding to the Nth frame, obtained by time-integrating an image projected from the optical unit 40 based on the signal after the second dithering process has been performed by the second arithmetic circuit 32. That is, FIG. 9C is a diagram showing the signal levels of pixels in multiple subframes in an image projected based on the second signal S2 corresponding to the Nth frame of the input signal Sin. FIG. 9D is a diagram showing the signal levels of pixels in the Nth frame that can be recognized when the image shown in FIG. 9C is viewed by the human eye.

[0060] 9A to 9D, the first arithmetic circuit 31 performs the first dithering process on each pixel arranged in a 4 x 4 matrix. In the example shown in Fig. 9A, the signal level of each pixel in the Nth frame of the input signal Sin is 128. The input signal Sin is 10 bits and 60 Hz.

[0061] The first calculation circuit 31 performs a first dithering process on the input signal Sin to generate a 10-bit, 240 Hz first signal S1 by applying a predetermined dithering to the input signal Sin ( FIG. 9B ). In this embodiment, the first calculation circuit 31 performs the first dithering process on the input signal Sin at 10 bits and 240 Hz. For example, based on the Nth frame of the input signal, the first calculation circuit 31 generates four subframes, namely, the mth subframe, the m+1th subframe, the m+2th subframe, and the m+3th subframe, by correcting the signal level of the Nth frame. In this embodiment, the Nth frame of the input signal Sin corresponds to the mth subframe, the m+1th subframe, the m+2th subframe, and the m+3rd subframe of the first signal S1.

[0062] As shown in FIG. 9B , the signal level shift amount for each pixel in the m-th, m+1-th, m+2-th, and m+3-th subframes of the first signal S1 is one of −4, −3, −2, −1, +1, +2, +3, and +4. The signal level shift amounts for each pixel in the generated m-th to m+3-th subframes are set so that the sum of the shift amounts for each pixel displayed at the same position in the m-th to m+3-th subframes is 0. The first arithmetic circuit 31 adds the shift amount to the signal level of the N-th frame of the input signal Sin to generate the m-th to m+3-th subframes of the first signal S1 and outputs them to the second arithmetic circuit 32. In other words, the first arithmetic circuit 31 corrects, for example, the signal level of the m-th subframe of the first signal S1 to a higher or lower signal level than the signal level of the N-th frame of the input signal Sin.

[0063] In the first dithering process, the storage device 33 may include multiple sets containing multiple tables, and the first arithmetic circuit 31 may generate the first signal S1 by applying multiple tables contained in one of the multiple sets to the input signal Sin. For example, the first arithmetic circuit 31 may apply dithering by switching the table to be applied for each subframe. The storage device 33 may include, for example, a set containing a table containing a shift amount equivalent to the matrix of each subframe shown in FIG. 9B. The tables contained in the set applied in the first dithering process are not limited to the matrix shown in FIG. 9B, and any table may be used. For example, the first arithmetic circuit 31 may apply a number of tables other than four, such as two tables, six tables, or the like.

[0064] The second arithmetic circuit 32 performs a second dithering process on the first signal S1 to generate an 8-bit, 960 Hz second signal S2 by applying a specific dithering process to the first signal S1. In this embodiment, the second arithmetic circuit 32 performs the second dithering process on the first signal S1 at 8 bits and at a frequency of 960 Hz or higher. In this embodiment, the second arithmetic circuit 32 is not capable of outputting a 10-bit signal but is capable of outputting an 8-bit signal. Therefore, by performing the second dithering process, the second arithmetic circuit 32 generates and outputs a second signal S2 having gradation equivalent to 10 bits based on the first signal S1. A specific dithering process related to the first dithering process has been applied to the first signal S1. Therefore, the second signal S2 output from the second arithmetic circuit 32 includes information about the specific dithering process related to the first dithering process.

[0065] As described above, even if the second arithmetic circuit 32 cannot output a signal with the number of bits of the first signal S1 due to hardware resource or software constraints, it can output a signal having information equivalent to that number of bits by performing the second dithering process. The second arithmetic circuit 32 generates, for example, four sub-subframes as the second signal S2 corresponding to the m-th frame of the first signal S1. Since the signal level of each pixel in the m-th frame of the first signal S1 is one of 124 to 127 or 129 to 132, the signal level of each pixel in the four sub-subframes is, for example, one of 31, 32, or 33 in 8 bits.

[0066] For example, the signal levels of pixels displayed at the same position in four sub-subframes are adopted so that a combination of the four sub-subframes corresponds to the signal level of a pixel displayed at the same position in the m-th frame of the first signal S1. The second signal S2 corresponding to the (m+1)-(m+3)-th frames of the first signal S1 is generated in the same manner as the second signal S2 corresponding to the m-th frame of the first signal S1.

[0067] When the second arithmetic circuit 32 outputs the second signal S2 to the optical unit 40, the optical unit 40 projects an image based on the second signal S2. The projected image has the same number of bits, frequency, and signal level as the second signal S2. Therefore, the projected image corresponding to one subframe of the first signal S1 includes four sub-subframes. When the projected image including four sub-subframes is integrated over time, it corresponds to an image having 10-bit and 240 Hz subframes, as shown in FIG. 9C. Furthermore, when the projected image is integrated over time, it has a signal level corresponding to the subframes of the first signal S1. For example, as shown in FIG. 9C, the pixels of each subframe obtained by time-integrating the image projected based on the second signal S2 have a signal level corresponding to one of 124 to 127 or 129 to 132. Each of the mth to m+3th subframes shown in FIG. 9C has the same number of bits and frequency as the mth to m+3th subframes of the first signal S1.

[0068] When a human views the image shown in Fig. 9C , it is integrated over time and perceived as shown in Fig. 9D . Specifically, the 10-bit, 240 Hz image shown in Fig. 9C can be perceived by a human as the 10-bit, 60 Hz image shown in Fig. 9D . Because the image projected based on the second signal includes the predetermined dithering applied in the first dithering process, dither noise that may occur in the image can be reduced by the predetermined dithering.

[0069] 8A to 8D, the display process by the display device 3 according to this embodiment can be applied to input signals with various bit counts and frequencies. The first dithering process can also be performed in various ways. Therefore, even if the functionality of the second dithering process performed by the second arithmetic circuit 32 is limited by hardware resources or software, the display device 3 can reduce dither noise without increasing costs or processing time.

[0070] 10A to 10D are diagrams showing changes in pixel signal levels in another example of the display processing according to the present embodiment. The display processing in this example shows processing executed when the second arithmetic circuit 32 can output only a 1-bit signal for a 2-bit input signal Sin. The example also shows an example in which the first arithmetic circuit 31 applies temporal dithering as the first dithering process to the input signal Sin to generate one frame of the first signal S1 corresponding to one frame of the input signal Sin.

[0071] 10A is a diagram showing pixel signal levels of the Nth and N+1th frames of the input signal Sin received from the control device 2. FIG. 10B is a diagram showing pixel signal levels of the Nth and N+1th frames of the signal after the first dithering process has been performed by the first arithmetic circuit 31. FIG. 10C is a diagram showing pixel signal levels of the Nth and N+1th frames obtained by time-integrating the image projected from the optical unit 40 based on the signal after the second dithering process has been performed by the second arithmetic circuit 32. FIG. 10D is a diagram showing pixel signal levels of the kth frame that can be recognized when the image shown in FIG. 10C is viewed by the human eye. The Nth and N+1th frames of the input signal Sin, first signal S1, and second signal S2 correspond to the kth frame of the image viewed by the human eye.

[0072] 10A to 10D, the first arithmetic circuit 31 performs the first dithering process on each pixel arranged in a 4x4 matrix. In the example shown in Fig. 10A, the signal level of each pixel in the Nth and N+1th frames of the input signal Sin is 3. The input signal Sin is 2 bits and 60 Hz.

[0073] The first calculation circuit 31 performs a first dithering process on the input signal Sin to generate a 2-bit, 60 Hz first signal S1 by applying a predetermined dithering to the input signal Sin ( FIG. 10B ). In this embodiment, the first calculation circuit 31 performs a first dithering process on the input signal Sin at 2 bits and 60 Hz. For example, the first calculation circuit 31 generates the Nth frame of the first signal S1 by correcting the signal level of the Nth frame of the input signal Sin based on the Nth frame of the input signal Sin. The first calculation circuit 31 also generates the N+1th frame of the first signal S1 by correcting the signal level of the Nth frame of the input signal Sin based on the N+1th frame of the input signal Sin. Since the signal level of each pixel in the Nth frame of the input signal Sin is 3, as shown in FIG. 10B , the signal level of each pixel in the Nth frame of the first signal S1 is set to 2 or 4 so that the average is 3. The Nth frame of the first signal S1 is generated so that neighboring pixels, specifically pixels adjacent to each other vertically or horizontally, have different signal levels. For pixels displayed at the same position, the signal level of the pixel in the (N+1)th frame is generated so that it is different from the signal level of the pixel in the Nth frame. In this way, the first arithmetic circuit 31 generates each frame of the first signal S1 based on each frame of the received input signal Sin and outputs it to the second arithmetic circuit 32.

[0074] The second arithmetic circuit 32 performs a second dithering process on the first signal S1 to generate a 1-bit, 240 Hz second signal S2 by applying a specific dithering to the first signal S1. In this embodiment, the second arithmetic circuit 32 performs the second dithering process on the first signal S1 at 1 bit and 240 Hz. In this embodiment, the second arithmetic circuit 32 is not capable of outputting a 2-bit signal, but is capable of outputting a 1-bit signal. Therefore, by performing the second dithering process, the second arithmetic circuit 32 generates and outputs a second signal S2 having gradation equivalent to 2 bits based on the first signal S1. A specific dithering process related to the first dithering process has been applied to the first signal S1. Therefore, the second signal S2 output from the second arithmetic circuit 32 includes information about the specific dithering process related to the first dithering process.

[0075] 8B to 8D in the above example, even if the second arithmetic circuit 32 cannot output a 2-bit signal due to hardware resource or software constraints, it can output a signal having information equivalent to 2 bits by performing the second dithering process. Therefore, the display device 3 projects an image based on the second signal S2 output from the second arithmetic circuit 32, and can project images corresponding to the Nth and N+1th frames using the optical unit 40, as shown in FIG. 10C. The Nth and N+1th frames in the image shown in FIG. 10C have the same number of bits and frequency as the Nth and N+1th frames in the input signal Sin and the first signal S1.

[0076] When a human visually recognizes the image shown in Fig. 10C , it is integrated over time and recognized as shown in Fig. 10D . Specifically, the 2-bit, 60 Hz image shown in Fig. 10C can be recognized as the 2-bit, 30 Hz image shown in Fig. 10D when visually recognized by a human. Since the image projected based on the second signal S2 includes the predetermined dithering applied in the first dithering process, dither noise that may occur in the image can be reduced by the predetermined dithering.

[0077] In this way, the first arithmetic circuit 31 corrects, through the first dithering process, the signal level of at least one first region of the DMD in a second frame of the first signal S1 corresponding to a first frame of the multiple frames of the input signal Sin to a signal level higher than the signal level in the first frame. Furthermore, the first arithmetic circuit 31 corrects, through the first dithering process, the signal level of at least one first region in a fourth frame of the first signal S1 corresponding to a third frame different from the first frame of the input signal Sin to a signal level lower than the signal level in the third frame. Therefore, the display device 3 can apply temporal dithering as the first dithering process to the input signal Sin using the first arithmetic circuit 31, which is different from the second arithmetic circuit 32.

[0078] In this way, the first dithering process is not limited to the process of generating, in the first signal S1, a plurality of subframes corresponding to one of the frames of the input signal Sin. The first dithering process includes the process of generating, in the first signal S1, a single frame corresponding to one of the frames of the input signal Sin. Therefore, the display device 3 can apply any dithering to the input signal Sin as the first dithering process using the first arithmetic circuit 31, thereby reducing dither noise in the projected image while suppressing increases in cost or processing time.

[0079] 11A to 11D are diagrams showing changes in pixel signal levels in another example of the display processing according to the present embodiment. The display processing in this example shows processing executed when the second arithmetic circuit 32 can output only a 1-bit signal for a 2-bit input signal Sin. The example also shows an example in which the first arithmetic circuit 31 applies spatial dithering as the first dithering process to the input signal Sin to generate one frame of the first signal S1 corresponding to one frame of the input signal Sin.

[0080] Fig. 11A is a diagram showing the signal level of pixels in the Nth frame of the input signal Sin received from the control device 2. Fig. 11B is a diagram showing the signal level of pixels in the Nth frame of the signal after the first dithering process has been performed by the first arithmetic circuit 31. Fig. 11C is a diagram showing the signal level of pixels in the Nth frame obtained by time-integrating the image projected from the optical unit 40 based on the signal after the second dithering process has been performed by the second arithmetic circuit 32. Fig. 11D is a diagram showing the signal level of pixels in the Nth frame that can be recognized when the image shown in Fig. 11C is viewed by the human eye.

[0081] 11A to 11D, the first arithmetic circuit 31 performs the first dithering process on each pixel arranged in a 4 × 4 matrix. In the example shown in Fig. 11A, the signal level of each pixel in the Nth frame of the input signal Sin is 3. The input signal Sin is 2 bits and 60 Hz.

[0082] The first calculation circuit 31 performs a first dithering process on the input signal Sin to generate a 2-bit, 60 Hz first signal S1 by applying a predetermined dithering to the input signal Sin ( FIG. 11B ). In this embodiment, the first calculation circuit 31 performs the first dithering process on the input signal Sin at 2-bit and 60 Hz. For example, the first calculation circuit 31 generates the Nth frame of the first signal S1 by correcting the signal level of the Nth frame of the input signal Sin based on the Nth frame of the input signal Sin. Since the signal level of each pixel in the Nth frame of the input signal Sin is 3, as shown in FIG. 11B , the signal level of each pixel in the Nth frame of the first signal S1 is set to 2 or 4 so that the average is 3. The Nth frame of the first signal S1 is generated so that neighboring pixels, specifically pixels adjacent to each other vertically or horizontally, have different signal levels.

[0083] The second arithmetic circuit 32 performs a second dithering process on the first signal S1 to generate a 1-bit, 240 Hz second signal S2 by applying a specific dithering to the first signal S1. In this embodiment, the second arithmetic circuit 32 performs the second dithering process on the first signal S1 at 1 bit and 240 Hz. In this embodiment, the second arithmetic circuit 32 is not capable of outputting a 2-bit signal, but is capable of outputting a 1-bit signal. Therefore, by performing the second dithering process, the second arithmetic circuit 32 generates and outputs a second signal S2 having gradation equivalent to 2 bits based on the first signal S1. A specific dithering process related to the first dithering process has been applied to the first signal S1. Therefore, the second signal S2 output from the second arithmetic circuit 32 includes information about the specific dithering process related to the first dithering process.

[0084] 8B to 8D in the above example, even if the second arithmetic circuit 32 cannot output a 2-bit signal due to hardware resource or software constraints, it can output a signal having information equivalent to 2 bits by performing the second dithering process. Therefore, the display device 3 can project an image based on the second signal S2 output from the second arithmetic circuit 32, thereby projecting an image corresponding to the Nth frame as shown in FIG. 11C. The Nth frame in the image shown in FIG. 11C has the same number of bits and frequency as the Nth frame in the input signal Sin and the first signal S1.

[0085] When a human views the image shown in Fig. 11C, it is spatially smoothed and can be perceived as shown in Fig. 11D. Since the image projected based on the second signal includes the predetermined dithering applied in the first dithering process, dither noise that may occur in the image can be reduced by the predetermined dithering.

[0086] In this way, the first arithmetic circuit 31 corrects the signal level of the first signal S1 for at least one first region of the DMD to a signal level higher than the signal level of the input signal Sin through the first dithering process. The first arithmetic circuit 31 also corrects the signal level of the first signal S1 for at least one second region different from the first region to a signal level lower than the signal level of the input signal Sin through the first dithering process. The at least one second region is located near the at least one first region. Therefore, the display device 3 can apply spatial dithering to the input signal Sin as the first dithering process using the first arithmetic circuit 31, which is different from the second arithmetic circuit 32.

[0087] In this way, the first dithering process performed by the first arithmetic circuit 31 is not limited to temporal dithering, and may include spatial dithering or both temporal and spatial dithering. Therefore, the display device 3 can apply any dithering to the input signal Sin as the first dithering process using the first arithmetic circuit 31, thereby reducing dither noise in the projected image while suppressing increases in cost or processing time.

[0088] In this embodiment, the at least one second region is a region different from the at least one first region. The at least one second region represents, for example, at least one second mirror panel different from the first mirror panel among the multiple mirror panels included in the DMD. The at least one second region corresponds, for example, to at least one second pixel different from the first pixel projected by one second mirror panel among the multiple mirror panels included in the DMD. The at least one second region corresponds, for example, to at least one second pixel different from the first pixel in the input signal Sin or the first signal S1.

[0089] In the present disclosure, "neighboring pixels" includes pixels adjacent to each other vertically or horizontally. Also, "neighboring pixels" includes pixels adjacent to each other diagonally. Also, "neighboring pixels" is not limited to adjacent pixels, but includes pixels spaced apart by anywhere from one to nine pixels. In this way, the display device 3 can reduce dither noise in the projected image by using the first arithmetic circuit 31 to apply dithering to the input signal Sin not only to adjacent pixels but also to pixels spaced apart by anywhere from one to nine pixels.

[0090] In the present disclosure, the second arithmetic circuit 32 performs the second dithering process at a frequency four times that of the first signal S1 to generate a second signal S2 having a frequency four times that of the first signal S1. However, the second dithering process and the frequency of the second signal S2 are not limited to four times the frequency of the first signal S1. The second arithmetic circuit 32 can perform the second dithering process at any frequency higher than the frequency of the first signal S1, such as 1.5 times, 2 times, 2.5 times, 3 times, or 6 times, to generate a second signal S2 having any frequency higher than the frequency of the first signal S1.

[0091] (Modifications) In the above-described embodiment, the first region and the second region each correspond to one pixel in the input signal Sin, the first signal S1, the second signal S2, etc., but are not limited to this. For example, the first region and the second region may each include a plurality of pixels in the input signal Sin, the first signal S1, the second signal S2, etc. For example, the first region may include a plurality of pixels arranged in a 2×2 matrix. The first region may also include a plurality of pixels arranged in a matrix of a predetermined size.

[0092] In the above-described embodiment, the first dithering process and the second dithering process are executed in the display device 3, but the invention according to the present disclosure is not limited to processing within the display device 3. For example, the invention according to the present disclosure may be configured to be executed within a display system 1 including the control device 2 and display device 3 shown in Fig. 1. Fig. 12 is a schematic diagram of a display device 3 according to a modified example.

[0093] The control device 2 according to the modified example has the same configuration as the control device 2 according to the above-described embodiment. The arithmetic circuit 21 includes the functions of the first arithmetic circuit 31 according to the above-described embodiment. In other words, the arithmetic circuit 21 can perform a first dithering process on the input signal Sin.

[0094] The display device 3 according to the modification is configured in the same manner as the display device 3 according to the embodiment described above, except that it does not include the first arithmetic circuit 31 .

[0095] In the display system 1 according to the modified example, the arithmetic circuit 21 of the control device 2 performs a first dithering process on an input signal Sin corresponding to an image to be projected via the display device 3 to generate a first signal S1. The arithmetic circuit 21 then transmits the first signal S1 to the display device 3 via the transmission circuit 26. Upon receiving the first signal S1 via the reception circuit 36, the second arithmetic circuit 32 of the display device 3 performs a second dithering process on the first signal S1 to generate a second signal S2. The second arithmetic circuit 32 then outputs the second signal S2 to the optical unit 40.

[0096] In this way, the above-described display process may be performed by a plurality of devices.

[0097] Signals such as the input signal Sin in the display process described above may be interlaced signals or progressive signals.

[0098] [1-3. Effects] According to the display device 3 or the display system 1 according to the first embodiment of the present disclosure, the following effects can be achieved.

[0099] The display device 3 modulates and projects light from a light source 39 based on an input signal Sin. The display device 3 includes a first arithmetic circuit 31, a second arithmetic circuit 32, a light source 39 that generates light, and a digital mirror device (DMD) 40. The first arithmetic circuit 31 performs a first dithering process on the input signal Sin to generate and output a first signal S1. The second arithmetic circuit 32 performs a second dithering process on the first signal S1 to generate and output a second signal S2. The DMD 40 modulates the light from the light source 39 based on the second signal S2 to generate image light.

[0100] With this configuration, the display device 3 can execute different dithering processes using the two arithmetic circuits 31 and 32. Even if the second arithmetic circuit 32 can only execute a specific dithering process due to hardware resource or software constraints, the display device 3 can include additional dithering in the projected image by executing a dithering process using the first arithmetic circuit 31. Executing two dithering processes using the two arithmetic circuits 31 and 32 can reduce costs and processing load compared to using pattern subdivision or feedback control. Therefore, the display device 3 according to the present disclosure can reduce degradation in the image quality of the projected image while suppressing increases in cost or processing time.

[0101] Furthermore, in the display device 3, the first dithering process includes correcting luminance information in the first signal S1 for at least one first region of the DMD 40 to a luminance higher than that of the luminance information in the input signal Sin. The first dithering process also includes correcting luminance information in the first signal S1 for at least one second region of the DMD 40 that is different from the at least one first region to a luminance lower than that of the luminance information in the input signal Sin. By operating in this manner, the display device 3 can apply spatial dithering to the input signal Sin as the first dithering process using the first arithmetic circuit 31, and include the spatial dithering in the projected image. Therefore, the display device 3 can reduce dither noise in the projected image while suppressing increases in cost or processing time.

[0102] In the display device 3, at least one second region is located near at least one first region. With this configuration, the display device 3 can apply spatial dithering to the input signal Sin as a first dithering process using the first arithmetic circuit 31, thereby including the spatial dithering in the projected image. Therefore, the display device 3 can reduce dither noise in the projected image while suppressing increases in cost or processing time.

[0103] In the display device 3, the DMD 40 includes a plurality of mirror panels. At least one first region corresponds to at least one first pixel projected by at least one first mirror panel among the plurality of mirror panels. At least one second region corresponds to at least one second pixel, different from the at least one first pixel, projected by at least one second mirror panel, different from the at least one first mirror panel among the plurality of mirror panels. With this configuration, an image including a predetermined dithering process can be projected using the plurality of mirror panels of the DMD 40. Therefore, the display device 3 can reduce dither noise in the projected image while suppressing increases in cost or processing time.

[0104] In the display device 3, the first dithering process includes correcting luminance information for at least one first region of the DMD 40 in a second frame of the first signal S1 corresponding to a first frame of the input signal Sin to a luminance higher than that of the first frame. The first dithering process also includes correcting luminance information for at least one first region in a fourth frame of the first signal S1 corresponding to a third frame different from the first frame of the input signal Sin to a luminance lower than that of the third frame. By operating in this manner, the display device 3 applies temporal dithering to the input signal Sin as the first dithering process using the first arithmetic circuit 31, thereby incorporating the temporal dithering in the projected image. Therefore, the display device 3 can reduce dither noise in the projected image without increasing costs or processing time.

[0105] In the display device 3, the first dithering process includes generating, in the first signal S1, multiple subframes corresponding to a first frame among the multiple frames of the input signal Sin. The first dithering process includes correcting, in the first subframe among the multiple subframes, luminance information for at least one first region of the DMD 40 to a luminance higher than that of the first frame. The first dithering process includes correcting, in a second subframe among the multiple subframes, luminance information for at least one first region to a luminance lower than that of the first frame. By operating in this manner, the display device 3 applies temporal dithering to the input signal Sin as the first dithering process using the first arithmetic circuit 31, and can include the temporal dithering in the projected image. Therefore, the display device 3 can reduce dither noise in the projected image without increasing costs or processing time.

[0106] The display system includes a control device 2 that outputs a predetermined signal and a display device 3 that modulates and projects light from a light source based on the predetermined signal input from the control device 2. The control device 2 includes a first arithmetic circuit 21 that performs a first dithering process on an input signal Sin to generate a first signal S1 and output the first signal S1 as the predetermined signal. The display device 3 includes a second arithmetic circuit 32 that performs a second dithering process on the first signal S1 to generate and output a second signal S2, a light source 39 that generates light, and a DMD 40 that modulates the light from the light source 39 based on the second signal S2 to generate image light. With this configuration, the display system 1 can reduce dither noise in a projected image using any display device 3 while suppressing increases in cost or processing time.

[0107] (Summary of Aspects) As is clear from the above description, the present disclosure includes the following aspects. In the following, reference numerals are given in parentheses only to clarify the correspondence with the embodiments.

[0108] (Aspect 1) A display device (3) according to the present disclosure is a display device that modulates and projects light from a light source (39) based on an input signal, and includes: a first arithmetic circuit (31) that performs a first dithering process on the input signal (Sin) to generate and output a first signal (S1); a second arithmetic circuit (32) that performs a second dithering process on the first signal to generate and output a second signal (S2); the light source that generates light; and a digital mirror device (DMD) (40) that modulates the light from the light source based on the second signal to generate image light.

[0109] (Aspect 2) In the display device (3) of aspect 1, the first dithering process may include: correcting luminance information in the first signal (S1) relating to at least one first region in the DMD (40) to a luminance higher than that in the input signal (Sin); and correcting luminance information in the first signal relating to at least one second region in the DMD that is different from the at least one first region to a luminance lower than that in the input signal.

[0110] (Aspect 3) In the display device (3) of aspect 2, the at least one second region may be located near the at least one first region.

[0111] (Aspect 4) In the display device (3) of Aspect 2 or Aspect 3, the DMD (40) may include a plurality of mirror panels, and the at least one first region may correspond to at least one first pixel projected by at least one first mirror panel of the plurality of mirror panels, and the at least one second region may correspond to at least one second pixel different from the at least one first pixel projected by at least one second mirror panel different from the at least one first mirror panel of the plurality of mirror panels.

[0112] (Aspect 5) In the display device (3) of aspect 1, the first dithering process may include: correcting luminance information for at least one first region in the DMD (40) in a second frame of the first signal (S1) corresponding to a first frame among the multiple frames of the input signal (Sin) to a luminance higher than the luminance information in the first frame; and correcting luminance information for the at least one first region in a fourth frame of the first signal corresponding to a third frame among the multiple frames, different from the first frame, to a luminance lower than the luminance information in the third frame.

[0113] (Aspect 6) In the display device (3) of aspect 1, the first dithering process may include: generating, in the first signal (S1), a plurality of subframes corresponding to a first frame of the plurality of frames of the input signal (Sin); correcting, in a first subframe of the plurality of subframes, luminance information for at least one first region of the DMD (40) to a luminance higher than the luminance information in the first frame; and correcting, in a second subframe of the plurality of subframes, different from the first subframe, luminance information for the at least one first region to a luminance lower than the luminance information in the first frame.

[0114] (Aspect 7) A system (1) according to the present disclosure is a system comprising: a control device (2) that outputs a predetermined signal (S1); and a display device (3) that modulates and projects light from a light source (39) based on the predetermined signal input from the control device, wherein the control device includes a first arithmetic circuit (21) that performs a first dithering process on an input signal (Sin) to generate a first signal (S1) and outputs it as the predetermined signal, and the display device includes: a second arithmetic circuit (32) that performs a second dithering process on the first signal to generate and output a second signal (S2), the light source that generates light, and a digital mirror device (DMD) (40) that modulates the light from the light source based on the second signal to generate image light.

[0115] As used herein, terms such as "first," "second," etc. are used for descriptive purposes only and should not be understood as expressing or implying relative importance or ranking of technical features. Features qualified as "first" and "second" expressly or imply the inclusion of one or more of that feature.

[0116] The display device and display system described in the present disclosure are realized by cooperation of hardware resources, such as a processor and memory, and software (computer program).

[0117] According to the present disclosure, it is possible to provide a display device and a display system that can reduce degradation in image quality compared to conventional techniques, and therefore the present disclosure can be suitably used in this type of industrial field.

Claims

1. A display device that modulates and projects light from a light source based on an input signal, comprising: a first arithmetic circuit that performs a first dithering process on the input signal to generate and output a first signal; a second arithmetic circuit that performs a second dithering process on the first signal to generate and output a second signal; the light source that generates light; and a digital mirror device (DMD) that modulates the light from the light source based on the second signal to generate image light.

2. The display device described in claim 1, wherein the first dithering process includes: correcting luminance information in the first signal relating to at least one first region in the DMD to a luminance higher than that in the input signal; and correcting luminance information in the first signal relating to at least one second region in the DMD that is different from the at least one first region to a luminance lower than that in the input signal.

3. The display device according to claim 2, wherein said at least one second region is located adjacent to said at least one first region.

4. The display device according to claim 2 or 3, wherein the DMD includes a plurality of mirror panels, the at least one first region corresponds to at least one first pixel projected by at least one first mirror panel of the plurality of mirror panels, and the at least one second region corresponds to at least one second pixel different from the at least one first pixel projected by at least one second mirror panel different from the at least one first mirror panel of the plurality of mirror panels.

5. The display device of claim 1, wherein the first dithering process includes: correcting luminance information for at least one first region in the DMD in a second frame of the first signal corresponding to a first frame of the plurality of frames of the input signal to a luminance higher than that of the luminance information in the first frame; and correcting luminance information for the at least one first region in a fourth frame of the first signal corresponding to a third frame of the plurality of frames different from the first frame to a luminance lower than that of the luminance information in the third frame.

6. The display device of claim 1, wherein the first dithering process includes: generating, in the first signal, a plurality of subframes corresponding to a first frame of the plurality of frames of the input signal; correcting, in a first subframe of the plurality of subframes, luminance information relating to at least one first region of the DMD to a luminance higher than that of the luminance information in the first frame; and correcting, in a second subframe of the plurality of subframes different from the first subframe, luminance information relating to the at least one first region to a luminance lower than that of the luminance information in the first frame.

7. A system comprising: a control device that outputs a predetermined signal; and a display device that modulates and projects light from a light source based on the predetermined signal input from the control device, wherein the control device includes a first arithmetic circuit that performs a first dithering process on the input signal to generate a first signal and output it as the predetermined signal, and the display device includes: a second arithmetic circuit that performs a second dithering process on the first signal to generate and output a second signal; the light source that generates light; and a digital mirror device (DMD) that modulates the light from the light source based on the second signal to generate image light.

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