Memory device, semiconductor device, and operating method thereof

Abstract

A memory device according to a first embodiment comprises: address cells storing all or a portion of addresses; data cells storing data; and a comparison circuit which compares the addresses stored in the address cells with an externally requested address in a subarray, wherein data writing or reading is performed on the data cells at a corresponding position according to the comparison result, a hierarchical distribution of the memory device has a channel, a rank, a chip, a bank group, and the subarray, the subarray includes a plurality of memory array tiles (MATs), at least one of the plurality of MATs is a metadata MAT, and the metadata MAT includes the comparison circuit performing tag matching.

Description

Memory elements and semiconductor devices and their operating methods

[0001] The present invention relates to a memory element, a semiconductor device including the same, and an operating method thereof.

[0002] This study is related to research projects and research tasks carried out with support from government-funded project management agencies, the list of which is as follows.

[0003] - This research project was conducted with the support of the National IT Industry Promotion Agency (NIPA) and the Ministry of Science and ICT (Government) (Project ID: 1711195788; Project ID: 00228970; Research Project Name: Development of Next-Generation Intelligent Semiconductor Technology (Design); Research Project Name: Development of Flexible SW / HW Integrated Solution for Edge Self-Supervised Learning; Research Period: 2023.04.01. ~ 2023.12.31.).

[0004] - This research project was conducted with the support of the National IT Industry Promotion Agency (NIPA) and the Ministry of Science and ICT (Government) (Project ID: 1711193231; Project No.: 2019-0-00421-005; Project Name: Training of Innovative Talents in Information and Communications Broadcasting; Project Name: Support for the Graduate School of Artificial Intelligence (Sungkyunkwan University); Research Period: January 1, 2023 - December 31, 2023).

[0005] - This research project was conducted with the support of the National Research Foundation of Korea (NRF) and the Ministry of Education (government) (Project ID: 1345376707; Project No.: 2022-0-01182; Research Project Name: University Innovation Support; Research Project Name: Artificial Intelligence Semiconductor Convergence Human Resources Training (Sungkyunkwan University); Research Period: March 1, 2023 - February 29, 2024).

[0006] - This research project was conducted with the support of the National IT Industry Promotion Agency (NIPA) and the Ministry of Science and ICT (Government) (Project ID: 1711193550; Project No.: 2021-0-00863; Research Project Name: Development of New Concept PIM Semiconductor Technology; Research Project Name: Development of Intelligent In-Memory Error Correction Device for High-Reliability Memory; Research Period: January 1, 2023 - December 31, 2023).

[0007] For reference, this application claims priority to Korean Patent Application No. 10-2024-0051623, filed April 17, 2024, Korean Patent Application No. 10-2024-0051648, filed April 17, 2024, and Korean Patent Application No. 10-2024-0080973, filed June 21, 2024. The entire contents of these priority applications are incorporated herein by reference.

[0008] The number of CPU cores installed in data centers' central processing units (CPUs) is steadily increasing. Intel Sierra Forest, featuring 144 cores, has already been announced, and according to an IEEE roadmap, a CPU with 640 cores is projected to be developed by 2037.

[0009] As the number of cores increases, cache capacity must also increase accordingly. Cache has a critical impact on CPU performance, and most CPUs use approximately 2-4MB of last-level cache (LCC) per core. To maintain this ratio as core counts increase, the total amount of LLC required per CPU must reach 1.2GB to 2.4GB.

[0010] Since implementing such a high-capacity cache with SRAM requires a large number of SRAMs, caches based on DRAM (hereinafter referred to as “DRAM caches”) that provide higher integration have begun to appear.

[0011] However, since DRAM was originally designed as main memory, using existing DRAM as a cache results in serious inefficiencies in terms of performance and energy consumption. If the main storage space provided in the DRAM cache is completely filled with stored data, the DRAM cache module sends a miss response when a data write is attempted. At this time, the cache controller checks all main storage spaces of the DRAM cache and allows the DRAM cache module to write data only after retrieving the data stored in the corresponding area of ​​the main storage space.

[0012] Meanwhile, some memory devices search their entire storage for a user-supplied search term, returning the address where the search term is located and, in some cases, data associated with the search term. Furthermore, some applications require that a search term be searched only within a specific region of memory, rather than the entire memory area. For example, a set-associative cache does not need to compare a requested memory address with all stored addresses, but only with addresses within a specific set. Similarly, an in-memory database may store keys in a specific region and compare keys only between values ​​with the same hash value, rather than comparing them across all stored keys.

[0013] Therefore, for these applications, it would be overkill to include a comparison circuit corresponding to each cell to perform a search across all regions of memory.

[0014] According to one embodiment, by providing a DRAM element and a semiconductor device and an operating method thereof that determine within the DRAM whether to perform an operation for writing or reading, efficiency in terms of performance and energy consumption is improved.

[0015] According to another embodiment, a memory device and a semiconductor device, and an operating method thereof, are provided, which can temporarily store data to be evicted by writing from a main storage space of a memory device such as a DRAM cache in a buffer and then provide it to the outside according to a command.

[0016] According to another embodiment, a memory device and a method of operating the same are provided, in which cells corresponding to at least two electrode lines share a comparison circuit.

[0017] The problems to be solved by the present invention are not limited to those mentioned above, and other problems to be solved that are not mentioned will be clearly understood by a person having ordinary skill in the art to which the present invention pertains from the description below.

[0018] According to a first aspect, a memory device includes an address cell storing all or part of an address; a data cell storing data; and a comparison circuit comparing an address stored in the address cell with an address requested externally within a subarray, and performing data writing or reading for the data cell at a corresponding position based on the comparison result, wherein a hierarchical distribution of the memory device has a channel, a rank, a chip, a bank group, and the subarray, and the subarray includes a plurality of MATs (memory array tiles), at least one of the plurality of MATs is a metadata MAT, and the metadata MAT includes the comparison circuit performing tag matching.

[0019] According to a second aspect, a method of operating a memory device according to the first aspect comprises: a step of comparing an address stored in an address cell with an externally requested address within a subarray; and a step of performing data writing or reading for a data cell at a corresponding position based on a result of the comparison; wherein the hierarchical distribution of the memory device has a channel, a rank, a chip, a bank group, and the subarray, the subarray includes a plurality of MATs, at least one of the plurality of MATs is a metadata MAT, and the metadata MAT includes a comparison circuit that performs the comparison through a tag match.

[0020] According to a third aspect, a semiconductor device includes a DRAM cache driven by a cache memory; and a cache controller controlling the DRAM cache; wherein the cache controller performs a request for writing or reading data to or from the DRAM cache, and the DRAM cache compares an address stored in an address cell with an address according to the request within a subarray, and performs the writing or reading of data to or from a data cell at a corresponding position based on a result of the comparison, wherein a hierarchical distribution of the DRAM cache has a channel, a rank, a chip, a bank group, and the subarray, and the subarray includes a plurality of MATs, at least one of the plurality of MATs is a metadata MAT, and the metadata MAT includes a comparison circuit that performs the comparison through a tag match.

[0021] According to a fourth aspect, a method for driving a semiconductor device includes: a step in which a cache controller controlling a DRAM cache driven by a cache memory performs a request for writing or reading data to or from the DRAM cache; a step in which the DRAM cache compares an address stored in an address cell with an address according to the request within a subarray; and a step in which the DRAM cache performs the writing or reading of data to or from a data cell at a corresponding position according to a result of the comparison; wherein a hierarchical distribution of the DRAM cache has a channel, a rank, a chip, a bank group, and the subarray, the subarray includes a plurality of MATs, at least one of the plurality of MATs is a metadata MAT, and the metadata MAT includes a comparison circuit that performs the comparison through a tag match.

[0022] According to a fifth aspect, a memory device driven by cache memory includes a victim buffer for temporarily storing data; and a main storage space; and stores data evicted from the main storage space by a write request in the victim buffer, reports whether the eviction has occurred to an external party, and provides the data stored in the victim buffer to an external party according to an external command.

[0023] According to a sixth aspect, a method of operating a memory device driven by cache memory includes: a step of temporarily storing data evicted from a main storage space by a write request in a victim buffer; a step of reporting whether or not the evicting has occurred to an external party; and a step of providing the data stored in the victim buffer to an external party according to an external command.

[0024] According to a seventh aspect, a semiconductor device includes a memory element driven by a cache memory, including a victim buffer for temporarily storing data and a main storage space; and a cache controller for controlling the memory element; wherein the memory element stores data evicted from the main storage space by a write request of the cache controller in the victim buffer and reports whether or not the evicting has occurred to the cache controller; and the cache controller transmits a command to the memory element in response to the report to receive the data stored in the victim buffer.

[0025] According to the eighth viewpoint, a method for driving a semiconductor device includes: a step of storing data evicted from a main storage space by a memory element in a victim buffer by a write request from a cache controller; a step of reporting, by the memory element, whether or not the evicting has occurred to the cache controller; and a step of transmitting, by the cache controller, a command corresponding to the report to the memory element, thereby receiving the data stored in the victim buffer.

[0026] According to a ninth aspect, a memory device comprises: a first cell array and a second cell array, each including a plurality of cell groups, each of which stores a different one of a key value and a data value in the cell groups; a plurality of first electrode lines capable of selecting a first cell group from among the cell groups included in the first cell array and a second cell group from among the cell groups included in the second cell array; a plurality of second electrode lines to which values ​​of the selected first cell groups of the first cell array are transmitted; a plurality of third electrode lines to which values ​​of the selected second cell groups of the second cell array are transmitted; a plurality of fourth electrode lines to which input key values ​​are transmitted; a comparison circuit for outputting a result of comparing a value transmitted to the second electrode lines with a value transmitted to the fourth electrode lines; and a selection circuit for selecting and outputting at least some of the values ​​transmitted to the third electrode lines according to an output value of the comparison circuit; wherein at least two of the plurality of second electrode lines share the comparison circuit.

[0027] According to a tenth aspect, a memory device comprises: a first cell array and a second cell array, each including a plurality of cell groups, wherein different ones of key values ​​and data values ​​are stored in the cell groups; a plurality of first electrode lines capable of selecting a first cell group from among the cell groups included in the first cell array and a second cell group from among the cell groups included in the second cell array; a plurality of second electrode lines to which values ​​of the selected first cell groups of the first cell array are transmitted; a plurality of third electrode lines to which values ​​of the selected second cell groups of the second cell array are transmitted; a plurality of fourth electrode lines to which input key values ​​are transmitted; a comparison circuit for outputting a result of comparing a value transmitted to the second electrode line with a value transmitted to the fourth electrode line; And a selection circuit that selects and outputs at least some of the values ​​transmitted to the third electrode line according to the output value of the comparison circuit; wherein the comparison circuit outputs values ​​for match or mismatch through a plurality of match lines, and the selection circuit selects and outputs some of the values ​​transmitted to the third electrode line according to the values ​​of the plurality of match lines.

[0028] According to an eleventh aspect, a method of operating a memory device according to the ninth aspect includes: selecting the first cell group and the second cell group through at least one of the plurality of first electrode lines; comparing a value transmitted to the second electrode line with a value input to the fourth electrode line through a comparison circuit shared by at least two of the plurality of second electrode lines; and selecting and outputting at least some of the values ​​transmitted to the third electrode line according to an output value of the comparison circuit.

[0029] According to a twelfth aspect, a method of operating a memory device according to the tenth aspect comprises: selecting the first cell group and the second cell group through at least one of the plurality of first electrode lines; comparing a value transmitted to the second electrode line with a value input to the fourth electrode line through the comparison circuit; and selecting and outputting at least some of the values ​​transmitted to the third electrode line according to an output value of the comparison circuit; wherein the comparison circuit outputs a match or mismatch between the value transmitted to the second electrode line and the value transmitted to the fourth electrode line, and the selection circuit outputs a value in the case of a match but does not output a value in the case of a mismatch.

[0030] In one embodiment, a decision is made within the DRAM whether to perform a write or read operation. This has the effect of improving the efficiency in terms of performance and energy consumption of the DRAM element and / or semiconductor device including the same.

[0031] In another embodiment, data to be written from the main storage space of a memory device, such as a DRAM cache, is temporarily stored in a buffer and then provided externally according to a command. This improves write speed, resulting in improved performance and energy efficiency of the memory device, compared to prior art where the cache controller only allowed data writing after retrieving data stored in the corresponding area of ​​the main storage space.

[0032] In another embodiment, a memory device is provided in which cells corresponding to at least two electrode lines share a comparison circuit.

[0033] Some central processing units (CPUs) use content addressable memory (CAM) in their L1 caches. In this case, the area of ​​the L1 cache is reduced by the shared compare circuit, which ultimately reduces the area of ​​the CPU. Even though applying CAM to the L2 / L3 caches could improve the performance of the CPU, the need for a compare circuit for each cell presents a stumbling block, so CAM was not applied. However, since the area of ​​the L2 / L3 caches can also be reduced by the shared compare circuit, applying CAM to the L2 / L3 caches can further improve the performance of the CPU.

[0034] According to another embodiment of the present invention, since the comparison is performed relatively more efficiently compared to a conventional memory element in which a shared comparison circuit is not employed, there is an effect of reducing memory power consumption, which accounts for a large proportion of the total energy consumption.

[0035] FIG. 1 is a schematic diagram showing a memory system including a DRAM cache module according to a first embodiment of the present invention.

[0036] FIG. 2 and FIG. 3 are detailed configuration diagrams of a DRAM cache according to a first embodiment of the present invention, wherein FIG. 2 is a block diagram and FIG. 3 shows the hierarchical order of the architecture.

[0037] FIG. 4 is a block diagram showing a cache set input from a cache controller to a DRAM cache according to a first embodiment of the present invention.

[0038] FIG. 5 is a flowchart for explaining an operating method of a DRAM cache module according to a first embodiment of the present invention.

[0039] FIG. 6 is a schematic diagram showing a memory system including a memory element and a semiconductor device according to a second embodiment of the present invention.

[0040] Figure 7 is a detailed configuration diagram of a memory device according to a second embodiment of the present invention.

[0041] Figure 8 is a flowchart for explaining an operating method of a memory device according to a second embodiment of the present invention.

[0042] Figure 9 is a configuration diagram of a memory device according to a third embodiment of the present invention.

[0043] Figure 10 is a flowchart for explaining a method of driving a memory element according to a third embodiment of the present invention.

[0044] The advantages and features of the present invention, and the methods for achieving them, will become clearer with reference to the embodiments described below together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below and may be implemented in various different forms. These embodiments are provided solely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined solely by the scope of the claims.

[0045] The terms used in this specification will be briefly explained, and the present invention will be described in detail.

[0046] The terms used in this invention have been selected from widely used, current terms, taking into account the functions of the invention. However, these terms may vary depending on the intentions of those skilled in the art, precedents, the emergence of new technologies, etc. Furthermore, in certain cases, terms may be arbitrarily selected by the applicant, in which case their meanings will be described in detail in the relevant description of the invention. Therefore, the terms used in this invention should not be defined simply as names, but rather based on their inherent meanings and the overall content of the invention.

[0047] When a part of a specification is said to 'include' a component, this does not mean that it excludes other components, but rather that it may include other components, unless otherwise stated.

[0048] Below, with reference to the attached drawings, embodiments of the present invention are described in detail so that those skilled in the art can easily practice them. Furthermore, in order to clearly explain the present invention, portions irrelevant to the description are omitted in the drawings.

[0049] <Example 1>

[0050] FIG. 1 is a block diagram showing a memory system including a DRAM cache module according to a first embodiment of the present invention, and FIGS. 2 and 3 are detailed block diagrams of a DRAM cache according to the first embodiment of the present invention, wherein FIG. 2 is a block diagram and FIG. 3 shows a hierarchical distribution of the architecture.

[0051] Referring to FIG. 1, a memory system (1100) may include a host (1110) including a memory controller (1111), a DRAM cache (1120) including a cache controller (1121), and a main memory (1130) connected via a memory bus (1140). Here, the DRAM cache (1120), which is a semiconductor device including the cache controller (1121), may be referred to as a DRAM cache module, but in the following, the cache controller (1121) and the DRAM cache (1120) will be referred to separately to help with understanding the explanation.

[0052] The host (1110) can process data or control components included in the memory system (1100). For example, the host (1110) can run various operating systems (OS) and execute various applications on the operating systems (OS). The host (1110) can write data to the main memory (1130) or read data stored in the main memory (1130). The host (1110) can load data to the main memory (1130) and perform various operations using the loaded data. For example, the host (1110) can include a central processing unit (CPU) that controls the memory system (1100).

[0053] The memory controller (1111) of the host (1110) is intended to control the DRAM cache (1120) and the main memory (1130). The host (1110) can transmit a read request to the memory controller (1111) to read data stored in the main memory (1130). The memory controller (1111) will access the main memory (1130) to read the data requested by the host (1110).

[0054] In particular, the memory controller (1111) uses the DRAM cache (1120) as a cache memory of the main memory (1130). That is, the memory controller (1111) can store data stored in the main memory (1130) in a cache line of the DRAM cache (1120) and access the cache line instead of the main memory (1130).

[0055] The DRAM cache (1120) is a DRAM element that may include an address cell (1122), a data cell (1123), and a comparison circuit (1124), and may be provided as a cache memory of the host (1110).

[0056] The address cell (1122) of the DRAM cache (1120) can store all or part of an address.

[0057] The data cell (1123) of the DRAM cache (1120) can store data.

[0058] The comparison circuit (1124) of the DRAM cache (1120) can compare the address stored in the address cell with an externally requested address within the subarray.

[0059] In this way, the DRAM cache (1120) including the address cell (1122), the data cell (1123), and the comparison circuit (1124) can perform data writing or reading for the data cell (1123) of the corresponding location based on the address comparison result by the comparison circuit (1124). For example, the DRAM cache (1120) can select a specific set by the addresses stored in the address cell (1122) based on the result of comparing the address stored in the address cell (1122) with a part of the requested address, and can determine the corresponding location based on the result of comparing the address stored in the selected specific set with another part of the requested address.

[0060] In addition, the DRAM cache (1120) includes a plurality of cache lines corresponding to specific memory units of the main memory (1130). And the DRAM cache (1120) stores data stored in a specific memory unit of the main memory (1130) in the mapped cache line. For this purpose, the data is provided through the memory bus (1140) in the form of a cache set. In addition, the DRAM cache (1120) and the cache controller (1121) may be connected through a pin (omitted) for signal transmission other than data and address. Then, the result of performing data writing or reading can be transmitted to the outside through the pin, and the host (1110) can access the cache line instead of accessing a specific memory unit of the main memory (1130) to read or write data at high speed.

[0061] The main memory (1130) may be provided as a memory device or memory module including non-volatile memory. The main memory (1130) may include memory devices that are relatively easy to increase in capacity compared to the DRAM cache (1120). The main memory (1130) may include an overwritable non-volatile memory device or a non-overwritable non-volatile memory device. The main memory (1130) may be provided as, for example, a plurality of flash memories. For example, the main memory (1130) may be implemented as various non-volatile memory devices such as an electrically erasable and programmable ROM (EEPROM), a NAND flash memory, a NOR flash memory, a phase change RAM (PRAM), a resistive RAM (ReRAM), a ferroelectric RAM (FRAM), a spin-torque magnetic RAM (STT-MRAM), etc.

[0062] The architectural hierarchy of the DRAM cache (1120) may have a hierarchy of a channel (not shown), a rank (not shown), a chip (not shown), a bank group (1210), and a subarray (1220), similar to a known DRAM architecture, and the subarray (1220) may include a plurality of MATs (memory array tiles) (1221, 1222, …, 1223), and at least one of the plurality of MATs (1221, 1222, …, 1223) may be a metadata MAT (1221), and the metadata MAT (1221) may include a comparison circuit (1124) that performs tag matching, and the remaining MATs may be data MATs (1222, 1223). A DRAM cache (1120) having such a sub-array (1220) structure can perform a read or write operation on a cache set (1300) including metadata (1310) and data (1320) as shown in FIG. 4.

[0063] The DRAM cache (1120) having the sub-array (1220) structure of FIG. 3 receives a request address for writing or reading in units of cells from the cache controller (1121), and in response to the request address, a comparison circuit (1124) performs a tag match within the sub-array (1220), and writes or reads data at the corresponding location according to the result of performing the tag match.

[0064] Here, the DRAM cache (1120) can receive the request address as metadata (1310) in the cache set (1300). To this end, the cache controller (1121) separates the request address into an index address and a tag address, first transmits the index address to the DRAM cache (1120) so that a specific set corresponding to the index address is selected by the DRAM cache (1120), and later transmits the tag address to the DRAM cache (1120) so that the corresponding location corresponding to the tag address is determined by the DRAM cache (1120).

[0065] In addition, when the DRAM cache (1120) needs to overwrite data by writing data to a random address where data is stored, it stores the data stored in the data cell (1123) of the random address in a temporary space (not shown) and transmits to the cache controller (1121) whether or not to store the data in the temporary space through a pin (not shown) for signal transmission other than data and address, and the cache controller (1121) can retrieve the data in the temporary space using a separate command.

[0066] Additionally, the DRAM cache (1120) can transmit the write result according to the performance of the tag match to the cache controller (1121) through a pin (omitted).

[0067] FIG. 5 is a flowchart illustrating an operation method of a DRAM cache module according to one embodiment of the present invention.

[0068] Hereinafter, with reference to FIGS. 1 to 5, a method of operating a DRAM cache module in a memory system including a DRAM cache module according to the first embodiment of the present invention will be described in detail.

[0069] First, the host (1110) can transmit a read request or a write request to the memory controller (1111) to read data stored in the main memory (1130) or to write data to the main memory (1130), and the memory controller (1111) can access the main memory (1130) to process the read request or the write request of the host (1110) (S1410).

[0070] Here, the memory controller (1111) uses the DRAM cache (1120) as a cache memory of the main memory (1130). For example, the memory controller (1111) can store data stored in the main memory (1130) in a cache line of the DRAM cache (1120) and access the cache line instead of the main memory (1130). In this case, data to be stored in the DRAM cache (1120) is provided through the memory bus (1140) in the form of a cache set (1300). At this time, a request address per cell for writing or reading may be provided by being included in the metadata (1310) of the cache set (1300).

[0071] Then, the DRAM cache (1120) performs a tag match by a comparison circuit (1124) within the sub-array (1220) in response to the request address. For example, among multiple MATs (1221, 1222, …, 1223), the metadata MAT (1221) may perform the tag match. To this end, the DRAM cache (1120) may separate the request address into an index address and a tag address (S1420).

[0072] And, the DRAM cache (1120) can perform tag matching on the corresponding index within the sub-array. Here, the DRAM cache (1120) can receive the request address as metadata (1310) within the cache set (1300). To this end, the cache controller (1121) separates the request address into an index address and a tag address, and first transmits the index address to the DRAM cache (1120) so that a specific set corresponding to the index address is selected by the DRAM cache (1120), and later transmits the tag address to the DRAM cache (1120) so that the corresponding location corresponding to the tag address is determined by the DRAM cache (1120) (S1430).

[0073] The DRAM cache (1120) writes or reads data at the corresponding location based on the result of the tag match performed in step S1430, i.e., if it is determined to be a match (S1440). For example, in the case of data writing, among multiple MATs (1221, 1222, …, 1223), the data MAT (1222, …, 1223) can store data (1320) of the cache set (1300) (S1450).

[0074] Additionally, the DRAM cache (1120) provides the result of step S1450 through a pin (not shown) connected between it and the cache controller (1121), which is then transmitted to the memory controller (1111) through the cache controller (1121). As a result, the memory controller (1111) can know the result of reading or writing data by the DRAM cache (1120). For the data, the data stored in the DRAM cache (1120) rather than the data stored in the main memory (1130) can be used.

[0075] Meanwhile, in step S1450, when data needs to be overwritten by writing data to a random address where data is stored, the DRAM cache (1120) stores the data stored in the data cell (1123) of the random address in a temporary space (not shown) and transmits to the cache controller (1121) whether or not to store the data in the temporary space through a pin (not shown) for signal transmission other than data and address, and the cache controller (1121) can retrieve the data in the temporary space using a separate command.

[0076] As described above, according to the first embodiment of the present invention, whether to perform a write or read operation is determined internally within the DRAM. This has the effect of improving efficiency in terms of performance and energy consumption.

[0077] Meanwhile, each step included in the operating method of the DRAM element and / or the operating method of the semiconductor device according to the first embodiment described above can be implemented as a computer program recorded on a recording medium including commands for causing a processor to perform these steps.

[0078] In addition, each step included in the operating method of the DRAM element and / or the operating method of the semiconductor device according to the first embodiment described above can be implemented in a computer-readable recording medium having recorded thereon a computer program including instructions for causing a processor to perform these steps.

[0079] <Example 2>

[0080] FIG. 6 is a schematic diagram showing a memory system including a memory element and a semiconductor device according to a second embodiment of the present invention, and FIG. 7 is a detailed schematic diagram of a memory element according to the second embodiment of the present invention. FIG. 6 illustrates a DRAM cache as an example of the memory element, but the present invention is not limited thereto. For example, the memory element may be an SRAM.

[0081] Referring to FIGS. 6 and 7, a memory system (2100) may include a processor (2110) including a memory controller (2111), a DRAM cache (2120) including a cache controller (2121), and a main memory (2130) connected via a memory bus (2140). Here, the DRAM cache (2120) including the cache controller (2121) may be referred to as a DRAM cache module, but in the following, the cache controller (2121) and the DRAM cache (2120) will be referred to separately to help with understanding the explanation.

[0082] The processor (2110) can process data or control components included in the memory system (2100). For example, the processor (2110) can run various operating systems (OS) and execute various applications on the operating systems (OS). The processor (2110) can write data to the main memory (2130) or read data stored in the main memory (2130). The processor (2110) can load data to the main memory (2130) and perform various operations using the loaded data. For example, the processor (2110) can include a central processing unit (CPU) that controls the memory system (2100).

[0083] The memory controller (2111) of the processor (2110) is for controlling the DRAM cache (2120) and the main memory (2130). The processor (2110) can transmit a read request to the memory controller (2111) to read data stored in the main memory (2130). The memory controller (2111) will access the main memory (2130) to read the data requested by the processor (2110).

[0084] In particular, the memory controller (2111) uses the DRAM cache (2120) as a cache memory of the main memory (2130). That is, the memory controller (2111) can store data stored in the main memory (2130) in a cache line of the DRAM cache (2120) and access the cache line instead of the main memory (2130).

[0085] The DRAM cache (2120) is provided as a cache memory of the processor (2110). The DRAM cache (2120) includes a main storage space (123) having a plurality of cache lines corresponding to specific memory units of the main memory (2130). The DRAM cache (2120) stores data stored in a specific memory unit of the main memory (2130) in a mapped cache line of the main storage space (2123). To this end, the data is provided in the form of a cache set through the memory bus (2140). Then, the processor (2110) can access the cache line of the main storage space (2123) to read or write data at high speed instead of accessing a specific memory unit of the main memory (2130).

[0086] The DRAM cache (2120) further includes a victim buffer (2122) for temporarily storing data. The cache controller (2121) stores data evicted from the main storage space (2123) by writing in the victim buffer (2122), reports the current status of the victim buffer (2122) (i.e., whether data from the main storage space (2123) has been evicted) to the outside, and provides the data stored in the victim buffer (2122) to the outside of the DRAM cache (2120) according to a command of the processor (2110).

[0087] This DRAM cache (2120) may further include a pin (2124) provided for signal transmission other than data and address between the cache controller (2121) and the DRAM cache (2120) and the processor (2110), and may report to the processor (2110) whether data has been evicted from the main storage space (2123) through the pin (2124).

[0088] The main memory (2130) may be provided as a memory device or memory module including non-volatile memory. The main memory (2130) may include memory devices that are relatively easy to increase in capacity compared to the DRAM cache (2120). The main memory (2130) may include an overwritable non-volatile memory device or a non-overwritable non-volatile memory device. The main memory (2130) may be provided as, for example, a plurality of flash memories. For example, the main memory (2130) may be implemented as various non-volatile memory devices such as an electrically erasable and programmable ROM (EEPROM), a NAND flash memory, a NOR flash memory, a phase change RAM (PRAM), a resistive RAM (ReRAM), a ferroelectric RAM (FRAM), a spin-torque magnetic RAM (STT-MRAM), etc.

[0089] FIG. 8 is a flowchart for explaining an operating method of a DRAM cache module according to a second embodiment of the present invention.

[0090] Hereinafter, with reference to FIGS. 6 to 8, the method of operating the DRAM cache module in a memory system including the DRAM cache module according to the second embodiment of the present invention will be described in detail.

[0091] First, the processor (2110) can transmit a read request or a write request to the memory controller (2111) to read data stored in the main memory (2130) or to write data to the main memory (2130), and the memory controller (2111) can access the main memory (2130) to process the read request or the write request.

[0092] Here, the memory controller (2111) uses the DRAM cache (2120) as a cache memory of the main memory (2130). For example, the memory controller (2111) can store data stored in the main memory (2130) in a cache line within the main storage space (2123) of the DRAM cache (2120), and access the cache line within the main storage space (2123) instead of the main memory (2130). In this case, data to be stored in the DRAM cache (2120) can be provided through the memory bus (140) in the form of a cache set. This can be said to be a state in which the cache controller (2121) of the DRAM cache module (2120) is ready to write data to the cache line within the main storage space (2123) of the DRAM cache (2120) (S2301).

[0093] In addition, the cache controller (2121) checks whether there is data to be evicted from the main storage space (2123) when performing data writing (S2302). At this time, the data that can be evicted is stored in the victim buffer (2122) (S2303), and the current status of the victim buffer (2122) is cache-reported to the processor (2110). Here, the cache controller (2121) can perform a cache report through a pin (2124) provided between the DRAM cache module (2120) and the processor (2110) (S2304).

[0094] Then, the memory controller (2111) of the processor (2110) transmits a command to the DRAM cache module (2120) to transmit data stored in the victim buffer (2122), and the cache controller (2121) provides the data stored in the victim buffer (2122) to the outside of the DRAM cache module (2120) according to the command (S2305).

[0095] If there is no data to be evicted by writing in step S2302 and after providing data stored in the big team buffer (2122) to the outside in step S2305, the cache controller (2121) performs writing of the data prepared in step S2301 to a cache line in the main storage space (2123) of the DRAM cache (2120) (S2306).

[0096] If step S2306 is performed without performing steps S2303 to S2305 even though there is data to be evicted from the DRAM cache (2120) by data writing, the data will be evicted from the DRAM cache module (2120). In this case, if the processor (2110) wishes to use the data, it must access the main memory (2130). In contrast, if the steps S2303 to S2305 are performed, the data provided from step S2305 can be stored in internal memory, etc., and in this case, there is no need to access the main memory (2130) when wishing to use the data.

[0097] As described so far, according to the second embodiment of the present invention, data to be written out of the main storage space of a memory device such as a DRAM cache is temporarily stored in a buffer and then provided externally according to a command. Accordingly, compared to the prior art in which the cache controller allowed data writing only after retrieving data stored in a corresponding area of ​​the main storage space, the write speed is improved, resulting in improved efficiency in terms of performance and energy consumption of the DRAM cache.

[0098] Meanwhile, each step included in the operating method of the memory element and / or semiconductor device according to the second embodiment described above can be implemented as a computer program recorded on a recording medium including commands for causing a processor to perform these steps.

[0099] In addition, each step included in the operating method of the memory element and / or semiconductor device according to the second embodiment described above can be implemented in a computer-readable recording medium having recorded thereon a computer program including instructions for causing a processor to perform these steps.

[0100] <Example 3>

[0101] Figure 9 is a configuration diagram of a memory device according to a third embodiment of the present invention.

[0102] Referring to FIG. 9, a memory device (3100) according to a third embodiment includes a first cell array (3110), a second cell array (3120), a plurality of first electrode lines (3130), a plurality of second electrode lines (3140), a plurality of third electrode lines (3150), a plurality of fourth electrode lines (3160), a comparison circuit (3170), and a selection circuit (3180). For example, the first electrode line (3130) may be a word line, the second electrode line (3140) and the third electrode line (3150) may be bit lines, and the fourth electrode line (3160) may be a query line.

[0103] The first cell array (3110) includes cells (3101) at each intersection of the first electrode line (3130) and the second electrode line (3140), and the second cell array (3120) includes cells (3101) at each intersection of the first electrode line (3130) and the third electrode line (3150).

[0104] By applying a signal to a plurality of first electrode lines (3130), some cells of the first cell array (3110) and some cells of the second cell array (3120) can be selected, and cells that can be selected together by one first electrode line (3130) can be referred to as a first cell group (3111) and a second cell group (3121).

[0105] A plurality of first electrode lines (3130) can select a first cell group (3111) among the cell groups included in the first cell array (3110) and also select a second cell group (3121) among the cell groups included in the second cell array (3120).

[0106] The first cell array (3110) and the second cell array (3120) each include a plurality of cell groups, and different ones of key values ​​and data values ​​are stored in each cell group. For example, a key value may be stored in a cell group of the first cell array (3110), and a data value may be stored in a cell group of the second cell array (3120). For example, the first cell array (3110) and the second cell array (3120) may be configured as DRAM or SRAM.

[0107] The values ​​of the selected first cell group (3111) of the first cell array (3110) are transmitted to the plurality of second electrode lines (3140).

[0108] The values ​​of the selected second cell group (3121) of the second cell array (3120) are transmitted to the plurality of third electrode lines (3150).

[0109] The input key values ​​are transmitted to a plurality of fourth electrode lines (3160). For example, the values ​​for selecting the first cell group (3111) and the second cell group (3121) and the values ​​to be transmitted to the fourth electrode line (3160) can be input in a distinguishable manner.

[0110] The comparison circuit (3170) outputs the result of comparing the value transmitted to the second electrode line (3140) with the value transmitted to the fourth electrode line (3160). For example, the comparison circuit (3170) can output values ​​for match or mismatch through multiple match lines.

[0111] The selection circuit (3180) selects and outputs at least some of the values ​​transmitted to the third electrode line (3150) according to the output value of the comparison circuit (3170). For example, the selection circuit (3180) may select and output some of the values ​​transmitted to the third electrode line (3150) according to the values ​​of a plurality of match lines by the comparison circuit (3170).

[0112] Although FIG. 9 illustrates an example in which the first cell array (3110) shares one comparison circuit (3170), the present invention is not limited thereto. For example, the second electrode lines (3140) may be grouped into two or more groups, and each of the grouped second electrode lines (3140) may share a different comparison circuit.

[0113] Figure 10 is a flowchart for explaining a method of driving a memory element according to a third embodiment of the present invention.

[0114] Hereinafter, with reference to FIGS. 9 and 10, the operating method of the memory device according to the third embodiment of the present invention will be described in detail. In the following description, to help understand the explanation, an example will be described in which the first electrode line (3130) is a word line, the second electrode line (3140) and the third electrode line (3150) are bit lines, and the fourth electrode line (3160) is a query line.

[0115] First, a signal for selecting a word line (3130) is input, and a key value is input through a query line (3160). Then, the first cell group (3111) of the first cell array (3110) is selected, and the second cell group (3121) of the second cell array (3120) is selected. Here, the signal for selecting a word line (3130) and the key value input through the query line (3160) may be input in a distinguishable state, bundled together, or input separately in a distinguishable state (S3210).

[0116] Then, the key values ​​stored in the first cell group (3111) of the first cell array (3110) are transmitted to the bit line (3140) and provided to the comparison circuit (3170), and the data values ​​stored in the second cell group (3121) of the second cell array (3120) are transmitted to the bit line (3150) and provided to the selection circuit (3180).

[0117] Here, the comparison circuit (3170) compares the key value of the bit line (3140) with the key value of the query line (3160), and provides the comparison result to the selection circuit (3180) through multiple match lines (S3220).

[0118] Then, the selection circuit (3180) selects and outputs some of the values ​​transmitted to the bit line (3150) according to the output value of the comparison circuit (3170). Here, the selection circuit (3180) can select and output some of the values ​​transmitted to the bit line (3150) according to the values ​​of the plurality of match lines by the comparison circuit (3170). For example, the comparison circuit (3170) can output a status value for a match or a mismatch through the plurality of match lines (S3230), and the selection circuit (3180) can output a value in case of a match but not output a value in case of a mismatch (S3240).

[0119] As described so far, in the memory device according to the third embodiment of the present invention, cells corresponding to at least two electrode lines share a comparison circuit.

[0120] According to the third embodiment of the present invention, since the comparison is performed relatively more efficiently compared to conventional memory elements that do not share a comparison circuit, there is an effect of reducing memory power consumption, which accounts for a large proportion of the overall energy consumption.

[0121] Meanwhile, each step included in the operating method of the memory device according to the third embodiment described above can be implemented as a computer program recorded on a recording medium including commands for causing a processor to perform these steps.

[0122] Additionally, each step included in the operating method of the memory device according to the third embodiment described above can be implemented in a computer-readable recording medium having recorded thereon a computer program including instructions for causing a processor to perform these steps.

[0123] The combinations of each step of the flowcharts attached to the present invention of the first to third embodiments may be performed by computer program instructions. These computer program instructions may be installed in a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing equipment, so that the instructions executed by the processor of the computer or other programmable data processing equipment create a means for performing the functions described in each step of the flowchart. These computer program instructions may also be stored in a computer-usable or computer-readable recording medium that can direct a computer or other programmable data processing equipment to implement a function in a specific manner, so that the instructions stored in the computer-usable or computer-readable recording medium can also produce a manufactured article that includes an instruction means for performing the functions described in each step of the flowchart. Since the computer program instructions can also be installed on a computer or other programmable data processing device, a series of operational steps can be performed on the computer or other programmable data processing device to create a computer-executable process, and the instructions that cause the computer or other programmable data processing device to perform can also provide steps for performing the functions described in each step of the flowchart.

[0124] Additionally, each step may represent a module, segment, or portion of code that includes one or more executable instructions for performing a specific logical function(s). It should also be noted that in some alternative embodiments, the functions described in the steps may occur out of order. For example, two steps depicted in succession may actually be performed substantially concurrently, or the steps may sometimes be performed in reverse order, depending on the corresponding function.

[0125] The above description is merely an illustrative illustration of the technical idea of ​​the present invention, and those skilled in the art will appreciate that various modifications and variations can be made without departing from the essential quality of the present invention. Therefore, the embodiments disclosed in the present invention are intended to illustrate, rather than limit, the technical idea of ​​the present invention, and the scope of the technical idea of ​​the present invention is not limited by these embodiments. The scope of protection of the present invention should be interpreted by the following claims, and all technical ideas within a scope equivalent thereto should be interpreted as being included in the scope of the rights of the present invention.

Claims

1. As a memory device, An address cell that stores all or part of an address; Data cells that store data; and A comparison circuit that compares the address stored in the above address cell with an address requested from outside within a subarray; According to the above comparison result, data writing or reading is performed for the data cell at the corresponding location. The hierarchical distribution of the memory element has a channel, a rank, a chip, a bank group, and the subarray, and the subarray includes a plurality of MATs (memory array tiles), at least one of the plurality of MATs is a metadata MAT, and the metadata MAT includes the comparison circuit that performs tag matching. Memory device.

2. In paragraph 1, Selecting a specific set by the addresses stored in the address cell based on the result of comparing the addresses stored in the address cell with a part of the requested address, and determining the corresponding location based on the result of comparing the addresses stored in the selected specific set with another part of the requested address. Memory device.

3. In paragraph 1, Includes additional pins for transmitting signals other than data and addresses, The result of writing or reading the above data is transmitted externally through the above pin. Memory device.

4. As an operating method of a memory device, A step of comparing the address stored in the address cell with an externally requested address within the subarray; and A step of performing data writing or reading for the data cell at the corresponding location according to the above comparison result; including; The hierarchical distribution of the memory element has a channel, a rank, a chip, a bank group and the subarray, and the subarray includes a plurality of MATs, at least one of the plurality of MATs is a metadata MAT, and the metadata MAT includes a comparison circuit that performs the comparison through a tag match. How memory devices work.

5. In paragraph 4, The above comparing steps are: A step of selecting a specific set by the addresses stored in the address cell based on the result of comparing the addresses stored in the address cell with a part of the requested address; and A step of determining the corresponding location based on the result of comparing the address stored in the selected specific set with another part of the requested address; How memory devices work.

6. In paragraph 4, The step of performing the above data writing or reading is to determine the corresponding location within a pre-selected set of address sets that can be selected based on the address stored in the address cell. How memory devices work.

7. In paragraph 4, The step of performing the above data writing or reading is: If the target address of the data write according to the above comparison result does not exist, a step of storing the data stored in the data cell of an arbitrary address in a temporary space; and A step of performing data writing corresponding to the requested address into the data cell of the above random address; How memory devices work.

8. In paragraph 7, A step of transmitting to the outside whether data is stored in the temporary space through a pin for transmitting signals other than data and addresses; further comprising; How memory devices work.

9. DRAM cache driven by cache memory; and A cache controller that controls the above DRAM cache; The cache controller performs a request to write or read data to the DRAM cache, The above DRAM cache compares the address stored in the address cell with the address according to the request within the subarray, and performs data writing or reading for the data cell at the corresponding location based on the result of the comparison. The hierarchical distribution of the DRAM cache has a channel, a rank, a chip, a bank group, and the subarray, and the subarray includes a plurality of MATs, at least one of the plurality of MATs is a metadata MAT, and the metadata MAT includes a comparison circuit that performs the comparison through a tag match. Semiconductor devices.

10. In paragraph 9, The cache controller separates the address according to the request into an index address and a tag address, first transmits the index address to the DRAM cache so that a specific set corresponding to the index address is selected by the DRAM cache, and later transmits the tag address to the DRAM cache so that the corresponding location corresponding to the tag address is determined by the DRAM cache. Semiconductor devices.

11. In paragraph 9, The above DRAM cache stores the data stored in the data cell of the random address in a temporary space when the data needs to be overwritten by writing the data to the random address where the data is stored, and transmits to the cache controller whether or not the data is stored in the temporary space through a pin for signal transmission other than data and address. The above cache controller uses a separate command to retrieve data from the temporary space. Semiconductor devices.

12. A method for driving a semiconductor device, A step in which a cache controller controlling a DRAM cache driven by cache memory performs a request for writing or reading data to the DRAM cache; A step of comparing the address stored in the address cell of the above DRAM cache with the address according to the request within the subarray; and A step in which the above DRAM cache performs data writing or reading for the data cell of the corresponding location according to the comparison result; The hierarchical distribution of the DRAM cache has a channel, a rank, a chip, a bank group, and the subarray, and the subarray includes a plurality of MATs, at least one of the plurality of MATs is a metadata MAT, and the metadata MAT includes a comparison circuit that performs the comparison through a tag match. Method for driving a semiconductor device.

13. In paragraph 12, The cache controller separates the address according to the request into an index address and a tag address, first transmits the index address to the DRAM cache so that a specific set corresponding to the index address is selected by the DRAM cache, and later transmits the tag address to the DRAM cache so that the corresponding location corresponding to the tag address is determined by the DRAM cache. Method for driving a semiconductor device.

14. In paragraph 12, The above DRAM cache stores the data stored in the data cell of the random address in a temporary space when the data needs to be overwritten by writing the data to the random address where the data is stored, and transmits to the cache controller whether or not the data is stored in the temporary space through a pin for signal transmission other than data and address. The above cache controller uses a separate command to retrieve data from the temporary space. Method for driving a semiconductor device.

15. As a memory device driven by cache memory, A victim buffer that temporarily stores data; and Includes main storage space; Stores data evicted from the main storage space by a write request in the big team buffer, reports whether the eviction has occurred to the outside, and provides data stored in the big team buffer to the outside according to an external command. Memory device.

16. In paragraph 15, Includes additional pins for transmitting signals other than data and addresses, Reporting the above expulsion to the outside through the above pin Memory device.

17. A method of operating a memory device driven by cache memory, A step of temporarily storing data evicted from the main storage space by a write request in a big team buffer; A step of reporting to the outside whether the above expulsion has occurred; and A step of providing data stored in the big team buffer to the outside according to an external command; How memory devices work.

18. In paragraph 17, Reporting to the outside whether the above extraction has occurred through a pin for signal transmission other than data and address. How memory devices work.

19. Memory elements driven by cache memory, including a big team buffer for temporary storage of data and main storage space; and A cache controller that controls the above memory element; The memory device stores data evicted from the main storage space by a write request of the cache controller in the big buffer, and reports whether or not the evicting has occurred to the cache controller. The cache controller, in response to the report, transmits a command to the memory element to receive data stored in the big team buffer. Semiconductor devices.

20. In paragraph 19, The above memory element reports whether the eviction has occurred through a pin for signal transmission other than data and address. Semiconductor devices.

21. A method for driving a semiconductor device, A step of storing data evicted from the main storage space by a write request from a cache controller in a big buffer; a step of reporting to the cache controller whether the memory element has been evicted; and A step in which the cache controller transmits a command corresponding to the report to the memory element to receive data stored in the big team buffer; Method for driving a semiconductor device.

22. In paragraph 21, The above memory element reports whether the eviction has occurred through a pin for signal transmission other than data and address. Method for driving a semiconductor device.

23. A first cell array and a second cell array, each including a plurality of cell groups, wherein different ones of key values ​​and data values ​​are stored in each of the cell groups; A plurality of first electrode lines capable of selecting a first cell group from among the cell groups included in the first cell array and selecting a second cell group from among the cell groups included in the second cell array; A plurality of second electrode lines through which values ​​of the selected first cell group of the first cell array are transmitted; A plurality of third electrode lines to which values ​​of the selected second cell group of the second cell array are transmitted; A plurality of fourth electrode lines through which the input key value is transmitted; A comparison circuit that outputs the result of comparing the value transmitted to the second electrode line with the value transmitted to the fourth electrode line; and A selection circuit that selects and outputs at least some of the values ​​transmitted to the third electrode line according to the output value of the comparison circuit; Two or more of the plurality of second electrode lines share the comparison circuit. Memory device.

24. In paragraph 23, The first electrode line is a word line, the second electrode line and the third electrode line are bit lines, and the fourth electrode line is a query line. Memory device.

25. In paragraph 23, The first cell array and the second cell array are composed of DRAM or SRAM. Memory device.

26. A first cell array and a second cell array, each including a plurality of cell groups, wherein different ones of key values ​​and data values ​​are stored in each of the cell groups; A plurality of first electrode lines capable of selecting a first cell group from among the cell groups included in the first cell array and selecting a second cell group from among the cell groups included in the second cell array; A plurality of second electrode lines through which values ​​of the selected first cell group of the first cell array are transmitted; A plurality of third electrode lines to which values ​​of the selected second cell group of the second cell array are transmitted; A plurality of fourth electrode lines through which the input key value is transmitted; A comparison circuit that outputs the result of comparing the value transmitted to the second electrode line with the value transmitted to the fourth electrode line; and A selection circuit that selects and outputs at least some of the values ​​transmitted to the third electrode line according to the output value of the comparison circuit; The above comparison circuit outputs values ​​for match or mismatch through multiple match lines, The above selection circuit selects and outputs some of the values ​​transmitted to the third electrode line according to the values ​​of the plurality of match lines. Memory device.

27. In paragraph 26, The values ​​for selecting the first cell group and the second cell group and the values ​​to be transmitted to the fourth electrode line are input in a distinguishable state. Memory device.

28. As an operating method of the memory device of Article 26, A step of selecting the first cell group and the second cell group through at least one of the plurality of first electrode lines; A step of comparing the value transmitted to the second electrode line and the value input to the fourth electrode line through a comparison circuit shared by two or more of the plurality of second electrode lines; and A step of selecting and outputting at least some of the values ​​transmitted to the third electrode line according to the output value of the comparison circuit; How memory devices work.

29. In paragraph 28, The first electrode line is a word line, the second electrode line and the third electrode line are bit lines, and the fourth electrode line is a query line. How memory devices work.

30. In paragraph 28, The first cell array and the second cell array are composed of DRAM or SRAM. How memory devices work.

31. As an operating method of the memory element of Article 26, A step of selecting the first cell group and the second cell group through at least one of the plurality of first electrode lines; A step of comparing the value transmitted to the second electrode line and the value input to the fourth electrode line through the comparison circuit; and A step of selecting and outputting at least some of the values ​​transmitted to the third electrode line according to the output value of the comparison circuit; The above comparison circuit outputs a match or mismatch between the value transmitted to the second electrode line and the value transmitted to the fourth electrode line, and the selection circuit outputs a value in the case of a match, but does not output a value in the case of a mismatch. How memory devices work.

32. In paragraph 31, The above comparison circuit outputs a status value for the match or the mismatch. How memory devices work.

33. In paragraph 31, The values ​​for selecting the first cell group and the second cell group and the values ​​to be transmitted to the fourth electrode line are input in a distinguishable state. How memory devices work.

Images