Clock and data recovery (CDR) circuitry utilizing blind sampling

Abstract

A method, system, and apparatus for digital clock and data recovery (CDR) with analog signal that samples blindly (i.e., independent of the baud rate). The CDR further has a digital monolithic circuit that includes an interpolator circuit, and a fully digital clock (FDC) that recovers the digital data from the analog signal.

Description

A orney Docket No.: 11744 002WO1Clock and Data Recovery (CDR) Circuitry U lizing Blind Sampling

[0001] CROSS REFERENCE TO RELATED APPLICATION

[0002] This applica on claims priority to U.S. Provisional Patent Applica on No. 63 / 634,616,led April 16, 2024, en tled “Clock and Data Recovery (CDR) Circuitry U lizing Blind Sampling,”which is expressly incorporated herein by reference in its en rety.

[0003] BACKGROUND

[0004] Test and measurement equipment, including oscilloscopes and protocol analyzersand exercisers are used to debug and test the func onality of various communica on channels (e.g.,PCI Express, MIPI M PHY / UniPro, JEDEC UFS, USB, or wireless networks) that allow components andsub systems to exchange commands and data. The protocol analyzer observes data tra c oncommunica on channels and provides insights into the behavior of devices communica ng overthese channels. Over the years, both the underlying PHY layers and the protocols have evolved, butthe use of protocol analyzers, however, has remained substan ally the same. For protocol analyzers,which capture data being communicated along a communica on channel, the “capture session” maybe ini ated by a user, by iden fying an occurrence in the transmi ed informa on (a “trigger event”)that triggers the device to start capture, or by external devices through pre de ned applica onprogramming interfaces (APIs).

[0005] Figure 1 illustrates a conven onal clock and data recovery (CDR) recovery circuitry100 for serial protocols. A CDR is used in conjunc on with a SERDES, serializer / deserializer, which isan integrated circuit that converts serial data to parallel data, and vice versa. A CDR and SERDES areused for many serial protocols, such as PCI Express, MIPI M PHY, IEEE 802.3, OIF CEI and may be usedin conjunc on with a protocol analyzer. The protocol analyzer captures an analog signal (e.g., a datastream) from the communica on channel of interest that is input to the CDR recovery circuitry. Thisanalog signal may contain informa on bearing transi ons (e.g., data bits, clock edges). A con nuousme linear equalizer (CTLE) and a variable gain ampli er (VGA) 102 par ally equalize the capturedsignal to condi on it for limited analog to digital converter (ADC) dynamic range and resolu on. TheADC 104 samples and quan zes the par ally equalized signal at 1x the symbol rate for furtherequaliza on in a digital signal processor (DSP) 110. A controlled clock source (VCO) 106 or phaseinterpolator (PI) triggers the ADC 104 to align samples with centers of received data symbols. TheVCO 106 generates an oscilla ng signal (usually a sinusoidal waveform) whose frequency iscontrolled by an external voltage.

[0006] The ADC 104 converts analog signals (such as voltage or current) into digitalrepresenta ons. The ADC 104 samples the analog signal, using a clock generated by the VCO 106 andA orney Docket No.: 11744 002WO1converts it into a digital format for further analysis. A digital feed forward equalizer (FFE) 112 anddecision feedback equalizer (DFE) 114 further equalize quan zed samples to prepare samples forerror free data recovery. A phase detector (PD) 116 and loop lter (LF) 118 control a clock source totrack phase of a received signal. Using the synchronized samples, the protocol analyzer reconstructsthe original data, which is then analyzed for errors, ming viola ons, or protocol compliance. Theconven onal CDR 100 of Figure 1 uses phase tracking to maintain synchroniza on with thetransmi ed signal’s phase. In communica on systems, maintaining phase alignment is crucial foraccurate data recovery and error detec on. When analyzing digital signals, the protocol analyzertracks the phase of the clock signal or data transi ons. It ensures that the sampling points aligncorrectly with the signal transi ons.

[0007] A disadvantage of the monolithic implementa on of Figure 1 is the complexity of thephase tracking loop that spans both analog and digital domains, leading to high loop latency andhigher costs.

[0008] Further, there has long been a desire to combine a real me protocol analyzer and areal me oscilloscope in the same instrument. Exis ng oscilloscopes are not protocol aware; in thesense they cannot decode protocols in real me. Most oscilloscopes can process saved data anddecode protocols. Typically, this is done in so ware. Some protocol analyzers include an eye viewerfunc on. The eye viewer constructs a view of the “eye”, much like a sampling oscilloscope would,meaning they are not real me. O en a user is debugging a protocol issue with a protocol analyzer,and they must also use a real me oscilloscope to aid in understanding the issue. This is problema cfor several reasons: the oscilloscope adds cost, me correla ng the oscilloscope with the protocolissue can be di cult, and it o en requires a separate physical connec on, such as an oscilloscopeprobe and a protocol analyzer probe. This is commonly referred to as “double probing”. Since eachprobe adds some load, in the form of capacitance, resistance and inductance, having to “doubleprobe” increases the load placed on the system. The present disclosure is the rst to o er thecapability of a real me oscilloscope and a protocol analyzer in the same instrument. Both func onsare internally me correlated and use the same single physical connec on.

[0009] Oscilloscopes incorporate nite impulse response lters that apply equaliza on inreal me, but without knowledge of the protocol, they are unable to use DFE. Addi onally, they donot have the ability to train an equaliza on algorithm based on an analog input and a protocoldecode. Rather, oscilloscopes perform equaliza on as a post processing so ware step. With thedigital CDR technology, described in detail below, an oscilloscope would have real me feedback ofthe protocol. This would enable real me DFE and training algorithms to be u lized on oscilloscopes.A orney Docket No.: 11744 002WO1

[0010] A further disadvantage of conven onal protocol analyzers, is that they require adedicated applica on speci c integrated circuit (ASIC), called a “PHY” to recover the serial protocolstream. The PHY converts an analog input to a digital output, and it also tracks the current state ofthe protocol and changes its opera on accordingly. Tradi onally, PHYs are monolithic and fullyintegrated in either an ASIC or eld programmable gate array (FPGA).

[0011] In addi on, protocol speci c PHYs are expensive, requiring massive non recurringengineering cost to implement. Protocol speci c PHYs are only good for one genera on of oneprotocol. They must be redesigned for di erent protocols and new genera ons of protocols. Oncethe PHYs are designed, they o er li le to no ability for future modi ca ons. The digital logic cannotbe refactored like it can be in an FPGA. This can prove challenging for companies designing PHYs,especially during the prototyping phases of development. Addi onally, the PHYs cannot be modi edto meet ever changing speci ca ons and user requirements. It should be noted that theselimita ons apply to all PHYs, not just PHYs within protocol analyzers.

[0012] SUMMARY

[0013] Systems and methods are disclosed herein that provide improved techniques for adigital clock and data recovery (CDR) system. In an aspect, the system may include a blind samplingcircuit that includes an analog to digital converter (ADC) and a clock that drives the ADC to samplean incoming analog signal to create a sampled signal; and a digital circuit that op onally includes aninterpolator circuit, a phase detector (PD), a loop lter (LF) and a digital clock (DC), that recovers theprotocol data from the analog signal. A related method of opera ng the CDR system is also disclosed.

[0014] In accordance with an aspect of the present disclosure, there is disclosed a digitalclock and data recovery (CDR) system that includes a blind sampling circuit that receives an inputsampled signal; and a digital monolithic circuit. The digital monolithic circuit includes a phasedetector (PD) that determines a phase error which is used to determine a unit interval (UI) center;and a fully digital clock (FDC) that creates a digital clock used to recover digital data from the inputsampled signal.

[0015] In accordance with another aspect of the disclosure, there is described a method forsampling an analog input signal. The method may include receiving an input sampled signal at a blindsampling circuit; and recovering digital data from the input sampled signal using a phase detector(PD) that determines a phase error which is used to determine a unit interval (UI) center and a fullydigital clock (FDC) that creates a digital clock used to recover digital data from the input sampledsignal

[0016] Addi onal aspects of the present disclosure will become apparent in the followingdiscussion, beginning with reference to the accompanying drawings.A orney Docket No.: 11744 002WO1

[0017] BRIEF DESCRIPTION OF DRAWINGS

[0018] The subject ma er of the present disclosure will be described in even greater detailbelow with reference to the gures. All features described and / or illustrated herein can be usedalone or combined in di erent combina ons. The features and advantages of variousimplementa ons will become apparent by reading the following detailed descrip on with referenceto the a ached drawings, which illustrate the following:

[0019] Figure 1 illustrates example conven onal clock and data recovery (CDR) circuitry thatmay be used in e.g., PCI Express, MIPI M PHY, a protocol analyzer;

[0020] Figure 2 an example of a CDR in accordance with the present disclosure;

[0021] Figure 3 is an example of a fully digital clock (FDC) circuit, implemented with a digitalalgorithm, in accordance with the present disclosure; and

[0022] Figure 4 is an example plot showing a waveform with both blind ADC samples andinterpolated edges and centers.

[0023] DETAILED DESCRIPTION

[0024] INTRODUCTION

[0025] The role of a clock and data recovery (CDR) system is to extract the clock signalembedded in the received data stream and use this ming to recover the data. As described withregard to Figure 1, tradi onal CDR architectures use a feedback path with four primary components:a sampler (ADC or other), a phase detector, a loop lter and a voltage controller oscillator. In thesearchitectures, the sample clock is frequency and / or phase synchronized with the received data.

[0026] Implementa ons of the present disclosure advantageously remove the sample clockfrom the loop, which removes the high latency that is typical in a clock recovery loop. In accordancewith the present disclosure, the ADC sampling clock is free running, with no phase rela onshipbetween the samples or symbol boundaries of the received data. The data is sampled by the ADC ata pre de ned clock frequency (sample rate) that is greater than or equal to the received data baudrate, thus the term “blind sampling.” This allows for coupling of a high performance, low ji er clocksource and an ADC with a much higher resolu on and dynamic range, when compared toconven onal monolithic implementa ons.

[0027] In an aspect, processing by the CDR system of the present disclosure is performed inthe digital domain using the digi zed samples. The CDR feedback loop is implemented en rely in thedigital domain, thus allowing digital logic to act on the ADC samples. FFE, DFE, and phase detec onare completely contained in a digital circuit. The digital logic can be implemented in an ASIC, an FPGAor in so ware. This enables substan al freedom between the input signal, clock source and digitallogic. Further advantages include, but are not limited to, separa on of development and purchasingA orney Docket No.: 11744 002WO1of the ADC and ASIC or FGPA. This aspect of the blind sampling ADC based receivers makes themhighly scalable with the technology nodes, robust to process, voltage and temperature varia ons,and allows for a short design me due to the automa on of the digital design ow.

[0028] FULLY DIGITAL CLOCK (FDC)

[0029] As discussed above, in conven onal systems such as that of Figure 1, the phasedetector’s control signal drives a phase interpolator (PI) or voltage controlled oscillator (VCO). Thepurpose of the PI or VCO block is to provide a sample clock source that has ne control of either itsfrequency and / or phase. This allows the control loop (phase detector (PD) and loop lter (LF)) toadjust the phase of the sample clock (PI or VCO) which tracks the phase of the data being recovered.However, implementa ons of the present disclosure move the sample recovery loop into the digitaldomain.

[0030] The term “fully digital clock” (FDC) is used herein to replace the tradi onal termsVCO and / or PI. In par cular, the “fully digital clock” (FDC 202) replaces the VCO or PI and creates aclock that can be used in the digital domain. For example, as shown in Figures 2 and 3 (described infurther detail below), the edge posi on output of the FDC 202 is used by the interpolator as thesample posi on for each data symbol. Both the frequency and phase of the digital clock can beadjusted with theore cal in nite resolu on (based on the number of bits of resolu on one chooses).The control loop will control the phase of digital clock. A separate loop (not shown) can control thefrequency of the digital clock. The phase and / or frequency can be changed every clock cycle. Thisoutput clock can be any arbitrary frequency and phase and is not related to the clock that is used tocontrol the block, the system clock. The output of the digital clock is the edge posi on of the sampleclock rela ve to the ADC samples. This edge posi on output is the ideal sample posi on. The edgeposi on output is used by the interpolator as the interpola on point, for example, as shown in Figure4.

[0031] In Figure 4, RXin is the analog input signal into the ADC 204. The ADC 204 blindlysamples the signal, indicated by the Si samples, without knowledge of the baud rate or phase. Torecover the clock and data, the FDC 202 interpolates between the blind samples, crea ng a new setof samples, Ii. Every UI has two interpolated samples such that one sample is close to the UI centerwhile the other sample is close to the UI edge. The PD 116 u lizes the interpolated UI edge samplesto determine the phase error, fERR, which represents the devia on of these samples from thesymbol boundaries in RXin. A digital loop lter then derives the average zero crossing phase, fAVG,from fERR. An interpola on index updater translates the recovered fAVG into an interpola on index,m, which adjusts the posi on of the interpolated samples rela ve to the blind samples, ensuring thatIi aligns with the UI boundaries and e ec vely closing the digital feedback loop. The data decisionA orney Docket No.: 11744 002WO1block leverages the interpolated UI center samples to produce the recovered data. The interpolatorwithin the feedback loop allows this CDR architecture to perform phase tracking en rely in the digitaldomain.

[0032] A novel part of the FDC 202 is the fully digital clock is independent of the input signalor ADC sample clock (e.g., CLK 206). For example, at a given system clock, N samples are receivedfrom the ADC. The digital clock will generate M+1 edges based on the frequency of the digital clock,which is the same frequency of the recovered data. Note the + 1 is used to account for non idealclocks. Thus, N / M is the ADC sample to baud rate ra o, where N > M. Below is example that showshow the ADC samples are sampled by the digital clock when the digital clock is in two separatephases rela ve to the ADC samples. For this example, assume N = 10 and M = 5, so the ADC sampleclock is 2 mes the baud rate. In other words, the digital clock frequency is one half of the ADCsample clock. For the purposes of this example, the ADC samples and numbered from 0 to 11; 0 isthe rst sample in me. The input phase adjustments and output digital clock are stated rela ve tothe ADC sample clock.

[0033] State 1 – FDC aligned with ADC: The output of the digital clock is 0,2,4,6,8,10, thisindicates that the ideal edge posi on is at exactly at sample 0, 2, 4, 6, 8 and no interpola on isneeded.

[0034] State 2 – FDC halfway between ADC samples: Star ng at state 1, if the phaseadjusted by one half of a period, 0.5, of the ADC sample clock, the output of the digital clock wouldbe 0.5, 2.5, 4.5, 6.5, 8.5, 10.5. This indicates that the ideal edge posi on is halfway between ADCsample 0 and sample 1, halfway between ADC sample 2 and sample 3, etc. In this case, interpola onis required to determine the value of the sample at the point halfway between the samples.

[0035] It is important to note that the digital CDR operates on any sampled data, not justthat provided by an ADC. In other words, an ADC is not a requirement. Rather, the digital CDR canoperate fully in so ware on any sampled data, such as a simulated waveform or an oscilloscopecapture. Addi onally, the digital CDR can be applied in an oscilloscope, adding protocol analysis toreal me oscilloscope captures. Lastly, an FPGA is not a requirement. Rather, it’s possible to integratethe digital CDR circuitry into a custom ASIC.

[0036] DETAILS OF THE DIGITAL CDR SYSTEM AND METHOD

[0037] With reference to Figure 2, there is illustrated an example digital CDR 200 inaccordance with the present disclosure. Compared to the conven onal CDR 100 of Figure 1, thereare di erences as to how baud rate sampling is achieved. For example, in conven onalimplementa ons, the VCO 106 output is the ideal sample loca on which the ADC uses to recover the“baud” rate sample. However, in the implementa on of Figure 2, the ADC 206 is blind sampling andA orney Docket No.: 11744 002WO1the FDC 202 with interpola on is used to recover the “baud” rate sample. Once the baud ratesamples are recovered the remainder of the blocks (e.g., FFE, DFE, PD, LF) may be usedconven onally. Yet a further di erence from the conven onal CDR 100 of Figure 1 is that the signalpre condi oning blocks, CTLE and VGA 102, are op onal due to a high resolu on and dynamic rangeprovided by the ADC 204 , and a high precision sampling clock 206.

[0038] In the example implementa on of Figure 2, discrete analog circuits may be used toenable a digital monolithic circuit receiver implementa on 201 in an FPGA or ASIC. This enables theuse of an ADC with a much higher resolu on and dynamic range compared to monolithicimplementa on. The ADC 206 may blindly sample at 1x or greater the symbol rate, with no phaserela onship between samples and symbol boundaries. In the example of Figure 2, the ITPL(interpolator) 208, and op onally, a FIFO (shown in 208), add interpolated samples to the data fromthe ADC 204. Digital FFE 112 and / or DFE 114 equalize interpolated samples for error free datarecovery. The fully digital clock (e.g., FDC 202) selects an ideal sample at the symbol rate, such that1x samples are aligned with symbol centers.

[0039] Figure 3 shows addi onal details of blind sampling and the fully digital clock. InFigure 3, the use of discrete blocks allows the use of high performance analog blocks, e.g., the lowji er sampling clock 206, and the high resolu on and high dynamic range ADC 204. The samplingclock 206 operates blindly, i.e., the clock 206 is free running with respect to boundaries of receivedsymbols. As the ADC sampling clock 206 is free running, this allows for a low latency, fully digitalclock recovery loop.

[0040] Referring again to Figure 2, the combina on of FIFO (op onal) and interpolator(ITPL) (op onal) 208, phase detector (PD 116) and FDC 202 e ec vely resample and phase align thesamples in the digital domain. The input to the FDC can use several di erent signals including, butnot limited to, the interpolated, equalized ADC samples, unequalized & non interpolated samples,interpolated and / or equalized samples. The source of recovered clock (FDC 202) is a digital algorithmwith no impairments associated with analog clock sources. Interpolated baud rate and phase alignedsamples allow the use of well established equaliza on algorithms in digital circuits. Sampleequaliza on and phase detec on are completely contained in a digital circuit or an FPGA. As such,the data is sampled “blind” (e.g., in the Blind Sample block 210 of Figure 2) with the highperformance sampling clock 206, opera ng at baud rate or greater.

[0041] The interpolated data is op onally fed to a feed forward equalizer (FFE) 112 and / or adecision feedback equalizer (DFE) 114. These blocks can improve the received signal to mi gatee ects such as channel distor on or intersymbol interference (ISI). Interpolated baud rate andphase aligned samples allow the use of well established equaliza on algorithms in digital circuits,A orney Docket No.: 11744 002WO1such as FFE 112 and DFE 114. Using the blind samples and the FDC 202, the baud rate samples arerecovered via interpola on. In other words, the FDC 202 de nes the ideal sample loca on, andprovides a digital clock. The sample posi on is selected as the ideal posi on between the symbolboundaries.

[0042] The output of the interpolator (FIFO & ITPL) 208, FFE 112, DFE 114 path is fed intothe phase detector (PD) 116. The phase detector 116 determines if the current sample posi on isearly or late compared to the ideal sample posi on and generates an error signal propor onal to thephase di erence. The next stage is the loop lter (LF) 118, which limits how quickly the loop canadjust the phase. The loop lter implementa on manages performance of loop bandwidth, phasenoise, stability, lock me, etc. The combina on of the FIFO (op onal) and interpolator (ITPL) 208e ec vely resamples and phase aligns the sample in the digital domain. The source of the FDC 202is a digital algorithm, which is free from impairments associated with analog clock sources.

[0043] Thus, comparing the CDR 200 of the present disclosure to conven onal CDRs, thereare several di erences: the implementa on is completely digital, the ADC sampled data is alsointerpolated, the ADC blindly samples the data stream at baud rate or greater, sample equaliza onand phase detec on are completely contained in digital circuits, and the PI produces a fully digitalclock, where both frequency and phase can be adjusted.

[0044] Advantages of Implementa ons of the Present Disclosure

[0045] Implementa ons of the present disclosure, using a blind sampling ADC with a freerunning sample clock, and a fully digital clock and data recovery loop (CDR), decouples the ADC fromthe clock recovery loop and allows the digital circuit to be implemented in an ASIC or FPGA. The freerunning sample clock does not have any rela onship to the data clock, in frequency or phase.

[0046] In addi on, below is a non exhaus ve list of the advantages of using blind samplingwith an ADC:

[0047] A real me protocol analyzer and a real me oscilloscope can be realized with thesame hardware. For the end user of the instrument, this simpli es debugging and reduces cost. Realme oscilloscopes typically have a very universal front end that can capture all types of signals. Beingable to u lize this type of front end would allow the protocol analyzer to be just as universal.

[0048] A single protocol analyzer can decode one or more protocols with the sameinstrument or even within the same capture. Tradi onally, each protocol needs its own analyzerinstrument. Each instrument is customized for the protocol it supports, including items such asdedicated physical layer (PHY) ASICs. For example, there could be two di erent protocols in the samechannel (e.g., over the air). The ADC would be able to capture all the frequencies up to Nyquist rateA orney Docket No.: 11744 002WO1and there could be mul ple CDRs processing the blind samples processing di erent protocols, usingthe same blind ADC samples.

[0049] Enables rapid prototyping, custom digital signal processing (DSP), and dynamicrecon gura on of physical SERDES and CDR implementa on. For example, an FPGA can be easilymodi ed to accommodate di erent SERDES and CDR implementa ons to support a myriad ofprotocols, covering applica ons much wider than just protocol analyzers.

[0050] The fully digital clock architecture can be implemented in an FPGA, hardened FPGAblocks, a dedicated ASIC, or so ware, improving signal capture and lowering metrics such as bit errorrate across myriad of protocol applica ons.

[0051] Allows the use of a fully digital clock that can change both frequency and phase, withtheore cally in nite resolu on. The fully digital clock is programable, allowing the frequency toeasily be changed. Tradi onal CDRs can only modify one or the other.

[0052] In one event capture on the same input signal (i.e. one physical input) and inherentlyme correlated, both sampled analog data and / or decoded protocol can be triggered on andanalyzed. This enables advanced triggering that can work on any of the following: the analog signalprior to the ADC, the digi zed samples (i.e., a digital trigger), or any aspect of the protocol decode.Addi onally, this allows trigger modes that cannot be realized on oscilloscopes or tradi onal protocolanalyzers. For example, the trigger can be set to an analog signal property (i.e. a runt pulse) within aprotocol mode (i.e. hibernate).

[0053] Enables real me signal quality and margin measurements such as eyemeasurements and SNR, with or without equaliza on.

[0054] As used herein, the term “comprises” or “comprising” or “includes” or any othervaria ons thereof is intended to encompass a non exclusive inclusion, such that a process, method,ar cle, or device that comprises a plurality of elements includes not only those elements but alsoother elements, or elements that are inherent to such a process, method, item, or device. Withoutmore restric ons, the element de ned by the phrase “include one” or the like does not exclude thatthere are other iden cal elements in the process, method, ar cle or equipment that includes theelement. In the present disclosure, if it is men oned that an ac on is performed according to anelement, it means the meaning of performing the ac on at least according to the element andincludes two cases: the behavior is performed only on the basis of the element, and the behavior isperformed based on the element and other elements.

[0055] Mul ple, repeatedly, various, etc., expressions include 2, twice, 2 types, and 2 ormore, twice or more, and 2 types or more types.A orney Docket No.: 11744 002WO1

[0056] The term “coupled to” and its deriva ves can be used herein. “Coupled” may meanthat two or more elements are in direct physical or electrical contact. However, “coupled” may alsomean that two or more elements are indirectly in contact with each other, but s ll cooperate orinteract with each other, and may mean that one or more other elements are coupled betweenelements that are said to be coupled to or connected with each other.

[0057] While subject ma er of the present disclosure has been illustrated and described indetail in the drawings and foregoing descrip on, such illustra on and descrip on are to beconsidered illustra ve or exemplary and not restric ve. Any statement made herein characterizingthe implementa ons is also to be considered illustra ve or exemplary and not restric ve as theinven on is de ned by the claims. It will be understood that changes and modi ca ons may bemade, by those of ordinary skill in the art, within the scope of the following claims, which mayinclude any combina on of features from di erent embodiments described above.

Claims

A orney Docket No.: 11744 002WO1Claims 1. A digital clock and data recovery (CDR) system, comprising:a blind sampling circuit that receives an input sampled signal; anda digital monolithic circuit that includes:a phase detector (PD) that determines a phase error which is used to determine aunit interval (UI) center; anda fully digital clock (FDC) that creates a digital clock used to recover digital data fromthe input sampled signal.

2. The CDR system of claim 1, further comprising:an analog to digital converter (ADC); andan ADC sample clock,wherein the ADC sample clock drives the ADC to provide the input sampled signal.

3. The CDR system of claim 2, wherein the FDC operates independently of the input sampledsignal or the ADC sample clock.

4. The CDR system of claim 2, wherein the ADC samples an incoming analog signal without afeedback loop from the digital monolithic circuit.

5. The CDR system of claim 2, wherein an ADC sample rate is greater than a baud rate.

6. The CDR system of claim 1, further comprising a loop lter (LF) circuit that uses the phaseerror from the PD and provides a phase adjustment to the FDC.

7. The CDR system of claim 1, the digital monolithic circuit further comprising:at least one of a feed forward equalizer (FFE) and a decision feedback equalizer (DFE),wherein the at least one of the FFE and DFE provide equalized sampled data to the PD.

8. The CDR system of claim 1, the digital monolithic circuit further comprising: aninterpolator that provides interpolated sample data to the PD.A orney Docket No.: 11744 002WO19. The CDR system of claim 8, wherein a feed forward equalizer (FFE) is placed ahead of theinterpolator and operates on the sampled signal, rather than interpolated samples.

10. The CDR system of claim 1, wherein the CDR system resides in so ware.

11. The CDR system of claim 1, wherein the CDR system is integrated in a custom ASIC or aField Programmable Gate Array (FPGA).

12. A method for sampling an analog input signal, comprising:receiving an input sampled signal at a blind sampling circuit; andrecovering digital data from the input sampled signal using a phase detector (PD) thatdetermines a phase error which is used to determine a unit interval (UI) center and a fully digitalclock (FDC) that creates a digital clock used to recover digital data from the input sampled signal.

13. The method of claim 12, further comprising:sampling the analog signal using an analog to digital converter (ADC); anddriving the ADC using an ADC sample clock to provide the input sampled signal.

14. The method of claim 13, further comprising opera ng the FDC independently of theanalog input signal or the sample clock.

15. The method of claim 13, further comprising opera ng the ADC sample clock without afeedback loop from a digital monolithic circuit.

16. The method of claim 13, further comprising opera ng the ADC sample clock at greaterthan a baud rate.

17. The method of claim 12, further comprising:using a loop lter (LF) circuit that that uses the phase error from the PD and provides a phaseadjustment to the FDC.

18. The method of claim 12, further comprising:using at least one of a feed forward equalizer (FFE) and a decision feedback equalizer (DFE)that receives an output of an interpolator circuit; andA orney Docket No.: 11744 002WO1outpu ng an equalized signal to the PD.

19. The method of claim 18, where the FFE is placed ahead of the interpolator circuit andoperates on the sampled signal, rather than interpolated rate samples.

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