Silicon-based virtual substrates with selectable lattice constant

Abstract

A method of manufacturing a semiconductor device comprises providing a pre-treated silicon substrate; forming an interfacial misfit (IMF) initiation layer on the pre-treated silicon substrate using a ternary or higher-order III-V semiconductor compound; and forming a buffer layer on the IMF initiation layer. The semiconductor device may be formed on the buffer layer, or an amorphous protection layer may be formed on the buffer layer to provide for later device manufacturing.

Description

SILICON-BASED VIRTUAL SUBSTRATES WITH SELECTABLE LATTICECONSTANTCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to and the benefit of U.S. Provisional Application No. 63 / 634,003, filed on April 15, 2024. The entire contents of which are herein incorporated by reference for all purposes.STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

[0002] This invention was made with government support under N00014-24- 1-2276 and N0014-24- 1-2445 awarded by the United States Navy, Office of Naval Research. The government has certain rights in the invention.TECHNICAL FIELD

[0003] This disclosure relates to the field of semiconductors. More particularly, this disclosure relates to systems and methods to produce semiconductor devices using a IILV semiconductor alloy on a silicon substrate.BACKGROUND

[0004] Semiconductor materials are used to form a wide range of electronic and photonic devices. Semiconductor materials include pure semiconductors formed of a single element and compound semiconductors formed of a plurality of different materials. IILV semiconductors are compound semiconductors that include at least one Group III element (e.g., boron (B), aluminum (Al), gallium (Ga), indium (In), etc.) and at least one Group V element (e.g., nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), etc.). Compound IILV semiconductors include binary compounds having one Group III element and one Group V element, ternary compounds having one Group III element and two Group V elements or two Group III elements and one Group V element, and so on.SUMMARY

[0005] The present disclosure provides for systems and methods of producing semiconductor devices on a silicon (Si) substrate using a virtual substrate with a selectable lattice constant having any desired value, such as between 5.8 and 6.5 Angstroms (A).

[0006] According to one aspect of the present disclosure, a method of manufacturing a semiconductor device is provided. The method comprises providing a pre-treated silicon substrate; forming an interfacial misfit (IMF) initiation layer on the pre-treated silicon substrate using a ternary or higher-order III-V semiconductor compound; forming a buffer layer on the IMF initiation layer; and forming the semiconductor device on the buffer layer.

[0007] According to another aspect of the present disclosure, a method of manufacturing a virtual substrate is provided. The method comprises providing a pre-treated silicon substrate; forming an interfacial misfit (IMF) initiation layer on the pre-treated silicon substrate using a ternary or higher-order III-V semiconductor compound; forming a buffer layer on the IMF initiation layer; and forming an amorphous protection layer on the buffer layer.BRIEF DESCRIPTION OF THE DRAWINGS

[0008] FIG. 1 illustrates images of example interfacial misfit arrays in accordance with a comparative example.

[0009] FIG. 2 illustrates a process flow of an example method in accordance with the present disclosure.

[0010] FIG. 3A illustrates a graph of semiconductor parameters in accordance with the present disclosure.

[0011] FIG. 3B illustrates a graph of semiconductor parameters in accordance with the present disclosure.

[0012] FIG. 4A illustrates a side view of an example semiconductor in production in accordance with the present disclosure.

[0013] FIG. 4B illustrates a side view of an example semiconductor in production in accordance with the present disclosure.

[0014] FIG. 4C illustrates a side view of an example semiconductor in production in accordance with the present disclosure.

[0015] FIG. 4D illustrates a side view of an example semiconductor in production in accordance with the present disclosure.

[0016] FIG. 4E illustrates a side view of an example semiconductor in production in accordance with the present disclosure.

[0017] FIG. 4F illustrates a side view of an example semiconductor in production in accordance with the present disclosure.

[0018] FIG. 5 illustrates images of virtual substrates in accordance with the present disclosure.DETAILED DESCRIPTION

[0019] The detailed description set forth below in connection with the appended drawings is intended as a description of various configurations and is not intended to represent the only configurations in which the subject matter described herein may be practiced. The detailed description includes specific details to provide a thorough understanding of various embodiments of the present disclosure. However, it will be apparent to those skilled in the art that the various features, concepts, and embodiments described herein may be implemented and practiced without these specific details.

[0020] Before any aspects of the invention are explained in detail, it is to be understood that the invention is not limited in its application to the details of construction and the arrangement of components set forth in the following description or illustrated in the following drawings. The invention is capable of other aspects and of being practiced or of being carried out in various ways. Also, it is to be understood that the phraseology and terminology used herein is for the purpose of description and should not be regarded as limiting. The use of “including,” “comprising,” or “having” and variations thereof herein is meant to encompass the items listed thereafter and equivalents thereof as well as additional items. Unless specified or limited otherwise, the terms “mounted,” “connected,” “supported,” and “coupled” and variations thereof are used broadly and encompass both direct and indirect mountings, connections, supports, and couplings. Further, “connected” and “coupled” are not restricted to physical or mechanical connections or couplings.

[0021] It is also to be understood that any reference to an element herein using a designation such as “first,” “second,” and so forth does not limit the quantity or order of those elements, unless such limitation is explicitly stated. Rather, these designations may be used herein as a convenient method of distinguishing between two or more elements or instances of an element. Thus, a reference to first and second elements does not mean that only two elements may be employed or that the first element must precede the second element in some manner.

[0022] Also as used herein, unless otherwise limited or defined, “or” indicates a nonexclusive list of components or operations that can be present in any variety of combinations, rather than an exclusive list of components that can be present only as alternatives to each other. For example, a list of “A, B, or C” indicates options of: A; B; C; A and B; A and C; B and C; and A, B, and C. Correspondingly, the term “or” as used herein is intended to indicate exclusive alternatives only when preceded by terms of exclusivity, such as, e.g., “either,” “one of,” “only one of,” or “exactly one of.” Further, a list preceded by “one or more” (and variations thereon) and including “or” to separate listed elements indicates options of one or more of any or all of the listed elements. For example, the phrases “one or more of A, B, or C” and “at least one of A, B, or C” indicate options of: one or more A; one or more B; one or more C; one or more A and one or more B; one or more B and one or more C; one or more A and one or more C; and one or more of each of A, B, and C. Similarly, a list preceded by “a plurality of’ (and variations thereon) and including “or” to separate listed elements indicates options of multiple instances of any or all of the listed elements. For example, the phrases “a plurality of A, B, or C” and “two or more of A, B, or C” indicate options of: A and B; B and C; A and C; and A, B, and C. In general, the term “or” as used herein only indicates exclusive alternatives (e.g., “one or the other but not both”) when preceded by terms of exclusivity, such as, e.g., “either,” “one of,” “only one of,” or “exactly one of.”

[0023] The following discussion is presented to enable a person skilled in the art to make and use embodiments of the invention. Various modifications to the illustrated embodiments will be readily apparent to those skilled in the art, and the generic principles herein can be applied to other embodiments and applications without departing from embodiments of the invention. Thus, embodiments of the invention are not intended to be limited to embodiments shown but are to be accorded the widest scope consistent with the principles and features disclosed herein. The following detailed description is to be read with reference to the figures, in which like elements in different figures have like reference numerals. The figures, which are not necessarily to scale,depict selected embodiments and are not intended to limit the scope of embodiments of the invention. Skilled artisans will recognize the examples provided herein have many useful alternatives and fall within the scope of embodiments of the invention.

[0024] According to comparative examples of semiconductor processes, III-V semiconductor materials with lattice constant (i.e., atomic spacing) in the range of 5.8-6.5 A must be grown on the binary III-V substrate materials InP, InAs, GaSb, or InSb. However, unless the lattice constant of the desired semiconductor material happens to match one of these four binary substrates, the semiconductor material will experience strain. As the semiconductor film grows, this strain relaxes, generally resulting in highly defective, poor-quality material that is unsuitable for use in electronic or photonic devices. In addition to this constraint on which semiconductor material can be grown without strain InP, InAs, GaSb, and InSb substrates are all extremely expensive and only available in comparatively small sizes when compared to Si substrates. Si substrates are also a more mature technology whose development has been driven by the electronics industry.

[0025] The present disclosure enables the use of Si substrates for the growth of III-V semiconductors (e.g., by molecular beam epitaxy (MBE)) with any lattice constant (e.g., in the range 5.8-6.5 A). By engineering the interface between the Si substrate and the III-V compound, these films grow strain-free and with defect levels that are acceptably low for the production of functional electronic or photonic devices. In addition to lifting the constraints on substrate lattice constant, by using Si instead of InP, InAs, GaSb, or InSb, the present disclosure also dramatically reduces substrate cost while allowing growth on large format (e.g., 200-300 millimeter (mm)) Si substrates for high-volume manufacturing.

[0026] Certain examples of systems and methods in accordance with the present disclosure are presented in the context of nBn photodetectors; however, the present disclosure may be practiced with any type of device in which there is a desire to provide a III-V semiconductor on a Si substrate with a selectable lattice constant, for example, the present disclosure may be applied to transistors, diodes, LiDAR detectors, laser devices, thermovoltaics, photodiodes, or any other electronic, optoelectronic, or photonic device of interest.

[0027] III-V nBn photodetectors may be used for, among other things, short- wavelength infrared (SWIR), medium-wavelength infrared (MWIR), and long- wavelength infrared (LWIR) imaging and detection. In comparative examples, nBn photodetectors are grown on GaSbsubstrates. However, GaSb substrates are expensive and limited in size, often to 100-150 mm diameters. Si substrates, by comparison, are available in large formats and at a significantly lower cost. For example, a 300 mm Si wafer may cost one-quarter that of a 50 mm GaSb wafer. Moreover, Si-based designs can take advantage of high-volume manufacturing developed by the electronics industry.

[0028] The comparative examples are unable to be properly integrated with silicon. There is a 12.1% lattice mismatch between Si and GaSb. Therefore, strain relaxation via defects such as threading dislocations compromise optoelectronic performance, for example by causing dead pixels in the focal plane array (FPA), thus causing reduced operability. Moreover, antiphase domains (APDs) at the interface between polar III-V materials and non-polar Si can impair material qualities. Additionally, the different thermal expansion coefficients of III-V compounds and Si can produce wafer bowing or cracking.

[0029] Additionally, direct growth of III-V photodetectors on Si readout integrated circuits (ROICs) is not feasible. ROICs have a maximum processing temperature of -400 °C, while a substrate temperature of -500 °C is needed to perform MBE of GaSb. Comparative attempts to overcome these issues, such as growing the III-V photodetectors on GaSb substrates and then wafer bonding the GaSb to a Si substrate, are themselves deficient. For example, these attempts result in increased processing time after device growth, in addition to the size disadvantages for GaSb substrates noted above. Thus, these comparative examples provide no pathway to large (e.g., 300 mm) FPAs based on III-V-to-Si wafer bonding.

[0030] The present disclosure leverages a particular growth mode that can occur within III-V semiconductors are grown directly on Si. The large compressive strains may give rise to a two-dimensional network of in-plane, pure edge-type misfit dislocations (i.e., 90° Lomer dislocations) right at the III- V / Si interface. This network is referred to as an interfacial misfit (IMF) array. FIG. 1 illustrates a comparative example of the IMF array in binary III-Sb-on-Si materials. Image (a) of FIG. 1 is a cross-sectional transmission electron microscope (XTEM) image along

[0110] showing binary IILSb layers grown on Si(001) with a lattice constant of -6.1 A. Arrows indicate the periodic strain-relieving misfit dislocations at the III-Sb / Si interface. Images (b) and (c) show an XTEM image of AlSb grown on 5° miscut Si(001) in low- and high-resolution, respectively, and show the periodic IMF array. Image (d) is an XTEM image of a GaSb buffergrown on GaAs in a comparative example, where the IMF array is visible as dark spots at the interface.

[0031] The IMF array ensures near-complete strain relaxation (>98%) at the III-V interface without forming high density threading dislocations. In this way, it is possible to grow high-quality III-V materials directly on Si(001) without the need for thick buffers. However, comparative examples have only achieved III-V material growth directly in Si(001) using binary III-V semiconductors, and are thus only applicable to a narrow range of lattice mismatches (e.g., 12- 13% for GaSb or Al Sb IMFs). For ternary or higher-order III-V semiconductor alloys, the full range of lattice mismatches is much wider (e.g., 8.1-19.3% for the materials covering the lattice constant range described herein). Furthermore, the comparative examples (whether based on IMF or otherwise) do not provide for the production of free-standing substrates of ternary or higher order III-V semiconductor alloys. The systems and methods described herein use the IMF technique to grow ternary or higher-order III-V semiconductor devices directly on Si substrates, for example by MBE.

[0032] As the terms are used herein, a “binary” III-V semiconductor alloy or compound refers to an alloy or compound of two different elements (i.e., one Group III element and one Group V element), a “ternary” III-V semiconductor alloy or compound refers to an alloy or compound of three different elements (i.e., one Group III element and two Group V elements, or two Group III elements and one Group V element), a “quaternary” III-V semiconductor alloy or compound refers to an alloy or compound of four different elements (i.e., one Group III element and three Group V elements, two Group III elements and two Group V elements, or three Group III elements and one Group V element), and “quinary” III-V semiconductor alloy or compound refers to an alloy or compound of five different elements (i.e., one Group III element and four Group V elements, two Group III elements and three Group V elements, three Group III elements and two Group V elements, or four Group III elements and one Group V elements). “Higher order” alloys or compounds, by extension, refer to alloys or compounds having a higher number of different elements.

[0033] FIG. 2 illustrates an example of a method 200 of producing a semiconductor device in accordance with the present disclosure. The method 200 as illustrated begins with an operation 202 of pre-treating a Si substrate. In some examples, however, a calibration operation may be performed prior to operation 202, to calibrate the growth rate of the various materials to oneanother. In either case, the substrate may be either an on-axis or intentionally miscut Si(001 ) substrate. Although on-axis Si(001) is more commonly used in the semiconductor industry, one can reduce APD at the polar / non-polar interface using Si(001) wafers offcut by 4-6° towards [0- 11], The offcut creates double-height steps on the Si surface, ensuring the III-V material that will be formed thereon grows in the correct registry without forming antiphase boundaries. In either case, in an example operation 202 begins with passivating the surface of the Si substrate, for example using hydrogen fluoride (HF). The Si substrate is then heated to an oxide desorption temperature (e.g., 800-850 °C for a surface passivated with hydrogen) in an MBE device until a bright (2x2) surface construction is observed, for example with reflection high-energy electron diffraction (RHEED). This corresponds to the removal of surface oxides. The substrate is then cooled to the growth temperature for III-V epitaxy (e.g., -500 °C).

[0034] Next, at operation 204, an IMF initiation layer is grown. The IMF initiation layer is grown using (e.g.) MBE to grow a ternary or higher-order III-V semiconductor alloy. The MBE operation may be performed under vacuum (e.g., ultra-high vacuum). If the ternary or higher-order III-V semiconductor alloy is a ternary alloy, then in one example, the ternary III-V semiconductor alloy has the form Ml(i-X)M2XM3, where both Ml and M2 are Group III elements, M3 is a Group V element, and x is a number greater than 0 and less than 1. In this example, the ternary III-V semiconductor may be Al(i-X)GaxP, Al(i-X)InxP, Ga<i-X)InxP, Al(i-X)GaxAs, Al(i-X)InxAs, Ga(i-X)InxAs, Al(i-X)GaxSb, Al(i-X)InxSb, or Ga(i-X)InxSb. In another example, the ternary III-V semiconductor alloy has the form MlM2(i-X)M3x, where Ml is a group III element, M2 and M3 are Group V elements, and x is a number greater than 0 and less than 1. In this example, the ternary III-V semiconductor may be AlP(i-X)Asx, AlP(i-X)Sbx, AlAs(i-X)Sbx, GaP(i-X)Asx, GaP(i-X)Sbx, GaAs(i-X)Sbx, InP(i-X)Asx, InP(i-X)Sbx, or InAs(i-X)Sbx. Preferably, however, the ternary or higher-order III-V semiconductor alloy includes Sb.

[0035] If the ternary or higher-order III-V semiconductor alloy is a quaternary alloy, it may have either have the form Ml(i-x.y)M2xM3yM4, where Ml, M2, and M3 are Group III elements and M4 is a group V element, x and y are numbers greater than 0 and less than 1, and x+y is less than 1; the form Ml(i-X)M2xM3(i-y)M4y, where Ml and M2 are Group III elements and M3 and M4 are Group V elements, and x and y are numbers greater than 0 and less than 1 ; or the form M 1 M2(i-x-y)M3xM4y, where Ml is a Group III element, M2, M3, and M4 are Group V elements, x and y are numbers greater than 0 and less than 1, and x+y is less than 1.

[0036] Quinary and higher-order alloys follow a similar pattern, in which one or more Group III elements and one or more Group V elements are present, such that the total ratio of Group III atoms to Group V atoms is 1 : 1. The particular ternary or higher-order III-V semiconductor alloy may be selected based on the desired lattice constant, as illustrated in FIGS. 3A and 3B. While any of these or higher-order III-V semiconductor alloys may be used for this IMF initiation layer, in some implementations it may be preferable to use an Al-rich layer and avoid the use of Ga because Ga atoms tend to be highly mobile. Moreover, while operation 204 uses MBE in this example, in other examples the IMF initiation layer may be formed using another deposition method, such as MOCVD, atomic layer deposition (ALD), and the like.

[0037] FIG. 3A illustrates a bandgap vs. lattice constant diagram for various semiconductors, including Si, germanium (Ge), and several binary III-V semiconductor compounds. As can be seen from FIG. 3 A, Si has a lattice constant of 5.43 A, Ge has a lattice constant of 5.66 A, InP has a lattice constant of 5.87 A, InAs has a lattice constant of 6.06 A, GaSb has a lattice constant of 6.10 A, and InSb has a lattice constant of 6.48 A. However, the methods of the present disclosure are not limited to these lattice constants. For example, by utilizing GalnSb, it is possible to achieve a lattice constant that is between 6.10 A and 6.48 A, which is represented by the lines in FIG. 3A connecting each binary semiconductor node. Thus, by replacing some of the Ga in GaSb with In (or conversely, by replacing some of the In in InSb with Ga), it is possible to move along the line connecting the GaSb node and the InSb node. Similarly, by replacing some of the Sb in GaSb with As (or conversely, by replacing some of the As in GaAs with Sb), it is possible to move along the line connecting the GaSb node and the GaAs node. Thus, by controlling the composition of the ternary or higher-order III-V semiconductor compound, it is possible to select any desired lattice constant within the achievable range (e.g., between 5.8 A and 6.5 A).

[0038] FIG. 3B illustrates an intensity vs. peak width diagram for eight of the semiconductor compounds shown in FIG. 3A and for Si, the data for which was obtained via X- ray diffraction. These eight semiconductors are identified in FIG. 3A: node 302 is Gao25Ino.75 Sb and has a lattice constant of 6.39 A, node 304 is Gao.55Ino45Sb and has a lattice constant of 6.27 A, node 306 is Gao 76lno 24Sb and has a lattice constant of 6.19 A, node 308 is GaAso 11Sbo s9 and has a lattice constant of 6.05 A, node 310 is GaAso.47Sbo.53 and has a lattice constant of 5.89 A, node 312 is GaAso 54Sbo.46 and has a lattice constant of 5.86, node 314 is GaAso.6iSbo.39 and has a latticeconstant of 5.82, and node 316 is GaSb (for comparison) and has a lattice constant of 6.1 A. The peaks from nodes 302-314 arise from the virtual substrate materials fo the present disclosure, with the specific angle corresponding to the lattice constant and hence composition of that ternary compound. The peak at the right (around 69°) arises from the underlying Si substrate. In theory, any point along a line connecting two binary compound nodes in FIG. 3A may be achieved and thus any desired lattice constant in the range shown in FIG. 3A may be realized. Moreover, it is possible to produce an alloy that lies at any point enclosed by the lines connecting two binary compound nodes in FIG. 3 A by using quaternary, quinary, or higher-order III-V semiconductor materials using the systems and methods described herein. The use of higher-order alloys may permit decoupling of the lattice constant from the band gap energy.

[0039] The IMF initiation layer may, in one example, be produced by soaking the surface of the pre-treated Si substrate with a Group V material (e.g., Sb?) from a valved-cracker cell. Next, the Group III material sources may be opened to grow a thin layer of the ternary or higher-order compound. The layer may be, for example, several (e.g., on the order of 10° to 101) monolayers thick or about 10° to 101nanometers (nm). The growth of a thin initiation layer on the Si produces an IMF structure and dramatically improves the structural properties of the layers (e.g., a buffer layer) that will be grown thereon. The IMF network may be affected by several factors, such as the precise sequence in which the shutters for the different elements are opened and growth initiated, the thickness of the IMF initiation layer, the substrate temperature, the growth rates, the flux ratios, the use of Al-containing ternary or higher-order alloys followed by Ga-containing alloys, etc. For example, the desired MBE growth conditions may be highly material-dependent (and may be quite different from the conditions for the binary compositions at either endpoint node). Thus, these factors may be controlled to precisely control the characteristics of the IMF network. The IMF layer may then be capped with a thin layer of another material (e.g., another III-V semiconductor compound) to prevent oxidation.

[0040] As well as promoting efficient IMF array formation, certain choices for the above described ternary or higher-order III-V compounds in the IMF initiation layer also help reduce the thermal expansion issues noted above with regard to comparative examples, for example if they have a thermal expansion coefficient that is similar to the thermal expansion coefficient of Si. Moreover, the use of ternary or higher-order III-V compounds provides an increased ability to tunethe thermal expansion coefficient as compared to the use of binary III-V compounds. As a result, wafer bowing or cracking can be minimized.

[0041] Returning to FIG. 2, at operation 206 a buffer layer is grown on top of the IMF array produced in operation 204. While the IMF initiation layer of operation 204 maybe grown using MBE, the buffer layer may be grown using another method such as metalorganic chemical vapor deposition (MOCVD) to take advantage of a higher growth rate. The buffer layer may be a binary, ternary, quaternary, quinary, or higher-order III-V semiconductor compound and may correspond to the lattice constant of the IMF initiation layer. If the buffer layer is a ternary compound, it may be a compound described by a line between nodes that is directly (or nearly directly) above or below the ternary compound as illustrated in FIG. 3. For example, if the ternary compound used for the IMF initiation layer is Al(i-X)InxSb, the ternary compound for the buffer layer may be Ga(i-y)InySb. In this case, the values of x and y may be selected so that the two ternary compounds have the same or nearly the same lattice constant. The buffer layer may be grown to a thickness on the order of hundreds or thousands of nm.

[0042] At operation 208, a semiconductor device is grown on the buffer layer. In the example case where the semiconductor device is an nBn photodetector, the nBn structures (i.e., an n-type absorber layer, a barrier layer, and an n-type contact layers) may be formed. In this case, the absorber and contact layers may be superlattice (SL) layers, and by adjusting the relative thickness and / or composition of the SL layers it is possible to produce strain-compensated SLs with miniband transition energies coverage a wide range in the SWIR, MWIR, and / or LWIR ranges. However, as noted above, the present disclosure is not limited to nBn photodetectors and the semiconductor device grown in operation 208 may be any electronic, optoelectronic, or photonic device using III-V compounds, including but not limited to, transistors, diodes, LiDAR detectors, laser devices, thermovoltaics, and / or photodiodes.

[0043] In some implementations, operation 208 may not occur directly after operation 206. For example, a virtual substrate may be formed by performing operations 202 to 206, and then an amorphous protection layer may be deposited on the virtual substrate, for example to prevent oxidation and / or contamination. The amorphous layer may be a film of As, Sb, and so on. Then, the protected virtual substrate may be provided to another manufacturer or another laboratory (or stored for later use by the same location) where operation 208 is performed to grow the semiconductor device. Because operation 208 generally takes place at high temperatures, theamorphous protection film will evaporate away and not affect the semiconductor manufacturing process.

[0044] FIGS. 4A-4F illustrate an example semiconductor device formed according to the present disclosure. For purposes of illustration and explanation, the semiconductor device will be described as being produced by the method 200 of FIG. 2. FIGS. 4A-4F are not to scale, and thus the dimensions illustrated therein (e.g., the absolute and relative thicknesses of the various layers) are not intended to be limiting.

[0045] FIG. 4A illustrates a pre-treated Si substrate 402 (e.g., after operation 202). As noted above, the Si substrate 402 may be either an ox-axis or intentionally miscut Si (001) substrate that is offcut by 4-6° towards [0-11], At the time illustrated in FIG. 4A, the Si substrate 402 may be positioned in a vacuum chamber, such as a vacuum chamber of an MBE device, at a temperature appropriate for growth of subsequent III-V layers (e.g., -500 °C).

[0046] FIGS. 4B and 4C illustrate the growth of ternary or higher-order semiconductor compound layers on the Si substrate 402 (e.g., during and after operation 204). In FIG. 4B, in the case where the compound is a ternary compound that has the form Ml(i-X)M2XM3 (Ml and M2 being Group III elements, and M3 being a Group V element), the Si substrate 402 has been briefly exposed to a group V material (e.g., Sb2), for example by soaking, to provide an initial Group V surface treatment layer 404 on the exposed surface of the Si substrate 402. In the case where the ternary compound has the more than one Group V element, the Si substrate 402 has been briefly exposed to one, multiple, or all Group V materials, either at the same time or in an alternating manner, to provide the initial Group V surface treatment layer 404. Note that, in some implementations, the soaking operation may be omitted and thus the semiconductor device may proceed directly from the illustration of FIG. 4A to the illustration of FIG. 4C. In FIG. 4C, the Si substrate 402 that has undergone the Group V soak is then exposed to the relevant Group III and Group V materials to begin growth of the ternary or higher-order compound. In the case where the ternary or higher-order compound has more than one Group III element, the Si substrate 402 may be exposed to one, multiple, or all Group III materials, either simultaneously or in an alternating manner. This proceeds until an IMF initiation layer 406 is formed. The IMF initiation layer 406 may be formed using MBE. The IMF initiation layer 404 may have a thickness of several monolayers (e.g., on the order of 10° - 101), and includes a network of in-plane misfit dislocations that relieve the strain.

[0047] FIG. 4D illustrates the growth of a buffer layer 408 on the Si substrate 402 (e.g., after operation 206). The buffer layer 408 may be formed using MBE or MOCVD. The buffer layer 408 may be a binary, ternary, quaternary, quinary, or higher-order III-V semiconductor compound with a lattice constant that is matched (i.e., typically within 1%) to the IMF initiation layer 406. The buffer layer 408 may be grown to a thickness on the order of hundreds or thousands of nm.

[0048] FIG. 4E describes operations that may, in some but not all implementations, occur prior to the formation of the end-result semiconductor device (e.g., after operation 208 but before operation 210) For example, if the prepared virtual substrate (i.e., layers 402, 406, and 408) will be used at a later date and / or at another facility, an amorphous protection layer 410 may be deposited on the buffer layer 408. In an example, the amorphous protection layer 410 may be formed of a film of a material such as As or Sb. The amorphous protection layer 410 serves to protect the virtual substrate until the time of device manufacture.

[0049] FIG. 4F illustrates the manufacture of a semiconductor device 412 atop the virtual substrate (e.g., after operation 210). If the virtual substrate was treated with an amorphous protection layer 410, the amorphous protection layer 410 will evaporate away upon heating the virtual substrate in an MBE or MOCVD tool to recover the pristine epitaxial surface. At this point the manufacture of the semiconductor device 412 on the virtual substrate consistent with the approaches that would be used for a standard binary substrate.

[0050] The mismatch in lattice constant of 6.8-17.9% between various III-V virtual substrates in accordance with the present disclosure and the underlying Si generates large compressive strains. However, results from experimentation performed in support of the present disclosure show that these strains are efficiently relieved directly at the interface via the spontaneous formation of an IMF. FIG. 5 illustrates micrographs showing characteristics of virtual substrates in accordance with the present disclosure. Image (a) of FIG. 5 illustrates the strain relief and shows, in particular, a transmission electron micrograph of the III-V / Si interface for an example Ino.45Gao.55 Sb virtual buffer having a lattice constant of 6.3 A (i.e., for a lattice mismatch of 17.9%). The scale bar corresponds to 20 nm. The IMF appears as a periodic contrast modulation at the interface, indicating the presence of a network of strain-relieving misfit dislocations. Defects extending from the interface into the epitaxial virtual substrate were not observed.

[0051] Moreover, the misfit dislocations of the IMF lie in the plane of the interface between the III-V virtual substrate of the present disclosure and SI, without generating extended defects that would negatively impact the electronic and / or optical properties of the overlying film. The virtual substrates are shiny to the eye and their surfaces are featureless when viewed using differential interference contrast microscopy. This is illustrated in image (b) of FIG. 5, which shows an optical differential interference contrast micrograph of the surface of an IMF-based GaAso.47Sbo.53 virtual buffer having a lattice constant of 5.9 A grown on Si via IMF. The scale bar corresponds to 25 nm. Taken together, the results illustrated in FIG. 5 demonstrate that the IMFbased approach set forth herein enables the growth of III-V ternary virtual buffers across the entire lattice constant range from 5.8-6.5 A.

[0052] Other examples and uses of the disclosed technology will be apparent to those having ordinary skill in the art upon consideration of the specification and practice of the invention disclosed herein. The specification and examples given should be considered exemplary only, and it is contemplated that the appended claims will cover any other such embodiments or modifications as fall within the true scope of the invention.

[0053] The Abstract accompanying this specification is provided to enable the United States Patent and Trademark Office and the public generally to determine quickly from a cursory inspection the nature and gist of the technical disclosure and in no way intended for defining, determining, or limiting the present invention or any of its embodiments.

Claims

CLAIMSWhat is claimed is:

1. A method of manufacturing a semiconductor device, comprising: providing a pre-treated silicon substrate; forming an interfacial misfit (IMF) initiation layer on the pre-treated silicon substrate using a ternary or higher-order III-V semiconductor compound; forming a buffer layer on the IMF initiation layer; and forming the semiconductor device on the buffer layer.

2. The method of claim 1, wherein the semiconductor compound is a ternary III-V semiconductor that has the form Ml(i-x)M2xM3, where both Ml and M2 are Group III elements, M3 is a Group V element, and x is a number greater than 0 and less than 1, or has the form MlM2(i- x)M3x, where Ml is a group III element, M2 and M3 are Group V elements, and x is a number greater than 0 and less than 1.

3. The method of claim 2, wherein the value of x is selected such that a lattice constant of the IMF initiation layer is matched to a lattice constant of the buffer layer.

4. The method of claim 3, wherein the lattice constant of the IMF initiation layer is between 5.8 A and 6.5 A.

5. The method of claim 1, wherein the operation of providing the pre-treated silicon substrate includes: providing a silicon substrate; passivating the silicon substrate; and heating the silicon substrate to a predetermined temperature.

6. The method of claim 1, wherein the silicon substrate is an on-axis Si(001) substrate or an intentionally miscut Si(001) substrate.

7. The method of claim 1, wherein the operation of forming the IMF initiation layer is performed using molecular beam epitaxy (MBE).

8. The method of claim 1, wherein the operation of forming the buffer layer is performed using molecular beam epitaxy (MBE) or metalorganic chemical vapor deposition (MOCVD).

9. The method of claim 1, wherein the semiconductor device includes an nBn photodetector, a transistor, a diode, a LiDAR detector, a laser device, a thermovoltaic device, or a photodiode.

10. A method of manufacturing a virtual substrate, comprising: providing a pre-treated silicon substrate; forming an interfacial misfit (IMF) initiation layer on the pre-treated silicon substrate using a ternary or higher-order III-V semiconductor compound; forming a buffer layer on the IMF initiation layer; and forming an amorphous protection layer on the buffer layer.

11. The method of claim 10, wherein the semiconductor is a ternary III-V semiconductor that has the form Ml(i-x)M2xM3, where both Ml and M2 are Group III elements, M3 is a Group V element, and x is a number greater than 0 and less than 1, or has the form MlM2(i- x)M3x, where Ml is a group III element, M2 and M3 are Group V elements, and x is a number greater than 0 and less than 1.

12. The method of claim 11, wherein the value of x is selected such that a lattice constant of the IMF initiation layer is matched to a lattice constant of the buffer layer.

13. The method of claim 12, wherein the lattice constant of the IMF initiation layer is between 5.8 A and 6.5 A.

14. The method of claim 10, wherein the operation of providing the pre-treated silicon substrate includes: providing a silicon substrate; passivating the silicon substrate; and heating the silicon substrate to a predetermined temperature.

15. The method of claim 10, wherein the silicon substrate is an on-axis Si(001) substrate or an intentionally miscut Si(001) substrate.

16. The method of claim 10, wherein the operation of forming the IMF initiation layer is performed using molecular beam epitaxy (MBE).

17. The method of claim 10, wherein the operation of forming the buffer layer is performed using molecular beam epitaxy (MBE) or metalorganic chemical vapor deposition (MOCVD).

18. The method of claim 10, wherein the amorphous protection layer is formed of a film of a Group V element.

19. The method of claim 10, further comprising: evaporating the amorphous protection layer; and forming a semiconductor device on the buffer layer.

20. The method of claim 10, wherein the semiconductor device includes an nBn photodetector, a transistor, a diode, a LiDAR detector, a laser device, a thermovoltaic device, or a photodiode.

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