Self-compensated printed circuit board (PCB)

Abstract

There is provided a self-compensated printed circuit board (PCB) comprising a plurality of first winding layers each comprising a first plurality of concentric winding turns, a plurality of second winding layers each comprising a second plurality of concentric winding turns, successive turns of the first and the second plurality of turns having a non-uniform width and a non-uniform spacing, and a plurality of separating dielectric layers each interposed between a respective first winding layer and a respective second winding layer, the respective first winding layer being connected in series with the respective second winding layer to form a two-layer winding structure, and successive ones of the two-layer winding structure being connected in parallel.

Description

SELF-COMPENSATED PRINTED CIRCUIT BOARD (PCB)CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] The present application claims the benefit of United States Provisional Patent Application No. 63 / 637,859 filed on April 23, 2024, the contents of which are hereby incorporated by reference.FIELD

[0002] The improvements generally relate to the field of power transfer, and more particularly to a self-compensated PCB for wireless power transfer.BACKGROUND

[0003] Wireless power transfer (WPT) systems use advanced technology for convenient and reliable energy transfer without direct connections. These systems, applied in various fields like medical devices and electric vehicles, rely on electromagnetic fields between transmitter and receiver coil pads. However, over longer distances, leakage fluxes increase impedances. To address this, a resonant circuit is typically used to compensate for leakage impedances and ensure efficient power transfer through electrical resonance. However, this generally requires high frequency and high voltage compensation capacitors to be connected to transmitter and receiver coils, which increases complexity and costs. Furthermore, under resonance, the voltage and current across the compensation capacitors become greater than that of the power source. This results in the generation a large electric field or current density that risks breakdown or changes in nominal values, leading to reduced reliability of the overall WPT system.

[0004] Therefore, there is a need for improvement.SUMMARY

[0005] In accordance with one aspect, there is provided a self-compensated printed circuit board (PCB), the self-compensated PCB comprising a plurality of first winding layers each comprising a first plurality of concentric winding turns, a plurality of second winding layers each comprising a second plurality of concentric winding turns, successive ones of the first plurality of turns and successive ones of the second plurality of turns having a non-uniform width and a non-uniform spacing, and a plurality of separating dielectric layers each interposed between a respective first winding layer and a respectivesecond winding layer, the respective first winding layer being connected in series with the respective second winding layer to form a two-layer winding structure, and successive ones of the two-layer winding structure being connected in parallel.

[0006] In at least one embodiment in accordance with any previous / other embodiment described herein, each of the first and the second plurality of turns comprises an innermost turn and an outermost turn, further wherein, from the innermost turn to the outermost turn, the width is increased by a predetermined width increment and the spacing is decreased by a predetermined spacing decrement.

[0007] In at least one embodiment in accordance with any previous / other embodiment described herein, a same width increment and a same spacing decrement are applied between successive ones of the first and the second plurality of winding turns.

[0008] In at least one embodiment in accordance with any previous / other embodiment described herein, a different width increment and a different spacing decrement are applied between successive ones of the first and the second plurality of winding turns.

[0009] In at least one embodiment in accordance with any previous / other embodiment described herein, the plurality of first winding layers and the plurality of second winding layers are planarly positioned relative to one another and vertically aligned along a central axis.

[0010] In at least one embodiment in accordance with any previous / other embodiment described herein, each first winding layer comprises a first electrical conductor wound to form the first plurality of winding turns and each second winding layer comprises a second electrical conductor wound to form the second plurality of winding turns, each of the first electrical conductor and the second electrical conductor having a first end defining a first terminal and a second end defining a second terminal and being wound from the first end to the second end.

[0011] In at least one embodiment in accordance with any previous / other embodiment described herein, each of the first electrical conductor and the second electrical conductor is wound about a geometrical center of a respective one of the first winding layer and the second winding layer, and the first end is spaced from the geometrical center to define a void thereabout.

[0012] In at least one embodiment in accordance with any previous / other embodiment described herein, the first electrical conductor and the second electrical conductor are wound in a same direction.

[0013] In at least one embodiment in accordance with any previous / other embodiment described herein, the first electrical conductor and the second electrical conductor are wound in opposite directions.

[0014] In at least one embodiment in accordance with any previous / other embodiment described herein, the respective first winding layer is connected in series with the respective second winding layer by connecting the first terminal of the first electrical conductor of the respective first winding layer and the second terminal of the second electrical conductor of the respective second winding layer to an alternating current source, and leaving the second terminal of the first electrical conductor of the respective first winding layer and the first terminal of the second electrical conductor of the respective second winding layer.

[0015] In at least one embodiment in accordance with any previous / other embodiment described herein, the successive ones of the two-layer winding structure are connected in parallel by connecting the second terminals of the first electrical conductors of the successive ones of the two-layer winding structure via a first connecting trace and connecting the first terminals of the second electrical conductors of the successive ones of the two-layer winding structure via a second connecting trace.

[0016] In at least one embodiment in accordance with any previous / other embodiment described herein, each of the plurality of separating dielectric layers creates an intra- winding capacitance between the respective first winding layer and the respective second winding layer of a respective two-layer winding structure, the intra-winding capacitance forming a resonant tank with an inductance of the two-layer winding structure for self- compensation of the PCB.

[0017] In at least one embodiment in accordance with any previous / other embodiment described herein, the self-compensated PCB further comprises a plurality of isolation layers each interposed between a respective pair of adjacent two-layer winding structures.

[0018] In at least one embodiment in accordance with any previous / other embodiment described herein, the successive ones of the two-layer winding structure are connected in parallel to achieve a self-resonant frequency below 150 kHz.

[0019] In accordance with another aspect, there is provided a wireless power transfer (WPT) system comprising a transmitter and a receiver, each of the transmitter and the receiver formed by the self-compensated PCB in accordance with any previous / other embodiment described herein.

[0020] In accordance with another aspect, there is provided a method for providing a self-compensated printed circuit board (PCB), the method comprising providing a plurality of first winding layers each comprising a first plurality of concentric winding turns, providing a plurality of second winding layers each comprising a second plurality of concentric winding turns, successive ones of the first plurality of turns and successive ones of the second plurality of turns having a non-uniform width and a non-uniform spacing, providing a plurality of separating dielectric layers and interposing each separating dielectric layer between a respective first winding layer and a respective second winding layer, connecting the respective first winding layer in series with the respective second winding layer to form a two-layer winding structure, and connecting successive ones of the two-layer winding structure in parallel.

[0021] In at least one embodiment in accordance with any previous / other embodiment described herein, each of the first and the second plurality of turns comprises an innermost turn and an outermost turn, and providing the plurality of first winding layers and providing the plurality of second winding layers comprises, from the innermost turn to the outermost turn, increasing the width by a predetermined width increment and decreasing the spacing by a predetermined spacing decrement.

[0022] In at least one embodiment in accordance with any previous / other embodiment described herein, providing the plurality of first winding layers and providing the plurality of second winding layers comprises one of applying a same width increment and a same spacing decrement between successive ones of the first and the second plurality of winding turns, and applying a different width increment and a different spacing decrement between the successive ones of the first and the second plurality of winding turns.

[0023] In at least one embodiment in accordance with any previous / other embodiment described herein, each separating dielectric layer creates an intra-winding capacitance between the respective first winding layer and the respective second winding layer of a respective two-layer winding structure, the intra-winding capacitance forming a resonant tank with an inductance of the two-layer winding structure for self-compensation of the PCB.

[0024] In at least one embodiment in accordance with any previous / other embodiment described herein, the successive ones of the two-layer winding structure are connected in parallel to achieve a self-resonant frequency below 150 kHz.

[0025] Many further features and combinations thereof concerning embodiments described herein will appear to those skilled in the art following a reading of the instant disclosure.DESCRIPTION OF THE FIGURES

[0026] In the figures,

[0027] Fig. 1 A is an exploded perspective view of a two-layer self-compensated PCB, in accordance with one embodiment;

[0028] Fig. 1 B is a side perspective view of the two-layer self-compensated PCB of Fig. 1A;

[0029] Fig. 2 is a perspective view of a multi-layer self-compensated PCB, in accordance with one embodiment;

[0030] Fig. 3 is a schematic diagram of a vertical cross-section of the multi-layer self- compensated PCB arrangement of Fig. 2, in accordance with one embodiment;

[0031] Fig. 4 is an equivalent circuit configuration of the multi-layer self-compensated PCB arrangement of Fig. 2, in accordance with one embodiment;

[0032] Fig. 5A shows the circuit analysis of the end loop of the equivalent circuit configuration of Fig. 4;

[0033] Fig. 5B shows the end loop equivalent circuit for the configuration of Fig. 4;

[0034] Fig. 5C shows the equivalent circuit of the two-layer self-compensated PCB of Fig. 1A;

[0035] Fig. 6 is a schematic diagram showing the parasitic capacitance forthe proposed coil structure, in accordance with one embodiment;

[0036] Fig. 7A and Fig. 7B illustrate the frequency characteristics of the proposed coil, in accordance with one embodiment;

[0037] Fig. 8 illustrates the coil to coil efficiencies and output power as load varies, in accordance with one embodiment;

[0038] Fig. 9A and Fig. 9B illustrate the output power and efficiencies at different frequencies and different distances, in accordance with one embodiment;

[0039] Fig. 10 illustrates the output power and efficiencies at different distances, in accordance with one embodiment;

[0040] Fig. 11A and Fig. 11 B illustrate the coupling coefficient at different distances, without misalignment and with horizontal misalignment, in accordance with one embodiment; and

[0041] Fig. 12A and Fig. 12B illustrate the steady-state voltage and current waveform of transmitter and receiver coils, in accordance with one embodiment.

[0042] Many further features and combinations thereof concerning embodiments described herein will appear to those skilled in the art following a reading of the instant disclosure.DETAILED DESCRIPTION

[0043] Described herein is a self-compensated printed circuit board (PCB) in which intra-winding capacitance is used for compensation to attain self-resonance. The PCB described herein may be used in a range of long- and short-range implementations and in a variety of fields. In one embodiment, the PCB may be used for Wireless Power Transfer (WPT), which has been widely used for charging and powering applications. In charging applications, the WPT system is used for wireless transfer of electrical energy between a transmitter and a receiver. In this case, the PCB described herein may serve as a coupler(e.g., a magnetic coupler) for the transmitter and receiver charging pads. Electrical power can then be transferred wirelessly through the magnetic coupling between the transmitter and receiver coils. It should however be understood that other embodiments may apply. For example, the PCB described herein may be used for electric motor applications. In this case, the PCB coil could be used to transfer energy to rotor windings of wound rotor synchronous machines, so as to eliminate the brush and improve reliability.

[0044] Referring to Fig. 1A and Fig. 1 B, an example of a two-layer (or double-layer) self-compensated PCB (also referred to herein as a PCB coil or a two-layer winding structure) 100 will now be described, in accordance with one embodiment. The PCB 100 is a winding structure formed of a first substantially planar winding layer 102, a second substantially planar winding layer 104, and a separating layer 106 disposed in the space between the first layer 102 and the second layer 104. The separating layer 106 is made of a dielectric material configured to create capacitance (also referred to herein as “intra- winding capacitance”) between the layers 102, 104, the intra-winding capacitance forming a resonant tank with the coil inductance (i.e. the inductance of the two-layer winding structure 100), as will be discussed further below. In particular, the intra-winding capacitance is used for compensation, eliminating the need for an additional physical capacitor (or compensation circuit) which typically increases PCB size, manufacturing costs, and potential points of failure. By integrating inductance and compensation capacitance in the same structure, the PCB 100 achieves self-compensation.

[0045] The separating layer 106 may have any suitable thickness. The layers 102, 104, and 106 are arranged vertically (i.e. stacked) so as to be planarly positioned (i.e. substantially parallel) relative to one another and aligned (i.e. positioned directly over each another) with respect to a central axis A. Although Fig. 1 A shows the layers 102, 104, 106 as being spaced from one another, this is for illustration purposes and without limitation, and it should be understood that the layers 102, 104, 106 may be arranged so that no air gap remains between the stacked layers 102, 104, 106 upon completion of assembly of the PCB 100, as can be seen from Fig. 1 B.

[0046] The first layer 102 comprises a first electrical conductor 1081and the second layer 104 comprises a second electrical conductor 1082identical to the first conductor 1081. The conductors 1081, 1082may be made of any suitable material including, but not limited to, copper. For instance, each conductor 1081, 1082may be formed by conductingcopper traces on or in a substrate (not shown) such as a PCB. In particular, the traces may be printed onto the PCB surface, thereby leveraging existing PCB fabrication processes.

[0047] Each conductor 1081, 1082has a first end defining a first (or inner) terminal (or lead) 1101and a second end defining a second (or outer) terminal (or lead) 1102. The first end defining the first terminal 1101of each conductor 1081, 1082is positioned adjacent to the geometrical center 1 12 of the respective layer 102, 104, at a distance (d1) from the geometrical center 1 12. In this manner, a void 1 14 (or core, such as an air core) is created about the geometrical center 112. The distance (d1) may have any suitable value such that the void 114 may have any suitable size. Each conductor 1081, 1082is then wound, from the first end to the second end (i.e., from the first terminal 1101to the second terminal 1102), in a plurality (N’) of turns 1111, 1112, ... 11 1Nthat are concentric about a geometrical center 112 of the respective layer 102, 104. The conductors 1081, 1082are wound away from the geometrical center 1 12 and towards the outermost boundary (or edge) 113 of the respective layer 102, 104. As can be seen from Fig. 1 B, the void 1 14 is delimited by the innermost turn 1111of the respective conductor 1081, 1082. In one embodiment, both conductors 1081, 1082are wound in the same winding direction (e.g., counterclockwise). It should however be understood that, in other embodiments, the conductors 1081, 1082may be wound in opposite winding directions (e.g., with the conductor 1081being wound counterclockwise and the conductor 1082being wound clockwise, or vice-versa). In the illustrated embodiment, the second end defining the second terminal H O2 extends away from (i.e. beyond) the edge 113 by a given distance (d2). It should however be understood that each conductor 1081, 1082may be wound such that the second end is flush with the edge 113.

[0048] Although Fig. 1A and Fig. 1 B illustrate an embodiment in which each conductor 1081, 1112is wound around ten (10) turns 1111, 1 112, ... 11 1N(i.e. N’ = 10), it should be understood that any suitable number of turns 1111, 1 112, ... 11 1Nmay apply. The number of turns 1111, 1 112, ... 11 1Nmay indeed vary depending on the application, e.g., on the dimensions (such as the total length and width) of each layer 102, 104, on the width of the conductors 1081, 1082, and on the spacing between successive turns 1111, 1 112, ... 11 1Nof the conductors 1081, 1082.

[0049] The turns 1111, 11 12, ... 11 1Nmay be wound so as to form any suitable shape or configuration that is symmetrical about the geometrical center A of the respective layer 102, 104. In one embodiment, the turns 1111, 1 112, ... 11 1Nform a rectangular shape and each layer 102, 104, 106 is rectangular-shaped to achieve a rectangular-shaped PCB 100, as illustrated in Fig. 1A. It should however be understood that other embodiments may apply. For example, the turns 1111, 1 112, ... 11 1Nmay form a square shape, a triangular shape, a polygonal shape (such as a pentagonal or a hexagonal shape), a round or circular shape, a spiral shape, an elliptical shape, or any other appropriate shape. Although Fig. 1A illustrates the corners of the layers 102, 104 (i.e. the corners formed by the turns 111 i, 11 12, ... 1 11N) as being square, it should be understood that the corners may be rounded. It will also be understood that most coils are commonly designed with circular or square shapes. The coupling coefficient of circular and square shapes is indeed approximately the same. However, in some embodiments, it may be desirable to achieve a square shape, which offers higher space efficiency (i.e. about 30% more capacitance) than a circular shape within the same defined space. In addition, the inductance produced by a square shape is typically greater than that produced by a circular shape, while the resistance value is lower, potentially leading to better overall performance and higher quality factor when a square shape is used.

[0050] In one embodiment, the first terminal 1101of the first conductor 108i and the second terminal 1 102of the second conductor 1082are configured to be connected to an alternating current (AC) source (not shown), i.e. to a positive and a negative terminal thereof, while the second terminal 1102of the first conductor 108i and the first terminal 1101of the second conductor 1082are left open (i.e. unconnected). In this manner, the conductors 1081, 1082are connected electrically in series such that, when the conductors 1081, 1082are connected to the AC source, current flows distributedly from the first terminal 1101of the first conductor 108i to the second terminal 1102of the second conductor 1082. The current covers the entire shape (e.g., spiral) formed by the wound conductors 1081, 1082and crosses the separating layer 106, thus creating a combination of an inductor (L) and a capacitor (C) connected in series, referred to as a series LC tank circuit.

[0051] As can be seen in Fig. 1 B, each conductor 1081, 1082has a given width (w) and a given spacing (s) separates successive turns 1111, 1112, ... 1 11Nof the conductor 1081, 1082. It is proposed herein to vary the width and the spacing as the conductors 1081, 1082are turned, such that the width and the spacing are non-uniform (i.e. variable or different) between successive turns 1111, 1 112, ... 11 1N. In particular, each of the width and the spacing has a starting value which is progressively varied as the conductor 1081, 1082is wound towards the edge 1 13 of the respective layer 102, 104, from the first turn 1111to the last turn 11 1N. In other words, the width and the spacing vary from the geometrical center 112 of each layer 102, 104 to the edges 1 13 of the layers 102, 104. In one embodiment, the width is increased and the spacing is decreased from the first turn 1111to the last turn 11 1N. In particular, the width is gradually increased from an innermost or first turn 1111(i.e. that which is the closest to the geometrical center 112) to an outermost or last turn 11 1N(i.e. that which is the closest to the edge 1 13), and the spacing is gradually decreased from the innermost turn 1111to the outermost turn 11 1N. In one embodiment, the value of the width increment and the value of the spacing decrement remain the same for successive turns 1111, 11 12, ... 11 1N(i.e. from one turn 1111, 1112, ... 11 1Nto the next), such that the width increase and the spacing decrease are uniform (i.e. remain the same) from one turn 1111, 1 112, ... 11 1Nto the next. The value of the width increment and the value of the spacing decrement may however vary, such that the width increase and the spacing decrease are non-uniform from one turn 1111, 1 112, ... 11 1Nto the next. Thus, each turn 1111, 11 12, ... 11 1Nmay have a unique configuration of conductor width and spacing.

[0052] In one embodiment, each conductor 1081, 1082is would around ten (10) turns (i.e. N’ = 10), has a width having a starting value of (i.e. the width of the innermost turn 1111is) 3.75 mm, and a spacing having a starting value of (i.e. the spacing between the innermost turn 1111and the second inner turn 1 112is) 3.5 mm separates successive turns 1111, 1 112, ... 11 1Nof each conductor 1081, 1082. The width is then gradually increased by an increment of 0.5 mm, so as to range from 3.75 mm (for the innermost turn 1111) to 8.25 mm (for the outermost turn 111N). The spacing is also gradually decreased by a decrement of 0.25 mm, so as to range from 3.5 mm (between the innermost turn 1111and the second inner turn 1112) to 1 .5 mm (between the turn before last, not shown, and the outermost turn 111N). It should however be understood that any suitable starting value for the width and the spacing, any suitable width increment, and any suitable spacing decrement may apply, depending on the application.

[0053] Referring now to Fig. 2, multiple ones of the two-layer PCB (reference 100 in Fig. 1A) may be connected electrically in parallel to increase the intra-windingcapacitance, effectively lowering the self-resonant frequency. In one embodiment, the self- resonant frequency may be reduced to below 150 kHz. This is illustrated in Fig. 2, which shows an example of a multilayer self-compensated PCB arrangement 200 comprising a plurality (n) of two-layer PCBs (also referred to herein as two-layer coils or two-layer winding structures) 2021, 2022, ... , 202narranged in a parallel configuration. In particular, the second terminals 1102of the first conductors 1081of the two-layer coils 2021, 2022, ... , 202nare connected together via a connecting trace 204, and the first terminals 1101ofthe second conductors 1082of the two-layer coils 2021, 2022, ... , 202nare connected together via a connecting trace 206. It should however be understood that, alternatively, the first terminals 1101of the first conductor 1081of each two-layer coil 2021, 2022, ... , 202nmay be connected together, and the second terminals 1102of the second conductor 1082of each two-layer coil 2021, 2022, .... 202nmay be connected together. Each two-layer coil 2021, 2022, . . , 202nis configured as illustrated and described herein with reference to Fig. 1A and 1 B such that the same materials are used in each two-layer coil 2021, 2022, ... , 202n.

[0054] The arrangement 200 further comprises a plurality of isolation layers 2081, ... , 208n-1, each isolation layer 2081, ... , 208n-1being provided between a respective pair of adjacent two-layer coils 2021, 2022, ... , 202nfor insulation purposes. In this manner, every two adjacent coil layers 102, 104 have an intra-winding capacitance, and all the intra- winding capacitances are in parallel, with the total capacitance for the arrangement 200 being the sum of the individual intra-winding capacitances. The isolation layers 2081, ... , 208n-1may be made of any suitable material including, but not limited to, insulation paper (thin paper sheets impregnated with insulating varnish, providing good electrical insulation and dielectric strength), polyimide (durable and heat-resistant polymer film used for high- temperature applications where thermal stability is crucial) such as Kapton, Polyethylene (PE) or Polypropylene (PP) Film (flexible plastic films offering good dielectric properties and moisture resistance), Mylar (polyester film commonly used for its high tensile strength and dielectric properties), Teflon or PTFE (known for its excellent electrical properties, chemical resistance, and high-temperature stability, making it suitable for demanding applications), epoxy resin (used for potting or encapsulating coils, providing mechanical protection and electrical insulation), glass-reinforced epoxy laminate materials (such as FR-4 with a thickness of 0.2 mm), and Rogers materials with high relative permeability.

[0055] Fig. 3 shows a vertical cross-section 300 of the multilayer arrangement 200 of Fig. 2. From Fig. 3, it can be seen that the multilayer arrangement 200 is supported by a supporting layer 302 positioned underneath the first two-layer coil (reference 2021in Fig. 2). The supporting layer 302 may be made of any suitable material including, but not limited to, ferrite.

[0056] For modeling purposes, each two-layer coil (reference 2021, 2022, ... , 202nin Fig. 2) is subdivided into a plurality (N) of segments and each segment is denoted by an inductor L. Each turn of the total N’ turns (reference 111 i, 1112, ... 11 1Nin Fig. 1 A) of the conductors (references 1081, 1082in Fig. 1A) in each two-layer coil 2021, 2022, ... , 202ncan be considered as a one-turn inductor, indicated as L(N,N’). The capacitor represented by C(N,N’) accounts for the capacitance between each turn and its neighboring two-layer coil. Notably, due to the equal length of L(1 ,n) and L(2,n), inductances within corresponding pairs (L(1 ,n) and L(2,n)) are equal (see equation (1) below), but those between segment pairs differ. (1)

[0057] The symmetrical conductor layout and using the same materials in each two- layer coil 2021, 2022, . . , 202nmake capacitors identical, as follows: (2)

[0058] Fig. 4 shows an equivalent circuit configuration 400 of the multilayer arrangement 200 of Fig. 2. The multi-loop structure is represented by an equivalent circuit containing two (2) pairs of capacitors and inductors in each loop of the circuit. The voltage of L(1 ,n) and L(2,n) can be written as:

[0059] With regards to the above relationship defined by equation (3), we have: (4)

[0060] According to equation (4), the voltage of each pair of inductors is identical. In a two-layer coil, the voltage equation is given by:

[0061] Where Vc(i.n) is the voltage of nthcapacitance between a pair of two-layer coils. Thus, considering the equality of the voltages across the two inductors, the voltages across the capacitors become equal as well. However, the actual sizes of the capacitors may vary. Therefore:(6)

[0062] where i = 1 , 2, ... , N and n = 1 , 2, ... , N’+1.

[0063] Reference will now be made to Fig. 5A, Fig. 5B, and Fig. 5C. Fig. 5A shows a schematic diagram 500 illustrating the circuit analysis of the end loop of the circuit configuration 400 of Fig. 4. Fig. 5B illustrates an end loop equivalent circuit 510. Fig. 5C illustrates the equivalent circuit 520 of a two-layer coil (reference 2021, 2022, ... , 202nin Fig. 2). As illustrated in Fig. 5A, the Kirchhoffs Current Law (KCL) is used to calculate the equivalent capacitance in a two-layer coil. With lin1and lin1as the input currents and loutas the output current, the relationship is given by:

[0064] Therefore, the equivalent capacitance equals the sum of the capacitors of each section. To determine the equivalent inductance for each two-layer coil, the voltage across L(1 ,N’) is assessed. This voltage, comprising its self-induced voltage and induced voltage from L(2,N’) is expressed as:

[0065] Where M is the mutual inductance between L(1 ,N’) and L(2,N’) which is given by:

[0066] Given the thin insulating layer (i.e. separating layer 106 in Fig. 1A) and consistent coil geometry, a uniform magnetic field permeates both copper foils on top and bottom of the dielectric. Consequently, the coupling coefficient (k) is treated as 1 and the following equation is obtained: (1 1 )

[0067] Therefore, the equation (9) can be rewritten as follows:

[0068] Based on the aforementioned calculations, the equivalent circuit in the nthloop is comprised of an inductance and a capacitor, as illustrated in FIG. 5B and FIG. 5C. By generalizing these relations across all loops, the equivalent capacitance in the initial two- layer coil (reference 2021in Fig. 2) is the sum of all capacitors, while the equivalent inductance in subsequent sections can be determined accordingly, as will be described further below.

[0069] The inductance of the multi-turn planar spiral coil (e.g., reference 2021in Fig. 2) is determined by the sum of the self-inductance for each turn and both positive and negative mutual inductances between turns, as indicated by:(13)

[0070] Self-inductance is calculable as follows:

[0071] Where μo, tn, wnrepresent the permeability of free space, thickness, and width of the nthcoil turn, respectively, and dn represents the length of each turn, as indicated by:(15)(16)

[0072] 11 and I2 denote the dimension of each side of the spiral planar coil. The calculation for positive and negative mutual inductance is as follows:(17)(18)

[0073] Where positive mutual inductance signifies the presence of identical current directions in each coil section, whereas negative mutual inductance indicates opposing current directions in their respective coils.

[0074] In the proposed structure, the electric field is composed of an electric field oriented vertically between each pair of two-layer coils (references 2021, 2022, ... , 202nin Fig. 2) within the dielectric, and undesirable fringing electric fields between adjacent traces. As illustrated in FIG. 2, there is a thin (e.g., having a thickness of about 0.2 mm) isolation layer (references 2081, ... , 208n-1in Fig. 2) between each pair of two-layer coils 2021, 2022, . . , 202n. Each two-layer coil 2021, 2022, .... 202ngenerates capacitance, and the isolation layers 2081, ... , 208n-1provide electrical insulation and another capacitance, The capacitance between these two-layer coils 2021, 2022, ... , 202nis computed similarly to that of a planar capacitor. Thus, each layer's total area ( ATotal) equals the sum of the individual areas (A1, A2, ... , AN) of every turn, as follows :ATotal=A1+ A2+ . . . + AN ( 19)

[0075] Consequently, the capacitance produced by a two-layer coil 2021, 2022, ..., 202n(also referred to herein as the “layer-to-layer capacitance”) is calculated as follows:

[0076] Where c / 1 , k1 , and εo represent the dielectric thickness, relative permittivity of the dielectric, and permittivity of free space, respectively. In addition to the capacitance generated in equation (20), the fringing electric field between turns also contributes to the creation of parasitic capacitance, particularly when the distance between two turns is minimal. As shown in Fig. 6, the fringing electric field applies to two adjacent turns with the air and dielectric. Cairand CDielectriccorrespond to the capacitance involving air and dielectric, respectively, which can be calculated based on conformal mapping and the assumption of the magnetic wall, as follows:(21)(22)

[0077] Where,(23)

[0078] Consequently, the parasitic capacitance between two turns is as follows:(24)

[0079] The overall capacitance of a multi-layer PCB coil, with isolated paper (i.e an isolation layer 2081, ..., 208n-1) between each two-layer coil 2021, 2022, ... , 202n, can be described as:(25)

[0080] Where n is the number of layers. Therefore, based on equation (25), increasing the number of layers allows for the production of a larger capacitance, consequently resulting in lower resistance and a low resonant frequency.

[0081] Coil resistance is determined by the sum of proximity effect resistance and skin effect resistance:(26)

[0082] Skin effect is the phenomenon where higher-frequency currents tend to concentrate nearthe surface of a conductor, limiting their penetration into the interior. This effect can be computed using the following formula:

[0083] Where o stands for the coil's conductivity. In Equation (27), the parameters α, β, and T are expressed as:(28)

[0084] Proximity effect refers to the phenomenon where the distribution of current in a conductor is affected by the presence of neighboring conductors, leading to non-uniform current density and increased resistance. The calculation is as follows:(29)Where,(30)

[0085] Hnindicates the magnetic field that is perpendicular to the turn's surface when exposed to a current of 1A. The calculation of dielectric loss relies on the dielectric material's loss tangent, expressed as Dk, which is given by:

[0086] Therefore, the total resistance of the coil can be calculated as expressed by: (32)

[0087] The inductance, resistance, and capacitance equations presented above underscore the influence of variations in the width, distance, and thickness of the traces in the multi-layer planar coil. Thus, the quality factor of the whole system can be derived as follows:(33)

[0088] In order to validate the self-compensated PCB proposed herein, experimental measurements were obtained using an experimental setup. Forthis purpose, six two-layer coils (reference 100 in Fig. 1A) were connected in parallel (to obtain an arrangement 200 as illustrated in Fig. 2) to form each of the transmitter and receiver coils of a WPT system. Direct current (DC) powerwas provided to the system by a DC power supply (e.g., a 6554 A DC power supply). An H-bridge inverter, utilizing semiconductors (e.g., metal-oxide- semiconductor field-effect transistors (MOSFETs) was employed to generate a high- frequency AC input. The generation and regulation of pulse-width modulation (PWM) signals, featuring a 50 ns dead time and a 50% duty cycle, were carried out by a digital signal processor (DSP) microcontroller. A diode rectifier was constructed using Schottky diodes, and a 200uF capacitor was used as an output filter. To determine the resonant frequency of the PCB coils, a network analyzer was utilized. The measured values for the capacitor and inductor in the parallel-connected multilayer self-compensated coils were 48.8 nF and 26 uH, respectively. Using the network analyzer, the impedance and phase of the self-resonant PCB were measured, as respectively illustrated in plots 700 and 710 of Fig. 7A and Fig. 7B, across a frequency range from about 100 kHz to about 250 kHz.The resonance frequency was identified at the minimum impedance, where the phase angle becomes zero. As can be seen in Fig. 7B, the resonant frequency of the coils was about 147.5 kHz.

[0089] In order to assess the impact of a load positioned at a given distance (e.g., 30 mm) between the transmitter and receiver coils, measurements of output power and coil to coil efficiency were conducted for various loads ranging from 10 Ω to 70 Ω, as depicted in the plot 800 of Fig. 8. As can be seen from Fig. 8, when the load is 25 Ω, the system achieves maximum efficiency of about 94.2%, while a load of 55 Ω allows for the transfer of about 174.6 watts of power. Fig. 9A and Fig. 9B further respectively illustrate plots 900 and 910 of the system's output power and coil-to-coil efficiencies across different frequencies and distances of 30 mm, 50 mm, and 70 mm. As depicted in Fig. 9A, measurements were conducted at all three distances within the frequency range, specifically up to about 150 kHz (i.e. up to the resonant frequency where the system exhibits minimum impedance), maximizing power transfer. As observed in Fig. 9A, at all three distances and when the frequency is around 150 kHz, which is the resonant frequency, both current and transfer power reach their maximum values. Similar results for efficiency are also illustrated in Fig. 9B, indicating maximum efficiency at the resonant frequency for all three distances. This demonstrates that, as the distance between the two coils increases, due to reducing the coupling coefficient between the coils, the efficiency decreases. The highest efficiency is achieved when the distance is 30 mm, reaching 94.2%. Fig. 10 further illustrates a plot 1000 of the power and efficiency of the system at various distances with a load of 25 Ω. As depicted, increasing the distance results in an increase in power, reaching its maximum at 50 mm. However, the efficiency decreases with the distance increment due to the lower coupling coefficient. The maximum efficiency is achieved when the distance is 30 mm.

[0090] The coupling coefficient is depicted in the plot 1100 of Fig. 11A for different distances, and in the plot 1110 of Fig. 11 B for horizontal misalignment. The figures reveal that the coupling coefficient decreases with increasing distance. Therefore, optimizing the coils with lower resistance can enhance the system's quality factor, subsequently improving power and efficiency.

[0091] Fig. 12A and Fig. 12B respectively display plots 1200 and 1210 of the steady- state voltage and current waveforms for both the transmitter and receiver coils. Underspecific conditions (i.e., a 25 Ω load, a 30 mm transmission distance, and an operating frequency of 150 kHz), the input voltage is 80V, and the output voltage is 73V. No phase difference is noted between the voltage and current of the receiver. Consequently, in one embodiment, the proposed coil attains a maximum efficiency of 94.1 % and achieves maximum power transfer at 210 W.

[0092] In some embodiments, the layout optimization of the self-compensated PCB coil proposed herein may leverage intra-winding capacitance to form a resonant tank, eliminating the need for a physical capacitor and achieving self-compensation. In particular, the proposed coil may allow to achieve higher capacitance and inductance than existing coil designs, while lowering resistance, which suggests that the proposed coil may offer improved performance across multiple key parameters. Furthermore, parallel connection of multilayer PCB coils may enhance intra-winding capacitance, reducing the resonant frequency. In particular, while existing coil designs with similar dimensions achieved capacitance values of about 1.5 nF and 2.2 nF, the proposed coil design yielded capacitance values of about 6.5 nF. Moreover, by increasing the spacing between the conductor traces and narrowing the width of the conductor traces in the center of the PCB coils, the quality factor may be improved (particularly at low frequencies, e.g., below 150 kHz, where achieving a high-quality factor is more challenging than at higher frequencies, e.g. in the MHz range) and coil resistance reduced, thus increasing the overall Power Transfer Efficiency (PTE). High performance may therefore be achieved in a compact and self-resonant design.

[0093] The above description is meant to be exemplary only, and one skilled in the art will recognize that changes may be made to the embodiments described without departing from the scope of the invention disclosed. Still other modifications which fall within the scope of the present invention will be apparent to those skilled in the art, in light of a review of this disclosure.

[0094] Various aspects of the systems and methods described herein may be used alone, in combination, or in a variety of arrangements not specifically discussed in the embodiments described in the foregoing and is therefore not limited in its application to the details and arrangement of components set forth in the foregoing description or illustrated in the drawings. For example, aspects described in one embodiment may be combined in any manner with aspects described in other embodiments. Althoughparticular embodiments have been shown and described, it will be apparent to those skilled in the art that changes and modifications may be made without departing from this invention in its broader aspects. The scope of the following claims should not be limited by the embodiments set forth in the examples, but should be given the broadest reasonable interpretation consistent with the description as a whole.

Claims

WHAT IS CLAIMED IS:1 . A self-compensated printed circuit board (PCB), the self-compensated PCB comprising: a plurality of first winding layers each comprising a first plurality of concentric winding turns; a plurality of second winding layers each comprising a second plurality of concentric winding turns, successive ones of the first plurality of turns and successive ones of the second plurality of turns having a non-uniform width and a non-uniform spacing; and a plurality of separating dielectric layers each interposed between a respective first winding layer and a respective second winding layer, the respective first winding layer being connected in series with the respective second winding layer to form a two-layer winding structure, and successive ones of the two-layer winding structure being connected in parallel.

2. The self-compensated PCB of claim 1 , wherein each of the first and the second plurality of turns comprises an innermost turn and an outermost turn, further wherein, from the innermost turn to the outermost turn, the width is increased by a predetermined width increment and the spacing is decreased by a predetermined spacing decrement.

3. The self-compensated PCB of claim 2, wherein a same width increment and a same spacing decrement are applied between successive ones of the first and the second plurality of winding turns.

4. The self-compensated PCB of claim 2, wherein a different width increment and a different spacing decrement are applied between successive ones of the first and the second plurality of winding turns.

5. The self-compensated PCB of any one of claims 1 to 4, wherein the plurality of first winding layers and the plurality of second winding layers are planarly positioned relative to one another and vertically aligned along a central axis.

6. The self-compensated PCB of any one of claims 1 to 5, wherein each first winding layer comprises a first electrical conductor wound to form the first plurality of winding turns and each second winding layer comprises a second electrical conductor wound to form thesecond plurality of winding turns, each of the first electrical conductor and the second electrical conductor having a first end defining a first terminal and a second end defining a second terminal and being wound from the first end to the second end.

7. The self-compensated PCB of claim 6, wherein each of the first electrical conductor and the second electrical conductor is wound about a geometrical center of a respective one of the first winding layer and the second winding layer, further wherein the first end is spaced from the geometrical center to define a void thereabout.

8. The self-compensated PCB of claim 6 or 7, wherein the first electrical conductor and the second electrical conductor are wound in a same direction.

9. The self-compensated PCB of claim 6 or 7, wherein the first electrical conductor and the second electrical conductor are wound in opposite directions.

10. The self-compensated PCB of any one of claims 6 to 9, wherein the respective first winding layer is connected in series with the respective second winding layer by connecting the first terminal of the first electrical conductor of the respective first winding layer and the second terminal of the second electrical conductor of the respective second winding layer to an alternating current source, and leaving the second terminal of the first electrical conductor of the respective first winding layer and the first terminal of the second electrical conductor of the respective second winding layer.

11. The self-compensated PCB of any one of claims 6 to 10, wherein the successive ones of the two-layer winding structure are connected in parallel by connecting the second terminals of the first electrical conductors of the successive ones of the two-layer winding structure via a first connecting trace and connecting the first terminals of the second electrical conductors of the successive ones of the two-layer winding structure via a second connecting trace.

12. The self-compensated PCB of any one of claims 1 to 11 , wherein each of the plurality of separating dielectric layers creates an intra-winding capacitance between the respective first winding layer and the respective second winding layer of a respective two-layer winding structure, the intra-winding capacitance forming a resonant tank with an inductance of the two-layer winding structure for self-compensation of the PCB.

13. The self-compensated PCB of any one of claims 1 to 12, further comprising a plurality of isolation layers each interposed between a respective pair of adjacent two-layer winding structures.

14. The self-compensated PCB of any one of claims 1 to 13, wherein the successive ones of the two-layer winding structure are connected in parallel to achieve a self-resonant frequency below 150 kHz.

15. A wireless power transfer (WPT) system comprising a transmitter and a receiver, each of the transmitter and the receiver formed by the self-compensated PCB of any one of claims 1 to 14.

16. A method for providing a self-compensated printed circuit board (PCB), the method comprising: providing a plurality of first winding layers each comprising a first plurality of concentric winding turns; providing a plurality of second winding layers each comprising a second plurality of concentric winding turns, successive ones of the first plurality of turns and successive ones of the second plurality of turns having a non-uniform width and a non-uniform spacing; providing a plurality of separating dielectric layers and interposing each separating dielectric layer between a respective first winding layer and a respective second winding layer; connecting the respective first winding layer in series with the respective second winding layer to form a two-layer winding structure; and connecting successive ones of the two-layer winding structure in parallel.

17. The method of claim 16, wherein each of the first and the second plurality of turns comprises an innermost turn and an outermost turn, further wherein providing the plurality of first winding layers and providing the plurality of second winding layers comprises, fromthe innermost turn to the outermost turn, increasing the width by a predetermined width increment and decreasing the spacing by a predetermined spacing decrement.

18. The method of claim 17, wherein providing the plurality of first winding layers and providing the plurality of second winding layers comprises one of: applying a same width increment and a same spacing decrement between successive ones of the first and the second plurality of winding turns; and applying a different width increment and a different spacing decrement between the successive ones of the first and the second plurality of winding turns.

19. The method of any one of claims 16 to 18, wherein each separating dielectric layer creates an intra-winding capacitance between the respective first winding layer and the respective second winding layer of a respective two-layer winding structure, the intra- winding capacitance forming a resonant tank with an inductance of the two-layer winding structure for self-compensation of the PCB.

20. The method of any one of claims 16 to 19, wherein the successive ones of the two- layer winding structure are connected in parallel to achieve a self-resonant frequency below 150 kHz.

Images