Display panel, gate driving circuit, shift register, and driving method therefor

Abstract

A display panel, a gate driving circuit, a shift register (GOA), and a driving method therefor. An input circuit (10) is used for, in response to a first clock signal (CK), transmitting an input signal to a first input node (N2); a first control circuit (20) is used for, under the control of one of the input signal and a signal of the first input node (N2), and the voltage of a second voltage end and the voltage of a third voltage end, controlling the voltage of a second input node (N1); the second input node (N1) is connected to a second output node (N6); an output circuit (70) is used for turning on or off a second clock signal end and an output end (OUT); and an output control circuit (60) is used for turning on or off the second voltage end and the output end (OUT).

Description

Display panel, gate drive circuit, shift register and its driving method

[0001] Cross-referencing

[0002] This disclosure claims priority to Chinese Patent Application No. 202410495141.9, filed on April 23, 2024, entitled “Display Panel, Gate Driving Circuit, Shift Register and Driving Method Thereof,” the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of display technology, and more specifically, to a display panel, a gate driving circuit, a shift register, and a method for driving the shift register. Background Technology

[0004] In display panels that use light-emitting diodes (LEDs) as light-emitting devices, the pixel circuits are typically scanned using scanning signals output from a driving circuit, which includes multiple shift registers. These shift registers then output the scanning signals to the pixel circuits.

[0005] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art.

[0006] Summary of the Invention

[0007] This disclosure provides a display panel, a gate driving circuit, a shift register, and a driving method thereof, which can output scanning signals to a pixel circuit.

[0008] According to one aspect of this disclosure, a shift register is provided, comprising:

[0009] An input circuit is connected to an input terminal, a first clock signal terminal, and a first input node, and is configured to transmit an input signal provided by the input terminal to the first input node in response to a first clock signal provided by the first clock signal terminal, wherein the first input node is connected to a first output node;

[0010] A first control circuit is connected to the input terminal or the first input node, and to a second voltage terminal, a third voltage terminal, and a second input node; the first control circuit is configured to control the voltage of the second input node under the control of one of the input signal and the signal of the first input node, the voltage of the second voltage terminal, and the voltage of the third voltage terminal; the second input node is connected to a second output node;

[0011] An output circuit is connected to the first output node, the third voltage terminal, the second clock signal terminal, and the output terminal, and is configured to turn on or off the second clock signal terminal and the output terminal under the control of the voltage of the first output node, wherein the second clock signal terminal is used to provide a second clock signal.

[0012] An output control circuit is connected to a second output node, a second voltage terminal, and the output terminal, and is configured to turn the second voltage terminal and the output terminal on or off under the control of the voltage of the second output node.

[0013] In one exemplary embodiment of this disclosure, the first control circuit includes a first control transistor, a second control transistor, and a control energy storage circuit; the gate of the first control transistor is connected to the input terminal or the first input node, the first electrode is connected to the second voltage terminal, and the second electrode is connected to the control node; the gate of the second control transistor is connected to the control node, the first electrode is connected to the third voltage terminal, and the second electrode is connected to the second input node; the control energy storage circuit is connected to the control node and the first clock signal terminal.

[0014] In one exemplary embodiment of this disclosure, the control energy storage circuit includes an input control capacitor connected to the control node and the first clock signal terminal.

[0015] In one exemplary embodiment of this disclosure, the shift register further includes a voltage regulator circuit connected to a first voltage terminal, the first output node, and the first input node, and configured to turn the first output node and the first input node on or off under the control of the voltage at the first voltage terminal, and to stabilize the voltage of the first output node when it is on.

[0016] In one exemplary embodiment of this disclosure, the shift register further includes a second control circuit connected to the second voltage terminal, the first input node, and the second input node, and configured to be turned on or off under the control of the voltage of the first input node, thereby controlling the voltage of the second input node. When the second control circuit is turned on, the voltage of the second output node is made to match the voltage of the second voltage terminal.

[0017] In one exemplary embodiment of this disclosure, the shift register further includes a third control circuit connected to a third clock signal terminal, the first input node, the second input node, and the second voltage terminal, and configured to be turned on or off under the control of a third clock signal provided by the third clock signal terminal and the voltage of the second input node, and when the third control circuit is turned on, to make the voltage of the first input node consistent with the voltage of the second voltage terminal.

[0018] In one exemplary embodiment of this disclosure, the input circuit includes an input transistor, the gate of which is connected to the first clock signal terminal, the first electrode of which is connected to the input terminal, and the second electrode of which is connected to the first input node;

[0019] The output control circuit includes an output control transistor and an output control capacitor. The gate of the output control transistor is connected to the second output node, the first terminal is connected to the second voltage terminal, and the second terminal is connected to the output terminal. The output control capacitor is connected to the gate and the second terminal of the output control transistor.

[0020] The output circuit includes an output transistor and an output capacitor. The gate of the output transistor is connected to the first output node, the first terminal is connected to the second clock signal terminal, and the second terminal is connected to the output terminal. The output capacitor is connected to the gate and the second terminal of the output transistor.

[0021] The voltage regulator circuit includes a Zener transistor, the gate of which is connected to the first voltage terminal, the first terminal of which is connected to the first input node, and the second terminal of which is connected to the first output node.

[0022] The second control circuit includes a third control transistor, the gate of which is connected to the first input node, the first terminal of which is connected to the second voltage terminal, and the second terminal of which is connected to the second input node;

[0023] The third control circuit includes a first noise reduction transistor and a second noise reduction transistor. The gate of the first noise reduction transistor is connected to the second output node. The first terminal of the first noise reduction transistor is connected to the second voltage terminal. The second terminal of the first noise reduction transistor is connected to the first terminal of the second noise reduction transistor. The second terminal of the second noise reduction transistor is connected to the first input node. The gate of the second noise reduction transistor is connected to the third clock signal terminal.

[0024] In one exemplary embodiment of this disclosure, the first control transistor and the second control transistor are N-type transistors; at least one of the input transistor, the Zener transistor, the third control transistor, the first noise reduction transistor, the second noise reduction transistor, the output control transistor, and the output transistor is an N-type transistor.

[0025] In one exemplary embodiment of this disclosure, the voltage at the first voltage terminal is less than the voltage at the third voltage terminal.

[0026] In one exemplary embodiment of this disclosure, the maximum voltage of the third clock signal is less than the maximum voltage of the second clock signal, and the maximum voltage of the third clock signal is less than the voltage of the third voltage terminal.

[0027] According to one aspect of this disclosure, a gate drive circuit is provided, including a plurality of cascaded shift registers, wherein the shift registers are any of the shift registers described above.

[0028] According to one aspect of this disclosure, a display panel is provided, including a plurality of pixel circuits and a gate driving circuit, the pixel circuits being arrayed along row and column directions; the gate driving circuit includes a plurality of cascaded shift registers; an output terminal of one of the shift registers is connected to at least one row of the pixel circuits;

[0029] The shift register includes multiple transistors, including an input transistor, a first control transistor, a second control transistor, a third control transistor, a Zener transistor, an output control transistor, an output transistor, a first noise reduction transistor, a second noise reduction transistor, an input control capacitor, an output control capacitor, and an output capacitor.

[0030] The gate of the input transistor is connected to the first clock signal terminal, the first electrode is connected to the input terminal, and the second electrode is connected to the first input node;

[0031] The gate of the first control transistor is connected to the input terminal or the first input node, the first terminal is connected to the second voltage terminal, and the second terminal is connected to the control node; the gate of the second control transistor is connected to the control node, the first terminal is connected to the third voltage terminal, and the second terminal is connected to the second input node.

[0032] The gate of the third control transistor is connected to the first input node, the first terminal is connected to the second voltage terminal, and the second terminal is connected to the second input node;

[0033] The gate of the Zener transistor is connected to the first voltage terminal, the first terminal is connected to the first input node, and the second terminal is connected to the first output node;

[0034] The gate of the output control transistor is connected to the second output node, the first terminal is connected to the second voltage terminal, and the second terminal is connected to the output terminal; the second input node is connected to the second output node; the gate of the output transistor is connected to the first output node, the first terminal is connected to the second clock signal terminal, and the second terminal is connected to the output terminal.

[0035] The gate of the first noise reduction transistor is connected to the second output node, the first terminal of the first noise reduction transistor is connected to the second voltage terminal, the second terminal of the first noise reduction transistor is connected to the first terminal of the second noise reduction transistor, the second terminal of the second noise reduction transistor is connected to the first input node, and the gate of the second noise reduction transistor is connected to the third clock signal terminal.

[0036] The first plate of the input control capacitor is connected to the control node, and the second plate is connected to the first clock signal terminal; the first plate of the output control capacitor is connected to the gate of the output control transistor, and the second plate is connected to the output terminal; the first plate of the output capacitor is connected to the gate of the output transistor, and the second plate is connected to the output terminal.

[0037] The display panel includes:

[0038] Substrate;

[0039] An oxide semiconductor layer is disposed on one side of the substrate and includes the active portions of each of the transistors of the shift register;

[0040] One plate of the input control capacitor, one plate of the output control capacitor, and one plate of the output capacitor are arranged in the same layer.

[0041] In one exemplary embodiment of this disclosure, the display panel further includes a first clock signal line, a second clock signal line, a first voltage line, a second voltage line, and a third voltage line extending along the column direction;

[0042] The first clock signal line is connected to the first clock signal terminal, the second clock signal line is connected to the second clock signal terminal and the third clock signal terminal, the first voltage line is connected to the first voltage terminal, the second voltage line is connected to the second voltage line, and the third voltage line is connected to the third voltage terminal.

[0043] The second clock signal line, the first clock signal line, the first voltage line, the third voltage line, and the second voltage line are distributed sequentially at intervals along the row direction; each of the transistors in the shift register is located between the third voltage line and the second voltage line.

[0044] In one exemplary embodiment of this disclosure, the display panel further includes a first clock signal line, a second clock signal line, a third clock signal line, a first voltage line, a second voltage line, and a third voltage line extending along the column direction;

[0045] The first clock signal line is connected to the first clock signal terminal, the second clock signal line is connected to the second clock signal terminal, the third clock signal line is connected to the third clock signal terminal, the first voltage line is connected to the first voltage terminal, the second voltage line is connected to the second voltage line, and the third voltage line is connected to the third voltage terminal.

[0046] The second clock signal line, the first clock signal line, the first voltage line, the third voltage line, the third clock signal line, and the second voltage line are distributed sequentially at intervals along the row direction; each of the transistors in the shift register is located between the third voltage line and the second voltage line.

[0047] In one exemplary embodiment of this disclosure, the oxide semiconductor layer includes a first semiconductor portion, a second semiconductor portion, a third semiconductor portion, and at least a fourth semiconductor portion distributed along the row direction;

[0048] The first semiconductor section extends along the column direction, and the active portions of the input transistor and the Zener transistor are located in the first semiconductor section and distributed along the column direction;

[0049] The second semiconductor section includes a first semiconductor segment and a second semiconductor segment distributed along the column direction, and a connection segment connecting the first semiconductor segment and the second semiconductor segment; the active portions of the second control transistor and the third control transistor are located in the first semiconductor segment and distributed along the row direction; the active portion of the first control transistor is located in the second semiconductor segment;

[0050] The third semiconductor section extends along the column direction, and the active portions of the first noise reduction transistor and the second noise reduction transistor are located in the third semiconductor section and distributed along the column direction;

[0051] The output control transistor and the active portion of the output transistor are located in the fourth semiconductor section and are distributed along the column direction.

[0052] In one exemplary embodiment of this disclosure, the display panel further includes:

[0053] A first gate layer is disposed on one side of the substrate and includes the first electrode of the input control capacitor and the first electrode of the output capacitor;

[0054] The second gate layer is disposed on the side of the first gate layer away from the substrate, and includes the second electrode of the input control capacitor, the second electrode of the output capacitor, and the first electrode of the output control capacitor; the oxide semiconductor layer is disposed on the side of the second gate layer away from the substrate;

[0055] The third gate layer is disposed on the side of the oxide semiconductor layer away from the substrate, and includes the gate of each of the transistors of the shift register and the second plate of the output control capacitor;

[0056] The first source / drain layer is disposed on the side of the third gate layer away from the substrate, and includes the second clock signal line, the first clock signal line, the first voltage line, the third voltage line, and the second voltage line.

[0057] In one exemplary embodiment of this disclosure, the display panel further includes:

[0058] A first gate layer is disposed on one side of the substrate and includes the first electrode of the input control capacitor and the first electrode of the output capacitor;

[0059] The second gate layer is disposed on the side of the first gate layer away from the substrate, and includes the second electrode of the input control capacitor, the second electrode of the output capacitor, and the first electrode of the output control capacitor; the oxide semiconductor layer is disposed on the side of the second gate layer away from the substrate;

[0060] The third gate layer is disposed on the side of the oxide semiconductor layer away from the substrate, and includes the gate of each of the transistors of the shift register and the second plate of the output control capacitor;

[0061] The first source / drain layer is disposed on the side of the third gate layer away from the substrate, and includes the second clock signal line, the first clock signal line, the first voltage line, the third voltage line, and the second voltage line;

[0062] The second source / drain layer is disposed on the side of the first source / drain layer away from the substrate, and includes the third clock signal line.

[0063] In one exemplary embodiment of this disclosure, in a shift register, there are multiple output control transistors and output transistors; the gates of each output control transistor are connected, the first terminal of each output control transistor is connected to the second voltage terminal, and the second terminal of each output control transistor is connected to the output terminal; the gates of each output transistor are connected, the first terminal of each output transistor is connected to the first output node, and the second terminal of each output transistor is connected to the output terminal.

[0064] In one exemplary embodiment of this disclosure, the output control transistor includes a plurality of sub-control transistors connected in series, and the output transistor includes a plurality of sub-output transistors connected in series.

[0065] In one exemplary embodiment of this disclosure, the third clock signal line overlaps with the output capacitor.

[0066] In one exemplary embodiment of this disclosure, the display panel further includes:

[0067] A first gate layer is disposed on one side of the substrate;

[0068] The second gate layer is disposed on the side of the first gate layer away from the substrate; the oxide semiconductor layer is disposed on the side of the second gate layer away from the substrate;

[0069] A third gate layer is disposed on the side of the oxide semiconductor layer away from the substrate, and includes the gate of each of the transistors of the shift register and a plate of at least one of the output capacitor and the output control capacitor.

[0070] In one exemplary embodiment of this disclosure, the display panel further includes:

[0071] A first gate layer is disposed on one side of the substrate and includes the first electrode of the input control capacitor and the first electrode of the output capacitor;

[0072] The second gate layer is disposed on the side of the first gate layer away from the substrate, and includes the second electrode of the input control capacitor, the second electrode of the output capacitor, and the first electrode of the output control capacitor; the oxide semiconductor layer is disposed on the side of the second gate layer away from the substrate;

[0073] The third gate layer is disposed on the side of the oxide semiconductor layer away from the substrate, and includes the gate of each of the transistors of the shift register and the second plate of the output control capacitor;

[0074] The first source / drain layer is disposed on the side of the third gate layer away from the substrate;

[0075] The second source / drain layer is disposed on the side of the first source / drain layer away from the substrate, and includes at least two of the first voltage line, the third voltage line, the second voltage line, the first clock signal line, the second clock signal line, and the third clock signal line.

[0076] According to one aspect of this disclosure, a method for driving a shift register is provided, wherein the shift register is any of the shift registers described above; the driving method includes:

[0077] In the first stage, the input circuit and the output circuit are turned on; the output control circuit is turned off, and the third voltage terminal and the second input node are turned off through the first control circuit;

[0078] In the second stage, the output circuit is turned on; the input circuit and the output control circuit are turned off, and the third voltage terminal and the second input node are turned off through the first control circuit;

[0079] In the third stage, the input circuit and the output control circuit are turned on, and the third voltage terminal and the second input node are turned on through the first control circuit; the output circuit is turned off.

[0080] In the fourth stage, the output control circuit is turned on; the output circuit is turned off, and the third voltage terminal and the second input node are turned off through the first control circuit.

[0081] The display panel, gate driving circuit, shift register, and driving method disclosed herein, under the control of the voltages of the first clock signal, the second clock signal, the first voltage terminal, the second voltage terminal, and the third voltage terminal, control the output terminal to output a scanning signal through the output circuit and the output control circuit, so as to drive the pixel circuit.

[0082] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0083] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0084] Figure 1 is a top view schematic diagram of one embodiment of the display panel of this disclosure.

[0085] Figure 2 is a cross-sectional schematic diagram of one embodiment of the display panel of this disclosure.

[0086] Figure 3 is a schematic diagram of the pixel circuit of one embodiment of the display panel of this disclosure.

[0087] Figure 4 is a schematic diagram of a shift register of one embodiment of the display panel of this disclosure.

[0088] Figure 5 is a timing diagram of a shift register driving method according to one embodiment of the display panel of this disclosure.

[0089] Figures 6-9 are schematic diagrams of the shift register in Figure 4 from the first stage to the fourth stage.

[0090] Figure 10 is a schematic diagram of the shift register of a third embodiment of the display panel of this disclosure.

[0091] Figures 11-14 are schematic diagrams showing the bias voltage of each transistor in the shift register of one embodiment of the display panel of this disclosure.

[0092] Figure 15 is a schematic diagram of the output signal of the shift register of one embodiment of the display panel of this disclosure.

[0093] Figure 16 is a top view of the first gate layer to the first source / drain layer in one embodiment of the first type of implementation.

[0094] Figure 17 is a top view of the first gate layer to the third gate layer in the embodiment shown in Figure 16.

[0095] Figure 18 is a top view of the first gate layer to the oxide semiconductor layer in the embodiment of Figure 16.

[0096] Figure 19 is a top view of the first gate layer to the second gate layer in the embodiment shown in Figure 16.

[0097] Figures 20-24 are top views of some of the membrane layers in the embodiment shown in Figure 16.

[0098] Figure 25 is a top view of the first gate layer to the second source / drain layer in one embodiment of the second type of implementation.

[0099] Figure 26 is a top view of the first gate layer to the first source / drain layer in the embodiment of Figure 25.

[0100] Figure 27 is a top view of the first source / drain layer in the embodiment shown in Figure 25.

[0101] Figure 28 is a top view of the second source / drain layer in the embodiment shown in Figure 25.

[0102] Figure 29 is a top view of the first gate layer to the second source / drain layer in another embodiment of the second type of implementation.

[0103] Figure 30 is a top view of the first gate layer to the first source / drain layer in the embodiment shown in Figure 29. Detailed Implementation

[0104] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0105] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0106] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.

[0107] In this document, the row direction X and column direction Y are two intersecting directions, which can be perpendicular to each other or non-perpendicular intersecting directions. In the accompanying drawings of this disclosure, the row direction X is horizontal and the column direction Y is vertical, but this is not a limitation. Those skilled in the art will understand that if the display panel is rotated, the actual orientation of the row direction X and column direction Y may change.

[0108] In this article, nTmC represents a circuit (e.g., a pixel circuit, a gate drive circuit, etc.) consisting of n transistors (represented by the letter "T") and m capacitors (represented by the letter "C").

[0109] The transistor described in this article includes a gate, a first terminal, and a second terminal. The conduction and turn-off of the first and second terminals can be achieved by controlling the voltage of the gate. The first terminal can be the source, and the second terminal can be the drain; of course, the first terminal can also be the drain, and the second terminal can also be the source. Specifically, if the input signal is from the first terminal, then the first terminal is the source, and the second terminal is the drain; if the input signal is from the second terminal, then the second terminal is the source, and the first terminal is the drain. In other words, the source and drain can be interchanged depending on the change in the input signal.

[0110] For an N-type transistor, when the gate receives a high-level signal, both the first and second terminals are turned on; when the gate receives a low-level signal, both the first and second terminals are turned off. For a P-type transistor, when the gate receives a high-level signal, both the first and second terminals are turned off; when the gate receives a low-level signal, both the first and second terminals are turned on.

[0111] As shown in Figure 1, this disclosure provides a display panel that can be divided into multiple areas, including a display area AA and an outer peripheral area WA located outside the display area AA. The outer peripheral area WA can be a continuous annular area surrounding the display area AA, or it can be a discontinuous area surrounding the display area AA.

[0112] As shown in Figure 2, the display panel may include a driving backplate BP and multiple light-emitting devices LDs disposed on one side of the driving backplate BP. Each light-emitting device LD can be distributed in an array along the row direction X and the column direction Y and is located in the display area AA. The light-emitting devices LD can be driven to emit light through the circuit in the driving backplate BP to display images.

[0113] As shown in Figure 2, the light-emitting device LD can be an OLED (organic light-emitting diode) made of organic light-emitting materials; it can also be an LED (light-emitting diode) made of inorganic light-emitting materials, such as Micro LED (micron light-emitting diode) and Mini LED (sub-millimeter light-emitting diode); it can also be a QLED (quantum dot diode) and other devices. No specific restrictions are placed on the specific structure of the light-emitting device LD here.

[0114] As shown in Figure 2, taking an OLED as an example, the light-emitting device (LD) can include a first electrode (ANO), an emissive layer (EL), and a second electrode (CAT) stacked sequentially along a direction away from the driving backplane (BP). By applying a first power signal to the first electrode (ANO) and a second power signal to the second electrode (CAT), the emissive layer (EL) can be excited to emit light. The specific principle will not be detailed here. Meanwhile, to define the range of the LD, a pixel definition layer (PDL) can be provided on the driving backplane (BP). The PDL and the first electrode (ANO) are located on the same surface of the driving backplane (BP), and the PDL can have pixel openings exposing each of the first electrodes (ANO), thereby defining the range of the LD through each pixel opening.

[0115] The circuit driving the backplane (BP) may include pixel circuits (PC) and driving circuits. The pixel circuits (PC) may be located in the display area (AA) and distributed in an array along the row direction (X) and column direction (Y). One pixel circuit (PC) may be connected to the first electrode (ANO) of a light-emitting device (LD). Of course, the same pixel circuit (PC) may also be connected to the first electrodes (ANO) of multiple light-emitting devices (LDs). The pixel circuit (PC) may include multiple transistors and may also include capacitors, such as 3T1C or 7T1C pixel circuits.

[0116] As shown in Figure 3, taking the pixel circuit PC with a 7T1C structure as an example, it may include a first reset transistor M1, a compensation transistor M2, a driving transistor M3, a writing transistor M4, a first light-emitting control transistor M5, a second light-emitting control transistor M6, a second reset transistor M7, and a storage capacitor Cst. A scan signal applied to the gate of the transistors can turn their first and second electrodes on or off. The storage capacitor Cst may include overlapping first and second plates; wherein:

[0117] As shown in Figure 3, the gate of the first light-emitting control transistor M5 is used to input the light-emitting scan signal EM, its first electrode is used to input the first power supply signal VDD, and its second electrode is connected to the first electrode of the driving transistor M3. The gate of the driving transistor M3 is connected to the first node N1, and its second electrode is connected to the first electrode of the second light-emitting control transistor M6 at the second node N2. The second electrode of the second light-emitting control transistor M6 is connected to the first electrode ANO of a light-emitting device LD at the fourth node N41. The gate of the second light-emitting control transistor M6 is used to input the light-emitting scan signal EM. The second electrode CAT of the light-emitting device LD is used to input the second power supply signal VSS.

[0118] The gate of the first reset transistor M1 is used to input the first reset scan signal RE1, the first terminal is used to input the first reset signal VI1, and the second terminal is connected to the gate of the drive transistor M3.

[0119] The gate of the write transistor M4 is used to input the write scan signal Gate1, the first terminal is used to input the data signal DA, and the second terminal is connected to the third node N31 along with the first terminal of the drive transistor M3 and the second terminal of the first light-emitting control transistor M5.

[0120] The gate of the compensation transistor M2 is used to input the compensation scan signal Gate2. The first terminal is connected to the second node N2, and the second terminal is connected to the first node N1, thereby connecting the second terminal and the gate of the driving transistor M3.

[0121] The gate of the second reset transistor M7 is used to input the second reset scan signal RE2, the first terminal is used to input the second reset signal VI2, and the second terminal is connected to the fourth node N41, that is, connected to the first electrode ANO of the light-emitting device and the second terminal of the driving transistor M3.

[0122] The first plate of the storage capacitor Cst is used to input the first power supply signal VDD, and the second plate is connected to the first node N1, thereby connecting to the gate of the driving transistor M3.

[0123] The specific working principle of the 7T1C pixel circuit will not be detailed here.

[0124] The aforementioned 7T1C pixel circuit can employ metal-oxide-semiconductor (MODS) transistors in at least a portion of its transistors. For example, it can utilize LTPO (Low Temperature Polycrystalline Oxide) technology, where the first reset transistor M1 and compensation transistor M2 are MODS, while the other transistors are polycrystalline silicon (PCS) transistors. Using MODS transistors can reduce leakage current. Furthermore, if MODS transistors are used, they are N-type transistors, and the active part material can be IGZO (Indium Gallium Zinc Oxide), etc.; if PCS transistors are used, they can be P-type transistors, and the active part material can be polycrystalline silicon.

[0125] Of course, all transistors in the pixel circuit can be polycrystalline silicon transistors, i.e., using LTPS (Low Temperature Polycrystalline Silicon) technology. This article will use the aforementioned LTPO technology as an example for explanation.

[0126] As shown in Figure 3, the driving circuit WG can be located in the peripheral area WA. Taking the aforementioned 7T1C pixel circuit as an example, the driving circuit WG can be divided into two categories. One category is a gate driving circuit, which is used to scan some transistors in the pixel circuit PC (e.g., the first reset transistor M1, the second reset transistor M7, the compensation transistor M2, and the write transistor M4). That is, it outputs the first reset scan signal RE1, the second reset scan signal RE2, the compensation scan signal Gate2, and the write scan signal Gate1 to the gates of the first reset transistor M1, the second reset transistor M7, the compensation transistor M2, and the write transistor M4. The other category is a light-emitting driving circuit, which can be used to scan the first light-emitting control transistor M5 and the second light-emitting control transistor M6. That is, it outputs scan signals (light-emitting scan signals EM) to the gates of the first light-emitting control transistor M5 and the second light-emitting control transistor M6. The first reset scan signal RE1, the second reset scan signal RE2, the compensation scan signal Gate2, the write scan signal Gate1, and the light-emitting scan signal EM are all scan signals output by the driving circuit WG. The signals output by the gate drive circuit and the light-emitting drive circuit described above can realize the conduction and shutdown of the transistors in the pixel circuit PC, that is, realize the scanning of the pixel circuit PC, thereby controlling the light-emitting device LD to emit light.

[0127] The peripheral area WA of the display panel may also be provided with a power bus connected to the second electrode CAT of the light-emitting device LD. A second power signal is applied to the second electrode CAT, and the current through the light-emitting device LD can be controlled by the pixel circuit PC, thereby controlling the brightness of the light-emitting device LD.

[0128] The driving circuit WG may include multiple cascaded shift registers GOA. Specifically, the output terminal OUT of the nth-stage shift register GOA is connected to the gate of the transistor in at least one row of pixel circuits PC, and also to the input terminal of the (n+1)th-stage shift register GOA, so that the output signal of the previous-stage shift register GOA serves as the input signal of the next-stage shift register GOA. Simultaneously, the input signal of the first-stage shift register GOA can be a trigger signal. Each shift register GOA may include multiple transistors and capacitors, and its structure can be 8T2C, 10T3C, etc., without special limitations.

[0129] As shown in Figure 1, the output signal of the shift register GOA is the scanning signal mentioned above. The gate of some transistors in a row of pixel circuit PC can be connected to the output of the first-level shift register GOA. Of course, the first-level shift register GOA can be connected to multiple rows of pixel circuit PC and scan multiple rows of pixel circuit PC at the same time. However, the output signal of the same shift register GOA can have different functions in different rows of pixel circuit PC. For example, when the i-th row of pixel circuit PC is in the writing stage, the (i+1)-th row of pixel circuit PC is in the first reset stage, where i is a positive integer.

[0130] The following explanation uses a shift register (GOA) of a gate drive circuit as an example:

[0131] As shown in Figures 4 and 10, the shift register includes an input circuit 10, a first control circuit 20, an output control circuit 60, and an output circuit 70, wherein:

[0132] Input circuit 10 is connected to the input terminal, the first clock signal terminal, and the first input node N2, and is configured to transmit the input signal provided by the input terminal to the first input node N2 in response to the first clock signal CK provided by the first clock signal terminal. The first output node N4 is connected to the first input node N2. In a gate drive circuit, the input terminal of the first-stage shift register can be used to receive the trigger signal STV, and the input terminal of the (n+1)th-stage shift register can be connected to the output terminal OUT of the nth-stage shift register.

[0133] The first control circuit 20 is connected to the input terminal or the first input node N2, and is also connected to the second voltage terminal, the third voltage terminal, and the second input node N1. The first control circuit 20 is configured to control the voltage of the second input node N1 under the control of one of the input signal and the signal of the first input node N2, the voltage of the second voltage terminal, and the voltage of the third voltage terminal.

[0134] The second input node N1 is connected to the second output node N6, and the second input node N1 and the second output node N6 are always connected, so that their voltages are the same (the voltage drop caused by the impedance of the trace can still be regarded as the same).

[0135] The output control circuit 60 is connected to the second output node N6, the second voltage terminal and the output terminal OUT, and is configured to turn on or off the second voltage terminal and the output terminal OUT under the control of the voltage of the second output node N6, so that the output terminal OUT outputs the second voltage VGL.

[0136] The output circuit 70 is connected to the first output node N4, the second clock signal terminal and the output terminal OUT, and is configured to turn on or off the second clock signal terminal and the output terminal OUT under the control of the voltage of the first output node N4, so that the output terminal OUT can output the second clock signal CB1, and the second clock signal terminal is used to provide the second clock signal CB1.

[0137] Furthermore, the shift register may also include a second control circuit 30, a third control circuit 40, and a voltage regulator circuit 50, wherein:

[0138] The voltage regulator circuit 50 is connected to the first voltage terminal, the first output node N4 and the first input node N2, that is, the first output node N4 and the first input node N2 are connected through the voltage regulator circuit 50; and the voltage regulator circuit 50 is configured to turn on or off the first output node N4 and the first input node N2 under the control of the voltage at the first voltage terminal, and when the voltage regulator circuit 50 is turned on, it can stabilize the voltage of the first output node N4.

[0139] The second control circuit 30 is connected to the second voltage terminal and the second input node N1, and is also connected to the first input node N2. The second control circuit 30 is configured to transmit the signal provided by the second voltage terminal to the second input node N1 under the control of the voltage of the first input node N2, that is, to transmit the second voltage VGL to the second input node N1 and the second output node N6, so as to stabilize the voltage of the second output node N6. That is, the voltage of the second output node N6 can be made consistent with the voltage of the second voltage terminal. The voltage of the second voltage terminal can keep the output control circuit 60 off to prevent the output terminal OUT from being output incorrectly.

[0140] The third control circuit 40 is connected to the third clock signal terminal, the first input node N2, the second input node N1, and the second voltage terminal. It is configured to control the voltage of the first input node N2 under the control of the third clock signal CB2 provided by the third clock signal terminal and the signal of the second input node N1. When the third control circuit 40 is turned on, it can make the voltage of the first output node N4 consistent with the voltage of the second voltage terminal. The voltage of the second voltage terminal can keep the output circuit 70 off to prevent the output terminal OUT from being output incorrectly.

[0141] The voltage at the first voltage terminal is the first voltage VGH-L, the voltage at the second voltage terminal is the second voltage VGL, and the voltage at the third voltage terminal is the third voltage VGH. The first voltage VGH-L, the second voltage VGL, and the third voltage VGH are all constant voltage signals. The third voltage VGH and the first voltage VGH-L are both high-level signals greater than the second voltage VGL, while the second voltage VGL is a low-level signal. The low-level voltage (minimum voltage) of the first clock signal CK, the second clock signal CB1, and the third clock signal CB2 can be the same as the second voltage VGL, and the high-level voltage (maximum voltage) can be the same as the third voltage VGH. However, at least two of the first clock signals CK, the second clock signal CB1, and the third clock signal CB2 can have different minimum voltages and different maximum voltages.

[0142] The voltage of the first output node can be stabilized by the voltage regulator circuit 50, and the voltage of the second output node can be made consistent with the voltage of the second voltage terminal by the second control circuit. The voltage of the first input node can be made consistent with the voltage of the second voltage terminal by the third control circuit, which helps to improve the stability of the output signal and thus prevents erroneous output during non-display periods, avoiding affecting the display effect.

[0143] As shown in Figure 4, in some embodiments of this disclosure, the input circuit 10 includes an input transistor T1, the gate of which is connected to a first clock signal terminal, the first terminal is connected to the input terminal, and the second terminal is connected to the first input node N2.

[0144] The control energy storage circuit 80 includes an input control capacitor C1, which is connected to the control node N3 and the first clock signal terminal. For example, the first plate of the input control capacitor C1 is connected to the control node N3, thereby connecting to the second terminal of the first control transistor T2 and the gate of the second control transistor T3. The second plate of the input control capacitor C1 is connected to the first clock signal terminal.

[0145] The first control circuit 20 includes a first control transistor T2, a second control transistor T3, and a control energy storage circuit 80. The gate of the first control transistor T2 is connected to its input terminal or the first input node N2. The first terminal of the first control transistor T2 is connected to the second voltage terminal, and the second terminal is connected to the control node N3. The gate of the second control transistor T3 is connected to the control node N3. The first terminal is connected to the third voltage terminal, and the second terminal is connected to the second input node N1. The control energy storage circuit 80 is connected to the control node N3 and the first clock signal terminal. The first control transistor T2 and the second control transistor T3 are N-type transistors, such as N-type metal-oxide-semiconductor transistors.

[0146] The second control circuit 30 includes a third control transistor T4. The gate of the third control transistor T4 is connected to the first input node N2, the first terminal is connected to the second voltage terminal, and the second terminal is connected to the second input node N1. The second control circuit 30 is configured to turn on or off under the control of the voltage of the first input node N2. When on, it can transmit the second voltage of the second voltage terminal to the second input node N1 and then to the second output node N6 to stabilize the voltage of the second output node N6. That is, it can make the voltage of the second output node N6 the second voltage, so that the third control transistor T4 remains off, preventing the output terminal OUT from being output incorrectly.

[0147] The third control circuit 40 includes a first noise-reducing transistor T8 and a second noise-reducing transistor T9. The gate of the first noise-reducing transistor T8 is connected to the second input node N1, the first terminal of the first noise-reducing transistor T8 is connected to the second voltage terminal, the second terminal of the first noise-reducing transistor T8 and the first terminal of the second noise-reducing transistor T9 are connected to node N5, the second terminal of the second noise-reducing transistor T9 is connected to the first input node N2, and the gate of the second noise-reducing transistor T9 is connected to the third clock signal terminal. The first noise-reducing transistor T8 can be turned on or off under the control of the voltage of the second input node N1, and the second noise-reducing transistor T9 can be turned on or off under the control of the third clock signal. When both are turned on simultaneously, the third control circuit 40 is considered to be on, making the voltage of the first input node N2 the second voltage. When at least one of the first noise-reducing transistor T8 and the second noise-reducing transistor T9 is turned off, the third control circuit 40 is considered to be off.

[0148] The voltage regulator circuit 50 includes a Zener transistor T5. The gate of Zener transistor T5 is connected to a first voltage terminal, the first terminal is connected to the first input node N2, and the second terminal is connected to the first output node N4. The first voltage VGH-L keeps Zener transistor T5 continuously conducting, ensuring that the first input node N2 and the first output node N4 are always on. Zener transistor T5 prevents leakage at the first output node N4 through the input transistor T1 and the second noise reduction transistor T9, reducing the stress of the first output node N4 on the first input node N2. This helps to make the voltage at the first output node N4 more stable and less prone to fluctuation, allowing the output transistor T7 of the output circuit 70 to conduct fully.

[0149] The output control circuit 60 includes an output control transistor T6 and an output control capacitor C2. The gate of the output control transistor T6 is connected to the second output node N6, the first terminal is connected to the second voltage terminal, and the second terminal is connected to the output terminal OUT. The output control capacitor C2 is connected to the gate and the second terminal of the output control transistor T6.

[0150] The output circuit 70 includes an output transistor T7 and an output capacitor C3. The gate of the output transistor T7 is connected to the first output node N4, the first terminal is connected to the second clock signal terminal, and the second terminal is connected to the output terminal OUT. The output capacitor C3 is connected to the gate and the second terminal of the output transistor T7.

[0151] The input transistor T1, Zener transistor T5, third control transistor T4, first noise reduction transistor T8, second noise reduction transistor T9, output control transistor T6, and output transistor T7 are N-type transistors, such as N-type metal-oxide transistors.

[0152] The following explains the driving method of the shift register based on its working principle:

[0153] The driving methods for shift registers include:

[0154] As shown in Figures 5 and 6, in the first stage t1, the first clock signal CK is at a high level, the second clock signal CB1 is at a low level, and the third clock signal CB2 and the second clock signal CB1 can be the same clock signal or two independent and synchronous clock signals. When the third clock signal CB2 and the second clock signal CB1 are independent signals, their maximum voltages (the voltage at the high level) can be the same or different.

[0155] For example, in the first stage t1, input transistor T1 turns on in response to a high-level first clock signal CK, transmitting the high-level input signal received at the input terminal to the first input node N2; the first voltage VGH-L turns on Zener transistor T5, thereby transmitting the signal from the first input node N2 to the first output node N4 and storing it in output capacitor C3, and turning on output transistor T7; the low-level second clock signal CB1 is output from the output terminal OUT through output transistor T7. Simultaneously, the first control transistor T2 and the third control transistor T4 turn on, the voltages of the second input node N1, control node N3, and second output node N6 are low, causing the second control transistor T3 and the first noise reduction transistor T8 to turn off, and the third clock signal CB2 turns off the second noise reduction transistor T9.

[0156] As shown in Figures 5 and 7, in the second stage t2, the first clock signal CK is low, while the second clock signal CB1 and the third clock signal CB2 are high. The second control circuit 30, the voltage regulator circuit 50, and the output circuit 70 are turned on; the input circuit 10, the output control circuit 60, the second control transistor T3, and the third control circuit 40 are turned off. At this time, the output terminal OUT outputs the second clock signal CB1, i.e., a high level.

[0157] For example, in the second stage t2, the first clock signal CK is low, the input transistor T1 is off, the first voltage VGH-L keeps the Zener transistor T5 on, and under the action of the output capacitor C3, the voltages of the first input node N2 and the first output node N4 are high, i.e., the third voltage VGH, and the output transistor T7 remains on. The second clock signal CB1 is high and is output from the output terminal OUT through the output transistor T7. At the same time, the voltages of the second input node N1, the control node N3, and the second output node N6 are low, the first control transistor T2 and the third control transistor T4 are on, the second control transistor T3 and the first noise reduction transistor T8 remain off, and the third clock signal CB2 turns on the second noise reduction transistor T9.

[0158] As shown in Figures 5 and 8, in the third stage t3, the first clock signal CK is high, and the second clock signal CB1 and the third clock signal CB2 are low. Input circuit 10, the second control transistor T3, the voltage regulator circuit 50, and the output control circuit 60 are turned on; the first control transistor T2, the second control circuit 30, the third control circuit 40, and the output circuit 70 are turned off. At this time, the output terminal OUT outputs the second voltage VGL, i.e., a low level.

[0159] For example, in the third stage t3, the first clock signal CK is high, the input transistor T1 is turned on, and the low-level input signal received at the input terminal is transmitted to the first input node N2; the first voltage VGH-L keeps the Zener transistor T5 on, thereby transmitting the signal from the first input node N2 to the first output node N4 and storing it in the output capacitor C3, and turning off the output transistor T7. At the same time, the first control transistor T2 and the third control transistor T4 are turned off, the control node N3 is high, and the second control transistor T3 is turned on; the third voltage VGH is written to the second input node N1 and the second output node N6 and stored in the output control capacitor C2, turning on the first noise reduction transistor T8 and the output control transistor T6, and the third clock signal CB2 is low, turning off the second noise reduction transistor T9, and the output terminal OUT outputs the second voltage VGL.

[0160] As shown in Figures 5 and 9, in the fourth stage t4, the first clock signal CK is low, while the second clock signal CB1 and the third clock signal CB2 are high. The third control circuit 40, the voltage regulator circuit 50, and the output control circuit 60 are turned on; the first control transistor T2, the second control transistor T3, the second control circuit 30, and the output circuit 70 are turned off. At this time, the output terminal OUT outputs the second voltage VGL, i.e., a low level.

[0161] For example, in the fourth stage t4, the first clock signal CK is low and the second clock signal CB1 is high; input transistor T1 is off, second control transistor T3 is off, the first voltage VGH-L keeps Zener transistor T5 on, and under the action of output capacitor C3, the voltages of the first input node N2 and the first output node N4 are low, i.e., the second voltage VGL. The first control transistor T2, the third control transistor T4, and the output transistor T7 remain off. Since the first clock signal CK is low, under the coupling effect of input control capacitor C1, the voltage of control node N3 jumps to low. At the same time, under the action of output control capacitor C2, the voltages of the second input node N1 and the second output node N6 are maintained at the third voltage VGH, keeping output control transistor T6 on, the first noise reduction transistor T8 on, and the third clock signal CB2 is high, making the second noise reduction transistor T9 on, thereby making the voltages of the first input node N2 and the first output node N4 low and stable at the second voltage VGL. The output terminal OUT maintains the second output voltage VGL.

[0162] It should be noted that although the steps of the driving method in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or a step may be broken down into multiple steps.

[0163] Based on the above shift register and its driving method, the inventors tested the bias voltage of each transistor in the shift register of this disclosure through experiments. The specific structure is shown in Figures 11-14. In the figure, the horizontal axis Vgs is the gate-source voltage of each transistor, and the vertical axis Vds is the source-drain voltage. PB indicates forward bias and is used to analyze PBTS (positive bias temperature instability). NB indicates negative bias and is used to analyze NBTIS.

[0164] Figure 15 shows the output signal of the shift register OUT when the threshold voltage of the second control transistor T3 deviates to different degrees. It can be seen that the deviation of the threshold voltage of the second control transistor T3 has no significant effect on the output signal of the shift register. Therefore, it has high resistance to bias temperature stability, especially high resistance to NBTIS.

[0165] In some embodiments of this disclosure, the first voltage VGH-L can be made less than the third voltage VGH, provided that the Zener transistor T5 can be turned on. For example, the third voltage VGH = 14V and the first voltage VGH-L = 10V. Since the Zener transistor T5 is in a forward bias state for a long time, making the first voltage VGH-L less than the third voltage VGH is beneficial to improving the resistance to PBTS and reducing power consumption.

[0166] In some embodiments of this disclosure, provided that the second noise reduction transistor T9 can be turned on, the maximum voltage of the second clock signal CB1, i.e., the voltage at the high level of the second clock signal CB1, can be the same as the third voltage VGH, and the maximum voltage of the third clock signal CB2, i.e., the voltage at the high level of the third clock signal CB2, is less than the third voltage VGH. In other words, the voltage applied to the gate of the second noise reduction transistor T9 is less than the voltage applied to the gates of some other transistors in the shift register (e.g., the second control transistor T3, the output transistor T7, etc.). For example, the maximum voltage of the third clock signal CB2 can be 10V, and the maximum voltage of the second clock signal CB1 can be 14V. Because the second noise reduction transistor T9 is in a positive bias state for a long time, the maximum voltage of the third clock signal CB2 is less than the third voltage VGH, which is beneficial for improving the anti-PBTS capability and maintaining the turn-on performance of the second noise reduction transistor T9, optimizing the noise reduction function of the third control circuit 40, and reducing power consumption.

[0167] As shown in Figures 16 and 24, in the first type of embodiment of this disclosure, the display panel may further include multiple signal lines, including a first clock signal line CKL, a second clock signal line CBL1, a first voltage line VHL1, a second voltage line VLL, and a third voltage line VHL2.

[0168] The first clock signal line CKL is connected to the first clock signal terminal and is used to transmit the first clock signal CK. The second clock signal line CBL1 is connected to both the second and third clock signal terminals and is used to transmit the second clock signal CB1. The second clock signal CB1 and the third clock signal CB2 can be the same clock signal. The first voltage line VHL1 is connected to the first voltage terminal and is used to transmit the first voltage VGH-L. The second voltage line VLL is connected to the second voltage terminal and is used to transmit the second voltage VGL. The third voltage line VHL2 is connected to the third voltage terminal and is used to transmit the third voltage VGH.

[0169] As shown in Figures 25 and 27, in the second type of embodiment of this disclosure, the display panel may include multiple signal lines, including a first clock signal line CKL, a second clock signal line CBL1, a third clock signal line CBL2, a first voltage line VHL1, a second voltage line VLL, and a third voltage line VHL2, wherein:

[0170] The first clock signal line CKL is connected to the first clock signal terminal and is used to transmit the first clock signal CK. The second clock signal line CBL1 is connected to the second clock signal terminal and is used to transmit the second clock signal CB1. The third clock signal line CBL2 is connected to the third clock signal terminal and is used to transmit the third clock signal CB2. The maximum voltage of the third clock signal CB2 can be less than the maximum voltage of the second clock signal CB1. The first voltage line VHL1 is connected to the first voltage terminal and is used to transmit the first voltage VGH-L. The second voltage line VLL is connected to the second voltage terminal and is used to transmit the second voltage VGL. The third voltage line VHL2 is connected to the third voltage terminal and is used to transmit the third voltage VGH.

[0171] Of course, in other embodiments of this disclosure, the second clock signal CB1 and the third clock signal CB2 may be the same signal, but the second clock signal line CBL can still be connected to the second clock signal terminal, and the third clock signal line CBL2 can be connected to the third clock signal terminal.

[0172] The following example, using the aforementioned shift register and pixel circuit employing LTPO, provides an exemplary description of the film layer driving the backplane BP:

[0173] As shown in Figure 2, the driving backplane BP may include a substrate SU and, in a direction away from the substrate SU, a light-shielding layer BSM, a polysilicon semiconductor layer SE, a first gate layer GA1, a second gate layer GA2, an oxide semiconductor layer IG, a third gate layer GA3, and a first source / drain layer SD1, wherein:

[0174] The light-shielding layer BSM is disposed on one side of the substrate SU, and its material can be metal or other conductive and light-shielding materials. The light-shielding layer BSM can overlap with the driving transistor M3 at least to avoid the influence of bottom signals and light on the driving transistor M3.

[0175] The polycrystalline silicon semiconductor layer SE is disposed on the side of the light-shielding layer BSM away from the substrate SU, and the polycrystalline silicon semiconductor layer SE can be fabricated using a low-temperature polycrystalline silicon process. It may include the active portions of other transistors in the pixel circuit, except for the first reset transistor M1 and the compensation transistor M2.

[0176] The first gate layer GA1 is disposed on the side of the polysilicon semiconductor layer SE away from the substrate SU. The first gate layer GA1 may include the first plate of the input control capacitor C1 and the first plate of the output capacitor C3 in the shift register GOA, and may also include the first plate of the storage capacitor Cst of the pixel circuit.

[0177] The second gate layer GA2 is located on the side of the first gate layer GA1 away from the substrate SU, and includes the second plate C12 of the input control capacitor C1 of the shift register GOA, the second plate C32 of the output capacitor C3, and the first plate C21 of the output control capacitor C2. It may also include the second plate of the storage capacitor Cst of the pixel circuit.

[0178] The oxide semiconductor layer IG can be disposed on the side of the second gate layer GA2 away from the substrate SU. Its material can be metal oxide such as IGZO (indium gallium zinc oxide). The oxide semiconductor layer IG can include the active parts of the first reset transistor M1 and the compensation transistor M2 of the pixel circuit PC, and also includes the active parts of each transistor of the shift register GOA.

[0179] The third gate layer GA3 may be disposed on the side of the oxide semiconductor layer IG away from the substrate SU, and may overlap with the oxide semiconductor layer IG. The third gate layer GA3 may include the gates of each transistor of the shift register GOA and the second plate C22 of the output control capacitor C2.

[0180] The first source / drain layer SD1 can be disposed on the side of the third gate layer GA3 away from the substrate SU, and can connect some transistors and capacitors. The first source / drain layer SD1 may include a second clock signal line CBL, a first clock signal line CKL, a first voltage line VHL1, a third voltage line VHL2, and a second voltage line VLL.

[0181] In addition, the first source-drain layer SD1 may also include a trigger signal line STL, which may be located on the side of the second clock signal line CBL1 away from the first clock signal line CKL, that is, outside the second clock signal line CBL1, for transmitting the trigger signal STV.

[0182] In some embodiments of this disclosure, the second clock signal line CBL1, the first clock signal line CKL, the first voltage line VHL1, the third voltage line VHL2, and the second voltage line VLL all extend along the column direction Y and are distributed sequentially at intervals along the row direction X. The transistors of the shift register are located between the third voltage line VHL2 and the second voltage line VLL.

[0183] Furthermore, in some embodiments of this disclosure, the display panel may further include a second source / drain layer SD2, which may be disposed on the side of the first source / drain layer SD1 away from the substrate SU, and the second source / drain layer SD2 may include a third clock signal line CBL2 extending along the column direction Y, the orthographic projection of which on the substrate SU may be located between the orthographic projections of the third voltage line VHL2 and the second voltage line VLL on the substrate SU; and the third clock signal line CBL2 may overlap with the output capacitor C3.

[0184] The patterns of the aforementioned film layers are explained below in conjunction with shift registers:

[0185] As shown in Figures 16-20, the first gate layer GA1 may include a first electrode C11 of the control capacitor C1, a first electrode C31 of the output capacitor C3, and a first transition portion GA11. The first electrode C11, the first electrode C31, and the first transition portion GA11 are spaced apart.

[0186] The second gate layer GA2 may include a second electrode C12 of the control capacitor C1, a second electrode C32 of the output capacitor C3, a first electrode C21 of the output control capacitor C2, and a second transition portion GA21. The second electrode C12 overlaps with the first electrode C11 to form the control capacitor C1; the first electrode C31 overlaps with the second electrode C32 to form the output capacitor C3.

[0187] As shown in Figures 16-18 and 22, the oxide semiconductor layer IG may include a first semiconductor portion IG1, a second semiconductor portion IG2, a third semiconductor portion IG3, and at least one fourth semiconductor portion IG4, which are spaced apart along the row direction X, wherein:

[0188] The first semiconductor section IG1 extends along the column direction Y, and the active parts of the input transistor T1 and the Zener transistor T5 are located in the first semiconductor section IG1 and distributed along the column direction Y.

[0189] The second semiconductor section IG2 includes a first semiconductor segment IG21 and a second semiconductor segment IG22 distributed along the column direction Y, and a connecting segment IG23 connecting the first semiconductor segment IG21 and the second semiconductor segment IG22. The first semiconductor segment IG21 and the second semiconductor segment IG22 can extend along the row direction X, and the connecting segment IG23 can extend along the column direction Y. The active parts of the second control transistor T3 and the third control transistor T4 are located in the first semiconductor segment IG21 and are distributed along the row direction X; the active part of the first control transistor T2 is located in the second semiconductor segment IG22.

[0190] The third semiconductor section IG3 extends along the column direction Y, and the active parts of the first noise reduction transistor T8 and the second noise reduction transistor T9 are located in the third semiconductor section IG3 and are distributed along the column direction Y.

[0191] The active portions of the output control transistor T6 and the output transistor T7 are located in the fourth semiconductor section IG4 and extend along the column direction Y.

[0192] In some embodiments of this disclosure, in a shift register GOA, there are multiple output control transistors T6 and T7. The gates of each output control transistor T6 are connected together, the first terminal of each output control transistor T6 is connected to a second voltage terminal, and the second terminal of each output control transistor T6 is connected to the output terminal OUT, i.e., the output control transistors T6 are connected in parallel. Simultaneously, the gates of each output transistor T7 are connected together, the first terminal of each output transistor T7 is connected to a first output node N4, and the second terminal of each output transistor T7 is connected to the output terminal OUT, i.e., the output transistors T7 are connected in parallel. Further, in some embodiments, one output transistor T7 includes multiple sub-output transistors connected in parallel, i.e., the first terminals of each sub-output transistor are connected together, the second terminals of each sub-output transistor are connected together, and the gates of each sub-output transistor are connected together.

[0193] Of course, the parallel output control transistor T6 can also be regarded as a single transistor, and the parallel output transistor T7 can also be regarded as a single transistor.

[0194] Correspondingly, the number of fourth semiconductor units IG4 can be multiple, such as four, and no special limit is made on the number here; each fourth semiconductor unit IG4 is distributed at intervals along the row direction X.

[0195] As shown in Figures 16-17 and 23, the third gate layer GA3 may include a first gate portion GA31, a second gate portion GA32, a third gate portion GA33, a fourth gate portion GA34, a fifth gate portion GA35, a sixth gate portion GA36, a seventh gate portion GA37, an eighth gate portion GA38, and a second electrode plate C22, wherein:

[0196] The first gate portion GA31 extends along the row direction X and overlaps with the first semiconductor portion IG1. The portion of the first gate portion GA31 that overlaps with the first semiconductor portion IG1 serves as the gate of the input transistor T1. The first gate portion GA31 overlaps with the first clock signal line CKL and is connected through a contact hole to transmit the first clock signal CK.

[0197] The second gate portion GA32 extends along the row direction X and overlaps with the first semiconductor portion IG1. The portion of the second gate portion GA32 that overlaps with the first semiconductor portion IG1 serves as the gate of the Zener transistor T5. The second gate portion GA32 overlaps with the first voltage line VHL1 and is connected through a contact hole to transmit the first voltage VGH-L.

[0198] The third gate portion GA33 and the fourth gate portion GA34 extend along the column direction Y and are distributed along the row direction X between the first semiconductor portion IG1 and the third semiconductor portion IG3. The third gate portion GA33 overlaps with the first semiconductor segment IG21, and the portion of the third gate portion GA33 that overlaps with the first semiconductor segment IG21 serves as the gate of the second control transistor T3. The fourth gate portion GA34 overlaps with the first semiconductor segment IG21, and the portion of the fourth gate portion GA34 that overlaps with the first semiconductor segment IG21 serves as the gate of the third control transistor T4. At the same time, the fourth gate portion GA34 overlaps with the second semiconductor segment IG22, and the portion of the fourth gate portion GA34 that overlaps with the second semiconductor segment IG22 serves as the gate of the first control transistor T2. The connecting segment IG23 is located on the side of the fourth gate portion GA34 away from the third gate portion GA33.

[0199] The fifth gate portion GA35 extends along the row direction X and overlaps with the third semiconductor portion IG3. The portion of the fifth gate portion GA35 that overlaps with the third semiconductor portion IG3 serves as the gate of the first noise reduction transistor T8. Simultaneously, the fifth gate portion GA35 overlaps with the fourth semiconductor portion IG4, and the portion of the fifth gate portion GA35 that overlaps with the fourth semiconductor portion IG4 serves as the gate of the output control transistor T6. Furthermore, the second electrode C22 overlaps with the first electrode C21 to form the output control capacitor C2. The second electrode C22 and the fifth gate portion GA35 are an integral structure, thereby connecting to the gate of the output control transistor T6.

[0200] The sixth gate portion GA36 extends along the row direction X and overlaps with the third semiconductor portion IG3. The portion of the sixth gate portion GA36 that overlaps with the third semiconductor portion IG3 serves as the gate of the second noise reduction transistor T9. The sixth gate portion GA36 does not overlap with the second semiconductor portion IG2.

[0201] The seventh gate portion GA37 overlaps with the fourth semiconductor portion IG4, and the portion of the seventh gate portion GA37 that overlaps with the fourth semiconductor portion IG4 serves as the gate of the output transistor T7. For example, the seventh gate portion GA37 includes a capacitor portion GA371 and a gate portion GA372, wherein:

[0202] The gate portion GA372 and the capacitor portion GA371 can be an integral structure, and the gate portion GA372 is located between the capacitor portion GA371 and the second plate C22. The gate portion GA372 overlaps with the fourth semiconductor portion IG4, and the portion of the gate portion GA372 that overlaps with the fourth semiconductor portion IG4 serves as the gate of the output transistor T7. The gate portion GA372 may include a plurality of sub-gates spaced along the column direction Y, and each sub-gate overlaps with the fourth semiconductor portion IG4 to form a plurality of sub-output transistors.

[0203] The capacitor section GA371 can be connected to the first plate 31 of the output capacitor C3, thereby connecting the gate of the output transistor T7 to the first plate 31. Simultaneously, the capacitor section GA371 overlaps with the output capacitor C3, allowing GA371 to function as one plate of the output capacitor C3. This increases the capacitance value (i.e., the charge storage capacity of the output capacitor C3) by increasing the number of overlapping plates without increasing the plate area. This helps save wiring space, reduce the width of the peripheral area W, narrow the bezel of the display panel, and increase the screen-to-body ratio.

[0204] The eighth gate section GA38 is connected to the second clock signal line CBL1 to transmit the second clock signal CB1. The eighth gate section GA38 overlaps with the control capacitor C1, and since it is located on a different layer from the control capacitor C1, short circuits can be avoided.

[0205] As shown in Figures 16 and 24, the first source / drain layer SD1 may include a first connection portion S1, a second connection portion S2, a third connection portion S3, a fourth connection portion S4, a fifth connection portion S5, a sixth connection portion S6, a seventh connection portion S7, an eighth connection portion S8, and a ninth connection portion S9, wherein:

[0206] One end of the first connection part S1 is connected to the first semiconductor part IG1 through a contact hole and is connected to the first pole of the input transistor T1, that is, connected to the input terminal of the shift register; the other end of the first connection part S1 can be connected to the output terminal OUT of the previous stage shift register. Of course, if the shift register of this stage is the first pole, the first connection part S1 can be connected to the trigger signal line STL in order to receive the trigger signal STV.

[0207] The second connection part S2 is connected to the first semiconductor part IG1, the fourth gate part GA34 and the third semiconductor part IG3 through contact holes, and can serve as the first input node N2, connecting the second terminal of the input transistor T1, the first terminal of the Zener transistor T5, the second terminal of the second noise reduction transistor T9, the gate of the third control transistor T4 and the gate of the first control transistor T2.

[0208] The third connection part S3 is connected to the first semiconductor part IG1, the first electrode plate C31 and the capacitor part GA371 of the seventh gate part GA37 through contact holes, and can serve as the first output node N4, connecting the gate of the output transistor T7, the second electrode of the Zener transistor T5 and the first electrode plate C31 of the output capacitor C3.

[0209] The fourth connection part S4 is connected to the first semiconductor segment IG21 of the second semiconductor part IG2 through a contact hole, thereby connecting to the first terminal of the second control transistor T3; and the fourth connection part S4 is connected to one end of the first adapter part GA11 through a contact hole, and the other end of the first adapter part GA11 is connected to the third voltage line VHL2 through a contact hole; thereby, the third voltage line VHL2 and the third voltage terminal of the shift register are connected through the fourth connection part S4.

[0210] The fifth connection part S5 is connected to the second semiconductor segment IG22 of the second semiconductor part IG2, the third gate part GA33 and the first plate C11 of the control capacitor C1 through contact holes, and can be used as a control node N3 to connect the second electrode of the first control transistor T2, the gate of the second control transistor T3 and the first plate C11.

[0211] The sixth connection part S6 is connected to the first semiconductor segment IG21 and the fifth gate part GA35 of the second semiconductor part IG2 through contact holes, and can be used as the second input node N1 to connect to the second terminal of the second control transistor T3, the first terminal of the third control transistor T4, the gate of the first noise reduction transistor T8 and the gate of the output control transistor T6.

[0212] The seventh connection part S7 is connected to the first semiconductor segment IG21 and connection segment IG23 of the second semiconductor part IG2 and the fourth semiconductor part IG4 through contact holes, and the seventh connection part S7 and the second voltage line VLL are integral structures, thereby connecting the first terminal of the first control transistor T2, the first terminal of the third control transistor T4 and the first terminal of the output control transistor T6 to the second voltage line VLL so as to simultaneously apply the second voltage VGL to the first control transistor T2, the third control transistor T4 and the output control transistor T6.

[0213] The eighth connecting part S8 can be described based on two different embodiments, wherein:

[0214] As shown in Figures 16 and 24, in the first type of embodiment described above, the eighth connection part S8 is connected to the sixth gate part GA36, the fourth semiconductor part IG4 and the eighth gate part GA38 through contact holes, so that the second clock signal CB1 can be transmitted to the gate of the second noise reduction transistor T9 and the first pole of the output transistor simultaneously through the same second clock signal line CBL1.

[0215] As shown in Figures 25-27, in the second type of embodiment described above, the eighth connection part S8, the fourth semiconductor part IG4, and the eighth gate part GA38 are connected through contact holes, but not connected to the sixth gate part GA36, so that the second clock signal line CBL1 can be connected to the first pole of the output transistor to transmit the second clock signal CB1.

[0216] The ninth connection part S9 is connected to the fourth semiconductor part IG4, the second electrode plate C32 of the output capacitor C3, and the second adapter part GA21 through contact holes, thereby connecting the second electrode of the output control transistor T6, the second electrode of the output transistor T7, and the second electrode plate C32 of the output capacitor C3. Meanwhile, to prevent the ninth connection part S9 from connecting to the seventh gate part GA37, a portion of the capacitor part GA371 and the second electrode plate C32 can be made not to overlap by means of openings or notches. The contact hole connecting the ninth connection part S9 and the second electrode plate C32 can pass through this non-overlapping area, connecting to the second electrode plate C32 while not connecting to the seventh gate part GA37.

[0217] Furthermore, the second adapter G21 and the second plate C22 of the output control capacitor C2 are connected, and can be used as the output terminal OUT to connect with the scan line GL extending to the display area AA so as to output the scan signal; the scan line is arranged on the same layer as the second adapter G21 and the second plate C22, and can be an integral structure.

[0218] As shown in Figures 25 and 28, in the second embodiment, the third clock signal line CBL2 of the second source-drain layer SD2 can overlap with the output capacitor C3. Its width in the row direction X is not greater than the width of the capacitor part GA371, the first electrode C31 and the second electrode C32, and it is connected to the sixth gate part GA36 through a contact hole, thereby connecting the third clock signal line CBL2 to the gate of the second noise reduction transistor T9.

[0219] In the first and second types of embodiments described above, the second source / drain layer SD2 may include multiple signal lines, such as at least two of the first clock signal line CKL, the second clock signal line CBL1, the third clock signal line CBL2, the first voltage line VHL1, the second voltage line VLL, and the third voltage line VHL2, while other signal lines may be located in the first source / drain layer SD1. This is beneficial for reducing the difference in the number of signal lines between the first source / drain layer SD1 and the second source / drain layer SD2, making full use of the space between the first source / drain layer SD1 and the second source / drain layer SD2, and avoiding an overly dense pattern in one film layer. For example, as shown in Figures 29 and 30, in some embodiments of this disclosure, based on the second type of embodiment described above, the first voltage line VHL1, the second voltage line VLL, and the third voltage line VHL2 are located in the first source / drain layer SD1, while the first clock signal line CKL, the second clock signal line CBL1, and the third clock signal line CBL2 may be located in the second source / drain layer SD2.

[0220] As shown in Figure 2, in the first embodiment described above, the display panel may further include a buffer layer BUF made of insulating material, a first gate insulating layer GI1, a second gate insulating layer GI2, a first insulating layer IL1, a third gate insulating layer GI3, a second insulating layer IL2, and a first planarization layer PLN1, wherein:

[0221] A light-shielding layer BSM is disposed on a substrate SU. A buffer layer BUF can cover the light-shielding layer BSM. A polysilicon semiconductor layer SE is disposed on the surface of the buffer layer BUF away from the substrate SU. A first gate insulating layer GI1 covers the polysilicon semiconductor layer SE. A first gate layer GA1 is disposed on the surface of the first gate insulating layer GI1 away from the substrate SU. A second gate insulating layer GI2 covers the first gate layer GA1. A second gate layer GA2 is disposed on the surface of the second gate insulating layer GI2 away from the substrate SU.

[0222] The first insulating layer IL1 may cover the second gate layer GA2. The first insulating layer IL1 may be a single layer or a multilayer structure, and the materials of different layers may be different. The oxide semiconductor layer IG is disposed on the surface of the first insulating layer IL1 away from the substrate SU. The third gate insulating layer GI3 covers the oxide semiconductor layer IG, and the third gate layer GA3 is disposed on the surface of the third gate insulating layer GI3 away from the substrate SU.

[0223] The second insulating layer IL2 may cover the third gate layer GA3. The second insulating layer IL2 may be a single layer or a multilayer structure, and the materials of different layers may be different. The first source / drain layer SD1 is disposed on the surface of the second insulating layer IL2 away from the substrate SU.

[0224] The first planarization layer PLN1 may cover the first source / drain layer SD1. The second source / drain layer SD2 may be disposed on the surface of the first planarization layer PLN1 away from the substrate SU. Furthermore, in some embodiments, a passivation layer may be used to cover the first source / drain layer SD1, and then the first planarization layer PLN1 may be used to cover the passivation layer. The first electrode and pixel definition layer PDL of the light-emitting device LD may be disposed on the surface of the second planarization layer PLN2 away from the substrate SU.

[0225] In the second embodiment described above, the display panel includes the buffer layer BUF, the first gate insulating layer GI1, the second gate insulating layer GI2, the first insulating layer IL1, the third gate insulating layer GI3, the second insulating layer IL2, and the first planarization layer PLN1 as described in the first embodiment. The second source / drain layer SD2 is disposed on the surface of the first planarization layer PLN1 away from the substrate SU. The display panel may also include the second planarization layer PLN2, which may cover the second source / drain layer SD2. The first electrode of the light-emitting device LD and the pixel definition layer PDL may be disposed on the surface of the second planarization layer PLN2 away from the substrate SU.

[0226] This disclosure also provides a display device, which may include the display panel of any of the above embodiments. The display panel is any of the display panels described above, and its specific structure and beneficial effects can be referred to the embodiments of the display panel described above, and will not be repeated here. The display device of this disclosure may be an electronic device such as a mobile phone, tablet computer, or television; or it may be a wearable device with image display function such as a smartwatch, virtual reality device, or augmented reality device; or it may be other electronic devices with display function such as an in-vehicle display device, which will not be listed here.

[0227] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A shift register, comprising: An input circuit is connected to an input terminal, a first clock signal terminal, and a first input node, and is configured to transmit an input signal provided by the input terminal to the first input node in response to a first clock signal provided by the first clock signal terminal, wherein the first input node is connected to a first output node; A first control circuit is connected to the input terminal or the first input node, and to a second voltage terminal, a third voltage terminal, and a second input node; the first control circuit is configured to control the voltage of the second input node under the control of one of the input signal and the signal of the first input node, the voltage of the second voltage terminal, and the voltage of the third voltage terminal; the second input node is connected to a second output node; An output circuit is connected to the first output node, the third voltage terminal, the second clock signal terminal, and the output terminal, and is configured to turn on or off the second clock signal terminal and the output terminal under the control of the voltage of the first output node, wherein the second clock signal terminal is used to provide a second clock signal. An output control circuit is connected to a second output node, a second voltage terminal, and the output terminal, and is configured to turn the second voltage terminal and the output terminal on or off under the control of the voltage of the second output node.

2. The shift register according to claim 1, wherein, The first control circuit includes a first control transistor, a second control transistor, and a control energy storage circuit; the gate of the first control transistor is connected to the input terminal or the first input node, the first electrode is connected to the second voltage terminal, and the second electrode is connected to the control node; the gate of the second control transistor is connected to the control node, the first electrode is connected to the third voltage terminal, and the second electrode is connected to the second input node; the control energy storage circuit is connected to the control node and the first clock signal terminal.

3. The shift register according to claim 2, wherein, The control energy storage circuit includes an input control capacitor, which is connected to the control node and the first clock signal terminal.

4. The shift register according to claim 2, wherein, The shift register further includes a voltage regulator circuit connected to the first voltage terminal, the first output node, and the first input node, and configured to turn the first output node and the first input node on or off under the control of the voltage at the first voltage terminal, and to stabilize the voltage of the first output node when it is on.

5. The shift register according to claim 4, wherein, The shift register further includes a second control circuit connected to the second voltage terminal, the first input node, and the second input node, and configured to be turned on or off under the control of the voltage of the first input node, thereby controlling the voltage of the second input node. When the second control circuit is turned on, it enables the voltage of the second output node to be consistent with the voltage of the second voltage terminal.

6. The shift register according to claim 5, wherein, The shift register further includes a third control circuit connected to a third clock signal terminal, the first input node, the second input node, and the second voltage terminal, and configured to be turned on or off under the control of the third clock signal provided by the third clock signal terminal and the voltage of the second input node, and when the third control circuit is turned on, it enables the voltage of the first input node to be consistent with the voltage of the second voltage terminal.

7. The shift register according to claim 6, wherein, The input circuit includes an input transistor, the gate of which is connected to the first clock signal terminal, the first electrode of which is connected to the input terminal, and the second electrode of which is connected to the first input node; The output control circuit includes an output control transistor and an output control capacitor. The gate of the output control transistor is connected to the second output node, the first terminal is connected to the second voltage terminal, and the second terminal is connected to the output terminal. The output control capacitor is connected to the gate and the second terminal of the output control transistor. The output circuit includes an output transistor and an output capacitor. The gate of the output transistor is connected to the first output node, the first terminal is connected to the second clock signal terminal, and the second terminal is connected to the output terminal. The output capacitor is connected to the gate and the second terminal of the output transistor. The voltage regulator circuit includes a Zener transistor, the gate of which is connected to the first voltage terminal, the first terminal of which is connected to the first input node, and the second terminal of which is connected to the first output node. The second control circuit includes a third control transistor, the gate of which is connected to the first input node, the first terminal of which is connected to the second voltage terminal, and the second terminal of which is connected to the second input node; The third control circuit includes a first noise reduction transistor and a second noise reduction transistor. The gate of the first noise reduction transistor is connected to the second output node. The first terminal of the first noise reduction transistor is connected to the second voltage terminal. The second terminal of the first noise reduction transistor is connected to the first terminal of the second noise reduction transistor. The second terminal of the second noise reduction transistor is connected to the first input node. The gate of the second noise reduction transistor is connected to the third clock signal terminal.

8. The shift register according to claim 7, wherein, The first control transistor and the second control transistor are N-type transistors; at least one of the input transistor, the Zener transistor, the third control transistor, the first noise reduction transistor, the second noise reduction transistor, the output control transistor, and the output transistor is an N-type transistor.

9. The shift register according to claim 4, wherein, The voltage at the first voltage terminal is less than the voltage at the third voltage terminal.

10. The shift register according to claim 6, wherein, The maximum voltage of the third clock signal is less than the maximum voltage of the second clock signal, and the maximum voltage of the third clock signal is less than the voltage of the third voltage terminal.

11. A gate drive circuit comprising a plurality of cascaded shift registers, wherein the shift registers are the shift registers according to any one of claims 1-10.

12. A display panel comprising a plurality of pixel circuits and a gate driving circuit, the pixel circuits being arrayed along a row direction and a column direction; the gate driving circuit comprising a plurality of cascaded shift registers; an output terminal of one of the shift registers being connected to at least one row of the pixel circuits; The shift register includes multiple transistors, including an input transistor, a first control transistor, a second control transistor, a third control transistor, a Zener transistor, an output control transistor, an output transistor, a first noise reduction transistor, a second noise reduction transistor, an input control capacitor, an output control capacitor, and an output capacitor. The gate of the input transistor is connected to the first clock signal terminal, the first electrode is connected to the input terminal, and the second electrode is connected to the first input node; The gate of the first control transistor is connected to the input terminal or the first input node, the first terminal is connected to the second voltage terminal, and the second terminal is connected to the control node; the gate of the second control transistor is connected to the control node, the first terminal is connected to the third voltage terminal, and the second terminal is connected to the second input node. The gate of the third control transistor is connected to the first input node, and the first electrode is connected to the... The second voltage terminal is connected, and the second pole is connected to the second input node; The gate of the Zener transistor is connected to the first voltage terminal, the first terminal is connected to the first input node, and the second terminal is connected to the first output node; The gate of the output control transistor is connected to the second output node, the first terminal is connected to the second voltage terminal, and the second terminal is connected to the output terminal. The second input node is connected to the second output node; the gate of the output transistor is connected to the first output node, the first terminal is connected to the second clock signal terminal, and the second terminal is connected to the output terminal. The gate of the first noise reduction transistor is connected to the second output node, the first terminal of the first noise reduction transistor is connected to the second voltage terminal, the second terminal of the first noise reduction transistor is connected to the first terminal of the second noise reduction transistor, the second terminal of the second noise reduction transistor is connected to the first input node, and the gate of the second noise reduction transistor is connected to the third clock signal terminal. The first plate of the input control capacitor is connected to the control node, and the second plate is connected to the first clock signal terminal; the first plate of the output control capacitor is connected to the gate of the output control transistor, and the second plate is connected to the output terminal. The first plate of the output capacitor is connected to the gate of the output transistor, and the second plate is connected to the output terminal. The display panel includes: Substrate; An oxide semiconductor layer is disposed on one side of the substrate and includes the active portions of each of the transistors of the shift register; One plate of the input control capacitor, one plate of the output control capacitor, and one plate of the output capacitor are arranged in the same layer.

13. The display panel according to claim 12, wherein, The display panel also includes a first clock signal line, a second clock signal line, a first voltage line, a second voltage line, and a third voltage line extending along the column direction; The first clock signal line is connected to the first clock signal terminal, the second clock signal line is connected to the second clock signal terminal and the third clock signal terminal, the first voltage line is connected to the first voltage terminal, the second voltage line is connected to the second voltage line, and the third voltage line is connected to the third voltage terminal. The second clock signal line, the first clock signal line, the first voltage line, and the The third voltage line and the second voltage line are distributed sequentially at intervals along the row direction; each of the transistors in the shift register is located between the third voltage line and the second voltage line.

14. The display panel according to claim 12, wherein, The display panel also includes a first clock signal line, a second clock signal line, a third clock signal line, a first voltage line, a second voltage line, and a third voltage line extending along the column direction; The first clock signal line is connected to the first clock signal terminal, the second clock signal line is connected to the second clock signal terminal, the third clock signal line is connected to the third clock signal terminal, the first voltage line is connected to the first voltage terminal, the second voltage line is connected to the second voltage line, and the third voltage line is connected to the third voltage terminal. The second clock signal line, the first clock signal line, the first voltage line, the third voltage line, the third clock signal line, and the second voltage line are distributed sequentially at intervals along the row direction; each of the transistors in the shift register is located between the third voltage line and the second voltage line.

15. The display panel according to claim 12, wherein, The oxide semiconductor layer includes a first semiconductor portion, a second semiconductor portion, a third semiconductor portion, and at least one fourth semiconductor portion distributed along the row direction; The first semiconductor section extends along the column direction, and the active portions of the input transistor and the Zener transistor are located in the first semiconductor section and distributed along the column direction; The second semiconductor section includes a first semiconductor segment and a second semiconductor segment distributed along the column direction, and a connection segment connecting the first semiconductor segment and the second semiconductor segment; the active portions of the second control transistor and the third control transistor are located in the first semiconductor segment and distributed along the row direction; the active portion of the first control transistor is located in the second semiconductor segment; The third semiconductor section extends along the column direction, and the active portions of the first noise reduction transistor and the second noise reduction transistor are located in the third semiconductor section and distributed along the column direction; The output control transistor and the active portion of the output transistor are located in the fourth semiconductor section and are distributed along the column direction.

16. The display panel according to claim 13, wherein, The display panel also includes: A first gate layer is disposed on one side of the substrate and includes the first electrode of the input control capacitor and the first electrode of the output capacitor; A second gate layer is disposed on the side of the first gate layer away from the substrate, and includes the... The second electrode of the input control capacitor, the second electrode of the output capacitor, and the first electrode of the output control capacitor are described; the oxide semiconductor layer is disposed on the side of the second gate layer away from the substrate; The third gate layer is disposed on the side of the oxide semiconductor layer away from the substrate, and includes the gate of each of the transistors of the shift register and the second plate of the output control capacitor; The first source / drain layer is disposed on the side of the third gate layer away from the substrate, and includes the second clock signal line, the first clock signal line, the first voltage line, the third voltage line, and the second voltage line.

17. The display panel according to claim 14, wherein, The display panel also includes: A first gate layer is disposed on one side of the substrate and includes the first electrode of the input control capacitor and the first electrode of the output capacitor; The second gate layer is disposed on the side of the first gate layer away from the substrate, and includes the second electrode of the input control capacitor, the second electrode of the output capacitor, and the first electrode of the output control capacitor; the oxide semiconductor layer is disposed on the side of the second gate layer away from the substrate; The third gate layer is disposed on the side of the oxide semiconductor layer away from the substrate, and includes the gate of each of the transistors of the shift register and the second plate of the output control capacitor; The first source / drain layer is disposed on the side of the third gate layer away from the substrate, and includes the second clock signal line, the first clock signal line, the first voltage line, the third voltage line, and the second voltage line; The second source / drain layer is disposed on the side of the first source / drain layer away from the substrate, and includes the third clock signal line.

18. The display panel according to claim 12, wherein, In one of the shift registers, there are multiple output control transistors and output transistors; the gates of each output control transistor are connected, the first terminal of each output control transistor is connected to the second voltage terminal, and the second terminal of each output control transistor is connected to the output terminal; the gates of each output transistor are connected, the first terminal of each output transistor is connected to the first output node, and the second terminal of each output transistor is connected to the output terminal.

19. The display panel according to claim 12, wherein, The output control transistor includes a plurality of sub-control transistors connected in series, and the output transistor includes a plurality of sub-output transistors connected in series.

20. The display panel according to claim 14, wherein, The third clock signal line overlaps with the output capacitor.

21. The display panel according to claim 12, wherein, The display panel also includes: A first gate layer is disposed on one side of the substrate; The second gate layer is disposed on the side of the first gate layer away from the substrate; the oxide semiconductor layer is disposed on the side of the second gate layer away from the substrate; A third gate layer is disposed on the side of the oxide semiconductor layer away from the substrate, and includes the gate of each of the transistors of the shift register and a plate of at least one of the output capacitor and the output control capacitor.

22. The display panel according to claim 14, wherein, The display panel also includes: A first gate layer is disposed on one side of the substrate and includes the first electrode of the input control capacitor and the first electrode of the output capacitor; The second gate layer is disposed on the side of the first gate layer away from the substrate, and includes the second electrode of the input control capacitor, the second electrode of the output capacitor, and the first electrode of the output control capacitor; the oxide semiconductor layer is disposed on the side of the second gate layer away from the substrate; The third gate layer is disposed on the side of the oxide semiconductor layer away from the substrate, and includes the gate of each of the transistors of the shift register and the second plate of the output control capacitor; The first source / drain layer is disposed on the side of the third gate layer away from the substrate; The second source / drain layer is disposed on the side of the first source / drain layer away from the substrate, and includes at least two of the first voltage line, the third voltage line, the second voltage line, the first clock signal line, the second clock signal line, and the third clock signal line.

23. A method for driving a shift register, wherein the shift register is the shift register according to any one of claims 1-10; the driving method includes: In the first stage, the input circuit and the output circuit are turned on; The output control circuit is turned off, and the third voltage terminal and the second input are turned off through the first control circuit. node; In the second stage, the output circuit is turned on; the input circuit and the output control circuit are turned off, and the third voltage terminal and the second input node are turned off through the first control circuit; In the third stage, the input circuit and the output control circuit are turned on, and the third voltage terminal and the second input node are turned on through the first control circuit; the output circuit is turned off. In the fourth stage, the output control circuit is turned on; The output circuit is turned off, and the third voltage terminal and the second input node are turned off through the first control circuit.

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