Pixel circuit, driving method and display apparatus

Abstract

Provided in the present disclosure are a pixel circuit, a driving method and a display apparatus. The pixel circuit comprises a driving circuit, a first control circuit, a second control circuit and a first initialization circuit, wherein under the control of a first control signal, the first control circuit controls the connection between a first node and a fourth node; under the control of a second control signal, the second control circuit controls the connection between the fourth node and a third node; and under the control of a first initial control signal, the first initialization circuit writes a first initial voltage into the fourth node. The pixel circuit having a new structure provided in the embodiments of the present disclosure can work normally without adding a GOA (gate on array, which is a gate driving circuit arranged on an array substrate) module, and can ameliorate the phenomenon of hysteresis of a driving transistor included in a driving circuit, thereby mitigating image sticking.

Description

Pixel circuits, driving methods, and display devices

[0001] Cross-references to related applications

[0002] This application claims priority to Chinese Patent Application No. 202410494908.6, filed in China on April 23, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of display technology, and more particularly to a pixel circuit, driving method, and display device. Background Technology

[0004] AMOLED (Active Matrix Organic Light Emitting Diode) display panels are still widely used in screen products due to their lower cost and shorter production time, but they have defects such as poor image retention. Summary of the Invention

[0005] The main objective of this disclosure is to provide a pixel circuit, driving method, and display device to solve the problem that the prior art cannot provide a pixel circuit with a new structure and cannot operate normally without adding a GOA (Gate On Array) module.

[0006] In one aspect, embodiments of this disclosure provide a pixel circuit, including a driving circuit, a first control circuit, a second control circuit, and a first initialization circuit;

[0007] The control terminal of the driving circuit is electrically connected to the first node, the first terminal of the driving circuit is electrically connected to the second node, and the second terminal of the driving circuit is electrically connected to the third node. The driving circuit is used to generate a driving current under the control of the potential of the first node.

[0008] The first control circuit is electrically connected to the first control terminal, the first node, and the fourth node, respectively, and is used to control the connection between the first node and the fourth node under the control of the first control signal provided by the first control terminal;

[0009] The second control circuit is electrically connected to the second control terminal, the fourth node, and the third node, respectively, and is used to control the connection between the fourth node and the third node under the control of the second control signal provided by the second control terminal;

[0010] The first initialization circuit is electrically connected to the first initial control terminal and the first initial voltage terminal respectively. The first initialization circuit is also electrically connected to the fourth node, and is used to write the first initial voltage provided by the first initial voltage terminal into the fourth node under the control of the first initial control signal provided by the first initial control terminal.

[0011] Optionally, the pixel circuit described in at least one embodiment of this disclosure further includes a second initialization circuit;

[0012] The second initialization circuit is electrically connected to the second initial control terminal, the second initial voltage terminal, and the first node, respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the first node under the control of the second initial control signal provided by the second initial control terminal.

[0013] Optionally, the pixel circuit described in at least one embodiment of this disclosure further includes a second initialization circuit;

[0014] The second initialization circuit is electrically connected to the second initial control terminal, the second initial voltage terminal, and the fourth node, respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the fourth node under the control of the second initial control signal provided by the second initial control terminal.

[0015] Optionally, the pixel circuit described in at least one embodiment of this disclosure further includes a light-emitting element, a first light-emitting control circuit, and a second initialization circuit;

[0016] The first light-emitting control circuit is electrically connected to the first light-emitting control signal terminal, the third node, and the first electrode of the light-emitting element, respectively, and is used to control the connection between the third node and the first electrode of the light-emitting element under the control of the first light-emitting control signal provided by the first light-emitting control signal terminal; the second electrode of the light-emitting element is electrically connected to the first voltage terminal.

[0017] The second initialization circuit is electrically connected to the second initial control terminal, the second initial voltage terminal, and the first electrode of the light-emitting element, respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the first electrode of the light-emitting element under the control of the second initial control signal provided by the second initial control terminal.

[0018] Optionally, the pixel circuit described in at least one embodiment of this disclosure further includes a voltage control circuit;

[0019] The voltage control circuit is electrically connected to the fourth node and the control voltage terminal respectively, and is used to control the potential of the fourth node according to the control voltage provided by the control voltage terminal; or,

[0020] The voltage control circuit is electrically connected to both the fourth node and the third node, and is used to control the potential of the fourth node according to the potential of the third node; or,

[0021] The pixel circuit further includes a light-emitting element and a first light-emitting control circuit. The voltage control circuit is electrically connected to the fourth node and the first light-emitting control signal terminal, respectively, and is used to control the potential of the fourth node according to the first light-emitting control signal provided by the first light-emitting control signal terminal.

[0022] Optionally, the first control terminal is the nth level scan terminal, the second control terminal is the nth level gate drive terminal, the first initial control terminal is the n+yth level gate drive terminal, and the second initial voltage terminal is the nxth level scan terminal;

[0023] n, x, and y are all positive integers.

[0024] Optionally, the first control terminal is the nth level gate drive terminal, the second control terminal includes the nth level scan terminal and the n+yth level scan terminal, the first initial control terminal is the n+yth level scan terminal, and the second initial control terminal is the nxth level scan terminal;

[0025] n, x, and y are all positive integers.

[0026] Optionally, the first control terminal includes an nth level scan terminal and an nxth level scan terminal, the second control terminal is an nth level gate drive terminal, the first initial control terminal is an n+yth level gate drive terminal, and the second initial control terminal is an nxth level scan terminal;

[0027] n, x, and y are all positive integers.

[0028] Optionally, the first control terminal is the nth level second light-emitting control terminal, the second control terminal is the nath level third light-emitting control terminal, the first initial control terminal is the nth level third light-emitting control terminal, and the second initial control terminal is the nbth level gate driving terminal.

[0029] n, a, and b are all positive integers.

[0030] Optionally, the first control terminal is the second light-emitting control terminal of the na-th stage, the second control terminal is the second light-emitting control terminal of the n-th stage, the first initial control terminal is the gate driving terminal of the n+b-th stage, and the second initial control terminal is the second light-emitting control terminal of the nc-th stage.

[0031] n, a, b, and c are all positive integers.

[0032] Optionally, the first control terminal is the second light-emitting control terminal of the nth stage, the second control terminal is the third light-emitting control terminal of the nath stage, the first initial control terminal is the third light-emitting control terminal of the nth stage, the first light-emitting control signal terminal is the first light-emitting control terminal of the n+bth stage, and the second initial control terminal is the gate driving terminal of the ncth stage.

[0033] n, a, b, and c are all positive integers.

[0034] Optionally, the first control circuit includes a first transistor, the second control circuit includes a second transistor, the first initialization circuit includes a third transistor, and the second initialization circuit includes a fourth transistor.

[0035] The gate of the first transistor is electrically connected to the nth scanning terminal, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the fourth node.

[0036] The gate of the second transistor is electrically connected to the nth gate drive terminal, the first terminal of the second transistor is electrically connected to the fourth node, and the second terminal of the second transistor is electrically connected to the third node.

[0037] The gate of the third transistor is electrically connected to the gate driving terminal of the (n+y)th stage, the first terminal of the third transistor is electrically connected to the first initial voltage terminal, and the second terminal of the third transistor is electrically connected to the fourth node.

[0038] The gate of the fourth transistor is electrically connected to the nx-th scanning terminal, the first terminal of the fourth transistor is electrically connected to the second initial voltage terminal, and the second terminal of the fourth transistor is electrically connected to the first node.

[0039] Optionally, the first control circuit includes a first transistor, the second control circuit includes a second transistor and a fifth transistor, the first initialization circuit includes a third transistor, and the second initialization circuit includes a fourth transistor.

[0040] The gate of the first transistor is electrically connected to the nth gate drive terminal, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the fourth node.

[0041] The gate of the second transistor is electrically connected to the nth scanning terminal, the first terminal of the second transistor is electrically connected to the fourth node, and the second terminal of the second transistor is electrically connected to the third node;

[0042] The gate of the fifth transistor is electrically connected to the (n+y)th scanning terminal, the first terminal of the fifth transistor is electrically connected to the fourth node, and the second terminal of the fifth transistor is electrically connected to the third node.

[0043] The gate of the third transistor is electrically connected to the (n+y)th scanning terminal, the first terminal of the third transistor is electrically connected to the first initial voltage terminal, and the second terminal of the third transistor is electrically connected to the fourth node.

[0044] The gate of the fourth transistor is electrically connected to the nx-th scanning terminal, the first terminal of the fourth transistor is electrically connected to the second initial voltage terminal, and the second terminal of the fourth transistor is electrically connected to the fourth node or the first node.

[0045] Optionally, the first control circuit includes a first transistor and a sixth transistor, the second control circuit includes a second transistor, the first initialization circuit includes a third transistor, and the second initialization circuit includes a fourth transistor.

[0046] The gate of the first transistor is electrically connected to the nxth scan terminal, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the fourth node.

[0047] The gate of the sixth transistor is electrically connected to the nth scanning terminal, the first terminal of the sixth transistor is electrically connected to the first node, and the second terminal of the sixth transistor is electrically connected to the fourth node.

[0048] The gate of the second transistor is electrically connected to the nth gate drive terminal, the first terminal of the second transistor is electrically connected to the fourth node, and the second terminal of the second transistor is electrically connected to the third node.

[0049] The gate of the third transistor is electrically connected to the gate scan terminal of the (n+y)th stage, the first terminal of the third transistor is electrically connected to the first initial voltage terminal, and the second terminal of the third transistor is electrically connected to the fourth node.

[0050] The gate of the fourth transistor is electrically connected to the nx-th scan terminal, the first terminal of the fourth transistor is electrically connected to the second initial voltage terminal, and the second terminal of the fourth transistor is electrically connected to the first node or the fourth node.

[0051] Optionally, the first control circuit includes a first transistor, the second control circuit includes a second transistor, and the first initialization circuit includes a third transistor.

[0052] The gate of the first transistor is electrically connected to the first control terminal, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the fourth node.

[0053] The gate of the second transistor is electrically connected to the second control terminal, the first terminal of the second transistor is electrically connected to the fourth node, and the second terminal of the second transistor is electrically connected to the third node.

[0054] The gate of the third transistor is electrically connected to the first initial control terminal, the first terminal of the third transistor is electrically connected to the first initial voltage terminal, and the second terminal of the third transistor is electrically connected to the fourth node.

[0055] Optionally, the first light-emitting control circuit includes an eighth transistor, and the second initialization circuit includes a fourth transistor;

[0056] The gate of the eighth transistor is electrically connected to the first light-emitting control signal terminal, the first electrode of the eighth transistor is electrically connected to the third node, and the second electrode of the eighth transistor is electrically connected to the first electrode of the light-emitting element.

[0057] The gate of the fourth transistor is electrically connected to the second initial control terminal, the first terminal of the fourth transistor is electrically connected to the second initial voltage terminal, and the second terminal of the fourth transistor is electrically connected to the first terminal of the light-emitting element.

[0058] Optionally, the voltage control circuit includes a first capacitor;

[0059] The first terminal of the first capacitor is electrically connected to the fourth node, and the second terminal of the first capacitor is electrically connected to the control voltage terminal; or...

[0060] The first terminal of the first capacitor is electrically connected to the fourth node, and the second terminal of the first capacitor is electrically connected to the third node; or...

[0061] The first end of the first capacitor is electrically connected to the fourth node, and the second end of the first capacitor is electrically connected to the first light-emitting control signal terminal.

[0062] Optionally, the pixel circuit described in at least one embodiment of this disclosure further includes a light-emitting element, a first light-emitting control circuit, a second light-emitting control circuit, a data writing circuit, and an energy storage circuit;

[0063] The first light-emitting control circuit is electrically connected to the light-emitting control terminal, the third node, and the first electrode of the light-emitting element, respectively, and is used to control the connection between the third node and the first electrode of the light-emitting element under the control of the light-emitting control signal provided by the light-emitting control terminal; the second electrode of the light-emitting element is electrically connected to the first voltage terminal.

[0064] The second light-emitting control circuit is electrically connected to the light-emitting control terminal, the power supply voltage terminal, and the second node, respectively, and is used to control the connection between the power supply voltage terminal and the second node under the control of the light-emitting control signal;

[0065] The data writing circuit is electrically connected to the nth level scanning terminal, the data line, and the second node, respectively, and is used to write the data voltage provided by the data line into the second node under the control of the nth level scanning signal provided by the nth level scanning terminal; n is a positive integer;

[0066] The first end of the energy storage circuit is electrically connected to the first node, and the second end of the energy storage circuit is electrically connected to the DC voltage terminal. The energy storage circuit is used to store electrical energy.

[0067] Optionally, the pixel circuit described in at least one embodiment of this disclosure further includes a voltage control circuit; the voltage control circuit includes a first capacitor, a first terminal of which is electrically connected to the fourth node, and a second terminal of which is electrically connected to the control voltage terminal; the energy storage circuit includes a storage capacitor; a first terminal of which is electrically connected to the first node, and a second terminal of which is electrically connected to the DC voltage terminal;

[0068] The capacitance value of the first capacitor is less than or equal to 1 / 5 of the capacitance value of the storage capacitor, and the capacitance value of the first capacitor is greater than or equal to 1fF.

[0069] Optionally, the pixel circuit described in at least one embodiment of this disclosure further includes a light-emitting element, a second light-emitting control circuit, a data writing circuit, and an energy storage circuit;

[0070] The second light-emitting control circuit is electrically connected to the second light-emitting control signal terminal, the power supply voltage terminal, and the second node, respectively, and is used to control the connection between the power supply voltage terminal and the second node under the control of the second light-emitting control signal provided by the second light-emitting control signal terminal;

[0071] The data writing circuit is electrically connected to the nth-level gate driving terminal, the data line, and the second node, respectively, and is used to write the data voltage provided by the data line into the second node under the control of the nth-level gate driving signal provided by the nth-level gate driving terminal; n is a positive integer;

[0072] The first end of the energy storage circuit is electrically connected to the first node, and the second end of the energy storage circuit is electrically connected to the DC voltage terminal. The energy storage circuit is used to store electrical energy.

[0073] Optionally, the pixel circuit described in at least one embodiment of this disclosure further includes a voltage control circuit; the voltage control circuit includes a first capacitor, a first terminal of which is electrically connected to the fourth node, and a second terminal of which is electrically connected to the third node; the energy storage circuit includes a storage capacitor; a first terminal of which is electrically connected to the first node, and a second terminal of which is electrically connected to a DC voltage terminal.

[0074] The capacitance value of the first capacitor is less than or equal to 1 / 5 of the capacitance value of the storage capacitor, and the capacitance value of the first capacitor is greater than or equal to 1fF.

[0075] Optionally, the pixel circuit described in at least one embodiment of this disclosure further includes a third initialization circuit;

[0076] The third initialization circuit is electrically connected to the third initial control terminal, the third initial voltage terminal, and the first electrode of the light-emitting element, respectively, and is used to write the third initial voltage provided by the third initial voltage terminal into the first electrode of the light-emitting element under the control of the third initial control signal provided by the third initial control terminal.

[0077] Optionally, the second light-emitting control circuit includes a seventh transistor, the first light-emitting control circuit includes an eighth transistor, the data writing circuit includes a ninth transistor, and the energy storage circuit includes a storage capacitor.

[0078] The gate of the seventh transistor is electrically connected to the light-emitting control terminal, the first terminal of the seventh transistor is electrically connected to the power supply voltage terminal, and the second terminal of the seventh transistor is electrically connected to the second node.

[0079] The gate of the eighth transistor is electrically connected to the light-emitting control terminal, the first terminal of the eighth transistor is electrically connected to the third node, and the second terminal of the eighth transistor is electrically connected to the first terminal of the light-emitting element.

[0080] The gate of the ninth transistor is electrically connected to the nth scanning terminal, the first terminal of the ninth transistor is electrically connected to the data line, and the second terminal of the ninth transistor is electrically connected to the second node.

[0081] The first end of the storage capacitor is electrically connected to the first node, and the second end of the storage capacitor is electrically connected to the DC voltage terminal.

[0082] Optionally, the second light-emitting control circuit includes a seventh transistor; the data writing circuit includes a ninth transistor; and the energy storage circuit includes a storage capacitor.

[0083] The gate of the seventh transistor is electrically connected to the second light-emitting control signal terminal, the first terminal of the seventh transistor is electrically connected to the power supply voltage terminal, and the second terminal of the seventh transistor is electrically connected to the second node.

[0084] The gate of the ninth transistor is electrically connected to the nth gate driving terminal, the first terminal of the ninth transistor is electrically connected to the data line, and the second terminal of the ninth transistor is electrically connected to the second node.

[0085] The first end of the storage capacitor is electrically connected to the first node, and the second end of the storage capacitor is electrically connected to the DC voltage terminal.

[0086] Optionally, the third initialization circuit includes a tenth transistor;

[0087] The gate of the tenth transistor is electrically connected to the third initial control terminal, the first terminal of the tenth transistor is electrically connected to the third initial voltage terminal, and the second terminal of the tenth transistor is electrically connected to the first terminal of the light-emitting element.

[0088] In a second aspect, embodiments of this disclosure provide a driving method applied to the aforementioned pixel circuit, wherein the refresh frame includes a compensation stage and a first hysteresis improvement stage set sequentially; the driving method includes:

[0089] During the compensation phase, the first control circuit, under the control of the first control signal, controls the connection between the first node and the fourth node; the second control circuit, under the control of the second control signal, controls the connection between the fourth node and the third node.

[0090] In the first hysteresis improvement stage, the first initialization circuit, under the control of the first initial control signal, writes the first initial voltage into the fourth node, and the second control circuit, under the control of the second control signal, controls the connection between the fourth node and the third node.

[0091] Optionally, the refresh frame further includes a first voltage control stage and a first light emission stage, set sequentially after the first hysteresis improvement stage; the pixel circuit further includes a voltage control circuit, a light-emitting element, a first light emission control circuit, and a second light emission control circuit; the driving method further includes:

[0092] During the first voltage control phase, the potential of the control voltage provided by the control voltage terminal is pulled down, and the voltage control circuit controls the potential of the fourth node to become lower according to the control voltage.

[0093] During the first light-emitting stage, the second light-emitting control circuit, under the control of the light-emitting control signal, controls the connection between the power supply voltage terminal and the second node; the first light-emitting control circuit, under the control of the light-emitting control signal, controls the connection between the third node and the first electrode of the light-emitting element.

[0094] Optionally, the pixel circuit further includes a voltage control circuit; the voltage control circuit is electrically connected to the fourth node and the third node respectively, and is used to control the potential of the fourth node according to the potential of the third node; the refresh frame further includes a first light emission stage set after the first hysteresis improvement stage; the driving method further includes:

[0095] At the start of the first light-emitting stage, the voltage control circuit controls the potential of the fourth node to decrease according to the potential of the third node.

[0096] Optionally, the holding frame includes a second hysteresis improvement phase; the driving method includes:

[0097] In the second hysteresis improvement stage, the first initialization circuit, under the control of the first initial control signal, writes the first initial voltage into the fourth node, and the second control circuit, under the control of the second control signal, controls the connection between the fourth node and the third node.

[0098] Optionally, the pixel circuit further includes a voltage control circuit; the voltage control circuit is electrically connected to the fourth node and the third node respectively, and is used to control the potential of the fourth node according to the potential of the third node; the holding frame further includes a second emission stage disposed after the second hysteresis improvement stage; the driving method further includes:

[0099] At the start of the second light-emitting stage, the voltage control circuit controls the potential of the fourth node to decrease according to the potential of the third node.

[0100] In a third aspect, embodiments of this disclosure provide a display device including the pixel circuit described above.

[0101] At least one embodiment of this disclosure provides a pixel circuit with a novel structure that can operate normally without adding a GOA (Gate On Array) module and can improve the hysteresis of the driving transistors included in the driving circuit, thereby improving image retention. Attached Figure Description

[0102] Figure 1 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0103] Figure 2 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0104] Figure 3A is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0105] Figure 3B is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0106] Figure 4 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0107] Figure 5A is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0108] Figure 5B is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0109] Figure 5C is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0110] Figure 6 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0111] Figure 7A is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0112] Figure 7B is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0113] Figure 7C is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0114] Figure 7D is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0115] Figure 8 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0116] Figure 9 is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 8 during a refresh frame.

[0117] Figure 10 is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 8 in the operation of the holding frame;

[0118] Figure 11 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0119] Figure 12 is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 11 during a refresh frame.

[0120] Figure 13 is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 11 in the operation of the holding frame;

[0121] Figure 14 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0122] Figure 15 is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 14 during a refresh frame.

[0123] Figure 16 is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 14 in the operation of the holding frame;

[0124] Figure 17 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0125] Figure 18 is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 17 during a refresh frame.

[0126] Figure 19 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0127] Figure 20 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0128] Figure 21 is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 20 during a refresh frame.

[0129] Figure 22 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0130] Figure 23 is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 22 during the refresh frame.

[0131] Figure 24 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0132] Figure 25 is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 24 during the refresh frame. Detailed Implementation

[0133] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this disclosure.

[0134] In all embodiments of this disclosure, the transistors used can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. In the embodiments of this disclosure, to distinguish the two terminals of the transistor other than the gate, one terminal is referred to as the first terminal and the other as the second terminal.

[0135] In actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the first electrode can be the drain and the second electrode can be the source; or, the first electrode can be the source and the second electrode can be the drain.

[0136] The pixel circuit described in this embodiment includes a driving circuit, a first control circuit, a second control circuit, and a first initialization circuit;

[0137] The control terminal of the driving circuit is electrically connected to the first node, the first terminal of the driving circuit is electrically connected to the second node, and the second terminal of the driving circuit is electrically connected to the third node. The driving circuit is used to generate a driving current under the control of the potential of the first node.

[0138] The first control circuit is electrically connected to the first control terminal, the first node, and the fourth node, respectively, and is used to control the connection between the first node and the fourth node under the control of the first control signal provided by the first control terminal;

[0139] The second control circuit is electrically connected to the second control terminal, the fourth node, and the third node, respectively, and is used to control the connection between the fourth node and the third node under the control of the second control signal provided by the second control terminal;

[0140] The first initialization circuit is electrically connected to the first initial control terminal and the first initial voltage terminal respectively. The first initialization circuit is also electrically connected to the fourth node, and is used to write the first initial voltage provided by the first initial voltage terminal into the fourth node under the control of the first initial control signal provided by the first initial control terminal.

[0141] When the pixel circuit described in the embodiments of this disclosure is in operation...

[0142] During the compensation phase, the first control circuit, under the control of the first control signal, controls the connection between the first node and the fourth node, and the second control circuit, under the control of the second control signal, controls the connection between the fourth node and the third node, so as to control the connection between the first node and the third node.

[0143] In the first hysteresis improvement stage, the first initialization circuit, under the control of the first initial control signal, writes the first initial voltage into the fourth node, and the second control circuit, under the control of the second control signal, controls the connection between the fourth node and the third node to write the first initial voltage into the third node, thereby improving the hysteresis phenomenon of the driving transistor included in the driving circuit.

[0144] At least one embodiment of this disclosure provides a pixel circuit with a novel structure that can operate normally without adding a GOA (Gate On Array) module and can improve the hysteresis of the driving transistors included in the driving circuit, thereby improving image retention.

[0145] At least one embodiment of this disclosure can conveniently switch between refresh frames and hold frames by controlling the first control signal provided by the first control terminal, thereby enabling high-precision frequency conversion. As shown in FIG1, the pixel circuit described in at least one embodiment of this disclosure includes a driving circuit 10, a first control circuit 11, a second control circuit 12, and a first initialization circuit 13;

[0146] The control terminal of the driving circuit 10 is electrically connected to the first node N1, the first terminal of the driving circuit 10 is electrically connected to the second node N2, and the second terminal of the driving circuit 10 is electrically connected to the third node N3. The driving circuit 10 is used to generate a driving current under the control of the potential of the first node N1.

[0147] The first control circuit 11 is electrically connected to the first control terminal TC1, the first node N1 and the fourth node N4 respectively, and is used to control the connection between the first node N1 and the fourth node N4 under the control of the first control signal provided by the first control terminal TC1.

[0148] The second control circuit 12 is electrically connected to the second control terminal TC2, the fourth node N4 and the third node N3 respectively, and is used to control the connection between the fourth node N4 and the third node N3 under the control of the second control signal provided by the second control terminal TC2;

[0149] The first initialization circuit 13 is electrically connected to the first initial control terminal TI1, the first initial voltage terminal I1 and the fourth node N4 respectively, and is used to write the first initial voltage Vi1 provided by the first initial voltage terminal I1 into the fourth node N4 under the control of the first initial control signal provided by the first initial control terminal TI1.

[0150] In at least one embodiment of the pixel circuit shown in FIG1 of this disclosure, when in operation, the refresh frame may include a compensation stage and a first hysteresis improvement stage set sequentially.

[0151] During the compensation phase, the first control circuit 11 controls the connection between the first node N1 and the fourth node N4 under the control of the first control signal, and the second control circuit 12 controls the connection between the fourth node N4 and the third node N3 under the control of the second control signal, so as to control the connection between the first node N1 and the third node N3.

[0152] In the first hysteresis improvement stage, the first initialization circuit 13, under the control of the first initial control signal, writes the first initial voltage Vi1 into the fourth node N4. The second control circuit 12, under the control of the second control signal, controls the connection between the fourth node N4 and the third node N3 to write the first initial voltage Vi1 into the third node N3, thereby improving the hysteresis phenomenon of the driving transistor included in the driving circuit 10.

[0153] In at least one embodiment of the pixel circuit shown in FIG1 of this disclosure, during the first hysteresis improvement stage, the driving circuit 10 controls the connection between the second node N2 and the third node N3 under the control of the potential of the first node N1, thereby improving the hysteresis phenomenon of the driving transistors included in the driving circuit 10.

[0154] In at least one embodiment of the pixel circuit shown in FIG1 of this disclosure, the frame holding phase may include a second hysteresis improvement phase during operation;

[0155] In the second hysteresis improvement stage, the first initialization circuit 13, under the control of the first initial control signal, writes the first initial voltage Vi1 into the fourth node N4. The second control circuit 12, under the control of the second control signal, controls the connection between the fourth node N4 and the third node N3 to write the first initial voltage Vi1 into the third node N3, thereby improving the hysteresis phenomenon of the driving transistor included in the driving circuit 10.

[0156] In at least one embodiment of the pixel circuit shown in FIG1 of this disclosure, during the second hysteresis improvement stage, the driving circuit 10 controls the connection between the second node N2 and the third node N3 under the control of the potential of the first node N1, thereby improving the hysteresis phenomenon of the driving transistor included in the driving circuit 10.

[0157] As shown in Figure 2, in at least one embodiment of the pixel circuit shown in Figure 1, the pixel circuit of this at least one embodiment further includes a second initialization circuit 21;

[0158] The second initialization circuit 21 is electrically connected to the second initial control terminal TI2, the second initial voltage terminal I2 and the first node N1 respectively, and is used to write the second initial voltage Vi2 provided by the second initial voltage terminal I2 into the first node N1 under the control of the second initial control signal provided by the second initial control terminal TI2.

[0159] The pixel circuit described in the embodiments of this disclosure further includes a second initialization circuit;

[0160] The second initialization circuit is electrically connected to the second initial control terminal, the second initial voltage terminal, and the fourth node, respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the fourth node under the control of the second initial control signal provided by the second initial control terminal.

[0161] In a specific implementation, the pixel circuit may further include a second initialization circuit, and the refresh frame may include an initialization phase and a compensation phase set sequentially. In the initialization phase, the first control circuit, under the control of the first control signal, controls the connection between the first node and the fourth node. The second initialization circuit, under the control of the second initial control signal, writes the second initial voltage into the fourth node, thereby writing the second initial voltage into the first node, so that at the beginning of the compensation phase, the driving circuit, under the control of the potential of the first node, controls the connection between the second node and the third node.

[0162] As shown in FIG3A, based on at least one embodiment of the pixel circuit shown in FIG1, the pixel circuit of the present disclosure further includes a second initialization circuit 21;

[0163] The second initialization circuit 21 is electrically connected to the second initial control terminal TI2, the second initial voltage terminal I2 and the fourth node N4 respectively, and is used to write the second initial voltage Vi2 provided by the second initial voltage terminal I2 into the fourth node N4 under the control of the second initial control signal provided by the second initial control terminal TI2.

[0164] The pixel circuit described in at least one embodiment of this disclosure may further include a light-emitting element, a first light-emitting control circuit, and a second initialization circuit;

[0165] The first light-emitting control circuit is electrically connected to the first light-emitting control signal terminal, the third node, and the first electrode of the light-emitting element, respectively, and is used to control the connection between the third node and the first electrode of the light-emitting element under the control of the first light-emitting control signal provided by the first light-emitting control signal terminal; the second electrode of the light-emitting element is electrically connected to the first voltage terminal.

[0166] The second initialization circuit is electrically connected to the second initial control terminal, the second initial voltage terminal, and the first electrode of the light-emitting element, respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the first electrode of the light-emitting element under the control of the second initial control signal provided by the second initial control terminal.

[0167] In a specific implementation, the pixel circuit may further include a first light-emitting control circuit and a second initialization circuit. Under the control of a first light-emitting control signal, the first light-emitting control circuit controls the connection between the third node and the first electrode of the light-emitting element. Under the control of a second initial control signal, the second initialization circuit writes the second initial voltage into the first electrode of the light-emitting element.

[0168] Optionally, the first light emission control signal terminal can be the (n+b)th level first light emission control terminal, but is not limited thereto; n and b are both positive integers.

[0169] As shown in Figure 3B, based on at least one embodiment of the pixel circuit shown in Figure 1, the pixel circuit described in at least one embodiment of this disclosure may further include a first light-emitting control circuit 61 and a second initialization circuit 21.

[0170] The first light-emitting control circuit 61 is electrically connected to the (n+b)th level first light-emitting control terminal EM1(n+b), the third node N3, and the first electrode of the light-emitting element E1, respectively. Under the control of the (n+b)th level first light-emitting control signal provided by the (n+b)th level first light-emitting control terminal EM1(n+b), it controls the connection between the third node N3 and the first electrode of the light-emitting element E1; the second electrode of the light-emitting element E1 is electrically connected to the first voltage terminal V1.

[0171] The second initialization circuit 21 is electrically connected to the second initial control terminal TI2, the second initial voltage terminal I2 and the first electrode of the light-emitting element E1, respectively, and is used to write the second initial voltage Vi2 provided by the second initial voltage terminal I2 into the first electrode of the light-emitting element E1 under the control of the second initial control signal provided by the second initial control terminal TI2.

[0172] In at least one embodiment of the pixel circuit shown in FIG3B of this disclosure, the refresh frame may include an initialization phase during operation;

[0173] During the initialization phase, the second initialization circuit 21, under the control of the second initial control signal, writes the second initial voltage Vi2 into the first electrode of the light-emitting element E1. The first light-emitting control circuit 61, under the control of the (n+b)th level first light-emitting control signal, controls the connection between the third node N3 and the first electrode of the light-emitting element E1. The second control circuit 12, under the control of the second control signal, controls the connection between the fourth node N4 and the third node N3. The first control circuit 11, under the control of the first control signal, controls the connection between the first node N1 and the fourth node N4 to write the second initial voltage Vi2 into the first node N1.

[0174] In at least one embodiment of this disclosure, the pixel circuit further includes a voltage control circuit;

[0175] The voltage control circuit is electrically connected to the fourth node and the control voltage terminal respectively, and is used to control the potential of the fourth node according to the control voltage provided by the control voltage terminal; or,

[0176] The voltage control circuit is electrically connected to both the fourth node and the third node, and is used to control the potential of the fourth node according to the potential of the third node; or,

[0177] The pixel circuit further includes a light-emitting element and a first light-emitting control circuit. The voltage control circuit is electrically connected to the fourth node and the first light-emitting control signal terminal, respectively, and is used to control the potential of the fourth node according to the first light-emitting control signal provided by the first light-emitting control signal terminal.

[0178] In a specific implementation, the pixel circuit may further include a voltage control circuit;

[0179] The voltage control circuit changes the potential of the fourth node according to the control voltage to improve the leakage current phenomenon of the first node; or,

[0180] The voltage control circuit controls the potential of the fourth node based on the potential of the third node, so as to improve the leakage phenomenon of the first node.

[0181] When the pixel circuit described in at least one embodiment of this disclosure is in operation, and the voltage control circuit is electrically connected to the fourth node and the control voltage terminal respectively, for controlling the potential of the fourth node according to the control voltage provided by the control voltage terminal,

[0182] The refresh frame may include a first hysteresis improvement stage and a first light emission stage set sequentially. In the first voltage control stage between the first hysteresis improvement stage and the first light emission stage, the potential of the control voltage provided by the control voltage terminal decreases to correspondingly lower the potential of the fourth node, so that the voltage difference between the fourth node and the first node is smaller, thereby improving the leakage phenomenon of the first node.

[0183] The holding frame may include a second hysteresis improvement stage and a second light emission stage set sequentially. In the second voltage control stage between the second hysteresis improvement stage and the second light emission stage, the potential of the control voltage provided by the control voltage terminal decreases to correspondingly lower the potential of the fourth node, so that the voltage difference between the fourth node and the first node is smaller, thereby improving the leakage phenomenon of the first node.

[0184] In the first voltage control stage and the second voltage control stage, the potential of the control voltage can be pulled down by a large amount, but is not limited thereto.

[0185] When the pixel circuit described in at least one embodiment of this disclosure is in operation, and the voltage control circuit is electrically connected to the fourth node and the third node respectively, for controlling the potential of the fourth node according to the potential of the third node,

[0186] The refresh frame may include a first light emission stage set after the first hysteresis improvement stage; at the beginning of the first light emission stage, the voltage control circuit controls the potential of the fourth node to be lower according to the potential of the third node, so that the voltage difference between the fourth node and the first node is smaller, thereby improving the leakage phenomenon of the first node.

[0187] The holding frame may include a second light emission stage set after the second hysteresis improvement stage; at the beginning of the second light emission stage, the voltage control circuit controls the potential of the fourth node to decrease according to the potential of the third node, so that the voltage difference between the fourth node and the first node is smaller, thereby improving the leakage phenomenon of the first node.

[0188] As shown in Figure 4, based on at least one embodiment of the pixel circuit shown in Figure 2, the pixel circuit of at least one embodiment of this disclosure further includes a voltage control circuit 41;

[0189] The voltage control circuit 41 is electrically connected to the fourth node N4 and the control voltage terminal VJ respectively, and is used to control the potential of the fourth node N4 according to the control voltage Vj provided by the control voltage terminal VJ.

[0190] As shown in FIG5A, based on at least one embodiment of the pixel circuit shown in FIG3A, the pixel circuit of at least one embodiment of the present disclosure further includes a voltage control circuit 41;

[0191] The voltage control circuit 41 is electrically connected to the fourth node N4 and the control voltage terminal VJ respectively, and is used to control the potential of the fourth node N4 according to the control voltage Vj provided by the control voltage terminal VJ.

[0192] As shown in FIG5B, based on at least one embodiment of the pixel circuit shown in FIG3A, the pixel circuit of at least one embodiment of the present disclosure further includes a voltage control circuit 41;

[0193] The voltage control circuit 41 is electrically connected to the fourth node N4 and the third node N3 respectively, and is used to control the potential of the fourth node N4 according to the potential of the third node N3.

[0194] As shown in FIG5C, based on at least one embodiment of the pixel circuit shown in FIG3B, the pixel circuit of at least one embodiment of the present disclosure further includes a voltage control circuit 41;

[0195] The voltage control circuit 41 is electrically connected to the fourth node N4 and the third node N3 respectively, and is used to control the potential of the fourth node N4 according to the potential of the third node N3.

[0196] Optionally, the first control terminal is the nth level scan terminal, the second control terminal is the nth level gate drive terminal, the first initial control terminal is the n+yth level gate drive terminal, and the second initial voltage terminal is the nxth level scan terminal;

[0197] n, x, and y are all positive integers.

[0198] In practical implementation, the first driving module can provide the nth level scan signal to the first control terminal and the nxth level scan signal to the second initial voltage terminal. The second driving module can provide the nth level gate drive signal to the second control terminal and the n+yth level gate drive signal to the first initial control terminal, thereby reducing the number of driving modules used in the display device and facilitating the realization of a narrow bezel.

[0199] Optionally, the first control terminal is the nth level gate drive terminal, the second control terminal includes the nth level scan terminal and the n+yth level scan terminal, the first initial control terminal is the n+yth level scan terminal, and the second initial control terminal is the nxth level scan terminal;

[0200] n, x, and y are all positive integers.

[0201] In practical implementation, the first driving module can provide the nth level scan signal to the first second control terminal, the n+yth level scan signal to the first initial control terminal, and the nxth level scan signal to the second initial control terminal. The second driving module can provide the nth level gate drive signal to the first control terminal and the n+yth level scan signal to the second second control terminal, thereby reducing the number of driving modules used in the display device and facilitating the realization of a narrow bezel.

[0202] Optionally, the first control terminal includes an nth level scan terminal and an nxth level scan terminal, the second control terminal is an nth level gate drive terminal, the first initial control terminal is an n+yth level gate drive terminal, and the second initial control terminal is an nxth level scan terminal;

[0203] n, x, and y are all positive integers.

[0204] In practical implementation, the first driving module can provide the nth level scan signal to the first first control terminal, the nxth level scan signal to the second first control terminal, and the nxth level scan signal to the second initial control terminal. The second driving module can provide the nth level gate drive signal to the second control terminal and the n+yth level gate drive signal to the first initial control terminal, thereby reducing the number of driving modules used in the display device and facilitating the realization of a narrow bezel.

[0205] In at least one embodiment of this disclosure, x can be at least 1. For example, x can be an integer greater than or equal to 2, and y can be an integer greater than or equal to 2. Furthermore, considering factors such as the duty cycle of the signal and the convenience of wiring, the values ​​of x and y should generally not be greater than 20.

[0206] Optionally, the first control terminal is the nth level second light-emitting control terminal, the second control terminal is the nath level third light-emitting control terminal, the first initial control terminal is the nth level third light-emitting control terminal, and the second initial control terminal is the nbth level gate driving terminal.

[0207] n, a, and b are all positive integers.

[0208] Optionally, the first control terminal is the second light-emitting control terminal of the na-th stage, the second control terminal is the second light-emitting control terminal of the n-th stage, the first initial control terminal is the gate driving terminal of the n+b-th stage, and the second initial control terminal is the second light-emitting control terminal of the nc-th stage.

[0209] n, a, b, and c are all positive integers.

[0210] Optionally, the first control terminal is the second light-emitting control terminal of the nth stage, the second control terminal is the third light-emitting control terminal of the nath stage, the first initial control terminal is the third light-emitting control terminal of the nth stage, the first light-emitting control signal terminal is the first light-emitting control terminal of the n+bth stage, and the second initial control terminal is the gate driving terminal of the ncth stage.

[0211] n, a, b, and c are all positive integers.

[0212] In at least one embodiment of this disclosure, the first control circuit includes a first transistor, the second control circuit includes a second transistor, the first initialization circuit includes a third transistor, and the second initialization circuit includes a fourth transistor.

[0213] The gate of the first transistor is electrically connected to the nth scanning terminal, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the fourth node.

[0214] The gate of the second transistor is electrically connected to the nth gate drive terminal, the first terminal of the second transistor is electrically connected to the fourth node, and the second terminal of the second transistor is electrically connected to the third node.

[0215] The gate of the third transistor is electrically connected to the gate driving terminal of the (n+y)th stage, the first terminal of the third transistor is electrically connected to the first initial voltage terminal, and the second terminal of the third transistor is electrically connected to the fourth node.

[0216] The gate of the fourth transistor is electrically connected to the nx-th scanning terminal, the first terminal of the fourth transistor is electrically connected to the second initial voltage terminal, and the second terminal of the fourth transistor is electrically connected to the first node.

[0217] Optionally, the first control circuit includes a first transistor, the second control circuit includes a second transistor and a fifth transistor, the first initialization circuit includes a third transistor, and the second initialization circuit includes a fourth transistor.

[0218] The gate of the first transistor is electrically connected to the nth gate drive terminal, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the fourth node.

[0219] The gate of the second transistor is electrically connected to the nth scanning terminal, the first terminal of the second transistor is electrically connected to the fourth node, and the second terminal of the second transistor is electrically connected to the third node;

[0220] The gate of the fifth transistor is electrically connected to the (n+y)th scanning terminal, the first terminal of the fifth transistor is electrically connected to the fourth node, and the second terminal of the fifth transistor is electrically connected to the third node.

[0221] The gate of the third transistor is electrically connected to the (n+y)th scanning terminal, the first terminal of the third transistor is electrically connected to the first initial voltage terminal, and the second terminal of the third transistor is electrically connected to the fourth node.

[0222] The gate of the fourth transistor is electrically connected to the nx-th scanning terminal, the first terminal of the fourth transistor is electrically connected to the second initial voltage terminal, and the second terminal of the fourth transistor is electrically connected to the fourth node or the first node.

[0223] Optionally, the first control circuit includes a first transistor and a sixth transistor, the second control circuit includes a second transistor, the first initialization circuit includes a third transistor, and the second initialization circuit includes a fourth transistor.

[0224] The gate of the first transistor is electrically connected to the nxth scan terminal, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the fourth node.

[0225] The gate of the sixth transistor is electrically connected to the nth scanning terminal, the first terminal of the sixth transistor is electrically connected to the first node, and the second terminal of the sixth transistor is electrically connected to the fourth node.

[0226] The gate of the second transistor is electrically connected to the nth gate drive terminal, the first terminal of the second transistor is electrically connected to the fourth node, and the second terminal of the second transistor is electrically connected to the third node.

[0227] The gate of the third transistor is electrically connected to the gate scan terminal of the (n+y)th stage, the first terminal of the third transistor is electrically connected to the first initial voltage terminal, and the second terminal of the third transistor is electrically connected to the fourth node.

[0228] The gate of the fourth transistor is electrically connected to the nx-th scan terminal, the first terminal of the fourth transistor is electrically connected to the second initial voltage terminal, and the second terminal of the fourth transistor is electrically connected to the first node or the fourth node.

[0229] Optionally, the first control circuit includes a first transistor, the second control circuit includes a second transistor, and the first initialization circuit includes a third transistor.

[0230] The gate of the first transistor is electrically connected to the first control terminal, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the fourth node.

[0231] The gate of the second transistor is electrically connected to the second control terminal, the first terminal of the second transistor is electrically connected to the fourth node, and the second terminal of the second transistor is electrically connected to the third node.

[0232] The gate of the third transistor is electrically connected to the first initial control terminal, the first terminal of the third transistor is electrically connected to the first initial voltage terminal, and the second terminal of the third transistor is electrically connected to the fourth node or the third node.

[0233] Optionally, the first light-emitting control circuit includes an eighth transistor, and the second initialization circuit includes a fourth transistor;

[0234] The gate of the eighth transistor is electrically connected to the first light-emitting control signal terminal, the first electrode of the eighth transistor is electrically connected to the third node, and the second electrode of the eighth transistor is electrically connected to the first electrode of the light-emitting element.

[0235] The gate of the fourth transistor is electrically connected to the second initial control terminal, the first terminal of the fourth transistor is electrically connected to the second initial voltage terminal, and the second terminal of the fourth transistor is electrically connected to the first terminal of the light-emitting element.

[0236] Optionally, the voltage control circuit includes a first capacitor;

[0237] The first terminal of the first capacitor is electrically connected to the fourth node, and the second terminal of the first capacitor is electrically connected to the control voltage terminal; or...

[0238] The first terminal of the first capacitor is electrically connected to the fourth node, and the second terminal of the first capacitor is electrically connected to the third node; or...

[0239] The first end of the first capacitor is electrically connected to the fourth node, and the second end of the first capacitor is electrically connected to the first light-emitting control signal terminal.

[0240] The pixel circuit described in at least one embodiment of this disclosure further includes a light-emitting element, a first light-emitting control circuit, a second light-emitting control circuit, a data writing circuit, and an energy storage circuit;

[0241] The first light-emitting control circuit is electrically connected to the light-emitting control terminal, the third node, and the first electrode of the light-emitting element, respectively, and is used to control the connection between the third node and the first electrode of the light-emitting element under the control of the light-emitting control signal provided by the light-emitting control terminal; the second electrode of the light-emitting element is electrically connected to the first voltage terminal.

[0242] The second light-emitting control circuit is electrically connected to the light-emitting control terminal, the power supply voltage terminal, and the second node, respectively, and is used to control the connection between the power supply voltage terminal and the second node under the control of the light-emitting control signal;

[0243] The data writing circuit is electrically connected to the nth level scanning terminal, the data line, and the second node, respectively, and is used to write the data voltage provided by the data line into the second node under the control of the nth level scanning signal provided by the nth level scanning terminal; n is a positive integer;

[0244] The first end of the energy storage circuit is electrically connected to the first node, and the second end of the energy storage circuit is electrically connected to the DC voltage terminal. The energy storage circuit is used to store electrical energy.

[0245] In a specific implementation, the pixel circuit may further include a light-emitting element, a first light-emitting control circuit, a second light-emitting control circuit, a data writing circuit, and an energy storage circuit; the second light-emitting control circuit, under the control of the light-emitting control signal, controls the connection between the power supply voltage terminal and the second node; the first light-emitting control circuit, under the control of the light-emitting control signal, controls the connection between the third node and the first electrode of the light-emitting element; the data writing circuit, under the control of the nth level scan signal, writes the data voltage provided by the data line into the second node; the energy storage circuit maintains the potential of the first node.

[0246] Optionally, the first voltage terminal can be a low voltage terminal, and the DC voltage terminal can be a power supply voltage terminal, but this is not a limitation.

[0247] The pixel circuit described in at least one embodiment of this disclosure may further include a voltage control circuit; the voltage control circuit includes a first capacitor, a first terminal of which is electrically connected to the fourth node, and a second terminal of which is electrically connected to the control voltage terminal; the energy storage circuit includes a storage capacitor; a first terminal of which is electrically connected to the first node, and a second terminal of which is electrically connected to the DC voltage terminal;

[0248] The capacitance value of the first capacitor is less than or equal to 1 / 5 of the capacitance value of the storage capacitor, and the capacitance value of the first capacitor is greater than or equal to 1fF.

[0249] In at least one embodiment of this disclosure, considering that if the equivalent capacitance value of the fourth node is too large, it will affect the compensation speed of the driving transistor, the capacitance value of the first capacitor should be less than or equal to 1 / 5 of the capacitance value of the storage capacitor. Furthermore, considering that when the potential of the control voltage provided by the control voltage terminal decreases, the potential of the fourth node needs to have a large pull-down amount, the capacitance value of the first capacitor should be greater than or equal to 1fF.

[0250] The pixel circuit described in at least one embodiment of this disclosure further includes a light-emitting element, a second light-emitting control circuit, a data writing circuit, and an energy storage circuit;

[0251] The second light-emitting control circuit is electrically connected to the second light-emitting control signal terminal, the power supply voltage terminal, and the second node, respectively, and is used to control the connection between the power supply voltage terminal and the second node under the control of the second light-emitting control signal provided by the second light-emitting control signal terminal;

[0252] The data writing circuit is electrically connected to the nth-level gate driving terminal, the data line, and the second node, respectively, and is used to write the data voltage provided by the data line into the second node under the control of the nth-level gate driving signal provided by the nth-level gate driving terminal; n is a positive integer;

[0253] The first end of the energy storage circuit is electrically connected to the first node, and the second end of the energy storage circuit is electrically connected to the DC voltage terminal. The energy storage circuit is used to store electrical energy.

[0254] Optionally, the second light emission control signal terminal can be the nth level first light emission control terminal, but is not limited thereto; n is a positive integer.

[0255] In at least one embodiment of this disclosure, the pixel circuit may further include a voltage control circuit; the voltage control circuit includes a first capacitor, a first terminal of which is electrically connected to the fourth node, and a second terminal of which is electrically connected to the third node; the energy storage circuit includes a storage capacitor; a first terminal of which is electrically connected to the first node, and a second terminal of which is electrically connected to a DC voltage terminal.

[0256] The capacitance value of the first capacitor is less than or equal to 1 / 5 of the capacitance value of the storage capacitor, and the capacitance value of the first capacitor is greater than or equal to 1fF.

[0257] In at least one embodiment of this disclosure, considering that if the equivalent capacitance value of the fourth node is too large, it will affect the compensation speed of the driving transistor, the capacitance value of the first capacitor should be less than or equal to 1 / 5 of the capacitance value of the storage capacitor. Furthermore, considering that when the potential of the third node decreases, the potential of the fourth node needs to be pulled down by a large amount, the capacitance value of the first capacitor should be greater than or equal to 1fF.

[0258] In at least one embodiment of this disclosure, the pixel circuit further includes a third initialization circuit;

[0259] The third initialization circuit is electrically connected to the third initial control terminal, the third initial voltage terminal, and the first electrode of the light-emitting element, respectively, and is used to write the third initial voltage provided by the third initial voltage terminal into the first electrode of the light-emitting element under the control of the third initial control signal provided by the third initial control terminal.

[0260] In a specific implementation, the pixel circuit may further include a third initialization circuit, which, under the control of the third initial control signal, writes the third initial voltage into the first electrode of the light-emitting element to clear the residual charge on the first electrode of the light-emitting element.

[0261] As shown in Figure 6, based on at least one embodiment of the pixel circuit shown in Figure 4, the pixel circuit described in at least one embodiment of this disclosure further includes a light-emitting element E1, a first light-emitting control circuit 61, a second light-emitting control circuit 62, a data writing circuit 63, an energy storage circuit 60, and a third initialization circuit 64.

[0262] The first light-emitting control circuit 61 is electrically connected to the light-emitting control terminal EM. The third node N3 is electrically connected to the first pole of the light-emitting element E1, and is used to control the connection between the third node N3 and the first pole of the light-emitting element E1 under the control of the light-emitting control signal. The second pole of the light-emitting element E1 is electrically connected to the first voltage terminal V1.

[0263] The second light-emitting control circuit 62 is electrically connected to the light-emitting control terminal EM, the power supply voltage terminal ELVDD, and the second node N2, respectively, and is used to control the connection between the power supply voltage terminal ELVDD and the second node N2 under the control of the light-emitting control signal provided by the light-emitting control terminal EM.

[0264] The data writing circuit 63 is electrically connected to the nth level scanning terminal S(n), the data line DT, and the second node N2, respectively, and is used to write the data voltage provided by the data line DT into the second node under the control of the nth level scanning signal provided by the nth level scanning terminal S(n); n is a positive integer;

[0265] The first terminal of the energy storage circuit 60 is electrically connected to the first node N1, and the second terminal of the energy storage circuit 60 is electrically connected to the power supply voltage terminal ELVDD. The energy storage circuit 60 is used to store electrical energy.

[0266] The third initialization circuit 64 is electrically connected to the third initial control terminal TI3, the third initial voltage terminal I3, and the first electrode of the light-emitting element E1, respectively, and is used to write the third initial voltage Vi3 provided by the third initial voltage terminal I3 into the first electrode of the light-emitting element E1 under the control of the third initial control signal provided by the third initial control terminal TI3.

[0267] As shown in FIG7A, based on at least one embodiment of the pixel circuit shown in FIG5A, the pixel circuit described in at least one embodiment of the present disclosure further includes a light-emitting element E1, a first light-emitting control circuit 61, a second light-emitting control circuit 62, a data writing circuit 63, an energy storage circuit 60, and a third initialization circuit 64.

[0268] The first light-emitting control circuit 61 is electrically connected to the light-emitting control terminal EM. The third node N3 is electrically connected to the first pole of the light-emitting element E1, and is used to control the connection between the third node N3 and the first pole of the light-emitting element E1 under the control of the light-emitting control signal. The second pole of the light-emitting element E1 is electrically connected to the first voltage terminal V1.

[0269] The second light-emitting control circuit 62 is electrically connected to the light-emitting control terminal EM, the power supply voltage terminal ELVDD, and the second node N2, respectively, and is used to control the connection between the power supply voltage terminal ELVDD and the second node N2 under the control of the light-emitting control signal provided by the light-emitting control terminal EM.

[0270] The data writing circuit 63 is electrically connected to the nth level scanning terminal S(n), the data line DT, and the second node N2, respectively, and is used to write the data voltage provided by the data line DT into the second node under the control of the nth level scanning signal provided by the nth level scanning terminal S(n); n is a positive integer;

[0271] The first terminal of the energy storage circuit 60 is electrically connected to the first node N1, and the second terminal of the energy storage circuit 60 is electrically connected to the power supply voltage terminal ELVDD. The energy storage circuit 60 is used to store electrical energy.

[0272] The third initialization circuit 64 is electrically connected to the third initial control terminal TI3, the third initial voltage terminal I3, and the first electrode of the light-emitting element E1, respectively, and is used to write the third initial voltage Vi3 provided by the third initial voltage terminal I3 into the first electrode of the light-emitting element E1 under the control of the third initial control signal provided by the third initial control terminal TI3.

[0273] As shown in FIG7B, based on at least one embodiment of the pixel circuit shown in FIG5B, the pixel circuit described in at least one embodiment of the present disclosure further includes a light-emitting element E1, a first light-emitting control circuit 61, a second light-emitting control circuit 62, a data writing circuit 63, an energy storage circuit 60, and a third initialization circuit 64.

[0274] The first light-emitting control circuit 61 is electrically connected to the light-emitting control terminal EM. The third node N3 is electrically connected to the first pole of the light-emitting element E1, and is used to control the connection between the third node N3 and the first pole of the light-emitting element E1 under the control of the light-emitting control signal. The second pole of the light-emitting element E1 is electrically connected to the first voltage terminal V1.

[0275] The second light-emitting control circuit 62 is electrically connected to the light-emitting control terminal EM, the power supply voltage terminal ELVDD, and the second node N2, respectively, and is used to control the connection between the power supply voltage terminal ELVDD and the second node N2 under the control of the light-emitting control signal provided by the light-emitting control terminal EM.

[0276] The data writing circuit 63 is electrically connected to the nth gate driving terminal G(n), the data line DT, and the second node N2, respectively, and is used to write the data voltage provided by the data line DT into the second node under the control of the nth gate driving signal provided by the nth gate driving terminal G(n); n is a positive integer.

[0277] The first terminal of the energy storage circuit 60 is electrically connected to the first node N1, and the second terminal of the energy storage circuit 60 is electrically connected to the power supply voltage terminal ELVDD. The energy storage circuit 60 is used to store electrical energy.

[0278] The third initialization circuit 64 is electrically connected to the third initial control terminal TI3, the third initial voltage terminal I3, and the first electrode of the light-emitting element E1, respectively, and is used to write the third initial voltage Vi3 provided by the third initial voltage terminal I3 into the first electrode of the light-emitting element E1 under the control of the third initial control signal provided by the third initial control terminal TI3.

[0279] As shown in FIG7C, in at least one embodiment of the pixel circuit shown in FIG3B, the pixel circuit of at least one embodiment of the present disclosure further includes a light-emitting element E1, a second light-emitting control circuit 62, a data writing circuit 63, an energy storage circuit 60, and a third initialization circuit 64.

[0280] The second light-emitting control circuit 62 is electrically connected to the nth-level first light-emitting control terminal EM1(n), the power supply voltage terminal ELVDD, and the second node N2, respectively, and is used to control the connection between the power supply voltage terminal ELVDD and the second node N2 under the control of the nth-level first light-emitting control signal provided by the nth-level first light-emitting control terminal EM1(n);

[0281] The data writing circuit 63 is electrically connected to the nth gate driving terminal G(n), the data line DT and the second node N2 respectively, and is used to write the data voltage Vdata provided by the data line DT into the second node N2 under the control of the nth gate driving signal provided by the nth gate driving terminal G(n); n is a positive integer;

[0282] The first terminal of the energy storage circuit 60 is electrically connected to the first node N1, and the second terminal of the energy storage circuit 60 is electrically connected to the power supply voltage terminal ELVDD. The energy storage circuit 60 is used to store electrical energy.

[0283] The third initialization circuit 64 is electrically connected to the third initial control terminal TI3, the third initial voltage terminal I3, and the first electrode of the light-emitting element E1, respectively, and is used to write the third initial voltage Vi3 provided by the third initial voltage terminal I3 into the first electrode of the light-emitting element E1 under the control of the third initial control signal provided by the third initial control terminal TI3.

[0284] The differences between at least one embodiment of the pixel circuit shown in Figure 7D and at least one embodiment of the pixel circuit shown in Figure 7C are as follows:

[0285] The second initialization circuit 21 is not electrically connected to the first electrode of the light-emitting element E1, and the second initialization circuit 21 is electrically connected to the third node N3;

[0286] The second initialization circuit 21 is used to write the second initial voltage Vi2 provided by the second initial voltage terminal I2 into the third node N3 under the control of the second initial control signal provided by the second initial control terminal TI2.

[0287] Optionally, the second light-emitting control circuit includes a seventh transistor, the first light-emitting control circuit includes an eighth transistor, the data writing circuit includes a ninth transistor, and the energy storage circuit includes a storage capacitor.

[0288] The gate of the seventh transistor is electrically connected to the light-emitting control terminal, the first terminal of the seventh transistor is electrically connected to the power supply voltage terminal, and the second terminal of the seventh transistor is electrically connected to the second node.

[0289] The gate of the eighth transistor is electrically connected to the light-emitting control terminal, the first terminal of the eighth transistor is electrically connected to the third node, and the second terminal of the eighth transistor is electrically connected to the first terminal of the light-emitting element.

[0290] The gate of the ninth transistor is electrically connected to the nth scanning terminal, the first terminal of the ninth transistor is electrically connected to the data line, and the second terminal of the ninth transistor is electrically connected to the second node.

[0291] The first end of the storage capacitor is electrically connected to the first node, and the second end of the storage capacitor is electrically connected to the DC voltage terminal.

[0292] Optionally, the second light-emitting control circuit includes a seventh transistor; the data writing circuit includes a ninth transistor; and the energy storage circuit includes a storage capacitor.

[0293] The gate of the seventh transistor is electrically connected to the second light-emitting control signal terminal, the first terminal of the seventh transistor is electrically connected to the power supply voltage terminal, and the second terminal of the seventh transistor is electrically connected to the second node.

[0294] The gate of the ninth transistor is electrically connected to the nth gate driving terminal, the first terminal of the ninth transistor is electrically connected to the data line, and the second terminal of the ninth transistor is electrically connected to the second node.

[0295] The first end of the storage capacitor is electrically connected to the first node, and the second end of the storage capacitor is electrically connected to the DC voltage terminal.

[0296] Optionally, the third initialization circuit includes a tenth transistor;

[0297] The gate of the tenth transistor is electrically connected to the third initial control terminal, the first terminal of the tenth transistor is electrically connected to the third initial voltage terminal, and the second terminal of the tenth transistor is electrically connected to the first terminal of the light-emitting element.

[0298] Optionally, the light-emitting element may be an organic light-emitting diode, but is not limited thereto; in specific implementations, the light-emitting element may be other types of light-emitting diodes.

[0299] As shown in Figure 8, based on at least one embodiment of the pixel circuit shown in Figure 6, the first control circuit includes a first transistor T1, the second control circuit includes a second transistor T2, the first initialization circuit includes a third transistor T3, and the second initialization circuit includes a fourth transistor T4; the light-emitting element is an organic light-emitting diode O1; and the driving circuit includes a driving transistor T0.

[0300] The gate of the driving transistor T0 is electrically connected to the first node N1, the source of the driving transistor T0 is electrically connected to the second node N2, and the drain of the driving transistor T0 is electrically connected to the third node N3.

[0301] The gate of the first transistor T1 is electrically connected to the nth scanning terminal S(n), the source of the first transistor T1 is electrically connected to the first node N1, and the drain of the first transistor T1 is electrically connected to the fourth node N4.

[0302] The gate of the second transistor T2 is electrically connected to the nth gate drive terminal G(n), the source of the second transistor T2 is electrically connected to the fourth node N4, and the drain of the second transistor T2 is electrically connected to the third node N3.

[0303] The gate of the third transistor T3 is electrically connected to the gate driving terminal G(n+y) of the (n+y)th stage, the source of the third transistor T3 is electrically connected to the first initial voltage terminal I1, and the drain of the third transistor T3 is electrically connected to the fourth node N4; the first initial voltage terminal I1 is used to provide the first initial voltage Vi1.

[0304] The gate of the fourth transistor T4 is electrically connected to the nx-th scan terminal S(nx), the source of the fourth transistor T4 is electrically connected to the second initial voltage terminal I2, and the drain of the fourth transistor T4 is electrically connected to the first node N1; the second initial voltage terminal I2 is used to provide the second initial voltage Vi2;

[0305] The voltage control circuit includes a first capacitor C1;

[0306] The first terminal of the first capacitor C1 is electrically connected to the fourth node N4, and the second terminal of the first capacitor C1 is electrically connected to the control voltage terminal VJ.

[0307] The second light-emitting control circuit includes a seventh transistor T7, and the first light-emitting control circuit includes an eighth transistor T8; the data writing circuit includes a ninth transistor T9; the energy storage circuit includes a storage capacitor Cst.

[0308] The gate of the seventh transistor T7 is electrically connected to the nth light-emitting control terminal EM(n), the source of the seventh transistor T7 is electrically connected to the power supply voltage terminal ELVDD, and the drain of the seventh transistor T7 is electrically connected to the second node N2.

[0309] The gate of the eighth transistor T8 is electrically connected to the nth stage light-emitting control terminal EM(n), the source of the eighth transistor T8 is electrically connected to the third node N3, the drain of the eighth transistor T8 is electrically connected to the anode of the organic light-emitting diode O1, and the cathode of O1 is electrically connected to the low voltage terminal ELVSS.

[0310] The gate of the ninth transistor T9 is electrically connected to the nth scanning terminal S(n), the source of the ninth transistor T9 is electrically connected to the data line DT, and the drain of the ninth transistor T9 is electrically connected to the second node N2.

[0311] The first terminal of the storage capacitor Cst is electrically connected to the first node N1, and the second terminal of the storage capacitor Cst is electrically connected to the power supply voltage terminal ELVDD.

[0312] The third initialization circuit includes a tenth transistor T10;

[0313] The gate of the tenth transistor T10 is electrically connected to the gate driving terminal G(n+y) of the n+y stage, the source of the tenth transistor T10 is electrically connected to the third initial voltage terminal I3, and the drain of the tenth transistor T10 is electrically connected to the anode of the organic light-emitting diode O1.

[0314] In at least one embodiment of the pixel circuit shown in Figure 8, the light emission control terminal can be the nth level light emission control terminal.

[0315] In at least one embodiment of the pixel circuit shown in Figure 8, all transistors are p-type transistors, but this is not a limitation.

[0316] In at least one embodiment of the pixel circuit shown in Figure 8, the second end of C1 can be electrically connected to N3, or the second end of C1 can be electrically connected to EM(n).

[0317] In at least one embodiment of the pixel circuit shown in Figure 8, T4 is controlled by S(nx), T1 and T9 are controlled by S(n), T3 and T10 are controlled by G(n+y), T2 is controlled by G(n), T7 and T8 are controlled by EM(n), scan signals are provided to S(nx) and S(n) through the same GOA module, and gate drive signals are provided to G(n+y) and G(n) through the same GOA module, so as to reduce the number of GOA modules used.

[0318] As shown in FIG9, in at least one embodiment of the pixel circuit shown in FIG8 of this disclosure, the refresh frame FX may include an initialization stage t11, a compensation stage t12, a first hysteresis improvement stage t13, a first voltage control stage t10, and a first light emission stage t14, which are set sequentially.

[0319] During the initialization phase t11, EM(n) provides a high voltage signal, G(n) provides a low voltage signal, S(nx) provides a low voltage signal, S(n) provides a high voltage signal, G(n+y) provides a high voltage signal, T4 is turned on, and I2 provides a second initial voltage Vi2 to the first node N1 so that T0 can be turned on at the start of the compensation phase t2.

[0320] During the compensation phase t12, EM(n) provides a high voltage signal, G(n) provides a low voltage signal, S(nx) provides a high voltage signal, S(n) provides a low voltage signal, G(n+y) provides a high voltage signal, T9 is turned on, DT provides the data voltage Vdata to the second node N2, T1 and T2 are turned on, and N1 and N3 are connected.

[0321] At the start of the compensation phase t12, T0 is turned on, and Vdata charges Cst through T9, T0, T2 and T1, changing the potential of N1 until the potential of N1 becomes Vdata+Vth, then T0 is turned off, and Vth is the threshold voltage of T0.

[0322] In the first hysteresis improvement stage t13, EM(n) provides a high voltage signal, G(n) provides a low voltage signal, S(nx) provides a high voltage signal, S(n+y) provides a high voltage signal, G(n+y) provides a low voltage signal, T3 is turned on, T2 is turned on, and I1 provides the first initial voltage Vi1 to the third node N3 to improve the hysteresis phenomenon of T0.

[0323] In the first hysteresis improvement stage t13, T0 is turned on to write Vi1 to the second node N2, thereby improving the hysteresis phenomenon of T0.

[0324] In the first hysteresis improvement stage t13, T10 is turned on, and I3 provides a third initial voltage Vi3 to the anode of O1 to clear the residual charge on the anode of O1;

[0325] In the first voltage control stage t10, the potential of the control voltage provided by VJ decreases to control the potential decrease of N4, reduce the voltage difference between N1 and N4, improve the leakage phenomenon of N1, and improve the flicker phenomenon.

[0326] In the first light-emitting stage t14, EM(n) provides a low voltage signal, G(n) provides a high voltage signal, S(nx) provides a high voltage signal, S(n) provides a high voltage signal, G(n+y) provides a high voltage signal, T7 and T8 are turned on, and T0 drives O1 to emit light.

[0327] In at least one embodiment shown in Figure 8, T4 and T1 can be dual-gate transistors, but are not limited thereto.

[0328] As shown in FIG10, when at least one embodiment of the pixel circuit shown in FIG8 of this disclosure is in operation, the holding frame FB may include a second hysteresis improvement stage t23, a second voltage control stage t20 and a second light emission stage t24 set sequentially.

[0329] In the second hysteresis improvement stage t23, EM(n) provides a high voltage signal, G(n) provides a low voltage signal, S(nx) provides a high voltage signal, S(n+y) provides a high voltage signal, G(n+y) provides a low voltage signal, T3 is turned on, T2 is turned on, and I1 provides the first initial voltage Vi1 to the third node N3 to improve the hysteresis phenomenon of T0 and improve the afterimage.

[0330] In the second hysteresis improvement stage t23, T0 is turned on to write Vi1 to the second node N2, thereby improving the hysteresis phenomenon of T0.

[0331] In the second hysteresis improvement stage t23, T10 is turned on, and I3 provides a third initial voltage Vi3 to the anode of O1 to remove the residual charge on the anode of O1;

[0332] In the second voltage control stage t20, the potential of the control voltage provided by VJ decreases to control the potential decrease of N4, reduce the voltage difference between N1 and N4, improve the leakage phenomenon of N1, and improve the flicker phenomenon.

[0333] In the second light-emitting stage t24, EM(n) provides a low voltage signal, G(n) provides a high voltage signal, S(nx) provides a high voltage signal, S(n) provides a high voltage signal, G(n+y) provides a high voltage signal, T7 and T8 are turned on, and T0 drives O1 to emit light.

[0334] In at least one embodiment of the pixel circuit shown in FIG8 of this disclosure, during operation, in the second voltage supply stage, or at the instant at the start of the light emission stage, the potential of the control voltage Vj supplied by the control voltage terminal VJ is pulled down to a large extent and is relatively stable in the light emission stage.

[0335] Considering that if the equivalent capacitance of the fourth node N4 is too large, it will affect the compensation speed of the driving transistor T0, the capacitance of C1 should be less than or equal to 1 / 5 of the capacitance of the storage capacitor Cst. Furthermore, considering that when the potential of Vj decreases, the potential of N4 needs to be pulled down by a large amount, the capacitance of C1 should be greater than or equal to 1fF.

[0336] The pixel circuit described in at least one embodiment of this disclosure can operate normally without increasing the number of GOA (Gate On Array) modules, and supports high-precision frequency conversion, image retention improvement, and low-frequency display.

[0337] As shown in Figure 11, based on at least one embodiment of the pixel circuit shown in Figure 7A, the first control circuit includes a first transistor T1, the second control circuit includes a second transistor T2 and a fifth transistor T5, the first initialization circuit includes a third transistor T3, the second initialization circuit includes a fourth transistor T4; the driving circuit includes a driving transistor T0, the light-emitting element includes an organic light-emitting diode O1; and the voltage control circuit includes a first capacitor C1.

[0338] The first terminal of the first capacitor C1 is electrically connected to the fourth node N4, and the second terminal of the first capacitor C1 is electrically connected to the control voltage terminal VJ.

[0339] The gate of T0 is electrically connected to the first node N1, the source of T0 is electrically connected to the second node N2, and the drain of T0 is electrically connected to the third node N3.

[0340] The gate of the first transistor T1 is electrically connected to the nth gate driving terminal G(n), the source of the first transistor T1 is electrically connected to the first node N1, and the drain of the first transistor T1 is electrically connected to the fourth node N4.

[0341] The gate of the second transistor T2 is electrically connected to the nth scanning terminal S(n), the source of the second transistor T2 is electrically connected to the fourth node N4, and the drain of the second transistor T2 is electrically connected to the third node N3.

[0342] The gate of the fifth transistor T5 is electrically connected to the (n+y)th scanning terminal S(n+y), the source of the fifth transistor T5 is electrically connected to the fourth node N4, and the drain of the fifth transistor T5 is electrically connected to the third node N3.

[0343] The gate of the third transistor T3 is electrically connected to the (n+y)th scanning terminal S(n+y), the source of the third transistor T3 is electrically connected to the first initial voltage terminal I1, and the drain of the third transistor T3 is electrically connected to the fourth node N4.

[0344] The gate of the fourth transistor T4 is electrically connected to the nx-th scan terminal S(nx), the source of the fourth transistor T4 is electrically connected to the second initial voltage terminal I2, and the drain of the fourth transistor T4 is electrically connected to the fourth node N4.

[0345] The second light-emitting control circuit includes a seventh transistor T7, and the first light-emitting control circuit includes an eighth transistor T8; the data writing circuit includes a ninth transistor T9; the energy storage circuit includes a storage capacitor Cst.

[0346] The gate of the seventh transistor T7 is electrically connected to the nth stage light-emitting control terminal EM(n), the source of the seventh transistor T7 is electrically connected to the power supply voltage terminal ELVDD, and the drain of the seventh transistor T7 is electrically connected to the second node N2.

[0347] The gate of the eighth transistor T8 is electrically connected to the nth stage light-emitting control terminal EM(n), the source of the eighth transistor T8 is electrically connected to the third node N3, the drain of the eighth transistor T8 is electrically connected to the anode of the organic light-emitting diode O1, and the cathode of O1 is electrically connected to the low voltage terminal ELVSS.

[0348] The gate of the ninth transistor T9 is electrically connected to the nth scanning terminal S(n), the source of the ninth transistor T9 is electrically connected to the data line DT, and the drain of the ninth transistor T9 is electrically connected to the second node N2.

[0349] The first terminal of the storage capacitor Cst is electrically connected to the first node N1, and the second terminal of the storage capacitor Cst is electrically connected to the power supply voltage terminal ELVDD.

[0350] The third initialization circuit includes a tenth transistor T10;

[0351] The gate of the tenth transistor T10 is electrically connected to the nth scanning terminal S(n), the source of the tenth transistor T10 is electrically connected to the third initial voltage terminal I3, and the drain of the tenth transistor T10 is electrically connected to the anode of the organic light-emitting diode O1.

[0352] In at least one embodiment of the pixel circuit shown in Figure 11, all transistors are p-type transistors, but this is not a limitation.

[0353] In at least one embodiment of the pixel circuit shown in Figure 11, the second end of C1 can be electrically connected to N3, or the second end of C1 can be electrically connected to EM(n).

[0354] In at least one embodiment of the pixel circuit shown in Figure 11, T3 and T5 are controlled by S(n+y), T2, T9 and T10 are controlled by S(n), T4 is controlled by S(nx), and T7 and T8 are controlled by EM(n). The same GOA module can provide scanning signals for S(n+y), S(n) and S(nx), thereby reducing the number of GOA modules used.

[0355] As shown in FIG12, when at least one embodiment of the pixel circuit shown in FIG11 of this disclosure is in operation, the refresh frame FX may include an initialization stage t11, a compensation stage t12, a first hysteresis improvement stage t13, a first voltage control stage t10, and a first light emission stage t14 set sequentially.

[0356] During the initialization phase t11, EM(n) provides a high voltage signal, G(n) provides a low voltage signal, S(nx) provides a low voltage signal, S(n) provides a high voltage signal, S(n+y) provides a high voltage signal, T4 and T1 are turned on, and I2 provides a second initial voltage Vi2 to the first node N1 so that T0 can be turned on at the beginning of the compensation phase t12.

[0357] During the compensation phase t12, EM(n) provides a high voltage signal, G(n) provides a low voltage signal, S(nx) provides a high voltage signal, S(n) provides a low voltage signal, S(n+y) provides a high voltage signal, T1 is turned on, T2 is turned on, T9 is turned on, T10 is turned on, DT provides the data voltage Vdata to the second node N2, and I3 provides the third initial voltage Vi3 to the anode of O1 to clear the residual charge on the anode of O1.

[0358] At the start of the compensation phase t12, T0 is turned on, and Vdata charges Cst through T9, T0, T2 and T1, changing the potential of N1 until the potential of N1 becomes Vdata+Vth, then T0 is turned off, and Vth is the threshold voltage of T0.

[0359] In the first hysteresis improvement stage t13, EM(n) provides a high voltage signal, G(n) provides a high voltage signal, S(nx) provides a high voltage signal, S(n+y) provides a low voltage signal, T3 is turned on, T5 is turned on, I1 provides the first initial voltage Vi1 to the third node N3, T0 is turned on, Vi is written to the second node N2, improving the hysteresis phenomenon of T0 and improving the afterimage;

[0360] In the first voltage control stage t10, the potential of the control voltage provided by VJ decreases to control the potential decrease of N4, reduce the voltage difference between N1 and N4, improve the leakage phenomenon of N1, and improve the flicker phenomenon.

[0361] In the first luminescence stage t14, EM(n) provides a low voltage signal, T7 and T8 are turned on, and T0 drives O1 to emit light.

[0362] As shown in FIG13, when at least one embodiment of the pixel circuit shown in FIG11 of this disclosure is in operation, the holding frame FB may include a second hysteresis improvement stage t23, a second voltage control stage t20 and a second light emission stage t24 set sequentially.

[0363] In the second hysteresis improvement stage t23, EM(n) provides a high voltage signal, G(n) provides a high voltage signal, S(nx) provides a high voltage signal, S(n+y) provides a low voltage signal, T3 and T5 are turned on, I1 provides the first initial voltage Vi1 to the third node N3, T0 is turned on, Vi1 is written to the second node N2, improving the hysteresis phenomenon of T0 and improving the afterimage;

[0364] In the second voltage control stage t20, the potential of the control voltage provided by VJ decreases to control the potential decrease of N4, reduce the voltage difference between N1 and N4, improve the leakage phenomenon of N1, and improve the flicker phenomenon.

[0365] In the second luminescence stage t24, EM(n) provides a low voltage signal, T7 and T8 are turned on, and T0 drives O1 to emit light.

[0366] As shown in Figure 14, based on at least one embodiment of the pixel circuit shown in Figure 6, the first control circuit includes a first transistor T1, the second control circuit includes a second transistor T2 and a fifth transistor T5, the first initialization circuit includes a third transistor T3, the second initialization circuit includes a fourth transistor T4; the driving circuit includes a driving transistor T0, the light-emitting element includes an organic light-emitting diode O1; and the voltage control circuit includes a first capacitor C1.

[0367] The gate of T0 is electrically connected to the first node N1, the source of T0 is electrically connected to the second node N2, and the drain of T0 is electrically connected to the third node N3.

[0368] The first terminal of the first capacitor C1 is electrically connected to the fourth node N4, and the second terminal of the first capacitor C1 is electrically connected to the control voltage terminal VJ.

[0369] The gate of the first transistor T1 is electrically connected to the nth gate driving terminal G(n), the source of the first transistor T1 is electrically connected to the first node N1, and the drain of the first transistor T1 is electrically connected to the fourth node N4.

[0370] The gate of the second transistor T2 is electrically connected to the nth scanning terminal S(n), the source of the second transistor T2 is electrically connected to the fourth node N4, and the drain of the second transistor T2 is electrically connected to the third node N3.

[0371] The gate of the fifth transistor T5 is electrically connected to the (n+y)th scanning terminal S(n+y), the source of the fifth transistor T5 is electrically connected to the fourth node N4, and the drain of the fifth transistor T5 is electrically connected to the third node N3.

[0372] The gate of the third transistor T3 is electrically connected to the (n+y)th scanning terminal S(n+y), the source of the third transistor T3 is electrically connected to the first initial voltage terminal I1, and the drain of the third transistor T3 is electrically connected to the fourth node N4.

[0373] The gate of the fourth transistor T4 is electrically connected to the nx-th gate drive terminal G(nx), the source of the fourth transistor T4 is electrically connected to the second initial voltage terminal I2, and the drain of the fourth transistor T4 is electrically connected to the fourth node N4.

[0374] The second light-emitting control circuit includes a seventh transistor T7, and the first light-emitting control circuit includes an eighth transistor T8; the data writing circuit includes a ninth transistor T9; the energy storage circuit includes a storage capacitor Cst.

[0375] The gate of the seventh transistor T7 is electrically connected to the nth stage light-emitting control terminal EM(n), the source of the seventh transistor T7 is electrically connected to the power supply voltage terminal ELVDD, and the drain of the seventh transistor T7 is electrically connected to the second node N2.

[0376] The gate of the eighth transistor T8 is electrically connected to the nth stage light-emitting control terminal EM(n), the source of the eighth transistor T8 is electrically connected to the third node N3, the drain of the eighth transistor T8 is electrically connected to the anode of the organic light-emitting diode O1, and the cathode of O1 is electrically connected to the low voltage terminal ELVSS.

[0377] The gate of the ninth transistor T9 is electrically connected to the nth scanning terminal S(n), the source of the ninth transistor T9 is electrically connected to the data line DT, and the drain of the ninth transistor T9 is electrically connected to the second node N2.

[0378] The first terminal of the storage capacitor Cst is electrically connected to the first node N1, and the second terminal of the storage capacitor Cst is electrically connected to the power supply voltage terminal ELVDD.

[0379] The third initialization circuit includes a tenth transistor T10;

[0380] The gate of the tenth transistor T10 is electrically connected to the nth scanning terminal S(n), the source of the tenth transistor T10 is electrically connected to the third initial voltage terminal I3, and the drain of the tenth transistor T10 is electrically connected to the anode of the organic light-emitting diode O1.

[0381] In at least one embodiment of the pixel circuit shown in Figure 14, all transistors are p-type transistors, but this is not a limitation.

[0382] In at least one embodiment of the pixel circuit shown in Figure 14, the second end of C1 can be electrically connected to N3, or the second end of C1 can be electrically connected to EM(n).

[0383] In at least one embodiment of the pixel circuit shown in Figure 14, T4 is controlled by G(nx), T1 is controlled by G(n), T3 and T5 are controlled by S(n+y), T2, T9 and T10 are controlled by S(n), and T7 and T8 are controlled by EM(n). The same GOA module can provide gate drive signals for G(nx) and G(n), and the same GOA module can provide scan signals for S(n+y) and S(n), thereby reducing the number of GOA modules used.

[0384] As shown in Figure 15, at least one embodiment of the pixel circuit shown in Figure 14 of this disclosure operates as follows:

[0385] The refresh frame FX may include an initialization phase t11, a compensation phase t12, a first hysteresis improvement phase t13, a first voltage control phase t10, and a first light emission phase t14, which are set sequentially.

[0386] During the initialization phase t11, EM(n) provides a high voltage signal, G(nx) provides a low voltage signal, G(n) provides a low voltage signal, S(n) provides a high voltage signal, S(n+y) provides a high voltage signal, T4 is turned on, and I2 provides a second initial voltage Vi2 to the first node N1 so that T0 can be turned on when the compensation phase t12 begins.

[0387] During the compensation phase t12, EM(n) provides a high voltage signal, G(nx) provides a high voltage signal, G(n) provides a low voltage signal, S(n) provides a low voltage signal, S(n+y) provides a high voltage signal, T1 is turned on, T9 and T1 are turned on, T2 is turned on, DT provides the data voltage Vdata to the second node N2, N1 and N3 are connected, I3 provides the third initial voltage Vi3 to the anode of O1 to clear the residual charge on the anode of O1;

[0388] At the start of the compensation phase t12, T0 is turned on, and Vdata charges Cst through T9, T2 and T1, changing the potential of N1 until the potential of N1 becomes Vdata+Vth, where Vth is the threshold voltage of T0.

[0389] In the first hysteresis improvement stage t13, EM(n) provides a high voltage signal, G(nx) provides a high voltage signal, G(n) provides a high voltage signal, S(n) provides a high voltage signal, S(n+y) provides a low voltage signal, T3 and T5 are turned on, I1 provides the first initial voltage Vi1 to the third node N3, T0 is turned on, Vi1 is written to the second node N2, improving the hysteresis phenomenon of T0 and improving the afterimage;

[0390] During the first voltage holding phase t10, the potential of the control voltage provided by VJ decreases to control the potential decrease of N4, reduce the voltage difference between N1 and N4, improve the leakage phenomenon of N1, and improve the flicker phenomenon.

[0391] In the first luminescence stage t14, EM(n) provides a low voltage signal, T7 and T8 are turned on, and T0 drives O1 to emit light.

[0392] As shown in FIG16, when at least one embodiment of the pixel circuit shown in FIG14 of this disclosure is in operation, the holding frame FB may include a second hysteresis improvement stage t23, a second voltage control stage t20 and a second light emission stage t24 set sequentially.

[0393] In the second hysteresis improvement stage t23, EM(n) provides a high voltage signal, G(nx) provides a high voltage signal, G(n) provides a high voltage signal, S(n) provides a high voltage signal, S(n+y) provides a low voltage signal, T3 and T5 are turned on, I1 provides the first initial voltage Vi1 to the third node N3, T0 is turned on, Vi1 is written to the second node N2, improving the hysteresis phenomenon of T0 and improving the afterimage;

[0394] In the second voltage control stage t20, the potential of the control voltage provided by VJ decreases to control the potential decrease of N4, reduce the voltage difference between N1 and N4, improve the leakage phenomenon of N1, and improve the flicker phenomenon.

[0395] In the second luminescence stage t24, EM(n) provides a low voltage signal, T7 and T8 are turned on, and T0 drives O1 to emit light.

[0396] As shown in Figure 17, based on at least one embodiment of the pixel circuit shown in Figure 6, the first control circuit includes a first transistor T1 and a sixth transistor T6, the second control circuit includes a second transistor T2, the first initialization circuit includes a third transistor T3, the second initialization circuit includes a fourth transistor T4; the driving circuit includes a driving transistor T0; and the voltage control circuit includes a first capacitor C1.

[0397] The gate of T0 is electrically connected to the first node N1, the source of T0 is electrically connected to the second node N2, and the drain of T0 is electrically connected to the third node N3.

[0398] The first terminal of the first capacitor C1 is electrically connected to the fourth node N4, and the second terminal of the first capacitor C1 is electrically connected to the control voltage terminal VJ.

[0399] The gate of the first transistor T1 is electrically connected to the nx-th scan terminal S(nx), the source of the first transistor T1 is electrically connected to the first node N1, and the drain of the first transistor T1 is electrically connected to the fourth node N4.

[0400] The gate of the sixth transistor T6 is electrically connected to the nth scanning terminal S(n), the source of the sixth transistor T6 is electrically connected to the first node N1, and the drain of the sixth transistor T6 is electrically connected to the fourth node N4.

[0401] The gate of the second transistor T2 is electrically connected to the nth gate drive terminal G(n), the source of the second transistor T2 is electrically connected to the fourth node N4, and the drain of the second transistor T2 is electrically connected to the third node N3.

[0402] The gate of the third transistor T3 is electrically connected to the gate scan terminal G(n+y) of the (n+y)th stage, the source of the third transistor T3 is electrically connected to the first initial voltage terminal I1, and the drain of the third transistor T3 is electrically connected to the fourth node N4; the first initial voltage terminal I1 is used to provide the first initial voltage Vi1.

[0403] The gate of the fourth transistor T4 is electrically connected to the nx-th scan terminal S(nx), the source of the fourth transistor T4 is electrically connected to the second initial voltage terminal I2, and the drain of the fourth transistor T4 is electrically connected to the first node N1; the second initial voltage terminal I2 is used to provide the second initial voltage Vi2.

[0404] The second light-emitting control circuit includes a seventh transistor T7, and the first light-emitting control circuit includes an eighth transistor T8; the data writing circuit includes a ninth transistor T9; the energy storage circuit includes a storage capacitor Cst.

[0405] The gate of the seventh transistor T7 is electrically connected to the nth stage light-emitting control terminal EM(n), the source of the seventh transistor T7 is electrically connected to the power supply voltage terminal ELVDD, and the drain of the seventh transistor T7 is electrically connected to the second node N2.

[0406] The gate of the eighth transistor T8 is electrically connected to the nth stage light-emitting control terminal EM(n), the source of the eighth transistor T8 is electrically connected to the third node N3, the drain of the eighth transistor T8 is electrically connected to the anode of the organic light-emitting diode O1, and the cathode of O1 is electrically connected to the low voltage terminal ELVSS.

[0407] The gate of the ninth transistor T9 is electrically connected to the nth scanning terminal S(n), the source of the ninth transistor T9 is electrically connected to the data line DT, and the drain of the ninth transistor T9 is electrically connected to the second node N2.

[0408] The first terminal of the storage capacitor Cst is electrically connected to the first node N1, and the second terminal of the storage capacitor Cst is electrically connected to the power supply voltage terminal ELVDD.

[0409] The third initialization circuit includes a tenth transistor T10;

[0410] The gate of the tenth transistor T10 is electrically connected to the gate driving terminal G(n+y) of the n+y stage, the source of the tenth transistor T10 is electrically connected to the third initial voltage terminal I3, and the drain of the tenth transistor T10 is electrically connected to the anode of the organic light-emitting diode O1.

[0411] In at least one embodiment of the pixel circuit shown in Figure 17, all transistors are p-type transistors, but this is not a limitation.

[0412] In at least one embodiment of the pixel circuit shown in Figure 17, the second end of C1 can be electrically connected to N3, or the second end of C1 can be electrically connected to EM(n).

[0413] In at least one embodiment of the pixel circuit shown in Figure 17, T1 and T4 are controlled by S(nx), T6 and T9 are controlled by S(n), T3 and T10 are controlled by G(n+y), T2 is controlled by G(n), and T7 and T8 are controlled by EM(n). The same GOA module provides scan signals to S(nx) and S(n), and the same GOA module provides gate drive signals to G(n+y) and G(n), thereby reducing the number of GOA modules used.

[0414] As shown in FIG18, when at least one embodiment of the pixel circuit shown in FIG17 of this disclosure is in operation, the refresh frame FX may include an initialization stage t11, a compensation stage t12, a first hysteresis improvement stage t13, a first voltage control stage t10, and a first light emission stage t14 set sequentially.

[0415] During the initialization phase t11, EM(n) provides a high voltage signal, G(n) provides a low voltage signal, S(nx) provides a low voltage signal, S(n) provides a high voltage signal, G(n+y) provides a high voltage signal, T4 is turned on, and I2 provides a second initial voltage Vi2 to the first node N1 so that T0 can be turned on at the start of the compensation phase t12.

[0416] During the compensation phase t12, EM(n) provides a high voltage signal, G(n) provides a low voltage signal, S(nx) provides a high voltage signal, S(n) provides a low voltage signal, G(n+y) provides a high voltage signal, T9 is turned on, DT provides the data voltage Vdata to the second node N2, T6 is turned on, and T2 is turned on, so that N1 and N3 are connected.

[0417] At the start of the compensation phase t12, T0 is turned on, and Vdata charges Cst through T9, T0, T2 and T6, changing the potential of N1 until the potential of N1 becomes Vdata+Vth, at which point T0 is turned off; Vth is the threshold voltage of T0.

[0418] In the first hysteresis improvement stage t13, EM(n) provides a high voltage signal, G(n) provides a low voltage signal, S(nx) provides a high voltage signal, S(n+y) provides a high voltage signal, G(n+y) provides a low voltage signal, T10 is turned on, I3 provides a third initial voltage Vi3 to the anode of O1 to clear the residual charge on the anode of O1; T3 and T2 are turned on, I1 provides a first initial voltage Vi1 to the third node N3, T0 is turned on to write Vi1 to the second node N2, improving the hysteresis phenomenon of T0 and improving the afterimage;

[0419] During the first voltage holding phase t10, the potential of the control voltage provided by VJ decreases to control the potential decrease of N4, reduce the voltage difference between N1 and N4, improve the leakage phenomenon of N1, and improve the flicker phenomenon.

[0420] In the first luminescence stage t14, EM(n) provides a low voltage signal, T7 and T8 are turned on, and T0 drives O1 to emit light.

[0421] The difference between at least one embodiment of the pixel circuit shown in FIG19 of this disclosure and at least one embodiment of the pixel circuit shown in FIG17 of this disclosure is that:

[0422] The drain of T4 is electrically connected to the fourth node N4.

[0423] As shown in Figure 20, based on at least one embodiment of the pixel circuit shown in Figure 7B, the light-emitting element is an organic light-emitting diode O1;

[0424] The first control circuit includes a first transistor T1, the second control circuit includes a second transistor T2, the first initialization circuit includes a third transistor T3, and the driving circuit includes a driving transistor T0.

[0425] The gate of T0 is electrically connected to the first node N1, the source of T0 is electrically connected to the second node N2, and the drain of T0 is electrically connected to the third node N3.

[0426] The gate of the first transistor T1 is electrically connected to the second light-emitting control terminal EM2(n) of the nth stage, the source of the first transistor T1 is electrically connected to the first node N1, and the drain of the first transistor T1 is electrically connected to the fourth node N4.

[0427] The gate of the second transistor T2 is electrically connected to the third light-emitting control terminal EM3(n-4) of the (n-4)th stage, the source of the second transistor T2 is electrically connected to the fourth node N4, and the drain of the second transistor T2 is electrically connected to the third node N3.

[0428] The gate of the third transistor T3 is electrically connected to the nth stage third light-emitting control terminal EM3(n), the source of the third transistor T3 is electrically connected to the first initial voltage terminal I1, and the drain of the third transistor T3 is electrically connected to the fourth node N4; the first initial voltage terminal I1 is used to provide the first initial voltage Vi1;

[0429] The first light-emitting control circuit includes an eighth transistor T8, and the second initialization circuit includes a fourth transistor T4;

[0430] The gate of the eighth transistor T8 is electrically connected to the first light-emitting control terminal EM1(n) of the nth stage, the source of the eighth transistor T8 is electrically connected to the third node N3, the drain of the eighth transistor T8 is electrically connected to the anode of the organic light-emitting diode O1, and the cathode of O1 is electrically connected to the low voltage terminal ELVSS.

[0431] The gate of the fourth transistor T4 is electrically connected to the (n-1)th stage gate driving terminal G(n-1), the source of the fourth transistor T4 is electrically connected to the second initial voltage terminal I2, and the drain of the fourth transistor T4 is electrically connected to the fourth node N4; the second initial voltage terminal I2 is used to provide the second initial voltage Vi2.

[0432] The second light-emitting control circuit includes a seventh transistor T7; the data writing circuit includes a ninth transistor T9; and the energy storage circuit includes a storage capacitor Cst.

[0433] The gate of the seventh transistor T7 is electrically connected to the first light-emitting control terminal EM1(n) of the nth stage, the source of the seventh transistor T7 is electrically connected to the power supply voltage terminal ELVDD, and the drain of the seventh transistor T7 is electrically connected to the second node N2.

[0434] The gate of the ninth transistor T9 is electrically connected to the nth gate driving terminal G(n), the source of the ninth transistor T9 is electrically connected to the data line DT, and the drain of the ninth transistor T9 is electrically connected to the second node N2.

[0435] The first terminal of the storage capacitor Cst is electrically connected to the first node N1, and the second terminal of the storage capacitor Cst is electrically connected to the power supply voltage terminal ELVDD.

[0436] The voltage control circuit includes a first capacitor C1;

[0437] The first terminal of the first capacitor C1 is electrically connected to the fourth node N4, and the second terminal of the first capacitor C1 is electrically connected to the third node N3.

[0438] The third initialization circuit includes a tenth transistor T10;

[0439] The gate of the tenth transistor T10 is electrically connected to the nth gate driving terminal G(n), the source of the tenth transistor T10 is electrically connected to the third initial voltage terminal I3, and the drain of the tenth transistor T10 is electrically connected to the anode of the organic light-emitting diode O1; the third initial voltage terminal I3 is used to provide the third initial voltage Vi3.

[0440] In at least one embodiment of the pixel circuit shown in Figure 20, all transistors are p-type transistors, but this is not a limitation.

[0441] In at least one embodiment of the pixel circuit shown in Figure 20, the second terminal of C1 can be replaced by being electrically connected to the control voltage terminal VJ.

[0442] In at least one embodiment of the pixel circuit shown in Figure 20, T7 and T8 are controlled by EM1(n), T9 and T10 are controlled by G(n), T4 is controlled by G(n-1), T2 is controlled by EM3(n-4), T3 is controlled by EM3(n), gate drive signals are provided to G(n) and G(n-1) through the same GOA module, and a third light emission control signal is provided to EM3(n-4) and EM3(n) through the same GOA module, so as to reduce the number of GOA modules used.

[0443] In at least one embodiment of the pixel circuit shown in Figures 20, 22, and 24 of this disclosure, only T1 is electrically connected to the first node N1. In this way, it is only necessary to control the leakage current between N4 and N1 to improve the problem of high brightness decay in LTPS (low-temperature polysilicon) pixel circuits in low-frequency displays.

[0444] As shown in FIG21, when at least one embodiment of the pixel circuit shown in FIG20 of this disclosure is in operation, the refresh frame includes an initialization stage t11, a compensation stage t12, a first hysteresis improvement stage t13, a first voltage control stage t10, and a first light emission stage t4, which are set sequentially.

[0445] During the initialization phase t11, EM1(n) provides a high voltage signal, EM2(n) provides a low voltage signal, G(n-1) provides a low voltage signal, G(n) provides a high voltage signal, EM3(n-4) provides a low voltage signal, and EM3(n) provides a high voltage signal. T1 and T4 are turned on. I2 provides a second initial voltage Vi2 to the first node N1 so that T0 can be turned on at the beginning of the compensation phase t12. When T2 is turned on, I2 writes Vi2 to the third node N3 to improve the hysteresis of T0.

[0446] During compensation phase t12, EM1(n) provides a high voltage signal, EM2(n) provides a low voltage signal, G(n-1) provides a high voltage signal, G(n) provides a low voltage signal, EM3(n-4) provides a low voltage signal, and EM3(n) provides a high voltage signal. T9 is turned on, DT provides the data voltage Vdata to the second node N2, T1 and T2 are turned on, and N1 and N3 are connected. T10 is turned on, and I3 provides the third initial voltage Vi3 to the anode of O1 to clear the residual charge on the anode of O1.

[0447] At the start of the compensation phase t12, T0 is turned on, and Vdata charges Cst through T9, T0, T1 and T2 until T0 is turned off. The potential of N1 is Vdata + Vth, where Vth is the threshold voltage of T0.

[0448] In the first hysteresis improvement stage t13, EM1(n) provides a high voltage signal, EM2(n) provides a high voltage signal, G(n-1) provides a high voltage signal, G(n) provides a high voltage signal, EM3(n-4) provides a low voltage signal, EM3(n) provides a low voltage signal, T3 is turned on, T2 is turned on, I1 provides the first initial voltage Vi1 to the third node N3, T0 is turned on, Vi1 is written to the second node N2, improving the hysteresis phenomenon of T0 and improving the afterimage;

[0449] In the first voltage control stage t10, the potential of the first light emission control signal of the nth stage provided by EM1(n) drops from high voltage to low voltage, the potential of N3 decreases, and the potential of N4 is pulled down through C1, reducing the voltage difference between N1 and N4, improving the leakage phenomenon of N1, and improving the flicker phenomenon.

[0450] In the first light-emitting stage t14, EM1(n) provides a low voltage signal, EM2(n) provides a high voltage signal, G(n-1) provides a high voltage signal, G(n) provides a high voltage signal, EM3(n-4) provides a high voltage signal, EM3(n) provides a high voltage signal, T7 and T8 are turned on, and T0 drives O1 to emit light.

[0451] At least one embodiment of the pixel circuit shown in FIG20 of this disclosure, when in operation, holds the frame without writing data or compensating for data.

[0452] The hold frame may include a second initialization phase, a third initialization phase, a second hysteresis improvement phase, a second voltage control phase, and a second light emission phase, which are set sequentially.

[0453] In the second initialization phase, T4 is turned on, T2 is turned on, I2 provides the second initial voltage Vi2 to the third node N3, T0 is turned on, and Vi2 is written to the second node N2 to improve the hysteresis of T0;

[0454] In the third initialization phase, T10 is turned on, and I3 provides the third initial voltage Vi3 to the anode of O1 to clear the residual charge on the anode of O1;

[0455] In the second hysteresis improvement stage, T3 is turned on, T2 is turned on, I1 provides the first initial voltage Vi1 to the fourth node N4, T2 is turned on, Vi1 is written to the third node N3, T0 is turned on, Vi1 is written to the second node N2, and the hysteresis phenomenon of T0 is improved.

[0456] In the second voltage control stage, the potential of the first light emission control signal of the nth stage provided by EM1(n) drops from high voltage to low voltage, the potential of N3 decreases, and the potential of N4 is pulled down through C1, reducing the voltage difference between N1 and N4, improving the leakage phenomenon of N1, and improving the flicker phenomenon.

[0457] In the second light-emitting stage, EM1(n) provides a low voltage signal, EM2(n) provides a high voltage signal, G(n-1) provides a high voltage signal, G(n) provides a high voltage signal, EM3(n-4) provides a high voltage signal, EM3(n) provides a high voltage signal, T7 and T8 are turned on, and T0 drives O1 to emit light.

[0458] As shown in Figure 22, based on at least one embodiment of the pixel circuit shown in Figure 7D, the light-emitting element is an organic light-emitting diode O1;

[0459] The first control circuit includes a first transistor T1, the second control circuit includes a second transistor T2, and the first initialization circuit includes a third transistor T3.

[0460] The gate of the first transistor T1 is electrically connected to the second light-emitting control terminal EM2(n) of the nth stage, the source of the first transistor T1 is electrically connected to the first node N1, and the drain of the first transistor T1 is electrically connected to the fourth node N4.

[0461] The gate of the second transistor T2 is electrically connected to the third light-emitting control terminal EM3(n-4) of the (n-4)th stage, the source of the second transistor T2 is electrically connected to the fourth node N4, and the drain of the second transistor T2 is electrically connected to the third node N3.

[0462] The gate of the third transistor T3 is electrically connected to the nth stage third light-emitting control terminal EM3(n), the source of the third transistor T3 is electrically connected to the first initial voltage terminal I1, and the drain of the third transistor T3 is electrically connected to the fourth node N4; the first initial voltage terminal I1 is used to provide the first initial voltage Vi1;

[0463] The first light-emitting control circuit includes an eighth transistor T8, and the second initialization circuit includes a fourth transistor T4;

[0464] The gate of the eighth transistor T8 is electrically connected to the first light-emitting control terminal EM1(n+b) of the n+b stage, the source of the eighth transistor T8 is electrically connected to the third node N3, and the drain of the eighth transistor T8 is electrically connected to the anode of the organic light-emitting diode O1; the cathode of O1 is electrically connected to the low-voltage terminal ELVSS; b is a positive integer.

[0465] The gate of the fourth transistor T4 is electrically connected to the (n-1)th stage gate driving terminal G(n-1), the source of the fourth transistor T4 is electrically connected to the second initial voltage terminal I2, and the drain of the fourth transistor T4 is electrically connected to the third node N3; the second initial voltage terminal I2 is used to provide the second initial voltage Vi2.

[0466] The driving circuit includes a driving transistor T0;

[0467] The gate of the driving transistor T0 is electrically connected to the first node N1, the source of the driving transistor T0 is electrically connected to the second node N2, and the drain of the driving transistor T0 is electrically connected to the third node N3.

[0468] The second light-emitting control circuit includes a seventh transistor T7; the data writing circuit includes a ninth transistor T9; and the energy storage circuit includes a storage capacitor Cst.

[0469] The gate of the seventh transistor T7 is electrically connected to the first light-emitting control terminal EM1(n) of the nth stage, the source of the seventh transistor T7 is electrically connected to the power supply voltage terminal ELVDD, and the drain of the seventh transistor T7 is electrically connected to the second node N2.

[0470] The gate of the ninth transistor T9 is electrically connected to the nth gate driving terminal G(n), the source of the ninth transistor T9 is electrically connected to the data line DT, and the drain of the ninth transistor T9 is electrically connected to the second node N2.

[0471] The first terminal of the storage capacitor Cst is electrically connected to the first node N1, and the second terminal of the storage capacitor Cst is electrically connected to the power supply voltage terminal ELVDD.

[0472] The voltage control circuit includes a first capacitor C1;

[0473] The first terminal of the first capacitor C1 is electrically connected to the fourth node N4, and the second terminal of the first capacitor C1 is electrically connected to the third node N3.

[0474] The third initialization circuit includes a tenth transistor T10;

[0475] The gate of the tenth transistor T10 is electrically connected to the nth gate driving terminal G(n), the source of the tenth transistor T10 is electrically connected to the third initial voltage terminal I3, and the drain of the tenth transistor T10 is electrically connected to the anode of the organic light-emitting diode O1; the third initial voltage terminal I3 is used to provide the third initial voltage Vi3.

[0476] In at least one embodiment of the pixel circuit shown in Figure 22, all transistors are p-type transistors, but this is not a limitation.

[0477] In at least one embodiment of the pixel circuit shown in Figure 22, the second terminal of C1 can be replaced by being electrically connected to the control voltage terminal VJ.

[0478] In at least one embodiment of the pixel circuit shown in Figure 22, T7 is controlled by EM1(n), T8 is controlled by EM1(n+b), T2 is controlled by EM3(n-4), T3 is controlled by EM3(n), T4 is controlled by G(n-1), and T9 and T10 are controlled by G(n). A third light emission control signal is provided to EM3(n-4) and EM3(n) through the same GOA module, and a gate drive signal is provided to G(n-1) and G(n) through the same GOA module, so as to reduce the number of GOA modules used.

[0479] As shown in FIG23, when at least one embodiment of the pixel circuit shown in FIG22 of this disclosure is in operation, the refresh frame may include an initialization stage t11, a compensation stage t12, a first hysteresis improvement stage t13, a first voltage control stage t10, and a first light emission stage t4 set sequentially.

[0480] During the initialization phase t11, EM1(n) provides a high voltage signal, EM1(n+b) provides a high voltage signal, EM2(n) provides a low voltage signal, G(n-1) provides a low voltage signal, G(n) provides a high voltage signal, EM3(n-4) provides a low voltage signal, EM3(n) provides a high voltage signal, T8 is turned on, T4 is turned on, T2 is turned on, T1 is turned on, and I2 provides a second initial voltage Vi2 to the first node N1 so that T0 can be turned on at the start of the compensation phase t12.

[0481] During compensation phase t12, EM1(n) provides a high voltage signal, EM1(n+b) provides a high voltage signal, EM2(n) provides a low voltage signal, G(n-1) provides a high voltage signal, G(n) provides a low voltage signal, EM3(n-4) provides a low voltage signal, EM3(n) provides a high voltage signal, T9 is turned on, DT provides the data voltage Vdata to the second node N2, T1 and T2 are turned on, and N1 and N3 are connected; T10 is turned on, I3 provides the third initial voltage Vi3 to the anode of O1, clearing the residual charge on the anode of O1;

[0482] At the start of the compensation phase t12, T0 is turned on, charging Cst through Vdata until T0 is turned off. The potential of the first node N1 becomes Vdata + Vth, where Vth is the threshold voltage of T0.

[0483] In the first hysteresis improvement stage t13, EM1(n) provides a high voltage signal, EM1(n+b) provides a high voltage signal, EM2(n) provides a high voltage signal, G(n-1) provides a high voltage signal, G(n) provides a high voltage signal, EM3(n-4) provides a low voltage signal, EM3(n) provides a low voltage signal, T3 and T2 are turned on, I1 provides the first initial voltage Vi1 to N3, T0 is turned on, Vi1 is written to the second node N2, and the hysteresis phenomenon of T0 is improved;

[0484] In the first voltage control stage t10, the potential of the first light emission control signal of the n+b level provided by EM1(n+b) drops from high voltage to low voltage, the potential of N3 decreases, and the potential of N4 is pulled down through C1, reducing the voltage difference between N1 and N4, improving the leakage phenomenon of N1, and improving the flicker phenomenon.

[0485] In the first light-emitting stage t14, EM1(n) provides a low voltage signal, EM(n+b) provides a low voltage signal, EM2(n) provides a high voltage signal, G(n-1) provides a high voltage signal, G(n) provides a high voltage signal, EM3(n-4) provides a high voltage signal, EM3(n) provides a high voltage signal, T7 and T8 are turned on, and T0 drives O1 to emit light.

[0486] In at least one embodiment of the pixel circuit shown in FIG22 of this disclosure, when in operation, the holding frame may include a second hysteresis improvement stage, a second voltage control stage, and a second light emission stage arranged sequentially.

[0487] In the second hysteresis improvement stage, T3 and T2 are turned on, I1 provides the first initial voltage Vi1 to N3, T0 is turned on, Vi1 is written to the second node N2, and the hysteresis phenomenon of T0 is improved.

[0488] In the second voltage control stage, the potential of the first light emission control signal of the n+b level provided by EM1(n+b) drops from high voltage to low voltage, the potential of N3 decreases, and the potential of N4 is pulled down through C1, reducing the voltage difference between N1 and N4, improving the leakage phenomenon of N1, and improving the flicker phenomenon.

[0489] In the second luminescence stage, T7 and T8 are turned on, and T0 drives O1 to emit light.

[0490] As shown in Figure 24, based on at least one embodiment of the pixel circuit shown in Figure 7C, the light-emitting element is an organic light-emitting diode O1;

[0491] The first control circuit includes a first transistor T1, the second control circuit includes a second transistor T2, and the first initialization circuit includes a third transistor T3.

[0492] The gate of the first transistor T1 is electrically connected to the second light-emitting control terminal EM2(n) of the nth stage, the source of the first transistor T1 is electrically connected to the first node N1, and the drain of the first transistor T1 is electrically connected to the fourth node N4.

[0493] The gate of the second transistor T2 is electrically connected to the third light-emitting control terminal EM3(n-4) of the (n-4)th stage, the source of the second transistor T2 is electrically connected to the fourth node N4, and the drain of the second transistor T2 is electrically connected to the third node N3.

[0494] The gate of the third transistor T3 is electrically connected to the nth stage third light-emitting control terminal EM3(n), the source of the third transistor T3 is electrically connected to the first initial voltage terminal I1, and the drain of the third transistor T3 is electrically connected to the fourth node N4; the first initial voltage terminal I1 is used to provide the first initial voltage Vi1;

[0495] The first light-emitting control circuit includes an eighth transistor T8, and the second initialization circuit includes a fourth transistor T4;

[0496] The gate of the eighth transistor T8 is electrically connected to the first light-emitting control terminal EM1(n+b) of the n+b stage, the source of the eighth transistor T8 is electrically connected to the third node N3, and the drain of the eighth transistor T8 is electrically connected to the anode of the organic light-emitting diode O1; the cathode of O1 is electrically connected to the low-voltage terminal ELVSS; b is a positive integer.

[0497] The gate of the fourth transistor T4 is electrically connected to the (n-1)th stage gate driving terminal G(n-1), the source of the fourth transistor T4 is electrically connected to the second initial voltage terminal I2, and the drain of the fourth transistor T4 is electrically connected to the anode of the organic light-emitting diode O1; the second initial voltage terminal I2 is used to provide the second initial voltage Vi2.

[0498] The driving circuit includes a driving transistor T0;

[0499] The gate of the driving transistor T0 is electrically connected to the first node N1, the source of the driving transistor T0 is electrically connected to the second node N2, and the drain of the driving transistor T0 is electrically connected to the third node N3.

[0500] The second light-emitting control circuit includes a seventh transistor T7; the data writing circuit includes a ninth transistor T9; and the energy storage circuit includes a storage capacitor Cst.

[0501] The gate of the seventh transistor T7 is electrically connected to the first light-emitting control terminal EM1(n) of the nth stage, the source of the seventh transistor T7 is electrically connected to the power supply voltage terminal ELVDD, and the drain of the seventh transistor T7 is electrically connected to the second node N2.

[0502] The gate of the ninth transistor T9 is electrically connected to the nth gate driving terminal G(n), the source of the ninth transistor T9 is electrically connected to the data line DT, and the drain of the ninth transistor T9 is electrically connected to the second node N2.

[0503] The first terminal of the storage capacitor Cst is electrically connected to the first node N1, and the second terminal of the storage capacitor Cst is electrically connected to the power supply voltage terminal ELVDD.

[0504] The voltage control circuit includes a first capacitor C1;

[0505] The first terminal of the first capacitor C1 is electrically connected to the fourth node N4, and the second terminal of the first capacitor C1 is electrically connected to the third node N3.

[0506] The third initialization circuit includes a tenth transistor T10;

[0507] The gate of the tenth transistor T10 is electrically connected to the nth gate driving terminal G(n), the source of the tenth transistor T10 is electrically connected to the third initial voltage terminal I3, and the drain of the tenth transistor T10 is electrically connected to the anode of the organic light-emitting diode O1; the third initial voltage terminal I3 is used to provide the third initial voltage Vi3.

[0508] In at least one embodiment of the pixel circuit shown in Figure 24, all transistors are p-type transistors, but this is not a limitation.

[0509] In at least one embodiment of the pixel circuit shown in Figure 24, the second terminal of C1 can be replaced by being electrically connected to the control voltage terminal VJ.

[0510] In at least one embodiment of the pixel circuit shown in Figure 24, T7 is controlled by EM1(n), T8 is controlled by EM1(n+b), T2 is controlled by EM3(n-4), T3 is controlled by EM3(n), T4 is controlled by G(n-1), and T9 and T10 are controlled by G(n). A third light emission control signal is provided to EM3(n-4) and EM3(n) through the same GOA module, and a gate drive signal is provided to G(n-1) and G(n) through the same GOA module, so as to reduce the number of GOA modules used.

[0511] As shown in FIG25, when at least one embodiment of the pixel circuit shown in FIG24 of this disclosure is in operation, the refresh frame may include an initialization stage t11, a compensation stage t12, a first hysteresis improvement stage t13, a first voltage control stage t10, and a first light emission stage t4 set sequentially.

[0512] During the initialization phase t11, EM1(n) provides a high voltage signal, EM1(n+b) provides a low voltage signal, EM2(n) provides a low voltage signal, G(n-1) provides a low voltage signal, G(n) provides a high voltage signal, EM3(n-4) provides a low voltage signal, EM3(n) provides a high voltage signal, T8 is turned on, T4 is turned on, T2 is turned on, T1 is turned on, and I2 provides a second initial voltage Vi2 to the first node N1 so that T0 can be turned on at the start of the compensation phase t12.

[0513] During compensation phase t12, EM1(n) provides a high voltage signal, EM1(n+b) provides a high voltage signal, EM2(n) provides a low voltage signal, G(n-1) provides a high voltage signal, G(n) provides a low voltage signal, EM3(n-4) provides a low voltage signal, EM3(n) provides a high voltage signal, T9 is turned on, DT provides the data voltage Vdata to the second node N2, T1 and T2 are turned on, and N1 and N3 are connected; T10 is turned on, I3 provides the third initial voltage Vi3 to the anode of O1, clearing the residual charge on the anode of O1;

[0514] At the start of the compensation phase t12, T0 is turned on, charging Cst through Vdata until T0 is turned off. The potential of the first node N1 becomes Vdata + Vth, where Vth is the threshold voltage of T0.

[0515] In the first hysteresis improvement stage t13, EM1(n) provides a high voltage signal, EM1(n+b) provides a high voltage signal, EM2(n) provides a high voltage signal, G(n-1) provides a high voltage signal, G(n) provides a high voltage signal, EM3(n-4) provides a low voltage signal, EM3(n) provides a low voltage signal, T3 and T2 are turned on, I1 provides the first initial voltage Vi1 to N3, T0 is turned on, Vi1 is written to the second node N2, and the hysteresis phenomenon of T0 is improved;

[0516] In the first voltage control stage t10, the potential of the first light emission control signal of the n+b level provided by EM1(n+b) drops from high voltage to low voltage, the potential of N3 decreases, and the potential of N4 is pulled down through C1, reducing the voltage difference between N1 and N4, improving the leakage phenomenon of N1, and improving the flicker phenomenon.

[0517] In the first light-emitting stage t14, EM1(n) provides a low voltage signal, EM(n+b) provides a low voltage signal, EM2(n) provides a high voltage signal, G(n-1) provides a high voltage signal, G(n) provides a high voltage signal, EM3(n-4) provides a high voltage signal, EM3(n) provides a high voltage signal, T7 and T8 are turned on, and T0 drives O1 to emit light.

[0518] In at least one embodiment of the pixel circuit shown in FIG24 of this disclosure, when in operation, the holding frame may include a second hysteresis improvement stage, a second voltage control stage, and a second light emission stage arranged sequentially.

[0519] In the second hysteresis improvement stage, T3 and T2 are turned on, I1 provides the first initial voltage Vi1 to N3, T0 is turned on, Vi1 is written to the second node N2, and the hysteresis phenomenon of T0 is improved.

[0520] In the second voltage control stage, the potential of the first light emission control signal of the n+b level provided by EM1(n+b) drops from high voltage to low voltage, the potential of N3 decreases, and the potential of N4 is pulled down through C1, reducing the voltage difference between N1 and N4, improving the leakage phenomenon of N1, and improving the flicker phenomenon.

[0521] In the second luminescence stage, T7 and T8 are turned on, and T0 drives O1 to emit light.

[0522] The driving method described in this embodiment is applied to the aforementioned pixel circuit, and the refresh frame includes a compensation stage and a first hysteresis improvement stage set sequentially; the driving method includes:

[0523] During the compensation phase, the first control circuit, under the control of the first control signal, controls the connection between the first node and the fourth node; the second control circuit, under the control of the second control signal, controls the connection between the fourth node and the third node.

[0524] In the first hysteresis improvement stage, the first initialization circuit, under the control of the first initial control signal, writes the first initial voltage into the fourth node, and the second control circuit, under the control of the second control signal, controls the connection between the fourth node and the third node; or, in the first hysteresis improvement stage, the first initialization circuit, under the control of the first initial control signal, writes the first initial voltage into the third node.

[0525] Optionally, the driving method further includes:

[0526] During the first hysteresis improvement stage, the drive circuit controls the connection between the second node and the third node under the control of the potential of the first node.

[0527] Optionally, the refresh frame further includes a first voltage control stage and a first light emission stage, set sequentially after the first hysteresis improvement stage; the pixel circuit further includes a voltage control circuit, a light-emitting element, a first light emission control circuit, and a second light emission control circuit; the driving method further includes:

[0528] During the first voltage control phase, the potential of the control voltage provided by the control voltage terminal is pulled down, and the voltage control circuit controls the potential of the fourth node to become lower according to the control voltage.

[0529] During the first light-emitting stage, the second light-emitting control circuit, under the control of the light-emitting control signal, controls the connection between the power supply voltage terminal and the second node; the first light-emitting control circuit, under the control of the light-emitting control signal, controls the connection between the third node and the first electrode of the light-emitting element.

[0530] Optionally, the pixel circuit further includes a voltage control circuit; the voltage control circuit is electrically connected to the fourth node and the third node respectively, and is used to control the potential of the fourth node according to the potential of the third node; the refresh frame further includes a first light emission stage set after the first hysteresis improvement stage; the driving method further includes:

[0531] At the start of the first light-emitting stage, the voltage control circuit controls the potential of the fourth node to decrease according to the potential of the third node.

[0532] Optionally, the holding frame includes a second hysteresis improvement phase; the driving method includes:

[0533] In the second hysteresis improvement stage, the first initialization circuit, under the control of the first initial control signal, writes the first initial voltage into the fourth node, and the second control circuit, under the control of the second control signal, controls the connection between the fourth node and the third node.

[0534] Optionally, the holding frame further includes a second voltage control stage and a second light emission stage, which are sequentially set after the second hysteresis improvement stage; the pixel circuit further includes a voltage control circuit, a light emission element, a first light emission control circuit, and a second light emission control circuit; the driving method further includes:

[0535] During the second voltage control phase, the potential of the control voltage provided at the control voltage terminal decreases, and the voltage control circuit controls the potential of the fourth node to decrease according to the control voltage.

[0536] In the second light-emitting stage, the second light-emitting control circuit, under the control of the light-emitting control signal, controls the connection between the power supply voltage terminal and the second node; the first light-emitting control circuit, under the control of the light-emitting control signal, controls the connection between the third node and the first electrode of the light-emitting element.

[0537] Optionally, the pixel circuit further includes a voltage control circuit; the voltage control circuit is electrically connected to the fourth node and the third node respectively, and is used to control the potential of the fourth node according to the potential of the third node; the holding frame further includes a second emission stage disposed after the second hysteresis improvement stage; the driving method further includes:

[0538] At the start of the second light-emitting stage, the voltage control circuit controls the potential of the fourth node to decrease according to the potential of the third node.

[0539] The display device described in this disclosure includes the pixel circuit described above.

[0540] The above description represents the preferred embodiments of this disclosure. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles described herein, and these improvements and modifications should also be considered within the scope of protection of this disclosure.

Claims

1. A pixel circuit, comprising a driving circuit, a first control circuit, a second control circuit, and a first initialization circuit; The control terminal of the driving circuit is electrically connected to the first node, the first terminal of the driving circuit is electrically connected to the second node, and the second terminal of the driving circuit is electrically connected to the third node. The driving circuit is used to generate a driving current under the control of the potential of the first node. The first control circuit is electrically connected to the first control terminal, the first node, and the fourth node, respectively, and is used to control the connection between the first node and the fourth node under the control of the first control signal provided by the first control terminal; The second control circuit is electrically connected to the second control terminal, the fourth node, and the third node, respectively, and is used to control the connection between the fourth node and the third node under the control of the second control signal provided by the second control terminal; The first initialization circuit is electrically connected to the first initial control terminal and the first initial voltage terminal respectively. The first initialization circuit is also electrically connected to the fourth node, and is used to write the first initial voltage provided by the first initial voltage terminal into the fourth node under the control of the first initial control signal provided by the first initial control terminal.

2. The pixel circuit as described in claim 1, wherein, It also includes a second initialization circuit; The second initialization circuit is electrically connected to the second initial control terminal, the second initial voltage terminal, and the first node, respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the first node under the control of the second initial control signal provided by the second initial control terminal.

3. The pixel circuit as described in claim 1, wherein, It also includes a second initialization circuit; The second initialization circuit is electrically connected to the second initial control terminal, the second initial voltage terminal, and the fourth node, respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the fourth node under the control of the second initial control signal provided by the second initial control terminal.

4. The pixel circuit as described in claim 1, wherein, It also includes a light-emitting element, a first light-emitting control circuit, and a second initialization circuit; The first light-emitting control circuit is electrically connected to the first light-emitting control signal terminal, the third node, and the first electrode of the light-emitting element, respectively, and is used to control the connection between the third node and the first electrode of the light-emitting element under the control of the first light-emitting control signal provided by the first light-emitting control signal terminal; the second electrode of the light-emitting element is electrically connected to the first voltage terminal. The second initialization circuit is electrically connected to the second initial control terminal, the second initial voltage terminal, and the first electrode of the light-emitting element, respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the first electrode of the light-emitting element under the control of the second initial control signal provided by the second initial control terminal.

5. The pixel circuit according to any one of claims 1 to 4, wherein, It also includes a voltage control circuit; The voltage control circuit is electrically connected to the fourth node and the control voltage terminal respectively, and is used to control the potential of the fourth node according to the control voltage provided by the control voltage terminal; or, The voltage control circuit is electrically connected to both the fourth node and the third node, and is used to control the potential of the fourth node according to the potential of the third node; or, The pixel circuit further includes a light-emitting element and a first light-emitting control circuit. The voltage control circuit is electrically connected to the fourth node and the first light-emitting control signal terminal, respectively, and is used to control the potential of the fourth node according to the first light-emitting control signal provided by the first light-emitting control signal terminal.

6. The pixel circuit as described in claim 2, wherein, The first control terminal is the nth level scan terminal, the second control terminal is the nth level gate drive terminal, the first initial control terminal is the n+yth level gate drive terminal, and the second initial voltage terminal is the nxth level scan terminal; n, x, and y are all positive integers.

7. The pixel circuit as described in claim 2 or 3, wherein, The first control terminal is the nth level gate drive terminal, the second control terminal includes the nth level scan terminal and the n+yth level scan terminal, the first initial control terminal is the n+yth level scan terminal, and the second initial control terminal is the nxth level scan terminal; n, x, and y are all positive integers.

8. The pixel circuit as described in claim 2 or 3, wherein, The first control terminal includes an nth level scan terminal and an nxth level scan terminal, the second control terminal is an nth level gate drive terminal, the first initial control terminal is an n+yth level gate drive terminal, and the second initial control terminal is an nxth level scan terminal; n, x, and y are all positive integers.

9. The pixel circuit as described in claim 3, wherein, The first control terminal is the second light-emitting control terminal of the nth stage, the second control terminal is the third light-emitting control terminal of the nath stage, the first initial control terminal is the third light-emitting control terminal of the nth stage, and the second initial control terminal is the gate driving terminal of the nbth stage. n, a, and b are all positive integers.

10. The pixel circuit as claimed in claim 3, wherein, The first control terminal is the second light-emitting control terminal of the na-th stage, the second control terminal is the second light-emitting control terminal of the n-th stage, the first initial control terminal is the gate driving terminal of the n+b-th stage, and the second initial control terminal is the second light-emitting control terminal of the nc-th stage. n, a, b, and c are all positive integers.

11. The pixel circuit as claimed in claim 4, wherein, The first control terminal is the second light-emitting control terminal of the nth stage, the second control terminal is the third light-emitting control terminal of the nath stage, the first initial control terminal is the third light-emitting control terminal of the nth stage, the first light-emitting control signal terminal is the first light-emitting control terminal of the n+bth stage, and the second initial control terminal is the gate driving terminal of the ncth stage. n, a, b, and c are all positive integers.

12. The pixel circuit as claimed in claim 6, wherein, The first control circuit includes a first transistor, the second control circuit includes a second transistor, the first initialization circuit includes a third transistor, and the second initialization circuit includes a fourth transistor. The gate of the first transistor is electrically connected to the nth scanning terminal, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the fourth node. The gate of the second transistor is electrically connected to the nth gate drive terminal, the first terminal of the second transistor is electrically connected to the fourth node, and the second terminal of the second transistor is electrically connected to the third node. The gate of the third transistor is electrically connected to the gate driving terminal of the (n+y)th stage, the first terminal of the third transistor is electrically connected to the first initial voltage terminal, and the second terminal of the third transistor is electrically connected to the fourth node. The gate of the fourth transistor is electrically connected to the nx-th scanning terminal, the first terminal of the fourth transistor is electrically connected to the second initial voltage terminal, and the second terminal of the fourth transistor is electrically connected to the first node.

13. The pixel circuit as claimed in claim 7, wherein, The first control circuit includes a first transistor, the second control circuit includes a second transistor and a fifth transistor, the first initialization circuit includes a third transistor, and the second initialization circuit includes a fourth transistor; The gate of the first transistor is electrically connected to the nth gate drive terminal, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the fourth node. The gate of the second transistor is electrically connected to the nth scanning terminal, the first terminal of the second transistor is electrically connected to the fourth node, and the second terminal of the second transistor is electrically connected to the third node; The gate of the fifth transistor is electrically connected to the (n+y)th scanning terminal, the first terminal of the fifth transistor is electrically connected to the fourth node, and the second terminal of the fifth transistor is electrically connected to the third node. The gate of the third transistor is electrically connected to the (n+y)th scanning terminal, the first terminal of the third transistor is electrically connected to the first initial voltage terminal, and the second terminal of the third transistor is electrically connected to the fourth node. The gate of the fourth transistor is electrically connected to the nx-th scanning terminal, the first terminal of the fourth transistor is electrically connected to the second initial voltage terminal, and the second terminal of the fourth transistor is electrically connected to the fourth node or the first node.

14. The pixel circuit as claimed in claim 8, wherein, The first control circuit includes a first transistor and a sixth transistor, the second control circuit includes a second transistor, the first initialization circuit includes a third transistor, and the second initialization circuit includes a fourth transistor. The gate of the first transistor is electrically connected to the nxth scanning terminal, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the fourth node. The gate of the sixth transistor is electrically connected to the nth scanning terminal, the first terminal of the sixth transistor is electrically connected to the first node, and the second terminal of the sixth transistor is electrically connected to the fourth node. The gate of the second transistor is electrically connected to the nth gate drive terminal, the first terminal of the second transistor is electrically connected to the fourth node, and the second terminal of the second transistor is electrically connected to the third node. The gate of the third transistor is electrically connected to the gate scan terminal of the (n+y)th stage, the first terminal of the third transistor is electrically connected to the first initial voltage terminal, and the second terminal of the third transistor is electrically connected to the fourth node. The gate of the fourth transistor is electrically connected to the nx-th scanning terminal, the first terminal of the fourth transistor is electrically connected to the second initial voltage terminal, and the second terminal of the fourth transistor is electrically connected to the first node or the fourth node.

15. The pixel circuit according to any one of claims 1 to 4, wherein, The first control circuit includes a first transistor, the second control circuit includes a second transistor, and the first initialization circuit includes a third transistor; The gate of the first transistor is electrically connected to the first control terminal, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the fourth node. The gate of the second transistor is electrically connected to the second control terminal, the first terminal of the second transistor is electrically connected to the fourth node, and the second terminal of the second transistor is electrically connected to the third node. The gate of the third transistor is electrically connected to the first initial control terminal, the first terminal of the third transistor is electrically connected to the first initial voltage terminal, and the second terminal of the third transistor is electrically connected to the fourth node.

16. The pixel circuit as claimed in claim 4, wherein, The first light-emitting control circuit includes an eighth transistor, and the second initialization circuit includes a fourth transistor; The gate of the eighth transistor is electrically connected to the first light-emitting control signal terminal, the first electrode of the eighth transistor is electrically connected to the third node, and the second electrode of the eighth transistor is electrically connected to the first electrode of the light-emitting element. The gate of the fourth transistor is electrically connected to the second initial control terminal, the first terminal of the fourth transistor is electrically connected to the second initial voltage terminal, and the second terminal of the fourth transistor is electrically connected to the first terminal of the light-emitting element.

17. The pixel circuit as claimed in claim 5, wherein, The voltage control circuit includes a first capacitor; The first terminal of the first capacitor is electrically connected to the fourth node, and the second terminal of the first capacitor is electrically connected to the control voltage terminal; or... The first terminal of the first capacitor is electrically connected to the fourth node, and the second terminal of the first capacitor is electrically connected to the third node; or... The first end of the first capacitor is electrically connected to the fourth node, and the second end of the first capacitor is electrically connected to the first light-emitting control signal terminal.

18. The pixel circuit as claimed in claim 1, wherein, It also includes a light-emitting element, a first light-emitting control circuit, a second light-emitting control circuit, a data writing circuit, and an energy storage circuit; The first light-emitting control circuit is electrically connected to the light-emitting control terminal, the third node, and the first electrode of the light-emitting element, respectively, and is used to control the connection between the third node and the first electrode of the light-emitting element under the control of the light-emitting control signal provided by the light-emitting control terminal; the second electrode of the light-emitting element is electrically connected to the first voltage terminal. The second light-emitting control circuit is electrically connected to the light-emitting control terminal, the power supply voltage terminal, and the second node, respectively, and is used to control the connection between the power supply voltage terminal and the second node under the control of the light-emitting control signal; The data writing circuit is electrically connected to the nth level scanning terminal, the data line, and the second node, respectively, and is used to write the data voltage provided by the data line into the second node under the control of the nth level scanning signal provided by the nth level scanning terminal; n is a positive integer; The first end of the energy storage circuit is electrically connected to the first node, and the second end of the energy storage circuit is electrically connected to the DC voltage terminal. The energy storage circuit is used to store electrical energy.

19. The pixel circuit as claimed in claim 18, wherein, It also includes a voltage control circuit; the voltage control circuit includes a first capacitor, a first terminal of which is electrically connected to the fourth node, and a second terminal of which is electrically connected to the control voltage terminal; the energy storage circuit includes a storage capacitor; a first terminal of which is electrically connected to the first node, and a second terminal of which is electrically connected to the DC voltage terminal. The capacitance value of the first capacitor is less than or equal to 1 / 5 of the capacitance value of the storage capacitor, and the capacitance value of the first capacitor is greater than or equal to 1fF.

20. The pixel circuit as claimed in claim 4, wherein, It also includes a light-emitting element, a second light-emitting control circuit, a data writing circuit, and an energy storage circuit; The second light-emitting control circuit is electrically connected to the second light-emitting control signal terminal, the power supply voltage terminal, and the second node, respectively, and is used to control the connection between the power supply voltage terminal and the second node under the control of the second light-emitting control signal provided by the second light-emitting control signal terminal; The data writing circuit is electrically connected to the nth-level gate driving terminal, the data line, and the second node, respectively, and is used to write the data voltage provided by the data line into the second node under the control of the nth-level gate driving signal provided by the nth-level gate driving terminal; n is a positive integer; The first end of the energy storage circuit is electrically connected to the first node, and the second end of the energy storage circuit is electrically connected to the DC voltage terminal. The energy storage circuit is used to store electrical energy.

21. The pixel circuit as claimed in claim 20, wherein, It also includes a voltage control circuit; the voltage control circuit includes a first capacitor, a first terminal of which is electrically connected to the fourth node, and a second terminal of which is electrically connected to the third node; the energy storage circuit includes a storage capacitor; a first terminal of which is electrically connected to the first node, and a second terminal of which is electrically connected to a DC voltage terminal. The capacitance value of the first capacitor is less than or equal to 1 / 5 of the capacitance value of the storage capacitor, and the capacitance value of the first capacitor is greater than or equal to 1fF.

22. The pixel circuit as claimed in claim 18 or 20, wherein, It also includes a third initialization circuit; The third initialization circuit is electrically connected to the third initial control terminal, the third initial voltage terminal, and the first electrode of the light-emitting element, respectively, and is used to write the third initial voltage provided by the third initial voltage terminal into the first electrode of the light-emitting element under the control of the third initial control signal provided by the third initial control terminal.

23. The pixel circuit as claimed in claim 18, wherein, The second light-emitting control circuit includes a seventh transistor, and the first light-emitting control circuit includes an eighth transistor; the data writing circuit includes a ninth transistor; and the energy storage circuit includes a storage capacitor. The gate of the seventh transistor is electrically connected to the light-emitting control terminal, the first terminal of the seventh transistor is electrically connected to the power supply voltage terminal, and the second terminal of the seventh transistor is electrically connected to the second node. The gate of the eighth transistor is electrically connected to the light-emitting control terminal, the first terminal of the eighth transistor is electrically connected to the third node, and the second terminal of the eighth transistor is electrically connected to the first terminal of the light-emitting element. The gate of the ninth transistor is electrically connected to the nth scanning terminal, the first terminal of the ninth transistor is electrically connected to the data line, and the second terminal of the ninth transistor is electrically connected to the second node. The first end of the storage capacitor is electrically connected to the first node, and the second end of the storage capacitor is electrically connected to the DC voltage terminal.

24. The pixel circuit of claim 20, wherein, The second light-emitting control circuit includes a seventh transistor; the data writing circuit includes a ninth transistor; and the energy storage circuit includes a storage capacitor. The gate of the seventh transistor is electrically connected to the second light-emitting control signal terminal, the first terminal of the seventh transistor is electrically connected to the power supply voltage terminal, and the second terminal of the seventh transistor is electrically connected to the second node. The gate of the ninth transistor is electrically connected to the nth gate driving terminal, the first terminal of the ninth transistor is electrically connected to the data line, and the second terminal of the ninth transistor is electrically connected to the second node. The first end of the storage capacitor is electrically connected to the first node, and the second end of the storage capacitor is electrically connected to the DC voltage terminal.

25. The pixel circuit as claimed in claim 22, wherein, The third initialization circuit includes a tenth transistor; The gate of the tenth transistor is electrically connected to the third initial control terminal, the first terminal of the tenth transistor is electrically connected to the third initial voltage terminal, and the second terminal of the tenth transistor is electrically connected to the first terminal of the light-emitting element.

26. A driving method applied to a pixel circuit as described in any one of claims 1 to 25, wherein refreshing a frame includes a compensation stage and a first hysteresis improvement stage set sequentially; the driving method includes: During the compensation phase, the first control circuit, under the control of the first control signal, controls the connection between the first node and the fourth node; The second control circuit, under the control of the second control signal, controls the connection between the fourth node and the third node; In the first hysteresis improvement stage, the first initialization circuit, under the control of the first initial control signal, writes the first initial voltage into the fourth node, and the second control circuit, under the control of the second control signal, controls the connection between the fourth node and the third node.

27. The driving method as described in claim 26, wherein, The refresh frame further includes a first voltage control stage and a first light emission stage, which are set sequentially after the first hysteresis improvement stage; the pixel circuit further includes a voltage control circuit, a light emission element, a first light emission control circuit, and a second light emission control circuit; the driving method further includes: During the first voltage control phase, the potential of the control voltage provided by the control voltage terminal is pulled down, and the voltage control circuit controls the potential of the fourth node to become lower according to the control voltage. During the first light-emitting stage, the second light-emitting control circuit, under the control of the light-emitting control signal, controls the connection between the power supply voltage terminal and the second node; the first light-emitting control circuit, under the control of the light-emitting control signal, controls the connection between the third node and the first electrode of the light-emitting element.

28. The driving method as described in claim 26, wherein, The pixel circuit further includes a voltage control circuit; the voltage control circuit is electrically connected to the fourth node and the third node respectively, and is used to control the potential of the fourth node according to the potential of the third node; The refresh frame also includes a first light emission stage set after the first hysteresis improvement stage; The driving method further includes: At the start of the first light-emitting stage, the voltage control circuit controls the potential of the fourth node to decrease according to the potential of the third node.

29. The driving method as described in claim 26, wherein, The frame holding includes a second hysteresis improvement phase; the driving method includes: In the second hysteresis improvement stage, the first initialization circuit, under the control of the first initial control signal, writes the first initial voltage into the fourth node, and the second control circuit, under the control of the second control signal, controls the connection between the fourth node and the third node.

30. The driving method as described in claim 29, wherein, The pixel circuit further includes a voltage control circuit; the voltage control circuit is electrically connected to the fourth node and the third node respectively, and is used to control the potential of the fourth node according to the potential of the third node; The holding frame further includes a second emission stage set after the second hysteresis improvement stage; the driving method further includes: At the start of the second light-emitting stage, the voltage control circuit controls the potential of the fourth node to decrease according to the potential of the third node.

31. A display device comprising a pixel circuit as described in any one of claims 1 to 25.

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