Data processing method, apparatus and system

Abstract

Disclosed in embodiments of the present application are a data processing method, apparatus and system. Specifically, the method comprises: firstly, acquiring p first data streams having undergone RS encoding; then, respectively performing first data processing, which comprises FEC encoding and first interleaving, on the p first data streams to obtain m second data streams, m being an integer greater than or equal to p; and performing second data processing, which comprises second interleaving, dual-polarization (DP)-16QAM symbol mapping and framing, on the m second data streams to obtain one first DP symbol stream, wherein the first DP symbol stream comprises a symbol stream in a first polarization direction and a symbol stream in a second polarization direction. By means of the method, a concatenated FEC transmission scheme is simple to implement, has low power consumption and relatively high burst tolerance, can be applied to more transmission scenarios, and is particularly applicable to actual coherent transmission scenarios where colored noise exists in a channel.

Description

Data processing method, device and system

[0001] This application claims priority to Chinese Patent Application No. 202410518237.2, filed with the State Intellectual Property Office of China on April 25, 2024, entitled “A Data Processing Method, Apparatus and System”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of communication technology, and in particular to a data processing method, apparatus and system. Background Technology

[0003] Driven by technologies such as 5G, cloud computing, big data, and artificial intelligence, high-speed optical transmission networks are developing towards higher capacity, packetization, and intelligence. Optical communication systems utilize the amplitude, phase, polarization, or frequency of light waves to carry information. Forward error correction (FEC) coding is used to correct transmission errors, allowing the receiver to recover the original data sent by the transmitter from the received data. A cascaded FEC transmission scheme is proposed, where the transmitting device and the transmitting processing module are connected via a connection unit interface. The transmitting device performs a first FEC encoding on the data to be transmitted and sends the first FEC-encoded data to the transmitting processing module. The transmitting processing module then performs a second FEC encoding on the first FEC-encoded data, modulates the bit sequence resulting from the second FEC encoding to generate a corresponding modulation symbol sequence, and finally generates an optical signal based on the modulation symbol sequence, which is then transmitted to the receiver via optical fiber.

[0004] Typically, interleaving can be performed before and / or after the second FEC coding to shuffle the data order, thereby enhancing the overall error correction performance of the FEC scheme. However, during actual transmission, burst factors can affect the transmission link, causing errors in several consecutive symbols in the modulation symbol sequence. The receiving end receives the burst-affected modulation symbol sequence. Due to the large number of consecutive errors, accurate error correction through the second FEC code is difficult, resulting in a high bit error rate in information transmission. In other words, the existing concatenated FEC coding schemes have poor burst resistance. Furthermore, existing concatenated FEC coding and interleaving schemes for coherent transmission scenarios are mainly applied to 800Gbps scenarios and do not consider the requirements for compatibility with next-generation rates, especially the data structure of next-generation transmitting equipment data streams. They cannot adapt to future scenarios above 800Gbps (such as 1.6Tbps), which is a problem that urgently needs to be solved in the future. Summary of the Invention

[0005] This application provides a data processing method, apparatus, and system. These enable the cascaded FEC transmission scheme to be simple to implement, consumes low power, has strong burst resistance, and can be applied to a wide range of transmission scenarios, especially suitable for actual coherent transmission scenarios where the channel contains colored noise.

[0006] Firstly, embodiments of this application provide a data processing method. Specifically, firstly, p first data streams encoded using Reed-Solomon (RS) are acquired, where p is a positive integer multiple of 4 and a power of 2. Each first data stream contains a... RS The adjacent RS symbols are respectively from a RS One RS codeword, a RS The first data stream is a power of 2 greater than or equal to 4. Then, the p first data streams are subjected to first data processing including FEC encoding and first interleaving to obtain m second data streams, where m is an integer greater than or equal to p. Next, the m second data streams are subjected to second data processing including second interleaving, dual-polarization 16-ary Quadrature Amplitude Modulation (DP-16QAM) symbol mapping, and framing to obtain one first dual-polarization symbol stream. The first dual-polarization symbol stream includes a symbol stream in the first polarization direction and a symbol stream in the second polarization direction.

[0007] In this embodiment, the provided cascaded FEC transmission scheme is simple to implement and has low power consumption. Because a second interleaving is introduced before DP-16QAM symbol mapping and framing, it helps reduce the impact of polarization-determined loss (PDL) in the X and Y polarization directions, exhibiting strong burst resistance and applicability to a wide range of transmission scenarios, especially suitable for practical coherent transmission scenarios where the channel has colored noise.

[0008] In some possible implementations, in scenarios where m > p, performing first data processing, including FEC encoding and first interleaving, on each of the p first data streams to obtain m second data streams includes: distributing each of the p first data streams to obtain m / p first sub-data streams, and then performing FEC encoding and first interleaving on each of the m first sub-data streams to obtain m second data streams. In this implementation, the distribution operation allows for better scalability of the data processing method, enriching the implementation of this solution. In particular, when m = 32, this data processing method is well compatible with existing 800G coherent cascaded FEC processing architectures.

[0009] In some possible implementations, each first sub-data stream obtained by distributing from a first data stream comprises K consecutive bits from the first data stream, where K is a positive integer, and K is the number of information bits involved in FEC encoding. For example, this adapts to an FEC encoding scheme where N=128 and K=120. Another example is an FEC encoding scheme where N=176 and K=160. Alternatively, each first sub-data stream obtained by distributing from a first data stream comprises K0 consecutive bits from the first data stream, where K0 is an integer multiple of 40. For example, if K is not an integer multiple of 40... in, This indicates rounding down to the nearest integer. For example, K = 110. It can adapt to FEC encoding schemes with N=126 and K=110. Multiple granularities for distributing the first data stream are provided to facilitate adaptation to different FEC encoding schemes.

[0010] In some possible implementations, performing first data processing, including FEC encoding and first interleaving, on p first data streams to obtain m second data streams includes: performing convolutional interleaving on each of the p first data streams; distributing each of the p convolutionally interleaved first data streams to obtain m / p first sub-data streams; and performing FEC encoding and first interleaving on each of the m first sub-data streams to obtain m second data streams. It should be understood that performing convolutional interleaving is beneficial for improving the performance of the cascaded FEC transmission scheme.

[0011] In some possible implementations, performing first data processing, including FEC encoding and first interleaving, on p first data streams to obtain m second data streams includes: performing convolutional interleaving on each of the p first data streams, and then performing FEC encoding and first interleaving on the convolutionally interleaved p first data streams to obtain m second data streams. In this implementation, convolutional interleaving and distribution are decoupled, enriching the implementation methods of this solution.

[0012] In some possible implementations, convolutional interleaving of a first data stream includes: delaying bits from the first data stream according to r delay lines, where r is an integer greater than 1; each delay line includes a different number of storage units, with the delay line having the fewest storage units containing 0 units; the difference in the number of storage units between any two adjacent delay lines is Q; each storage unit stores d bits; the input bits are sequentially input to the r delay lines according to their indices; d bits are input to each delay line at a time and d bits are output from each delay line at a time; where Q and d are both integers greater than or equal to 1. It should be understood that the aforementioned storage units are also called delay elements.

[0013] In some possible implementations, the delay line with the largest index among the r delay lines includes 0 storage units, or the delay line with the smallest index among the r delay lines includes 0 storage units. This provides several different implementations of convolutional interleaving to facilitate adaptation to various application scenarios.

[0014] In some possible implementations, d = a RS ×10.

[0015] In some possible implementations, a RS =4 or 8.

[0016] In some possible implementations, the delay line with the largest index among the r delay lines includes 0 memory units, or the delay line with the smallest index among the r delay lines includes 0 memory units, p = 8, r = 3, d = 40, Q ≥ 23. To reduce the difficulty of high-speed implementation of the convolutional interleaver, Q is considered to be a multiple of 2, 4, or 8, for example, Q = 24. Alternatively, the delay line with the largest index among the r delay lines includes 0 memory units, p = 16, r = 3, d = 40, Q ≥ 11. To reduce the difficulty of high-speed implementation of the convolutional interleaver, Q is considered to be a multiple of 2, 4, or 8, for example, Q = 12, 14, or 16. Alternatively, the delay line with the smallest index among the r delay lines includes 0 memory units, p = 16, r = 3, d = 40, Q ≥ 12. To reduce the difficulty of high-speed implementation of the convolutional interleaver, Q is considered to be a multiple of 2, 4, or 8, for example, Q = 12, 14, or 16. Alternatively, the delay line with the largest sequence number among the r delay lines includes 0 storage units, p=4, r=3, d=40, Q≥45. To reduce the difficulty of high-speed implementation of the convolutional interleaver, consider Q to be a multiple of 2, 4, or 8, such as Q=46 or 48. Or, the delay line with the smallest sequence number among the r delay lines includes 0 storage units, p=4, r=3, d=40, Q≥46. To reduce the difficulty of high-speed implementation of the convolutional interleaver, consider Q to be a multiple of 2, 4, or 8, such as Q=46 or 48. By selecting appropriate r, d, and Q parameters and convolutional interleaving implementation methods for different p values, any 12 consecutive RS symbols in the convolutionally interleaved data stream can come from 12 different RS codewords. This can be used in FEC encoding schemes such as N=128, K=120, allowing the FEC concatenation scheme including RS encoding and internal code encoding to achieve optimal performance. Alternatively, by selecting appropriate r, d, and Q parameters and the implementation method of convolutional interleaving, any 11 consecutive RS symbols in the convolutionally interleaved data stream can come from 11 different RS codewords. This can be used in FEC encoding methods with N=126 and K=110, which can make the FEC concatenation scheme including RS encoding and internal code encoding have optimal performance.

[0017] In some possible implementations, the delay line with the largest index among the r delay lines includes 0 memory units, p = 4, r = 4, d = 40, and Q ≥ 34. To reduce the difficulty of high-speed implementation of the convolutional interleaver, Q is considered to be a multiple of 2, 4, or 8, for example, Q = 36, 38, or 40. Alternatively, the delay line with the smallest index among the r delay lines includes 0 memory units, p = 4, r = 4, d = 40, and Q ≥ 35. To reduce the difficulty of high-speed implementation of the convolutional interleaver, Q is considered to be a multiple of 2, 4, or 8, for example, Q = 36, 38, or 40. Alternatively, the delay line with the largest index among the r delay lines includes 0 memory units, p = 8, r = 4, d = 40, and Q ≥ 17. To reduce the difficulty of high-speed implementation of the convolutional interleaver, Q is considered to be a multiple of 2, 4, or 8, for example, Q = 18, 20, or 24. Alternatively, the delay line with the smallest sequence number among the r delay lines may have 0 memory units, p=8, r=4, d=40, Q≥18. To reduce the difficulty of high-speed implementation of the convolutional interleaver, Q can be a multiple of 2, 4, or 8, such as Q=18, 20, or 24. Alternatively, the delay line with the largest sequence number among the r delay lines may have 0 memory units, or the delay line with the smallest sequence number among the r delay lines may have 0 memory units, p=16, r=4, d=40, Q≥9. To reduce the difficulty of high-speed implementation of the convolutional interleaver, Q can be a multiple of 2, 4, or 8, such as Q=10, 12, or 16. By selecting appropriate r, d, and Q parameters and the implementation method of convolutional interleaver, any 16 consecutive RS symbols in the convolutionally interleaved data stream can come from 16 different RS codewords. This can be used in FEC encoding schemes such as N=176, K=160, allowing the FEC concatenation scheme including RS encoding and internal code encoding to achieve optimal performance.

[0018] In some possible implementations, the number of information bits involved in FEC encoding is K, each codeword after FEC encoding includes N bits, and the NK parity bits in the codeword are obtained by FEC encoding the K information bits. The first interleaving is used to cyclically shift every K information bits in the first data stream. A specific implementation of the first interleaving is provided here. By using the first interleaving to shuffle the order of the K information bits, it is beneficial to improve the burst resistance of the overall concatenated code.

[0019] In some possible implementations, p = 4, and the first interleaving is used to cyclically shift every K information bits in the first data stream i. 4 bits, 0≤i<4 Satisfy one of the following:

[0020] Alternatively, p=8, where the first interleaving is used to cyclically shift every K information bits in the first data stream i. 8 bits, 0≤i<8 Satisfy one of the following:

[0021] Alternatively, p = 16, where the first interleaving is used to cyclically shift every K information bits in the first data stream i. 16 bits, 0≤i<16 Satisfy one of the following:

[0022] In some possible implementations, the first data processing, including FEC encoding and first interleaving, of the first data stream includes one of the following methods: Method 1: Perform first interleaving on the first data stream, and then perform FEC encoding on the first interleaved first data stream. Method 2: Perform FEC encoding on the first data stream, and then perform first interleaving on the FEC-encoded first data stream. Method 3: Perform FEC encoding on K information bits in the first data stream to obtain NK parity bits, and then perform first interleaving on the K information bits to obtain N bits including NK parity bits and the first interleaved K information bits, where K is a positive integer and N > K. Multiple implementations of the first data processing are provided here, improving the scalability of this scheme.

[0023] In some possible implementations, performing a second interleaving and DP-16QAM symbol mapping on m second data streams includes: acquiring N bits from each second data stream to obtain m×N bits, where the N bits include K information bits and NK parity bits from the FEC-encoded codeword; performing a second interleaving on the m×N bits; and performing DP-16QAM symbol mapping on the m×N bits after the second interleaving to obtain N×m / 8 DP-16QAM symbols. In other words, one codeword is acquired from each second data stream to obtain a total of m codewords, and these m codewords are combined for a second interleaving to shuffle the bit order, thereby improving the overall burst resistance of the concatenated code.

[0024] In some possible implementations, p = 8, m = 8. This represents the j0th bit out of the N bits obtained from the i0th second data stream, where 0 ≤ i0 ≤ 7 and 0 ≤ j0 ≤ N-1, and is mapped to the 8 bits of the i-th DP-16QAM symbol as follows: 0≤i≤N-1, From It should be understood that this mapping method allows N bits in the second data stream to be uniformly mapped to 16QAM symbols in the X-polarization and Y-polarization directions, which is beneficial for combating PDL impairments.

[0025] In some possible implementations, The i-th bit from the N bits of the (i+4)%8th second data stream;

[0026] The i-th bit from the N bits of the (i+5)%8th second data stream;

[0027] The i-th bit from the N bits of the (i+6)%8th second data stream;

[0028] The i-th bit from the N bits of the (i+7)%8th second data stream;

[0029] The i-th bit from the N bits of the (i)%8th second data stream;

[0030] The i-th bit from the N bits of the (i+1)%8th second data stream;

[0031] The i-th bit from the N bits of the (i+2)%8th second data stream;

[0032] The i-th bit from the N bits of the (i+3)%8th second data stream.

[0033] It should be understood that this mapping method allows N bits in the second data stream to be uniformly mapped to 16QAM symbols in the X-polarization and Y-polarization directions, which is beneficial for combating PDL impairments.

[0034] In some possible implementations, performing second data processing on m second data streams, including second interleaving, DP-16QAM symbol mapping, and framing, to obtain one first dual-polarization symbol stream includes one of the following methods, enriching the application scenarios of this scheme. Method 1: Perform second interleaving and DP-16QAM symbol mapping on m second data streams to obtain a second dual-polarization symbol stream, and insert target symbol sequences into the second dual-polarization symbol streams to obtain a first dual-polarization symbol stream. Method 2: Perform second interleaving on m second data streams to obtain one third data stream, insert target bit sequences into the third data stream to obtain a fourth data stream, and perform DP-16QAM symbol mapping on the fourth data stream to obtain a first dual-polarization symbol stream, wherein the target bit sequence is processed through DP-16QAM symbol mapping to obtain the target symbol sequence. Method 3: Perform a second interleaving on m second data streams to obtain two third data streams. Insert the target bit sequence into each of the two third data streams to obtain two fourth bit streams. Perform DP-16QAM symbol mapping on the two fourth bit streams to obtain a first dual-polarized symbol stream. The target bit sequence is then processed by DP-16QAM symbol mapping to obtain the target symbol sequence. Method 4: Perform a second interleaving on m second data streams to obtain four third data streams. Insert the I component of the target bit sequence into two of the four third data streams and the Q component of the target bit sequence into the other two third data streams to obtain four fourth bit streams. Perform DP-16QAM symbol mapping on the four fourth bit streams to obtain a first dual-polarized symbol stream. The I component of the target bit sequence is then processed by DP-16QAM symbol mapping to obtain the I component of the target symbol sequence, and the Q component of the target bit sequence is processed by DP-16QAM symbol mapping to obtain the Q component of the target symbol sequence.

[0035] In some possible implementations, the first dual-polarization symbol stream includes multiple dual-polarization symbol sequences, and a target symbol sequence is included at a fixed position in each dual-polarization symbol sequence. The target symbol sequence includes at least one of the following: frame synchronization symbol sequence, training symbol sequence, reserved symbol sequence, and pilot symbol sequence, so as to flexibly select the target symbol sequence to be inserted according to actual needs.

[0036] In some possible implementations, each codeword after FEC encoding includes K information bits and NK parity bits, for a total of N bits; N=128, K=120, or N=126, K=110, or N=176, K=160, which allows for flexible selection of the FEC encoding method according to actual needs.

[0037] In some possible implementations, m = 4, 8, 16 or 32, thus allowing for compatibility with a variety of different scenarios.

[0038] In some possible implementations, every four adjacent RS symbols in each first data stream come from four RS codewords, resulting in better resistance to colored noise.

[0039] In some possible implementations, p first data streams are obtained by processing 16 fifth data streams through a symbol-multiplexed Physical Media Attachment (PMA) layer. These 16 fifth data streams are obtained by processing the service data to be transmitted through a Physical Coding Sublayer (PCS) including RS encoding. This provides a specific implementation method for processing the service data to be transmitted to obtain p first data streams, improving the completeness of this solution.

[0040] In some possible implementations, p first data streams are obtained from t signals through t:p PMA processing, and t signals are obtained from 16 fifth data streams through 16:t PMA processing, where t is a positive integer multiple of 4. This provides a scheme for obtaining p first data streams by performing two-step PMA processing on the data streams after PCS processing, which is well compatible with the application scenario shown in Figure 2. One step of the PMA processing is performed by the sending device, and the other step is performed by the sending processing module.

[0041] In some possible implementations, p first data streams are obtained by processing 16 fifth data streams through 16:p PMA. Here, a scheme is provided to obtain p first data streams by performing a one-step PMA process on the data streams after PCS processing, which is well compatible with the application scenario shown in Figure 3. This PMA process is performed by the originating device.

[0042] In some possible implementations, the p first data streams are obtained from t signals through t:p PMA processing based on symbol multiplexing. That is, for the application scenario shown in Figure 2, the sending processing module obtains the p first data streams by performing t:p PMA processing based on symbol multiplexing on t signals from the sending device, thus improving the data processing flow of the sending processing module.

[0043] In some possible implementations, t = 8, p = 8; or t = 16, p = 8; or t = 4, p = 8; or t = 8, p = 16; or t = 16, p = 16; or t = 4, p = 16; or t = 4, p = 4; or t = 8, p = 4. Several possible implementations of the t:p PMA processing are given here, improving the scalability of this solution.

[0044] In some possible implementations, p first data streams are obtained from the service data to be sent through PCS processing, including RS encoding. This provides a method to directly obtain p first data streams by PCS processing of the service data to be sent, without requiring PMA processing, allowing for flexible selection of different implementation methods according to actual needs.

[0045] In some possible implementations, the data processing method provided in this application is applied to scenarios including Ethernet, optical transport networks, and space optical communication.

[0046] Secondly, embodiments of this application provide a data processing apparatus, which includes an acquisition unit and a processing unit. The acquisition unit is used to acquire p first data streams encoded by Reed-Solomon RS, where p is a positive integer multiple of 4 and p is an integer power of 2. Each first data stream contains a... RS The adjacent RS symbols are respectively from a RS One RS codeword, a RS The integer power of 2 is greater than or equal to 4. The processing unit is used to: perform first data processing, including forward error correction (FEC) coding and first interleaving, on p first data streams to obtain m second data streams, where m is an integer greater than or equal to p; and perform second data processing, including second interleaving, DP-16QAM symbol mapping and framing, on the m second data streams to obtain 1 first dual-polarization symbol stream.

[0047] In some possible implementations, in the scenario where m > p, the processing unit is specifically used to: distribute each of the p first data streams to obtain m / p first sub-data streams, to obtain m first sub-data streams, and perform FEC encoding and first interleaving on the m first sub-data streams respectively to obtain m second data streams.

[0048] In some possible implementations, each first sub-data stream obtained by distributing from a first data stream comprises K consecutive bits from the first data stream, where K is a positive integer, and K is the number of information bits involved in FEC encoding. For example, this adapts to an FEC encoding scheme where N=128 and K=120. Another example is an FEC encoding scheme where N=176 and K=160. Alternatively, each first sub-data stream obtained by distributing from a first data stream comprises K0 consecutive bits from the first data stream, where K0 is an integer multiple of 40. For example, if K is not an integer multiple of 40... in, This indicates rounding down to the nearest integer. For example, K = 110. It can adapt to FEC encoding schemes with N=126 and K=110. Multiple granularities for distributing the first data stream are provided to facilitate adaptation to different FEC encoding schemes.

[0049] In some possible implementations, the processing unit is specifically used to: perform convolutional interleaving on p first data streams respectively, distribute each of the p first data streams after convolutional interleaving to obtain m / p first sub-data streams, to obtain m first sub-data streams, and perform FEC encoding and first interleaving on the m first sub-data streams respectively to obtain m second data streams.

[0050] In some possible implementations, the processing unit is specifically used to: perform convolutional interleaving on p first data streams respectively, and perform FEC encoding and first interleaving on the p first data streams after convolutional interleaving to obtain m second data streams.

[0051] In some possible implementations, the processing unit is specifically used to: delay bits from the first data stream according to r delay lines, where r is an integer greater than 1, each delay line includes a different number of storage units, the delay line with the smallest number of storage units includes 0 storage units, the difference in the number of storage units between any two adjacent delay lines is Q, each storage unit is used to store d bits, the input bits are sequentially input to the r delay lines according to the sequence number of the r delay lines, d bits are input to each delay line at a time and d bits are output from each delay line at a time, where Q and d are both integers greater than or equal to 1.

[0052] In some possible implementations, the delay line with the largest index among the r delay lines includes 0 storage units, or the delay line with the smallest index among the r delay lines includes 0 storage units. This provides several different implementations of convolutional interleaving to facilitate adaptation to various application scenarios.

[0053] In some possible implementations, d = a RS ×10.

[0054] In some possible implementations, a RS =4 or 8.

[0055] In some possible implementations, the delay line with the largest index among the r delay lines includes 0 memory units, or the delay line with the smallest index among the r delay lines includes 0 memory units, p = 8, r = 3, d = 40, Q ≥ 23. To reduce the difficulty of high-speed implementation of the convolutional interleaver, Q is considered to be a multiple of 2, 4, or 8, for example, Q = 24. Alternatively, the delay line with the largest index among the r delay lines includes 0 memory units, p = 16, r = 3, d = 40, Q ≥ 11. To reduce the difficulty of high-speed implementation of the convolutional interleaver, Q is considered to be a multiple of 2, 4, or 8, for example, Q = 12, 14, or 16. Alternatively, the delay line with the smallest index among the r delay lines includes 0 memory units, p = 16, r = 3, d = 40, Q ≥ 12. To reduce the difficulty of high-speed implementation of the convolutional interleaver, Q is considered to be a multiple of 2, 4, or 8, for example, Q = 12, 14, or 16. Alternatively, the delay line with the largest sequence number among the r delay lines may have 0 memory units, p=4, r=3, d=40, Q≥45. To reduce the difficulty of high-speed implementation of the convolutional interleaver, Q can be a multiple of 2, 4, or 8, such as Q=46 or 48. Or, the delay line with the smallest sequence number among the r delay lines may have 0 memory units, p=4, r=3, d=40, Q≥46. To reduce the difficulty of high-speed implementation of the convolutional interleaver, Q can be a multiple of 2, 4, or 8, such as Q=46 or 48. By selecting appropriate r, d, and Q parameters and convolutional interleaving implementation methods for different p values, any 12 consecutive RS symbols in the convolutionally interleaved data stream can come from 12 different RS codewords, which can be used in FEC encoding schemes such as N=128, K=120. Alternatively, by selecting appropriate r, d, and Q parameters and the implementation method of convolutional interleaving, any 11 consecutive RS symbols in the convolutionally interleaved data stream can come from 11 different RS codewords, which can be used in FEC encoding methods such as N=126 and K=110.

[0056] In some possible implementations, the delay line with the largest index among the r delay lines includes 0 memory units, p = 4, r = 4, d = 40, and Q ≥ 34. To reduce the difficulty of high-speed implementation of the convolutional interleaver, Q is considered to be a multiple of 2, 4, or 8, for example, Q = 36, 38, or 40. Alternatively, the delay line with the smallest index among the r delay lines includes 0 memory units, p = 4, r = 4, d = 40, and Q ≥ 35. To reduce the difficulty of high-speed implementation of the convolutional interleaver, Q is considered to be a multiple of 2, 4, or 8, for example, Q = 36, 38, or 40. Alternatively, the delay line with the largest index among the r delay lines includes 0 memory units, p = 8, r = 4, d = 40, and Q ≥ 17. To reduce the difficulty of high-speed implementation of the convolutional interleaver, Q is considered to be a multiple of 2, 4, or 8, for example, Q = 18, 20, or 24. Alternatively, the delay line with the smallest sequence number among the r delay lines can have 0 memory units, p=8, r=4, d=40, Q≥18. To reduce the difficulty of high-speed implementation of the convolutional interleaver, consider Q to be a multiple of 2, 4, or 8, such as Q=18, 20, or 24. Alternatively, the delay line with the largest sequence number among the r delay lines can have 0 memory units, or the delay line with the smallest sequence number among the r delay lines can have 0 memory units, p=16, r=4, d=40, Q≥9. To reduce the difficulty of high-speed implementation of the convolutional interleaver, consider Q to be a multiple of 2, 4, or 8, such as Q=10, 12, or 16. By selecting appropriate r, d, and Q parameters and the implementation method of convolutional interleaver, any 16 consecutive RS symbols in the convolutionally interleaved data stream can come from 16 different RS codewords, which can be used in FEC encoding schemes such as N=176, K=160.

[0057] In some possible implementations, the number of information bits involved in FEC encoding is K, each codeword after FEC encoding includes N bits, the NK parity bits in the codeword are obtained by FEC encoding the K information bits, and the first interleaving is used to cyclically shift each K information bits in the first data stream.

[0058] In some possible implementations, p = 4, and the first interleaving is used to cyclically shift every K information bits in the first data stream i. 4 bits, 0≤i<4 Satisfy one of the following:

[0059] Alternatively, p=8, where the first interleaving is used to cyclically shift every K information bits in the first data stream i. 8 bits, 0≤i<8 Satisfy one of the following:

[0060] Alternatively, p = 16, where the first interleaving is used to cyclically shift every K information bits in the first data stream i. 16 bits, 0≤i<16 Satisfy one of the following:

[0061] In some possible implementations, the processing unit is specifically configured to perform one of the following methods: Method 1: Perform a first interleaving on the first data stream, and then perform FEC encoding on the first interleaved first data stream. Method 2: Perform FEC encoding on the first data stream, and then perform a first interleaving on the FEC-encoded first data stream. Method 3: Perform FEC encoding on K information bits in the first data stream to obtain NK parity bits, and then perform a first interleaving on the K information bits to obtain N bits including the NK parity bits and the K information bits after the first interleaving, where K is a positive integer and N > K.

[0062] In some possible implementations, the processing unit is specifically configured to: acquire N bits from each second data stream to obtain m×N bits, wherein the N bits include K information bits and NK parity bits in the codeword encoded by FEC; perform a second interleaving on the m×N bits; and perform DP-16QAM symbol mapping on the m×N bits after the second interleaving to obtain N×m / 8 DP-16QAM symbols.

[0063] In some possible implementations, p = 8, m = 8. This represents the j0th bit out of the N bits obtained from the i0th second data stream, where 0 ≤ i0 ≤ 7 and 0 ≤ j0 ≤ N-1, and is mapped to the 8 bits of the i-th DP-16QAM symbol as follows: 0≤i≤N-1, From

[0064] In some possible implementations, The i-th bit from the N bits of the (i+4)%8th second data stream;

[0065] The i-th bit from the N bits of the (i+5)%8th second data stream;

[0066] The i-th bit from the N bits of the (i+6)%8th second data stream;

[0067] The i-th bit from the N bits of the (i+7)%8th second data stream;

[0068] The i-th bit from the N bits of the (i)%8th second data stream;

[0069] The i-th bit from the N bits of the (i+1)%8th second data stream;

[0070] The i-th bit from the N bits of the (i+2)%8th second data stream;

[0071] The i-th bit from the N bits of the (i+3)%8th second data stream.

[0072] In some possible implementations, the processing unit is specifically used to perform one of the following methods: Method 1: Perform a second interleaving and DP-16QAM symbol mapping on m second data streams to obtain a second dual-polarized symbol stream, and insert a target symbol sequence into each of the second dual-polarized symbol streams to obtain a first dual-polarized symbol stream. Method 2: Perform a second interleaving on m second data streams to obtain one third data stream, insert a target bit sequence into the third data stream to obtain a fourth data stream, and perform DP-16QAM symbol mapping on the fourth data stream to obtain a first dual-polarized symbol stream, wherein the target bit sequence is processed through DP-16QAM symbol mapping to obtain a target symbol sequence. Method 3: Perform a second interleaving on m second data streams to obtain two third data streams, insert a target bit sequence into each of the two third data streams to obtain two fourth bit streams, and perform DP-16QAM symbol mapping on the two fourth bit streams to obtain a first dual-polarized symbol stream, wherein the target bit sequence is processed through DP-16QAM symbol mapping to obtain a target symbol sequence. Method 4: Perform a second interleaving on m second data streams to obtain 4 third data streams. Insert the I component of the target bit sequence into 2 of the 4 third data streams respectively, and insert the Q component of the target bit sequence into the other 2 of the 4 third data streams respectively to obtain 4 fourth bit streams. Perform DP-16QAM symbol mapping on the 4 fourth bit streams to obtain a first dual-polarization symbol stream. The I component of the target bit sequence is mapped by DP-16QAM to obtain the I component of the target symbol sequence, and the Q component of the target bit sequence is mapped by DP-16QAM to obtain the Q component of the target symbol sequence.

[0073] In some possible implementations, the first dual-polarization symbol stream includes multiple dual-polarization symbol sequences, and a target symbol sequence is included at a fixed position in each dual-polarization symbol sequence. The target symbol sequence includes at least one of the following: frame synchronization symbol sequence, training symbol sequence, reserved symbol sequence, and pilot symbol sequence, so as to flexibly select the target symbol sequence to be inserted according to actual needs.

[0074] In some possible implementations, each codeword encoded by FEC includes K information bits and NK parity bits, for a total of N bits; N = 128, K = 120, or N = 126, K = 110, or N = 176, K = 160.

[0075] In some possible implementations, m = 8, 16, or 32.

[0076] In some possible implementations, every four adjacent RS symbols in each first data stream come from four RS codewords.

[0077] In some possible implementations, p first data streams are obtained by PMA processing based on symbol multiplexing from 16 fifth data streams, and the 16 fifth data streams are obtained by PCS processing including RS encoding from the service data to be sent.

[0078] In some possible implementations, p first data streams are obtained by processing t signals through t:p PMA, and t signals are obtained by processing 16 fifth data streams through 16:t PMA, where t is a positive integer multiple of 4.

[0079] In some possible implementations, p first data streams are obtained by processing 16 fifth data streams through 16:p PMA.

[0080] In some possible implementations, p first data streams are obtained from t signals through t:p PMA processing based on symbol multiplexing.

[0081] In some possible implementations, t = 8, p = 8; or t = 16, p = 8; or t = 4, p = 8; or t = 8, p = 16; or t = 16, p = 16; or t = 4, p = 16; or t = 4, p = 4; or t = 8, p = 4.

[0082] In some possible implementations, p first data streams are obtained from the service data to be sent through PCS processing, including RS encoding.

[0083] In some possible implementations, the data processing apparatus provided in this application is used in scenarios including Ethernet, optical transport networks, and space optical communication.

[0084] Thirdly, embodiments of this application provide a chip for performing the method as described in any of the embodiments of the first aspect.

[0085] Fourthly, embodiments of this application provide an optical module. The optical module includes a processor and an interface. The processor is used to execute the methods described in any embodiment of the first aspect and to transmit signals through the interface. For example, the interface is used to transmit signals from the processor or to transmit received signals to the processor.

[0086] Fifthly, embodiments of this application provide a transmitting device. The transmitting device includes a host-side device and an optical module as described in any embodiment of the fourth aspect. The optical module is used to generate an optical signal based on data from the host-side device and to transmit the optical signal.

[0087] Sixthly, embodiments of this application provide an apparatus. The apparatus includes a processor and an interface. The processor is used to execute the method described in any embodiment of the first aspect and to transmit signals through the interface. For example, the interface is used to transmit signals from the processor or to transmit received signals to the processor. The apparatus may be a router, switch, server, or optical transport network equipment, etc.

[0088] In a seventh aspect, embodiments of this application provide a communication system, which includes the transmitting device and receiving device described in the fifth aspect, wherein the transmitting device is used to transmit optical signals to the receiving device.

[0089] Eighthly, this application provides a computer-readable storage medium storing instructions that, when executed by a computer, cause the method described in any embodiment of the first aspect to be implemented.

[0090] Ninthly, this application provides a computer program product including program instructions that, when executed, implement the method described in any of the embodiments of the first aspect. Attached Figure Description

[0091] Figure 1 is a schematic diagram of a communication system applied in an embodiment of this application;

[0092] Figure 2 is a schematic diagram of a data transmission process in the communication system shown in Figure 1;

[0093] Figure 3 is a schematic diagram of another communication system applied in the embodiments of this application;

[0094] Figure 4 is a flowchart illustrating a data processing method provided in an embodiment of this application.

[0095] Figure 5(a) is a schematic diagram of the first structure of convolutional interleaving in an embodiment of this application;

[0096] Figure 5(b) is a schematic diagram of the second structure of convolutional interleaving in an embodiment of this application;

[0097] Figure 6(a) is a schematic diagram of one embodiment of dual polarization symbol mapping and DSP framing in this application;

[0098] Figure 6(b) is a schematic diagram of another implementation of dual polarization symbol mapping and DSP framing in the embodiments of this application;

[0099] Figure 6(c) is a schematic diagram of another implementation of dual polarization symbol mapping and DSP framing in the embodiments of this application;

[0100] Figure 6(d) is a schematic diagram of another implementation of dual polarization symbol mapping and DSP framing in the embodiments of this application;

[0101] Figure 7(a) is a data processing flowchart corresponding to the data processing method in the embodiments of this application;

[0102] Figure 7(b) is another data processing flowchart corresponding to the data processing method in the embodiments of this application;

[0103] Figure 7(c) is another data processing flowchart corresponding to the data processing method in the embodiments of this application;

[0104] Figure 7(d) is another data processing flowchart corresponding to the data processing method in the embodiments of this application;

[0105] Figure 7(e) is another data processing flowchart corresponding to the data processing method in the embodiments of this application;

[0106] Figure 7(f) is another data processing flowchart corresponding to the data processing method in the embodiments of this application;

[0107] Figure 8(a) is another data processing flowchart corresponding to the data processing method in the embodiment of this application;

[0108] Figure 8(b) is another data processing flowchart corresponding to the data processing method in the embodiments of this application;

[0109] Figure 8(c) is another data processing flowchart corresponding to the data processing method in the embodiments of this application;

[0110] Figure 8(d) is another data processing flowchart corresponding to the data processing method in the embodiments of this application;

[0111] Figure 8(e) is another data processing flowchart corresponding to the data processing method in the embodiments of this application;

[0112] Figure 8(f) is another data processing flowchart corresponding to the data processing method in the embodiments of this application;

[0113] Figure 8(g) is another data processing flowchart corresponding to the data processing method in the embodiments of this application;

[0114] Figure 9(a) is a schematic diagram of one embodiment of the present application that performs the first data processing and the second data processing.

[0115] Figure 9(b) is a schematic diagram of another embodiment of the first and second data processing in this application.

[0116] Figure 9(c) is a schematic diagram of another embodiment of the first and second data processing in this application.

[0117] Figure 10(a) is a schematic diagram of another embodiment of the first and second data processing in this application.

[0118] Figure 10(b) is a schematic diagram of another embodiment of the first and second data processing in this application.

[0119] Figure 11(a) is a schematic diagram of another embodiment of the first data processing and the second data processing in this application;

[0120] Figure 11(b) is a schematic diagram of another embodiment of the first and second data processing in this application.

[0121] Figure 11(c) is a schematic diagram of another embodiment of the first data processing and the second data processing in this application.

[0122] Figure 12(a) is a schematic diagram of another embodiment of the first data processing and the second data processing in this application;

[0123] Figure 12(b) is a schematic diagram of another embodiment of the first and second data processing in this application.

[0124] Figure 13 is a schematic diagram of the format of a first data stream in an embodiment of this application;

[0125] Figure 14 is a schematic diagram of one embodiment of convolutional interleaving in this application;

[0126] Figure 15 is a schematic diagram of another implementation of convolutional interleaving in the embodiments of this application;

[0127] Figure 16 is a schematic diagram of one embodiment of the internal code encoding in this application;

[0128] Figure 17 is a schematic diagram of one embodiment of the first interlacing in this application;

[0129] Figure 18 is a schematic diagram of a DSP frame structure in an embodiment of this application;

[0130] Figure 19 is a schematic diagram of an embodiment of the present application that distributes data streams in a 1:4 ratio.

[0131] Figure 20 is a schematic diagram of an embodiment of the present application that performs a 1:2 distribution of data streams;

[0132] Figure 21 is a schematic diagram of a data processing device in an embodiment of this application;

[0133] Figure 22 is a schematic diagram of a structure of an optical module in an embodiment of this application;

[0134] Figure 23 is a schematic diagram of a transmitting device in an embodiment of this application. Detailed Implementation

[0135] This application provides a data processing method, apparatus, and system. This makes the cascaded FEC transmission scheme simple to implement, consumes little power, has strong burst resistance, and can be applied to a wide range of transmission scenarios, especially suitable for actual coherent transmission scenarios where the channel has colored noise.

[0136] It should be noted that the terms "first," "second," etc., in this application specification, claims, and the accompanying drawings are used to distinguish similar objects, not to limit a specific order or sequence. It should be understood that the above terms can be used interchangeably where appropriate so that the embodiments described in this application can be implemented in a sequence other than that described in this application. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or devices.

[0137] Figure 1 is a schematic diagram of a communication system applied in an embodiment of this application. As shown in Figure 1, the communication system includes a transmitting device 01, a transmitting processing module 02, a channel transmission medium 03, a receiving processing module 04, and a receiving device 05. Taking a data center network as an example, the transmitting device 01 and the receiving device 05 can be devices such as switches, routers, or servers. The transmitting device 01 is also called a client device located at the transmitting end, and the receiving device 05 is also called a client device located at the receiving end. The channel transmission medium 03 can be an optical fiber. The client device is sometimes also called a host device. The client device includes a client chip and an interface. The client chip is also called a host chip. The connection interface between the transmitting device 01 and the transmitting processing module 02 can be connected through an attachment unit interface (AUI), and the connection interface between the receiving device 05 and the receiving processing module 04 can be connected through an AUI. The transmitting end processing module 02 and the receiving end processing module 04 can be optical modules, electrical modules, connectors, or other modules that process data during data transmission. For example, the processing module can be an LR optical module, such as a 1600LR module (a coherent optical module). Furthermore, the transmitting end device 01, transmitting end processing module 02, channel transmission medium 03, receiving end processing module 04, and receiving end device 05 in this communication system can all support bidirectional transmission or unidirectional transmission; specific limitations are not specified here.

[0138] Figure 2 is a schematic diagram of a data transmission process in the communication system shown in Figure 1. As shown in Figure 2, during the data transmission process from the transmitting device 01 to the receiving device 05, the transmitting device 01 performs external code encoding on the data and then transmits the externally encoded data to the transmitting processing module 02. The transmitting processing module 02 performs internal code encoding on the externally encoded data to obtain data with both external and internal code encoding, and transmits the data with both external and internal code encoding to the channel transmission medium 03. The channel transmission medium 03 transmits the data with both external and internal code encoding to the receiving processing module 04. The receiving processing module 04 performs internal code decoding on the data with both external and internal code encoding and transmits the internally decoded data to the receiving device 05. The receiving device 05 performs external code decoding on the data with internal code decoding.

[0139] It should be understood that the distinction between "internal" in "internal code" and "external" in "external code" is based solely on the distance between the entity performing the data operation and the channel transmission medium 03. The entity operating on the internal code is closer to the channel transmission medium, while the entity operating on the external code is farther away. In this embodiment, after data is sent from the transmitting device 01, it is transmitted to the channel transmission medium 03 via the transmitting processing module 02, and then from the channel transmission medium 03 via the receiving processing module 04 to the receiving device 05. The data encoded by the transmitting device 01 is farther from the channel transmission medium 03 than the data encoded by the transmitting processing module 02, and the data decoded by the receiving device 05 is farther from the channel transmission medium 03 than the data decoded by the receiving processing module 04. Therefore, the data encoded by the transmitting device 01 is called data encoded with the external code, the data encoded by the transmitting processing module 02 is called data encoded with the internal code, the data decoded by the receiving device 05 is called data decoded with the external code, and the data decoded by the receiving processing module 04 is called data decoded with the internal code. In one possible implementation, both the internal and external code encoding described above employ FEC encoding, thus forming a cascaded FEC transmission scheme. For example, the transmitting device 01 can use RS code for external code encoding, and the transmitting processing module 02 can use Hamming code for internal code encoding. Alternatively, the transmitting device 01 can use RS code for external code encoding, and the transmitting processing module 02 can use Bose-Chaudhuri-Hocquenghem (BCH) code for internal code encoding. A BCH code correcting a single error is equivalent to a Hamming code. Again, the transmitting device 01 can use RS code for external code encoding, and the transmitting processing module 02 can use Polar code for internal code encoding.

[0140] Figure 3 is a schematic diagram of another communication system applied in an embodiment of this application. As shown in Figure 3, the communication system includes a transmitting device 01, a channel transmission medium 03, and a receiving device 05. The transmitting device 01 performs external code encoding and internal code encoding on the data. The data after external code encoding and internal code encoding is sent to the transmission medium 03. The receiving device 05 decodes the internal code and external code of the data received from the transmission medium 03. Taking a data center network as an example, the transmitting device 01 and the receiving device 05 can be devices such as switches, routers, or servers. The transmitting device 01 is also called a client device or host device located at the transmitting end, and the receiving device 05 is also called a client chip located at the receiving end. The channel transmission medium 03 can be an optical fiber. The client device includes a client chip and an interface. The client chip is also called a host chip. The transmitting device 01, the channel transmission medium 03, and the receiving device 05 in this communication system can all support bidirectional transmission or unidirectional transmission, which is not limited here. In other words, the transmitting device 01 shown in Figure 3 also integrates the functions of the transmitting processing module 02 shown in Figure 2, and the receiving device 05 shown in Figure 3 also integrates the functions of the receiving processing module 04 shown in Figure 2. In this case, the transmitting device 01 can also employ linear pluggable optics (LPO), co-packaged optics (CPO), or near packaged optics (NPO) technology.

[0141] It should be noted that, as shown in Figures 2 and 3, in some specific applications, the data after internal encoding is further processed by DSP framing by adding at least one of the following sequences: Frame Alignment Word Sequence (FAW Sequence), Training Symbol Sequence, Reserved Symbol Sequence, and Pilot Symbol Sequence, to obtain the DSP frame to be transmitted. Optionally, the reserved symbols can also be called fixed stuff (FS), and the frame alignment symbols can also be called multi-frame alignment signal (MFAS).

[0142] It should also be noted that the above content is an exemplary description of the application scenarios of the data processing method provided in the embodiments of this application, and does not constitute a limitation on the application scenarios of the data processing method. As those skilled in the art will know, as business needs change, the application scenarios can be adjusted according to the application needs, and the embodiments of this application do not list them one by one.

[0143] Figure 4 is a schematic flowchart of a data processing method provided in an embodiment of this application. It should be understood that this data processing method is applied to the sending end, for example, it can be implemented by the sending end processing module 02 shown in Figure 2 above, or by the sending end device 01 shown in Figure 3 above.

[0144] 101. Obtain p first data streams after RS ​​encoding.

[0145] In this embodiment, all p first data streams are data streams encoded with external codes. For ease of explanation, the following description uses RS encoding as an example of external code encoding. In practical applications, other encoding methods can also be used for external code encoding. The data stream after RS ​​encoding can include multiple RS codewords. In this embodiment, the code length of the RS code is counted in units of symbols. The symbols in the RS code can be called RS symbols. For example, the RS code uses RS(544,514) code, also known as KP4 code. The code length of the RS code is 544 RS symbols, that is, the codeword of the RS code includes 544 RS symbols, and one RS symbol contains 10 bits. Each a in each first data stream RS The adjacent RS symbols are respectively from a RS 1 RS codeword, where a RS An integer power greater than or equal to 4 and equal to 2. In some specific scenarios, such as 1.6T Ethernet transmission, a RS =4, meaning that every 4 adjacent RS symbols in each first data stream come from 4 RS codewords, where p is an integer multiple of 4 and p is an integer power of 2.

[0146] 102. Perform first data processing, including internal code encoding and first interleaving, on p first data streams to obtain m second data streams.

[0147] Specifically, m is an integer greater than or equal to p, for example, p = 4, 8, or 16, m = 4, 8, 16, or 32. If each first data stream is not distributed, then m = p; if each first data stream is distributed, then m > p. Taking p = 4 first data streams as an example, if each first data stream is not distributed, then m = 4 second data streams are obtained after first data processing. Taking p = 4 first data streams as an example, if each first data stream is distributed in a 1:2 ratio, then m = 8 second data streams are obtained after first data processing. Taking p = 4 first data streams as an example, if each first data stream is distributed in a 1:4 ratio, then m = 16 second data streams are obtained after first data processing. Taking p = 4 first data streams as an example, if each first data stream is distributed in a 1:8 ratio, then m = 32 second data streams are obtained after first data processing. Taking p = 8 first data streams as an example, if each first data stream is not distributed, then m = 8 second data streams are obtained after first data processing. Taking p = 8 first data streams as an example, if each first data stream is distributed in a 1:2 ratio, then m = 16 second data streams are obtained after first data processing. Taking p = 8 first data streams as an example, if each first data stream is distributed in a 1:4 ratio, then m = 32 second data streams are obtained after first data processing.

[0148] The following uses a single data stream as an example to illustrate the internal code encoding method. Specifically, every K information bits in the first data stream are internally encoded to generate NK check bits, thus obtaining an internal codeword consisting of N bits, where 1 < K < N. For example, the internal code encoding uses a linear block code with N = 126 and K = 110, such as BCH(126, 110). Another example is using a linear block code with N = 128 and K = 120, such as BCH(128, 120). Yet another example is using a linear block code with N = 176 and K = 160, such as BCH(176, 160).

[0149] In some scenarios, considering that K is a multiple of 10, and that the K information bits in each inner codeword correspond to K / 10 outer code RS symbols, and that the corresponding K / 10 outer code RS symbols come from K / 10 different outer code RS codewords, the FEC concatenation scheme including RS encoding and inner code encoding can achieve optimal performance. For example, the inner code encoding uses BCH(126,110), where K=110 information bits in each inner codeword correspond to K / 10=11 outer code symbols, and that the corresponding K / 10=11 outer code symbols come from K / 10=11 different outer code RS codewords. Another example is the inner code encoding using a linear block code of N=128 and K=120, where K=120 information bits in each inner codeword correspond to K / 10=12 outer code symbols, and that the corresponding K / 10=12 outer code symbols come from K / 10=12 different outer code RS codewords. For example, the internal code encoding uses a linear block code with N=176 and K=160. Each internal codeword contains K=160 information bits, corresponding to K / 10=16 external code symbols, and these K / 10=16 external code symbols come from K / 10=16 different external code RS codewords. In some possible scenarios, to ensure that the K information bits in each internal codeword correspond to K / 10 different external code RS codewords, the first data stream undergoes convolutional interleaving before internal code encoding. The convolutional interleaving process will be described in detail below.

[0150] Specifically, the convolutional interleaver (CIE) performing the convolutional interleaving process includes r delay lines, each with a different number of storage units. The delay line with the fewest storage units has 0 storage units. The difference in the number of storage units between any two adjacent delay lines is Q, where r is an integer greater than 1 and Q is an integer greater than or equal to 1. Each storage unit stores d bits, where d is an integer greater than or equal to 1. The bits in the input data stream of the CIE are sequentially input to the r delay lines according to their numbers, with d bits input and output from each delay line at a time. In some applications, the CIE outputs d bits at a time. In other applications, the CIE outputs r × d bits at a time, where r × d bits come from the r delay lines and include the d bits output from each delay line. The consecutive r × d bits in the output data stream of the CIE include the d bits output from each delay line.

[0151] It should be understood that the r delay lines each comprise 0, Q, 2Q, ..., (r-1)Q storage units, with each unit storing d bits. The r delay lines correspond to r delay values, which include 0 bits, Q×d bits, 2Q×d bits, ..., (r-1)Q×d bits. The more bits a delay line includes in its delay values, the longer the delay (also called latency) of that delay line to the data stream. It should be understood that when a delay line contains no storage units, the delay is 0 bits, which is called zero-latency pass-through. It should be understood that the aforementioned storage units are also called delay elements.

[0152] Figure 5(a) is a schematic diagram of the first structure of convolutional interleaving in an embodiment of this application. As shown in Figure 5(a), the number of storage units in the r delay lines decreases sequentially according to the sequence number of the r delay lines. That is, delay line 0 has (r-1)Q storage units, each delay line decreases by Q storage units sequentially, and delay line r-1 has 0 storage units. Figure 5(b) is a schematic diagram of the second structure of convolutional interleaving in an embodiment of this application. As shown in Figure 5(b), the number of storage units in the r delay lines increases sequentially according to the sequence number of the r delay lines. That is, delay line 0 has 0 storage units, each delay line increases by Q storage units sequentially, and delay line r-1 has (r-1)Q storage units.

[0153] It should be noted that at any given moment, the input and output switches of the convolutional interleaver are located on the same delay line. After the current delay line receives and outputs d bits in a single input, the switch is switched to the next delay line. This ensures that the bits in the input data stream are sequentially input to the r delay lines according to their sequence numbers, and that the consecutive r×d bits in the output data stream include the d bits output from each delay line. The specific data read / write operations are as follows: d bits are read from the memory cell closest to the output port of the current delay line; the d bits stored in each memory cell of the current delay line are transferred to the next memory cell; then, d bits are written to the memory cell closest to the input port of the current delay line. Afterward, the switch is moved to the next delay line, and the above operations are repeated, and so on.

[0154] It should be understood that when the same parameters r, Q, and d are used, the convolutional interleaving process in Figure 5(a) and the convolutional interleaving process in Figure 5(b) are the inverse operations of each other. That is, when the sending-end processing module uses the convolutional interleaving structure shown in Figure 5(a), the corresponding convolutional deinterleaving in its receiving-end processing module uses the structure shown in Figure 5(b). Similarly, when the sending-end processing module uses the convolutional interleaving structure shown in Figure 5(b), the corresponding convolutional deinterleaving in its receiving-end processing module uses the structure shown in Figure 5(a).

[0155] Typically, the number of bits stored in each memory cell is d = a. RS ×10. For example, in a 1.6T Ethernet transmission scenario, a RS =4, d=a RS ×10=40. It should be noted that each a in each of the first data streams... RS The adjacent RS symbols are respectively from a RS A different external code RS codeword, when a RS When the value is larger, in order to achieve K / 10 different external code RS codewords corresponding to K information bits in each internal codeword, the total number of bits in the storage unit (also called delay unit) of the convolutional interleaver is smaller, which means the latency and complexity of the convolutional interleaver are lower.

[0156] The first interleaving, included in the first data processing described above, is described in detail below. The first interleaving is used to interleave every K information bits in the first data stream to shuffle their order, thereby improving the overall burst resistance of the concatenated code. The first interleaving is also called bit shuffling or permutation. In some possible scenarios, the first interleaving is performed after internal code encoding; that is, the first data stream is first internally encoded, and then the internally encoded first data stream is subjected to the first interleaving. In other possible scenarios, the first interleaving is performed before internal code encoding; that is, the first data stream is first first interleaved, and then the first interleaved first data stream is subjected to internal code encoding. In still other possible scenarios, considering that the first interleaving is only used to interleave K information bits to shuffle their order, and the parity bits do not participate in the first interleaving, the first interleaving and internal code encoding can be processed in parallel. Specifically, the K information bits are represented by U, and internal code encoding is performed first to obtain the corresponding internal codeword (U, V), where the NK parity bits generated by the internal code encoding are represented by V. Then, the K information bits U in the codeword (U,V) are first interleaved to obtain N bits (W,V), where the K bits obtained from the first interleaving of the K information bits U are represented by W. This is equivalent to the internal code encoding and the first interleaving being processed in parallel; that is, the K information bits U are internally encoded to obtain NK parity bits V, and simultaneously, the K bits W obtained from the first interleaving of the K information bits U are combined to obtain the N bits (W,V) after internal code encoding and the first interleaving. For simplicity, the N bits (W,V) are also called the codeword interleaving sequence.

[0157] In some specific applications, the first interleaving is used to perform a right circular shift of K information bits. bits, where the integer In other specific applications, the first interleaving is used to cyclically shift K information bits to the left by δ bits. In this case, the first interleaving is also called a circular shift. It should be noted that a right circular shift of K information bits... Each bit is equivalent to a left circular shift of K information bits. The following description of the circular shift operation uses a right circular shift as an example. Typically, the number of bits used in a right circular shift for the first interleaving of m data streams is... Not exactly the same, among which, The number of bits to circularly shift to the right of the i-th data stream out of m data streams. For example, K is an integer multiple of 10. It is an integer multiple of 10. The first interleaving can further improve the overall scheme's resistance to colored noise.

[0158] It should be noted that for scenarios where m > p, the aforementioned first data processing also includes a distribution operation. Each of the p first data streams is distributed to obtain m / p first sub-data streams, resulting in a total of p × (m / p) = m first sub-data streams. These m first sub-data streams are then subjected to internal code encoding and first interleaving to obtain m second data streams. It should be understood that distribution and convolutional interleaving are decoupled; for example, only convolutional interleaving can be performed; or only distribution can be performed; or convolutional interleaving can be performed first, followed by distribution.

[0159] In some possible scenarios, distribution is performed at a granularity of K bits. For example, if a first data stream is distributed into four first sub-data streams, the 4 × K consecutive bits in the first data stream are distributed into the four corresponding sub-data streams. Each sub-data stream contains K consecutive bits from the 4 × K bits. In this case, the distribution is also called 1:(m / p)K-bit block distribution. The distribution operation can also be called de-muxing.

[0160] In other possible scenarios, distribution is performed in granularity of K0 bits. A consecutive (m / p) × K0 bits from one first data stream is distributed to its corresponding m / p first sub-data streams. Each first sub-data stream contains a consecutive K0 bits from the (m / p) × K0 bits, where K0 is an integer multiple of 40. As another example, K may not be an integer multiple of 40. in This indicates rounding down to the nearest integer. For example, K = 110.

[0161] 103. Perform second data processing on m second data streams, including second interleaving, dual polarization symbol mapping and framing, to obtain 1 first dual polarization symbol stream.

[0162] Specifically, one internal codeword is obtained from each second data stream, resulting in a total of m internal codewords from m second data streams, with a bit count of m×N. The second interleaving is used to shuffle the order of the m×N bits in the m internal codewords, thereby improving the burst resistance and colored noise resistance of the cascaded FEC scheme. The second interleaving can also be called codeword interleaving. As an example, the second interleaving here can be divided into two steps: first, a multiplexing operation to obtain the m internal codewords, and then interleaving the m internal codewords. As another example, the second interleaving here can be implemented in one step, achieving the same effect as the two-step implementation described above.

[0163] The data stream obtained after the second interleaving is subjected to dual-polarization symbol mapping and framing to obtain a first dual-polarization symbol stream to be transmitted. This framing can also be called DSP framing. The following description uses DP-16QAM symbol mapping as an example. For instance, dual-polarization symbol mapping is used to map every 8 bits in the data stream after the second interleaving to one dual-polarization 16QAM (DP-16QAM) symbol. Each DP-16QAM symbol includes one 16QAM symbol in the X-polarization direction and one 16QAM symbol in the Y-polarization direction, where the X-polarization and Y-polarization directions are orthogonal to each other. Furthermore, the 16QAM symbol in the X-polarization direction includes an in-phase component and a quadrature-phase component in the X-polarization direction, and the 16QAM symbol in the Y-polarization direction includes an in-phase component and a quadrature-phase component in the Y-polarization direction. It should be understood that dual-polarization symbol mapping is also called DP-16QAM symbol mapping, or 16QAM symbol mapping and polarization distribution. Specifically, the DP-16QAM symbol stream to be transmitted contains multiple DP-16QAM symbol sequences. DSP framing is used to insert target symbol sequences at fixed positions in each DP-16QAM symbol sequence. The DP-16QAM symbol sequence is also called a DSP frame.

[0164] The following section provides a detailed description of possible implementation methods for dual-polarization symbol mapping and DSP framing.

[0165] Figure 6(a) is a schematic diagram of one embodiment of dual-polarization symbol mapping and DSP framing in this application. As shown in Figure 6(a), DSP framing is performed after DP-16QAM symbol mapping, and DSP framing is an operation performed on symbols. First, the m second data streams are subjected to second interleaving and DP-16QAM symbol mapping to obtain a second dual-polarization symbol stream, which can also be called the pre-framing symbol stream. Then, DSP framing is performed on the second dual-polarization symbol stream. Specifically, target symbol sequences are inserted into the symbol streams in the X-polarization direction and the Y-polarization direction of the second dual-polarization symbol stream, respectively, to obtain the first dual-polarization symbol stream to be transmitted. It should be understood that the values ​​of the target symbol sequences inserted in the X-polarization direction and the target symbol sequences inserted in the Y-polarization direction may not be exactly the same. Here, they are collectively referred to as target symbol sequences without specific distinction. For example, the target symbol sequence includes at least one of the following: Frame Alignment Word Sequence (FAW Sequence), Training Symbol Sequence, Reserved Symbol Sequence, and Pilot Symbol Sequence. Optionally, reserved symbols may also be referred to as fixed stuff (FS), and frame alignment symbols may also be referred to as multi-frame alignment signal (MFAS).

[0166] In one possible scenario, the target symbol sequence is a pilot symbol sequence. In either the X-polarization or Y-polarization direction, each N in the DSP frame... G One symbol at a fixed position among the symbols is the pilot symbol. As an example, every N... G The first symbol in the set is the pilot symbol. Typically, N G =32, 64, 96, or 128, etc. In the X-polarization or Y-polarization direction, each pilot symbol is one of 3+3j, 3-3j, -3+3j, or -3-3j. Here, j is the imaginary unit of a complex number. That is, each pilot symbol uses one of the outermost four symbols in the 16QAM constellation diagram.

[0167] In some specific applications, the DSP framing operation adds one pilot symbol to every 63 DP-16QAM symbols in every 96 × 63 = 6048 pre-framing DP-16QAM symbols, resulting in 96 × 64 = 6144 DP-16QAM symbols to be transmitted. These 6144 DP-16QAM symbols are called a DSP frame. It should be understood that, in the X-polarization direction or the Y-polarization direction, every N... G =The first symbol in the 64 symbols is the pilot symbol. The 96×63=6048 pre-framing DP-16QAM symbols are obtained by mapping 6048×8=48384 bits in the data stream obtained after the second interleaving through DP-16QAM.

[0168] Figure 6(b) is a schematic diagram of another implementation of dual-polarization symbol mapping and DSP framing in this application embodiment. As shown in Figure 6(b), DSP framing is performed before DP-16QAM symbol mapping, and DSP framing is performed on a bit-by-bit basis. Specifically, m second data streams are interleaved a second time to obtain one third data stream, a target bit sequence is inserted into the third data stream to obtain a fourth data stream, and DP-16QAM symbol mapping is performed on the fourth data stream to obtain a first dual-polarization symbol stream. The target bit sequence is then processed by DP-16QAM symbol mapping to obtain the target symbol sequence.

[0169] Figure 6(c) is a schematic diagram of another implementation of dual-polarization symbol mapping and DSP framing in this application embodiment. As shown in Figure 6(c), DSP framing is performed before DP-16QAM symbol mapping. DSP framing is performed on a bit-by-bit basis, and the data after the second interleaving is represented by two data streams. Specifically, the m second data streams are second-interleaved to obtain two third data streams. The two third data streams are then inserted into the target bit sequence X and the target bit sequence Y to obtain two fourth bit streams. The two fourth bit streams are then subjected to DP-16QAM symbol mapping to obtain the first dual-polarization symbol stream. Specifically, the target bit sequence X is subjected to DP-16QAM symbol mapping to obtain the target symbol sequence in the X-polarization direction, and the target bit sequence Y is subjected to DP-16QAM symbol mapping to obtain the target symbol sequence in the Y-polarization direction.

[0170] Figure 6(d) is a schematic diagram of another implementation of dual-polarization symbol mapping and DSP framing in this application. As shown in Figure 6(d), DSP framing is performed before DP-16QAM symbol mapping. DSP framing is performed on a bit-by-bit basis, and the data after the second interleaving is represented by four data streams. Specifically, the m second data streams are second-interleaved to obtain four third data streams, and the target bit sequence X is inserted into each of the four third data streams. ITarget bit sequence X Q Target bit sequence Y I Target bit sequence Y Q Four fourth bit streams are obtained, and DP-16QAM symbol mapping is performed on these four fourth bit streams to obtain the first dual-polarization symbol stream. The target bit sequence X... I After DP-16QAM symbol mapping, the I component of the target symbol sequence in the X polarization direction is obtained, and the target bit sequence X is obtained. Q After DP-16QAM symbol mapping, the Q component of the target symbol sequence in the X-polarization direction is obtained, and the target bit sequence Y is obtained. I After DP-16QAM symbol mapping, the I component of the target symbol sequence in the Y polarization direction is obtained, and the target bit sequence Y... Q The Q component of the target symbol sequence in the Y polarization direction is obtained by DP-16QAM symbol mapping.

[0171] It should be noted that in some specific scenarios, the first dual-polarization symbol stream to be transmitted is described by two symbol streams: one is the symbol stream of the first dual-polarization symbol stream in the X-polarization direction, and the other is the symbol stream of the first dual-polarization symbol stream to be transmitted in the Y-polarization direction. In other specific scenarios, the first dual-polarization symbol stream is described by four data streams, the first of which is the data stream of the I-path component in the X-polarization direction corresponding to the first dual-polarization symbol stream (referred to as X...). I The second data stream is the Q-path data stream in the X-polarization direction corresponding to the first dual-polarization symbol stream (abbreviated as X). Q The third data stream is the data stream of the I-path component in the Y-polarization direction corresponding to the first dual-polarization symbol stream (abbreviated as Y). I The fourth data stream is the data stream of the Q-path component in the Y-polarization direction corresponding to the first dual-polarization symbol stream (abbreviated as Y). Q (Data flow).

[0172] Considering the service transmission of 1.6T Ethernet (1.6Terabit Ethernet, 1.6TE), the total bit rate of p first data streams is 106.25 × 2 × 8 = 1700 Gbits per second. It should also be understood that the bit rates in this application are nominal rates; in practical applications, the bit rate will have a certain offset range, for example, a ±V0 (ppm) error, where V0 can be 20, 25, 50, or 100, etc. Each first data stream contains four consecutive RS symbols derived from four different RS codewords; each first data stream is also called a 4-symbol-quartet stream. In some specific applications, the first data streams are further processed by a Physical Media Attachment (PMA) layer based on symbol multiplexing. More specifically, the first data streams are obtained through PMA processing based on 4-symbol-quartet multiplexing. It should be noted that, in the embodiments of this application, m0:m1 PMA means that m0 input data streams are symbolically multiplexed to obtain m1 output data streams. In some other specific applications, the first data stream is also processed by a Physical Coding Sublayer (PCS).

[0173] Figure 7(a) is a data processing flowchart corresponding to the data processing method in this application embodiment. As shown in Figure 7(a), 1.6T service data is processed by 1.6T PCS to obtain 16 PCS channel data streams, also known as 16 PCS Lanes. Specifically, the 1.6T PCS processing includes 4 RS encoding processing units, namely RS-A, RS-B, RS-C, and RS-D in the figure. The encoded data streams obtained after the 4 RS encoding processing units are then subjected to symbol distribution and interleave to obtain 16 PCS Lanes. Among them, the symbol distribution is granular with 10 bits. Each of the 4 adjacent RS symbols in the 16 PCS Lanes comes from 4 different RS codewords. The 16 PCS Lanes are processed by 1.6T 16:8PMA based on 4-symbol multiplexing to obtain 8 1.6T AUI-8 signals. Each of the eight 1.6T AUI-8 signals has a bit rate of 212.5 Gbits per second, using PAM4 modulation. The corresponding baud rate (also known as symbol rate) is 106.25 GBaud, meaning the total bit rate of the eight 1.6T AUI-8 signals is 106.25 × 2 × 8 = 1700 Gbits per second. Considering 1.6T Ethernet services, the 1.6T PCS is also called the 1.6T BASE-R PCS, and the 1.6T 16:8PMA is also called the 1.6T BASE-R 16:8PMA. The 1.6T PCS processing and 1.6T 16:8PMA are implemented in the transmitting device 01. The transmitting processing module 02 receives the eight 1.6T AUI-8 signals. These eight signals first undergo 1.6T 8:8PMA to obtain p = eight first data streams, which are then processed by first and second data processing to obtain one first dual-polarization symbol stream to be transmitted.

[0174] Figure 7(b) is another data processing flowchart corresponding to the data processing method in this application embodiment. As shown in Figure 7(b), 16 PCS lanes are processed by 1.6T 16:16PMA based on 4-symbol multiplexing to obtain 16 1.6T AUI-16 signals. The bit rate of each of the 16 1.6T AUI-16 signals is 106.25 Gbits per second, which adopts PAM4 modulation, and the corresponding baud rate (also known as symbol rate) is 53.125 G Baud, that is, the total bit rate of the 16 1.6T AUI-16 signals is 106.25 × 16 = 1700 Gbits per second. The 1.6T PCS processing and 1.6T 16:16PMA are implemented in the transmitting device 01. The transmitting processing module 02 receives 16 1.6T AUI-16 signals, first processes them through 1.6T 16:8PMA to obtain p=8 first data streams, and then performs first data processing and second data processing to obtain 1 first dual-polarization symbol stream to be transmitted.

[0175] Figure 7(c) is another data processing flowchart corresponding to the data processing method in this application embodiment. As shown in Figure 7(c), 16 PCS Lanes are processed by 1.6T 16:8PMA based on 4-symbol multiplexing to obtain p=8 first data streams, and then undergo first data processing and second data processing to obtain 1 first dual-polarization symbol stream to be transmitted. The 1.6T PCS processing, 1.6T 16:8PMA, first data processing and second data processing are implemented in the transmitting device 01.

[0176] Figure 8(a) is another data processing flowchart corresponding to the data processing method in this application embodiment. As shown in Figure 8(a), 16 PCS lanes are processed by 1.6T 16:8PMA based on 4-symbol multiplexing to obtain 8 1.6T AUI-8 signals. The bit rate of each of the 8 1.6T AUI-8 signals is 212.5 Gbits per second, which adopts PAM4 modulation, and the corresponding baud rate (also known as symbol rate) is 106.25 GBaud, that is, the total bit rate of the 8 1.6T AUI-8 signals is 106.25 × 2 × 8 = 1700 Gbits per second. Considering 1.6T Ethernet services, 1.6T PCS is also called 1.6T BASE-R PCS, and 1.6T 16:8PMA is also called 1.6T BASE-R 16:8PMA. 1.6T PCS processing and 1.6T 16:8PMA are implemented in the transmitting device 01. The transmitting processing module 02 receives eight 1.6T AUI-8 signals, first processes them through 1.6T 8:16PMA to obtain p=16 first data streams, and then performs first data processing and second data processing to obtain one first dual-polarization symbol stream to be transmitted.

[0177] Figure 8(b) is another data processing flowchart corresponding to the data processing method in this application embodiment. As shown in Figure 8(b), 16 PCS lanes are processed by 1.6T 16:16PMA based on 4-symbol multiplexing to obtain 16 1.6T AUI-16 signals. The bit rate of each of the 16 1.6T AUI-16 signals is 106.25 Gbits per second, which adopts PAM4 modulation and the corresponding baud rate (also known as symbol rate) is 53.125 G Baud. That is, the total bit rate of the 16 1.6T AUI-16 signals is 106.25 × 16 = 1700 Gbits per second. The 1.6T PCS processing and 1.6T 16:16PMA are implemented in the transmitting device 01. The transmitting processing module 02 receives 16 1.6T 16:16 signals, first processes them through 1.6T 16:16PMA to obtain p=16 first data streams, and then performs first data processing and second data processing to obtain 1 first dual-polarization symbol stream to be transmitted.

[0178] Figure 8(c) is another data processing flowchart corresponding to the data processing method in this application embodiment. As shown in Figure 8(c), the total bit rate of the 16 PCS Lanes is 106.25 × 16 = 1700 Gbits per second. The 16 PCS Lanes serve as p = 16 first data streams, undergoing first data processing and second data processing to obtain one first dual-polarization symbol stream to be transmitted. The 1.6T PCS processing, the first data processing, and the second data processing are implemented in the transmitting device 01.

[0179] Figure 8(d) is another data processing flowchart corresponding to the data processing method in this application embodiment. As shown in Figure 8(d), 16 PCS lanes are processed by 1.6T 16:4PMA based on 4-symbol multiplexing to obtain 4 1.6T AUI-4 signals. The bit rate of each of the 4 1.6T AUI-4 signals is 425 Gbits per second, which adopts PAM4 modulation, and the corresponding baud rate (also known as symbol rate) is 212.5 GBaud. The 1.6T PCS processing and 1.6T 16:4PMA are implemented in the transmitting device 01. The transmitting processing module 02 receives the 4 1.6T AUI-4 signals, first processes them through 1.6T 4:16PMA to obtain p=16 first data streams, and then performs first data processing and second data processing to obtain 1 first dual-polarization symbol stream to be transmitted.

[0180] It should be noted that in the scenarios for 1.6T services shown in Figures 7(a), 7(b), and 7(c), p = 8 first data streams participate in the first and second data processing. In the scenarios for 1.6T services shown in Figures 8(a), 8(b), 8(c), and 8(d), p = 16 first data streams participate in the first and second data processing. The p = 8 first data streams participating in the first and second data processing is applicable not only to the 1.6T service scenarios described above but also to other service scenarios with a total rate of 1.6T, such as two 800G services or four 400G services.

[0181] Figure 7(d) is another data processing flowchart corresponding to the data processing method in this application embodiment. As shown in Figure 7(d), consider two 800G service scenarios, where each 800G service data is processed by 800G PCS to obtain 32 PCS Lanes. Specifically, each 800G PCS process includes four RS encoding processing units, namely RS-A, RS-B, RS-C, and RS-D in the figure. The encoded data streams obtained after the four RS encoding processing units are then symbol-distributed and interleaved to obtain 32 PCS Lanes. The symbol distribution is granular with 10 bits. The 32 PCS Lanes are processed by 800G 32:4PMA based on 4-symbol multiplexing to obtain four 800G AUI-4 signals. The two 800G service data are processed by the above 800G PCS and 800G 32:4PMA to obtain a total of two sets of 800G AUI-4 signals, totaling eight signal streams. Each of the two 800G AUI-4 signals has a bit rate of 212.5 Gbits per second, using PAM4 modulation with a corresponding baud rate (also known as symbol rate) of 106.25 G Baud. Therefore, the total bit rate of the two 800G AUI-4 signals is 106.25 × 2 × 4 × 2 = 1700 Gbits per second. The transmitting processing module 02 receives the two 800G AUI-4 signals. Each 800G AUI-4 signal is processed by 800G 4:4 PMA to obtain four first data streams, resulting in a total of p = eight first data streams. These eight first data streams then undergo first data processing and second data processing to obtain one first dual-polarization symbol stream to be transmitted.

[0182] Figure 7(e) is another data processing flowchart corresponding to the data processing method in this application embodiment. As shown in Figure 7(e), consider four 400G service scenarios, where each 400G service data is processed by 400G PCS to obtain 16 PCS Lanes. Specifically, each 400G PCS process includes two RS encoding processing units. For example, the 400G PCS process in the figure may include RS-A and RS-B, and the 400G PCS process may also include RS-C and RS-D. The encoded data streams obtained after the two RS encoding processing units are then symbol-distributed and interleaved to obtain 16 PCS Lanes. The symbol distribution is granular with 10 bits. The 16 PCS Lanes are processed by 400G 16:2PMA based on 4-symbol multiplexing to obtain two 400G AUI-2 signals. The four 400G service data are processed by the above 400G PCS and 400G 16:2PMA to obtain a total of four sets of 400G AUI-2 signals, totaling eight signal streams. Each of the four 400G AUI-2 signals has a bit rate of 212.5 Gbits per second, using PAM4 modulation, with a corresponding baud rate (also known as symbol rate) of 106.25 G Baud. Therefore, the total bit rate of the four 400G AUI-2 signals is 106.25 × 2 × 4 × 2 = 1700 Gbits per second. The transmitting processing module 02 receives the four 400G AUI-2 signals. Each 400G AUI-2 signal is processed by 400G 2:2 PMA to obtain two first data streams, resulting in a total of p = 8 first data streams. These 8 first data streams then undergo first data processing and second data processing to obtain one first dual-polarization symbol stream to be transmitted.

[0183] Figure 7(f) is another data processing flowchart corresponding to the data processing method in this application embodiment. As shown in Figure 7(f), 16 PCS lanes are processed by 1.6T 16:4PMA based on 4-symbol multiplexing to obtain 4 1.6T AUI-4 signals. The bit rate of each of the 4 1.6T AUI-4 signals is 425 Gbits per second, which adopts PAM4 modulation, and the corresponding baud rate (also known as symbol rate) is 212.5 GBaud. The 1.6T PCS processing and 1.6T 16:4PMA are implemented in the transmitting device 01. The transmitting processing module 02 receives the 4 1.6T AUI-4 signals, first processes them through 1.6T 4:8PMA to obtain p=8 first data streams, and then performs first data processing and second data processing to obtain 1 first dual-polarization symbol stream to be transmitted.

[0184] The data processing flow for p=4 is described below. Figure 8(e) is another data processing flowchart corresponding to the data processing method in this embodiment. As shown in Figure 8(e), 16 PCS lanes are processed by 1.6T 16:4PMA based on 4-symbol multiplexing to obtain 4 1.6TAUI-4 signals. The bit rate of each of the 4 1.6T AUI-4 signals is 425 Gbits per second, which adopts PAM4 modulation, and the corresponding baud rate (also known as symbol rate) is 212.5 G Baud. The 1.6T PCS processing and 1.6T 16:4PMA are implemented in the transmitting device 01. The transmitting processing module 02 receives the 4 1.6TAUI-4 signals, first processes them through 1.6T 4:4PMA to obtain p=4 first data streams, and then performs first data processing and second data processing to obtain 1 first dual-polarization symbol stream to be transmitted.

[0185] Figure 8(f) is another data processing flowchart corresponding to the data processing method in this application embodiment. As shown in Figure 8(f), 16 PCS lanes are processed by 1.6T 16:8PMA based on 4-symbol multiplexing to obtain 8 1.6T AUI-8 signals. The 1.6T PCS processing and 1.6T 16:8PMA are implemented in the transmitting device 01. The transmitting processing module 02 receives the 8 1.6T AUI-8 signals, first processes them through 1.6T 8:4PMA to obtain p=4 first data streams, and then performs first data processing and second data processing to obtain 1 first dual-polarization symbol stream to be transmitted.

[0186] Figure 8(g) is another data processing flowchart corresponding to the data processing method in this application embodiment. As shown in Figure 8(g), 16 PCS Lanes are processed by 1.6T 16:4PMA based on 4-symbol multiplexing to obtain p=4 first data streams, and then undergo first data processing and second data processing to obtain 1 first dual-polarization symbol stream to be transmitted. The 1.6T PCS processing, 1.6T 16:4PMA, first data processing and second data processing are implemented in the transmitting device 01.

[0187] The following section, using the values ​​of p and m, further introduces the specific operations of the first and second data processing steps.

[0188] For scenarios where p=8 and m=8, for example, as shown in Figure 7(a), 8 first data streams are acquired from 1.6T 8:8PMA. As another example, as shown in Figures 7(b) and 7(c), 8 first data streams are acquired from 1.6T 16:8PMA. As yet another example, as shown in Figure 7(d), a total of 8 first data streams are acquired from 2 groups of 800G 32:4PMA. As yet another example, as shown in Figure 7(e), a total of 8 first data streams are acquired from 4 groups of 400G 16:2PMA. As yet another example, as shown in Figure 7(f), 8 first data streams are acquired from 1.6T 4:8PMA.

[0189] Figure 9(a) is a schematic diagram of one embodiment of the first and second data processing in this application. As shown in Figure 9(a), eight first data streams (i.e., first data streams 0-7) are respectively subjected to convolutional interleaving, internal code encoding, and first interleaving to obtain eight second data streams. Then, the eight second data streams are subjected to second interleaving, and then the data streams after second interleaving are subjected to DP-16QAM symbol mapping and DSP framing to obtain the first dual-polarization symbol stream to be transmitted. It can be seen that in the embodiment shown in Figure 9(a), each first data stream after convolutional interleaving is first subjected to internal code encoding and then first interleaving.

[0190] Figure 9(b) is a schematic diagram of another implementation of the first data processing and the second data processing in the embodiments of this application. Unlike the implementation shown in Figure 9(a), as shown in Figure 9(b), each first data stream after convolutional interleaving is first interleaved and then encoded using internal codes.

[0191] Figure 9(c) is a schematic diagram of another implementation of the first data processing and the second data processing in the embodiments of this application. Unlike the implementation shown in Figures 9(a) and 9(b), as shown in Figure 9(c), each first data stream after convolutional interleaving is processed in parallel for internal code encoding and first interleaving.

[0192] It should be noted that, for the implementation methods shown in Figures 9(a), 9(b), and 9(c), in some scenarios requiring low latency, the convolutional interleaving process can be skipped, resulting in advantages of low latency and low power consumption. It should also be noted that the first data processing with p=8 described above is applicable to service scenarios involving a total rate of 1.6T, including one 1.6T service, two 800G services, and four 400G services, and can be applied to a wider range of scenarios.

[0193] For the scenario where p=8 and m=8, the following describes a possible implementation of the second interleaving.

[0194] One codeword interleaving sequence is obtained from each second data stream after the first data processing, resulting in a total of 8×N bits, called the first bit set, which can be represented as follows:

[0195] in This represents the j0th (0≤j0≤N-1) bit in the codeword interleaving sequence obtained from the second data stream i0 (0≤i0≤7). The first bit set, consisting of 8×N bits, undergoes a second interleaving to obtain a second bit set of 8×N bits. DP-16QAM symbol mapping is then performed on the second bit set, mapping every 8 bits to obtain one DP-16QAM symbol, resulting in a total of N DP-16QAM symbols, denoted as S0, S1, S2, ..., S... N-2 ,S N-1 Consider S i Let the 8 bits of the i-th (0≤i≤N-1)th DP-16QAM symbol in N DP-16QAM symbols be denoted as .

[0196] The first implementation of the second interleaving is described below. Consider that the number of bits N in the internal codeword is even. Taking 0≤i≤N / 2-1 as an example, it consists of 8 bits. From 8 bits Taking N / 2≤i≤N-1 as an example, 8 bits From 8 bits

[0197] The first specific embodiment of the second interleaving is given below, where 0≤i≤N-1.

[0198] From the second data stream The 2nd × (i % (N / 2)) + i % 2th bit in the codeword interleaving sequence.

[0199] From the second data stream The 2nd × (i % (N / 2)) + (i+1) % 2th bit in the codeword interleaving sequence.

[0200] From the second data stream The 2nd × (i % (N / 2)) + i % 2th bit in the codeword interleaving sequence.

[0201] From the second data stream The 2nd × (i % (N / 2)) + (i+1) % 2th bit in the codeword interleaving sequence.

[0202] From the second data stream The 2nd × (i % (N / 2)) + i % 2th bit in the codeword interleaving sequence.

[0203] From the second data stream The 2nd × (i % (N / 2)) + (i+1) % 2th bit in the codeword interleaving sequence.

[0204] From the second data stream The 2nd × (i % (N / 2)) + i % 2th bit in the codeword interleaving sequence.

[0205] From the second data stream The 2nd × (i % (N / 2)) + (i+1) % 2th bit in the codeword interleaving sequence.

[0206] The second implementation of the second interleaving is described below. Consider that the number of bits N in the internal codeword does not need to be even; it can also be odd. Taking 0≤i≤N-1 as an example, 8 bits... From 8 bits

[0207] The second specific embodiment of the second interleaving is given below, where 0≤i≤N-1.

[0208] The i-th bit from the codeword interleaving sequence of the second data stream (i+4)%8.

[0209] The i-th bit from the codeword interleaving sequence of the second data stream (i+5)%8.

[0210] The i-th bit from the codeword interleaving sequence of the second data stream (i+6)%8.

[0211] The i-th bit from the codeword interleaving sequence of the second data stream (i+7)%8.

[0212] The i-th bit from the codeword interleaving sequence of the second data stream (i)%8.

[0213] The i-th bit from the codeword interleaving sequence of the second data stream (i+1)%8.

[0214] The i-th bit from the codeword interleaving sequence of the second data stream (i+2)%8.

[0215] The i-th bit from the codeword interleaving sequence of the second data stream (i+3)%8.

[0216] For scenarios where p=8 and m=32, for example, as shown in Figure 7(a), 8 first data streams are obtained from 1.6T 8:8PMA. As another example, as shown in Figures 7(b) and 7(c), 8 first data streams are obtained from 1.6T 16:8PMA. As yet another example, as shown in Figure 7(d), a total of 8 first data streams are obtained from 2 groups of 800G 32:4PMA. And as yet another example, as shown in Figure 7(e), a total of 8 first data streams are obtained from 4 groups of 400G 16:2PMA.

[0217] Figure 10(a) is a schematic diagram of another implementation of the first and second data processing in this application. As shown in Figure 10(a), the eight first data streams (i.e., first data streams 0-7) are convolutionally interleaved to obtain eight convolutionally interleaved data streams. Each convolutionally interleaved data stream is distributed in a 1:4 K-bit block distribution to obtain four first sub-data streams, resulting in a total of 32 first sub-data streams. The 32 first sub-data streams are then encoded using internal codes and interleaved using the first method to obtain 32 second data streams. Considering that the number of bits N in the internal codeword is even, one codeword interleaving sequence is obtained from each second data stream, totaling 32×N bits, which is called the first bit set. The first bit set is interleaved using the second method to obtain a second bit set containing 32×N bits, and DP-16QAM symbol mapping is performed on the second bit set to map every 8 bits to one DP-16QAM symbol, resulting in a total of 4×N DP-16QAM symbols, i.e., S0, S1, S2, ..., S N-2 ,S 4×N-1 Consider S i Let the 8 bits of the DP-16QAM symbol, which is the i-th (0≤i≤4×N-1)th DP-16QAM symbol out of 4×N symbols, be denoted as . As can be seen, in the embodiment shown in Figure 10(a), each first data stream that has undergone convolutional interleaving is first encoded with an internal code and then interleaved.

[0218] Figure 10(b) is a schematic diagram of another implementation of the first data processing and the second data processing in the embodiments of this application. Unlike the implementation shown in Figure 10(a), as shown in Figure 10(b), each first data stream after convolutional interleaving is first interleaved and then encoded using internal codes.

[0219] It should be noted that, for the implementation methods shown in Figures 10(a) and 10(b) above, in some scenarios requiring low latency, the convolutional interleaving process can be bypassed, which has the advantages of low latency and low power consumption.

[0220] For the scenario where p = 8 and m = 32, the third specific implementation of the second interleaving is given below, where 0 ≤ i ≤ 4 × N - 1.

[0221] From the second data stream The 2nd × (i % (N / 2)) + i % 2th bit in the codeword interleaving sequence.

[0222] From the second data stream The 2nd × (i % (N / 2)) + (i+1) % 2th bit in the codeword interleaving sequence.

[0223] From the second data stream The 2nd × (i % (N / 2)) + i % 2th bit in the codeword interleaving sequence.

[0224] From the second data stream The 2nd × (i % (N / 2)) + (i+1) % 2th bit in the codeword interleaving sequence.

[0225] From the second data stream The 2nd × (i % (N / 2)) + i % 2th bit in the codeword interleaving sequence.

[0226] From the second data stream The 2nd × (i % (N / 2)) + (i+1) % 2th bit in the codeword interleaving sequence.

[0227] From the second data stream The 2nd × (i % (N / 2)) + i % 2th bit in the codeword interleaving sequence.

[0228] From the second data stream The 2nd × (i % (N / 2)) + (i+1) % 2th bit in the codeword interleaving sequence.

[0229] For scenarios where p=16 and m=16, for example, as shown in Figure 8(a), 16 first data streams are obtained from 1.6T 8:16PMA. Another example, as shown in Figure 8(b), 16 first data streams are obtained from 1.6T 16:16PMA. Yet another example, as shown in Figure 8(c), 16 first data streams are obtained from 1.6TPCS.

[0230] Figure 11(a) is a schematic diagram of another implementation of the first and second data processing in this application. As shown in Figure 11(a), 16 first data streams (i.e., first data streams 0-15) are processed by convolutional interleaving, internal code encoding, and first interleaving to obtain 16 second data streams. Considering that the number of bits N included in the internal code codeword is even, one codeword interleaving sequence is obtained from each second data stream, totaling 16×N bits, which is called the first bit set. The first bit set is processed by the second interleaving to obtain a second bit set including 16×N bits, and DP-16QAM symbol mapping is performed on the second bit set to map every 8 bits to obtain one DP-16QAM symbol, resulting in a total of 4×N DP-16QAM symbols, i.e., S0, S1, S2, ..., S N-2 ,S 4×N-1 Consider S i For the i-th (0≤i≤2×N-1) DP-16QAM symbol out of 2×N DP-16QAM symbols, the mapping to the 8 bits of the i-th DP-16QAM symbol is denoted as . As can be seen, in the embodiment shown in Figure 10(a), each first data stream that has undergone convolutional interleaving is first encoded with an internal code and then interleaved.

[0231] Figure 11(b) is a schematic diagram of another implementation of the first data processing and the second data processing in the embodiments of this application. Unlike the implementation shown in Figure 11(a), as shown in Figure 11(b), each first data stream after convolutional interleaving is first interleaved and then encoded using internal codes.

[0232] Figure 11(c) is a schematic diagram of another implementation of the first data processing and the second data processing in the embodiments of this application. Unlike the implementation shown in Figures 11(a) and 11(b), as shown in Figure 11(c), each first data stream after convolutional interleaving is processed in parallel for internal code encoding and first interleaving.

[0233] It should be noted that, for the implementation methods shown in Figures 11(a), 11(b) and 11(c) above, in some scenarios requiring low latency, the convolutional interleaving process can be bypassed, which has the advantages of low latency and low power consumption.

[0234] For the scenario where p = 16 and m = 16, the fourth specific implementation of the second interleaving is given below, where 0 ≤ i ≤ 2 × N - 1.

[0235] From the second data stream The 2nd × (i % (N / 2)) + i % 2th bit in the codeword interleaving sequence.

[0236] From the second data stream The 2nd × (i % (N / 2)) + (i+1) % 2th bit in the codeword interleaving sequence.

[0237] From the second data stream The 2nd × (i % (N / 2)) + i % 2th bit in the codeword interleaving sequence.

[0238] From the second data stream The 2nd × (i % (N / 2)) + (i+1) % 2th bit in the codeword interleaving sequence.

[0239] From the second data stream The 2nd × (i % (N / 2)) + i % 2th bit in the codeword interleaving sequence.

[0240] From the second data stream The 2nd × (i % (N / 2)) + (i+1) % 2th bit in the codeword interleaving sequence.

[0241] From the second data stream The 2nd × (i % (N / 2)) + i % 2th bit in the codeword interleaving sequence.

[0242] From the second data stream The 2nd × (i % (N / 2)) + (i+1) % 2th bit in the codeword interleaving sequence.

[0243] For scenarios where p=16 and m=32, for example, as shown in Figure 8(a), 16 first data streams are obtained from 1.6T 8:16PMA. Another example, as shown in Figure 8(b), 16 first data streams are obtained from 1.6T 16:16PMA. Yet another example, as shown in Figure 8(c), 16 first data streams are obtained from 1.6TPCS.

[0244] Figure 12(a) is a schematic diagram of another implementation of the first and second data processing in this application. As shown in Figure 12(a), 16 first data streams (i.e., first data streams 0-15) are convolutionally interleaved to obtain 16 convolutionally interleaved data streams. Each convolutionally interleaved data stream undergoes a 1:2K-bit block distribution to obtain 2 first sub-data streams, resulting in a total of 32 first sub-data streams. The 32 first sub-data streams are then encoded using internal codes and subjected to first interleaving to obtain 32 second data streams. Considering that the number of bits N included in the internal codeword is even, one codeword interleaving sequence is obtained from each second data stream, totaling 32×N bits, which is called the first bit set. The first bit set undergoes a second interleaving to obtain a second bit set comprising 32×N bits. DP-16QAM symbol mapping is then performed on the second bit set to map every 8 bits to one DP-16QAM symbol, resulting in a total of 4×N DP-16QAM symbols, namely S0, S1, S2, ..., S... N-2 ,S 4×N-1 Consider S i For the i-th (0≤i≤4×N-1)-th DP-16QAM symbol out of 4×N DP-16QAM symbols, the 8 bits mapped to the i-th (0≤i≤4×N-1)-th DP-16QAM symbol are denoted as As can be seen, in the embodiment shown in Figure 12(a), each first data stream that has undergone convolutional interleaving is first encoded with an internal code and then interleaved.

[0245] Figure 12(b) is a schematic diagram of another implementation of the first data processing and the second data processing in the embodiments of this application. Unlike the implementation shown in Figure 12(a), as shown in Figure 12(b), each first data stream after convolutional interleaving is first interleaved and then encoded with internal code.

[0246] It should be noted that, for the implementation methods shown in Figures 12(a) and 12(b) above, in some scenarios requiring low latency, the convolutional interleaving process can be bypassed, which has the advantages of low latency and low power consumption.

[0247] For the scenario where p=16 and m=32, the third specific embodiment of the second interleaving described above can be used, which will not be repeated here.

[0248] Based on the above description of the first and second data processing methods, several specific implementation examples are given below.

[0249] Example 1: This example provides a specific implementation scheme for 8 first data streams when the transmitting device 01 transmits 1.6T service and the internal code encoding uses BCH(126,110). Where p = 8, m = 8.

[0250] This embodiment obtains eight first data streams from the 1.6T 8:8PMA shown in Figure 7(a), or the 1.6T 16:8PMA shown in Figures 7(b) and 7(c), or the 1.6T 4:8PMA shown in Figure 7(f). Figure 13 is a schematic diagram of the format of one type of first data stream in this embodiment. Combining 1.6T PCS processing and 1.6T PMA processing, each first data stream satisfies the format shown in Figure 13. Every four consecutive RS symbols come from four different RS codewords, namely from the four RS encoders RS-A, RS-B, RS-C, and RS-D mentioned above. The four adjacent RS symbols are represented as an RS-FEC symbol-quartet.

[0251] Figure 14 is a schematic diagram of one implementation of convolutional interleaving in this application. As shown in Figure 14, each convolutional interleaver contains r = 3 delay lines, and each delay unit contains d = 40 bits, i.e., 4 RS symbols. Delay line 0 has 2Q delay units, delay line 1 has Q delay units, and delay line 2 has no delay units. Figure 15 is a schematic diagram of another implementation of convolutional interleaving in this application. As shown in Figure 15, each convolutional interleaver contains r = 3 delay lines, and each delay unit stores d = 40 bits, i.e., 4 RS symbols. Delay line 0 has 0 delay units, delay line 1 has Q delay units, and delay line 2 contains 2Q delay units.

[0252] For ease of description, let's use A. i (a) represents the a-th RS-FEC symbol-quartet in the first data stream i, A′ i (a) is the a-th RS-FEC symbol-quartet in the output data stream of convolutional interleaver i, which consists of 4 RS symbols output by one delay line of the convolutional interleaver, where a is an integer greater than or equal to 0, and 0 ≤ i < 8. The specific implementation process of convolutional interleaver is to... i (3t) Input to delay line 0, and delay line 0 outputs A′. i (3t); then A i (3t+1) is input to delay line 1, and delay line 1 outputs A′. i (3t+1); then A i (3t+2) is input to delay line 2, and delay line 2 outputs A′. i (3t+2); then A i(3t+3) is input to delay line 0, and delay line 0 outputs A′. i (3t+3); and so on. When Q≥23, A′ in the data stream output by the convolutional interleaver... i (3t), A′ i (3t+1), A′ i (3t+2) A total of 12 consecutive RS symbols come from 12 different RS codewords. To reduce the difficulty of high-speed implementation of the convolutional interleaver, let Q be a multiple of 2, 4, or 8, such as Q = 24, 26, 28, 32, etc. Where t is an integer greater than or equal to 0.

[0253] Then, the data stream output from each convolutional interleaver is encoded using internal code. The internal code employs extended BCH(126,110), which is obtained by shortening the T=2 BCH(127,113) constructed based on the GF(2^7) field by 3 bits to obtain BCH(124,110). Then, odd-bit parity and even-bit parity are added to BCH(124,110) to finally obtain BCH(126,110). Its corresponding generator polynomial is: g(x) = M1(x)·M3(x)·(x... 2 +1)=(x 7 +x 3 +1)(x 7 +x 3 +x 2 +x+1)(x 2 +1)=x 16 +x 14 +x 11 + x 10 +x 9 +x 7 +x 5 +x 3 +x+1.

[0254] Figure 16 is a schematic diagram of one implementation of the internal code encoding in this application. As shown in Figure 16, the 3 delay lines of the convolutional interleaver are polled 11 times to output 33 consecutive RS-FEC symbol-quartets (i.e., 132 RS symbols), which is represented as {A′ i (3t),A′ i (3t+1),A′ i (3t+2),A′ i (3t+3),A′ i (3t+4),A′ i (3t+5),…,A′ i (3t+30),A′ i (3t+31),A′ i (3t+32)} is divided into 12 information bit sequences U.j Each information bit sequence contains 110 bits, represented by (u0, u1, ..., u...). 108 ,u 109 ) represents, and the information bit sequence U j This includes bits 110×j to 110×j+109 of the 33 RS-FEC symbol-quartets shown. For each information bit block U... j BCH(126,110) encoding with 16 parity bits results in a codeword C containing 126 internal code bits. j The 16 parity bits are represented as (v0, v1, ..., v 14 ,v 15 Then the internal codeword C j The 126 bits are represented as (u0, u1, ..., u 108 ,u 109 ,v0,v1,…,v 14 ,v 15 ), where 0≤j<12. Then the data stream i output by the internal code encoder i is processed by the first interleaver i to obtain the second data stream i, where 0≤i<8.

[0255] Figure 17 is a schematic diagram of one implementation of the first interleaving in this application. As shown in Figure 17, performing the first interleaving i on data stream i involves performing the first interleaving process on each BCH(126,110) codeword C in data stream i to obtain the codeword interleaving sequence C′. Specifically, this involves interleaving the 110 information bits (u0, u1, ..., u) of each BCH(126,110) codeword C. 108 ,u 109 Perform a left circular shift of (i*δ)%110 bits to obtain a sequence W consisting of 110 bits, denoted as (w0, w1, ..., w...). 108 ,w 109 ), where w j = u(j+(i*δ)%110)%110, 0≤i<8, 0≤j<110, while the codeword C has 16 parity bits (v0,v1,…,v 14 ,v 15 The position of ) remains unchanged. Alternatively, the 110 information bits (u0, u1, ..., u) of each BCH(126, 110) codeword C in the data stream i are kept unchanged. 108 ,u 109 Perform a right circular shift. Each bit yields a sequence W consisting of 110 bits, denoted as (w0, w1, ..., w...). 108 ,w 109 ),in, If 0 ≤ i < 8, 0 ≤ j < 110, then the 126 bits of the codeword interleaved sequence C′ are represented as (w0, w1, ..., w 108 ,w 109 ,v0,v1,…,v 14 ,v 15 ). Where δ and Both are integer multiples of 10, and δ and Both are greater than 10 and less than 110. To ensure the concatenated code after the first interleaving can better resist bursts, δ and The possible values ​​are 20, 30, 40, 70, and 80. The following example, using a rightward loop, shows the specific loop shifts corresponding to the first interlacing 0 to the first interlacing 7. The values ​​of are shown in Table 1.

[0256] Table 1

[0257] Then, a second interleaving is performed on the eight second data streams. Specifically, one codeword interleaving sequence C′ is obtained from each second data stream, totaling 8 × 126 bits. Let C' represent the j-th (0≤j<126) bit in the codeword interleaving sequence C′ obtained from the second data stream i (0≤i≤7). For ease of description, these 8 interleaving sequences C′ are called the first bit set. The first bit set is then subjected to a second interleaving to obtain 1004 consecutive bits in the data stream, which is represented as the second bit set. Let represent the (8i+j)th bit of the second bit set, where 0 ≤ i ≤ 125 and 0 ≤ j ≤ 7. Then, a specific embodiment of the second interleaving is:

[0258] From the second data stream The 2nd (i%63)+i%2th bit in the codeword interleaving sequence.

[0259] From the second data stream The 2nd × (i % 63) + (i + 1) % 2th bit in the codeword interleaving sequence.

[0260] From the second data stream The 2nd (i%63)+i%2th bit in the codeword interleaving sequence.

[0261] From the second data stream The 2nd × (i % 63) + (i + 1) % 2th bit in the codeword interleaving sequence.

[0262] From the second data stream The 2nd (i%63)+i%2th bit in the codeword interleaving sequence.

[0263] From the second data stream The 2nd × (i%63) + (i+1)%2th bit in the codeword interleaving sequence.

[0264] From the second data stream The 2nd (i%63)+i%2th bit in the codeword interleaving sequence.

[0265] From the second data stream The 2nd × (i%63) + (i+1)%2th bit in the codeword interleaving sequence.

[0266] Then, each second bit set is mapped using DP-16QAM symbols to obtain 126 DP-16QAM symbols, specifically by mapping 8 consecutive bits from the second bit set. Mapped to a DP-16QAM symbol S i Where 0≤i≤125, the specific mapping method is as follows: Mapped to DP-16QAM symbol S i The I-path component in the X-polarization direction; Mapped to DP-16QAM symbol S i The Q-path component in the X-polarization direction; Mapped to DP-16QAM symbol S i The I-path component in the Y-polarization direction; Mapped to DP-16QAM symbol S i The Q-path component in the Y-polarization direction.

[0267] For each component, its bit-to-symbol magnitude mapping is (0,0)→-3, (0,1)→-1, (1,1)→+1, (1,0)→+3. After the second interleaving and DP-16QAM symbol mapping, each inner codeword is uniformly mapped to each constellation point of the DP-16QAM symbol. This ensures that errors in each DP-16QAM symbol at the receiver are uniformly mapped to each inner codeword, improving the performance of concatenated coding.

[0268] Figure 18 is a schematic diagram of a DSP frame structure in an embodiment of this application. As shown in Figure 18, the 6048 DP-16QAM symbols obtained after 48 consecutive second interleavings and DP-16QAM symbol mappings are finally encapsulated by inserting a pilot symbol every 63 DP-16QAM symbols, resulting in a DSP frame as shown in Figure 18. This frame contains 96 subframes, each containing 64 DP-16QAM symbols. The first symbol of each subframe is the inserted pilot symbol, and the remaining 63 symbols are the DP-16QAM symbols obtained from the second bit set mapping. The inserted pilot symbol is one of 3+3j, 3-3j, -3+3j, and -3-3j, where j is the imaginary unit of a complex number.

[0269] Example 2: This Example 2 is a specific scheme based on Example 1, which first performs the first interleaving and then performs the corresponding internal code encoding.

[0270] In this embodiment 2, the eight first data streams are convolutionally interleaved according to the convolutional interleaving scheme given in embodiment 1. Then, each convolutionally interleaved data stream undergoes first interleaving and internal code encoding. Specifically, the 132 consecutive RS symbols, i.e., 33 RS-FEC-symbol-quartets, in each convolutionally interleaved data stream are represented as {A′ i (3t),A′ i (3t+1),A′ i (3t+2),A′ i (3t+3),A′ i (3t+4),A′ i (3t+5),…,A′ i (3t+30),A′ i (3t+31),A′ i (3t+32)} is divided into 12 information bit sequences U. j Each information bit sequence contains 110 bits, represented by (u0, u1, ..., u...). 108 ,u 109 ) represents, and the information bit sequence U j This includes bits 110×j to 110×j+109 of the 33 RS-FEC symbol-quartets shown. For each information bit sequence U... j The first interleaving is performed to obtain the information bit interleaving sequence W. j It contains 110 bits and is represented as (w0, w1, ..., w 108 ,w 109 Then, for each information bit, interleave the sequence W. jPerform BCH(126,110) encoding, and add 16 parity bits to obtain a 126-bit internal codeword C. j The 16 parity bits are represented as (v0, v1, ..., v 14 ,v 15 Then the internal codeword C j The 126 bits are represented as (w0, w1, ..., w 108 ,w 109 ,v0,v1,…,v 14 ,v 15 ), where 0≤j<12. The generator polynomial of BCH(126,110) is as described in Example 1.

[0271] One specific implementation of the first interleaving is as follows: A specific implementation of the first interleaving of the data stream i after convolutional interleaving is to perform the first interleaving on each information bit sequence U = (u0, u1, ..., u...) in the data stream i. 108 ,u 109 Perform a left circular shift (i*δ)% 110 bits to obtain an information bit interleaving sequence W = (w0, w1, ..., w...). 108 ,w 109 ), where w j = u(j+(i*δ)%110)%110. Or, for each information bit sequence U = (u0, u1, ..., u...) in data stream i... 108 ,u 109 Perform a right circular shift. This yields an information bit interleaving sequence W = (w0, w1, ..., w1) consisting of 110 information bits. 108 ,w 109 ),in Where 0≤i<8, 0≤j<110, δ and Both are integer multiples of 10, and δ and Both are greater than 10 and less than 110. To ensure the interleaved concatenated code can better resist bursts, δ and The possible values ​​are 20, 30, 40, 70, 80, and 90. Below, taking a rightward loop as an example, the specific loop shift values ​​corresponding to the first interlacing 0 to the first interlacing 31 are...

[0272] The eight second data streams, after the first interleaving and internal code encoding, undergo second interleaving, DP-16QAM mapping, and DSP framing processing according to the scheme given in Example 1 to obtain the first dual-polarization symbol stream to be sent, which will not be elaborated here.

[0273] Example 3: This example 3 provides a specific scheme for 16 first data streams when the transmitting device 01 transmits 1.6T service and the internal code encoding adopts BCH(126,110).

[0274] In this embodiment, 16 first data streams are obtained from the 1.6T 8:16PMA shown in Figure 8(a), or the 1.6T 16:16PMA shown in Figure 8(b), or the PCS module shown in Figure 8(c), or the 1.6T 4:16PMA shown in Figure 8(d). Then, a convolutional interleaver as shown in Figure 14 is used to convolve and interleave each first data stream. When Q≥11, A′ in the data stream output by the convolutional interleaver... i (3t), A′ i (3t+1), A′ i (3t+2) A total of 12 consecutive RS symbols come from 12 different RS codewords. Alternatively, a convolutional interleaver as shown in Figure 15 can be used to convolve and interleave each first data stream. When Q≥12, A′ in the data stream output by the convolutional interleaver... i (3t), A′ i (3t+1), A′ i (3t+2) A total of 12 consecutive RS symbols come from 12 different RS codewords.

[0275] To reduce the difficulty of implementing high-speed convolutional interleavers, Q is set to a multiple of 2, 4, or 8, such as Q = 12 or 16.

[0276] Then, using the internal code encoding and first interleaving scheme in Example 1, each data stream that has undergone convolutional interleaving is first encoded with internal code and then interleaved with the first interleaving to obtain 16 second data streams. Alternatively, using the first interleaving and internal code encoding scheme in Example 2, each data stream that has undergone convolutional interleaving is first interleaved and then encoded with internal code to obtain 16 second data streams.

[0277] The first interleaving process for data stream i involves performing a first interleaving process on each BCH(126,110) codeword C in data stream i to obtain a codeword interleaving sequence C′. Specifically, this involves interleaving the 110 information bits (u0, u1, ..., u) of each BCH(126,110) codeword C in data stream i. 108 ,u 109 Perform a right circular shift. Each bit yields a sequence W consisting of 110 bits, denoted as (w0, w1, ..., w...). 108 ,w 109 ),in, If 0 ≤ i < 16, 0 ≤ j < 110, then the 126 bits of the codeword interleaved sequence C′ are represented as (w0, w1, ..., w108 ,w 109 ,v0,v1,…,v 14 ,v 15 ). where δ and Both are integer multiples of 10, and δ and Both are greater than 10 and less than 110. To ensure the concatenated code after the first interleaving can better resist bursts, δ and The possible values ​​are 20, 30, 40, 70, and 80. The following example, using a rightward loop, shows the specific loop shifts corresponding to the first interlacing 0 to the first interlacing 15. The values ​​of are shown in Table 2.

[0278] Table 2

[0279] Then, a second interleaving is performed on the 16 second data streams. Specifically, one codeword interleaving sequence C′ is obtained from each second data stream, totaling 16 × 126 bits. Let C' represent the j-th (0≤j≤126) bit in the codeword interleaving sequence C' obtained from the second data stream i (0≤i≤15). For convenience, this 16-bit interleaving sequence C' is called the first bit set. The first bit set is then subjected to a second interleaving to obtain 2016 consecutive bits in the second interleaved data stream, which is represented as the second bit set. This represents the (8i+j)th bit of the second bit set, where 0 ≤ i ≤ 251 and 0 ≤ j ≤ 7. A specific embodiment of the second interleaving is as follows:

[0280] From the second data stream The 2nd (i%63)+i%2th bit in the codeword interleaving sequence.

[0281] From the second data stream The 2nd × (i%63) + (i+1)%2th bit in the codeword interleaving sequence.

[0282] From the second data stream The 2nd (i%63)+i%2th bit in the codeword interleaving sequence.

[0283] From the second data stream The 2nd × (i%63) + (i+1)%2th bit in the codeword interleaving sequence.

[0284] From the second data stream The 2nd (i%63)+i%2th bit in the codeword interleaving sequence.

[0285] From the second data stream The 2nd × (i % 63) + (i + 1) % 2th bit in the codeword interleaving sequence.

[0286] From the second data stream The 2nd (i%63)+i%2th bit in the codeword interleaving sequence.

[0287] From the second data stream The 2nd × (i % 63) + (i + 1) % 2th bit in the codeword interleaving sequence.

[0288] Then, DP-16QAM symbol mapping is performed on each second bit set to obtain 252 DP-16QAM symbols. Specifically, 8 consecutive bits in the second bit set are mapped... Mapped to a DP-16QAM symbol S i Where 0≤i≤251, the specific mapping method is as follows: Mapped to DP-16QAM symbol S i The I-path component in the X-polarization direction; Mapped to DP-16QAM symbol S i The Q-path component in the X-polarization direction; Mapped to DP-16QAM symbol S i The I-path component in the Y-polarization direction; Mapped to DP-16QAM symbol S i The I-path component in the Y-polarization direction.

[0289] For each component, its bit-to-symbol magnitude mapping is (0,0)→-3, (0,1)→-1, (1,1)→+1, (1,0)→+3. After the second interleaving and DP-16QAM symbol mapping, each inner codeword is uniformly mapped to each constellation point of the DP-16QAM symbol. This ensures that errors in each DP-16QAM symbol at the receiver are uniformly mapped to each inner codeword, improving the performance of concatenated coding.

[0290] Finally, the 6048 DP-16QAM symbols obtained from the second interleaving and DP-16QAM symbol mapping, obtained through 24 consecutive iterations, are encapsulated by inserting a pilot symbol every 63 DP-16QAM symbols, resulting in a DSP frame as shown in Figure 18. This frame contains 96 subframes, each with 64 DP-16QAM symbols. The first symbol of each subframe is the inserted pilot symbol, and the remaining 63 symbols are the DP-16QAM symbols obtained from the second bit set mapping. The inserted pilot symbol is one of 3+3j, 3-3j, -3+3j, or -3-3j, where j is the imaginary unit of the complex number.

[0291] Example 4: This example 4 provides a specific solution for a 1:4 distribution scenario when the transmitting device 01 transmits 1.6T service and the internal code encoding uses BCH(126,110).

[0292] In this embodiment, eight first data streams are obtained from either the 1.6T 8:8PMA shown in Figure 7(a) or the 1.6T 16:8PMA shown in Figures 7(b) and 7(c). Since the transmitting device 01 transmits 1.6T services, the first data stream output by the PMA in the transmitting processing module 02 after processing the data from the transmitting device 01 conforms to the format shown in Figure 13. In the first data stream, every four consecutive RS symbols come from the four RS encoders described above: RS-A, RS-B, RS-C, and RS-D. Each first data stream is fed into the convolutional interleaver described in Embodiment 1 for convolutional interleaving. Then, each convolutionally interleaved data stream is distributed in a 1:4 ratio to obtain four first sub-data streams.

[0293] Figure 19 is a schematic diagram of one embodiment of the data stream distribution in this application. As shown in Figure 19, using B i (t) represents the 12 consecutive RS symbols in the i-th convolutionally interleaved data stream, which includes the A′ outputs of the three delay lines of convolution interleaver i. i (3t), A′ i (3t+1), A′ i (3t+2), i.e., B i (t)=(A′ i (3t), A′ i (3t+1), A′ i (3t+2)). By distributing the convolutionally interleaved data stream i in a 1:4 ratio, four first sub-data streams are obtained, which are the 48 consecutive RS symbols B in the convolutionally interleaved data stream i. i (4t),B i (4t+1),B i (4t+2),B i B in (4t+3)i Distribute (4t+j) to the first sub-data stream 4i+j, where 0≤i<8, 0≤j<4, and t is an integer. In this case, the granularity of distribution is 120 bits (i.e., 12 RS symbols). In other specific applications, the granularity of distribution can be 110 bits (i.e., 11 RS symbols), which means distributing 44 consecutive RS symbols B from the first data stream i. i (4t),B i (4t+1),B i (4t+2),B i B in (4t+3) i (4t+j) is distributed to the first sub-data stream 4i+j, where 0≤i<8, 0≤j<4, and t is an integer.

[0294] Another implementation of the 1:4 distribution of the data stream in this application embodiment is to divide every 33 consecutive RS-FEC-symbol-quartets in the convolutionally interleaved data stream into 12 information bit sequences U of length 110 bits, as shown in Figure 16. j Where 0 ≤ j < 12. Data distribution involves round-robin distribution of the information bit sequences to the four first sub-data streams. Specifically, for the i-th convolutionally interleaved data stream, information bit sequences U0, U4, and U8 are distributed to the first sub-data stream 4×i; information bit sequences U1, U5, and U9 are distributed to the first sub-data stream 4×i+1; and information bit sequences U2, U6, and U7 are distributed to the first sub-data stream 4×i+1. 10 Distribute to the first sub-data stream 4×i+2; information bit sequence U3, information bit sequence U7, information bit sequence U 11 Distribute it to the first sub-data stream 4×i+3.

[0295] Then, using the internal code encoding and first interleaving scheme in Example 1, each first sub-data stream is first internally encoded and then first interleaved to obtain 32 second data streams. Alternatively, using the first interleaving and internal code encoding scheme in Example 2, each first sub-data stream is first first interleaved and then internally encoded to obtain 32 second data streams.

[0296] Then, a second interleaving is performed on the 32 second data streams. Specifically, one codeword interleaving sequence C′ is obtained from each second data stream, totaling 32 × 126 bits. Let C' represent the j-th (0≤j≤126) bit in the codeword interleaving sequence C' obtained from the second data stream i (0≤i≤31). For convenience, this 32-bit interleaving sequence C' is called the first bit set. The first bit set is then subjected to a second interleaving to obtain 4032 consecutive bits in the data stream, which is represented as the second bit set. Let represent the (8i+j)th bit of the second bit set, where 0 ≤ i ≤ 503 and 0 ≤ j ≤ 7. Then, a specific embodiment of the second interleaving is:

[0297] From the second data stream The 2nd (i%63)+i%2th bit in the codeword interleaving sequence.

[0298] From the second data stream The 2nd × (i % 63) + (i + 1) % 2th bit in the codeword interleaving sequence.

[0299] From the second data stream The 2nd (i%63)+i%2th bit in the codeword interleaving sequence.

[0300] From the second data stream The 2nd × (i % 63) + (i + 1) % 2th bit in the codeword interleaving sequence.

[0301] From the second data stream The 2nd (i%63)+i%2th bit in the codeword interleaving sequence.

[0302] From the second data stream The 2nd × (i % 63) + (i + 1) % 2th bit in the codeword interleaving sequence.

[0303] From the second data stream The 2nd (i%63)+i%2th bit in the codeword interleaving sequence.

[0304] From the second data stream The 2nd × (i % 63) + (i + 1) % 2th bit in the codeword interleaving sequence.

[0305] Then, DP-16QAM symbol mapping is performed on each second bit set to obtain 504 DP-16QAM symbols. Specifically, 8 consecutive bits in the second bit set are mapped... Mapped to a DP-16QAM symbol S i Where 0≤i≤503, the specific mapping method is as follows: Mapped to DP-16QAM symbol S i The I-path component in the X-polarization direction; Mapped to DP-16QAM symbol S i The Q-path component in the X-polarization direction; Mapped to DP-16QAM symbol S i The I-path component in the Y-polarization direction; Mapped to DP-16QAM symbol S i The Q-path component in the Y-polarization direction.

[0306] For each component, its bit-to-symbol magnitude mapping is (0,0)→-3, (0,1)→-1, (1,1)→+1, (1,0)→+3. After the second interleaving and DP-16QAM symbol mapping, each inner code is uniformly mapped to each constellation point of the DP-16QAM symbol. This ensures that errors in each DP-16QAM symbol at the receiver are uniformly mapped to each inner codeword, improving the performance of the concatenated code.

[0307] Finally, the 6048 DP-16QAM symbols obtained from the above second interleaving and DP-16QAM mapping are interleaved 12 times consecutively, with a pilot symbol inserted every 63 DP-16QAM symbols. This encapsulation results in a DSP frame as shown in Figure 18, which contains 96 subframes. Each subframe contains 64 DP-16QAM symbols, where the first symbol of each subframe is the inserted pilot symbol, and the remaining 63 symbols are the DP-16QAM symbols obtained from the second bit set mapping. The inserted pilot symbol is one of 3+3j, 3-3j, -3+3j, or -3-3j, where j is the imaginary unit of the complex number.

[0308] Example 5: This example 5 provides a specific scheme for 1:2 distribution when the transmitting device 01 transmits 1.6T service and the internal code encoding adopts BCH(126,110).

[0309] In this embodiment, 16 first data streams are obtained from the 1.6T 8:16PMA shown in Figure 8(a), or the 1.6T 16:16PMA shown in Figure 8(b), or the PCS shown in Figure 8(c), or the 1.6T 4:16PMA shown in Figure 8(d). Since the transmitting device 01 transmits 1.6T services, the first data stream output by the PMA in the transmitting processing module 02 after processing the data from the transmitting device 01 meets the format shown in Figure 13, with each consecutive 4 RS symbols coming from the aforementioned 4 RS encoders RS-A, RS-B, RS-C, and RS-D. Each first data stream is fed into the convolutional interleaver described in Embodiment 1 for convolutional interleaving. Then, each convolutionally interleaved data stream is distributed in a 1:2 ratio to obtain 2 first sub-data streams.

[0310] Figure 20 is a schematic diagram of one embodiment of the data stream 1:2 distribution in this application. As shown in Figure 20, using B... i (t) represents the 12 consecutive RS symbols in the i-th data stream, which include the A′ outputs of the three delay lines of the convolutional interleaver i. i (3t), A′ i (3t+1), A′ i (3t+2) A total of 12 consecutive RS symbols, i.e., B i (t)=(A′ i (3t), A′ i (3t+1), A′ i (3t+2)). By distributing i, the convolutionally interleaved data stream i is divided in a 1:2 ratio to obtain two first sub-data streams, which are the 24 consecutive RS symbols B in the convolutionally interleaved data stream i. i (2t),B i B in (2t+1) i (2t+j) is distributed to the first sub-data stream 2i+j, where 0≤i<16, 0≤j<2, and t is an integer.

[0311] Another implementation of the 1:2 distribution of the data stream in this application embodiment is to divide every 33 consecutive RS-FEC-symbol-quartets in the convolutionally interleaved data stream into 12 information bit sequences U of length 110 bits, as shown in Figure 16. j Where 0 ≤ j < 12. Data distribution involves round-robin distributing the information bit sequence to the two first sub-data streams, i.e., to the i-th convolutionally interleaved data stream, with information bit sequence U0, information bit sequence U2, information bit sequence U4, information bit sequence U6, and information bit sequence U... 8, Information bit sequence U 10 Distribute to the first sub-data stream 2×i; information bit sequence U1, information bit sequence U3, information bit sequence U5, information bit sequence U7, information bit sequence U9, information bit sequence U 11 Distribute it to the first sub-data stream 2×i+1.

[0312] Then, the 32 first sub-data are encoded according to the scheme given in Example 4, including internal code encoding, first interleaving, second interleaving, DP-16QAM symbol mapping, and DSP framing, to obtain a first dual-polarization symbol stream to be sent.

[0313] Example 6: This Example 6 is a specific solution based on Example 1, Example 2 or Example 4, when considering the transmission of 2x800G services by the transmitting device 01.

[0314] In this embodiment, eight first data streams are obtained from two 800G 4:4PMA processors as shown in Figure 7(d). Combining 800G PCS processing and 800G 32:4PAM processing, each first data stream conforms to the format shown in Figure 13. Every four consecutive RS symbols come from four different RS codewords, namely, from the aforementioned four RS encoders: RS-A, RS-B, RS-C, and RS-D. These four consecutive RS symbols are represented as RS-FEC symbol-quartets. Then, a convolutional interleaver as shown in Figure 14 or Figure 15 is used to convolve and interleave each first data stream. Specifically, three consecutive RS-FEC symbol-quartets in the first data stream, i.e., every twelve consecutive RS symbols A... i (3t), A i (3t+1), A i A in (3t+2) i (3t+j) is fed into the j-th delay line of the convolutional interleaver, where 0≤j<2, and t is an integer. When the convolutional interleaver shown in Figure 14 is used, and Q≥45, A′ in the data stream output by the convolutional interleaver... i (3t), A′ i (3t+1), A′ i (3t+2) A total of 12 consecutive RS symbols come from 12 different RS codewords. When using the convolutional interleaver shown in Figure 15, when Q≥46, A′ in the data stream output by the convolutional interleaver i (3t), A′ i (3t+1), A′ i (3t+2) A total of 12 consecutive RS symbols come from 12 different RS codewords. To reduce the difficulty of high-speed implementation of the convolutional interleaver, Q is set to a multiple of 2, 4, or 8, such as Q = 46, 48, or 52.

[0315] Then, the eight convolutionally interleaved data streams are subjected to internal code encoding, first interleaving, second interleaving, DP-16QAM symbol mapping, and DSP framing according to the scheme of Example 1 or Example 2 to obtain a first dual-polarization symbol stream to be transmitted. Alternatively, the eight convolutionally interleaved data streams are distributed, internally encoded, first interleaved, second interleaved, DP-16QAM symbol mapping, and DSP framing according to the scheme of Example 4 to obtain a first dual-polarization symbol stream to be transmitted.

[0316] Example 7: This Example 7 is a solution based on Example 1, Example 2 or Example 4, when considering the transmission of 4x400G services by the transmitting device 01.

[0317] In this embodiment, eight first data streams are obtained from the four 400G 2:2 PMAs shown in Figure 7(e). Combining 400G PCS processing and 400G 16:2 PAM processing, each first data stream conforms to the format shown in Figure 13. Every four consecutive RS symbols come from four different RS codewords, namely from the aforementioned RS-A, RS-B, RS-C, and RS-D encoders. These four consecutive RS symbols are represented as RS-FEC symbol-quartets. Then, a convolutional interleaver, as shown in Figure 14 or Figure 15, is used to convolve and interleave each first data stream. Specifically, every 12 consecutive RS symbols A in the first data stream are... i (3t), A i (3t+1), A i A in (3t+2) i (3t+j) is fed into the j-th delay line of the convolutional interleaver, where A i (3t+j) represents four consecutive RS symbols in the first data stream, where 0 ≤ j < 2, and t is an integer. When Q ≥ 91, A′ in the data stream output by the convolutional interleaver... i (3t), A′ i (3t+1), A′ i (3t+2) A total of 12 consecutive RS symbols come from 12 different RS codewords. To reduce the difficulty of high-speed implementation of the convolutional interleaver, Q is set to a multiple of 2, 4, or 8, such as Q = 92, 94, 96, or 100.

[0318] Then, the eight convolutionally interleaved data streams are subjected to internal code encoding, first interleaving, second interleaving, DP-16QAM symbol mapping, and DSP framing according to the scheme of Embodiment 1 or Embodiment 2 to obtain a first dual-polarization symbol stream to be transmitted. Alternatively, the eight convolutionally interleaved data streams are distributed, internally encoded, first interleaved, second interleaved, DP-16QAM symbol mapping, and DSP framing according to the scheme of Embodiment 4 to obtain a first dual-polarization symbol stream to be transmitted.

[0319] Example 8: This example 8 proposes a lower redundancy and lower power consumption internal code encoding scheme based on examples 1 to 7.

[0320] In this embodiment, the first data is convolutionally interleaved according to any of the convolutional interleaving schemes given in Embodiments 1 to 7. Then, each convolutionally interleaved data stream is encoded using internal code, which employs extended hamming (128, 120). Specifically, the encoding process involves encoding 12 consecutive RS symbols {A′} in the convolutionally interleaved data stream. i (3t),A′ i (3t+1),A′i (3t+2)} is taken as an information bit sequence U, and (u0,u1,…,u 118 ,u 119 The code is represented as follows: Each information bit sequence U is extended using Hamming (128, 120) encoding to add 8 check bits, resulting in a 128-bit codeword C. The 8 check bits are represented as (v0, v1, ..., v6, v7). Therefore, the 128 bits of the codeword C are represented as (u0, u1, ..., u...). 118 ,u 119 (v0,v1,…,v6,v7).

[0321] Then, the data stream i encoded with internal codes is interleaved first to obtain the second data stream i, where 0 ≤ i < 8 or 0 ≤ i < 16. The first interleaving of data stream i specifically involves interleaving each extended hamming (128, 120) codeword C in data stream i to obtain the codeword interleaving sequence C′. Specifically, each extended hamming (128, 120) codeword C has 120 information bits (u0, u1, ..., u...). 118 ,u 119 Perform a left circular shift of (i*δ) % 120 bits to obtain a sequence W = (w0, w1, ..., w...) bits. 118 ,w 119 ), where w j = u(j+(i*δ)%120)%120, 0≤j<120. The positions of the 8 parity bits (v0,v1,…,v6,v7) of codeword C remain unchanged. Alternatively, the 120 information bits (u0,u1,…,u) of each extended hamming(128,120) codeword C in data stream i are... 108 ,u 109 Perform a right circular shift. This yields a 120-bit sequence W = (w0, w1, ..., w...). 108 ,w 109 ),in If 0 ≤ j < 110, then the codeword interleaving sequence C′ represents (w0, w1, ..., w 118 ,w 119 (v0, v1, ..., v6, v7). Where δ and Both are integer multiples of 10, and δ and All are greater than 0 and less than 120.

[0322] Then, a second interleaving and DP-16QAM symbol mapping are performed on the m=8 or m=16 second data streams. Specifically, one codeword interleaving sequence C′ is obtained from each second data stream, totaling m×128 bits, and used... Let C' represent the j-th (0≤j≤127) bit in the codeword interleaving sequence C' obtained from the second data stream i (0≤i≤m-1). For convenience, this m interleaving sequence C' is called the first bit set. Performing a second interleaving on the first bit set yields m×128 consecutive bits in the data stream, which is represented as the second bit set. Denotes the (8i+j)th bit of the second bit set, where 0≤j≤7. Therefore, a specific embodiment of the second interleaving is:

[0323] From the second data stream The 2nd (i%64)+i%2th bit in the codeword interleaving sequence.

[0324] From the second data stream The 2nd × (i%64) + (i+1)%2th bit in the codeword interleaving sequence.

[0325] From the second data stream The 2nd (i%64)+i%2th bit in the codeword interleaving sequence.

[0326] From the second data stream The 2nd × (i%64) + (i+1)%2th bit in the codeword interleaving sequence.

[0327] From the second data stream The 2nd (i%64)+i%2th bit in the codeword interleaving sequence.

[0328] From the second data stream The 2nd × (i%64) + (i+1)%2th bit in the codeword interleaving sequence.

[0329] From the second data stream The 2nd (i%64)+i%2th bit in the codeword interleaving sequence.

[0330] From the second data stream The 2nd × (i%64) + (i+1)%2th bit in the codeword interleaving sequence.

[0331] 8 bits Mapped to a DP-16QAM symbol S i The method is: Mapped to s i The I-path component in the X-polarization direction; Mapped to s i The Q-path component in the X-polarization direction; Mapped to s i The I-path component in the Y-polarization direction; Mapped to s i The Q-path component in the Y-polarization direction.

[0332] For each component, its bit-to-symbol magnitude mapping is (0,0)→-3, (0,1)→-1, (1,1)→+1, (1,0)→+3. After the second interleaving and symbol mapping, each inner codeword can be uniformly mapped to each constellation point of the DP-16QAM symbol, and errors in each DP-16QAM symbol can be uniformly mapped to each inner codeword, improving the performance of concatenated coding.

[0333] Finally, the 6144 DP-16QAM symbols obtained from the second interleaving and mapping process are processed 48 / (m / 8) times consecutively. A pilot symbol is inserted every 65 DP-16QAM symbols, resulting in a DSP frame as shown in Figure 18. This frame contains 96 subframes, each with 65 DP-16QAM symbols. The first symbol in each subframe is the inserted pilot symbol, and the remaining 64 symbols are the DP-16QAM symbols obtained by mapping the second bit set. The inserted pilot symbol is one of 3+3j, 3-3j, -3+3j, or -3-3j, where j is the imaginary unit of the complex number.

[0334] Example 9: This example 9 provides a specific scheme for the four first data streams when the transmitting device 01 transmits 1.6T service and the internal code encoding adopts BCH(126,110).

[0335] In this embodiment, four first data streams are obtained from the 1.6T 4:4PMA shown in Figure 8(e), the 1.6T 8:4PMA shown in Figure 8(f), or the 1.6T 16:4PMA shown in Figure 8(g). Then, each first data stream is convolutionally interleaved. When Q≥46, A′ in the data stream output by the convolutional interleaver is... i (3t), A′ i (3t+1), A′ i (3t+2) A total of 12 consecutive RS symbols come from 12 different RS codewords. To reduce the difficulty of high-speed implementation of the convolutional interleaver, Q is set to a multiple of 2, 4, or 8, such as Q = 46 or 48.

[0336] Then, each convolutionally interleaved data stream is first encoded using internal codes and then subjected to a first interleaving to obtain four second data streams. Alternatively, each convolutionally interleaved data stream is first interleaved and then encoded using internal codes to obtain four second data streams.

[0337] The first interleaving process for data stream i involves performing a first interleaving process on each BCH(126,110) codeword C in data stream i to obtain a codeword interleaving sequence C′. Specifically, this involves interleaving the 110 information bits (u0, u1, ..., u) of each BCH(126,110) codeword C in data stream i. 108 ,u 109 Perform a right circular shift. Each bit yields a sequence W consisting of 110 bits, denoted as (w0, w1, ..., w...). 108 ,w 109 ),in, If 0 ≤ i < 4, 0 ≤ j < 110, then the 126 bits of the codeword interleaved sequence C′ are represented as (w0, w1, ..., w 108 ,w 109 ,v0,v1,…,v 14 ,v 15 ). Where δ and Both are integer multiples of 10, and δ and Both are greater than 10 and less than 110. To ensure the concatenated code after the first interleaving can better resist bursts, δ and The possible values ​​are 20, 30, 40, 70, and 80. The following example, using a rightward loop, shows the specific cyclic shifts corresponding to the first interleaving 0 to the first interleaving 3. The values ​​of are shown in Table 3.

[0338] Table 3

[0339] Example 10: Based on Example 9, consider a specific scheme where the internal code encoding uses BCH(176,160) encoding and corresponds to 4 first data streams. In this example, the convolutional interleaver uses r=4 and d=40. When Q≥35, the 16 consecutive RS symbols in the data stream output by the convolutional interleaver come from 16 different RS codewords. To reduce the difficulty of high-speed implementation of the convolutional interleaver, Q is set to a multiple of 2, 4, or 8, such as Q=36 or 40. Then, each convolutionally interleaved data stream is first encoded using internal code and then first interleaved to obtain 4 second data streams. Alternatively, each convolutionally interleaved data stream is first interleaved and then encoded using internal code to obtain 4 second data streams.

[0340] Example 11: Based on Example 10, consider a specific scheme using BCH(176,160) encoding for the internal code, corresponding to 8 first data streams. In this example, the convolutional interleaver uses r=4 and d=40. When Q≥18, the 16 consecutive RS symbols in the data stream output by the convolutional interleaver come from 16 different RS codewords. To reduce the difficulty of high-speed implementation of the convolutional interleaver, Q is set to a multiple of 2, 4, or 8, such as Q=18, 20, or 24. Then, each convolutionally interleaved data stream is first encoded using the internal code and then subjected to the first interleaving to obtain 8 second data streams. Alternatively, each convolutionally interleaved data stream is first subjected to the first interleaving and then encoded using the internal code to obtain 8 second data streams.

[0341] Example 12: Based on Example 10, consider a specific scheme using BCH(176,160) encoding for the internal code, corresponding to 16 first data streams. In this example, the convolutional interleaver uses r=4 and d=40. When Q≥9, the 16 consecutive RS symbols in the data stream output by the convolutional interleaver come from 16 different RS codewords. To reduce the difficulty of high-speed implementation of the convolutional interleaver, Q is set to a multiple of 2, 4, or 8, such as Q=10, 12, or 16. Then, each convolutionally interleaved data stream is first encoded using the internal code and then subjected to the first interleaving to obtain 16 second data streams. Alternatively, each convolutionally interleaved data stream is first subjected to the first interleaving and then encoded using the internal code to obtain 16 second data streams.

[0342] Figure 21 is a schematic diagram of a data processing device according to an embodiment of this application. As shown in Figure 21, the data processing device includes an acquisition unit 201 and a processing unit 202. The acquisition unit 201 is used to execute the operation of step 101 in the above embodiment, and the processing unit 202 is used to execute the operations of steps 102 and 103 in the above embodiment. It should be understood that the data processing device provided in this application can also be implemented in other ways. For example, the unit division in the above device is only a logical functional division, and there may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system. In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or they can be independent physical units, or two or more functional units can be integrated into one processing unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0343] Figure 22 is a schematic diagram of an optical module structure in an embodiment of this application. As shown in Figure 22, the optical module includes a processor 301 and an interface 302. The processor 301 is used to execute the operations of steps 102 and 103 in the above embodiments. In one possible implementation, the processor 301 includes the processing unit 202 shown in Figure 21. The interface 302 can be a transceiver or an input / output interface. The interface 302 is used to receive signals from other devices and transmit them to the processor 301 or to send signals from the processor 301 to other devices. As an example, after performing the first data processing and the second data processing described above, the processor 301 obtains a first dual-polarization symbol stream and sends the first dual-polarization symbol stream through the interface 302. In this example, the interface 202 can specifically refer to an electrical interface. As another example, after performing the first data processing and the second data processing, the processor 301 obtains a first dual-polarization symbol stream. The modulator in the optical module performs signal processing such as electro-optic conversion based on the first dual-polarization symbol stream to obtain an optical signal, and then sends the optical signal through the interface 302. In this example, the interface 302 can specifically refer to an optical interface. Optionally, the optical module may also include a memory 303, wherein the memory 303 is used to store program instructions and data.

[0344] Typically, an optical module consists of optoelectronic devices, a processor, and an interface. The optoelectronic devices include transmitting and receiving devices. The transmitting end of the optical module converts electrical signals into optical signals and transmits them through optical fibers. The receiving end of the optical module receives the optical signals and converts them back into electrical signals.

[0345] It should be noted that the types of optical modules in this application embodiment include, but are not limited to, normal optical modules, near package optics (NPO) modules, and co-packaged optics (CPO) modules. Normal optical modules can perform functions including, but not limited to, digital signal processing (DSP) and clock data recovery (CDR). For example, a normal optical module converts analog signals to digital signals, performs DSP on the digital signals, and then converts them back to analog signals before sending them to the host device. Because DSP requires retiming, a normal optical module can also be called a retimed module. Normal optical modules are connected to the host device via an attachment unit interface (AUI). NPO and CPO modules do not have pluggable physical packaging and are closer to the host device. NPO and CPO modules can also be called optical engines. NPO or CPO technology is a technology that "packages" the host device (or host chip) and the optical engine. When NPO technology is used to encapsulate the host-side device and the optical engine, the optical engine can be called an NPO module. When CPO technology is used to encapsulate the host-side device and the optical engine, the optical engine can be called a CPO module.

[0346] Figure 23 is a schematic diagram of a transmitting device in an embodiment of this application. As shown in Figure 23, the transmitting device includes a host-side device 401 and an optical module 402. The host-side device 401 is used to send data to the optical module 402, and the optical module 402 generates an optical signal based on the data sent by the host-side device 401 and transmits the optical signal through a channel. For example, the host-side device may specifically be a switch, router, or server. The transmitting device can be a communication device including the host-side device 401 and the optical module 402. It should also be understood that the transmitting device in the embodiments of this application is named based on the data flow direction and does not limit the function of the device. For example, the transmitting device may also have a receiving function.

[0347] This application also provides an Optical Transport Network (OTN) device, which includes line-side equipment and client-side equipment. The client-side equipment may also be referred to as a tributary-side equipment in some scenarios. The line-side equipment includes a processor and an interface. The processor is used to execute the data processing methods described in the above embodiments. The interface can be a transceiver or an input / output interface, used to receive signals from other devices outside the line-side equipment and transmit them to the processor, or to send signals from the processor to other devices outside the line-side equipment.

[0348] This application also provides a chip. The chip integrates circuitry for implementing the functions of the aforementioned processor and one or more interfaces. As an example, the chip integrates a memory. As another example, when the chip does not integrate a memory, it can be connected to an external memory via the interface. The chip can perform the method steps of any one or more of the foregoing embodiments. Alternatively, the chip can implement the actions performed by the data processing device in the foregoing embodiments based on program code stored in the memory.

[0349] As an example, the chip in the embodiments of this application can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. A general-purpose processor can be a microprocessor, any conventional processor, or a processing circuit that implements a specific function.

[0350] This application also provides a computer-readable storage medium, including a program or instructions that, when run on a computer, cause the method performed as described in the above method embodiments to be implemented.

[0351] It should be understood that the processor mentioned in the embodiments of this application can be implemented in hardware or software. When implemented in hardware, the processor can be a logic circuit, integrated circuit, etc. When implemented in software, the processor can be a general-purpose processor that reads software code stored in memory. The memory can exist independently and be connected to the processor, or the memory can be integrated with the processor.

[0352] As an example, the processor in the embodiments of this application can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. A general-purpose processor can be a microprocessor, any conventional processor, or a processing circuit that implements a specific function.

[0353] In embodiments of this application, the memory may be random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, portable hard disks, CD-ROMs, or any other form of storage medium known in the art. An exemplary storage medium is coupled to a processor, enabling the processor to read information from and write information to the storage medium. Of course, the storage medium may also be a component of the processor. The processor and storage medium may reside in an ASIC. Additionally, the ASIC may reside in a network device or a terminal device. Alternatively, the processor and storage medium may exist as discrete components in the network device or terminal device.

[0354] In the above embodiments, it can be implemented entirely or partially by software, hardware, firmware, or any combination thereof.

[0355] When implemented in hardware, the data processing method provided in this application embodiment may be implemented without reading software code or instructions. For example, it may be implemented by CPU, DSP, ASIC, FPGA, other programmable logic devices, transistor logic devices, hardware components, or any combination thereof.

[0356] When implemented using software, it can be implemented entirely or partially in the form of a computer program product. A computer program product includes one or more computer programs or instructions. When the computer program or instructions are loaded and executed on a computer, all or part of the processes or functions of the embodiments of this application are performed. The computer can be a general-purpose computer, a special-purpose computer, a computer network, a network device, a terminal device, or other programmable device. The computer program or instructions can be stored in or transmitted through a computer-readable storage medium. The computer-readable storage medium can be any available medium that a computer can access, or a data storage device such as a server that integrates one or more available media. The available medium can be a magnetic medium, such as a floppy disk, hard disk, or magnetic tape; it can also be an optical medium, such as a Digital Versatile Disc (DVD); or it can be a semiconductor medium, such as a solid-state disk (SSD).

[0357] Finally, it should be noted that the above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A data processing method, characterized in that, include: Obtain p first data streams encoded by Reed-Solomon RS, where p is a positive integer multiple of 4 and p is a power of 2. Each of the first data streams contains a... RS The adjacent RS symbols are respectively from a RS 1 RS codeword, where a RS An integer power greater than or equal to 4 and equal to 2; The p first data streams are subjected to first data processing including forward error correction (FEC) coding and first interleaving to obtain m second data streams, where m is an integer greater than or equal to p; The m second data streams are subjected to a second data processing process, including second interleaving, dual-polarization hexadecimal quadrature amplitude modulation (DP-16QAM) symbol mapping, and framing, to obtain a first dual-polarization symbol stream.

2. The method according to claim 1, characterized in that, If m > p, perform first data processing, including FEC encoding and first interleaving, on the p first data streams to obtain m second data streams, including: Each of the p first data streams is distributed to obtain m / p first sub-data streams, resulting in m first sub-data streams. The m first sub-data streams are then subjected to FEC encoding and first interleaving to obtain the m second data streams.

3. The method according to claim 2, characterized in that, Each first sub-data stream obtained by distributing from a first data stream includes K consecutive bits from the first data stream, where K is a positive integer and K is the number of information bits involved in the FEC encoding; Alternatively, each of the first sub-data streams obtained by distributing from a first data stream comprises K0 consecutive bits from the first data stream, where K0 is an integer multiple of 40.

4. The method according to claim 2 or 3, characterized in that, The number of information bits involved in the FEC encoding is K, and each first sub-data stream obtained by distributing it from one first data stream includes K0 consecutive bits in the first data stream, where K = 110 and K0 = 120.

5. The method according to any one of claims 2 to 4, characterized in that, Performing first data processing, including FEC encoding and first interleaving, on the p first data streams to obtain m second data streams includes: The p first data streams are convolutionally interleaved. Each of the p first data streams after convolutional interleaving is distributed to obtain m / p first sub-data streams, resulting in m first sub-data streams. The m first sub-data streams are then subjected to FEC encoding and first interleaving to obtain the m second data streams.

6. The method according to claim 1, characterized in that, Performing first data processing, including FEC encoding and first interleaving, on the p first data streams to obtain m second data streams includes: The p first data streams are convolutionally interleaved, and the p first data streams after convolutional interleaving are FEC encoded and firstly interleaved to obtain the m second data streams.

7. The method according to claim 5 or 6, characterized in that, Convolutional interleaving of one of the first data streams includes: Bits from the first data stream are delayed using r delay lines, where r is an integer greater than 1. Each delay line has a different number of storage units, with the delay line having the fewest storage units (0 units). The difference in the number of storage units between any two adjacent delay lines is Q. Each storage unit stores d bits. The input bits are sequentially input to the r delay lines according to their numbers, with d bits being input to each delay line and d bits being output from each delay line at a time. Q and d are both integers greater than or equal to 1.

8. The method according to claim 7, characterized in that, The delay line with the largest sequence number among the r delay lines includes 0 memory units, or the delay line with the smallest sequence number among the r delay lines includes 0 memory units.

9. The method according to claim 7 or 8, characterized in that, p=8, r=3, d=40, Q≥23; Alternatively, the delay line with the largest sequence number among the r delay lines includes 0 memory cells, p = 16, r = 3, d = 40, Q ≥ 11; Alternatively, the delay line with the smallest sequence number among the r delay lines includes 0 memory cells, p = 16, r = 3, d = 40, Q ≥ 12; Alternatively, the delay line with the largest sequence number among the r delay lines includes 0 memory cells, p=4, r=3, d=40, Q≥45; Alternatively, the delay line with the smallest sequence number among the r delay lines includes 0 memory cells, p=4, r=3, d=40, Q≥46; Alternatively, the delay line with the largest sequence number among the r delay lines includes 0 memory cells, p=4, r=4, d=40, Q≥34; Alternatively, the delay line with the smallest sequence number among the r delay lines includes 0 memory cells, p=4, r=4, d=40, Q≥35; Alternatively, the delay line with the largest sequence number among the r delay lines includes 0 memory cells, p = 8, r = 4, d = 40, Q ≥ 17; Alternatively, the delay line with the smallest sequence number among the r delay lines includes 0 memory cells, p = 8, r = 4, d = 40, Q ≥ 18; Alternatively, p = 16, r = 4, d = 40, Q ≥ 9.

10. The method according to any one of claims 1 to 9, characterized in that, The number of information bits involved in the FEC encoding is K. Each codeword after FEC encoding includes N bits. The NK parity bits in the codeword are obtained by FEC encoding the K information bits. The first interleaving is used to cyclically shift each K information bits in the first data stream.

11. The method according to claim 10, characterized in that, p=4, the first interleaving is used to cyclically shift every K information bits in the first data stream i. 4 bits, 0≤i<4 Satisfy one of the following: Alternatively, p=8, where the first interleaving is used to cyclically shift every K information bits in the first data stream i. 8 bits, 0≤i<8 Satisfy one of the following: Alternatively, p=16, where the first interleaving is used to cyclically shift every K information bits in the first data stream i. 16 bits, 0≤i<16 Satisfy one of the following:

12. The method according to any one of claims 1 to 11, characterized in that, The first data processing, which includes FEC encoding and first interleaving, of the first data stream includes: The first data stream is subjected to a first interleaving, and the first data stream after the first interleaving is subjected to FEC encoding; or, The first data stream is FEC encoded, and the first data stream after FEC encoding is interleaved for the first time. or, The K information bits in the first data stream are FEC encoded to obtain NK parity bits, and the K information bits are first interleaved to obtain N bits including the NK parity bits and the K information bits after the first interleaving, where K is a positive integer and N > K.

13. The method according to any one of claims 1 to 12, characterized in that, The second interleaving and DP-16QAM symbol mapping for the m second data streams includes: Obtain N bits from each of the second data streams to obtain m×N bits, wherein the N bits include K information bits and NK check bits in the codeword encoded by the FEC; Perform a second interleaving on the m×N bits; The m×N bits after the second interleaving are mapped to DP-16QAM symbols to obtain N×m / 8 DP-16QAM symbols.

14. The method according to claim 13, characterized in that, p = 8, m = 8 This represents the j0th bit out of the N bits obtained from the i0th second data stream, where 0 ≤ i0 ≤ 7 and 0 ≤ j0 ≤ N-1, and is mapped to the 8 bits of the i-th DP-16QAM symbol as follows: From 15. The method according to claim 14, characterized in that, The i-th bit from the N bits of the (i+4)%8th second data stream; The i-th bit from the N bits of the (i+5)%8th second data stream; The i-th bit from the N bits of the (i+6)%8th second data stream; The i-th bit from the N bits of the (i+7)%8th second data stream; The i-th bit from the N bits of the (i)%8th second data stream; The i-th bit from the N bits of the (i+1)%8th second data stream; The i-th bit from the N bits of the (i+2)%8th second data stream; The i-th bit from the N bits of the (i+3)%8th second data stream.

16. The method according to any one of claims 1 to 15, characterized in that, Performing second data processing on the m second data streams, including second interleaving, DP-16QAM symbol mapping, and framing, to obtain one first dual-polarization symbol stream includes one of the following methods: Perform second interleaving and DP-16QAM symbol mapping on the m second data streams to obtain a second dual-polarization symbol stream, and insert the target symbol sequence into the second dual-polarization symbol stream to obtain the first dual-polarization symbol stream; or, The m second data streams are interleaved to obtain one third data stream. A target bit sequence is inserted into the third data stream to obtain a fourth data stream. The fourth data stream is then subjected to DP-16QAM symbol mapping to obtain the first dual-polarization symbol stream. The target bit sequence is then subjected to DP-16QAM symbol mapping to obtain a target symbol sequence. or, The m second data streams are interleaved to obtain two third data streams. The target bit sequence is inserted into the two third data streams to obtain two fourth bit streams. The two fourth bit streams are then subjected to DP-16QAM symbol mapping to obtain the first dual-polarization symbol stream. The target bit sequence is then subjected to DP-16QAM symbol mapping to obtain the target symbol sequence. or, The m second data streams are interleaved a second time to obtain four third data streams. Two of the four third data streams are inserted with the I component of the target bit sequence, and the other two are inserted with the Q component of the target bit sequence to obtain four fourth bit streams. The four fourth bit streams are then subjected to DP-16QAM symbol mapping to obtain the first dual-polarization symbol stream. The I component of the target bit sequence is mapped by DP-16QAM to obtain the I component of the target symbol sequence, and the Q component of the target bit sequence is mapped by DP-16QAM to obtain the Q component of the target symbol sequence.

17. The method according to claim 16, characterized in that, The first dual-polarization symbol stream includes multiple dual-polarization symbol sequences, and a fixed position in each dual-polarization symbol sequence includes the target symbol sequence. The target symbol sequence includes at least one of the following: frame synchronization symbol sequence, training symbol sequence, reserved symbol sequence, and pilot symbol sequence.

18. The method according to any one of claims 1 to 17, characterized in that, Each codeword encoded by the FEC consists of K information bits and NK check bits, for a total of N bits; N = 128, K = 120, or N = 126, K = 110, or N = 176, K = 160.

19. The method according to any one of claims 1 to 18, characterized in that, m = 4, 8, 16 or 32.

20. The method according to any one of claims 1 to 19, characterized in that, In each of the first data streams, every four adjacent RS symbols come from four RS codewords.

21. The method according to any one of claims 1 to 20, characterized in that, The p first data streams are obtained by processing 16 fifth data streams through a symbol-based physical media adaptation layer (PMA). The 16 fifth data streams are obtained by processing the service data to be sent through a physical coding sublayer (PCS) including RS coding.

22. The method according to claim 21, characterized in that, The p first data streams are obtained by processing t signals through t:p PMA, and the t signals are obtained by processing the 16 fifth data streams through 16:t PMA, where t is a positive integer multiple of 4.

23. The method according to claim 21, characterized in that, The p first data streams are obtained by processing the 16 fifth data streams through 16:p PMA.

24. The method according to any one of claims 1 to 20, characterized in that, The p first data streams are obtained by processing t signals through t:p PMA based on symbol multiplexing.

25. The method according to claim 22 or 24, characterized in that, t = 8, p = 8; or t = 16, p = 8; or t = 4, p = 8; Alternatively, t = 8, p = 16; Alternatively, t = 16, p = 16; Alternatively, t = 4, p = 16; Alternatively, t = 4, p = 4; Alternatively, t = 8, p = 4.

26. The method according to any one of claims 1 to 20, characterized in that, The p first data streams are obtained by processing the service data to be sent through a PCS including RS encoding.

27. The method according to any one of claims 1 to 26, characterized in that, The data processing method is applicable to scenarios including Ethernet, optical transport networks, and space optical communication.

28. A data processing apparatus, characterized in that, The data processing device includes: an acquisition unit and a processing unit; The acquisition unit is used to: acquire p first data streams encoded by Reed-Solomon RS, where p is a positive integer multiple of 4 and p is an integer power of 2, and each a in each first data stream... RS The adjacent RS symbols are respectively from a RS 1 RS codeword, where a RS An integer power greater than or equal to 4 and equal to 2; The processing unit is used to: perform first data processing, including forward error correction (FEC) coding and first interleaving, on the p first data streams to obtain m second data streams, where m is an integer greater than or equal to p; The m second data streams are subjected to a second data processing process, including second interleaving, dual-polarization hexadecimal quadrature amplitude modulation (DP-16QAM) symbol mapping, and framing, to obtain a first dual-polarization symbol stream.

29. A chip, characterized in that, The chip is used to perform the method as described in any one of claims 1 to 27.

30. An optical module, characterized in that, The optical module includes a processor and an interface, the processor being used to perform the method as described in any one of claims 1 to 27 and to transmit and receive signals through the interface.

31. A transmitting device, characterized in that, The transmitting device includes a host-side device and an optical module as described in claim 30, wherein the optical module is used to generate an optical signal based on data from the host-side device and to transmit the optical signal.

32. A communication system, characterized in that, include: The transmitting device and the receiving device as described in claim 31, wherein the transmitting device is configured to transmit a signal to the receiving device.

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