Configurable gate driver assembly

Abstract

A configurable gate driver assembly (2) is disclosed. The configurable gate driver assembly comprises: an interface (5) for receiving a removably insertable power electronic assembly (6); at least one gate driver (4) for driving at least one power transistor (8) in the removably insertable power electronic assembly; and a microcontroller (3) arranged to control operation of each gate driver, the microcontroller being configurable by an external computer system (11) whereby a testing or operating mode is selectable from a plurality of different testing or operating modes, each testing or operating mode corresponding to a use case or application of the power electronic assembly.

Description

[0001] Configurable gate driver assembly

[0002] Field

[0003] The present invention relates to a configurable gate driver assembly.

[0004] Background

[0005] Gate drivers are used to control the operation of power semiconductor devices, such as MOSFETs and IGBTs, by providing the signals required to turn them on and off. Using gate drivers to effectively control power semiconductor devices, for example with low electro-magnetic interference (EMI) and high switching efficiency, can ensure that satisfactory performance is achieved by the systems in which they are employed.

[0006] Gate drivers are used in a diverse range of use cases and applications, for example, in the testing of power semiconductor devices and in power conversion systems such as DC / AC converters, AC / DC converters, and DC / DC converters. The way in which power semiconductor devices are best controlled by gate drivers is dependent on the use case or application.

[0007] H. Al Fahel: "Evaluate Power Device Efficiency with Double-Pulse Testing Using an AFG" (2019) (hereinafter referred to as "Fahel") describes a system for double pulse testing.

[0008] "AN1968: Unclamped Inductive Switching (UIS) Test and Rating Methodology" (2015) (hereinafter referred to as "AN1968"') describes circuits for unclamped inductive switching testing.

[0009] S. Diao et al. : "Determination of failure degree of 1.2 kV SiC MOSFETs after short- circuit test using an improved test setup", Nanotechnology and Precision Engineering, volume 3, issue 4, pages 235-240 (2020) (hereinafter referred to as "Diao") describes a test bench for short circuit testing.

[0010] Z. Ye and S. Rajagopalan: "Bidirectional DC / DC converter topology comparison and design", Power Supply Design Seminar 2016 / 17 (2016) (hereinafter referred to as "Ye") describes bidirectional buck-boost converter circuits.

[0011] Adapting off-the-shelf gate drivers from various suppliers for the specific requirements of each application can, however, be a complex and time-consuming process and require rebuilding or altering the design of hardware. US 2006 / 120001 Al describes a power converter which can be adapted for multiple power conversion applications by making changes to its hardware.

[0012] Summary

[0013] According to a first aspect of the present invention there is provided a configurable gate driver assembly. The configurable gate driver assembly comprises an interface for receiving a removably insertable power electronic assembly, at least one gate driver for driving at least one power transistor in the removably insertable power electronic assembly, and a microcontroller arranged to control operation of each gate driver. The microcontroller is configurable by an external computer system whereby a testing or operating mode is selectable from a plurality of different testing or operating modes, each testing or operating mode corresponding to a use case or application of the power electronic assembly.

[0014] Thus, the configurable gate driver assembly can be easily adapted to suit the specific requirements of a variety of use cases or applications, making what can otherwise be a complex and time-consuming process and require rebuilding hardware and / or altering the design of the gate driver more convenient and time efficient. In particular, the gate driver assembly being configurable by the computer system can improve ease of use and provide time savings.

[0015] The configurable gate driver assembly may comprise a configurable gate driver module. The power electronic assembly may comprise a power electronic module.

[0016] The configurable gate driver assembly may be for receiving the power electronic assembly directly. The configurable gate driver assembly may be for receiving the power electronic assembly directly indirectly, via an adapter such as an adapter board.

[0017] The at least one gate driver may comprise a single-channel gate driver for driving a power transistor in the power electronic assembly. The single-channel gate driver may be a high side gate driver or a low side gate driver. The power transistor may be a high side power transistor or a low side power transistor. The at least one gate driver may consist of the first single-channel gate driver. The configurable gate driver assembly may comprise only one gate driver: the single-channel gate driver.

[0018] The at least one gate driver may comprise a first single-channel gate driver for driving a first power transistor of the power electronic assembly and a second single-channel gate driver for driving a second power transistor of the power electronic assembly.

[0019] The first single-channel gate driver may be a high-side gate driver. The second singlechannel gate driver may be a low-side gate driver. The at least one gate driver may consist of the first single-channel gate driver and the second single-channel gate driver.

[0020] The configurable gate driver assembly may comprise only two gate drivers. The only two gate drivers may be the first single-channel gate driver and the second singlechannel gate driver.

[0021] The at least one gate driver may comprise a dual-channel gate driver for driving a first power transistor of the power electronic assembly and a second power transistor of the power electronic assembly.

[0022] The at least one gate driver may consist of the dual-channel gate driver.

[0023] The configurable gate driver assembly may comprise only one gate driver, the only one gate driver being the dual-channel gate driver.

[0024] The first power transistor may be a high side power transistor and the second power transistor may be a low side power transistor.

[0025] The configurable gate driver assembly may be a configurable gate driver module. The power electronic assembly may be a power electronic module.

[0026] The at least one gate driver may be capable of outputting at least one drive signal having a voltage in the range VL to VH and / or a current in the range II to IH, where VL and VH are application dependant voltages and II and IH are application dependant currents.

[0027] The at least one gate driver may be capable of outputting at least one drive signal having a voltage in the range 14 to 21 V and / or a current in the range 10 to 30 A to the at least one power transistor.

[0028] The at least one drive signal may have a voltage that is capable of being positive or negative. This can help provide a route to speed up turn-off.

[0029] In the case that the at least one gate driver is configured to output at least two drive signals, each drive signal may be output to a respective power transistor of the power electronic assembly. In the case that the at least one gate driver comprises at least two gate drivers, at least one of the at least two gate drivers may be configured to source and sink current. In the case that the at least one gate driver comprises at least two gate drivers, each gate driver may be configured to source and sink current.

[0030] Each gate driver may be a smart gate driver.

[0031] Each gate driver may have a set of registers for storing values of one or more parameters of a testing or operating mode according to which said gate driver is to operate.

[0032] Values stored in the set of registers of each gate driver may be configurable by the microcontroller and / or an external controller. The set of registers of each gate driver may be volatile memory.

[0033] One or more of the values stored in the set of registers of each gate driver may be indicative of whether the gate driver to which it belongs is to be controlled by the microcontroller or by the external controller.

[0034] The microcontroller may have a set of registers for storing values of parameters of one or more testing or operating modes. The set of registers of the microcontroller may be non-volatile memory. The values stored in the set of registers of the microcontroller may be configurable by the computer system.

[0035] The values stored in the set of registers of the microcontroller may be usable by the microcontroller to set a testing or operating mode according to which the configurable gate driver assembly is to operate.

[0036] The values stored in the set of registers of the microcontroller may be usable to set the values stored in the set of registers of each gate driver.

[0037] The configurable gate driver assembly may be arranged to be configured based on an instruction received from a software application installed on the computer system.

[0038] The configurable gate driver assembly may be arranged to be configured based on an instruction received from a software application installed on a server connected to the computer system. In other words, the configurable gate driver assembly may be configurable using client software and / or server software.

[0039] The software application can provide a user with easy access to the main gate driver functions of each of the gate drivers. The flexibility of this approach can mean that the configurable gate driver assembly is not required to use a particular type of gate driver. Thus, gate driver(s) having different register configurations and addresses (for example, off-the-shelf gate drivers from different manufacturers) may be used as the at least one gate driver and controlled using the software application without there being any need to use different hardware configurations of the configurable gate driver assembly for different types of gate driver(s).

[0040] The microcontroller may be configured to provide a readout to the computer system. Thus, the software may be used for both control and analysis.

[0041] The at least one power transistor may comprise a metal-oxide-semiconductor fieldeffect transistor (MOSFET). The at least one power transistor may comprise an insulated-gate bipolar transistor (IGBT). The at least one power transistor may comprise a bipolar junction transistor (BJT). The at least one power transistor may comprise a static induction transistor (SIT).

[0042] The at least one power transistor may be implemented in silicon carbide (SiC). The at least one power transistor may be implemented in gallium nitride (GaN).

[0043] According to a second aspect of the present invention there is provided a first system. The first system comprises a computer system having a user interface and the configurable gate driver assembly of the first aspect. The computer system is operable to receive an instruction from a user, via the user interface, to select a testing or operating mode selectable from a plurality of different testing or operating modes corresponding to different use case or application of the power electronic assembly and to set parameters for the testing or operating mode.

[0044] According to a third aspect of the present invention there is provided a second system. The second system comprises the configurable gate driver assembly of the first aspect or the first system of the second aspect. The second system further comprises the removably insertable power electronic assembly. Each testing or operating mode may correspond to a use case or application of the configurable gate driver assembly with the power electronic assembly.

[0045] The second system of claim 16 may be operable in a testing mode for one or more of double pulse testing, unclamped inductive switching testing, and short circuit testing.

[0046] The second system of claim 16 may be operable in an operating mode for power factor correction.

[0047] In the case that the second system is operable in an operating mode for power factor correction, the second system may be included in an on-board charger for a battery of a vehicle.

[0048] The second system may be operable in an operating mode for a bidirectional buck boost converter.

[0049] In the case that the power electronic assembly comprises a bidirectional buck boost converter comprising two half bridges, the second system may comprise two configurable gate driver assemblies and the removably insertable power electronic assembly, each configurable gate driver assembly usable to control a respective transistor or pair of transistors in the power electronic assembly.

[0050] The second system may be operable in an operating mode for a three-phase inverter.

[0051] In the case that the power electronic assembly comprises the three-phase inverter comprising three half-bridges, the second system may comprise three configurable gate driver assemblies and the removably insertable power electronic assembly, each configurable gate driver assembly usable to control a respective transistor or pair of transistors in the power electronic assembly.

[0052] The second system may be operable in an operating mode for a dual active bridge.

[0053] In the case that the power electronic assembly comprises the dual active bridge comprising two full bridges, the second system may comprise four configurable gate driver assemblies and the removably insertable power electronic assembly, each configurable gate driver assembly usable to control a respective transistor or pair of transistors in the power electronic assembly. The second system may be operable in an operating mode for a multi-active bridge.

[0054] The second system may comprise a first configurable gate driver assembly having a first microcontroller configured to operate in slave mode and a second configurable gate driver assembly having a second microcontroller configured to operate in master mode and to control the first microcontroller.

[0055] The first microcontroller may be configured, in response to detecting a fault, to provide a fault signal to the second microcontroller.

[0056] The first microcontroller may be configured, in response to detecting a fault, to provide a fault signal to the second microcontroller for example via a GPIO pin.

[0057] The fault signal can, once provided to the second controller, be provided to the computer system. Once the fault signal is provided to the computer system, the software application may be configured to output a fault notification to a user for example via the user interface. The fault notification may take the form of a visual indicator being displayed or an audible alarm being emitted.

[0058] According to a fourth aspect of the present invention there is provided a method of operating a configurable gate driver. The configurable gate driver assembly comprises an interface for receiving a removably insertable power electronic assembly, at least one gate driver for driving at least one power transistor in the removably insertable power electronic assembly, and a microcontroller arranged to control operation of each gate driver. The microcontroller is configurable by an external computer system whereby a testing or operating mode is selectable from a plurality of different testing or operating modes, each testing or operating mode corresponding to a use case or application of the power electronic assembly. The method comprises one or more of the interface receiving the removably insertable power electronic assembly, the computer system configuring the microcontroller, the microcontroller controlling operation of each gate driver, and the at least one gate driver driving the at least one power transistor.

[0059] The method may comprise the interface receiving the removably insertable power electronic assembly, and the computer system configuring the microcontroller. The method may comprise the interface receiving the removably insertable power electronic assembly, the computer system configuring the microcontroller, the microcontroller controlling operation of each gate driver, and the at least one gate driver driving the at least one power transistor. The method may comprise the interface receiving the removably insertable power electronic assembly, the microcontroller controlling operation of each gate driver, and the at least one gate driver driving the at least one power transistor.

[0060] The method may comprise the computer system configuring the microcontroller, and the microcontroller controlling operation of each gate driver. The method may comprise the computer system configuring the microcontroller, and the at least one gate driver driving the at least one power transistor. The method may comprise the computer system configuring the microcontroller, the microcontroller controlling operation of each gate driver, and the at least one gate driver driving the at least one power transistor.

[0061] The method may comprise the microcontroller controlling operation of each gate driver, and the at least one gate driver driving the at least one power transistor.

[0062] According to a fifth aspect of the present invention there is provided a computer program which, when executed by at least one processor, causes the at least one processor to perform the method of the fourth aspect.

[0063] According to a sixth aspect of the present invention there is provided a computer program product comprising a computer-readable medium storing the computer program of the fifth aspect.

[0064] Brief Description of the Drawings

[0065] Certain embodiments of the present invention will now be described, by way of example, with reference to the accompanying drawings in which:

[0066] Figure 1 is a schematic block diagram of a system comprising a configurable gate driver assembly;

[0067] Figure 2 is a schematic block diagram of parts of the system shown in Figure 1, illustrating the interface and the connector;

[0068] Figure 3 is a more detailed schematic block diagram of the system shown in Figure 1;

[0069] Figure 4 is a schematic block diagram of a modified version of the system shown in

[0070] Figure 3;

[0071] Figure 5A is a top view of a configurable gate driver module;

[0072] Figure 5B is a bottom view of the configurable gate driver module shown in Figure 5A;

[0073] Figure 5C is a perspective view of the configurable gate driver module shown in Figure 5A;

[0074] Figures 6A-1 and 6A-2 are first screenshots of a user interface for controlling a configurable gate driver module;

[0075] Figure 6B is a second screenshot of the user interface shown in Figures 6A-1 and 6A- 2;

[0076] Figure 6C is a third screenshot of the user interface shown in Figure 6A-1 and 6A-2;

[0077] Figure 7A is a circuit schematic of a system for double pulse testing;

[0078] Figure 7B is a screenshot of a user interface for operating the system shown in Figure 7A;

[0079] Figure 8A is a circuit schematic of a system for unclamped inductive switching testing;

[0080] Figure 8B is a screenshot of a user interface for operating the system shown in Figure 8A;

[0081] Figure 9A is a circuit schematic of a system for short circuit testing;

[0082] Figure 9B is a screenshot of a user interface for operating the system shown in Figure 9A;

[0083] Figure 10A is a circuit schematic of a system for power factor correction;

[0084] Figure 10B is a schematic block diagram of an on-board charger system for a battery of a vehicle;

[0085] Figure 11 is a circuit schematic of a bidirectional buck-boost converter system;

[0086] Figure 12 is a circuit schematic of a single-phase inverter system;

[0087] Figure 13 is a circuit schematic of a three-phase inverter system;

[0088] Figure 14A is a circuit schematic of a dual-active bridge system;

[0089] Figure 14B is a schematic block diagram of the system shown in Figure 14A;

[0090] Figure 15 is a schematic block diagram of a multi-active bridge system; and

[0091] Figure 16 is a circuit schematic of a system for validating a shift in threshold voltage. Detailed Description of Certain Embodiments

[0092] In the following, like parts are denoted by like reference numerals.

[0093] Introduction

[0094] Herein, configurable gate driver assemblies are described. The hardware of these gate driver assemblies, which includes a microcontroller and at least one gate driver for controlling at least one power transistor in a separate power electronic assembly, can be easily adapted to suit the specific requirements of a variety of use cases or applications, making what can otherwise be a complex and time-consuming process requiring rebuilding the hardware and / or altering the design of the hardware more convenient and time efficient. In particular, the gate driver assemblies being configurable by an external computer system can improve ease of use and provide time savings.

[0095] Configurable gate driver assemblv / module 2

[0096] Referring to Figure 1, the electronic structure of a system 1 comprising a configurable gate driver assembly 2 (hereinafter referred to as the "driver assembly") is shown.

[0097] The driver assembly 2 includes a microcontroller 3 and at least one gate driver 4. The microcontroller 3 is connected to and controls operation of each gate driver 4.

[0098] The driver assembly 2 also includes an interface 5 to which a power electronic assembly 6 (hereinafter referred to as the "electronic assembly") is, using a connector 7, mechanically coupled. The interface 5 may be a socket and the connector 7 may be a plug. This need not be the case, however, and the interface 5 may be a plug and the connector 7 may be a socket. The interface 5 and the connector 7 can take any form suitable for mechanically coupling the electronic assembly 6 to the driver assembly 2.

[0099] The electronic assembly 6 also includes at least one power transistor 8. The driver assembly 2 is connected to and controls operation of the electronic assembly 6, in particular to each power transistor 8, by outputting at least one drive signal 9 from at least one output terminal 10 of the driver assembly 2. Each gate driver 4 provides its output to a respective output terminal 10 and, in turn, each output terminal 10 provides a drive signal 9 to a respective power transistor 8. Each output terminal 10 may be an output terminal of a gate driver 4, however this need not be the case and further circuitry (not shown) may be included between at least one gate driver 4 and its respective output terminal 10. This further circuitry may consist of a direct connection, for example taking the form of a wire or a PCB trace, or may comprise other electronic components for processing the output of a gate driver 4 to provide the drive signal 9 to an output terminal 10.

[0100] The driver assembly 2 is connected to and controlled by a computer system 11 which includes a user interface 12 and a software application 13. A user (not shown) can operate the user interface 12 to provide an instruction to the software application 13 to select a testing or operating mode corresponding to a particular use case or application of the electronic assembly 6 and to cause the computer system 11 to output a signal 14 to the driver assembly 2 to set the driver assembly 2 to operate with the electronic assembly 6 in that mode.

[0101] Referring also to Figure 2, the mechanical structure of the driver assembly 2 and electronic assembly 6 of the system 1 is shown. The connector 7 includes a portion 7a which is designed to be removably inserted into the interface 5.

[0102] Referring to Figure 3, a more detailed example of the system 1 is shown. The driver assembly 2 includes first 4, 4i and second 4, 42 gate drivers and the electronic assembly 6 includes first 8, 8i and second 8, 82 power transistors. Herein, in examples in which the driver assembly 2 includes two or more gate drivers 4 and / or the electronic module 6 includes two or more power transistors 8, the term module is used interchangeably with the term assembly.

[0103] The driver module 2 has first 10, 10i and second 10, IO2 output terminals from which first 9, 9i and second 9, 92 drive signals are respectively provided to the first 8, 81 and second 8, 82 power transistors. The first power transistor 8, 81 may be a high side power transistor and the second power transistor 8, 82 may be a low side power transistor. Likewise, the first gate driver 4, 4i may be a high side gate driver and the second gate driver 4, 42 may be a low side gate drive. This need not be the case, however, and the first gate driver 4, 4i and the second gate driver 4, 42 may be replaced with, for example, a dual-channel gate driver (not shown).

[0104] The microcontroller 3 has a set of registers 15 which store values of parameters of the mode according to which the driver module 2 is to operate with the electronic module 6. These values can written by the computer system 11 to configure the driver module 2, that is, to set a testing or operating mode according to which the driver module 2 is to operate. The registers 15 include non-volatile memory so values stored in the registers 15 can be retained when the driver module 2 is turned off. In this way, once initially configured by the computer system 11, the driver module 2 can be used without the computer system 11.

[0105] The first gate driver 4, 4i has a set of registers 16 and the second gate driver 4, 42 has a set of registers 17. The registers 16, 17 store values of one or more parameters of the mode according to which their respective gate driver 4, 4i, 42 is to operate based on. These values can be written by the microcontroller 3. Alternatively, or additionally, these values may be written by an external controller (not shown) connected to the driver module 2, that is, without the microcontroller 3. The registers 16, 17 are volatile memory, and one or more of the values stored in the registers 16, 17 may be indicative of whether the gate driver to which it belongs is configured to be controlled by the microcontroller 3 or by the external controller.

[0106] The computer system 11 can configure the driver module 2 by writing values to the registers 15 and the microcontroller 3 can configure the first 4, 4i and second 4, 42 gate drivers by writing values to the registers 16, 17. In this way, the system 1 can be set to operate in a particular testing or operating mode, with a particular set of parameters, each parameter having a respective value.

[0107] The signal 14 can be output from the computer system 11 to the microcontroller via a USB connection (not shown) connected to an electrical interface (not shown) of the driver module 2. The first 4, 4i and second 4, 42 gate drivers may each be connected to (not shown) and configurable by the microcontroller according to the serial peripheral interface (SPI) protocol.

[0108] In addition to being able to write values to the registers 16, 17, the microcontroller 3 may read the values stored in those registers and provide a readout of those values to the computer system 11, and thus in turn to the user, via the USB connection. Likewise, the microcontroller 3 can provide a readout of the values stored in the register 15 to the computer system 11. In this way, the computer system 11, particularly the software application 13, can be used both for controlling the driver module 2 and electronic module 6 and for analysis of the operation of the driver module 2 with the electronic module 6.

[0109] Referring to Figure 4, a system 20 is shown. The system 20 is a modified version of the system 1 which is different from the system 1 in that it includes a server 21 and a computer system 22 in place of the computer system 11. In the system 20, the software application 13 is installed on the server 21. Thus, the software application 13 can be cloud-based, and the computer system 22 connected to the server 21 on which the software application 13 is installed.

[0110] Referring to Figures 5A to 5C, top, bottom, and perspective views of a more detailed example of the driver module 2 are respectively shown.

[0111] The driver module 2 includes output test points 25 to facilitate connection to be made to a measurement probe for monitoring the drive signals 8 output by the gate drivers 4, 4i and 4, 42, and thus improve the ease with which a user can detect and resolve any faults. The driver module 2 also includes isolated power-good indicators 26 for indicating whether a power supply is being provided to the driver module 2.

[0112] An external SPI communication port 27 is provided on the driver module 2 to facilitate communication with an external controller (not shown) or other driver modules (not shown) according to the SPI protocol.

[0113] The driver module 2 also includes an integrated analog-to-digital converter to measure a DC link voltage 28 of a power module. The associated value is accessible through the microcontroller 3, stored in the registers 16, 17, and can be accessed using the computer system 11.

[0114] Hardware for NTC / Temp. reading access / conn 29 is included on the driver module 2 to allow for a determination of an overtemperature condition made by the driver module 2, for example by the microcontroller 3, to be communicated to the computer system 11. The associated value is accessible through the microcontroller 3, stored in the registers 16, 17, and can be accessed using the computer system 11.

[0115] The driver module 2 also includes fault / power indicators 30 to indicate to the user whether a determination of a presence of a fault such as a short circuit has been made by the driver module 2, optionally by a watchdog timer (not shown), and / or whether a determination that a suitable power supply is being provided to the driver module 2 has been made by the driver module 2.

[0116] A pulse-width modulated (PWM) input 31 is provided on the driver module 2 to allow an external electrical PWM signal, for example from an external controller, to be provided to one or more of the gate drivers 4, subject to hardware 35 for PWM input selection being configured to permit the external electrical PWM signal to be provided to one or more of the gate drivers 4.. The driver module 2 also includes an external power input 32 to receive a power supply for the driver module 2, and serial communication indicators 33 to indicate whether the microcontroller 3 is transmitting and receiving information to and from the computer system 11 according to the UART (Tx, Rx) protocol .

[0117] A switch 34 included on the driver module 2 allows a user to manually set the microcontroller into a programming mode in which a testing or operating mode according to which the driver module 2 is to operate with the electronic module 6 can be programmed. The switch 34 may take the form of a push button.

[0118] The driver module 2 can be configured for receiving an external electrical PWM signal, for example from the external controller, using hardware 35 for PWM input selection included in the driver module 2. A PWM signal may be provided via an optical PWM input 42, the external power input 32, and / or internally from the microcontroller 3.

[0119] Gate resistors 36 are included in the driver module to allow for modification of drive signals 9 between gate driver(s) 4 and the output terminal(s) 10, that is, as a part of the intermediate circuitry described hereinbefore. The gate resistors 36 can help to speed up the turn on / off of the power transistor(s) 8. The resistance provided by the gate resistors 36 may take any one of only two values, a first value corresponding to an on state and a second value corresponding to an off state. Alternatively, the resistance provided by the gate resistors 36 may take any one of three or more values. Thus, the gate resistors 36 can provide a flexible way of modifying the drive signals 9 between the gate driver(s) 4 and the output terminal(s) 10.

[0120] The driver module 2 also includes hardware 37 for isolated power supply output access and external access to allow the output of isolated power supply modules 48 to be monitored, hardware 38 for selection of a short-circuit testing mode to allow for a testing mode for short circuit testing to be manually selected by a user, and a transient voltage suppressor 39 for suppressing local transient voltages associated with turn on / off of one or more power transistors 8.

[0121] A reset switch 40 is provided as a part of the driver module 2. A user can use the reset switch 40 to force the microcontroller 3 to revert to a default state, for example by erasing the values stored in the registers 15 or resetting those values to a factory configuration. A USB port 41 is also included as a part of the driver module 2 to allow for connection of the driver module 2 to the computer system 11. The driver module 2 includes optical PWM inputs 42 to allow for the external electrical PWM signal to be provided to one or more gate drivers 4 and hardware for gate resistor bypass 43 to allow the power of the at least one drive signal 9 provided to a control terminal of at least one power transistor 8 to be adjusted.

[0122] The driver module 2 also includes isolated power supply modules 44 to provide power to the gate drivers 4 and an alternative programming port 45 to allow the driver module 2 to be configured by either the computer system 11 or an external controller without needing to use the USB port 45.

[0123] Referring to Figures 6A-1 and 6A-2, first screenshots of the user interface 12 are shown. Figure 6A-1 shows panels for configuring a low side power transistor 8, 82 of the electronic module 6 and Figure 6A-2 shows corresponding panels for configuring a high side power transistor 8, 81 of the electronic module 6.

[0124] A first panel 48 is for initialising serial communications to and from the driver module 2.

[0125] A second panel 49 is for reading out values from the registers 15, 16, 17.

[0126] A third panel 50 is for selecting between the low side gate driver 8, 82 and the high side gate driver 8, 81.

[0127] A fourth panel 51 is for selecting and monitoring whether the driver module 2 is to be configured or to be run in a configuration.

[0128] A fifth panel 52 is for monitoring values read out by the microcontroller 3 to the computer system 11. The values may include DC-link voltage 28, a temperature read out by the hardware 29, positive gate drive supply voltage, or negative gate drive supply voltage.

[0129] A sixth panel 53 is for selecting an operating mode for the low side power transistor 8, 82, an operating mode for the high side transistor 8, 81, and / or a specific testing or operating mode for the driver module 2 with the electronic module 6 (in particular, double pulse testing, short circuit testing, unclamped inductive switching testing). A seventh panel 54 is for selecting the group of registers 15 of the microcontroller 3 to be read from or written to (namely, MODE, CONFIG, Status, ADC measurements, REQBIST, Quick Actions).

[0130] An eighth panel 55 is for reading and writing values to registers of the microcontroller 3, in this case to the MODE registers.

[0131] Referring also to Figure 6B, a second screenshot of the user interface 12 is shown. As for Figure 6A-1, panels for configuring a low side power transistor 8, 82 of the electronic module 6 are shown, and the user interface 12 includes corresponding panels (not shown) for configuring a high side power transistor 8, 81 of the electronic module 6.

[0132] A ninth panel 56 is for monitoring error signals and clearing faults communicated by the microcontroller 3 to the computer system 11.

[0133] A tenth panel 57 is for reading values from and writing values to the CONFIG registers of the microcontroller 3.

[0134] Referring also to Figure 6C, a third screenshot of the user interface 12 is shown. In particular, panels for configuring a low side power transistor 8, 82 of the electronic module 6 are shown. The panels shown in the third screenshot can provide a convenient way to configure the drive module 2. In particular, the panels shown in the third screenshot can provide a way to configure the drive module 2 which does not require a user to directly input values to be written to registers.

[0135] An eleventh panel 58 is for allowing a quick action to change an output voltage of a post regulator of the microcontroller 3 and for enabling / disabling the protection features of the driver module 2.

[0136] Double pulse testing

[0137] Referring to Figure 7A, a system 61 for double pulse testing is shown. The system 61 includes a driver module 2 including a high side gate driver 4, 4i and a low side gate driver 4, 42. The driver module also includes a microcontroller 3 which is connected to and configurable by an external computer system 11. The high side gate driver 4, 4i is connected to a control terminal of a first power transistor QI and the low side gate driver 4, 42 is connected to a control terminal of a second power transistor Q2. The first power transistor QI and the second power transistor Q2 are connected in series between a positive voltage rail 62 and a negative voltage rail 63, with an inductive load LI connected in parallel with the first power transistor QI, between the positive voltage rail 62 and a node between the first power transistor QI and the second power transistor Q2. In this way, the system 61 has a half bridge topology. Power is provided to the positive voltage rail 62 and the negative voltage rail 63 by a DC voltage source arranged in parallel with a capacitor C.

[0138] Unlike some systems for double pulse testing, such as those described in Fahel, the system 61 does not require the presence of a separate function generator. This is because the driver module 2 can be configured by the computer system 11 to perform the same functions as the separate function generator.

[0139] Referring also to Figure 7B, a fourth screenshot of the user interface 12 is shown. The fourth screenshot shows panels for configuring the system 61.

[0140] A first panel 64 is for selecting whether the driver module 2 is to drive one or both of the high side gate driver 4, 4i and the low side gate driver 4, 42. The first power transistor QI and the second power transistor Q2 can be respectively driven with complementary drive signals 9i, 92 by the high side gate driver 4, 4i and the low side gate driver 4, 42, so as to provide synchronous rectification operation, while double pulse testing is being carried out by the system 61.

[0141] A second panel 65 is for controlling either the high side gate driver 4, 4i or the low side gate driver 4, 42 to generate a single PWM drive signal 9 having a specific frequency and duty ratio. The panel 65 can be used to switch the first power transistor QI (or the second power transistor Q2) independently of the second power transistor Q2 (or the first power transistor QI) while double pulse testing is not being carried out by the system 61.

[0142] A third panel 66 is for generating a double pulse signal having an adjustable time profile.

[0143] A fourth panel 67 is for generating two complementary PWM drive signals 9, 9i and 9, 92 each having a specific frequency and duty ratio.

[0144] A fifth panel 68 is for generating a complementary double pulse signal having an adjustable time profile. A sixth panel 69 is for changing the deadtime for both the high side gate driver 4, 4i and the low side gate driver 4, 42.

[0145] Unclamped inductive switching testing

[0146] Referring to Figure 8A, a system 72 for unclamped inductive switching testing is shown. The system 72 includes a driver module 2 having a low side gate driver 4, 42 connected to a control terminal of a low side power transistor Q2. The low side power transistor Q2 is connected between a low voltage rail 63 and a node connected to a positive voltage rail 62. A high side power transistor QI is connected to the node and to the positive voltage rail in parallel with the connection between the node and the positive voltage rail 62. The high side power transistor QI has a control terminal which is (not shown) shorted to a source of the high side power transistor QI or connected to a negative voltage. Power is provided to the positive voltage rail 62 and the negative voltage rail 63 by a DC voltage source. An inductive load LI is connected between the positive terminal of the DC voltage source and the positive voltage rail 62.

[0147] Unlike some systems for unclamped inductive switching testing, such as those described in AN 1968, the system 72 does not require a separate pulse controller. This is because the driver module 2 can be configured by the computer system 11 to perform the same functions as the separate pulse controller.

[0148] Referring also to Figure 8B, a fifth screenshot of the user interface 12 is shown. The fifth screenshot shows panels for configuring the system 72, in particular, a panel 73 for generating a pulse with specific duration for unclamped inductive switching testing.

[0149] Short circuit testing

[0150] Referring to Figure 9A, a system 76 for short circuit testing is shown. The system 76 includes a driver module 2 including a high side gate driver 4, 4i and a low side gate driver 4, 42. The high side gate driver 4, 4i is connected to a control terminal of a third power transistor IGBT. The third power transistor IGBT is connected in parallel with a first power transistor QI between a positive voltage rail 62 and a node between the first power transistor QI and a second power transistor Q2. The first power transistor QI has a control terminal connected to a node between the first power transistor QI and the second power transistor Q2. The second power transistor Q2 has a control terminal connected to the low side gate driver 4, 42 and is connected at its remaining terminal to a negative voltage rail 63. Power is provided to the positive voltage rail 62 and the negative voltage rail 63 by a DC voltage source arranged in parallel with a capacitor C.

[0151] Unlike some systems for short circuit testing, such as those described in Diao, the system 76 does not require a separate pulse controller for a device under test and a protection device. This is because the driver module 2 can be configured by the computer system 11 to perform the same functions as the separate pulse controller.

[0152] Referring also to Figure 9B, a sixth screenshot of the user interface 12 is shown. The sixth screenshot shows panels for configuring the system 76, in particular, a panel 77 for generating synchronise pulses for the device under test and the protection device.

[0153] Power factor correction

[0154] Referring to Figure 10A, a system 80 for power factor correction is shown. The system 80 includes a driver module 2 which includes a high side gate driver 4, 4i and a low side gate driver 4, 42. The high side gate driver 4, 4i is connected to a control terminal of a first power transistor QI and the low side gate driver 4, 42 is connected to a control terminal of a second power transistor Q2. The first power transistor QI and the second power transistor are connected in parallel between a positive voltage rail 62 and a negative voltage rail 63, with an output diode D5 arranged between a first node where the first power transistor QI is connected to the positive voltage rail 62 and a second node where the second power transistor Q2 is connected to the positive voltage rail 62. Power is provided to the positive voltage rail 62 and the negative voltage rail 63 by an AC voltage source having its outputs connected to across an input smoothing capacitor Cl via a diode bridge rectifier DI, D2, D3, D4. An inductive load LI is arranged between the capacitor Cl and a node on the positive voltage rail 62 where the first power transistor QI is connected. A further capacitor C2 is arranged between the positive voltage rail 62 and the negative voltage rail 63 and the voltage across that further capacitor is taken as the output voltage Vout of the system 80.

[0155] Referring also to Figure 10B, an on-board charger system 83 for a battery of a vehicle is shown. In the on-board charger system 83, the system 80 is connected between the AC voltage source and the capacitor C2. The output voltage Vout is provided to a primary side 84 which is coupled to a secondary side 85 via a transformer. The secondary side 85 is connected to a HV battery 86 and a capacitor C3 is arranged between the positive voltage rail and negative voltage rail connecting the secondary side 85 to the HV battery 86. Bidirectional buck-boost converter

[0156] Referring to Figure 11, bidirectional buck-boost converter system 89 is shown. The system 89 includes a driver module 2 having a high side gate driver 4, 4i connected to a control terminal of a first power transistor QI and a low side gate driver 4, 42 connected to a terminal of a second power transistor Q2. The first power transistor QI and second power transistor Q2 are connected in series between a positive voltage rail 62 and a negative voltage rail 63. Power is provided to the positive voltage rail 62 and the negative voltage rail 63 by a DC voltage source arranged in parallel with a capacitor Cl. A node between the first power transistor QI and the second power transistor Q2 is connected to the negative voltage rail 63 via an inductive load LI and a further capacitor C2, with a terminal of the further capacitor C2 connected to the negative voltage rail 63. The voltage Vout across the capacitor C2 is taken to be the output voltage of the system 89.

[0157] Unlike some systems for providing a bidirectional buck-boost converter, such as those described in Ye, the system 89 does not require a separate controller to operate in this way. This is because the driver module 2 can be configured by the computer system 11 to perform the same functions as the separate controller.

[0158] Single-phase inverter

[0159] Referring to Figure 12, a single-phase inverter system 92 is shown. In contrast to the systems described hereinbefore which have a half bridge topology, the system 92 has a full bridge topology in which a first pair of power transistors Qll, Q12 are connected in series between a positive voltage rail 62 and a negative voltage rail 63, and a second pair of power transistors Q21, Q22 are connected in series between the positive voltage rail 62 and the negative voltage rail 63 in parallel with the first pair of power transistors Qll, Q22. A first driver module 2, 2i has a first high side gate driver (not shown) connected to a control terminal of the power transistor Qll and a first low side gate driver (not shown) connected to a terminal of the power transistor Q12, and a second driver module 2, 22 has a second high side gate driver (not shown) connected to a control terminal of the power transistor Q21 and a second low side gate driver (not shown) connected to a control terminal of the power transistor Q22. Power is provided to the positive voltage rail 62 and the negative voltage rail 63 by a DC voltage source arranged in parallel with a capacitor Cl. The output voltage Vout of the system 92 is taken as the voltage between a first node between the power transistors Qll and Q12 and a second node between the power transistors Q21 and Q22. Each driver module 2i, 22 has a respective microcontroller 3, each of which may operate in master mode and be directly controlled by the computer system 11. This need not be the case, however, and one of the microcontrollers may operate in slave mode and be controlled by another microcontroller.

[0160] In the case in which a microcontroller 3 that is operating in slave mode detects a fault, that microcontroller 3 may provide a fault signal to the computer system 11 via the USB connection and the microcontroller operating in master mode that is controlling it. In the case in which a microcontroller 3 that is operating in master mode detects a fault, that microcontroller may provide a fault signal to the computer system 11 that is operating in master mode via the USB connection. In response to receiving the fault signal, the computer system 11 can notify a user of the fault, for example by using one or both of the software application 13 and the user interface 12 to provide a visual indicator (not shown) to a user. The visual indication may take the form of an icon or a pop-up window containing an error message.

[0161] Three-phase inverter

[0162] Referring to Figure 13, a three-phase inverter system 95 is shown. The system 95 is a modified version of the system 92 in which a third pair of power transistors Q31, Q32 is connected between the positive voltage rail 62 and the negative power rail 63, in parallel with the first pair of power transistors Qll, Q22 and the second pair of power transistors Q21, Q22. A third driver module 2, 23 has a third high side gate driver connected to a control terminal of the power transistor Q31 and a third low side gate driver connected to a control terminal of the power transistor Q32. In the system 95, three output voltages are provided: a first output voltage V12 is taken as the voltage between a first node between the first pair of power transistors Qll, Q12 and a second node between the second pair of power transistors Q21, Q22, a second output voltage V23 is taken as the voltage between the second node and a third node between the third pair of power transistors Q31, Q32, and a third output voltage V13 is taken as the voltage between the first node and the third node.

[0163] As for the system 92, there is no requirement for each driver module 2 to include a respective microcontroller 3 operating in master mode. Rather, one or more of the driver modules 2 may have a respective microcontroller 3 operating in master mode which is controlled by the microcontroller of 3 another driver module 2 operating in master mode. Dual-active bridge

[0164] Referring to Figure 14A, a dual-active bridge system 98 is shown. The system 98 includes a first system 92, 92i having its output voltage connected across the primary winding of a transformer and a second system 92', 92'i connected across the secondary winding of a transformer. The second system 92', 92'i is a modified version of the system 92 in which the DC voltage source is omitted and an output voltage Vout is taken as the voltage across the terminals to which the DC voltage source would be connected were it not omitted.

[0165] Referring also to Figure 14B, a simplified representation of the system 98 of Figure 14A is shown, in which the first system 92, 92i is shown as one block and the second system 92', 92'2 is shown as another block.

[0166] Multi-active bridge

[0167] Referring to Figure 15, a multi-active bridge system 101 is shown. The system 101 is a generalised version of the system 98 in that it can include more than one first system 92, 92i...92nconnected to the primary winding of of the transformer and more than one second system 92', 92T...92'nconnected to the secondary winding of the transformer. The case of a dual active bridge corresponds to the case of m+n = 2. The case of a triple active bridge corresponds to the case of m+n=3. The case of a quad active bridge corresponds to the case of m+n=4. For each of these cases, m and n are required to be at least 1.

[0168] Validating shift in threshold voltage

[0169] Referring to Figure 16, a system 104 for validating shift in threshold voltage is shown. The system 104 includes a driver module 2 including a high side gate driver 4, 4i and a low side gate driver 4, 42. The driver module also includes a microcontroller 3 which is connected to and configurable by an external computer system 11. The high side gate driver 4, 4i is connected to a control terminal of a first power transistor QI and the low side gate driver 4, 42 is connected to a control terminal of a second power transistor Q2. The first power transistor QI and the second power transistor Q2 are connected in series between a positive voltage rail 62 and a negative voltage rail 63. Power is provided to the positive voltage rail 62 and the negative voltage rail 63 by a DC voltage source.

[0170] Modifications

[0171] It will be appreciated that various modifications may be made to the embodiments hereinbefore described. Such modifications may involve equivalent and other features which are already known in the field of power electronics, and which may be used instead of or in addition to features already described herein. Features of one embodiment may be replaced or supplemented by features of another embodiment.

[0172] As hereinbefore described, the configurable gate driver assembly 2 can be used with the electronic assembly 6 in a wide variety of testing or operating modes, each testing or operating mode corresponding to a use case or application of the electronic assembly 6. The configurable gate driver assembly 2 and electronic assembly 6, however, need not be limited to these use cases or applications and may be employed in other use cases or applications. For example, the configurable gate driver 2 may be used with the electronic assembly / module 6 in a use case or application which relates to or makes use of artificial intelligence (Al).

[0173] Although claims have been formulated in this application to particular combinations of features, it should be understood that the scope of the disclosure of the present invention also includes any novel features or any novel combination of features disclosed herein either explicitly or implicitly or any generalization thereof, whether or not it relates to the same invention as presently claimed in any claim and whether or not it mitigates any or all of the same technical problems as does the present invention. The applicants hereby give notice that new claims may be formulated to such features and / or combinations of such features during the prosecution of the present application or of any further application derived therefrom.

Claims

Claims1. A configurable gate driver assembly comprising : an interface for receiving a removably insertable power electronic assembly; at least one gate driver for driving at least one power transistor in the removably insertable power electronic assembly; and a microcontroller arranged to control operation of each gate driver, the microcontroller being configurable by an external computer system whereby a testing or operating mode is selectable from a plurality of different testing or operating modes, each testing or operating mode corresponding to a use case or application of the power electronic assembly.

2. The configurable gate driver assembly of claim 1, wherein the at least one gate driver comprises: a first single-channel gate driver for driving a first power transistor of the power electronic assembly; and a second single-channel gate driver for driving a second power transistor of the power electronic assembly.

3. The configurable gate driver assembly of claim 2, wherein the configurable gate driver assembly comprises only two gate drivers, the only two gate drivers being the first single-channel gate driver and the second single-channel gate driver.

4. The configurable gate driver assembly of claim 1, wherein the at least one gate driver comprises a dual-channel gate driver, the dual-channel gate driver for driving a first power transistor of the power electronic assembly and a second power transistor of the power electronic assembly.

5. The configurable gate driver assembly of any one of claims 2 to 4, wherein the first power transistor is a high side power transistor and the second power transistor is a low side power transistor.

6. The configurable gate driver assembly of any one of claims 1 to 5, wherein the configurable gate driver assembly is a configurable gate driver module and the power electronic assembly is a power electronic module.

7. The configurable gate driver assembly of any one of claims 1 to 6, wherein the at least one gate driver is capable of outputting at least one drive signal having:a voltage in the range VL to VH, wherein VL and VH are application dependant voltages; and / or a current in the range II to IH, wherein II and IH are application dependant currents.

8. The configurable gate driver assembly of any one of claims 1 to 7, wherein each gate driver has a set of registers for storing values of one or more parameters of a testing or operating mode according to which said gate driver is to operate.

9. The configurable gate driver assembly of claim 8, wherein: values stored in the set of registers of each gate driver are configurable by the microcontroller and / or an external controller; and the set of registers of each gate driver is volatile memory.

10. The configurable gate driver assembly of any one of claims 1 to 9, wherein: the microcontroller has a set of registers for storing values of parameters of one or more testing or operating modes; the set of registers of the microcontroller is non-volatile memory; and the values stored in the set of registers of the microcontroller are configurable by the computer system.

11. The configurable gate driver assembly of claim 10, wherein the values stored in the set of registers of the microcontroller are usable by the microcontroller to set a testing or operating mode according to which the configurable gate driver assembly is to operate.

12. The configurable gate driver assembly of claim 10 or 11, wherein the values stored in the set of registers of the microcontroller are usable to set the values stored in the set of registers of each gate driver.

13. The configurable gate driver assembly of any one of claims 1 to 12, wherein the configurable gate driver assembly is arranged to be configured based on an instruction received from a software application installed on the computer system.

14. The configurable gate driver assembly of any one of claims 1 to 13, wherein the configurable gate driver assembly is arranged to be configured based on an instruction received from a software application installed on a server connected to the computer system.

15. A first system comprising: a computer system having a user interface; and the configurable gate driver assembly of any one of claims 1 to 14, wherein the computer system is operable to receive an instruction from a user, via the user interface, to select a testing or operating mode selectable from a plurality of different testing or operating modes corresponding to different use case or application of the power electronic assembly and to set parameters for the testing or operating mode.

16. A second system comprising: the configurable gate driver assembly of any one of claims 1 to 14 or the first system of claim 15; and the removably insertable power electronic assembly.

17. The second system of claim 16, operable: in a testing mode for one or more of double pulse testing, unclamped inductive switching testing, and short circuit testing; and / or in an operating mode for power factor correction.

18. The second system of claim 16 or 17, operable in an operating mode for a bidirectional buck boost converter.

19. The second system of any one of claims 16 to 18, operable in an operating mode for a three-phase inverter.

20. The second system of any one of claims 16 to 19, operable in an operating mode for a dual active bridge.

21. The second system of any one of claims 16 to 20, wherein the second system comprises: a first configurable gate driver assembly having a first microcontroller configured to operate in slave mode; and a second configurable gate driver assembly having a second microcontroller configured to operate in master mode and to control the first microcontroller.

22. The second system of claim 21, wherein the first microcontroller is configured, in response to detecting a fault, to provide a fault signal to the second microcontroller.

23. A method of operating a configurable gate driver, the configurable gate driver comprising: an interface for receiving a removably insertable power electronic assembly; at least one gate driver for driving at least one power transistor in the removably insertable power electronic assembly; and a microcontroller arranged to control operation of each gate driver, the microcontroller being configurable by an external computer system whereby a testing or operating mode is selectable from a plurality of different testing or operating modes, each testing or operating mode corresponding to a use case or application of the power electronic assembly, the method comprising one or more of: the interface receiving the removably insertable power electronic assembly; the computer system configuring the microcontroller; the microcontroller controlling operation of each gate driver; and the at least one gate driver driving the at least one power transistor.

24. A computer program which, when executed by at least one processor, causes the at least one processor to perform the method of claim 23.

25. A computer program product comprising a computer-readable medium storing the computer program of claim 24.

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