Semiconductor device and method for driving semiconductor device

Abstract

Provided is a novel method for driving a semiconductor device. This method is for driving a semiconductor device including a plurality of memory cells connected to one word line, the plurality of memory cells being connected in a one-to-one manner to a plurality of bit lines, the plurality of memory cells being connected in a one-to-one manner to a plurality of plate lines, and each of the plurality of memory cells including a ferroelectric capacitor and a transistor. The method comprises, when writing data to the plurality of memory cells, applying a first potential to the plate line to which is connected a memory cell in which to write data for 0, and applying a second potential to the plate line to which is connected a memory cell in which to write data for 1.

Description

Semiconductor device and method for driving the same

[0001] One embodiment of the present invention relates to a semiconductor device and a method for driving the semiconductor device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one embodiment of the invention disclosed in this specification and the like relates to an object, a method, a driving method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter. More specifically, examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include semiconductor devices, display devices, light-emitting devices, power storage devices, optical devices, imaging devices, lighting devices, projection devices, electro-optical devices, light-receiving devices, detection devices, power supply devices, communication devices, information processing devices, arithmetic units, control devices, memory devices, input devices, output devices, input / output devices, signal processing devices, arithmetic processing devices, electronic computers, electronic devices, systems including these devices, and driving methods or manufacturing methods thereof.

[0003] Development of semiconductor devices such as large-scale integration (LSI), central processing units (CPU), and memories (storage devices) is progressing. These semiconductor devices are used in various electronic devices such as computers and personal digital assistants. Furthermore, memories of various storage methods have been developed depending on the application, such as temporary storage during arithmetic processing and long-term storage of data. Typical memory storage methods include, for example, dynamic random access memory (DRAM), static random access memory (SRAM), and flash memory.

[0004] Furthermore, as shown in Non-Patent Documents 1 and 2, research and development of memories using ferroelectrics is being actively carried out. For next-generation ferroelectric memories, ferroelectric HfO ２ Research on Hf-based materials (Non-Patent Document 3), ０．５ Zr ０．５ O ２ Research on ferroelectricity of thin films (Non-Patent Document 4), HfO２ Research on ferroelectricity of thin films (Non-Patent Document 5), and ferroelectric Hf ０．５ Zr ０．５ O ２ Research related to hafnium oxide is also being actively conducted, including the demonstration of integration of FeRAM (Ferroelectric Random Access Memory) and CMOS using hafnium oxide (Non-Patent Document 6).

[0005] Also, In ２ O ３ It has been reported that the compound is used in thin film transistors (Non-Patent Document 7).

[0006] T. S. Boescke, et al. , “Ferroelectricity in hafnium oxide thin films”, APL99, 2011N. Ramaswamy, et al. , “NVDRAM: A 32Gb Dual Layer 3D Stacked Non-volatile Ferroelectric Memory with Near-DRAM Performance for Demanding AI “Workloads”, IEDM 2023Zhen Fan, et al. , "Ferroelectric HfO2-based materials for next-generation ferroelectric memories," JOURNAL OF ADVANCED DIELECTRICS, Vol. 6, No. 2, 2016; Jun Okuno, et al., "SoC compatible 1T1C FeRAM memory array based on ferroelectric Hf0.5Zr0.5O2," VLSI 2020; Akira Toriumi, "Ferroelectricity of HfO2 thin films," The Japan Society of Applied Physics, Vol. 88, No. 9, 2019. Francois, et al. , “Demonstration of BEOL-compatible ferroelectric Hf▲0.5▼Zr▲0.5▼O▲2▼ scaled FeRAM co-integrated with 130nm CMOS for embedded NVM applications”, IEDM 2019Dhananjay and C. W. Chu, “Realization of In▲2▼O▲3▼ thin film transistors through reactive evaporation process” Appl. Phys. Lett. 91, 132111 (2007). Takashi Koida, "High Mobility Transparent Conductive Film", National Institute of Advanced Industrial Science and Technology, AIST Photovoltaic Power Generation Research Results Report 2019, Internet <URL: https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13.pdf>

[0007] An object of one embodiment of the present invention is to provide a semiconductor device with high operating speed, a storage device including the semiconductor device, or a method for driving the semiconductor device. Another object of one embodiment of the present invention is to provide a semiconductor device with long retention time, a storage device including the semiconductor device, or a method for driving the semiconductor device. Another object of one embodiment of the present invention is to provide a semiconductor device with high recording density, a storage device including the semiconductor device, or a method for driving the semiconductor device. Another object of one embodiment of the present invention is to provide a miniaturized semiconductor device, a storage device including the semiconductor device, or a method for driving the semiconductor device. Another object of one embodiment of the present invention is to provide a highly reliable semiconductor device, a storage device including the semiconductor device, or a method for driving the semiconductor device. Another object of one embodiment of the present invention is to provide a semiconductor device with low power consumption, a storage device including the semiconductor device, or a method for driving the semiconductor device. Another object of one embodiment of the present invention is to provide a novel semiconductor device, a storage device including the semiconductor device, or a method for driving the semiconductor device.

[0008] The above-mentioned problem does not preclude the existence of other problems. A person skilled in the art can naturally derive other problems from the description in this specification, drawings, claims, etc., and can extract other problems from the description in this specification, drawings, claims, etc. Note that one embodiment of the present invention does not necessarily solve all of these problems (the above-mentioned problem and other problems).

[0009] (1) One aspect of the present invention is a method for driving a semiconductor device having a plurality of memory cells connected to one word line, the plurality of memory cells being connected one-to-one to a plurality of bit lines, and the plurality of memory cells being connected one-to-one to a plurality of plate lines, each of the plurality of memory cells having a ferroelectric capacitor and a transistor, and in each of the plurality of memory cells, one terminal of the ferroelectric capacitor is electrically connected to one of the source or drain of the transistor, the other terminal of the ferroelectric capacitor is electrically connected to the plate line, the other of the source or drain of the transistor is electrically connected to the bit line, and the gate of the transistor is electrically connected to the word line, wherein, when writing data to the plurality of memory cells, a first potential is applied to the plate line connected to the memory cell to which data 0 is to be written, and a second potential is applied to the plate line connected to the memory cell to which data 1 is to be written.

[0010] (2) In the above (1), the difference between the first potential and the second potential may be equal to or greater than the saturated polarization voltage of the ferroelectric capacitor.

[0011] (3) One aspect of the present invention is a memory cell having a first memory cell, a second memory cell, a first drive circuit, and a second drive circuit, the first memory cell having a first ferroelectric capacitor and a first transistor, the second memory cell having a second ferroelectric capacitor and a second transistor, one terminal of the first ferroelectric capacitor being electrically connected to one of the source or drain of the first transistor, the other terminal of the first ferroelectric capacitor being electrically connected to a first plate line, the other of the source or drain of the first transistor being electrically connected to a first bit line, the gate of the first transistor being electrically connected to a word line, one terminal of the second ferroelectric capacitor being electrically connected to the second transistor the other terminal of the second ferroelectric capacitor is electrically connected to one of the source or drain of the second transistor, the other terminal of the second ferroelectric capacitor is electrically connected to a second plate line, the other of the source or drain of the second transistor is electrically connected to a second bit line, the gate of the second transistor is electrically connected to a word line, the first drive circuit is electrically connected to the first plate line, and the second drive circuit is electrically connected to the second plate line, the first drive circuit has a function of applying a potential corresponding to data to the first plate line when writing data to the first memory cell, and the second drive circuit has a function of applying a potential corresponding to data to the second plate line when writing data to the second memory cell.

[0012] (4) Also, in the above (3), the first drive circuit has a function of applying a first potential to the first plate line when writing data 0 and applying a second potential to the first plate line when writing data 1, the second drive circuit has a function of applying a first potential to the second plate line when writing data 0 and applying a second potential to the second plate line when writing data 1, and the difference between the first potential and the second potential may be equal to or greater than the saturation polarization voltage of the first ferroelectric capacitor and equal to or greater than the saturation polarization voltage of the second ferroelectric capacitor.

[0013] (5) One aspect of the present invention includes a substrate, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and an insulating layer, the substrate including a channel formation region, a source region, and a drain region of a transistor, the first conductive layer functions as a gate electrode of the transistor, the second conductive layer is provided above a layer in which the first conductive layer is provided, the second conductive layer is electrically connected to one of the source region and the drain region, and the third conductive layer is provided above the layer in which the second conductive layer is provided. the third conductive layer is electrically connected to the other of the source region or the drain region, the third conductive layer has a columnar shape, the insulating layer is provided so as to cover the third conductive layer, the insulating layer includes a material that may have ferroelectricity, the fourth conductive layer is provided so as to cover the insulating layer, the first conductive layer extends in a first direction along an upper surface of the substrate, the second conductive layer extends in a second direction that intersects with the first direction and is along the upper surface of the substrate, and the fourth conductive layer extends in the second direction.

[0014] (6) In the above (5), the first conductive layer may function as a word line, the second conductive layer may function as a bit line, and the fourth conductive layer may function as a plate line.

[0015] (7) In the above (5) or (6), the substrate may have a trench located between the source region and the drain region, and the first conductive layer may be provided so as to fill at least a portion of the trench.

[0016] According to one embodiment of the present invention, a semiconductor device with high operating speed, a storage device including the semiconductor device, or a method for driving the semiconductor device can be provided. According to one embodiment of the present invention, a semiconductor device with long retention time, a storage device including the semiconductor device, or a method for driving the semiconductor device can be provided. According to one embodiment of the present invention, a semiconductor device with high recording density, a storage device including the semiconductor device, or a method for driving the semiconductor device can be provided. According to one embodiment of the present invention, a miniaturized semiconductor device, a storage device including the semiconductor device, or a method for driving the semiconductor device can be provided. According to one embodiment of the present invention, a highly reliable semiconductor device, a storage device including the semiconductor device, or a method for driving the semiconductor device can be provided. According to one embodiment of the present invention, a low-power semiconductor device, a storage device including the semiconductor device, or a method for driving the semiconductor device can be provided. According to one embodiment of the present invention, a novel semiconductor device, a storage device including the semiconductor device, or a method for driving the semiconductor device can be provided.

[0017] Note that the above effects do not preclude the existence of other effects. A person skilled in the art can naturally derive other effects from the description in this specification, drawings, claims, etc., and can extract other effects from the description in this specification, drawings, claims, etc. Note that one embodiment of the present invention does not necessarily have all of these effects (the above effects and other effects).

[0018] FIG. 1A is a circuit diagram illustrating an example of the configuration of a semiconductor device. FIG. 1B is a timing chart illustrating an example of a method for driving a semiconductor device. FIG. 2 is a diagram illustrating an example of hysteresis characteristics of a ferroelectric. FIGS. 3A and 3B are circuit diagrams illustrating an example of the operation of a semiconductor device. FIGS. 4A and 4B are circuit diagrams illustrating an example of the operation of a semiconductor device. FIGS. 5A and 5B are circuit diagrams illustrating an example of the operation of a semiconductor device. FIG. 6 is a timing chart illustrating an example of a method for driving a semiconductor device. FIG. 7 is a timing chart illustrating an example of a method for driving a semiconductor device. FIGS. 8A and 8B are circuit diagrams illustrating an example of the operation of a semiconductor device. FIGS. 9A and 9B are circuit diagrams illustrating an example of the operation of a semiconductor device. FIGS. 10A and 10B are circuit diagrams illustrating an example of the operation of a semiconductor device. FIG. 11 is a timing chart illustrating an example of a method for driving a semiconductor device. FIGS. 12A and 12B are circuit diagrams illustrating an example of the configuration of a semiconductor device. FIG. 13 is a circuit diagram illustrating an example of the configuration of a semiconductor device. FIG. 14 is a schematic diagram illustrating an example of the configuration of a memory device. FIG. 15 is a perspective schematic view illustrating an example of the configuration of a semiconductor device. 16A and 16B are top views illustrating an example of the configuration of a semiconductor device. FIG. 17 is a cross-sectional view illustrating an example of the configuration of a semiconductor device. FIG. 18 is a cross-sectional view illustrating an example of the configuration of a semiconductor device. FIG. 19 is a cross-sectional view illustrating an example of the configuration of a semiconductor device. FIGS. 20A and 20B are diagrams illustrating the carrier concentration dependence of Hall mobility. FIG. 20C is a cross-sectional view illustrating an indium oxide film. FIG. 21 is a diagram illustrating various memory devices by layer. FIGS. 22A and 22B are diagrams illustrating an example of electronic components. FIGS. 23A and 23B are diagrams illustrating an example of electronic equipment. FIGS. 23C to 23E are diagrams illustrating an example of a mainframe computer. FIG. 24A is a diagram illustrating an example of space equipment. FIG. 24B is a diagram illustrating an example of a storage system applicable to a data center. FIGS. 24C and 24D are diagrams illustrating an example of electronic equipment. FIGS. 25A1 to 25A7 and 25B1 to 25B6 are diagrams illustrating electrical connections.

[0019] In this specification, a semiconductor device refers to a device that utilizes semiconductor characteristics, such as a circuit including a semiconductor element (e.g., a transistor or a diode), or a device having such a circuit. It also refers to any device that can function by utilizing semiconductor characteristics. Examples of semiconductor devices include electronic circuits including semiconductor elements, chips equipped with electronic circuits, electronic components with chips housed in packages, and electronic devices equipped with electronic components. Furthermore, display devices, light-emitting devices, power storage devices, optical devices, imaging devices, lighting devices, projection devices, electro-optical devices, light-receiving devices, detection devices, power supply devices, communication devices, information processing devices, arithmetic units, control devices, memory devices, input devices, output devices, input / output devices, signal processing devices, arithmetic processing devices, electronic computers, and electronic devices may themselves be semiconductor devices and may also include semiconductor devices.

[0020] The following description of the embodiments will be given with reference to the drawings. However, the embodiments can be implemented in many different forms. Therefore, it will be readily understood by those skilled in the art that various changes can be made to the embodiments and their details without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the following description of the embodiments.

[0021] In this specification and the like, the configuration shown in each embodiment can be appropriately combined with the configuration shown in another embodiment to form one aspect of the present invention. Furthermore, when multiple configurations are shown in one embodiment, these configurations can be appropriately combined to form one aspect of the present invention.

[0022] In addition, in the drawings illustrating the embodiments, the same reference numerals may be used in common between different drawings for the same parts or parts having similar functions in the configuration of the invention, thereby omitting repeated description thereof. Furthermore, when the drawings indicate similar functions, for example, the same hatching patterns may be used and no particular reference numerals may be used. Furthermore, in the drawings, for example, in perspective views or top views (also called "plan views"), the illustration of some components may be omitted for ease of understanding. Furthermore, in the drawings, for example, the illustration of some hidden lines may be omitted. Furthermore, in the drawings, for example, the illustration of hatching patterns may be omitted.

[0023] In addition, in the drawings, the size, layer thickness, or region may be exaggerated for clarity. Therefore, the drawings are not limited to, for example, their size or aspect ratio. The drawings are schematic illustrations to facilitate understanding of the present invention and are not limited to, for example, the shapes or values ​​shown in the drawings. For example, in an actual manufacturing process, layers or resist masks may be unintentionally thinned by processes such as etching. However, these may not be reflected in the drawings to facilitate understanding. Furthermore, for example, in actual circuit operation, variations in voltage or current may occur due to noise or timing errors. However, these may not be reflected in the drawings to facilitate understanding.

[0024] Furthermore, in this specification and drawings, components may be classified by function and shown as independent elements. However, it may be difficult to separate components by function, and one element may be involved in multiple functions, or one function may be involved across multiple elements. Therefore, the elements shown in this specification and drawings may not be limited to the descriptions therein, and may be rephrased appropriately.

[0025] Furthermore, in this specification and drawings, when the same reference numeral is used for multiple elements, and particularly when it is necessary to distinguish between them, the reference numeral may be accompanied by an identifying symbol such as "A", "b", "_1", "[n]", or "[m, n]". Furthermore, when explaining matters common to multiple elements accompanied by identifying symbols, or when it is not necessary to distinguish between them, the elements may be described without the identifying symbol.

[0026] In this specification and the like, the "conductive state" or "on state" of a transistor refers to, for example, a state in which the source and drain of the transistor are considered to be electrically short-circuited, or a state in which a current can flow between the source and drain (also referred to as a state in which a current can flow). For example, a state in which the voltage between the gate and source of an n-channel transistor is higher than the threshold voltage, or a state in which the voltage between the gate and source of a p-channel transistor is lower than the threshold voltage, may be referred to as the "conductive state" or "on state." In addition, the "non-conductive state," "cutoff state," or "off state" of a transistor refers to a state in which the source and drain of the transistor are considered to be electrically cut off. For example, a state in which the voltage between the gate and source of an n-channel transistor is lower than the threshold voltage, or a state in which the voltage between the gate and source of a p-channel transistor is higher than the threshold voltage, may be referred to as the "non-conductive state," "cutoff state," or "off state."

[0027] In this specification and the like, the voltage between the gate and the source (gate-source) (based on the source potential unless otherwise specified) may be referred to as the "gate voltage," the voltage between the drain and the source (drain-source) (based on the source potential unless otherwise specified) may be referred to as the "drain voltage," and the voltage between the backgate and the source (backgate-source) (based on the source potential unless otherwise specified) may be referred to as the "backgate voltage." Furthermore, the current flowing between the drain and the source (positive in the direction from the drain to the source unless otherwise specified) may be referred to as the "drain current." Note that, in an n-channel transistor, terms such as "high gate voltage," "high drain voltage," and "high backgate voltage" can be interchangeable with terms such as "low gate voltage," "low drain voltage," and "low backgate voltage" in a p-channel transistor, as appropriate. Furthermore, in an n-channel transistor, descriptions such as a low gate voltage, a low drain voltage, and a low back gate voltage can be interchanged with descriptions such as a high gate voltage, a high drain voltage, and a high back gate voltage in a p-channel transistor, as appropriate.

[0028] In this specification and the like, unless otherwise specified, the "off-state current" of a transistor refers to the drain current when the transistor is in an off state. Note that in this specification and the like, the off-state current and the current flowing between the gate and the source and drain (also referred to as gate leakage current) may be collectively referred to as leakage current.

[0029] Embodiment 1 A semiconductor device according to one embodiment of the present invention will be described with reference to the drawings. At least part of a semiconductor device according to one embodiment of the present invention can be used for a memory device or the like.

[0030] 1A is a circuit diagram illustrating a semiconductor device 100 according to one embodiment of the present invention. FIG. 1B is a timing chart illustrating an example of a method for driving the semiconductor device 100.

[0031] The semiconductor device 100 has a plurality of memory cells arranged in a matrix. The semiconductor device 100 can also be called a memory array.

[0032] 1A shows four representative memory cells MC: a memory cell MC11 arranged in the first row and first column, a memory cell MC12 arranged in the first row and second column, a memory cell MC21 arranged in the second row and first column, and a memory cell MC22 arranged in the second row and second column.

[0033] The memory cell MC11 includes a transistor Tr11 and a capacitor Cfe11. One of the source and drain of the transistor Tr11 is connected to one terminal of the capacitor Cfe11. The other of the source and drain of the transistor Tr11 is connected to a wiring BL1. The gate of the transistor Tr11 is connected to a wiring WL1. The other terminal of the capacitor Cfe11 is connected to a wiring PL1.

[0034] The memory cell MC12 includes a transistor Tr12 and a capacitor Cfe12. One of the source and drain of the transistor Tr12 is connected to one terminal of the capacitor Cfe12. The other of the source and drain of the transistor Tr12 is connected to a wiring BL2. The gate of the transistor Tr12 is connected to a wiring WL1. The other terminal of the capacitor Cfe12 is connected to a wiring PL2.

[0035] The memory cell MC21 includes a transistor Tr21 and a capacitance element Cfe21. One of the source and drain of the transistor Tr21 is connected to one terminal of the capacitance element Cfe21. The other of the source and drain of the transistor Tr21 is connected to a wiring BL1. The gate of the transistor Tr21 is connected to a wiring WL2. The other terminal of the capacitance element Cfe21 is connected to a wiring PL1.

[0036] The memory cell MC22 includes a transistor Tr22 and a capacitor Cfe22. One of the source and drain of the transistor Tr22 is connected to one terminal of the capacitor Cfe22. The other of the source and drain of the transistor Tr22 is connected to a wiring BL2. The gate of the transistor Tr22 is connected to a wiring WL2. The other terminal of the capacitor Cfe22 is connected to a wiring PL2.

[0037] The wirings WL1 and WL2 each function as a word line and extend, for example, in the row direction. The wirings BL1 and BL2 each function as a bit line and extend, for example, in the column direction. The wirings PL1 and PL2 each function as a plate line and extend, for example, in the column direction.

[0038] Therefore, in the semiconductor device 100, the direction in which the wiring that functions as a plate line extends can be perpendicular to the direction in which the wiring that functions as a word line extends, and can be parallel to the direction in which the wiring that functions as a bit line extends.

[0039] In the semiconductor device 100, when describing matters common to each memory cell, they may be simply referred to as memory cell MC. When describing matters common to the transistor and capacitor element of each memory cell, they may be simply referred to as transistor Tr and capacitor element Cfe. When describing matters common to each wiring functioning as a word line, they may be simply referred to as wiring WL. When describing matters common to each wiring functioning as a bit line, they may be simply referred to as wiring BL. When describing matters common to each wiring functioning as a plate line, they may be simply referred to as wiring PL.

[0040] The transistor Tr can be an n-channel or p-channel transistor. Here, an n-channel transistor is used as an example. The transistor Tr functions as a switch.

[0041] As the capacitance element Cfe, a capacitance element (also called a ferroelectric capacitor) using a material (also called a ferroelectric) that can have ferroelectricity as a dielectric can be used.

[0042] A ferroelectric material has the property that when a voltage is applied, the polarization aligns in a certain direction, and the polarization remains aligned even after the voltage application is stopped.Ferroelectrics also have the property that the polarization reverses when the voltage application is reversed.Memory cells using ferroelectric capacitors can function as nonvolatile memory elements by applying the properties of ferroelectrics.Note that storage devices having memory cells using ferroelectric capacitors are sometimes called ferroelectric memories (FeRAM).

[0043] In a memory cell using a ferroelectric capacitor, for example, binary data can be stored by making the polarity of the remanent polarization of the ferroelectric correspond to "1" or "0".

[0044] Here, in a memory cell MC using a ferroelectric capacitor as the capacitance element Cfe, the polarity of the voltage applied to the capacitance element Cfe needs to be changed when writing data "1" and when writing data "0," resulting in a high operating voltage. Therefore, in order to lower the operating voltage, for example, different potentials are applied to the wiring PL when writing data "1" and when writing data "0." In this case, for example, in a configuration in which the direction in which the wiring PL extends is parallel to the direction in which the wiring WL extends, i.e., in a configuration in which multiple memory cells MC arranged in one row are connected to one wiring PL, it is necessary to provide separate periods for writing data "1" and writing data "0" when writing data.

[0045] The semiconductor device 100 according to one embodiment of the present invention has a configuration in which the direction in which the wiring PL extends is parallel to the direction in which the wiring BL extends, i.e., multiple memory cells MC arranged in one column are connected to one wiring PL. This allows the potential applied to the wiring PL to be controlled for each column. That is, when writing data to multiple memory cells MC arranged in one row, the potential of the wiring PL can be controlled for each memory cell MC. Therefore, data "1" and data "0" can be simultaneously written to multiple memory cells MC arranged in one row. As will be described in detail later, for example, in period T13 (corresponding to the data write period) in FIG. 1B , different potentials are applied to the wiring PL1 and the wiring PL2, thereby simultaneously writing data "0" to memory cell MC11 and data "1" to memory cell MC12. This shortens the data write time and improves the operating speed.

[0046] In one embodiment of the present invention, a transistor including a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, or an amorphous semiconductor in a channel formation region can be used as a transistor included in a memory cell MC. The semiconductor is not limited to a simple semiconductor whose main component is a single element (such as silicon or germanium), but can also be, for example, a compound semiconductor (such as silicon germanium or gallium arsenide), an oxide semiconductor, or the like.

[0047] For example, a transistor including silicon in a channel formation region (Si transistor) or a transistor including an oxide semiconductor in a channel formation region (OS transistor) may be used as a transistor included in the memory cell MC.

[0048] Furthermore, various types of transistors can be used as the transistors that make up the memory cells MC, such as MOS field effect transistors, junction field effect transistors, and bipolar transistors.

[0049] In addition, transistors of various structures can be used as transistors constituting the memory cell MC. For example, transistors of various structures can be used, such as top-gate type (e.g., planar type, staggered type, etc.), bottom-gate type (e.g., inverted planar type, inverted staggered type, etc.), dual-gate type (structure in which gates are arranged on both sides (e.g., top and bottom) of a channel formation region), FIN type (fin type), TRI-GATE type (tri-gate type), and GAA type (gate-all-around type). In addition, for example, a vertical transistor (a transistor whose channel length direction is vertical (also referred to as the height direction or the direction perpendicular to the formation surface)) can be used.

[0050] In one embodiment of the present invention, an OS transistor, for example, is preferably used as a transistor included in the memory cell MC.

[0051] The OS transistor has a characteristic of having an extremely small off-state current because the band gap of the oxide semiconductor in which the channel is formed is 2 eV or more. The off-state current of an OS transistor per 1 μm of channel width in a room temperature environment is 1 aA (1×10 −１８ A) Below, 1zA (1×10 −２１ A) or less, or 1 yA (1 x 10 −２４ In the case of a Si transistor, the off-state current per 1 μm of channel width in a room temperature environment can be 1 fA (1×10 −１５ A) or more and 1 pA (1 × 10 −１２ Therefore, it can be said that the off-state current of an OS transistor is smaller than that of a Si transistor by about 10 orders of magnitude.

[0052] Furthermore, the off-state current of an OS transistor hardly increases even in a high-temperature environment. Specifically, the off-state current hardly increases even in an environment of room temperature or higher and 200° C. or lower. Furthermore, the on-state current of an OS transistor is unlikely to decrease even in a high-temperature environment. Therefore, a semiconductor device including an OS transistor can operate stably and achieve high reliability even in a high-temperature environment.

[0053] Furthermore, an OS transistor has a high withstand voltage between the source and the drain (also referred to as drain withstand voltage). Therefore, a semiconductor device including an OS transistor can operate stably and with high reliability even when driven at high voltage.

[0054] Depending on the configuration of the ferroelectric capacitor, a relatively large voltage may need to be applied to reverse the polarization. Therefore, it is preferable to use a transistor with a high drain breakdown voltage as the transistor Tr of the memory cell MC. For example, using an OS transistor with a high drain breakdown voltage as the transistor Tr can stabilize operation and improve reliability.

[0055] Furthermore, depending on the composition of the ferroelectric, a large current may flow through the ferroelectric. Therefore, for example, a current flowing through the transistor Tr and the capacitor Cfe of the memory cell MC (i.e., a current flowing between the wiring BL and the wiring PL) may increase power consumption. Furthermore, for example, when reading data, the current flowing through the transistor Tr and the capacitor Cfe may affect the potential change of the wiring BL, resulting in a decrease in data read accuracy. Therefore, it is preferable to use a transistor with a small off-state current for the transistor Tr of the memory cell MC. For example, using an OS transistor as the transistor Tr with a small off-state current can reduce the current flowing through the transistor Tr and the capacitor Cfe, thereby reducing power consumption. Furthermore, data read accuracy and reliability can be improved.

[0056] Furthermore, it is preferable to use a transistor with a large on-state current as the transistor Tr included in the memory cell MC. For example, by using an OS transistor with a large on-state current as the transistor Tr, a sufficient on-state current can be obtained even if the channel width of the transistor Tr is reduced. Therefore, for example, the area occupied by the transistor Tr can be reduced, thereby improving the recording density. Furthermore, the gate capacitance of the transistor Tr can be reduced, thereby improving the operating speed.

[0057] Here, various oxide semiconductors can be used for the OS transistor. When an OS transistor is used as the transistor Tr included in the memory cell MC, it is preferable to use an oxide semiconductor that exhibits low off-state current and high on-state current. Examples of oxide semiconductors that exhibit low off-state current and high on-state current include indium oxide. Details of oxide semiconductors that can be used for OS transistors will be described later. Indium oxide, which is one of the oxide semiconductors, will also be described in detail in Embodiment 3.

[0058] [Hysteresis Characteristics of Ferroelectrics] Ferroelectrics have hysteresis characteristics, which will be described below.

[0059] FIG. 2 is a diagram showing an example of the hysteresis characteristic of a ferroelectric. The hysteresis characteristic of a ferroelectric can be measured using a ferroelectric capacitor. In FIG. 2, the horizontal axis represents the voltage (electric field) applied to the ferroelectric. This voltage is the potential difference between one electrode and the other electrode of the ferroelectric capacitor. The electric field strength can be calculated by dividing this potential difference by the thickness of the ferroelectric.

[0060] In Figure 2, the vertical axis represents the polarization of the ferroelectric. When the polarization is positive, it indicates that the positive charge in the ferroelectric is biased toward one electrode of the capacitance element, and the negative charge is biased toward the other electrode of the capacitance element. On the other hand, when the polarization is negative, it indicates that the negative charge in the ferroelectric is biased toward one electrode of the capacitance element, and the positive charge is biased toward the other electrode of the capacitance element.

[0061] In addition, the polarization shown on the vertical axis of the graph in Figure 2 may be positive when negative charges are biased toward one electrode side of the capacitance element and positive charges are biased toward the other electrode side of the capacitance element, and may be negative when positive charges are biased toward one electrode side of the capacitance element and negative charges are biased toward the other electrode side of the capacitance element.

[0062] As shown in Fig. 2, the hysteresis characteristics of a ferroelectric material can be expressed by curve cv1 and curve cv2. The voltages at the intersections of curve cv1 and curve cv2 are referred to as the saturated polarization voltage +VSP (also referred to as "+VSP") and the saturated polarization voltage -VSP (also referred to as "-VSP"). +VSP and -VSP can be said to have opposite polarities.

[0063] When a voltage equal to or less than -VSP is applied to a ferroelectric, and then the voltage applied to the ferroelectric is increased, the polarization of the ferroelectric changes according to curve cv1. On the other hand, when a voltage equal to or greater than +VSP is applied to a ferroelectric, and then the voltage applied to the ferroelectric is decreased, the polarization of the ferroelectric changes according to curve cv2. Note that +VSP may be referred to as a "positive saturation polarization voltage" or a "first saturation polarization voltage." Furthermore, -VSP may be referred to as a "negative saturation polarization voltage" or a "second saturation polarization voltage." The absolute values ​​of the first saturation polarization voltage and the second saturation polarization voltage may be the same or different.

[0064] When the absolute value of the first saturated polarization voltage and the absolute value of the second saturated polarization voltage are the same, the absolute value may be referred to as the saturated polarization voltage VSP (also referred to as "VSP"). When the absolute value of the first saturated polarization voltage and the absolute value of the second saturated polarization voltage are different, the voltage with the larger absolute value may be referred to as the saturated polarization voltage VSP (also referred to as "VSP").

[0065] When the polarization of a ferroelectric changes according to the curve cv1, the voltage at which the polarization becomes 0 is referred to as the coercive voltage +Vc. Furthermore, when the polarization of a ferroelectric changes according to the curve cv2, the voltage at which the polarization becomes 0 is referred to as the coercive voltage -Vc. The values ​​of +Vc and -Vc are between +VSP and -VSP. Note that +Vc may be referred to as the "positive coercive voltage" or "first coercive voltage," and -Vc may be referred to as the "negative coercive voltage" or "second coercive voltage." The absolute values ​​of the first coercive voltage and the second coercive voltage may be the same or different.

[0066] Furthermore, when no voltage is applied to the ferroelectric (when the voltage is 0 V), the maximum value of polarization is denoted as "residual polarization +Pr" or "residual polarization Pr1," and the minimum value is denoted as "residual polarization -Pr" or "residual polarization Pr2." The capacitance value of the ferroelectric capacitor according to the present embodiment and the like is assumed to be larger when the remnant polarization of the dielectric is -Pr than when the remnant polarization is +Pr.

[0067] The absolute value of the difference between the remanent polarization +Pr and the remanent polarization -Pr is referred to as "remanent polarization 2Pr." The larger the remanent polarization 2Pr, the larger the fluctuation range of the capacitance value of the ferroelectric capacitor due to polarization reversal. The larger the remanent polarization 2Pr, the more preferable it is.

[0068] [Operation Example 1] Next, an example of a method for driving the semiconductor device 100 will be described with reference to the timing chart shown in FIG. 1B and the circuit diagrams shown in FIGS. 3A to 5B.

[0069] Here, as an example, we will explain the case where data is read and data is written back (here, this means reading data and then writing the same data) from a memory cell MC11 in which data "0" is stored and a memory cell MC12 in which data "1" is stored.

[0070] The potential of the signal applied to each of the wirings WL1 and WL2 is either a potential L (sometimes simply referred to as "L") or a potential H (sometimes simply referred to as "H") that is higher than the potential L. The potential L is a potential that can turn off the transistor Tr, and the potential H is a potential that can turn on the transistor Tr.

[0071] The potential applied to each of the wirings PL1 and PL2 is either a potential Vcom (sometimes simply referred to as "Vcom") or a potential Vw (sometimes simply referred to as "Vw") that is higher than the potential Vcom. The potential Vcom can be a potential corresponding to data "0" and can be, for example, 0 V. The potential Vw can be a potential corresponding to data "1" and can be, for example, VSP or higher.

[0072] 1A, the wiring BL1 is connected to the sense amplifier SA1, and the wiring BL2 is connected to the sense amplifier SA2. The sense amplifier SA1 and the sense amplifier SA2 are each connected to a wiring SA_EN. When describing matters common to the respective sense amplifiers, they may be simply referred to as the sense amplifier SA.

[0073] Here, when a potential Vcom is applied to the wiring SA_EN, the sense amplifier SA is inactivated, and when a potential Vw is applied to the wiring SA_EN, the sense amplifier SA is activated. At this time, when the sense amplifier SA is inactivated, the wiring BL is floating. Furthermore, when the sense amplifier SA is activated, the potential Vcom or the potential Vw is output to the wiring BL by comparing the potential of the wiring BL immediately before the sense amplifier SA was activated with a reference potential Vref (sometimes simply referred to as "Vref"). Here, the reference potential Vref is a potential (also referred to as an intermediate potential) between the potential Vcom and the potential Vw.

[0074] In the description of the operation, when the potential changes, a rise time and a fall time may occur due to, for example, a load (parasitic capacitance and parasitic resistance) such as a wiring. Also, even if two different operations are shown to have the same timing, this does not necessarily mean that they are exactly the same timing. For example, even if there is a slight time difference due to signal delay in the wiring, they may be considered to have the same timing.

[0075] Furthermore, in the timing chart, even if each period is shown to have the same length in the drawing for ease of explanation, the time length of each period may be different.

[0076] 1B shows the potential of each wiring during each period of operation, with the potential of each wiring indicated by a solid line and the reference potential Vref indicated by a dashed line.

[0077] 3A to 5B show the state of the semiconductor device 100 at each time point during operation (such as the potential of each wiring and each node, the state of each transistor, and the current flowing through each wiring and each node). In this case, symbols indicating potential, such as "H," "L," "Vw," or "Vcom" (also referred to as potential symbols), may be enclosed in a box next to each wiring and each node. In particular, a change in potential may be indicated by a thicker box, and a floating state may be indicated by a dotted box. An "x" symbol may be placed over a transistor in an off state. In addition, dashed arrows may be used to indicate the direction of current flow (which may also be referred to as the direction of positive charge movement) or the state in which a potential is supplied along each wiring and each node. In particular, the thickness of the line may indicate the magnitude of the current value. In addition, an outline arrow indicating the direction of polarization may be placed next to each capacitor. In particular, when polarization reversal occurs, a bold white arrow may be added.

[0078] Immediately before the period T11, a potential L is applied to each of the wirings WL1 and WL2. Therefore, the transistors Tr11, Tr12, Tr21, and Tr22 are each in an off state. A potential Vcom is applied to each of the wirings PL1 and PL2. At this time, data "0" is stored in the memory cell MC11, and the remanent polarization of the capacitor Cfe11 is −Pr (corresponding to point pt12 in FIG. 2 ). Data "1" is stored in the memory cell MC12, and the remanent polarization of the capacitor Cfe12 is +Pr (corresponding to point pt11 in FIG. 2 ). A potential Vcom is applied to the wiring SA_EN. Therefore, the sense amplifiers SA1 and SA2 are each in an inactive state, and the wirings BL1 and BL2 are each floating. At this time, the wirings BL1 and BL2 are each precharged to the potential Vcom. Note that in the following description, unless otherwise specified, the immediately preceding states are maintained.

[0079] The state of the semiconductor device 100 at this time is shown in FIG. 3A.

[0080] In the period T11, the potential H is applied to the wiring WL1, thereby turning on the transistors Tr11 and Tr12.

[0081] At this time, the potential of the line BL1 is the potential Vcom, and the potential of the line PL1 is the potential Vcom, so that in the memory cell MC11, no voltage is applied to the capacitive element Cfe11, and therefore no voltage is applied to the ferroelectric of the capacitive element Cfe11, and the polarization remains at −Pr (corresponding to point pt12 in FIG. 2 ).

[0082] Furthermore, since the potential of the wiring BL2 is the potential Vcom and the potential of the wiring PL2 is the potential Vcom, no voltage is applied to the capacitance element Cfe12 in the memory cell MC12, and therefore no voltage is applied to the ferroelectric of the capacitance element Cfe12, and the polarization remains +Pr (corresponding to point pt11 in FIG. 2).

[0083] The state of the semiconductor device 100 at this time is shown in FIG. 3B.

[0084] In a period T12, a potential Vw is applied to each of the wirings PL1 and PL2.

[0085] At this time, since the potential of the wiring BL1 is the potential Vcom and the potential of the wiring PL1 is the potential Vw, "potential Vcom - potential Vw" is applied to the capacitance element Cfe11 in the memory cell MC11. Therefore, a voltage equal to or lower than -VSP is applied to the ferroelectric of the capacitance element Cfe11, and the polarization changes slightly from -Pr to a value smaller than -Pr (corresponding to the change from point pt12 to point pt22 in FIG. 2). This causes a slight current to flow from one terminal of the capacitance element Cfe11 to the wiring BL1 via the transistor Tr11, slightly increasing the potential of the wiring BL1. Here, it is assumed that the potential of the wiring BL1 has increased to a potential smaller than the reference potential Vref.

[0086] Furthermore, since the potential of wiring BL2 is potential Vcom and the potential of wiring PL2 is potential Vw, "potential Vcom - potential Vw" is applied to capacitance element Cfe12 in memory cell MC12. Therefore, a voltage of -VSP or less is applied to the ferroelectric of capacitance element Cfe12, and polarization changes significantly from +Pr to a value smaller than -Pr (corresponding to the change from point pt11 to point pt22 in FIG. 2). As a result, a large current flows from one terminal of capacitance element Cfe12 to wiring BL2 via transistor Tr12, and the potential of wiring BL2 rises significantly. Here, it is assumed that the potential of wiring BL2 has risen to a potential greater than reference potential Vref.

[0087] Here, in the memory cell MC12, the operation of the period T12 reverses the polarization of the ferroelectric material of the capacitive element Cfe12. This destroys the data stored in the memory cell MC12. Therefore, after reading the data, it is necessary to write it back.

[0088] The state of the semiconductor device 100 at this time is shown in FIG. 4A.

[0089] In the period T13, the potential Vw is applied to the wiring SA_EN, so that the sense amplifier SA1 and the sense amplifier SA2 are activated.

[0090] At this time, just before the sense amplifier SA1 is activated, the potential of the wiring BL1 is lower than the reference potential Vref. Therefore, when the sense amplifier SA1 is activated, the data "0" stored in the memory cell MC11 can be read. In addition, the potential Vcom corresponding to the data "0" is output to the wiring BL1.

[0091] As a result, in memory cell MC11, potential Vcom is applied to one terminal of capacitance element Cfe11 from wiring BL1 via transistor Tr11. Also, potential Vw is applied to wiring PL1. Therefore, "potential Vcom - potential Vw" is applied to capacitance element Cfe11. Therefore, a voltage equal to or lower than -VSP is applied to the ferroelectric of capacitance element Cfe11, and polarization becomes a value smaller than -Pr (corresponding to point pt22 in FIG. 2). This allows data "0" to be written (also called written back) to memory cell MC11.

[0092] Immediately before the sense amplifier SA2 is activated, the potential of the wiring BL2 is higher than the reference potential Vref. Therefore, when the sense amplifier SA2 is activated, the data "1" stored in the memory cell MC12 can be read. Furthermore, a potential Vw corresponding to the data "1" is output to the wiring BL2.

[0093] As a result, in memory cell MC12, potential Vw is applied to one terminal of capacitance element Cfe12 from wiring BL2 via transistor Tr12. Furthermore, potential Vcom is applied to wiring PL2. Therefore, "potential Vw - potential Vcom" is applied to capacitance element Cfe12. Therefore, a voltage of +VSP or more is applied to the ferroelectric substance of capacitance element Cfe12, and the polarization becomes a value greater than +Pr (corresponding to point pt21 in FIG. 2). This allows data "1" to be written (also called written back) to memory cell MC12.

[0094] The state of the semiconductor device 100 at this time is shown in FIG. 4B.

[0095] In the period T14, the potential Vcom is applied to the wiring SA_EN. Therefore, the sense amplifiers SA1 and SA2 are inactivated. At this time, the wirings BL1 and BL2 are precharged to the potential Vcom. The potential Vcom is also applied to the wirings PL1 and PL2.

[0096] At this time, the potential of the wiring BL1 is the potential Vcom, and the potential of the wiring PL1 is the potential Vcom, so that in the memory cell MC11, no voltage is applied to the capacitive element Cfe11, and therefore no voltage is applied to the ferroelectric of the capacitive element Cfe11, and the polarization becomes −Pr (corresponding to point pt12 in FIG. 2 ).

[0097] Furthermore, since the potential of the wiring BL2 is the potential Vcom and the potential of the wiring PL2 is the potential Vcom, no voltage is applied to the capacitance element Cfe12 in the memory cell MC12, so no voltage is applied to the ferroelectric of the capacitance element Cfe12, and the polarization becomes +Pr (corresponding to point pt11 in FIG. 2).

[0098] The state of the semiconductor device 100 at this time is shown in FIG. 5A.

[0099] After that, a potential L is applied to the wiring WL1. This turns off the transistors Tr11 and Tr12. This allows data "0" to be stored in the memory cell MC11. Furthermore, data "1" can be stored in the memory cell MC12.

[0100] The state of the semiconductor device 100 at this time is shown in FIG. 5B.

[0101] In one embodiment of the present invention, for example, by applying different potentials to the wiring PL1 and the wiring PL2 in the period T13, data "0" can be written to the memory cell MC11 and data "1" can be written to the memory cell MC12 simultaneously. In other words, there is no need to provide separate periods for writing data "1" and writing data "0". Therefore, the period for writing data can be shortened, and the operating speed can be improved.

[0102] Note that, as an example, the case where data is read and then written (i.e., written back) has been described here, but the same applies to the case where data is rewritten. In this case, for example, in the period T13, potentials corresponding to data to be written may be applied to the wirings BL1 and BL2 and to the wirings PL1 and PL2. In this case, for example, the data reading in the period T12 may be omitted.

[0103] 6 shows an example of a timing chart different from the above. As shown in FIG. 6, for example, in the period T14, the wirings PL1 and PL2 may be supplied with a potential Vw, and the wirings BL1 and BL2 may be precharged to the potential Vw. In this case, in the data storage period (corresponding to the period after the period T14 and the period before the period T11), the potentials of the wirings PL1, PL2, BL1, and BL2 are set to the potential Vw. Therefore, just before the period T11, the wirings PL1 and PL2 may be supplied with a potential Vcom, and the wirings BL1 and BL2 may be precharged to the potential Vcom.

[0104] [Operation Example 2] Next, another example of a method for driving the semiconductor device 100 will be described with reference to the timing chart shown in Fig. 7 and the circuit diagrams shown in Fig. 8A to Fig. 10B. Note that the above description can be referred to, and therefore the description may be omitted.

[0105] Immediately before the period T11, a potential L is applied to each of the wirings WL1 and WL2. Therefore, the transistors Tr11, Tr12, Tr21, and Tr22 are each in an off state. A potential Vcom is applied to each of the wirings PL1 and PL2. At this time, data "0" is stored in the memory cell MC11, and the remanent polarization of the capacitor Cfe11 is −Pr (corresponding to point pt12 in FIG. 2 ). Data "1" is stored in the memory cell MC12, and the remanent polarization of the capacitor Cfe12 is +Pr (corresponding to point pt11 in FIG. 2 ). A potential Vcom is applied to the wiring SA_EN. Therefore, the sense amplifiers SA1 and SA2 are each in an inactive state, and the wirings BL1 and BL2 are each floating. At this time, the wirings BL1 and BL2 are each precharged to the potential Vcom. Note that in the following description, unless otherwise specified, the immediately preceding states are maintained.

[0106] The state of the semiconductor device 100 at this time is shown in FIG. 8A.

[0107] In the period T11, the wirings BL1 and BL2 are precharged to a potential Vw.

[0108] The state of the semiconductor device 100 at this time is shown in FIG. 8B.

[0109] In a period T12, a potential H is applied to the wiring WL1, thereby turning on the transistors Tr11 and Tr12.

[0110] At this time, since the potential of the wiring BL1 is potential Vw and the potential of the wiring PL1 is potential Vcom, "potential Vw - potential Vcom" is applied to the capacitance element Cfe11 in the memory cell MC11. Therefore, a voltage of +VSP or more is applied to the ferroelectric of the capacitance element Cfe11, and the polarization changes significantly from -Pr to a value greater than +Pr (corresponding to the change from point pt12 to point pt21 in FIG. 2). As a result, a large current flows from the wiring BL1 to one terminal of the capacitance element Cfe11 via the transistor Tr11, and the potential of the wiring BL1 drops significantly. Here, it is assumed that the potential of the wiring BL1 drops to a potential smaller than the reference potential Vref.

[0111] Furthermore, since the potential of wiring BL2 is potential Vw and the potential of wiring PL2 is potential Vcom, "potential Vw - potential Vcom" is applied to capacitance element Cfe12 in memory cell MC12. Therefore, a voltage of +VSP or higher is applied to the ferroelectric of capacitance element Cfe12, causing a slight change in polarization from +Pr to a value greater than +Pr (corresponding to the change from point pt11 to point pt21 in FIG. 2). This causes a slight current to flow from wiring BL2 to one terminal of capacitance element Cfe12 via transistor Tr12, slightly lowering the potential of wiring BL2. Here, it is assumed that the potential of wiring BL2 has dropped to a potential greater than the reference potential Vref.

[0112] Here, in the memory cell MC11, the operation of the period T12 reverses the polarization of the ferroelectric material of the capacitive element Cfe11. This destroys the data stored in the memory cell MC11. Therefore, after reading the data, it is necessary to write it back.

[0113] The state of the semiconductor device 100 at this time is shown in FIG. 9A.

[0114] In the period T13, the potential Vw is applied to the wiring SA_EN, so that the sense amplifier SA1 and the sense amplifier SA2 are activated.

[0115] At this time, just before the sense amplifier SA1 is activated, the potential of the wiring BL1 is lower than the reference potential Vref. Therefore, when the sense amplifier SA1 is activated, the data "0" stored in the memory cell MC11 can be read. After the potential Vw is output to the wiring BL1, the potential Vcom corresponding to the data "0" is output.

[0116] As a result, in memory cell MC11, potential Vcom is applied to one terminal of capacitance element Cfe11 from wiring BL1 via transistor Tr11. Also, potential Vw is applied to wiring PL1. Therefore, "potential Vcom - potential Vw" is applied to capacitance element Cfe11. Therefore, a voltage equal to or lower than -VSP is applied to the ferroelectric of capacitance element Cfe11, and polarization becomes a value smaller than -Pr (corresponding to point pt22 in FIG. 2). This allows data "0" to be written (also called written back) to memory cell MC11.

[0117] Immediately before the sense amplifier SA2 is activated, the potential of the wiring BL2 is higher than the reference potential Vref. Therefore, when the sense amplifier SA2 is activated, the data "1" stored in the memory cell MC12 can be read. After the potential Vw is output to the wiring BL2, the potential Vw corresponding to the data "1" is output.

[0118] As a result, in memory cell MC12, potential Vw is applied to one terminal of capacitance element Cfe12 from wiring BL2 via transistor Tr12. Furthermore, potential Vcom is applied to wiring PL2. Therefore, "potential Vw - potential Vcom" is applied to capacitance element Cfe12. Therefore, a voltage of +VSP or more is applied to the ferroelectric substance of capacitance element Cfe12, and the polarization becomes a value greater than +Pr (corresponding to point pt21 in FIG. 2). This allows data "1" to be written (also called written back) to memory cell MC12.

[0119] The state of the semiconductor device 100 at this time is shown in FIG. 9B.

[0120] In the period T14, the potential Vcom is applied to the wiring SA_EN. Therefore, the sense amplifiers SA1 and SA2 are inactivated. At this time, the wirings BL1 and BL2 are precharged to the potential Vw. The potential Vw is also applied to the wirings PL1 and PL2.

[0121] At this time, the potential of the line BL1 is the potential Vw, and the potential of the line PL1 is the potential Vw, so that in the memory cell MC11, no voltage is applied to the capacitive element Cfe11, and therefore no voltage is applied to the ferroelectric of the capacitive element Cfe11, and the polarization becomes −Pr (corresponding to point pt12 in FIG. 2 ).

[0122] Furthermore, since the potential of the wiring BL2 is the potential Vw and the potential of the wiring PL2 is the potential Vw, no voltage is applied to the capacitance element Cfe12 in the memory cell MC12, so no voltage is applied to the ferroelectric of the capacitance element Cfe12, and the polarization becomes +Pr (corresponding to point pt11 in FIG. 2).

[0123] The state of the semiconductor device 100 at this time is shown in FIG. 10A.

[0124] After that, a potential L is applied to the wiring WL1. As a result, the transistors Tr11 and Tr12 are turned off. The wirings BL1 and BL2 are precharged to the potential Vcom, and the potential Vcom is applied to the wirings PL1 and PL2. This allows data "0" to be stored in the memory cell MC11. Furthermore, data "1" can be stored in the memory cell MC12.

[0125] The state of the semiconductor device 100 at this time is shown in FIG. 10B.

[0126] In one embodiment of the present invention, for example, by applying different potentials to the wiring PL1 and the wiring PL2 in the period T13, data "0" can be written to the memory cell MC11 and data "1" can be written to the memory cell MC12 simultaneously. In other words, there is no need to provide separate periods for writing data "1" and writing data "0". Therefore, the period for writing data can be shortened, and the operating speed can be improved.

[0127] Note that, as an example, the case where data is read and then written (i.e., written back) has been described here, but the same applies to the case where data is rewritten. In this case, in the period T13, potentials corresponding to data to be written may be applied to the wirings BL1 and BL2 and to the wirings PL1 and PL2. In this case, for example, the data reading in the period T12 may be omitted.

[0128] 11 shows an example of a timing chart different from the above. As shown in FIG. 11, for example, in the period T14, the potential Vcom may be applied to the wirings PL1 and PL2, and the wirings BL1 and BL2 may be precharged to the potential Vcom.

[0129] [PL Line Driver] One embodiment of the present invention is a structure in which a potential applied to a wiring PL can be controlled for each column in the semiconductor device 100. Therefore, outside the semiconductor device 100, a circuit (here, also referred to as a PL line driver or a PL line driver circuit) that controls a potential applied to the wiring PL in accordance with data to be written to a memory cell MC can be provided for each column.

[0130] 12A and 12B are circuit diagrams illustrating a PL line driver. FIG. 12A illustrates a semiconductor device 100 and a sense amplifier and PL line driver provided externally to the semiconductor device 100. The semiconductor device 100 and the sense amplifier and PL line driver provided externally to the semiconductor device 100 may be collectively referred to as a semiconductor device 110. FIG. 12A illustrates, as a representative example, memory cells MC11, MC12, MC21, and MC22 included in the semiconductor device 100, wirings WL1 and WL2, wirings BL1 and BL2, and wirings PL1 and PL2. Also illustrated are a sense amplifier SA1 connected to wiring BL1, a sense amplifier SA2 connected to wiring BL2, a PL line driver PLD1 connected to wirings BL1 and PL1, and a PL line driver PLD2 connected to wirings BL2 and PL2. 12A, the sense amplifier SA1, the sense amplifier SA2, the PL line driver PLD1, and the PL line driver PLD2 are each connected to a wiring SA_EN. The PL line driver PLD1 and the PL line driver PLD2 are each connected to a wiring PL0. When describing matters common to each PL line driver, they may be simply referred to as PL line driver PLD.

[0131] Each of the sense amplifiers SA1 and SA2 may be configured using an inverter loop as shown in Fig. 12A, or may be configured using a comparator as shown in Fig. 13. Furthermore, without being limited to these, various configurations that can realize the above-described operation example may be used.

[0132] The PL line driver PLD has a function of outputting a potential Vw to the wiring PL, for example, during a data read period (corresponding to the above-described period T12). The PL line driver PLD also has a function of outputting a potential obtained by inverting the logical value of the potential of the wiring BL to the wiring PL, for example, during a data write period (corresponding to the above-described period T13). The PL line driver PLD also has a function of outputting a potential Vcom to the wiring PL, for example, during periods other than the above.

[0133] 12B is a circuit diagram showing an example configuration of the PL line driver PLD. As shown in FIG. 12B, the PL line driver PLD calculates, for example, a non-conjunction between the logical value of the potential of the wiring SA_EN and the logical value of the potential of the wiring BL, and then calculates a logical product of the logical value of the result of this non-conjunction and the logical value of the potential of the wiring PL0. A potential corresponding to the logical value of the result of this logical product is output to the wiring PL. At this time, a potential Vw is applied to the wiring PL0 during periods in which data is read and written (corresponding to the above-described periods T12 and T13), and a potential Vcom is applied during periods other than those periods.

[0134] 12B is just an example, and the configuration of the PL line driver that can be used in the semiconductor device of one embodiment of the present invention is not limited to this. As shown in the above-described operation example, the PL line driver PLD can have various configurations that can control the potential applied to the wiring PL in accordance with data written to the memory cell MC.

[0135] <Structure Example of Memory Device> A memory device including a memory cell of one embodiment of the present invention will be described.

[0136] 14 is a block diagram illustrating an example of the configuration of a storage device 700. The storage device 700 shown in FIG.

[0137] The memory array 721 has a plurality of memory cells 741. The plurality of memory cells 741 are arranged in a matrix of M rows and N columns, where M is an integer equal to or greater than 1, and N is an integer equal to or greater than 1.

[0138] In Figure 14, as representative examples, memory cell 741[1,1] arranged in the first row and first column, memory cell 741[1,N] arranged in the first row and Nth column, memory cell 741[M,1] arranged in the Mth row and first column, and memory cell 741[M,N] arranged in the Mth row and Nth column are shown.

[0139] In addition, Figure 14 illustrates, as representative examples, wiring WL[1] connected to N memory cells 741 arranged in the first row, wiring WL[M] connected to N memory cells 741 arranged in the Mth row, wiring BL[1] connected to M memory cells 741 arranged in the first column, wiring BL[N] connected to M memory cells 741 arranged in the Nth column, wiring PL[1] connected to M memory cells 741 arranged in the first column, and wiring PL[N] connected to M memory cells 741 arranged in the Nth column.

[0140] Therefore, the memory device 700 has M x N memory cells 741, and each memory cell 741 is connected to one of M wirings WL (wirings WL[1] to WL[M]) that function as word lines, one of N wirings BL (wirings BL[1] to BL[N]) that function as bit lines, and one of N wirings PL (wirings PL[1] to PL[N]) that function as plate lines.

[0141] That is, N memory cells 741 are connected to each of the wirings WL[1] to WL[M]. M memory cells 741 are connected to each of the wirings BL[1] to BL[N]. M memory cells 741 are connected to each of the wirings PL[1] to PL[N]. In other words, it can be said that the memory cells 741[m,1] to 741[m,N] connected to the wiring WL[m] on the m-th row (m is an integer greater than or equal to 1 and less than or equal to M) are connected to the wirings BL[1] to BL[N] in a one-to-one relationship. It can also be said that the memory cells 741[m,1] to 741[m,N] connected to the wiring WL[m] on the m-th row are connected to the wirings PL[1] to PL[N] in a one-to-one relationship. It can also be said that the memory cells 741[1,n] to 741[M,n] connected to the wirings BL[n] and PL[n] in the nth column (n is an integer greater than or equal to 1 and less than or equal to N) are connected one-to-one to the wirings WL[1] to WL[M].

[0142] Here, the memory array 721 corresponds to the semiconductor device 100 described above, and the memory cell 741 corresponds to the memory cell MC described above.

[0143] The drive circuit 722 includes a power switch 761, a power switch 762, and a peripheral circuit 771. The peripheral circuit 771 includes a peripheral circuit 781, a control circuit 772, and a voltage generation circuit 773.

[0144] In one embodiment of the present invention, for example, a Si transistor can be used as a transistor included in the driver circuit 722. Therefore, for example, a CMOS circuit (e.g., a circuit operating complementarily, a CMOS logic gate, or a CMOS logic circuit) formed by connecting the gate of an n-channel Si transistor and the gate of a p-channel Si transistor can be used as the driver circuit 722.

[0145] Here, for example, by using OS transistors as transistors constituting the memory cells 741, the memory array 721 can be stacked on the driver circuit 722 that uses Si transistors. This allows the memory device 700 to be miniaturized. Furthermore, multiple memory arrays 721 can be stacked. This allows the memory density of the memory device 700 to be improved. Furthermore, the wiring distance between the driver circuit 722 and the memory array 721 can be shortened. This allows at least one of an improvement in the read speed and an improvement in the write speed of the memory device 700 to be achieved.

[0146] For example, a signal is supplied to each of the terminal BW, terminal CE, terminal GW, terminal MCK, terminal WAKE, terminal ADDR, terminal WDA, terminal PON1, and terminal PON2 from outside the storage device 700. In addition, for example, a signal is output from the terminal RDA to outside the storage device 700.

[0147] For example, a clock signal is applied to terminal MCK. Furthermore, a control signal is applied to each of terminal BW, terminal CE, and terminal GW. A chip enable signal is applied to terminal CE. A global write enable signal is applied to terminal GW. A byte write enable signal is applied to terminal BW. An address signal is applied to terminal ADDR. Write data is applied to terminal WDA. Read data is applied to terminal RDA. A power gating control signal is applied to terminals PON1 and PON2. The signals applied to terminals PON1 and PON2 may be generated by, for example, control circuit 772.

[0148] The control circuit 772 has a function of controlling the operation of the memory device 700. The control circuit 772 has a function of performing a logical operation on signals provided to the terminals CE, GW, and BW, respectively, to determine an operation mode (e.g., a write operation or a read operation) of the memory device 700. The control circuit 772 also has a function of generating a signal that controls the peripheral circuit 781 so that the operation mode is executed.

[0149] The voltage generation circuit 773 has a function of generating an arbitrary potential for operating the driver circuit 722. For example, the voltage generation circuit 773 has a function of generating an arbitrary potential by inputting a clock signal provided to a terminal MCK in accordance with a signal provided to a terminal WAKE. For example, a signal that controls whether or not the clock signal provided to the terminal MCK is input to the voltage generation circuit 773 is provided to the terminal WAKE.

[0150] The peripheral circuit 781 has a function of writing and reading data to and from the memory cells 741. The peripheral circuit 781 has a function of generating various signals for controlling the operation of the memory cells 741, etc. The peripheral circuit 781 has a row decoder 782, a column decoder 784, a row driver 783, a column driver 789, an input circuit 787, and an output circuit 788.

[0151] The row decoder 782 and the column decoder 784 have the function of decoding an address signal applied to the terminal ADDR. The row decoder 782 has the function of specifying a row to be accessed. The column decoder 784 has the function of specifying a column to be accessed. The row driver 783 has the function of selecting a row specified by the row decoder 782 and applying a desired signal to, for example, the corresponding memory cell 741. The column driver 789 has the function of selecting a column specified by the column decoder 784 and applying a desired signal to, for example, the corresponding memory cell 741.

[0152] The column driver 789 also has a function of writing and reading data to and from the memory cell 741 selected by the row driver 783. The input circuit 787 has a function of holding data provided to a terminal WDA from outside the memory device 700. The data (data Din) held in the input circuit 787 is written to the memory cell 741 via the column driver 789. The data stored in the memory cell 741 is read out to the output circuit 788 via the column driver 789. The output circuit 788 has a function of holding the read data (data Dout). The output circuit 788 also has a function of outputting the held data from a terminal RDA to outside the memory device 700.

[0153] The column driver 789 includes a sense amplifier unit 785 and a PL line driver unit 786. The sense amplifier unit 785 includes, for example, N sense amplifiers. Each of the N sense amplifiers is connected to a corresponding one of the wirings BL[1] to BL[N]. The PL line driver unit includes, for example, N PL line drivers. Each of the N PL line drivers is connected to a corresponding one of the wirings BL[1] to BL[N] and a corresponding one of the wirings PL[1] to PL[N].

[0154] Here, each of the N sense amplifiers corresponds to the above-mentioned sense amplifier SA, and each of the N PL line drivers corresponds to the above-mentioned PL line driver PLD.

[0155] In the memory device 700 shown in Figure 14, for example, the row driver 783 has a function of supplying desired signals to the wirings WL[1] to WL[M], and the column driver 789 has a function of exchanging data with the wirings BL[1] to BL[N].

[0156] The power switch 761 has a function of controlling whether or not the potential applied to the terminal VMD is supplied to the peripheral circuit 771. The power switch 762 has a function of controlling whether or not the potential applied to the terminal VMH is supplied to the row driver 783. Here, for example, a high power supply potential (e.g., potential VDD) for operating the drive circuit 722 is applied to the terminal VMD, and a low power supply potential (e.g., potential VSS) is applied to the terminal VMS. Also, for example, a high power supply potential (e.g., a potential higher than potential VDD) for operating the memory cell 741 and the like is applied to the terminal VMH. The power switch 761 is controlled to a conductive state or a non-conductive state by a signal applied to the terminal PON1. The power switch 762 is controlled to a conductive state or a non-conductive state by a signal applied to the terminal PON2.

[0157] Here, it is preferable to use transistors with small off-state current as each of the power switches 761 and 762. This can reduce the current that flows through the power switches when the power switches are turned off, for example, and therefore reduce power consumption in the power-off state. It is also preferable to use transistors with large on-state current as each of the power switches 761 and 762. This can reduce loss when the power switches are turned on, for example, and therefore reduce power consumption in the power-on state.

[0158] As a transistor with low off-state current, for example, an OS transistor may be used for each of the power switches 761 and 762. Various oxide semiconductors can be used for the OS transistor. In particular, it is preferable to use an oxide semiconductor that has low off-state current and high on-state current. Examples of oxide semiconductors that have low off-state current and high on-state current include indium oxide. Details of oxide semiconductors that can be used for OS transistors will be described later. Indium oxide, which is one of oxide semiconductors, will also be described in detail in Embodiment 3.

[0159] Note that the circuits and terminals of the driver circuit 722 may be omitted as appropriate. Other circuits and terminals may be added as appropriate.

[0160] <Semiconductor Layer of Transistor> An OS transistor can be used in the semiconductor device and the memory device of one embodiment of the present invention. The OS transistor includes a metal oxide (also referred to as an oxide semiconductor) functioning as a semiconductor in a semiconductor layer including a channel formation region.

[0161] An OS transistor has an oxygen vacancy (V Ｏ ) and impurities, the electrical characteristics are likely to fluctuate and reliability may be reduced. Ｏ H) and generate electrons that serve as carriers. Therefore, if the channel formation region in the metal oxide contains oxygen vacancies, the OS transistor is likely to have normally-on characteristics. Therefore, it is preferable that the oxygen vacancies and impurities are reduced as much as possible in the channel formation region in the metal oxide. In other words, it is preferable that the carrier concentration in the channel formation region in the metal oxide is reduced and the channel formation region in the metal oxide is made i-type (intrinsic) or substantially i-type.

[0162] On the other hand, the source and drain regions of an OS transistor have more oxygen vacancies than the channel formation region. ＯThe source and drain regions of an OS transistor are preferably n-type regions having a high carrier concentration and low resistance, as compared with a channel formation region, due to a high concentration of H or an impurity such as hydrogen, nitrogen, or a metal element.

[0163] The band gap of a metal oxide functioning as a semiconductor is preferably 2.0 eV or more, more preferably 2.5 eV or more. By using a metal oxide with a wide band gap for a semiconductor layer, the off-state current of a transistor can be reduced. Because the off-state current of an OS transistor is small, the power consumption of a semiconductor device can be sufficiently reduced. Furthermore, because the frequency characteristics of an OS transistor are high, the semiconductor device can operate at high speed.

[0164] A metal oxide that can be used for the semiconductor layer of an OS transistor preferably contains at least indium (In). The metal oxide preferably contains at least indium (In) or zinc (Zn). The metal oxide preferably contains two or three elements selected from indium, an element M, and zinc. The element M is a metal element or a metalloid element that has a high bond energy with oxygen, for example, a metal element or a metalloid element that has a higher bond energy with oxygen than indium. For example, an example of a metal oxide that can be used for the semiconductor layer of an OS transistor is indium oxide (In oxide). Examples of the metal oxide include zinc oxide (Zn oxide), indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide), gallium zinc oxide (Ga-Zn oxide, also referred to as "GZO"), aluminum zinc oxide (Al-Zn oxide, also referred to as "AZO"), and indium aluminum. Examples of usable materials include indium zinc oxide (In-Al-Zn oxide, also referred to as "IAZO"), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as "IGZO"), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as "IGZTO"), and indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as "IGAZO" or "IAGZO"). Alternatively, silicon-containing indium tin oxide, gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), and the like can be used.

[0165] Examples of the crystalline structure of metal oxides that function as semiconductors include amorphous (including completely amorphous), c-axis-aligned crystalline line (CAAC), nanocrystalline line (nc), cloud-aligned composite (CAC), single crystal, and polycrystalline.

[0166] Furthermore, by increasing the ratio of the number of zinc atoms to the total number of atoms of the metal elements among the main component elements contained in the metal oxide, the metal oxide can be made highly crystalline, and the diffusion of impurities in the metal oxide can be suppressed, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0167] Furthermore, by increasing the ratio of the number of atoms of element M to the sum of the number of atoms of metal elements among the main component elements contained in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies can be suppressed, and a transistor with a small off-state current can be obtained. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.

[0168] By increasing the ratio of the number of indium atoms to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the field-effect mobility of the transistor can be increased. Typically, by using single-crystal or polycrystalline indium oxide for the semiconductor layer, the field-effect mobility of the transistor can be significantly increased. Furthermore, a transistor using single-crystal or polycrystalline indium oxide for the semiconductor layer can achieve good frequency characteristics.

[0169] Note that a transistor including a channel formation region made of another semiconductor material may be used in the semiconductor device and the memory device of one embodiment of the present invention. Examples of the other semiconductor material include a semiconductor made of a single element or a compound semiconductor.

[0170] Examples of semiconductors made of elemental elements that can be used as semiconductor materials include silicon and germanium. Examples of silicon that can be used as semiconductor materials include single-crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low-temperature polysilicon (LTPS).

[0171] Compound semiconductors that can be used for the semiconductor material include silicon carbide, silicon germanium, gallium arsenide, indium phosphide, boron nitride, and boron arsenide. Boron nitride that can be used for the semiconductor layer preferably has an amorphous structure. Boron arsenide that can be used for the semiconductor layer preferably has a cubic crystal structure. Other examples of compound semiconductors include organic semiconductors and nitride semiconductors. The aforementioned metal oxides are also a type of compound semiconductor. These semiconductor materials may contain impurities as dopants.

[0172] Further, a transistor in which a layer substance functioning as a semiconductor is used for a channel formation region may be applied to the semiconductor device and the memory device of one embodiment of the present invention.

[0173] Note that one embodiment of the present invention is not limited to the configuration examples, operation examples, and the like described in this embodiment. The contents of this embodiment can be implemented by combining them as appropriate. The contents of this embodiment can also be implemented by combining them as appropriate with other embodiments, etc.

[0174] In this embodiment, a memory device which is a semiconductor device of one embodiment of the present invention will be described. At least part of the memory device can be applied to the semiconductor device 100 described in Embodiment 1.

[0175] <Configuration example of memory device> Figures 15 to 19 show configuration examples of the memory device. Figure 15 is a schematic perspective view of the memory device SCD. Figure 16A is a top view of the memory device SCD. Figure 16B is a top view showing some components of the memory device SCD by dotted lines. Figure 17 is a cross-sectional view corresponding to the dashed-dotted line A1-A2 shown in Figures 16A and 16B. Figure 18 is a cross-sectional view corresponding to the dashed-dotted line B1-B2 shown in Figures 16A and 16B. Figure 19 is a cross-sectional view corresponding to the dashed-dotted line C1-C2 shown in Figures 16A and 16B.

[0176] 15 to 19, the direction in which the conductive layer ME1 (wiring WL) extends is the X direction. The direction in which the conductive layer ME3 (wiring BL) and the conductive layer ME6 (wiring PL) extend is the Y direction. The direction perpendicular to the X and Y directions is the Z direction. The X and Y directions can be perpendicular to each other. In the explanation of the top views in FIGS. 16A and 16B, the right side may be referred to as the +X direction, the left side as the −X direction, the upper side as the +Y direction, and the lower side as the −Y direction. In the explanation of the cross-sectional views in FIGS. 17 to 19, the upper side may be referred to as the +Z direction and the lower side as the −Z direction.

[0177] 15 shows only some conductive layers, insulating layers, and semiconductor layers in order to clearly show the configuration of the memory device SCD. Also, in the top view shown in FIG. 16B, the conductive layer ME6 (wiring PL) is shown by a dotted line in order to clearly show the configuration of the memory device SCD.

[0178] The memory device SCD has a substrate BS, a transistor TR formed on the substrate BS, and a capacitance element CFE and a capacitance element DCF located above the transistor TR. Specifically, the memory device SCD has a memory cell MEM, and the memory cell MEM has a transistor TR and a capacitance element CFE.

[0179] Here, for example, the X direction can be said to be a direction along the top surface of the substrate BS, the Y direction can be said to be a direction that intersects with the X direction and is along the top surface of the substrate BS, and the Z direction can be said to be a direction that intersects with the top surface of the substrate BS.

[0180] In addition, in the perspective schematic diagram shown in FIG. 15, some of the components may be omitted in order to clearly show the internal configurations of the transistor TR, the capacitance element CFE, and the capacitance element DCF.

[0181] The memory cell MEM is a storage circuit having one transistor and one capacitance element, and has a DRAM configuration. Furthermore, by using a material that can have ferroelectricity as the dielectric of the capacitance element, the capacitance element can be made into a ferroelectric capacitor, and the memory cell MEM can have an FeRAM configuration.

[0182] The memory device SCD has conductive layers ME1, ME2, ME3, ME4, ME5, ME6, insulating layers GI1, UI1, UI2, UI3, IS1, IS2, IS3, IS4, BI1, BI2, and FDI. Note that some of the components listed above may also be included in the transistor TR, the capacitance element CFE, or the capacitance element DCF.

[0183] As an example, a semiconductor substrate (single crystal made of silicon, germanium, or the like) can be used as the substrate BS. Note that in this specification and the like, the substrate BS will be described as being a single crystal substrate made of silicon.

[0184] The transistor TR will now be described. The transistor TR is a transistor formed on a substrate BS, and a transistor region TA (sometimes referred to as an element formation region) is formed by forming an element isolation layer ST (sometimes referred to as an element isolation region) in the substrate BS. Two trenches MZ are formed in each transistor region TA, and the two trenches MZ divide the low-resistance region included in the transistor region TA of the substrate BS into three. In FIG. 17, the respective low-resistance regions are shown as low-resistance region LRa, low-resistance region LRb, and low-resistance region LRc. In addition, semiconductor regions SEAb and SEAc are formed in the substrate BS corresponding to the inner walls and bottoms of the two trenches MZ. In other words, one of the two trenches MZ overlaps with at least a portion of the semiconductor region SEAb, and the other of the two trenches MZ overlaps with at least a portion of the semiconductor region SEAc. The semiconductor regions SEAb and SEAc may also be referred to as channel formation regions.

[0185] That is, the transistor TR has a semiconductor region SEAb (or semiconductor region SEAc) that is U-shaped in cross section, and a low-resistance region LRa and a low-resistance region LRb (or low-resistance region LRc) that face each other via the trench portion MZ in top or cross section. As described above, two transistors TR can be formed in the transistor region TA.

[0186] An insulating layer GI1 is located on the substrate BS corresponding to the inner wall and bottom of the trench portion MZ. Furthermore, a conductive layer ME1 is located in a region of the trench portion MZ facing the semiconductor region SEAb (or semiconductor region SEAc) with the insulating layer GI1 interposed therebetween. As shown in FIGS. 15 to 19 , the conductive layer ME1 is provided so as to extend in the X direction. Furthermore, as shown in FIGS. 17 and 19 , the conductive layer ME1 is provided so as to fill a portion of the bottom side (−Z direction side) of the trench portion MZ. Furthermore, the insulating layer UI1 is provided so as to fill the remaining trench portion MZ. Thus, in the trench portion MZ, the conductive layer ME1 has a region in contact with the insulating layer GI1 and a region in contact with the insulating layer UI1. Furthermore, the insulating layer UI1 has a region in contact with the conductive layer ME1 and a region in contact with the insulating layer GI1.

[0187] The insulating layer GI1 functions as a gate insulating film of the transistor TR and also functions as an insulating layer to prevent the low resistance region LRa and the low resistance region LRb (or the low resistance region LRc) from directly contacting each other.

[0188] The insulating layer GI1 may be made of, for example, silicon oxide, silicon nitride, or silicon oxynitride.

[0189] In this specification and the like, an oxynitride refers to a material whose composition contains more oxygen than nitrogen, and a nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0190] The conductive layer ME1 has a region that functions as the gate electrode of the transistor TR.

[0191] The conductive layer ME1 also has a region that functions as a wiring. For example, the conductive layer ME1 has a region that functions as the wiring WL described in the first embodiment. Note that in FIGS. 16A and 16B, etc., the conductive layer ME1 is also denoted in parentheses with a symbol WL[x]. Note that [x] indicates the ordinal number of the wiring. For example, in FIGS. 16A and 16B, the conductive layer ME1 having regions that function as gate electrodes of transistors TR in three different rows is denoted in parentheses with a wiring WL[1], a wiring WL[2], and a wiring WL[3]. However, in this specification and the like, [x] may not necessarily coincide with the row number or column number in the matrix.

[0192] In particular, in the memory device SCD, the conductive layer ME1 (wiring WL) has a region that functions as a word line.

[0193] In the conductive layer ME1, it is difficult to clearly separate the region that functions as the gate electrode of the transistor TR from the region that functions as wiring, and they may share the same region.

[0194] For example, the conductive layer ME1 may be made of a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, palladium, iridium, strontium, and lanthanum, or an alloy containing two or more of the above-mentioned metal elements, or an alloy combining two or more of the above-mentioned metal elements. For example, the conductive layer ME1 may be made of tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferable because they are conductive materials that are resistant to oxidation or materials that maintain conductivity even when absorbing oxygen. In addition, the conductive layer may be made of a semiconductor with high conductivity, typified by polycrystalline silicon containing an impurity element (e.g., phosphorus), or a silicide (e.g., nickel silicide).

[0195] By using a material with high conductivity (a material with low electrical resistance), the power consumption of the memory device SCD can be reduced. In addition, by using a material with high conductivity (a material with low electrical resistance), the amount of electric heat generated can be reduced, thereby reducing the effect of heat on the transistor TR.

[0196] A plurality of conductive layers formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-mentioned material containing a metal element and a conductive material containing oxygen. A stacked structure may also be formed by combining the above-mentioned material containing a metal element and a conductive material containing nitrogen. A stacked structure may also be formed by combining the above-mentioned material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0197] The materials listed above are merely examples, and it is preferable to select an appropriate material depending on the type of substrate used for the substrate BS. For example, if the substrate BS is a single-crystal substrate containing silicon, it is preferable to select a material for the conductive layer ME1 that does not contain metal elements that diffuse into the single-crystal substrate and degrade the electrical characteristics of the transistors formed on the substrate BS.

[0198] The insulating layer UI1 functions as a planarizing film that fills the grooves MZ and covers the uneven shape of the substrate BS. Similarly to the insulating layer GI1, the insulating layer UI1 also functions as an insulating layer that prevents the low resistance region LRa and the low resistance region LRb (or the low resistance region LRc) from directly contacting each other.

[0199] For example, the insulating layer UI1 can be made of silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon nitride. Alternatively, the insulating layer UI1 can be made of, for example, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, or silicon oxide having vacancies. Silicon oxide and silicon oxynitride are particularly preferred because they are thermally stable. Materials such as silicon oxide, silicon oxynitride, or silicon oxide having vacancies are particularly preferred because they can easily form regions containing oxygen that desorbs upon heating. The material used for the insulating layer UI1 may also be an appropriate combination of the insulating materials described above. For example, the insulating layer UI1 may have a single-layer structure selected from the above materials, or a stacked structure combining the above materials.

[0200] The low-resistance region LRa and the low-resistance region LRb (or the low-resistance region LRc) included in the transistor region TA function as source or drain regions in the transistor TR. For example, one of the two transistors TR included in the transistor region TA can be a transistor in which the low-resistance region LRa serves as one of the source or drain regions and the low-resistance region LRb serves as the other of the source or drain regions. Furthermore, for example, the other of the two transistors TR included in the transistor region TA can be a transistor in which the low-resistance region LRa serves as one of the source or drain regions and the low-resistance region LRc serves as the other of the source or drain regions.

[0201] Next, the element isolation layer ST will be described.

[0202] The element isolation layer ST functions as an insulating layer for electrically isolating adjacent transistor regions TA, for example. The element isolation layer ST may also be called an STI (Shallow Trench Isolation) region, an STI portion, or the like.

[0203] The element isolation layer ST includes, for example, an insulating layer UI2 and an insulating layer UI3. In addition, a conductive layer ME1 may be embedded in the element isolation layer ST.

[0204] The insulating layer UI2 functions as an insulating layer for electrically isolating adjacent transistor regions TA. The insulating layer UI2 also functions as an insulating layer for filling a part of a groove that is generated when multiple transistor regions TA are formed on the substrate BS. For these reasons, the insulating layer UI2 is located on the substrate BS, which corresponds to the inner wall of the groove.

[0205] The insulating layer UI2 can be made of the same material as that used for the insulating layer UI1.

[0206] 17 to 19, the conductive layer ME1 has a region that functions as a wiring. In FIG. 17, the conductive layer ME1 having a region that functions as the gate electrodes of the two transistors TR is indicated in parentheses as wiring WL[1] and wiring WL[2], and the conductive layer ME1 provided in the element isolation layer ST is indicated in parentheses as wiring WL[3].

[0207] Here, as shown in the top views of Figures 16A and 16B, the conductive layer ME1 provided in the element isolation layer ST of Figure 17 has a region that functions as a gate electrode of a transistor TR different from the transistor TR shown in Figure 17.

[0208] The conductive layer ME1 included in the element isolation layer ST can be formed in the same process as the conductive layer ME1 having a region that functions as the gate electrode of the transistor TR. Therefore, the conductive layer ME1 included in the element isolation layer ST and the conductive layer ME1 having a region that functions as the gate electrode of the transistor TR can be made of the same material.

[0209] Furthermore, the length in the depth direction (e.g., Z direction) of the conductive layer ME1 provided in the element isolation layer ST and the length in the depth direction of the conductive layer ME1 provided in the trench MZ in the transistor region TA may be the same or different. For example, the length in the depth direction of the conductive layer ME1 provided in the element isolation layer ST may be longer or shorter than the length in the depth direction of the conductive layer ME1 provided in the trench MZ in the transistor region TA. Furthermore, the length in the depth direction of the conductive layer ME1 provided in the element isolation layer ST is determined by the depth of the element isolation layer ST formed in the substrate BS, the film thickness of the insulating layer UI2, etc.

[0210] The insulating layer UI3 functions as a planarizing film that fills the grooves of the element isolation layer ST and covers the uneven shape of the substrate BS. Similarly to the insulating layer UI2, the insulating layer UI3 also functions as an insulating layer that prevents adjacent transistor regions TA from directly contacting each other.

[0211] Therefore, the insulating layer UI3 can be made of a material that can be used for the insulating layer UI1 or the insulating layer UI2.

[0212] An insulating layer IS1 and an insulating layer BI1 are formed in this order on the upper surfaces of the transistor region TA and the element isolation layer ST of the substrate BS.

[0213] The insulating layer IS1 functions as an interlayer film for arranging wiring, capacitive elements, etc. above the transistor TR. The insulating layer IS1 may be formed simultaneously with the insulating layer UI3. In other words, the insulating layer IS1 may function as a planarizing film that covers the uneven shape of the substrate BS.

[0214] The insulating layer IS1 can be made of the same material as the insulating layer UI1. In addition to the above, the insulating layer IS1 can also be made of a resin.

[0215] Furthermore, it is preferable to use a material with a low dielectric constant for the insulating layer IS1. By using a material with a low dielectric constant for the insulating layer IS1, the parasitic capacitance occurring between wirings (between conductive layers) can be reduced. For this reason, it is preferable to use one or more of the following materials with a low dielectric constant for the insulating layer IS1: silicon oxide, silicon oxynitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, and silicon oxide having vacancies.

[0216] In particular, silicon oxide and silicon oxynitride are preferred because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide having vacancies are preferred because they can easily form regions containing oxygen that is desorbed by heating.

[0217] The insulating layer BI1 functions as an insulating film that separates the transistor TR from a conductive layer, an insulating layer, etc. located above the insulating layer BI1. Specifically, the insulating layer BI1 functions as a barrier insulating film that suppresses the diffusion of impurities from above the insulating layer BI1 to the transistor TR. Examples of impurities include materials that degrade the electrical characteristics of the transistor TR. The insulating layer BI1 may also function as a barrier insulating film that suppresses the diffusion of oxygen to prevent the wiring from being oxidized and the electrical resistance of the wiring from increasing.

[0218] As a barrier insulating film having a function of suppressing oxygen permeation, for example, an insulator containing one or more elements selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum can be used, in a single layer or a stacked layer. Specifically, examples of insulators having a function of suppressing the permeation of impurities such as water and hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. Examples of insulators having a function of suppressing the permeation of impurities such as water and hydrogen and oxygen include oxides containing aluminum and hafnium (hafnium aluminate). Examples of insulators having a function of suppressing the permeation of impurities such as water and hydrogen and oxygen include nitrides such as aluminum nitride, aluminum titanium nitride, silicon nitride oxide, and silicon nitride. The above materials can suppress the diffusion of not only oxygen but also water or hydrogen.

[0219] The insulating layer IS1 and the insulating layer BI1 have a plurality of openings that reach the low-resistance regions LRa to LRc included in the transistor region TA of the substrate BS. Furthermore, a conductive layer ME2 that functions as a contact plug (sometimes simply referred to as a plug) is embedded in these openings. That is, the conductive layer ME2 can be said to be provided in an upper layer (here, corresponding to the layer in which the insulating layer IS1 and the insulating layer BI1 are located) above the layer in which the conductive layer ME1 is provided (here, corresponding to the layer in which the substrate BS and the like are located).

[0220] In particular, in this specification and the like, the conductive layer ME2 in contact with the low resistance region LRa may be referred to as a first plug, and the conductive layer ME2 in contact with the low resistance region LRb or low resistance region LRc may be referred to as a second plug.

[0221] The conductive layer ME2, which functions as a plug, can be made of one or more conductive materials selected from metal materials, alloy materials, nitride materials, and oxide materials, either as a single layer or as a laminate. It is preferable to use a high-melting-point material such as tungsten or molybdenum, which has both heat resistance and conductivity, and tungsten is preferred. Furthermore, it is preferable to use a low-resistance conductive material such as aluminum or copper as the material. Using a low-resistance conductive material can reduce the electrical resistance of the wiring.

[0222] Furthermore, the conductive layer ME2 can be made of a material that can be used for the conductive layer ME1.

[0223] A conductive layer ME3 is formed on the upper surfaces of the insulating layer BI1 and the conductive layer ME2. That is, the conductive layer ME3 can be said to be provided in a layer (corresponding to the layer where the insulating layer IS2 and the like are located here) above the layer where the conductive layer ME2 is provided (corresponding to the layer where the insulating layer IS1 and the insulating layer BI1 and the like are located here). Note that the conductive layer ME3 is provided so as to extend in the Y direction, as shown in FIGS. 15 to 19 .

[0224] The conductive layer ME3 has a region that functions as a wiring. For example, the conductive layer ME3 has a region that functions as the wiring BL described in the first embodiment. Note that in FIGS. 16A and 16B, etc., the conductive layer ME3 is also denoted with a symbol BL[x] in parentheses. Note that, like the conductive layer ME1, [x] indicates the ordinal number of the wiring. For example, in FIGS. 16A and 16B, the conductive layers ME3 in three different columns are denoted with a wiring BL[1], a wiring BL[2], and a wiring BL[3] in parentheses. However, in this specification and the like, like the conductive layer ME1, [x] may not necessarily coincide with the row number or column number in the matrix.

[0225] In particular, in the memory device SCD, the conductive layer ME3 (wiring BL) has a region that functions as a bit line.

[0226] The conductive layer ME3 is preferably made of a low-resistance material, similar to the wiring WL. As an example, the conductive layer ME3 may be made of a material that can be used for the conductive layer ME1 or ME2.

[0227] An insulating layer IS2 is formed on the upper surface of each of the insulating layer BI1 and the conductive layer ME3.

[0228] The insulating layer IS2 functions as an interlayer film, similar to the insulating layer IS1, and therefore, for example, the insulating layer IS2 can be made of a material that can be used for the insulating layer IS1.

[0229] Furthermore, the insulating layer IS2 has a plurality of openings that reach the insulating layer BI1 and the conductive layer ME2, which is a second plug. Furthermore, a conductive layer ME4 that functions as a plug is buried in these openings. In other words, it can be said that the conductive layer ME4 is provided in a layer (here, corresponding to the layer in which the insulating layer IS2, etc. are located) above the layer in which the conductive layer ME2 is provided (here, corresponding to the layer in which the insulating layer IS1, the insulating layer BI1, etc. are located).

[0230] In particular, in this specification and the like, the conductive layer ME4 in contact with the conductive layer ME2 functioning as the second plug may be referred to as a third plug.

[0231] As will be described in detail later, the conductive layer ME4 has an area that comes into contact with the conductive layer ME5 that will be formed later, and therefore functions as a lead wiring for providing electrical continuity between the conductive layer ME2 and the conductive layer ME5.

[0232] The conductive layer ME4 is preferably made of a low-resistance material, similar to the conductive layer ME2 having the function as a plug. As an example, the conductive layer ME4 can be made of a material that can be applied to the conductive layers ME1 to ME3.

[0233] An insulating layer BI2 and an insulating layer IS3 are formed in this order on the upper surfaces of the insulating layer IS2 and the conductive layer ME4, respectively.

[0234] Similar to the insulating layer BI1, the insulating layer BI2 functions as a barrier insulating film to suppress deterioration of the electrical characteristics of the transistor TR, oxidation of the conductive layer, etc. For this reason, the insulating layer BI2 can be made of a material that can be applied to the insulating layer BI1.

[0235] The insulating layer IS3 functions as an interlayer film, similar to the insulating layers IS1 and IS2, and therefore, for example, the insulating layer IS3 can be made of a material that can be used for the insulating layers IS1 and IS2.

[0236] The insulating layer BI2 and the insulating layer IS3 have a plurality of openings that reach the conductive layer ME4, which is the third plug. The bottom of each opening may also include a partial region of the insulating layer IS2.

[0237] Furthermore, a conductive layer ME5 having a columnar shape is formed so as to include the opening and extend parallel to the +Z direction. That is, the conductive layer ME5 can be said to be provided in an upper layer (corresponding to the layer where the insulating layer BI2, insulating layer IS3, insulating layer IS4, etc. are located here) above the layer where the conductive layers ME3 and ME4 are provided (corresponding to the layer where the insulating layer IS2, etc. are located here).

[0238] The bottom surface of the pillar may be circular, elliptical, curved (e.g., elliptical, cloud-shaped, triangle with rounded corners, polygonal such as square or pentagon, etc.), cornered (e.g., polygonal such as triangle, square or pentagon, etc.), or a combination of these shapes.

[0239] In this specification and the like, a columnar body refers to a structure having a shape with a high aspect ratio in a cross-sectional view. For example, the aspect ratio of the conductive layer ME5 in the cross-sectional views of FIGS. 17 and 18 refers to the ratio of the height H of the conductive layer ME5 (which can be referred to as the length H in a direction perpendicular to the surface on which the conductive layer ME5 is formed (e.g., the Z direction)) to the width L of the conductive layer ME5 (which can be referred to as the length L in a direction parallel to the surface on which the conductive layer ME5 is formed (e.g., the XY plane)). The aspect ratio of the conductive layer ME5 is preferably as large as possible without causing the conductive layer ME5 to collapse during the manufacturing process of the capacitive element CFE or the capacitive element DCF. In other words, the height H of the conductive layer ME5 is preferably greater than the width L of the conductive layer ME5 without causing the conductive layer ME5 to collapse.

[0240] In this specification and the like, a columnar body may be referred to as a pillar or the like. A columnar body or a pillar may have a tapered shape. In this specification and the like, a columnar body or a pillar having a tapered shape may be referred to as a truncated cone.

[0241] In this specification and the like, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined with respect to the substrate surface. Alternatively, it refers to a shape in which at least a portion of the side surface of a structure is inclined with respect to the film surface underlying the structure. The angle between the inclined side surface and the substrate surface or the film surface is referred to as the taper angle. In this specification and the like, a tapered shape having a taper angle greater than 0° and less than 90° is referred to as a forward taper shape, and a tapered shape having a taper angle greater than 90° and less than 180° is referred to as a reverse taper shape.

[0242] The conductive layer ME5 has a function as, for example, one of a pair of electrodes of the capacitance element CFE.

[0243] The conductive layer ME5 is preferably made of a low-resistance material, similar to, for example, the plugs, wiring, etc. As an example, the conductive layer ME5 can be made of a material that can be applied to the conductive layers ME1 to ME4.

[0244] Furthermore, the conductive layer ME5 can be formed, for example, by forming a sacrificial layer of the desired thickness on the upper surface of the insulating layer IS3, providing multiple openings in the sacrificial layer, the insulating layer IS3, and the insulating layer BI2 that reach the conductive layer ME4, burying the conductive layer ME5 in the multiple openings, and then removing the sacrificial layer.

[0245] An insulating layer FDI is formed on the upper surfaces of the insulating layer IS3 and the conductive layer ME5. In particular, the insulating layer FDI has a region that also contacts the side and upper surface of the conductive layer ME5, which is a columnar body. In addition, a conductive layer ME6 is formed on the upper surface of the insulating layer FDI. In particular, the conductive layer ME6 is formed so as to include a region that faces the conductive layer ME5 via the insulating layer FDI. In other words, it can be said that the insulating layer FDI includes a region that is provided so as to cover the conductive layer ME5, and the conductive layer ME6 includes a region that is provided so as to cover the insulating layer FDI.

[0246] The insulating layer FDI has, for example, a region that functions as a dielectric of the capacitive element CFE.

[0247] For example, the insulating layer FDI can be made of a material that functions as a dielectric. It is preferable to use, for example, a material with a high relative dielectric constant (high-k) as the dielectric. Specifically, for example, for the insulating layer FDI, a high-dielectric-constant material such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, or hafnium zirconium oxide can be used. Alternatively, as another example, it is preferable to use an oxide containing one or both of aluminum and hafnium, more preferably an oxide having an amorphous structure and containing one or both of aluminum and hafnium, and even more preferably hafnium oxide having an amorphous structure. Furthermore, as another example, lead zirconate titanate (PZT), strontium titanate (SrTiO ３ ), or (Ba,Sr)TiO ３By using a high dielectric constant material for the dielectric of the capacitance element CFE, the capacitance value can be increased, and the voltage written in the capacitance element CFE can be held for a long time.

[0248] Furthermore, a material capable of exhibiting ferroelectricity can be used for the insulating layer FDI. Furthermore, by using a material capable of exhibiting ferroelectricity for the insulating layer FDI, the capacitive element CFE can be made into a ferroelectric capacitor.

[0249] Materials that can have ferroelectricity include hafnium oxide, zirconium oxide, and hafnium zirconium oxide (HfZrO Ｘ (where X is a real number greater than 0), and the element J is added to hafnium oxide. １ (Element J here １ refers to one or more elements selected from zirconium (Zr), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), and strontium (Sr), and zirconium oxide is doped with element J. ２ (Element J here ２ Examples of materials that can have ferroelectricity include materials to which one or more elements selected from hafnium (Hf), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), and strontium (Sr) are added. Ｘ Piezoelectric ceramics having a perovskite structure, such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), and barium titanate, may also be used. Furthermore, as a material that can have ferroelectricity, for example, a mixture or compound of a plurality of materials selected from the materials listed above may be used. Incidentally, hafnium oxide, zirconium oxide, zirconium hafnium oxide, and hafnium oxide containing element J may be used. １The crystal structure (characteristics) of a material to which an ion beam is added may change depending not only on the film formation conditions but also on various processes. Therefore, in this specification and the like, a material that exhibits ferroelectricity is not only called a ferroelectric but also called a material that can have ferroelectricity.

[0250] Among these, materials that can have ferroelectricity, such as materials containing hafnium oxide or materials containing hafnium oxide and zirconium oxide, are preferred because they can have ferroelectricity even in thin films of a few nanometers. This allows the process of fabricating a ferroelectric capacitor to be shortened. In this specification and the like, a layer of a material that can have ferroelectricity may be referred to as a ferroelectric layer.

[0251] When the insulating layer FDI is formed by atomic layer deposition (ALD) using a material containing hafnium oxide and zirconium oxide, for example, tetrakis(ethylmethylamido)hafnium (TEMAHf) or hafnium tetrachloride can be used as a precursor containing hafnium. Furthermore, tetrakis(ethylmethylamido)zirconium (TEMAZr) or zirconium tetrachloride can be used as a precursor containing zirconium. Furthermore, H ２ O and O ３ However, the oxidizing agent is not limited to these. For example, O ２ , O ３ , N ２ O, NO ２ , H ２ O and H ２ O ２ It can include one or more selected from the following.

[0252] Furthermore, the insulating layer FDI can have a single layer structure or a laminated structure. In particular, when the insulating layer FDI has a laminated structure, each insulating layer included in the insulating layer FDI can be made of, for example, one or both of the above-mentioned high-k material and the above-mentioned material that can have ferroelectricity.

[0253] The thickness of the insulating layer FDI is preferably 1 nm or more and 30 nm or less, more preferably 2 nm or more and 20 nm or less, and even more preferably 3 nm or more and 15 nm or less.

[0254] Furthermore, unlike paraelectric materials, ferroelectric materials maintain their internal dielectric polarization even when no voltage is applied (sometimes called remanent polarization). Because the dielectric polarization is maintained, by using a ferroelectric capacitor as the capacitive element CFE, degradation of data stored in the memory cells MEM is suppressed. This allows for a reduction in refresh operations to the memory cells MEM, thereby reducing the power consumption of the storage device SCD.

[0255] The conductive layer ME6 has, for example, a region that functions as the other of the pair of electrodes of the capacitance element CFE.

[0256] As a result of the above, a capacitive element CFE can be formed in which a portion of the conductive layer ME5 serves as one of a pair of electrodes, a portion of the insulating layer FDI serves as a dielectric, and a portion of the conductive layer ME6 serves as the other of the pair of electrodes. Furthermore, by forming the conductive layer ME5 into a columnar body, the area of ​​the insulating layer FDI sandwiched between the pair of electrodes can be increased. This allows the threshold voltage distribution of data in the FeRAM to be increased, enabling the logic of "0" and "1" to be read accurately.

[0257] 15 to 19, the conductive layer ME6 is provided so as to extend in the Y direction. Furthermore, in order to provide the conductive layer ME6 so as to extend in the Y direction, in addition to the capacitive element CFE of the memory cell MEM, the memory device SCD is provided with dummy capacitive elements DCF arranged along the Y direction. Furthermore, in the top view shown in FIGS. 16A and 16B, the outer shape of the conductive layer ME6 is such that a plurality of shapes (e.g., circular shapes) that reflect the outer shape of the conductive layer ME5 are provided along the Y direction, and adjacent shapes partially overlap each other. For this reason, the conductive layer ME6 is sometimes referred to as a rosary-shaped wiring.

[0258] Furthermore, the conductive layer ME6 has a region that functions as a wiring. For example, the conductive layer ME6 has a region that functions as the wiring PL described in the first embodiment. Note that in FIGS. 16A and 16B, etc., the conductive layer ME6 is also denoted with the symbol PL[x] in parentheses. Note that, like the conductive layers ME1 and ME3, [x] indicates the ordinal number of the wiring. For example, in FIGS. 16A and 16B, the conductive layers ME6 in four different columns are denoted in parentheses as wiring PL[1], wiring PL[2], wiring PL[3], and wiring PL[4]. However, in this specification and the like, like the conductive layers ME1 and ME3, [x] may not necessarily coincide with the row number or column number in the matrix.

[0259] In particular, when the capacitance element CFE of the memory device SCD is a ferroelectric capacitor, the conductive layer ME6 (wiring PL) has a region that functions as a plate line.

[0260] When the memory device SCD is a DRAM instead of an FeRAM, the conductive layer ME6 (wiring PL) preferably has a function as a wiring for applying a constant potential.

[0261] Since the conductive layer ME6 functions as each of the wirings PL[1] to PL[4], it is necessary to electrically isolate adjacent wirings from each other. As a specific process, after forming a film that will become the conductive layer ME6 on the insulating layer FDI, regions of the film that will become the conductive layer ME6 that will be between the wirings may be removed by etching or the like so as to form each of the wirings PL[1] to PL[4].

[0262] The conductive layer ME6 is preferably made of a low-resistance material, similar to the conductive layers ME1 and ME3 that function as wirings. As an example, the conductive layer ME6 can be made of a material that can be applied to the conductive layers ME1 to ME5.

[0263] An insulating layer IS4 is formed on the upper surfaces of the insulating layer FDI and the conductive layer ME6.

[0264] The insulating layer IS4 functions as an interlayer film, similar to the insulating layers IS1 to IS4. Therefore, for the insulating layer IS4, for example, a material that can be applied to the insulating layers IS1 to IS3 can be used.

[0265] After the insulating layer IS4 is formed, the upper surface of the insulating layer IS4 may be planarized using chemical mechanical polishing (CMP). This allows further wiring, circuit elements, and the like to be formed above the insulating layer IS4. In this case, the memory device SCD can be treated as part of a monolithic stack configuration. For example, by providing a processing circuit, an arithmetic circuit, and the like above the memory device SCD, a novel semiconductor device can be realized in which data resulting from processing performed by the processing circuit, arithmetic circuit, and the like is temporarily stored in the memory device SCD.

[0266] Next, a description will be given of the dummy capacitance element DCF for providing the conductive layer ME6 so as to extend in the Y direction.

[0267] The insulating layer IS1 and the insulating layer BI1 are provided with a plurality of openings that reach the element isolation layer ST of the substrate BS. Furthermore, the openings are filled with conductive layers ME2 that function as plugs.

[0268] In particular, in this specification and the like, the conductive layer ME2 in contact with the element isolation layer ST may be referred to as a fourth plug.

[0269] The insulating layer IS2 has a plurality of openings that reach the conductive layer ME2, which is the fourth plug. A conductive layer ME4 that functions as a plug is buried in these openings. The openings may include a region that reaches the insulating layer BI1.

[0270] In particular, in this specification and the like, the conductive layer ME4 in contact with the conductive layer ME2 functioning as the fourth plug may be referred to as a fifth plug.

[0271] The insulating layer BI2 and the insulating layer IS3 have a plurality of openings that reach the conductive layer ME4, which is the fourth plug. The bottom of each opening may also include a partial region of the insulating layer IS2.

[0272] Furthermore, a columnar conductive layer ME5 is formed so as to include the opening and extend in a direction parallel to the +Z direction. The conductive layer ME5 filling the opening functions as one of a pair of electrodes of the capacitance element DCF.

[0273] In the capacitive element DCF, like the capacitive element CFE, a portion of the conductive layer ME5 functions as one of a pair of electrodes, a portion of the insulating layer FDI functions as a dielectric, and a portion of the conductive layer ME6 functions as the other of the pair of electrodes. As described above, the conductive layer ME2, which is the fourth plug, is located on the upper surface of the element isolation layer ST, and the conductive layer ME4, which is the fifth plug, is not in contact with any conductive layers other than the conductive layers ME2 and ME5. Therefore, the conductive layer ME2, which is the fourth plug, and the conductive layers ME4 and ME5, which are the fifth plugs, are each in a floating state. In other words, because one of the pair of electrodes of the capacitive element DCF is in a floating state, the capacitive element DCF does not retain data, unlike the capacitive element CFE.

[0274] As a result, as shown in FIGS. 16A, 16B, and 18, the conductive layer ME5 functioning as one of a pair of electrodes of the capacitance element DCF and the conductive layer ME5 functioning as one of a pair of electrodes of the capacitance element CFE can be arranged side by side along the Y direction. Furthermore, by forming the conductive layer ME6 so as to face these conductive layers ME5 via the insulating layer FDI, the capacitance elements CFE and DCF can be arranged side by side along the Y direction. This also allows the conductive layer ME6 functioning as the wiring PL to be arranged so as to extend along the Y direction. This also allows the capacitance element CFE and the wiring PL to be formed simultaneously, making it easy to fabricate the memory device SCD. Furthermore, since there is no need to route the wiring PL over a long distance, the power consumption of the memory device SCD can be reduced. Furthermore, since there is no need to provide a separate conductive layer functioning as the wiring PL, the process cost of the memory device SCD can be reduced.

[0275] 15 to 19 , in the memory device SCD of one embodiment of the present invention, the wirings BL functioning as bit lines and the wirings PL functioning as plate lines extend in parallel to each other. That is, the memory device SCD has a configuration in which the potential applied to the wirings PL can be controlled for each column in memory cells arranged in a matrix.

[0276] Therefore, the memory device SCD described in this embodiment can be applied to the semiconductor device 100 described in the above-described embodiment 1. In this case, the memory cell MEM, the transistor TR, and the capacitor CFE included in the memory device SCD correspond to the memory cell MC, the transistor Tr, and the capacitor Cfe included in the semiconductor device 100, respectively.

[0277] In this embodiment, as an example of the configuration of the memory cell MEM, a memory cell including a transistor having a U-shaped channel formation region provided in a single crystal substrate made of silicon and a capacitor element provided above the transistor and having a conductive layer in the shape of a pillar as one of a pair of electrodes has been described; however, the present invention is not limited to this.

[0278] As one embodiment of the present invention, for example, a transistor may be provided over a substrate made of a material other than silicon. Furthermore, for example, a transistor may have a channel formation region that is not U-shaped. Furthermore, for example, a transistor may be provided so as to have a channel formation region in a semiconductor layer provided over an insulating substrate or an insulating film. In this case, for example, a material containing silicon or an oxide semiconductor can be used for the semiconductor layer. Furthermore, for example, a capacitor may have a conductive layer that is not shaped like a pillar as one of a pair of electrodes.

[0279] Furthermore, for example, as an example of the configuration of the memory cell MEM, a configuration in which a capacitive element is provided below a transistor or a configuration in which a capacitive element is provided to the side of a transistor may be used.Furthermore, for example, a configuration in which a plurality of memory cells MEM are stacked may be used.In other words, a configuration in which a plurality of memory devices SCD are stacked may be used.

[0280] The contents of this embodiment can be implemented by combining them as appropriate. The contents of this embodiment can also be implemented by combining them as appropriate with the contents of other embodiments.

[0281] Embodiment 3 In this embodiment, an indium oxide film that can be used for a semiconductor layer of a transistor according to one embodiment of the present invention will be described.

[0282] In this specification and the like, indium oxide having at least a crystalline portion or a crystalline region in a film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystalline IO or crystalline IO include single-crystalline indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0283] Indium oxide is a semiconductor material having physical properties that are completely different from those of oxide semiconductors such as In—Ga—Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0284] The carrier concentration dependence of the Hall mobility of indium oxide, silicon, and IGZO will be explained. FIG. 20A shows the carrier concentration dependence of the Hall mobility of silicon (Si) and indium oxide (InO Ｘ ) and FIG. 20B is a schematic diagram showing the carrier concentration dependence of the hole mobility for IGZO.

[0285] First, IGZO tends to exhibit higher hole mobility as the carrier concentration increases, as shown by the arrows in Figure 20B. On the other hand, indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases, as shown by the arrows in Figure 20A (see Non-Patent Document 8). This trend is similar to that of silicon; the lower the dopant (impurity) concentration in the material, the less impurity scattering there is and the higher the hole mobility. In other words, the higher the purity and intrinsic indium oxide, the higher the hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties similar to those of silicon. Note that the characteristics of indium oxide shown in Figure 20A are assumed to be single crystal. Therefore, when indium oxide is non-single crystal (e.g., polycrystalline), the characteristics may differ from those shown in Figure 20A.

[0286] 20A, the range R1 of low carrier concentration has extremely high hole mobility, and therefore can be said to be a range of carrier concentration suitable for, for example, a channel formation region of a transistor. For example, in the case of indium oxide, the range R1 is a range where the carrier concentration value is 1×10 １５ cm −３ The range includes, for example, 1×10 １４ cm −３ That's it, 1 x 10 １８ cm −３ By sufficiently reducing the carrier concentration, the Hall mobility value can be increased to 270 cm ２ It is expected that the resistance can be increased to about / (V·s).

[0287] In addition, in indium oxide, the region where the carrier concentration is in the range R1 may contain an element that lowers the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. By substituting these elements for indium, the carrier concentration can be lowered. Examples of elements that lower the carrier concentration include nitrogen, phosphorus, arsenic, and antimony. For example, by substituting nitrogen, phosphorus, arsenic, or antimony for oxygen, the carrier concentration can be lowered.

[0288] On the other hand, the range R2 with a high carrier concentration has a low electrical resistance, and can be said to be a range of carrier concentrations suitable for, for example, the source and drain regions of a transistor, a resistor, or a transparent conductive film. ２０ cm −３ The range includes, for example, 1×10 １９ cm −３ That's it, 1 x 10 ２２ cm −３ By increasing the carrier concentration sufficiently, the resistivity can be reduced to 1×10 −４ It is expected that the resistivity can be reduced to Ω·cm or less.

[0289] In addition, in indium oxide, the region where the carrier concentration is in the range R2 may contain an element that increases the carrier concentration. For example, it is preferable that the indium oxide contains an element that is common to the source electrode and drain electrode of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use an element whose oxide has conductive or semiconducting properties. Note that, as a method for supplying an element that increases the carrier concentration, a method of forming a film containing the element and diffusing it, ion implantation, ion doping, plasma immersion ion implantation, or plasma treatment can be used. Note that, unless otherwise specified in this specification, the presence or absence of mass separation is not limited. For example, in this specification, a method of supplying ions after mass separation is referred to as an ion implantation method, and a method of supplying ions without mass separation is referred to as an ion doping method.

[0290] In this way, indium oxide uses a region with a low carrier concentration as the channel formation region of a transistor, and a region with a high carrier concentration as the source and drain regions of the transistor. In other words, indium oxide can be said to be an oxide capable of valence electron control. Note that IGZO may experience strain in the source and drain regions due to stress from electrodes in contact with the IGZO, resulting in the formation of n-type regions. On the other hand, unlike IGZO, indium oxide is capable of valence electron control, and therefore does not require strain to be formed in the film as with IGZO. Less strain in the film is expected to improve reliability. For example, by separately creating a region with a carrier concentration in the range R1 shown in FIG. 20A and a region with a carrier concentration in the range R2 in the indium oxide film, a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region) can be created. Note that valence electron control in transistors using silicon is generally known. On the other hand, valence electron control in transistors using indium oxide is a novel technical concept that would not normally be conceived.

[0291] By using the above technical concept, a transistor having indium oxide in this specification and the like has two or more, preferably three or more, more preferably four or more, and most preferably five of the following characteristics (1) to (5): (1) a large on-current (in other words, high mobility); (2) a small off-current; (3) a normally-off state; (4) high reliability; and (5) a high cutoff frequency (fT). For example, a transistor having indium oxide in this specification and the like has high mobility, a small off-current, and is normally-off. The transistor has high mobility and is different from a normally-on transistor.

[0292] In addition, a semiconductor being i-type can be rephrased as having the same Fermi level (Ef) and intrinsic Fermi level (Ei) (Ef = Ei). As shown in FIG. 20B, in IGZO, the lower the carrier concentration, the smaller the hole mobility. Therefore, when Ef = Ei finally occurs, the carriers disappear (in other words, the physical properties become similar to those of an insulator), and there is a possibility that the transistor will no longer function. On the other hand, in indium oxide, as shown in FIG. 20A, the lower the carrier concentration, the larger the hole mobility. When Ef = Ei finally occurs, the hole mobility is maximized. In other words, a transistor containing indium oxide can achieve high field-effect mobility by setting Ef = Ei. Note that a transistor containing indium oxide is likely to be normally-off due to its low carrier concentration. Therefore, a transistor containing indium oxide can be normally-off and achieve high field-effect mobility.

[0293] Unless otherwise specified, normally-off refers to a state in which no current flows through a transistor when no potential is applied to the gate or when the gate-source voltage is 0 V. Normally-off can be evaluated by the threshold voltage (Vth) or shift value (Vsh) of the transistor. Unless otherwise specified, Vth is calculated by a constant current method. More specifically, Vth refers to the state in which the value of drain current (Id) × channel length (Lch) ÷ channel width (Wch) in the Id-Vg characteristics of a transistor is 1 nA (1 × 10 −９ A). Vsh is the gate voltage (Vg) when the drain current (Id) in the Id-Vg characteristic of the transistor is expressed logarithmically and the tangent of the maximum slope is Id = 1 pA (1 × 10 −１２ The gate voltage (Vg) is the intersection point between the line of Id = 1 pA and the line extrapolated from two points where the slope of Id is maximum when Id is expressed logarithmically in the Id-Vg characteristics of the transistor. For example, if either or both of Vth and Vsh are zero or a positive value, the transistor can be considered to be normally-off.

[0294] In addition, in a transistor containing indium oxide, in order to make the semiconductor i-type, that is, to achieve Ef = Ei, the film structure in contact with the indium oxide film is important. For example, in a transistor containing indium oxide, a film structure in which a silicon oxide film in contact with the indium oxide film, a hafnium oxide film, and a silicon nitride film are stacked is exemplified. By using this film structure, a semiconductor device with high reliability and Ef = Ei can be obtained.

[0295] In the above film configuration, a film containing oxygen, such as a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, or a gallium oxide film, can be used instead of the silicon oxide film. Also, in the above film configuration, a silicon nitride oxide film, a silicon oxynitride film, or the like can be used instead of the silicon nitride film. The hafnium oxide film, which is located closer to the indium oxide film than the silicon nitride film, functions as a gettering site for hydrogen.

[0296] The above film configuration can also be considered as a stacked structure of a film (e.g., a silicon oxide film) capable of supplying oxygen to the indium oxide film from the indium oxide film side, a film (e.g., a hafnium oxide film) capable of gettering hydrogen, and a film (e.g., a silicon nitride film) that suppresses the penetration of oxygen and hydrogen. With this configuration, oxygen vacancies in the indium oxide film are filled with oxygen in the silicon oxide film. Hydrogen in the indium oxide film is captured by the hafnium oxide film by heat treatment or the like. Furthermore, the provision of the silicon nitride film results in a film configuration that reduces the penetration of oxygen and hydrogen from the outside. That is, with the above film configuration, the indium oxide film can be made closer to i-type. Therefore, a transistor having the above-described indium oxide film has high field-effect mobility and high reliability.

[0297] Next, an indium oxide film applied to a transistor will be described. The indium oxide film preferably has crystallinity (i.e., has crystal grains). Examples of films having crystal grains include single-crystal films, polycrystalline films, and amorphous films containing crystal grains (also called microcrystalline films). In particular, the indium oxide film is preferably a polycrystalline film, and more preferably a single-crystal film. A single-crystal film does not have grain boundaries. Impurities (typically, insulating impurities, insulating oxides, etc.) that hinder carrier flow tend to segregate at grain boundaries. The use of a single-crystal film can suppress carrier scattering at grain boundaries, thereby realizing a transistor exhibiting high field-effect mobility. Furthermore, the use of a single-crystal film has the excellent effect of suppressing variations in transistor characteristics due to the grain boundaries.

[0298] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using a polycrystalline film, it is preferable to use a film with as large a crystal grain size as possible and with few crystal grain boundaries. Note that in a transistor using an indium oxide polycrystalline film, if there is no crystal grain boundary in the channel formation region or no crystal grain boundary is observed, the channel formation region is located within a single crystal region included in the polycrystalline film, and therefore the transistor can be considered to be using single-crystal indium oxide.

[0299] The crystallinity of indium oxide can be analyzed by, for example, X-ray diffraction (XRD), transmission electron microscope (TEM), or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0300] In this specification and the like, a semiconductor layer in which no crystal grain boundary is observed in the channel formation region, a semiconductor layer in which the channel formation region is included in one crystal grain, or a semiconductor layer in which the crystal axis direction is the same in at least two regions in the channel formation region can be called a single crystal film. Also, a semiconductor layer in which, in the channel formation region, within one crystal grain, the direction of another crystal axis continuously changes around a certain crystal axis or a certain crystal orientation as the axis of rotation can be called a single crystal film.

[0301] Unless otherwise specified, the channel formation region refers to a region of the semiconductor layer that overlaps (or faces) the gate electrode via the gate insulating film, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The current path in the channel formation region is the shortest distance between the source electrode and the drain electrode. Therefore, the crystal grains, crystal grain boundaries, crystal axes, crystal orientation, etc. in the channel formation region can be confirmed by observing a cross section including the semiconductor layer, source electrode, and drain electrode.

[0302] The indium oxide film in the channel formation region preferably has a lower impurity concentration. Impurities in the indium oxide film in the channel formation region can be a scattering source of carriers, which can lead to a decrease in field-effect mobility. These impurities can also hinder the crystal growth of the indium oxide film. Examples of impurities in the indium oxide film include boron and silicon. The indium oxide film preferably contains these impurities at concentrations of 0.1% or less, and more preferably 0.01% (100 ppm) or less. Carbon, hydrogen, and other elements may be contained in the film-forming gas or precursor during film formation, and may remain in the indium oxide film in greater amounts than the above-mentioned impurities.

[0303] The indium oxide film in the channel formation region may contain an element that can become the same trivalent cation as indium, as long as the crystal maintains a cubic crystal structure (bixbyite type). Examples of such an element include Group 13 elements of the periodic table, such as gallium and aluminum, and Group 3 elements of the periodic table. These elements exist mainly as trivalent cations in oxides, and therefore the carrier concentration of indium oxide can be maintained low.

[0304] In addition, the indium oxide film in this specification and the like has a high film density. ２ O ３ The film densities of the films are shown in Table 1.

[0305]

[0306] As shown in Table 1, the film density of the indium oxide film was evaluated at six levels, Sample 1 to Sample 6. In Table 1, Condition 1 is the condition of the underlayer film for the indium oxide film, Samples 1 to 3 are glass, Sample 4 is a SiOx film formed by sputtering, and Samples 5 and 6 are yttria-stabilized zirconia (YSZ). Condition 2 is the film formation condition for the indium oxide film, Samples 1 to 3 are film formation by sputtering (SP), and Samples 4 to 6 are film formation by ALD. Condition 3 is the heat treatment condition after the formation of the indium oxide film, with Sample 1, Sample 4, and Sample 5 being no heat treatment (as-deposited), Sample 2 being baked at 350°C in a CDA atmosphere, Sample 3 being baked at 650°C in a CDA atmosphere, and Sample 6 being baked at 250°C in a vacuum atmosphere.

[0307] In Table 1, CDA stands for clean dry air. It is preferable that the atmosphere used in the heat treatment (condition 3) after the formation of the indium oxide film contains as little hydrogen and water as possible. It is preferable to use a high-purity gas with a dew point of −60° C. or lower, preferably −100° C. or lower, as the atmosphere.

[0308] As shown in Table 1, the indium oxide film tends to have a higher film density when subjected to heat treatment compared to when not subjected to heat treatment (Sample 1, Sample 4, or Sample 5). This is because the heat treatment removes impurity elements (e.g., carbon, nitrogen, hydrogen, argon, etc.) from the film, thereby increasing the purity of the indium oxide film. Furthermore, as shown in Samples 5 and 6, the indium oxide film on YSZ has a film density of 7.00 g / cm. ３ The theoretical film density of an indium oxide film is 7.18 g / cm ３ In this specification, the range of the film density of the indium oxide film is 6.70 g / cm ３ 7.18g / cm or more ３ Preferably, it is 6.90 g / cm or less.３ 7.18g / cm or more ３ More preferably, it is 7.00 g / cm or less. ３ 7.18g / cm or more ３ The following is the result.

[0309] The film density can be evaluated by, for example, Rutherford backscattering spectroscopy (RBS) or X-ray reflectometry (XRR). Differences in film density can sometimes be evaluated by cross-sectional transmission electron microscope (TEM) images. In TEM observation, a high film density results in a dense (dark) transmission electron (TE) image, whereas a low film density results in a faint (bright) transmission electron (TE) image.

[0310] By using such an indium oxide film in a transistor, the field effect mobility of the transistor can be increased to 50 cm ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ / (V·s) or more.

[0311] One of the features of an indium oxide film is that it has higher oxygen permeability (diffusibility) than an IGZO film. As shown in FIG. 20C, an indium oxide film (InO Ｘ Oxygen (O) diffusing into the indium oxide film passes through the indium oxide film and becomes oxygen molecules (O ２ ) and is released as water molecules (H ２ In some cases, oxygen atoms are released as oxygen vacancies (Vo) in the film. If oxygen vacancies (Vo) exist in the film, the diffusing oxygen atoms compensate for the oxygen vacancies. Since oxygen easily diffuses in an indium oxide film, it can be said that oxygen vacancies are more easily compensated for in comparison with an IGZO film.

[0312] As described above, an indium oxide film can more easily reduce oxygen vacancies in the film than an IGZO film. Therefore, by using such an indium oxide film in a transistor, a transistor with extremely high reliability can be realized.

[0313] Furthermore, as shown in FIG. 20C, the indium oxide film diffuses hydrogen. Hydrogen that diffuses into the indium oxide film from the outside passes through the indium oxide film and becomes hydrogen molecules (H ２ ) or reacts with oxygen contained in the film and is released as water molecules. The oxygen and hydrogen diffuse in the indium oxide film by heat treatment. The temperature of the heat treatment is 200° C. or higher and 700° C. or lower, preferably 350° C. or higher and 650° C. or lower, and more preferably 400° C. or higher and 500° C. or lower.

[0314] A transistor using an indium oxide film is an accumulation-type transistor that uses electrons as majority carriers. Assuming that the carrier relaxation time is constant, the smaller the effective mass of the electrons (carriers), the higher the electron mobility. In other words, by using indium oxide, which has a small effective mass of electrons, for a transistor, the on-state current or field-effect mobility of the transistor can be increased.

[0315] Table 2 shows the results of single crystal indium oxide (here, In ２ O ３ ) and single-crystal silicon (Si). As shown in Table 2, indium oxide is characterized by a small effective mass of electrons and a large effective mass of holes. Indium oxide also has the characteristic that the effective mass of electrons is almost independent of the crystal orientation. Therefore, by using crystalline indium oxide in a transistor, a transistor with high field-effect mobility and high frequency characteristics (also called f characteristics) can be realized. Furthermore, since the effective mass of holes is large, a transistor with extremely small off-current can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm of channel width can be reduced to 1 fA (1×10) in an environment of 125° C. −１５ A) or less, or 1aA (1 x 10 −１８ A) or less, and under room temperature (25°C) conditions, −１８ A) or less, or 1zA (1 x 10 −２１Furthermore, as shown in Table 2, indium oxide has a smaller effective mass of electrons and a larger effective mass of holes than silicon, and therefore may be able to realize a transistor with higher field-effect mobility and smaller off-state current than a Si transistor.

[0316]

[0317] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. The seed layer is preferably made of a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with indium oxide. This can improve the crystallinity of the indium oxide film. Note that a substrate (e.g., a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0318] One method for evaluating the degree of lattice mismatch is to use the value of the lattice mismatch shown below. The lattice mismatch Δa [%] of the crystals of the formed film (here, the indium oxide film) with respect to the crystals of the seed layer is expressed as Δa = ((L １ -L ２ ) / L ２ ) × 100, where L １ is the length or lattice constant of the unit lattice vector of the crystal of the formed film, and L ２ is the length of the unit cell vector or the lattice constant of the crystal of the seed layer.

[0319] The smaller the absolute value of the lattice mismatch Δa between the seed layer and the indium oxide film, the more preferable, and it is most preferably 0. For example, Δa can be set to −5% or more and 5% or less, preferably −4% or more and 4% or less, more preferably −3% or more and 3% or less, and even more preferably −2% or more and 2% or less.

[0320] Here, the indium oxide crystal has a cubic crystal structure (bixbyite type). For example, the crystal of yttria-stabilized zirconia (YSZ) can have a cubic crystal structure (fluorite type). The lattice mismatch of the indium oxide crystal with the cubic YSZ crystal is in the range of −2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on the YSZ substrate.

[0321] It should be noted that the crystal structure of the seed layer and the crystal structure of the indium oxide film may not necessarily have the same crystal system or crystal orientation. For example, a film having crystals of a hexagonal or trigonal structure may be used under an indium oxide film having crystals of a cubic structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to the crystal orientation necessary for epitaxial growth can be satisfied. Examples of hexagonal or trigonal crystals include wurtzite structure, YbFe ２ O ４ Type structure, Yb ２ Fe ３ O ７ YbFeFe alloys have the following structures: ２ O ４ Type structure or Yb ２ Fe ３ O ７ An example of a crystal having a crystalline structure is IGZO. It should be noted that a single crystal film of indium oxide can be formed not only on a YSZ substrate but also on an insulating film. On the other hand, it is difficult to form a single crystal film of silicon on an insulating film. Silicon crystals have a diamond structure. As such, indium oxide and silicon have similar properties in terms of single crystal. However, when comparing indium oxide and silicon in terms of whether they can be formed as single crystals on an insulating film, they have different properties.

[0322] Here, a comparison is made among a transistor having a crystalline indium oxide film, a transistor having an IGZO (a compound oxide of In, Ga, and Zn) film, and a transistor having a silicon (Si) film. The comparison is shown in Table 3.

[0323]

[0324] In Table 3, transistors having a crystalline indium oxide film are intended for use in LSIs and are clearly indicated as crystalline IO (LSI). Hereinafter, this may be simply referred to as crystalline IO. Transistors having an IGZO film are intended for use in displays and are clearly indicated as IGZO (Display). Hereinafter, this may be simply referred to as IGZO. Transistors having a Si film are also clearly indicated as Si. In Table 3, ◎ represents +2 points, ○ represents +1 point, △ represents 0 points, and × represents −1 point, respectively. Total is the total value of the ◎, ○, △, and × points shown in Table 3. A higher score indicates better characteristics than a lower score.

[0325] In Table 3, the first comparison item is extremely small off-state current, with crystalline IO and IGZO being superior to Si. The second comparison item is on-state current (Ion) characteristics, with crystalline IO and Si being superior to IGZO. The third comparison item is reliability, with crystalline IO and Si being superior to IGZO. The fourth comparison item is miniaturization of channel length, with crystalline IO and IGZO being superior to Si. In the section on miniaturization of channel length, VFET represents a vertical transistor, UFET represents a transistor with a U-shape structure, and 3D structure represents a three-dimensional structure. The fifth comparison item is cutoff frequency, with the characteristics increasing in the order of crystalline IO, Si, and IGZO. The sixth comparison item is improvement in integration, with Si being superior to crystalline IO and IGZO. The seventh comparison item is threshold voltage controllability (Vth controllability), in which Si is superior to crystalline IO and IGZO. The eighth comparison item is radiation resistance, in which crystalline IO and IGZO are superior to Si. The ninth comparison item is 3D (multi-level) integrated structure, in which crystalline IO and IGZO are superior to Si. The tenth comparison item is the possibility of self-heating, in which crystalline IO and IGZO are superior to Si.

[0326] As shown in Table 3, the total score for crystalline IO (LSI) is 9 points, for IGZO (Display) is 4 points, and for Si is 3 points. As described above, the semiconductor device of one embodiment of the present invention, in particular the semiconductor device including a crystalline indium oxide film, has the potential to replace a semiconductor device using Si.

[0327] The contents of this embodiment can be implemented by combining them as appropriate. The contents of this embodiment can also be implemented by combining them as appropriate with the contents of other embodiments.

[0328] Embodiment 4 In this embodiment, an application example of a memory device according to one embodiment of the present invention will be described. The memory device according to one embodiment of the present invention is, for example, a memory device including an oxide semiconductor.

[0329] <Example of Hierarchical Structure of Storage Devices> Generally, computers and the like use various storage devices depending on the application. FIG. 21 shows various storage devices by hierarchy. The higher the storage device, the faster the operating speed is required, while the lower the storage device, the larger the storage capacity and recording density are required. FIG. 21 shows, from the top layer to the bottom, a register, a cache memory, a main memory, and storage. The cache memory may also include, from top to bottom, a primary cache (L1), a secondary cache (L2), and a tertiary cache (L3). While an example having up to a tertiary cache is shown here, a lower-level cache memory may also be included. The lowest-level cache memory may also be called an LLC (Last Level Cache) or an FLC (Final Level Cache). For example, a storage class memory may be included between the main memory and the storage.

[0330] Registers integrated into arithmetic processing units (also called processors) such as CPUs (Central Processing Units), GPUs (Graphics Processing Units), NPUs (Neural Processing Units), and TPUs (Tensor Processing Units) are used to temporarily store the results of calculations performed by cores. They also have the function of retaining setting information for the arithmetic processing units. For this reason, they are frequently accessed by the arithmetic processing units. Therefore, registers are required to have high operating speeds.

[0331] For example, a static random access memory (SRAM) is used as the cache memory. The cache memory has the function of duplicating and storing a portion of the data stored in the main memory. By storing a copy of frequently used data, the speed of accessing the data can be increased. The cache memory is required to have a faster operating speed than the main memory.

[0332] The main memory may be, for example, a dynamic random access memory (DRAM). The main memory has a function of storing programs and data read from storage. The main memory is required to have a larger storage capacity and a higher recording density than cache memory.

[0333] Storage has the function of storing data that requires long-term storage and various programs used by processing units. Therefore, storage requires large storage capacity and high recording density. For example, a hard disk drive (HDD) or a solid state drive (SSD) located on top of an HDD can be used as the storage. For example, a large-capacity, non-volatile storage device such as a NAND flash memory (e.g., 3D NAND) can be used as the SSD.

[0334] A memory device according to one embodiment of the present invention (for example, a memory device using an oxide semiconductor) is excellent in that it has high operation speed, is capable of retaining data for a long period of time, has high rewrite endurance, and can be driven at a low voltage.

[0335] A storage device according to one aspect of the present invention is suitable as a storage device located in an area target1 that includes a tier where a cache memory is located, a tier where a main memory is located, and a tier where a storage is located, because it is capable of retaining data for a long period of time. In other words, a storage device according to one aspect of the present invention is suitable for use in an area target1 that includes, in addition to the area where the main memory is located, the boundary area between the main memory and the storage, and the boundary area between the main memory and the cache memory.

[0336] Therefore, for example, it is preferable to replace a DRAM used in a main memory with a storage device according to one embodiment of the present invention. Here, since DRAM requires a refresh operation and is a destructive readout storage device, it consumes more power than other storage devices. Therefore, by not using DRAM, it is possible to reduce power consumption. It is also preferable to replace, for example, a portion of an SRAM used in a cache memory and a portion of a 3D NAND used in storage with a storage device according to one embodiment of the present invention.

[0337] For example, a memory device according to one embodiment of the present invention includes a capacitor including a ferroelectric material, which enables data retention for a long time. Therefore, when the memory device is used as a replacement for a DRAM, the frequency of refresh can be reduced. Furthermore, the reliability of the memory device can be improved.

[0338] Furthermore, a storage device according to one embodiment of the present invention is suitable for use in the area target2 that includes a layer where the cache memory is located and a layer where the register is located, because the storage device according to one embodiment of the present invention has a high operating speed and can achieve excellent write and read operations. In other words, a storage device according to one embodiment of the present invention is suitable for use in the area target2 that includes a part of the area where the cache memory is located and an area where the register is located.

[0339] Therefore, for example, a storage device according to an embodiment of the present invention is preferably used as at least a part of a register included in a CPU, a GPU, an NPU, etc. Also, for example, a storage device according to an embodiment of the present invention is preferably used as at least a part of a cache memory (such as L1, L2, L3, LLC, and FLC).

[0340] One embodiment of the present invention can be configured without using a DRAM, which has conventionally been used as a main memory or the like. In this case, a storage device according to one embodiment of the present invention can be used in place of the DRAM. Such a configuration can dramatically reduce power consumption (for example, by one hundredth or one thousandth or less). Furthermore, the storage device according to one embodiment of the present invention may be stacked on a processor such as a CPU, a GPU, or an NPU. Such a configuration in which a processor and a storage device are stacked may be referred to as a monolithic stack. By configuring the processor and the storage device as a monolithic stack, for example, the power consumption required for data access between the processor and the storage device can be significantly reduced. Therefore, global warming can be mitigated by deploying information processing devices including supercomputers (also referred to as high performance computers (HPCs)), computers, servers, and the like, to which such a configuration is applied, all over the world.

[0341] As one embodiment of the present invention, for example, instead of a DRAM used as a main memory, at least a part of the semiconductor device 100, the memory device 700, the memory device SCD, and the like described in Embodiment 1 can be used.

[0342] The contents of this embodiment can be implemented by combining them as appropriate. The contents of this embodiment can also be implemented by combining them as appropriate with other embodiments.

[0343] In this embodiment, electronic components, electronic devices, mainframes, space equipment, and data centers (also referred to as data centers (DCs)) that can use the semiconductor device described in the above embodiment will be described. The electronic components, electronic devices, mainframes, space equipment, and data centers that use the semiconductor device of one embodiment of the present invention are effective in achieving high performance, such as low power consumption.

[0344] [Electronic Component] Fig. 22A is a perspective view of an electronic component 5700 and a substrate (mounting substrate 5704) on which the electronic component 5700 is mounted. The electronic component 5700 shown in Fig. 22A has a semiconductor device 5710 in a mold 5711. Fig. 22A omits some parts to show the interior of the electronic component 5700. The electronic component 5700 has lands 5712 on the outside of the mold 5711. The lands 5712 are connected to electrode pads 5713. The electrode pads 5713 are connected to the semiconductor device 5710 by wires 5714. The electronic component 5700 is mounted on, for example, a printed circuit board 5702. A plurality of such electronic components are combined and connected on the printed circuit board 5702 to complete the mounting substrate 5704.

[0345] The semiconductor device 5710 also includes a layer 5715 having an operation core and a layer 5716 having a memory. For example, an n-channel transistor and a p-channel transistor can be used for both the layer 5715 and the layer 5716. For example, a CMOS circuit may be configured using a p-channel transistor for the layer 5715 and an n-channel transistor for the layer 5716. However, one embodiment of the present invention is not limited thereto, and a structure may be used in which both an n-channel transistor and a p-channel transistor are used for the layer 5715 and an n-channel transistor is used for the layer 5716.

[0346] Alternatively, for example, a Si transistor may be used for the layer 5715 and an OS transistor may be used for the layer 5716 .

[0347] The memory-containing layer 5716 has a configuration in which multiple memory cell arrays are stacked. The stacked configuration of the processor core-containing layer 5715 and the memory-containing layer 5716 can be a monolithically stacked configuration. In a monolithically stacked configuration, the processor cores and memories of each layer can be connected to each other without using through-electrode technology such as TSV (Through Silicon Via) or bonding technology such as Cu-Cu direct bonding. By monolithically stacking the processor core-containing layer 5715 and the memory-containing layer 5716, for example, a so-called on-chip memory configuration can be achieved, in which the memory is formed directly on the processor. The on-chip memory configuration enables the operation of the interface between the processor and the memory to be faster. Part of the function of the processor core-containing layer 5715 (part of the computing function) may be provided in a part of the memory-containing layer 5716.

[0348] Furthermore, by configuring an on-chip memory, it is possible to reduce the size of connection wiring, etc., compared to technologies that use through electrodes such as TSVs, and therefore it is also possible to increase the number of connection pins. Increasing the number of connection pins enables parallel operation, which makes it possible to improve the memory bandwidth (also called memory bandwidth).

[0349] It is also preferable that the memory cell arrays included in the memory-containing layer 5716 are formed using OS transistors, and the memory cell arrays are monolithically stacked. By monolithically stacking the memory cell arrays, it is possible to improve either or both of the memory bandwidth and the memory access latency. Note that the bandwidth is the amount of data transferred per unit time. The access latency is the time from access to the start of data exchange. Note that when Si transistors are used for the memory-containing layer 5716, it is more difficult to achieve a monolithically stacked structure than OS transistors. Therefore, it can be said that OS transistors have a superior structure to Si transistors in a monolithically stacked structure.

[0350] That is, OS transistors have an excellent effect of enabling a wider memory bandwidth than Si transistors.

[0351] The semiconductor device 5710 may also be referred to as a die. In this specification, a die refers to a chip piece obtained by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and cutting it into dices during the semiconductor chip manufacturing process. Examples of semiconductor materials that can be used for the die include silicon, silicon carbide, and gallium nitride. For example, a die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.

[0352] 22B is a perspective view of an electronic component 5730. The electronic component 5730 is an example of a SiP (System in Package) or an MCM (Multi Chip Module). The electronic component 5730 has an interposer 5731 provided on a package substrate 5732 (printed circuit board), and a semiconductor device 5735 and a plurality of semiconductor devices 5710 provided on the interposer 5731.

[0353] In the electronic component 5730, the semiconductor device 5710 can be used as, for example, a memory device such as a high bandwidth memory (HBM). The semiconductor device 5735 can be used as, for example, an integrated circuit (e.g., an arithmetic unit, a control unit, an arithmetic processing unit, or a signal processing unit) such as a CPU, a GPU, an NPU, a TPU, or an FPGA (Field Programmable Gate Array).

[0354] For example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate can be used for the package substrate 5732. For example, a silicon interposer or a resin interposer can be used for the interposer 5731.

[0355] The interposer 5731 has a plurality of wirings and functions to connect a plurality of integrated circuits with different terminal pitches via each of the plurality of wirings. The plurality of wirings are provided in a single layer or multiple layers. The interposer 5731 also functions to connect the integrated circuits provided on the interposer 5731 to electrodes provided on the package substrate 5732. For these reasons, the interposer 5731 is sometimes referred to as a "rewiring substrate" or "intermediate substrate." The interposer 5731 may also be provided with through electrodes, which may be used to connect the integrated circuits to the package substrate 5732. When a silicon interposer is used for the interposer 5731, TSVs may also be used as the through electrodes.

[0356] It is preferable to use a silicon interposer as the interposer 5731. A silicon interposer does not require an active element, and therefore can be manufactured at lower cost than an integrated circuit. Furthermore, since the wiring of a silicon interposer can be formed using a semiconductor process, it is easy to form fine wiring that is difficult to form with a resin interposer.

[0357] To achieve a wide memory bandwidth, an HBM needs to connect many wires. Therefore, the interposer on which the HBM is mounted must have fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.

[0358] Furthermore, for example, SiP or MCM using a silicon interposer is less likely to suffer from a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer. Furthermore, since the silicon interposer has a highly flat surface, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is less likely to occur. In particular, it is preferable to use a silicon interposer for a 2.5D package (2.5-dimensional packaging) in which multiple integrated circuits are arranged side by side on an interposer.

[0359] On the other hand, for example, when connecting multiple integrated circuits with different terminal pitches using a silicon interposer, a TSV, or the like, a space is required, such as the width of the terminal pitch. Therefore, when attempting to reduce the size of the electronic component 5730, the width of the terminal pitch becomes an issue, and it may be difficult to provide the many wirings necessary to achieve a wide memory bandwidth. Therefore, as described above, a monolithically stacked configuration using OS transistors is preferable. Also, a composite structure may be used in which a memory cell array stacked using TSVs and a monolithically stacked memory cell array are combined.

[0360] The substrate on which the electronic component 5730 is mounted may be provided with a heat sink (heat dissipation plate) overlapping the electronic component 5730. When a heat sink is provided, it is preferable that the height of the integrated circuit provided on the interposer 5731 be the same. For example, it is preferable that the height of the electronic component 5730 be the same as that of the semiconductor device 5710 and the semiconductor device 5735.

[0361] In order to mount the electronic component 5730 on another substrate, the package substrate 5732 may have electrodes 5733 on its bottom. FIG. 22B shows an example in which the electrodes 5733 are formed with solder balls. By providing solder balls in a matrix on the bottom of the package substrate 5732, the electronic component 5730 can be mounted using a ball grid array (BGA) method. The electrodes 5733 may also be formed with conductive pins. By providing conductive pins in a matrix on the bottom of the package substrate 5732, the electronic component 5730 can be mounted using a pin grid array (PGA) method.

[0362] The electronic component 5730 can be mounted on other substrates using various mounting methods, not limited to BGA or PGA, such as a staggered pin grid array (SPGA), a land grid array (LGA), a quad flat package (QFP), a quad flat J-leaded package (QFJ), or a quad flat non-leaded package (QFN).

[0363] 23A is a perspective view of an electronic device 6500. The electronic device 6500 shown in FIG. 23A is a portable information terminal that can be used as a smartphone. The electronic device 6500 includes, for example, a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, and a control device 6509. Note that the control device 6509 includes, for example, one or more selected from an arithmetic processing device, a memory device, and the like. The semiconductor device of one embodiment of the present invention can be applied to the display portion 6502 or the control device 6509, for example. The use of the semiconductor device of one embodiment of the present invention for the control device 6509 is preferable because power consumption can be reduced.

[0364] FIG. 23B is a perspective view of an electronic device 6600. The electronic device 6600 shown in FIG. 23B is an information terminal that can be used as a laptop personal computer. The electronic device 6600 includes, for example, a housing 6611, a keyboard 6612, a pointing device 6613, an external connection port 6614, a display portion 6615, and a control device 6616. Note that the control device 6616 includes, for example, one or more selected from an arithmetic processing device, a memory device, and the like. The semiconductor device of one embodiment of the present invention can be applied to the display portion 6615 or the control device 6616, for example. The use of the semiconductor device of one embodiment of the present invention for the control device 6616 is preferable because power consumption can be reduced.

[0365] [Mainframe] Fig. 23C is a perspective view of a mainframe 5600. The mainframe 5600 shown in Fig. 23C has a rack 5610 housing a plurality of rack-mounted computers 5620. The mainframe 5600 may also be called a supercomputer.

[0366] Fig. 23D is a perspective view illustrating an example configuration of a computer 5620. In Fig. 23D, the computer 5620 has a motherboard 5630. The motherboard 5630 has a plurality of slots 5631 and a plurality of connection terminals (not shown). A PC card 5621 is inserted into the slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, each of which is connected to the motherboard 5630.

[0367] PC card 5621 shown in Figure 23E is an example of a processing board equipped with, for example, a processing unit and a storage device. PC card 5621 has board 5622. Board 5622 also has connection terminals 5623, 5624, 5625, semiconductor devices 5626, 5627, 5628, and 5629. Note that Figure 23E illustrates semiconductor devices other than semiconductor devices 5626, 5627, and 5628, but for these semiconductor devices, the following descriptions of semiconductor devices 5626, 5627, and 5628 can be referenced.

[0368] The connection terminal 5629 has a shape that allows it to be inserted into a slot 5631 of the motherboard 5630, and functions as an interface for connecting the PC card 5621 and the motherboard 5630. An example of the standard for the connection terminal 5629 is PCIe (Peripheral Component Interconnect Express).

[0369] Each of the connection terminals 5623, 5624, and 5625 can be, for example, an interface for supplying power or inputting signals to the PC card 5621. Furthermore, each of the connection terminals 5623, 5624, and 5625 can be, for example, an interface for outputting signals calculated by the PC card 5621. Examples of standards for each of the connection terminals 5623, 5624, and 5625 include Universal Serial Bus (USB), Serial ATA (SATA), and Small Computer System Interface (SCSI). Furthermore, when a video signal is output from each of the connection terminals 5623, 5624, and 5625, examples of the respective standards include High-Definition Multimedia Interface (HDMI (registered trademark)).

[0370] The semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and the semiconductor device 5626 can be connected to the board 5622 by inserting the terminal into a socket (not shown) provided on the board 5622.

[0371] The semiconductor device 5627 has a plurality of terminals, and the semiconductor device 5627 can be connected to the board 5622 by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5627 include a CPU, a GPU, an NPU, a TPU, and an FPGA. For example, the electronic component 5730 described above can be used as the semiconductor device 5627.

[0372] The semiconductor device 5628 has a plurality of terminals, and the semiconductor device 5628 can be connected to the board 5622 by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5628 include a memory device. For example, the electronic component 5700 described above can be used as the semiconductor device 5628.

[0373] The mainframe computer 5600 can also function as a parallel computer. By using the mainframe computer 5600 as a parallel computer, it is possible to perform large-scale calculations necessary for learning and inference in artificial intelligence, for example.

[0374] [Space Equipment] The semiconductor device of one embodiment of the present invention can be used in space equipment such as equipment that processes and stores information, for example.

[0375] The semiconductor device of one embodiment of the present invention can include an OS transistor. The OS transistor exhibits small changes in electrical characteristics due to radiation exposure. That is, the OS transistor has high radiation resistance and is therefore suitable for use in an environment where radiation may be incident. For example, the OS transistor is suitable for use in outer space.

[0376] Fig. 24A shows an artificial satellite 6800 as an example of space equipment. The artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. Fig. 24A also shows a planet 6804 in outer space. Although outer space refers to an altitude of 100 km or higher, the outer space described in this specification may also include the thermosphere, mesosphere, and stratosphere.

[0377] 24A , a battery management system (also referred to as a BMS) or a battery control circuit may be provided for the secondary battery 6805. The use of an OS transistor in the battery management system or the battery control circuit is preferable because it consumes low power and has high reliability even in space.

[0378] Furthermore, outer space is an environment with radiation levels 100 times higher than on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, and particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0379] The solar panel 6802 generates the power necessary for the operation of the satellite 6800 when irradiated with sunlight. However, for example, in a situation where the solar panel 6802 is not irradiated with sunlight or where the amount of sunlight irradiating the solar panel 6802 is small, the solar panel 6802 generates less power. Therefore, the satellite 6800 may not generate the power necessary for its operation. In order to operate the satellite 6800 even in a situation where the power generated by the solar panel 6802 is small, the satellite 6800 may be provided with a secondary battery 6805. The solar panel 6802 may also be called a solar cell module.

[0380] The satellite 6800 can generate a signal. The signal is transmitted via the antenna 6803. Furthermore, for example, a receiver installed on the ground or another satellite can receive the signal. For example, the receiver can measure the position of the receiver by receiving the signal transmitted by the satellite 6800. As described above, the satellite 6800 can constitute a satellite positioning system.

[0381] The control device 6807 has a function of controlling the artificial satellite 6800. The control device 6807 is configured using, for example, one or more devices selected from an arithmetic processing device, a storage device, and the like. Note that the control device 6807 is preferably a semiconductor device including an OS transistor, which is one embodiment of the present invention. The OS transistor has smaller fluctuations in electrical characteristics due to radiation exposure than a Si transistor. That is, the OS transistor is preferable because it has high reliability even in an environment where radiation may be incident.

[0382] That is, an OS transistor has an excellent effect of being more radiation resistant than a Si transistor.

[0383] The artificial satellite 6800 may also be configured to include a sensor. For example, the artificial satellite 6800 may be configured to include a visible light sensor, thereby enabling it to have the function of detecting sunlight reflected from an object on the ground. The artificial satellite 6800 may also be configured to include a thermal infrared sensor, thereby enabling it to have the function of detecting thermal infrared rays emitted from the earth's surface. As described above, the artificial satellite 6800 may function as, for example, an earth observation satellite.

[0384] Although an artificial satellite is shown here as an example of space equipment, the present invention is not limited thereto. The semiconductor device of one embodiment of the present invention can be used in space equipment such as a spaceship, a space capsule, or a space probe, for example.

[0385] [Data Center] The semiconductor device according to one embodiment of the present invention can be used in a storage system applied to a data center, for example. The data center is required to perform long-term management of data, for example, by ensuring the immutability of data. Managing long-term data requires, for example, the installation of storage and servers for storing huge amounts of data, the securing of a stable power source for retaining the data, or the securing of cooling equipment required for retaining the data. Therefore, for example, the data center building needs to be enlarged.

[0386] By using the semiconductor device of one embodiment of the present invention in a storage system applied to a data center, it is possible to reduce the power required to store data and the size of the semiconductor device that stores data. Therefore, for example, it is possible to reduce the size of the storage system, the size of the power supply for storing data, and the scale of the cooling equipment. Therefore, it is possible to reduce the space required for the data center.

[0387] Furthermore, the semiconductor device of one embodiment of the present invention has low power consumption, which allows heat generation from the circuit to be reduced. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and peripheral modules can be reduced. Furthermore, by using the semiconductor device of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. Therefore, the reliability of the data center can be improved.

[0388] Fig. 24B shows a storage system applicable to a data center. The storage system 7000 shown in Fig. 24B has a plurality of servers 7001sb as hosts 7001 (illustrated as Host Computers). It also has a plurality of storage devices 7003md as storage 7003 (illustrated as Storage). The host 7001 and storage 7003 are connected via a storage area network 7004 (illustrated as SAN: Storage Area Network) and a storage control circuit 7002 (illustrated as Storage Controller).

[0389] The host 7001 corresponds to a computer that accesses data stored in the storage 7003. The hosts 7001 may be connected to each other via a network.

[0390] Although the storage 7003 uses flash memory to reduce the data access speed, i.e., the time required to write or read data, this time is significantly longer than the time required for DRAM, which can be used as cache memory within the storage. In order to solve the problem of the long access speed of the storage 7003, a storage system typically provides cache memory within the storage to reduce the time required to write or read data.

[0391] The above-mentioned cache memory is used in the storage control circuit 7002 and the storage 7003. Data exchanged between the host 7001 and the storage 7003 is stored in the cache memory in the storage control circuit 7002 and the storage 7003, and then output to the host 7001 or the storage 7003.

[0392] By using OS transistors as transistors for storing data in the cache memory and holding a potential corresponding to the data, the frequency of refreshing the cache memory can be reduced and the power consumption of the cache memory can be reduced.Furthermore, by using a stacked memory cell array, the cache memory can be miniaturized.

[0393] [Head-Mountable Electronic Device] A semiconductor device according to one aspect of the present invention can be used in head-mountable electronic devices (sometimes called wearable devices, headsets, etc.), such as devices for VR, devices for AR, devices for SR (Substitutional Reality), devices for MR (Mixed Reality), and devices that implement spatial computing such as spatial computers.

[0394] 24C and 24D , examples of head-mountable electronic devices will be described. These electronic devices have at least one of the following functions: a function for displaying AR content, a function for displaying VR content, a function for displaying SR content, a function for displaying MR content, and a function for displaying spatial computing content. By having an electronic device with the function for displaying at least one of AR, VR, SR, MR, spatial computing, or other content, it is possible to enhance the sense of immersion felt by the user.

[0395] 24C shows the appearance of an electronic device 8710. The electronic device 8710 includes an attachment portion 8711, a lens 8712, a main body 8713, a display portion 8714, and a cable 8715. The attachment portion 8711 includes a battery 8716 built therein.

[0396] A cable 8715 supplies power from a battery 8716 to the main body 8713. The main body 8713 includes a wireless receiver and can display received image information such as image data on a display portion 8714. A camera provided in the main body 8713 captures the movements of the user's eyeballs, eyelids, and the like, and calculates the user's line of sight based on the information, thereby allowing the user's line of sight to be used as an input means.

[0397] The attachment portion 8711 may be provided with a plurality of electrodes at positions that come into contact with the user. The main body 8713 may have a function of recognizing the user's line of sight by detecting a current flowing through the electrodes in accordance with the movement of the user's eyeballs. The main body 8713 may also have a function of monitoring the user's pulse by detecting the current flowing through the electrodes. The attachment portion 8711 may also have various sensors such as a temperature sensor, a pressure sensor, and an acceleration sensor, and may have a function of displaying biological information of the user on the display portion 8714. The attachment portion 8711 may also detect the movement of the user's head and change the image displayed on the display portion 8714 in accordance with the movement.

[0398] 24D shows the appearance of the electronic device 8720. The electronic device 8720 is a goggle-type information processing device.

[0399] The electronic device 8720 includes a housing 8721, operation buttons 8723, a band-shaped fixture 8724, and two display units 8722. The two display units 8722 allow a user to view one display unit per eye. This allows high-resolution images to be displayed even when performing 3D display using parallax. The fixture 8724 is also provided with a battery 8725. While the battery 8725 may be provided in the housing 8721, providing the battery 8725 in the fixture 8724 is preferable because the center of gravity of the electronic device 8720 can be shifted rearward, improving the wearing comfort for the user. In addition to the battery 8725, a driver circuit for operating the display unit 8722 may be provided in the fixture 8724 to adjust the center of gravity of the electronic device 8720.

[0400] The operation button 8723 has a function of a power button, etc. In addition to the operation button 8723, other buttons may be provided.

[0401] Note that the semiconductor device of one embodiment of the present invention can be applied to any one or more of electronic components, electronic devices, mainframe computers, space equipment, and data centers to reduce power consumption. Therefore, while energy demand is expected to increase with the improvement in performance or high integration of semiconductor devices, the use of the semiconductor device of one embodiment of the present invention can contribute to the reduction of carbon dioxide (CO ２ Furthermore, the semiconductor device of one embodiment of the present invention consumes low power and is therefore effective as a countermeasure against global warming.

[0402] The contents of this embodiment can be implemented by combining them as appropriate. The contents of this embodiment can also be implemented by combining them as appropriate with the contents of other embodiments.

[0403] (Additional Notes Regarding the Description of the Present Specification, etc.) The following additional notes will be given regarding the above-described embodiments and the explanation of each configuration in the embodiments.

[0404] In this specification, "connection" includes, for example, "electrical connection." When "electrical connection" is used to define the connection relationship between circuit elements as an object, "electrical connection" includes, for example, "direct connection" and "indirect connection." For example, "A and B are directly connected" refers to a connection between A and B without the intervention of a circuit element (e.g., a transistor or a switch; wiring is not considered a circuit element). On the other hand, "A and B are indirectly connected" refers to a connection between A and B via one or more circuit elements. Note that A, B, and C, which will be described later, represent objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers.

[0405] Here, when "A and B are indirectly connected," it refers to the following connection relationship, for example. That is, assuming that a circuit is operating, if there is a time during the operation of the circuit when electrical signal transmission or potential interaction occurs between A and B, such a circuit can be defined as an entity, and "A and B are indirectly connected." Note that even if there is a time when electrical signal transmission or potential interaction does not occur between A and B, if there is a time during the operation of the circuit when electrical signal transmission or potential interaction occurs between A and B, it can be defined as "A and B are indirectly connected." Note that "A and B are indirectly connected" is a definition of the connection relationship between circuit elements as an entity. Therefore, for example, even when a power supply voltage is not supplied to a circuit and the circuit is not operating, the circuit can be defined as an entity, and "A and B are indirectly connected" (however, for example, this is limited to the case where electrical signal transmission or potential interaction occurs between A and B during the operation of the circuit when a power supply voltage is supplied to the circuit and the circuit is operating).

[0406] Specific examples of "indirect connection" are shown below. First, an example of "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors, as shown in FIGS. 25A1 and 25A2. Another example of "A and B are indirectly connected" is when A and B are connected via one or more switches. When "A and B are indirectly connected," it is assumed that, assuming the circuit is operating, there is at least one time when a transistor between A and B is in an on state, a conductive state, or a state in which a current can flow. Note that "A and B are indirectly connected" also includes cases where a transistor between A and B is in an off state or a non-conductive state. When "A and B are indirectly connected," if multiple transistors are connected between A and B, it is assumed that, assuming the circuit is operating, each of the multiple transistors between A and B is in an on state, a conductive state, or a state in which a current can flow at least one time. In other words, when "A and B are indirectly connected," it is not necessary for all of the multiple transistors to be in an on state, a conductive state, or a state in which current can flow simultaneously. Therefore, when "A and B are indirectly connected," it also includes cases in which the multiple transistors between A and B are in an off state or a non-conductive state at the same time or at different times. As another example, as shown in FIG. 25A3, when A and C are connected via the source and drain of transistor TrP and B and C are connected via the source and drain of transistor TrQ, it can be defined as "A and C are indirectly connected," "B and C are indirectly connected," or "A and B are indirectly connected." However, as will be described later, when a constant potential V is supplied to C from a power supply, GND, or the like, it can be said that "A and C are indirectly connected" or "B and C are indirectly connected," but it cannot be said that "A and B are indirectly connected."

[0407] While we have provided examples of cases where an "indirect connection" can and cannot be established, we will now present another example of a case where an "indirect connection" cannot be established. Even if an electrical signal exchange or potential interaction occurs between A and B during the operation of the circuit, there are exceptional cases where it cannot be said that "A and B are indirectly connected." An example of such an exceptional case is when A and B are connected via an insulator. In other words, when A and B are connected via an insulator, it cannot be said that "A and B are indirectly connected." A specific example of a case where A and B are connected via an insulator is when a capacitive element is connected between A and B, as shown in FIG. 25A4. Another example of a case where A and B are connected via an insulator is when a gate insulating film of a transistor is interposed between A and B, as shown in FIG. 25A5. In this case, it cannot be said that "A (the gate of the transistor) and B (the source or drain of the transistor) are indirectly connected."

[0408] Another example of a case where it cannot be said that "A and B are indirectly connected" is a case where there is no timing when an electrical signal is exchanged or when potential interaction occurs between A and B. An example of this is when, as shown in Figures 25A6 and 25A7, multiple transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between the transistors from a power supply, GND, or the like. In this case, it cannot be said that "A and B are indirectly connected," but it is possible to say that "A and V are indirectly connected" or "B and V are indirectly connected." In addition, in Figure 25A3, if A and C are connected via the source and drain of transistor TrP, and B and C are connected via the source and drain of transistor TrQ, and a constant potential V is supplied to C from a power supply or GND, etc., the connection relationship will be the same as in Figures 25A6 and 25A7, so it cannot be said that "A and B are indirectly connected," but it can be said that "A and C are indirectly connected" or "B and C are indirectly connected."

[0409] Although an example of "indirect connection" has been given above, as an example, the definition of "indirect connection" is included in the definition of "electrical connection," so if "A and B are indirectly connected," it can also be said that "A and B are electrically connected."

[0410] Next, specific examples of "direct connection" are shown. Examples of "A and B are directly connected" include cases where A and B are connected without any circuit element between them, as shown in FIGS. 25B1, 25B2, and 25B3. When A and B are connected to a power supply that supplies a constant potential V or to GND without any circuit element between them, as shown in FIGS. 25B4 and 25B5, it can be said that "A and B are directly connected," "A and V are directly connected," or "B and V are directly connected." It can also be said that "A and B are directly connected," even when A (or B) is connected to a constant potential V via the source and drain of a transistor, as shown in FIG. 25B6. Because A and V or B and V are connected via the source and drain of a transistor, they cannot be said to be directly connected, but rather that "A and V are indirectly connected" or "B and V are indirectly connected."

[0411] Although an example of "direct connection" has been given above, as an example, the definition of "direct connection" is included in the definition of "electrical connection," so when "A and B are directly connected," it can also be said that "A and B are electrically connected."

[0412] Note that even when independent components are shown connected to each other in a circuit diagram, one component may have the functions of multiple components. For example, if part of a wiring also functions as an electrode, one conductive film has the functions of both the wiring and the electrode. Therefore, in this specification, the term "connection" also includes such cases where one conductive film has the functions of multiple components.

[0413] Furthermore, in this specification, the term "resistive element" may refer to, for example, a circuit element or wiring having a resistance value higher than 0 Ω. Therefore, in this specification, the term "resistive element" includes, for example, wiring having a resistance value, a transistor in which current flows from drain to source, a diode, or a coil. Therefore, the term "resistive element" may be replaced with, for example, terms such as "resistance," "load," or "region having a resistance value." Conversely, the terms "resistance," "load," or "region having a resistance value" may be replaced with, for example, terms such as "resistive element." The resistance value may be, for example, preferably 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, and even more preferably 10 mΩ or more and 1 Ω or less. Furthermore, for example, the resistance value may be, for example, 1 Ω or more and 1×10 ９ It may be set to Ω or less.

[0414] When a wiring is used as a resistor, the resistance value of the resistor may be determined by the length of the wiring. Alternatively, the resistor may use a conductor having a different resistivity from the conductor used as the wiring. Alternatively, when a semiconductor is used as a resistor, the resistance value of the resistor may be determined by doping impurities into the semiconductor.

[0415] Furthermore, in this specification, a "capacitive element" can refer to, for example, a circuit element having a capacitance value higher than 0 F, a region of wiring having a capacitance value higher than 0 F, a parasitic capacitance, or a gate capacitance of a transistor. Therefore, in this specification, a "capacitive element" is not limited to a circuit element including a pair of electrodes and a dielectric sandwiched between the electrodes. A "capacitive element" also includes, for example, a parasitic capacitance occurring between wirings, or a gate capacitance occurring between one of the source or drain of a transistor and the gate. Furthermore, terms such as "capacitive element," "parasitic capacitance," or "gate capacitance" can be replaced with terms such as "capacitance" or "capacitance." Conversely, terms such as "capacitance" or "capacitance" can be replaced with terms such as "capacitive element," "parasitic capacitance," or "gate capacitance." Furthermore, terms such as "pair of electrodes," "pair of wirings," "pair of terminals," "pair of conductive layers," "pair of conductors," "pair of conductive regions," and "pair of regions" of a "capacitive element" can sometimes be interchangeable. The capacitance value may be, for example, 0.05 fF to 10 pF, or may be, for example, 1 pF to 10 μF.

[0416] In this specification and the like, a transistor has three terminals called a gate (also referred to as a gate terminal, a gate region, or a gate electrode), a source (also referred to as a source terminal, a source region, or a source electrode), and a drain (also referred to as a drain terminal, a drain region, or a drain electrode). The transistor also has a region where a channel is formed between the drain and the source (also referred to as a channel formation region). A transistor can pass a current between the source and the drain through the channel formation region. That is, a transistor can transmit and receive an electric signal or generate a potential interaction between the source and the drain through the channel formation region. The channel formation region is a region through which a current mainly flows. The gate is a control terminal that controls the amount of current flowing in the channel formation region. The two terminals that function as a source and a drain are input / output terminals that input or output a current flowing in the channel formation region.

[0417] Note that one of the two input / output terminals functions as a source and the other as a drain depending on the conductivity type of the transistor (n-channel or p-channel) and the level of the potential applied to the three terminals of the transistor. Furthermore, for example, when the direction of current changes during circuit operation, the function as a source and the function as a drain may be interchanged. For this reason, in this specification, the terms "source" and "drain" are interchangeable. Furthermore, in this specification, when describing the connection relationship of a transistor, the terms "one of the source or drain" (or first electrode or first terminal) or "the other of the source or drain" (or second electrode or second terminal) are used.

[0418] Depending on the structure, a transistor may have a terminal called a back gate (also referred to as a back gate terminal, back gate region, or back gate electrode) in addition to the three terminals described above. In this case, in this specification and the like, one of the gate or the back gate of the transistor may be referred to as a first gate, and the other of the gate or the back gate of the transistor may be referred to as a second gate. Furthermore, for the same transistor, the terms "gate" and "back gate" may be interchangeable. Furthermore, when a transistor has three or more gates, in this specification and the like, each gate may be referred to as, for example, a first gate, a second gate, a third gate, or the like.

[0419] In this specification, a transistor having a multi-gate structure with two or more gate electrodes can be used. A multi-gate transistor has channel formation regions connected in series, resulting in a structure in which multiple transistors are connected in series. Therefore, a multi-gate transistor can reduce off-state current and improve the transistor's breakdown voltage (improved reliability). Furthermore, when a multi-gate transistor operates in the saturation region, even if the voltage between the drain and source changes, the current between the drain and source does not change significantly, resulting in a voltage-current characteristic with a flat slope. A transistor having a voltage-current characteristic with a flat slope can realize an ideal current source circuit or an active load with a very high resistance value. As a result, a transistor having a voltage-current characteristic with a flat slope can realize, for example, a differential circuit or a current mirror circuit with good characteristics.

[0420] Furthermore, in this specification, when a single circuit element is illustrated on a circuit diagram, the circuit element may include multiple circuit elements. For example, when a single resistor is illustrated on a circuit diagram, the resistor is considered to include two or more resistors connected in series. For example, when a single capacitor is illustrated on a circuit diagram, the capacitor is considered to include two or more capacitors connected in parallel. For example, when a single transistor is illustrated on a circuit diagram, the transistor is considered to include two or more transistors connected in series, with the gates of the respective transistors connected to each other. Similarly, when a single switch is illustrated on a circuit diagram, the switch is considered to include two or more transistors, with the two or more transistors connected in series or in parallel, and with the gates of the respective transistors connected to each other.

[0421] Furthermore, in this specification and the like, a "node" can be rephrased as a "terminal," "wiring," "electrode," "conductive layer," "conductor," or "impurity region," depending on, for example, the circuit configuration or the device structure. Furthermore, for example, a "terminal" or "wiring" can be rephrased as a "node."

[0422] Furthermore, in this specification, "voltage" and "potential" can be interchanged as appropriate. "Voltage" refers to the potential difference from a reference potential. For example, if the reference potential is the ground potential (earth potential), then "voltage" can be interchanged with "potential." Note that ground potential does not necessarily mean 0 V. Furthermore, potential is relative. In other words, a change in the reference potential will change, for example, the potential applied to wiring, the potential applied to a circuit, or the potential output from a circuit.

[0423] Furthermore, in this specification and the like, the terms "high-level potential (also referred to as "high-level potential," "H potential," or "H")" and "low-level potential (also referred to as "low-level potential," "L potential," or "L")" do not refer to any particular potential. For example, when two wirings are both described as "functioning as wirings that supply a high-level potential," the high-level potentials provided by both wirings do not have to be equal to each other. Similarly, when two wirings are both described as "functioning as wirings that supply a low-level potential," the low-level potentials provided by both wirings do not have to be equal to each other.

[0424] Furthermore, in this specification, "electric current" refers to the phenomenon of charge transfer (electrical conduction). For example, the statement "electrical conduction of positively charged bodies is occurring" can be rephrased as "electrical conduction of negatively charged bodies is occurring in the opposite direction." Therefore, in this specification, unless otherwise specified, "electric current" refers to the phenomenon of charge transfer (electrical conduction) associated with the movement of carriers. Examples of carriers include electrons, holes, anions, cations, and complex ions. Note that carriers vary depending on the system through which the current flows (e.g., semiconductor, metal, electrolyte, vacuum, etc.). Furthermore, the "direction of current" in, for example, wiring, is the direction in which positive carriers move and is expressed as a positive current amount. In other words, the direction in which negative carriers move is opposite to the direction of current and is expressed as a negative current amount. Therefore, in this specification and the like, unless otherwise specified, regarding the positive / negative (or current direction) of a current, for example, a statement such as "a current flows from element A to element B" can be rephrased as "a current flows from element B to element A" etc. Furthermore, for example, a statement such as "a current is input to element A" can be rephrased as "a current is output from element A" etc.

[0425] Furthermore, in this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be referred to as "second" in another embodiment or in the claims. Furthermore, for example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0426] Furthermore, in this specification, terms indicating arrangement, such as "above," "below," "upward," or "belowward," may be used for convenience in describing the positional relationship between components with reference to drawings. Furthermore, the positional relationship between components changes as appropriate depending on the orientation in which each component is depicted. Therefore, terms indicating arrangement described in this specification are not limited to these terms and can be rephrased appropriately. For example, the expression "insulator located on the upper surface of a conductor" can be rephrased as "insulator located on the lower surface of a conductor" by rotating the orientation of the drawing by 180 degrees. Furthermore, the expression "insulator located on the upper surface of a conductor" can be rephrased as "insulator located on the left (or right) surface of a conductor" by rotating the orientation of the drawing by 90 degrees.

[0427] Furthermore, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below and in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not necessarily mean that electrode B is formed on insulating layer A in direct contact with it, and does not exclude the inclusion of other components between insulating layer A and electrode B. Thus, the term "above" may be replaced with terms such as "above," "upper side," or "upper layer," and the term "below" may be replaced with terms such as "below," "lower side," or "lower layer."

[0428] Furthermore, in this specification, terms such as "row" or "column" may be used to describe components arranged in a matrix and their positional relationships. Furthermore, the positional relationships between components change as appropriate depending on the direction in which each component is depicted. Therefore, terms such as "row" or "column" used in this specification are not limited to these terms and can be rephrased appropriately. For example, the expression "row direction" can be rephrased as "column direction" by rotating the orientation of the drawing by 90 degrees.

[0429] Furthermore, in this specification and the like, for example, terms such as "overlap" do not limit the state of the stacking order of components, etc. For example, the expression "electrode B overlapping insulating layer A" is not limited to the state in which electrode B is formed on insulating layer A. The expression "electrode B overlapping insulating layer A" does not exclude, for example, the state in which electrode B is formed under insulating layer A, or the state in which electrode B is formed on the right (or left) side of insulating layer A.

[0430] Furthermore, in this specification and the like, the terms "adjacent" or "close to" do not limit components to being in direct contact with each other. For example, the expression "electrode B adjacent to insulating layer A" does not necessarily mean that insulating layer A and electrode B are formed in direct contact with each other, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0431] Furthermore, in this specification and the like, terms such as "film" or "layer" may be interchangeable. For example, the term "conductive layer" may be interchangeable with the term "conductive film." For example, the term "insulating film" may be interchangeable with the term "insulating layer." Furthermore, terms such as "film" or "layer" may be interchangeable with other terms without using those terms. For example, the term "conductive layer" or "conductive film" may be interchangeable with the term "conductor." Furthermore, the term "conductor" may be interchangeable with the term "conductive layer" or "conductive film." For example, the term "insulating layer" or "insulating film" may be interchangeable with the term "insulator." Furthermore, the term "insulator" may be interchangeable with the term "insulating layer" or "insulating film."

[0432] Furthermore, in this specification and the like, terms such as "electrode," "wiring," or "terminal" do not functionally limit these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" or "wiring" include, for example, cases where multiple "electrodes" or "wirings" are integrally formed. Furthermore, for example, a "terminal" may be used as part of a "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" includes, for example, cases where multiple "electrodes," "wirings," or "terminals" are integrally formed. Therefore, for example, an "electrode" can be part of a "wiring" or "terminal." Furthermore, for example, a "terminal" can be part of a "wiring" or "electrode." Furthermore, for example, terms such as "electrode," "wiring," or "terminal" may be replaced with terms such as "region."

[0433] Furthermore, in this specification and the like, for example, terms such as "signal line" or "power line" may be changed to the term "wiring." Furthermore, for example, the term "potential" applied to wiring may be changed to the term "signal." The same is true in reverse, for example, terms such as "signal" may be changed to the term "potential."

[0434] In addition, in this specification, a "switch" refers to a circuit element that has multiple terminals and the ability to switch (select) between conduction and non-conduction between the terminals. In other words, a switch can be said to have the ability to control whether or not a current flows between the multiple terminals, or the ability to control whether or not an electrical signal or potential interaction occurs between the multiple terminals. For example, if a switch has two terminals and the two terminals are considered to be electrically short-circuited, the switch is said to be in a "conductive state" or "on state." Furthermore, if the two terminals are considered to be electrically disconnected, the switch is said to be in a "non-conductive state" or "off state." Note that switching the switch between a conductive state or a non-conductive state, or maintaining the switch in either a conductive state or a non-conductive state, may be referred to as "controlling the conduction state."

[0435] In other words, a switch is a device that has the function of controlling whether or not a current flows. Alternatively, a switch is a device that has the function of selecting and switching a path through which a current flows. For example, an electrical switch or a mechanical switch can be used as the switch. In other words, the switch is not limited to a specific type.

[0436] There are types of switches that are normally in a non-conductive state but can be made conductive by controlling the conductive state, and these switches are sometimes called "contact A." There are also types of switches that are normally in a conductive state but can be made non-conductive by controlling the conductive state, and these switches are sometimes called "contact B."

[0437] Examples of electrical switches include transistors (e.g., bipolar transistors or MOS transistors), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, or diode-connected transistors), and logic circuits that combine these. Note that when a transistor is operated simply as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0438] An example of a mechanical switch is a switch that uses MEMS (microelectromechanical systems) technology. Such a switch has an electrode that can be mechanically moved, and the movement of the electrode selects a conductive state or a non-conductive state.

[0439] In this specification, the "channel length" of a transistor may refer to, for example, the distance between the source and drain in a region where the semiconductor (or the portion in the semiconductor through which current flows when the transistor is on) and the gate overlap, or the distance between the source and drain in a region where a channel is formed.

[0440] In addition, in this specification, the "channel width" of a transistor may refer to, for example, the length of the portion where the source and drain face each other in a region where the semiconductor (or the portion where current flows in the semiconductor when the transistor is on) and the gate overlap, or the length of the portion where the source and drain face each other in a region where a channel is formed.

[0441] In this specification and the like, terms such as "substrate," "wafer," or "die" do not limit the functionality of these components. For example, terms such as "substrate," "wafer," or "die" may be used interchangeably.

[0442] In this specification, "parallel" does not necessarily mean strictly parallel. Therefore, the term "parallel" can be appropriately interchanged with terms such as "approximately parallel," "generally parallel," or "substantially parallel." Unless otherwise specified, "parallel," "generally parallel," "generally parallel," or "substantially parallel" may include, for example, a state in which two lines or planes are arranged at an angle of -5° or more and 5° or less. Alternatively, they may include a state in which two lines or planes are arranged at an angle of -10° or more and 10° or less. Alternatively, they may include a state in which two lines or planes are arranged at an angle of -30° or more and 30° or less. Therefore, "parallel" can mean, for example, "parallel or roughly parallel." Furthermore, "perpendicular" does not necessarily mean strictly perpendicular. Therefore, the term "perpendicular" can be appropriately interchanged with terms such as "generally vertical," "generally vertical," or "substantially vertical." Unless otherwise specified, "vertical," "approximately vertical," "generally vertical," or "substantially vertical" may include, for example, a state in which two straight lines or planes are arranged at an angle of 85° or more and 95° or less. Alternatively, it may also include a state in which two straight lines or planes are arranged at an angle of 80° or more and 100° or less. Alternatively, it may also include a state in which two straight lines or planes are arranged at an angle of 60° or more and 120° or less. Therefore, "vertical" may mean, for example, "vertical or roughly vertical."

[0443] In this specification, "equal heights" refers to the same height from a reference surface (e.g., a flat surface such as a substrate surface) in a cross-sectional view. For example, in a semiconductor device manufacturing process, a planarization process may expose the surface of a single layer or multiple layers. In this case, the surfaces to be planarized have the same height from the reference surface. However, depending on the processing equipment, processing method, or material of the processed surface during the planarization process, the heights of multiple layers may not be strictly equal. In this specification, "equal heights" is also used. For example, when there are two layers (here, a first layer and a second layer) with different heights relative to a reference surface, the difference between the height of the top surface of the first layer and the height of the top surface of the second layer is 20 nm or less. Therefore, "equal heights" may mean, for example, "equal heights or approximately equal heights."

[0444] In this specification, "edges coincide" means that, when viewed from above, at least a portion of the contours of stacked layers overlap. For example, this includes cases in which, in a semiconductor device manufacturing process, upper and lower layers are processed using the same mask pattern or a portion of the same mask pattern. However, strictly speaking, the contours may not overlap, and the contour of the upper layer may be located inside the contour of the lower layer, or the contour of the upper layer may be located outside the contour of the lower layer. In this specification, this case is also referred to as "edges coincide." Therefore, "edges coincide" can mean, for example, "edges coincide or approximately coincide."

[0445] In this specification, for example, when referring to counting values ​​and measurement values, or to things, methods, and events that can be converted into counting values ​​or measurement values, terms such as "identical," "same," "equal," "simultaneous," "matching," or "uniform" (including synonyms thereof) are intended to include errors. Therefore, unless otherwise specified, these terms may include an error of plus or minus 10% or an error of plus or minus 20%. Thus, "identical" means "identical or approximately identical," "same" means "same or approximately the same," "equal" means "equal or approximately equal," "simultaneous" means "simultaneous or approximately simultaneous," "matching" means "matching or approximately matching," and "uniform" may mean "uniform or approximately uniform."

[0446] In this specification and the like, the term "impurity" in a semiconductor refers to, for example, a substance other than the main component constituting the semiconductor. For example, an element with a concentration of less than 0.1 atomic % is an impurity. The presence of impurities in a semiconductor may, for example, increase the defect state density of the semiconductor, decrease the carrier mobility, or decrease the crystallinity. When the semiconductor is an oxide semiconductor, examples of impurities that change the characteristics of the semiconductor include Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main component of the oxide semiconductor. In particular, examples of impurities include hydrogen (also contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. For example, the inclusion of impurities in an oxide semiconductor may cause oxygen vacancies in the oxide semiconductor.

[0447] In this specification and the like, a metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into, for example, oxide insulators, oxide conductors (including transparent oxide conductors), and oxide semiconductors (also referred to as oxide semiconductors or simply as OSs). For example, when a metal oxide is used as a semiconductor including a channel formation region of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, when a metal oxide is used as a material capable of forming a channel formation region of a transistor having at least one of an amplifying function, a rectifying function, and a switching function, the metal oxide can be referred to as a metal oxide semiconductor. Furthermore, the term "OS transistor" can be rephrased as a transistor including a metal oxide or an oxide semiconductor.

[0448] In this specification and the like, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0449] In addition, in drawings and the like relating to this specification, arrows indicating the X direction, Y direction, and Z direction may be used. In this specification, the "X direction" refers to the direction along the X axis, and unless otherwise specified, the forward direction and the reverse direction may not be distinguished. The same applies to the "Y direction" and the "Z direction." The X direction, Y direction, and Z direction are directions that intersect with each other. For example, the X direction, Y direction, and Z direction are directions that are perpendicular to each other. In this specification, one of the X direction, Y direction, and Z direction may be referred to as the "first direction" or "first direction." The other may be referred to as the "second direction" or "second direction." The remaining one may be referred to as the "third direction" or "third direction."

[0450] 100: semiconductor device, 110: semiconductor device, MC: memory cell, MC11: memory cell, MC12: memory cell, MC21: memory cell, MC22: memory cell, Tr: transistor, Tr11: transistor, Tr12: transistor, Tr21: transistor, Tr22: transistor, Cfe: capacitance element, Cfe11: capacitance element, Cfe12: capacitance element, Cfe21: capacitance element, Cfe22: capacitance element, WL: wiring, WL1: wiring, WL2: wiring, BL : wiring, BL1: wiring, BL2: wiring, PL: wiring, PL0: wiring, PL1: wiring, PL2: wiring, SA_EN: wiring, SA: sense amplifier, PLD: PL line driver, 700: storage device, 721: memory array, 722: drive circuit, 741: memory cell, 761: power switch, 762: power switch, 771: peripheral circuit, 772: control circuit, 773: voltage generation circuit, 781: peripheral circuit, 782: row decoder, 783: row driver, 784: column decoder , 785: Sense amplifier section, 786: PL line driver section, 787: Input circuit, 788: Output circuit, 789: Column driver, BW: Terminal, CE: Terminal, GW: Terminal, MCK: Terminal, WAKE: Terminal, ADDR: Terminal, RDA: Terminal, WDA: Terminal, PON1: Terminal, PON2: Terminal, VMD: Terminal, VMS: Terminal, VMH: Terminal, SCD: Storage device, MEM: Memory cell, TR: Transistor, CFE: Capacitor, DCF: Capacitor, BS: Substrate, ST: Element isolation layer, TA: transistor region, SEAb: semiconductor region, SEAc: semiconductor region, LRa: low resistance region, LRb: low resistance region, LRc: low resistance region, MZ: groove portion, ME1: conductive layer, ME2: conductive layer, ME3: conductive layer, ME4: conductive layer, ME5: conductive layer, ME6: conductive layer, GI1: insulating layer, UI1: insulating layer, UI2: insulating layer, UI3: insulating layer, IS1: insulating layer, IS2: insulating layer, IS3: insulating layer, IS4: insulating layer, BI1: insulating layer, BI2: insulating layer, FDI: insulating layer

Claims

A plurality of memory cells connected to one word line; the plurality of memory cells are connected to a plurality of bit lines in a one-to-one relationship; the plurality of memory cells are connected to a plurality of plate lines in a one-to-one relationship; Each of the plurality of memory cells includes a ferroelectric capacitor and a transistor; In each of the plurality of memory cells, one terminal of the ferroelectric capacitor is electrically connected to one of the source and drain of the transistor; the other terminal of the ferroelectric capacitor is electrically connected to the plate line; the other of the source and the drain of the transistor is electrically connected to the bit line; a gate of the transistor electrically connected to the word line, When writing data into the plurality of memory cells, a first potential is applied to a plate line connected to a memory cell into which data 0 is to be written, and a second potential is applied to a plate line connected to a memory cell into which data 1 is to be written. A method for driving a semiconductor device. 　 In claim 1, a difference between the first potential and the second potential is equal to or greater than a saturation polarization voltage of the ferroelectric capacitor; A method for driving a semiconductor device. 　 a first memory cell, a second memory cell, a first drive circuit, and a second drive circuit; the first memory cell includes a first ferroelectric capacitor and a first transistor; the second memory cell includes a second ferroelectric capacitor and a second transistor; one terminal of the first ferroelectric capacitor is electrically connected to one of the source and the drain of the first transistor; the other terminal of the first ferroelectric capacitor is electrically connected to a first plate line; the other of the source and the drain of the first transistor is electrically connected to a first bit line; a gate of the first transistor electrically connected to a word line; one terminal of the second ferroelectric capacitor is electrically connected to one of the source and the drain of the second transistor; the other terminal of the second ferroelectric capacitor is electrically connected to a second plate line; the other of the source and the drain of the second transistor is electrically connected to a second bit line; a gate of the second transistor electrically connected to the word line; the first drive circuit is electrically connected to the first plate line; the second drive circuit is electrically connected to the second plate line; the first drive circuit has a function of applying a potential corresponding to data to the first plate line when writing data to the first memory cell; the second drive circuit has a function of applying a potential corresponding to data to the second plate line when writing data to the second memory cell; Semiconductor device. 　 In claim 3, the first drive circuit has a function of applying a first potential to the first plate line when writing data of 0, and applying a second potential to the first plate line when writing data of 1; the second drive circuit has a function of applying the first potential to the second plate line when writing data of 0, and applying the second potential to the second plate line when writing data of 1, a difference between the first potential and the second potential is equal to or greater than a saturation polarization voltage of the first ferroelectric capacitor and equal to or greater than a saturation polarization voltage of the second ferroelectric capacitor; Semiconductor device. 　 a substrate, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and an insulating layer; the substrate includes a channel forming region, a source region, and a drain region of a transistor; the first conductive layer functions as a gate electrode of the transistor; the second conductive layer is provided above a layer on which the first conductive layer is provided, the second conductive layer is electrically connected to one of the source region or the drain region; the third conductive layer is provided above a layer on which the second conductive layer is provided, the third conductive layer is electrically connected to the other of the source region or the drain region; the third conductive layer has a columnar shape, the insulating layer is provided to cover the third conductive layer, the insulating layer includes a material that may have ferroelectric properties; the fourth conductive layer is provided to cover the insulating layer, the first conductive layer extends in a first direction along an upper surface of the substrate; the second conductive layer extends in a second direction that intersects the first direction and runs along the top surface of the substrate; the fourth conductive layer extends in the second direction; Semiconductor device. 　 In claim 5, the first conductive layer functions as a word line; the second conductive layer functions as a bit line; the fourth conductive layer functions as a plate line. Semiconductor device. 　 In claim 5 or claim 6, the substrate has a trench located between the source region and the drain region; The first conductive layer is provided so as to fill at least a portion of the groove. Semiconductor device.

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