Semiconductor device and method for producing semiconductor device

Abstract

The purpose of the present invention is to provide technology capable of enhancing the insulation properties of an interlayer insulation film in a termination region. This semiconductor device comprises: a gate electrode that is provided in a first trench with a first insulation film therebetween; a first interlayer insulation film that is provided in the first trench and on the upper portion of the gate electrode; a termination electrode that is provided on the bottom surface of a second trench and on the active-region-side side surface of the second trench with a second insulation film therebetween; and a second interlayer insulation film that is provided on the termination electrode. The termination electrode includes a tapered section that is tapered and a continuous section that is continuous with the tapered section.

Description

Semiconductor device and manufacturing method thereof

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device.

[0002] A known semiconductor device configuration includes a sidewall electrode extending from a wide trench in a termination region to the outside thereof (see, for example, Patent Document 1). On the other hand, a proposed semiconductor device configuration includes a gate electrode provided in a gate trench in an active region via a gate insulating film, and an interlayer insulating film provided entirely within the gate trench on the gate electrode.

[0003] International Publication No. 2022 / 024810

[0004] Generally, the gate electrode and the sidewall electrodes are formed by etching the same conductive film. When fabricating a structure in which the entire interlayer insulating film is provided within the gate trench, the gate electrode is etched more than conventionally in order to lower the upper end of the gate electrode within the gate trench. Accordingly, the sidewall electrodes are also etched more than conventionally, and the sidewall electrodes are provided within the wide trench and have tapered portions that narrow toward the top.

[0005] However, the out-of-plane direction of the upper surface of the tapered portion is significantly different from the deposition direction in which the interlayer insulating film is likely to be deposited on the tapered portion, so when the sidewall electrode has only a tapered portion, the thickness of the interlayer insulating film in the tapered portion becomes partially thin, resulting in a problem of reduced insulation properties of the interlayer insulating film in the termination region.

[0006] Therefore, the present disclosure has been made in consideration of the above-mentioned problems, and has an object to provide a technique that can improve the insulating properties of the interlayer insulating film in the termination region.

[0007] The semiconductor device according to the present disclosure comprises a semiconductor layer having a first trench in an active region and a second trench in a termination region, the second trench being wider than the first trench; a gate electrode provided in the first trench via a first insulating film; a first interlayer insulating film provided in the first trench on top of the gate electrode; a termination electrode made of the same material as the gate electrode and provided on a bottom surface of the second trench and on a side surface on the active region side via a second insulating film; and a second interlayer insulating film provided on the termination electrode, wherein the termination electrode includes a tapered portion provided along the side surface of the second trench and tapering upward, and a continuous portion provided along the bottom surface of the second trench and continuous with the tapered portion.

[0008] According to the present disclosure, the termination electrode includes a tapered portion and a continuous portion that is continuous with the tapered portion. With this configuration, the insulation properties of the interlayer insulating film in the termination region can be improved.

[0009] The objects, features, aspects and advantages of the present disclosure will become more apparent from the following detailed description and the accompanying drawings.

[0010] 1 is a plan view showing a configuration of a semiconductor device according to a first embodiment; 2 is a cross-sectional view showing a configuration of a semiconductor device according to a first embodiment; 3 is a cross-sectional view showing a configuration of a semiconductor device according to a first embodiment; 4 is a cross-sectional view showing a configuration of a semiconductor device according to a first embodiment; 5 is a flowchart showing a method for manufacturing a semiconductor device according to a first embodiment; 6 is a cross-sectional view for explaining a method for manufacturing a semiconductor device according to a first embodiment; 7 is a cross-sectional view showing a configuration of a related device; 8 is a cross-sectional view showing a configuration of a semiconductor device according to a first embodiment; 9 is a cross-sectional view showing a configuration of a semiconductor device according to a second embodiment; 10 is a flowchart showing a method for manufacturing a semiconductor device according to a second embodiment;

[0011] Hereinafter, embodiments will be described with reference to the accompanying drawings. Features described in each of the following embodiments are merely examples, and not all features are necessarily required. Furthermore, in the following description, similar components in multiple embodiments are denoted by the same or similar reference numerals, and different components will be mainly described. Furthermore, in the following description, specific positions and directions such as "top," "bottom," "left," "right," "front," or "back" do not necessarily correspond to the positions and directions in actual implementation. Furthermore, a certain portion having a higher concentration than another portion may mean, for example, that the average concentration of the certain portion is higher than the average concentration of the other portion. Conversely, a certain portion having a lower concentration than another portion may mean, for example, that the average concentration of the certain portion is lower than the average concentration of the other portion. Furthermore, although the following description will be given assuming that the first conductivity type is n-type and the second conductivity type is p-type, the first conductivity type may also be p-type and the second conductivity type may also be n-type.

[0012] <First Preferred Embodiment> Fig. 1 is a plan view showing the configuration of a semiconductor device according to a first preferred embodiment. Fig. 2 is a cross-sectional view taken along line A-A in Fig. 1, and Fig. 3 is a cross-sectional view taken along line B-B in Fig. 1. Fig. 4 is a cross-sectional view showing an enlarged portion of Fig. 3. For convenience, some of the components in Fig. 4 are omitted or simplified in Figs. 2 and 3.

[0013] Hereinafter, the semiconductor device according to the first embodiment will be described as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), but is not limited to this. The semiconductor device according to the first embodiment may be, for example, an IGBT (Insulated Gate Bipolar Transistor) or an RC-IGBT (Reverse Conducting-IGBT), which is a semiconductor switching element including a diode.

[0014] As shown in FIG. 4 , the semiconductor device according to the first embodiment includes a semiconductor layer 1, a gate insulating film 2 which is a first insulating film, a gate electrode 3, a first interlayer insulating film 4, a termination insulating film 5 which is a second insulating film, a sidewall electrode 6 which is a termination electrode, a second interlayer insulating film 7, and a source electrode 8.

[0015] The semiconductor layer 1 is made of, for example, silicon (Si) or a wide bandgap semiconductor, and includes at least one of a normal semiconductor wafer and an epitaxial growth layer. In this specification, for example, at least one of A, B, C, ..., and Z means any one of all combinations of one or more types extracted from the group A, B, C, ..., and Z. Wide bandgap semiconductors include, for example, silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga ２ O ３ ), diamond, etc. When the semiconductor layer 1 is made of a wide band gap semiconductor, the semiconductor element can operate stably under high temperatures and high voltages, and can achieve high switching speeds.

[0016] As shown in FIG. 4, an active region 1j and a termination region 1k are defined in the semiconductor layer 1. A semiconductor cell that functions as a MOSFET is provided in the active region 1j. The termination region 1k is a region that surrounds the active region 1j, and is provided with a breakdown voltage structure such as a guard ring (not shown). Note that the gate pad 31 in FIG. 1 is provided generally above the semiconductor layer 1 in the termination region 1k, and the source pad 32 is provided generally above the semiconductor layer 1 in the active region 1j. Below, the configuration of the active region 1j will be described first, followed by the configuration of the termination region 1k.

[0017] <Active Region 1j> As shown in FIG. 4, the semiconductor layer 1 of the active region 1j includes a drift region 1a, a low-resistance region 1b, a well region (also called a base region) 1c, a source region 1d, a contact region 1e, and an electric field relaxation region 1f.

[0018] The drift region 1a is －The low resistance region 1b is an n-type region and is provided above the drift region 1a. The low resistance region 1b is a part of the drift region 1a. The well region 1c is a p-type region and is provided on the low resistance region 1b. The source region 1d is an n-type region. ＋ This is a mold region and is provided on the well region 1c.

[0019] The contact region 1e is p ＋ 2, the contact region 1e may or may not be provided depending on the position in the extending direction of the gate trench 1p, which will be described later.

[0020] 4, the active region 1j of the semiconductor layer 1 includes a gate trench 1p, which is a first trench that penetrates from the top surface of the source region 1d through the well region 1c. In plan view, the gate trenches 1p may or may not have a striped shape. The electric field relaxation region 1f is a p-type region and is provided on the bottom surface of the gate trench 1p.

[0021] The configuration of the semiconductor layer 1 is not limited to that shown in Fig. 1. For example, the configuration shown in Fig. 4 may include a p-type impurity region (not shown) that is provided along the gate trench 1p and connects the well region 1c and the electric field relaxation region 1f. Also, for example, the well region 1c and the source region 1d may not be provided in some areas.

[0022] The gate insulating film 2 is provided in the gate trench 1p, and the gate electrode 3 is provided in the gate trench 1p via the gate insulating film 2. A recess is provided in the center of the upper part of the gate electrode 3. Although not shown, the gate electrode 3 is electrically connected to the gate pad 31 of FIG.

[0023] 4, the first interlayer insulating film 4 is provided in the gate trench 1p above the gate electrode 3. A recess is provided in the center of the upper part of the first interlayer insulating film 4. In the first embodiment, the entire first interlayer insulating film 4 is provided in the gate trench 1p, and the upper end of the first interlayer insulating film 4 is located lower than the upper end of the semiconductor layer 1 (i.e., the upper end of the source region 1d).

[0024] The source electrode 8 is provided on the first interlayer insulating film 4 and is electrically connected to the source region 1d and the contact region 1e. The source electrode 8 may be provided not only on the first interlayer insulating film 4 but also on the second interlayer insulating film 7. Although not shown, the source electrode 8 is electrically connected to the source pad 32 in FIG. 1. A drain electrode (not shown) is provided below the semiconductor layer 1. When a voltage equal to or greater than the threshold voltage is applied to the gate electrode 3, a channel is formed in the well region 1c on the gate electrode 3 side, and a current flows between the source electrode 8 and the drain electrode via the channel.

[0025] <Termination Region 1k> As shown in FIG. 4, the termination region 1k of the semiconductor layer 1 includes a wide trench 1q, which is a second trench that extends from the top surface of the source region 1d through the well region 1c and is wider than the gate trench 1p. The width here corresponds to the horizontal distance in FIG. 4. The mesa portion 1r, which is the upper portion of the semiconductor layer 1, is located between the gate trench 1p and the wide trench 1q. It is preferable that the depths of the gate trench 1p and the wide trench 1q are the same or substantially the same. This configuration allows the depletion layer depths in the drift region 1a to be uniform, thereby suppressing a decrease in the breakdown voltage of the semiconductor device due to electric field concentration around the periphery of the active region 1j.

[0026] The sidewall electrode 6 is provided on the bottom surface 1q1 of the wide trench 1q and on the side surface 1q2 on the active region 1j side, with a termination insulating film 5 interposed therebetween. The sidewall electrode 6 is formed from the same conductive film as the gate electrode 3, and the material of the sidewall electrode 6 is the same as the material of the gate electrode 3. The fact that the material of the sidewall electrode 6 is the same as the material of the gate electrode 3 means that the sidewall electrode 6 is formed from the same conductive film as the gate electrode 3, and an error of the order of manufacturing variations is acceptable. If the opening sizes of the gate trench 1p and the wide trench 1q were the same, the thicknesses of the gate electrode 3 and the sidewall electrode 6 in the vertical direction would be the same. However, in the first embodiment, the opening sizes of these trenches are different, so the thicknesses of these electrodes are slightly different from each other.

[0027] Although not shown, in the first embodiment, the sidewall electrode 6 is continuous with the gate electrode 3, and the termination insulating film 5 is continuous with the gate insulating film 2. In other words, the sidewall electrode 6 is electrically connected to the gate electrode 3.

[0028] 4, the sidewall electrode 6 includes a tapered portion 6a and a continuous portion 6b. The tapered portion 6a is provided along the side surface 1q2 of the wide trench 1q and tapers upward. The continuous portion 6b is provided along the bottom surface 1q1 of the wide trench 1q and is continuous with the tapered portion 6a. In the first embodiment, the tapered portion 6a includes a first portion and a second portion that is closer to the continuous portion 6b than the first portion, and the out-of-plane direction D1 of the first portion is closer to the vertical direction than the out-of-plane direction D2 of the second portion.

[0029] The second interlayer insulating film 7 is provided on the sidewall electrode 6. In the first embodiment, the second interlayer insulating film 7 is provided on the tapered portion 6a, the continuous portion 6b, and the mesa portion 1r.

[0030] 5 is a flowchart showing a method for manufacturing the semiconductor device according to the present embodiment 1. Since each region of the semiconductor layer 1 can be formed using a general semiconductor device manufacturing process, the formation of the gate electrode 3 and the sidewall electrodes 6 will be mainly described here.

[0031] In step S1, a gate trench 1p is formed in the active region 1j of the semiconductor layer 1, and a wide trench 1q is formed in the termination region 1k of the semiconductor layer 1. In step S2, an insulating film 9 is formed in the gate trench 1p and the wide trench 1q, as shown in FIG.

[0032] 6, a conductive film 10 is formed on the insulating film 9. In step S4, the conductive film 10 is patterned to form the gate electrode 3 and the sidewall electrode 6 in parallel, as shown in Fig. 6. In the sidewall electrode 6, the continuous portion 6b can be made continuous with the tapered portion 6a by adjusting the position of the mask for patterning the conductive film 10, the thickness of the continuous portion 6b, and the etching conditions.

[0033] In step S5, an interlayer insulating film is formed in the gate trench 1p above the gate electrode 3, and an interlayer insulating film is formed on the sidewall electrode 6. The interlayer insulating film is then patterned to form the first interlayer insulating film 4 and the second interlayer insulating film 7, and the insulating film 9 is patterned to form the gate insulating film 2 and the termination insulating film 5. The first interlayer insulating film 4 and the second interlayer insulating film 7 may be formed in parallel or separately. Thereafter, a source electrode 8, a drain electrode, etc. are formed, and the semiconductor device is completed.

[0034] 7 is a cross-sectional view showing the configuration of a related device, which is a semiconductor device related to the semiconductor device according to the first embodiment. In the related device, the sidewall electrode 6 does not include the continuous portion 6 b but includes the tapered portion 6 a.

[0035] The out-of-plane direction D of the upper surface of the tapered portion 6a is significantly different from the deposition direction (corresponding to the up-and-down direction in FIG. 7 ) in which the second interlayer insulating film 7 is likely to be deposited on the tapered portion 6a. Therefore, when the sidewall electrode 6 has only the tapered portion 6a, the thickness of the second interlayer insulating film 7 in the out-of-plane direction D becomes thin, which causes a problem of degrading the insulating properties of the second interlayer insulating film 7 in the termination region 1k.

[0036] 4 according to the first embodiment, the sidewall electrode 6 includes a tapered portion 6a and a continuous portion 6b that is continuous with the tapered portion 6a. This configuration allows the continuous portion 6b to reduce the upper surface of the tapered portion 6a, the out-of-plane direction of which is significantly different from the deposition direction. This allows the thickness of the second interlayer insulating film 7 to be increased, thereby improving the insulating properties of the second interlayer insulating film 7 in the termination region 1k.

[0037] Furthermore, in a configuration in which the sidewall electrode 6 is electrically connected to the gate electrode 3, the gate voltage can be maintained by increasing the insulating properties of the second interlayer insulating film 7 in the termination region 1k as described above.

[0038] 4, in the first embodiment, tapered portion 6a includes a first portion and a second portion that is closer to continuous portion 6b than the first portion, and the out-of-plane direction D1 of the first portion is closer to the vertical direction than the out-of-plane direction D2 of the second portion. With this configuration, the out-of-plane direction of tapered portion 6a can be made closer to the deposition direction of second interlayer insulating film 7, thereby making it possible to increase the thickness of second interlayer insulating film 7 near side surface 1q2 at the boundary between active region 1j and termination region 1k. This is not limited to the configuration of FIG. 4, but can also be achieved in a configuration such as that of FIG. 8, in which the portion of continuous portion 6b on the tapered portion 6a side is thinner than other portions of continuous portion 6b.

[0039] <Modifications> In the first embodiment, the sidewall electrode 6 is electrically connected to the gate electrode 3, but this is not limiting. As a first example, the sidewall electrode 6 may be electrically connected to the source electrode 8 instead of the gate electrode 3. In such a configuration, the source voltage can be maintained by increasing the insulating properties of the second interlayer insulating film 7 in the termination region 1k as described above. As a second example, the sidewall electrode 6 may be a floating electrode that is not electrically connected to either the gate electrode 3 or the source electrode 8. In such a configuration, increasing the insulating properties of the second interlayer insulating film 7 in the termination region 1k as described above can reduce an increase in resistance due to a short circuit between the gate electrode 3 or the source electrode 8 and the sidewall electrode 6, which is a floating electrode.

[0040] 9 is a cross-sectional view showing the configuration of a semiconductor device according to a second embodiment, specifically a cross-sectional view corresponding to Fig. 4. Hereinafter, of the components according to the second embodiment, components that are the same as or similar to the components described above will be given the same or similar reference numerals, and different components will be mainly described.

[0041] In the second embodiment, the sidewall electrode 6 including the tapered portion 6a described in the related device is not provided in the wide trench 1q. Instead, a second interlayer insulating film 7 is provided on the bottom surface 1q1 of the wide trench 1q and on the side surface 1q2 on the active region 1j side, via a termination insulating film 5. Note that a sidewall electrode that does not include the tapered portion 6a may be provided in the wide trench 1q.

[0042] <Manufacturing Method> Fig. 10 is a flowchart showing a method for manufacturing a semiconductor device according to the present embodiment 2. Note that steps S1 to S3 in Fig. 10 are similar to steps S1 to S3 in Fig. 5, and therefore steps S4a and S5a will be mainly described below.

[0043] In step S4a, the conductive film 10 is patterned to form the gate electrode 3, but the sidewall electrode 6 is not formed in the wide trench 1q. The conductive film 10 in the wide trench 1q may be removed using a mask, or may be removed without using a mask by appropriately adjusting the opening size of the wide trench 1q.

[0044] In step S5a, a first interlayer insulating film 4 is formed in the gate trench 1p above the gate electrode 3, and a second interlayer insulating film 7 is formed on the bottom surface 1q1 and side surface 1q2 of the wide trench 1q via a termination insulating film 5. The first interlayer insulating film 4 and the second interlayer insulating film 7 may be formed in parallel or separately. Thereafter, a source electrode 8, a drain electrode, etc. are formed, and the semiconductor device is completed.

[0045] Summary of Second Embodiment According to the semiconductor device of the second embodiment as described above, instead of providing, in wide trench 1q, sidewall electrode 6 including tapered portion 6a that reduces the thickness of second interlayer insulating film 7, second interlayer insulating film 7 is provided in wide trench 1q via termination insulating film 5. With this configuration, the tapered shape that would have made second interlayer insulating film 7 thinner is not provided, so the thickness of second interlayer insulating film 7 can be increased, and as a result, the insulating properties of second interlayer insulating film 7 in termination region 1k can be improved.

[0046] <Modifications> In the first and second embodiments, the sidewall electrode 6 is continuous with the gate electrode 3, and the termination insulating film 5 is continuous with the gate insulating film 2. However, this is not limitative. For example, depending on the planar layout of the semiconductor device, the sidewall electrode 6 may be separated from the gate electrode 3, and the termination insulating film 5 may be separated from the gate insulating film 2.

[0047] In the first and second embodiments, the sidewall electrode 6 including the tapered portion 6 a and the continuous portion 6 b is applied to the cross-sectional structure taken along line B-B in Fig. 1, but this is not limiting. For example, depending on the planar layout of the semiconductor device, the sidewall electrode 6 may be applied to the cross-sectional structure taken along line A-A in Fig. 1.

[0048] In this disclosure, 'a' and 'an' mean one or more. Therefore, 'a', 'an', 'one or more', and 'at least one' can be used interchangeably.

[0049] It should be noted that the embodiments and modifications may be freely combined, and the embodiments and modifications may be modified or omitted as appropriate.

[0050] The above description is illustrative in all respects and is not restrictive. It is understood that countless variations not illustrated can be envisioned.

[0051] 1 semiconductor layer, 1j active region, 1k termination region, 1p gate trench, 1q wide trench, 1q1 bottom surface, 1q2 side surface, 1r mesa portion, 2 gate insulating film, 3 gate electrode, 4 first interlayer insulating film, 5 termination insulating film, 6 sidewall electrode, 6a tapered portion, 6b continuous portion, 7 second interlayer insulating film, 8 source electrode.

Claims

1. A semiconductor device comprising: a semiconductor layer having a first trench in an active region and a second trench in a termination region, the second trench being wider than the first trench; a gate electrode provided in the first trench with a first insulating film interposed therebetween; a first interlayer insulating film provided in the first trench on top of the gate electrode; a termination electrode made of the same material as the gate electrode and provided on the bottom surface of the second trench and on the side surface facing the active region with a second insulating film interposed therebetween; and a second interlayer insulating film provided on the termination electrode, wherein the termination electrode has a tapered portion provided along the side surface of the second trench and tapering upward, and a continuous portion provided along the bottom surface of the second trench and continuing from the tapered portion.

2. A semiconductor device according to claim 1, wherein the termination electrode is electrically connected to the gate electrode.

3. A semiconductor device according to claim 1, wherein the termination electrode is electrically connected to a source electrode.

4. The semiconductor device according to claim 1, wherein the termination electrode is a floating electrode.

5. A semiconductor device according to any one of claims 1 to 4, wherein the semiconductor layer has a mesa portion between the first trench and the second trench, and the second interlayer insulating film is provided on the tapered portion, the continuous portion, and the mesa portion.

6. A semiconductor device according to any one of claims 1 to 5, wherein the tapered portion includes a first portion and a second portion that is closer to the continuous portion than the first portion, and the out-of-plane direction of the first portion is closer to the vertical direction than the out-of-plane direction of the second portion.

7. A semiconductor device comprising: a semiconductor layer having a first trench in an active region and a second trench in a termination region, the second trench being wider than the first trench; a gate electrode provided in the first trench with a first insulating film interposed therebetween; a first interlayer insulating film provided in the first trench above the gate electrode; and a second interlayer insulating film provided on the bottom surface of the second trench and on the side surface on the active region side with a second insulating film interposed therebetween; wherein a termination electrode including a tapered portion that narrows toward the upper side is not provided in the second trench.

8. A method for manufacturing a semiconductor device, comprising: forming a first trench in an active region of a semiconductor layer; forming a second trench in a termination region of the semiconductor layer, the second trench being wider than the first trench; forming a gate electrode in the first trench with a first insulating film interposed therebetween; and forming a termination electrode made of the same material as the gate electrode on a bottom surface of the second trench and on a side surface on the active region side with a second insulating film interposed therebetween; forming a first interlayer insulating film in the first trench above the gate electrode; and forming a second interlayer insulating film on the termination electrode; the termination electrode comprising: a tapered portion provided along the side surface of the second trench and tapering upward; and a continuous portion provided along the bottom surface of the second trench and continuous with the tapered portion.

9. A method for manufacturing a semiconductor device, comprising: forming a first trench in an active region of a semiconductor layer; forming a second trench in an end region of the semiconductor layer, the second trench being wider than the first trench; forming a gate electrode in the first trench via a first insulating film; but not forming an end electrode in the second trench that includes a tapered portion that narrows toward the top and is made of the same material as the gate electrode; forming a first interlayer insulating film in the first trench above the gate electrode; and forming a second interlayer insulating film on the bottom surface of the second trench and on the side surface on the active region side via a second insulating film.

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