Multilayer ceramic capacitor

Abstract

The present invention addresses the problem of providing a multilayer ceramic capacitor having a reduced size and increased capacity, as well as high moisture resistance reliability and impact resistance.　A multilayer ceramic capacitor 1 includes: a laminate 10 including an inner layer part 100 in which internal electrode layers 30 and dielectric layers 20 are laminated; and external electrodes respectively arranged on two end faces LS. When viewed from the end face LS, the multilayer ceramic capacitor 1 includes a central region RC provided with internal electrode layers 30 having a length of 95-105% in the width direction W, and an outside region RG provided with an internal electrode layer 30 having a length of 70% or more and less than 95% in the width direction W, with respect to the length in the width direction W of an internal electrode layer 30 arranged in the center of the inner layer part 100 in the lamination direction T. In the lamination direction T, two of said outside regions RG are arranged so as to sandwich the central region RC.

Description

Multilayer ceramic capacitors

[0001] The present invention relates to a multilayer ceramic capacitor.

[0002] Multilayer ceramic capacitors have been widely used in various electronic devices, such as mobile terminal devices such as mobile phones and personal computers. However, with the recent development of electronic devices, there is a demand for further miniaturization, higher capacitance, and high moisture resistance.

[0003] Generally, a multilayer ceramic capacitor has a structure comprising a laminate having a substantially rectangular parallelepiped shape, which has an inner layer portion in which dielectric layers and internal electrode layers are alternately stacked, and outer layer portions formed by stacking dielectric layers on the upper and lower parts of the inner layer portion, and external electrodes on both longitudinal end surfaces of the laminate, and the external electrodes are arranged so as to extend continuously from the end surfaces and cover part of the main surface and side surfaces.

[0004] Japanese Patent Application Laid-Open No. 2015-216337

[0005] However, the thickness of the external electrodes is thin at ridges formed by joining any two of the end faces, main surfaces, and side surfaces of the laminate, and at corners formed by the intersection of three ridges. Furthermore, among the internal electrode layers stacked in the stacking direction, the upper and lower internal electrode layers are easily routed to the ridges and corners of the laminate, making them prone to moisture penetration. In particular, moisture is prone to penetrate the corners of the laminate, and the penetrated moisture easily reaches the internal electrode layers, which can easily cause a loss of moisture resistance reliability. Furthermore, the corners of the laminate are prone to external impact, which can easily lead to failure.

[0006] An object of the present invention is to provide a multilayer ceramic capacitor that is small in size, has a high capacitance, and is highly reliable in terms of moisture resistance and impact resistance.

[0007] The inventors discovered that high moisture resistance reliability and impact resistance can be achieved by adjusting the width direction length of the internal electrode layers that constitute a multilayer ceramic capacitor at the end faces of the laminate, and have completed the present invention.

[0008] That is, the present invention provides a multilayer ceramic capacitor comprising: an inner layer portion in which internal electrode layers and dielectric layers are stacked, and a laminate having two main surfaces opposing each other in the stacking direction, two side surfaces opposing each other in a width direction intersecting the stacking direction, and two end faces opposing each other in a length direction intersecting the stacking direction and the width direction; and external electrodes arranged on the two end faces, respectively, wherein, when viewed from the end faces, the laminate comprises: a central region in which internal electrode layers are arranged whose length in the width direction is 95% or more and 105% or less of the length in the width direction of internal electrode layers arranged at the center in the stacking direction of the inner layer portion; and outer regions in which internal electrode layers are arranged whose length in the width direction is 70% or more and less than 95%, and the two outer regions are arranged so as to sandwich the central region in the stacking direction.

[0009] According to the present invention, it is possible to provide a multilayer ceramic capacitor that prevents moisture from penetrating into the internal electrode layers and has high moisture resistance reliability.

[0010] Furthermore, according to the present invention, it is possible to provide a multilayer ceramic capacitor that has excellent impact resistance while maintaining capacitance.

[0011] 1 is a perspective view showing a multilayer ceramic capacitor according to an embodiment of the present invention. FIG. 1 is a cross-sectional view (LT cross-section) of the multilayer ceramic capacitor shown in FIG. 1 taken along line II-II. FIG. 2 is a cross-sectional view (WT cross-section) of the multilayer ceramic capacitor shown in FIG. 1 taken along line III-III. FIG. 3 is a cross-sectional view (WT cross-section) of the multilayer ceramic capacitor shown in FIG. 1 taken along line IV-IV. FIG. 4 is a cross-sectional view (LW cross-section) of the multilayer ceramic capacitor shown in FIG. 4 taken along line VI-VI. FIG. 5 is a cross-sectional view (LW cross-section) of the multilayer ceramic capacitor shown in FIG. 4 (First Embodiment). FIG. 6 is a cross-sectional view (LW cross-section) of the multilayer ceramic capacitor shown in FIG. 4 (Second Embodiment). FIG. 7 is a cross-sectional view (LW cross-section) of the multilayer ceramic capacitor shown in FIG. 4 (Third Embodiment). FIG. 8 is a cross-sectional view (LW cross-section) of the multilayer ceramic capacitor shown in FIG. 4 (Fourth Embodiment). FIG. 9 is a cross-sectional view (WT cross-section) of the multilayer ceramic capacitor shown in FIG. 1 taken along line III-III. FIG. 10 is a cross-sectional view (WT cross-section) of the multilayer ceramic capacitor shown in FIG. 1 (Fifth Embodiment). Two internal electrode patterns formed on a dielectric sheet are shown. Two internal electrode patterns formed on a dielectric sheet are shown. 2A to 2C are diagrams illustrating steps for forming the multilayer ceramic capacitor shown in Fig. 1. FIG. 2A to 2C are diagrams illustrating steps for forming the multilayer ceramic capacitor shown in Fig. 1.

[0012] Hereinafter, embodiments of the multilayer ceramic capacitor of the present invention will be described, but the present invention is not limited thereto. Furthermore, the drawings may be drawn in a simplified and schematic manner to explain the contents of the invention, and the dimensional ratios of the depicted components or between the components may not match the dimensional ratios of those components described in the specification. Furthermore, components described in the specification may be omitted in the drawings, or the number of components may be omitted.

[0013] (Multilayer Ceramic Capacitor) Fig. 1 is a perspective view showing a multilayer ceramic capacitor, Fig. 2 is a cross-sectional view of the multilayer ceramic capacitor shown in Fig. 1 taken along line II-II, and Fig. 3 is a cross-sectional view of the multilayer ceramic capacitor shown in Fig. 1 taken along line III-III. Fig. 4 is a cross-sectional view of the multilayer ceramic capacitor shown in Fig. 1 taken along line IV-IV. Fig. 5 is a cross-sectional view of line V-V shown in Fig. 4. Fig. 6 is a cross-sectional view of line VI-VI shown in Fig. 4. The multilayer ceramic capacitor 1 shown in Figs. 1 to 6 includes a laminate 10 and external electrodes 40. The external electrodes 40 include a first external electrode 41 and a second external electrode 42.

[0014] 1 to 6 show an XYZ Cartesian coordinate system. The X direction is the length direction L of the multilayer ceramic capacitor 1 and the laminate 10, the Y direction is the width direction W of the multilayer ceramic capacitor 1 and the laminate 10, and the Z direction is the lamination direction T of the multilayer ceramic capacitor 1 and the laminate 10. Therefore, the cross section shown in FIG. 2 is also called an LT cross section, the cross sections shown in FIGS. 3 and 4 are also called WT cross sections, and the cross sections shown in FIGS. 5 and 6 are also called LW cross sections.

[0015] The length direction L, width direction W, and stacking direction T do not necessarily have to be perpendicular to each other, and may intersect each other.

[0016] The laminate 10 has a substantially rectangular parallelepiped shape and has a first main surface TS1 and a second main surface TS2 that face each other in the stacking direction T, a first side surface WS1 and a second side surface WS2 that face each other in the width direction W, and a first end surface LS1 and a second end surface LS2 that face each other in the length direction L. The surface of each surface may be uneven or may be roughened.

[0017] When there is no need to distinguish between the first main surface TS1 and the second main surface TS2, they will be collectively referred to as the main surface TS; when there is no need to distinguish between the first side surface WS1 and the second side surface WS2, they will be collectively referred to as the side surface WS; and when there is no need to distinguish between the first end surface LS1 and the second end surface LS2, they will be collectively referred to as the end surface LS.

[0018] It is preferable that the ridges and corners of the laminate 10 are rounded. A ridge is a portion where two surfaces of the laminate 10 intersect, and a corner is a portion where three surfaces of the laminate 10 intersect.

[0019] 2 and 3 , the laminate 10 has a plurality of dielectric layers 20 and a plurality of internal electrode layers 30 stacked in a stacking direction T. The laminate 10 also has, in the stacking direction T, an inner layer portion 100, and a first outer layer portion 201 and a second outer layer portion 202 arranged to sandwich the inner layer portion 100.

[0020] The internal layer portion 100 includes a plurality of dielectric layers 20i and a plurality of internal electrode layers 30. The internal layer portion 100 is a region in which the dielectric layers 20i and the internal electrode layers 30 are alternately stacked, and is sandwiched between the internal electrode layers 30 located at both ends in the stacking direction T. The internal layer portion 100 is a portion in which the plurality of internal electrode layers 30 are arranged opposite each other via the dielectric layers 20i, and generates electrostatic capacitance and essentially functions as a capacitor.

[0021] The first outer layer portion 201 is disposed on the first main surface TS1 side of the laminate 10, and the second outer layer portion 202 is disposed on the second main surface TS2 side of the laminate 10. More specifically, the first outer layer portion 201 is disposed between the first main surface TS1 and an internal electrode layer 30 of the plurality of internal electrode layers 30 that is closest to the first main surface TS1, and the second outer layer portion 202 is disposed between the second main surface TS2 and an internal electrode layer 30 of the plurality of internal electrode layers 30 that is closest to the second main surface TS2. The first outer layer portion 201 and the second outer layer portion 202 do not include the internal electrode layer 30.

[0022] The material of the dielectric layer 20 is, for example, BaTiO ３ , CaTiO ３ , SrTiO ３ , or CaZrO ３ A dielectric ceramic containing, as a main component, a Mn compound, an Fe compound, a Cr compound, a Co compound, a Ni compound, or the like may be added to the material of the dielectric layer 20 as a secondary component.

[0023] The thickness of the dielectric layer 20 is not particularly limited, but is preferably 0.40 μm or more and 0.50 μm or less, and more preferably 0.40 μm or more and 0.45 μm or less. The number of dielectric layers 20 is not particularly limited, but is preferably 100 to 2000. The number of dielectric layers 20 is the total number of the dielectric layers 20i of the inner layer portion 100 and the dielectric layers 20o of the outer layer portion 200.

[0024] The multiple internal electrode layers 30 include multiple first internal electrode layers 31 and multiple second internal electrode layers 32. The multiple first internal electrode layers 31 and the multiple second internal electrode layers 32 are alternately arranged in the stacking direction T of the laminate 10.

[0025] The first internal electrode layer 31 includes a facing portion 311 and a lead portion 312 , and the second internal electrode layer 32 includes a facing portion 321 and a lead portion 322 .

[0026] The opposing portion 311 of the first internal electrode layer 31 and the opposing portion 321 of the second internal electrode layer 32 face each other via the dielectric layer 20i in the stacking direction T of the laminate 10. The shapes of the opposing portions 311 and 321 are not particularly limited and may be, for example, approximately rectangular. The opposing portions 311 and 321 are portions that generate electrostatic capacitance and essentially function as capacitors.

[0027] The lead portion 312 of the first internal electrode layer 31 extends from the opposing portion 311 toward the first end face LS1 of the laminate 10 and is exposed at the first end face LS1. The lead portion 322 of the second internal electrode layer 32 extends from the opposing portion 321 toward the second end face LS2 of the laminate 10 and is exposed at the second end face LS2.

[0028] As a result, the first internal electrode layer 31 is connected to the first external electrode 41, and a gap is provided between the first internal electrode layer 31 and the second end surface LS2 of the laminate 10, i.e., the second external electrode 42. In addition, the second internal electrode layer 32 is connected to the second external electrode 42, and a gap is provided between the second internal electrode layer 32 and the first end surface LS1 of the laminate 10, i.e., the first external electrode 41.

[0029] The first internal electrode layer 31 and the second internal electrode layer 32 contain metal Ni as a main component. The first internal electrode layer 31 and the second internal electrode layer 32 may contain at least one selected from metals such as Cu, Ag, Pd, or Au, or alloys containing at least one of these metals, such as an Ag-Pd alloy, as a main component or a component other than the main component. Furthermore, the first internal electrode layer 31 and the second internal electrode layer 32 may contain, as a component other than the main component, particles of a dielectric material having the same composition as the ceramic contained in the dielectric layer 20i. In this specification, the term "main component metal" refers to the metal component with the highest weight percentage.

[0030] The thickness of the first internal electrode layer 31 and the second internal electrode layer 32 is not particularly limited, but is preferably, for example, 0.30 μm or more and 0.40 μm or less, and more preferably, 0.30 μm or more and 0.35 μm or less. The number of the first internal electrode layer 31 and the second internal electrode layer 32 is not particularly limited, but is preferably, for example, 10 to 1000.

[0031] The thicknesses of the dielectric layers 20i and the internal electrode layers 30 may be measured by, for example, observing the LT cross section of the laminate exposed by polishing near the center in the width direction with a scanning electron microscope. Each value may be an average value of measurements taken at multiple locations in the length direction, or may be an average value of measurements taken at multiple locations in the stacking direction.

[0032] 3 , the laminate 10 has, in the width direction W, an electrode opposing portion W30 where the internal electrode layers 30 are opposed to each other, and a first side margin portion WG1 and a second side margin portion WG2 arranged to sandwich the electrode opposing portion W30. The electrode opposing portion W30 is composed of an inner layer portion 100 where the internal electrode layers 30 and the dielectric layers 20i are stacked, and two outer layer portions 200 arranged to sandwich the inner layer portion 100 from the stacking direction T. In other words, the first side margin portion WG1 and the second side margin portion WG2 are arranged to sandwich the inner layer portion 100 and the two outer layer portions 200 from the width direction W.

[0033] The first side margin WG1 is located between the electrode opposing portion W30 and the first side surface WS1, and the second side margin WG2 is located between the electrode opposing portion W30 and the second side surface WS2. More specifically, the first side margin WG1 is located between the end of the internal electrode layer 30 on the first side surface WS1 side and the first side surface WS1, and the second side margin WG2 is located between the end of the internal electrode layer 30 on the second side surface WS2 side and the second side surface WS2. The first side margin WG1 and the second side margin WG2 do not include the internal electrode layer 30, but include only the dielectric layer 20. The first side margin WG1 and the second side margin WG2 are also called side gaps or W gaps.

[0034] 3, the side margin portion WG can be composed of an inner layer WGi and an outer layer WGo laminated in the width direction W. The side margin portion WG may be composed of a single layer, or may be composed of three or more layers.

[0035] The inner layer WGi is a dielectric layer, for example, BaTiO ３ , CaTiO ３ , SrTiO ３ , CaZrO ３ The inner layer WGi may be made of a dielectric ceramic material containing, as a main component, SiO. ２ The main component can be, but is not limited to,

[0036] The inner layer WGi may contain a sintering-promoting element. Examples of the sintering-promoting element include Dy, Ni, Ba, B, Li, K, Na, Mn, Mg, Ho, Ca, and V. The sintering-promoting element may be one type or two or more types. The inner layer WGi of this embodiment preferably contains a larger amount of the sintering-promoting element than the dielectric layer 20. The thickness of the inner layer WGi in the width direction W is preferably 0.1 μm or more and 10 μm or less.

[0037] The outer layer WGo is a dielectric layer, for example, BaTiO ３ , CaTiO ３, SrTiO ３ , CaZrO ３ The outer layer WGo may be made of a dielectric ceramic material containing, as a main component, SiO. ２ The main component can be, but is not limited to,

[0038] The side margin portion WG can be formed by attaching a side covering portion SC for forming the side margin portion WG to both sides in the width direction W of the laminate chip 10T for forming the inner layer portion 100 and the outer layer portion 200, as described below.

[0039] 2 , the laminate 10 has, in the longitudinal direction L, an electrode facing portion L30 where the first internal electrode layer 31 and the second internal electrode layer 32 of the internal electrode layer 30 face each other, a first end margin LG1, and a second end margin LG2. The first end margin LG1 is located between the electrode facing portion L30 and the first end face LS1, and the second end margin LG2 is located between the electrode facing portion L30 and the second end face LS2. More specifically, the first end margin LG1 is located between the end of the second internal electrode layer 32 on the first end face LS1 side and the first end face LS1, and the second end margin LG2 is located between the end of the first internal electrode layer 31 on the second end face LS2 side and the second end face LS2.

[0040] The first end margin LG1 includes the first internal electrode layer 31 and the dielectric layer 20, but does not include the second internal electrode layer 32. Therefore, a dielectric layer 20z having a thickness equivalent to that of the second internal electrode layer 32 can be disposed, thereby eliminating a step at the end of the second internal electrode layer 32 on the first end face LS1 side. The second end margin LG2 includes the second internal electrode layer 32 and the dielectric layer 20, but does not include the first internal electrode layer 31. Therefore, a dielectric layer 20z having a thickness equivalent to that of the first internal electrode layer 31 can be disposed, thereby eliminating a step at the end of the first internal electrode layer 31 on the second end face LS2 side. Note that the dielectric layer 20z does not necessarily have to be disposed, and the laminate 10 may be formed without disposing the dielectric layer 20z.

[0041] The first end margin LG1 is a portion that functions as an extraction electrode portion to the first end face LS1 of the first internal electrode layer 31, and the second end margin LG2 is a portion that functions as an extraction electrode portion to the second end face LS2 of the second internal electrode layer 32. The first end margin LG1 and the second end margin LG2 are also referred to as an L gap.

[0042] The electrode opposing portion L30 is provided with the opposing portion 311 of the first internal electrode layer 31 and the opposing portion 321 of the second internal electrode layer 32. The first end margin portion LG1 is provided with the lead portion 312 of the first internal electrode layer 31, and the second end margin portion LG2 is provided with the lead portion 322 of the second internal electrode layer 32.

[0043] An example of a method for measuring the thickness of each portion of the laminate 10 is to observe, using a scanning electron microscope, an LT cross section near the center of the width direction of the laminate exposed by polishing, or a WT cross section near the center of the length direction of the laminate exposed by polishing. Each value may also be the average of measurements taken at multiple locations in the length or width direction. Similarly, an example of a method for measuring the length of each portion of the laminate 10 is to observe, using a scanning electron microscope, an LT cross section near the center of the width direction of the laminate exposed by polishing. Each value may also be the average of measurements taken at multiple locations in the stacking direction. Similarly, an example of a method for measuring the width of each portion of the laminate 10 is to observe, using a scanning electron microscope, a WT cross section near the center of the length direction of the laminate exposed by polishing. Each value may also be the average of measurements taken at multiple locations in the stacking direction.

[0044] The external electrodes 40 include a first external electrode 41 and a second external electrode 42 .

[0045] The first external electrode 41 is disposed on the first end face LS1 of the laminate 10 and is connected to the first internal electrode layer 31. The first external electrode 41 may extend from the first end face LS1 to a portion of the first main surface TS1 and a portion of the second main surface TS2. Alternatively, the first external electrode 41 may extend from the first end face LS1 to a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0046] The second external electrode 42 is disposed on the second end face LS2 of the laminate 10 and is connected to the second internal electrode layer 32. The second external electrode 42 may extend from the second end face LS2 to a portion of the first main face TS1 and a portion of the second main face TS2. The second external electrode 42 may also extend from the second end face LS2 to a portion of the first side face WS1 and a portion of the second side face WS2.

[0047] The first external electrode 41 has a base electrode layer 415 and a plating layer 416, and the second external electrode 42 has a base electrode layer 425 and a plating layer 426. The first external electrode 41 may be composed of only the plating layer 416, and the second external electrode 42 may be composed of only the plating layer 426.

[0048] The base electrode layers 415, 425 may be fired layers containing a metal and glass. Examples of the glass include glass components containing at least one selected from B, Si, Ba, Mg, Al, Li, and the like. Specific examples include borosilicate glass. The metal contains Cu as a main component. The metal may contain at least one selected from metals such as Ni, Ag, Pd, and Au, or alloys such as Ag-Pd alloys, as a main component, or may contain at least one selected from the group consisting of Ni, Ag, Pd, and Au, as a main component, or as a component other than the main component.

[0049] The fired layer is a layer formed by applying a conductive paste containing metal and glass to the laminate by a dipping method and firing the layer. The fired layer may be fired after firing the internal electrode layer or simultaneously with firing the internal electrode layer. The fired layer may also be a multi-layer structure.

[0050] Alternatively, the base electrode layers 415 and 425 may be resin layers containing conductive particles and a thermosetting resin. The resin layers may be formed on the fired layer described above, or may be formed directly on the laminate without forming a fired layer.

[0051] The resin layer is a layer formed by applying a conductive paste containing conductive particles and a thermosetting resin to the laminate by a coating method and then firing the layer. The resin layer may be fired after firing the internal electrode layer or simultaneously with firing the internal electrode layer. The resin layer may also be a multi-layered layer.

[0052] The thickness of each of the base electrode layers 415, 425 as the fired layer or resin layer is not particularly limited, and may be 1 μm or more and 10 μm or less.

[0053] Alternatively, the base electrode layers 415 and 425 may be thin film layers of 1 μm or less formed by a thin film forming method such as sputtering or vapor deposition, and on which metal particles are deposited.

[0054] The plating layer 416 covers at least a portion of the base electrode layer 415, and the plating layer 426 covers at least a portion of the base electrode layer 425. The plating layers 416 and 426 include, for example, at least one selected from metals such as Cu, Ni, Ag, Pd, and Au, and alloys such as Ag—Pd alloys.

[0055] The plating layers 416, 426 may each be formed of multiple layers. Preferably, they have a two-layer structure of Ni plating and Sn plating. The Ni plating layer can prevent the base electrode layer from being eroded by solder when mounting the ceramic electronic component, and the Sn plating layer improves the wettability of the solder when mounting the ceramic electronic component, facilitating mounting. The plating layers 416, 426 may each have a three-layer structure, for example, by stacking Sn plating, Ni plating, and Sn plating. The outermost layer may be Au plating.

[0056] The thickness of each of the plating layers 416, 426 is not particularly limited, and may be 1 μm or more and 10 μm or less.

[0057] (Central region RC and outer regions RG) In the multilayer ceramic capacitor 1 of the present invention, as shown in Figure 4, when the end surface LS of the laminate 10 is viewed from the longitudinal direction L, one central region RC is arranged so as to be sandwiched between two outer regions RG from the stacking direction T.

[0058] The central region RC is a region in which the internal electrode layers 30 are arranged with a length in the width direction W of 95% or more and 105% or less of the length in the width direction W of the internal electrode layer 30C arranged at the center in the stacking direction T of the internal layer portion 100. The outer region RG is a region in which the internal electrode layers 30 are arranged with a length in the width direction W of 70% or more and less than 95% of the length in the width direction W of the internal electrode layer 30C arranged at the center in the stacking direction T of the internal layer portion 100.

[0059] Here, the centrally arranged internal electrode layer 30C refers to the internal electrode layer 30 among the multiple stacked internal electrode layers 30 for which the difference between the distance from the internal electrode layer 30 closest to the first main surface TS1 and the distance from the internal electrode layer 30 closest to the second main surface TS2 is the smallest.

[0060] In this way, by arranging the central region RC between the two outer regions RG in the stacking direction T on the end surface LS of the laminate 10, it is possible to lengthen the path that the infiltrated moisture takes to reach the internal electrode layers 30, thereby improving the moisture resistance reliability of the multilayer ceramic capacitor 1. Note that, in the outer regions RG, if the length in the width direction W of the internal electrode layers 30 is 95% or more of the length in the width direction W of the internal electrode layers 30C arranged at the center in the stacking direction T, the length of the path that the infiltrated moisture takes to reach the internal electrode layers 30 cannot be sufficiently maintained, and therefore the moisture resistance reliability cannot be improved. On the other hand, if the length in the width direction W of the internal electrode layers 30 in the outer regions RG is less than 70% of the length in the width direction W of the internal electrode layers 30C arranged at the center in the stacking direction T, it is not possible to maintain good electrical connection with the external electrodes 40.

[0061] Furthermore, the internal electrode layer 30 in the outer region RG can be positioned at a longer distance from the corner formed by the joining of the three surfaces of the laminate 10, namely, the end surface LS, the main surface TS, and the side surface WS, thereby improving impact resistance while minimizing the reduction in capacitance.

[0062] It is preferable that the length in the stacking direction T of the central region RC is 40% to 80% of the length in the stacking direction T of the inner layer portion 100, and the length in the stacking direction T of the outer region RG is 10% to 30% of the length in the stacking direction T of the inner layer portion 100. In this way, by forming the inner layer portion 100 from the central region RC and the outer region RG, it is possible to more reliably improve the moisture resistance reliability.

[0063] When the end face LS of the laminate 10 is viewed from the longitudinal direction L, the internal electrode layer 30 has a central region RC in which the internal electrode layer 30 has a length in the width direction W that is 95% or more and 105% or less of the length in the width direction W of the internal electrode layer 30C arranged at the center in the stacking direction T of the inner layer portion 100, and an outer region RG in which the internal electrode layer 30 has a length in the width direction W that is 70% or more and less than 95% of the length in the width direction W. Examples of shapes of the internal electrode layer 30 for forming these regions are shown below.

[0064] The shape of the internal electrode layer 30 in the center region RC may be, for example, as shown in Fig. 5 , such that the opposing portion 321 and the lead portion 322 have the same length in the width direction W. The shape of the internal electrode layer 30 in the outer region RG may be, for example, as shown in Fig. 6 , such that the length in the width direction W of the lead portion 322 gradually decreases toward the exposed second end face LS2 (first embodiment). Here, the width direction length of the lead portion 322 of the portion exposed at the end face LS of the internal electrode layer 30C in the center in the stacking direction T of the internal layer portion 100 is 95% to 105% of the width direction W length of the portion exposed at the end face LS of the internal electrode layer 30C arranged at the center in the stacking direction T of the internal layer portion 100 ( Fig. 5 ). Furthermore, the width direction length of the lead portion 322 of the portion exposed at the end face LS of the internal electrode layer 30C in the outer region RG is 70% to 95% of the width direction W length of the portion exposed at the end face LS of the internal electrode layer 30C arranged at the center in the stacking direction T of the internal layer portion 100 ( Fig. 6 ). 5 and 6 show the shape of the second internal electrode layer 32, the first internal electrode layer 31 can have the same shape as the second internal electrode layer 32 except that the lead portion is provided on the first end face side LS1. Therefore, the shape of the first internal electrode layer 31 can be obtained by flipping the shapes shown in FIGS. 5 and 6 left to right.

[0065] 7 , the internal electrode layer 30 in the outer region RG can have a rectangular drawn-out portion 322 whose length in the width direction W is shorter than that of the facing portion 321 (second embodiment). Here, the width direction length of the drawn-out portion 322 of the portion exposed at the end face LS of the internal electrode layer 30 in the outer region RG is 70% or more and less than 95% of the width direction W length of the portion exposed at the end face LS of the internal electrode layer 30C arranged at the center in the stacking direction T of the internal layer section 100. Note that while FIG. 7 shows the shape of the second internal electrode layer 32, the first internal electrode layer 31 can have the same shape as the second internal electrode layer 32 except that the drawn-out portion is provided on the first end face LS1 side. Therefore, the shape of the first internal electrode layer 31 can be obtained by left-right reversing the shape shown in FIG. 7 .

[0066] Furthermore, the internal electrode layer 30 in the outer region RG preferably has a minimum width portion SS, in which the length in the width direction W is minimum, in the lead portions 312, 322, closer to the center in the length direction L than the end face LS. With such a shape, the path taken by infiltrated moisture to reach the internal electrode layer 30 is lengthened, improving moisture resistance, and the length in the width direction W of the lead portions 312, 322 exposed at the end face LS can be maintained, thereby maintaining good electrical connection with the external electrode 40.

[0067] 8, the internal electrode layer 30 may have a shape in which the lead portion 322 is trapezoidal and the shorter of the opposite parallel sides is connected to the facing portion 321, thereby forming a minimum width portion SS at the boundary between the facing portion 321 and the lead portion 322 (third embodiment). In the internal electrode layer 30 shaped as shown in FIG. 8, the length in the width direction W of the lead portion 322 can be made largest at the portion exposed to the end face LS, thereby improving the electrical connection with the external electrode 40.

[0068] 9, for example, both sides of the lead portion 322 of the internal electrode layer 30 in the width direction W can be recessed in an arc shape, and the portion where the vertices of the two arcs face each other can be made to have a minimum width portion SS (fourth embodiment). In this way, by forming both sides of the lead portion 322 in an arc shape, it is possible to relieve stress that occurs during manufacturing, etc.

[0069] 8 and 9 both show the shape of the second internal electrode layer 32, but the first internal electrode layer 31 can have the same shape as the second internal electrode layer 32 except that the lead portion is provided on the first end face LS1 side. Therefore, the shape of the first internal electrode layer 31 can be obtained by flipping the shapes shown in FIGS. 8 and 9 left and right.

[0070] (Confirming the shape of the internal electrode layers) The shape of the internal electrode layers can be confirmed by the following method. 1. Prepare multiple samples of multilayer ceramic capacitors. 2. Using one sample, polish it so that the end face of the laminate is exposed, and observe the end face of the laminate using an optical microscope. 3. Measure the positions of the outer layer portion, outer region, and central region in the stacking direction. 4. Using the other sample, polish it so that the LW cross section parallel to the length and width directions is exposed, based on the position information of the outer layer portion, outer region, and central region in the stacking direction measured in 3 above. Observe the exposed LW cross section using an optical microscope, and measure the dimensions of the internal electrode layer in each region.

[0071] (glass area)

[0072] When the end surface LS of the laminate 10 is viewed from the longitudinal direction L, the multilayer ceramic capacitor 1 preferably includes a glass region GL in which Si segregates in the side margin portion WG of the laminate 10, as shown in FIG. 10 . More specifically, the glass region GL is preferably included in the inner layer WGi. By providing the glass region GL in the side margin portion WG, particularly the inner layer WGi, the external electrode 40 disposed on the end surface LS of the laminate 10 is more easily adhered to the laminate 10, ensuring the sealing of the end surface LS by the external electrode 40. This improves moisture resistance reliability while also improving adhesion between the side margin portion WG and the inner layer portion 100 and the outer layer portion 200. This enables miniaturization and high capacitance while further improving moisture resistance reliability.

[0073] When viewing the end face LS of the laminate 10, the glass region GL is preferably located at least within the side margins WG located on both sides of the outer region RG in the width direction W. By locating the glass region GL in such a position, the bond between the external electrode 40 and the laminate 10 is strengthened, the sealing performance of the end face LS by the external electrode 40 is improved, and moisture resistance reliability is reliably ensured.

[0074] The glass region GL can be arranged continuously within the side margins WG located on both sides of the inner layer section 100 and the two outer layer sections 200 in the width direction W. By arranging the glass region GL continuously within the side margins WG located on both sides of the inner layer section 100 and the two outer layer sections 200 in this way, the bond between the external electrode 40 and the laminate 10 becomes stronger, the sealing performance of the end face LS by the external electrode 40 is improved, and moisture resistance reliability is more reliably ensured.

[0075] When viewing the end surface LS of the laminate 10, the length in the width direction W of the internal electrode layer 30 in the outer region RG is 70% or more and less than 95% of the length in the width direction W of the internal electrode layer 30C arranged at the center in the stacking direction T, and therefore the internal electrode layer 30 in the outer region RG does not contact the side margin portion WG in the width direction W. Therefore, at the interface between the outer region RG and the side margin portion WG, the dielectric layer 20 in the outer region RG and the side margin portion WG are continuously bonded in the stacking direction T. In this way, the dielectric layer 20 in the outer region RG and the side margin portion WG are continuously bonded in the stacking direction T, thereby preventing peeling of the side margin portion WG from the inner layer portion 100 and suppressing the occurrence of internal defects in the laminate 10.

[0076] (Method for detecting glass region) Elemental analysis of Si was performed on the end surface LS of the laminate 10 using wavelength dispersive X-ray analysis (WDX) and a scanning electron microscope (FE-WDX), and regions where the Si content was significantly higher than other regions were detected as glass regions.

[0077] (Manufacturing Method) An example of a manufacturing method for the above-mentioned multilayer ceramic capacitor 1 will be described. First, a dielectric sheet for the dielectric layers 20 and a conductive paste for the internal electrode layers 30 are prepared. The dielectric sheet and the conductive paste contain a binder and a solvent. Known materials can be used as the binder and the solvent.

[0078] Next, a conductive paste is printed on the dielectric sheet in a predetermined pattern, for example, to form an internal electrode pattern on the dielectric sheet. The internal electrode pattern can be formed by screen printing, gravure printing, or the like.

[0079] In mass production, a dielectric sheet with two internal electrode patterns as shown in FIG. 11 can be prepared. FIG. 11 shows an internal electrode pattern for forming a central region RC. The coated portions 30N coated with conductive paste are spaced apart in the longitudinal direction L, and ceramic paste is applied between adjacent coated portions 30N to form height adjustment portions 20N. The height adjustment portions 20N are coated with conductive paste to a thickness approximately equal to that of the coated portions 30N, thereby eliminating any unevenness on the dielectric sheet caused by the application of the conductive paste and smoothing the surface of the dielectric sheet coated with the conductive paste. As shown in FIG. 11, the two internal electrode layer patterns are printed with a shift in the longitudinal direction L. As described below, the dielectric sheets with the two internal electrode patterns are alternately stacked in the stacking direction T and cut along the cutting lines x and y in the stacking direction T to form the structure of the inner layer portion 100 in the central region RC.

[0080] Fig. 12 shows an internal electrode pattern for forming the outer region RG. In Fig. 12, the internal electrode pattern is such that the length in the width direction W is shorter at the end surface LS of the laminate 10 after firing. As shown in Fig. 12, the two internal electrode layer patterns are printed with a shift in the length direction L. As will be described later, by overlapping the dielectric sheets of the two internal electrode patterns alternately in the stacking direction T and cutting them in the stacking direction T along the cutting lines x and y, the structure of the internal layer portion 100 in the outer region RG can be formed.

[0081] The coated portion 30N to which the conductive paste is applied will form the first internal electrode layer 31 and the second internal electrode layer 32 of the inner layer portion 100 in the laminate 10 after firing, the height adjustment portion 20N will form the dielectric layer 20z of the inner layer portion 100, and the dielectric sheet will form the dielectric layer 20i of the inner layer portion 100.

[0082] To form the outer layer portion 200, a predetermined number of dielectric sheets for the second outer layer portion 202, on which no internal electrode patterns are printed, are stacked. Dielectric sheets for the inner layer portion 100 in the outer region RG, on which two internal electrode patterns are printed, are alternately stacked on top of these. Dielectric sheets for the inner layer portion 100 in the center region RC, on which two internal electrode patterns are printed, are alternately stacked on top of these. Furthermore, dielectric sheets for the inner layer portion 100 in the outer region RG, on which two internal electrode patterns are printed, are alternately stacked on top of these. Then, a predetermined number of dielectric sheets for the first outer layer portion 201, on which no internal electrode patterns are printed, are stacked. In this way, a laminated sheet is produced.

[0083] Next, the laminated sheet is pressed in the stacking direction by means of a hydrostatic press or the like to produce a laminated block, which is then cut to a predetermined size in the stacking direction T along cutting lines x and y shown in Figures 11 and 12 to cut out laminate chips 10T.

[0084] As shown in Figure 13, the laminate chip 10T is formed in an approximately rectangular shape by alternately stacking multiple material sheets on the surface of the laminate ceramic green sheet 120, which becomes the dielectric layer 20, with a conductive pattern 131 that becomes the first internal electrode layer 31 printed on the surface and a conductive pattern 132 that becomes the second internal electrode layer 32 printed on the surface.

[0085] Of the pair of end faces 10Ta of the laminated chip 10T, a conductive pattern 131 is exposed on one end face, and a conductive pattern 132 is exposed on the other end face.

[0086] Furthermore, on the side surface 10Tp3 of the stacked chip 10T, all ends in the width direction W of the stacked conductive patterns 131 and 132 are aligned along the stacking direction T.

[0087] Similarly, on the side surface 10Tp4 of the stacked chip 10T, all ends in the width direction W of the stacked conductive patterns 131 and 132 are aligned along the stacking direction T.

[0088] A side surface covering portion SC for forming a first side margin portion WG1 and a second side margin portion WG2 is attached to the side surface 10Tp3 and the side surface 10Tp4 of the stacked chip 10T so as to cover them, respectively.

[0089] The side surface covering portion SC can be configured by a side surface covering portion SC1 and a side surface covering portion SC2. The side surface covering portion SC1 becomes the inner layer WGi, and the side surface covering portion SC2 becomes the outer layer WGo.

[0090] The ceramic slurry for the side covering portion SC1 and the side covering portion SC2 is prepared by preparing a perovskite-type compound containing Ba and Ti as a dielectric ceramic material, and mixing a dielectric powder obtained from this dielectric ceramic material with at least one of Si, Mg, and Ba as additives, as well as a binder resin, an organic solvent, a plasticizer, and a dispersant in a predetermined ratio. Si is added to the ceramic slurry for the side covering portion SC2. Specifically, Si is added so that the ratio of moles of Si to moles of Ti is 1.0 or more and 7.0 or less. Si is also added to the ceramic slurry for the side covering portion SC1. Specifically, Si is added so that the ratio of moles of Si to moles of Ti is 1.0 or more and 4.0 or less.

[0091] The side covering portion SC1, which becomes the inner layer WGi, is doped with sintering accelerators such as Dy, Ni, Ba, B, Li, K, Na, Mn, Mg, Ho, Ca, and V, and the sintering accelerators are contained in a higher concentration than in the dielectric sheet.

[0092] The ceramic slurry that will become the side surface covering portion SC2 formed on the surface of the resin film is applied and dried to obtain a ceramic green sheet that will become the side surface covering portion SC2.

[0093] Next, the ceramic slurry for the side covering portion SC1 is applied to the surface of the ceramic green sheet for the side covering portion SC2, and then dried to obtain a ceramic green sheet for the side covering portion SC1. In this manner, a ceramic green sheet for the side covering portion SC having a two-layer structure is obtained.

[0094] The ceramic slurry for the side surface covering portion SC1 contains an appropriate solvent to prevent dissolution of the ceramic green sheets that will become the side surface covering portions SC2.

[0095] Although the above describes a method for forming a ceramic green sheet that will become a two-layered side covering portion SC, it is possible to create a ceramic green sheet that will become a side covering portion with three or more layers by further stacking side covering portions.

[0096] Next, the ceramic green sheet that will become the side surface covering portion SC1 of the peeled ceramic green sheet that will become the side surface covering portion SC is placed opposite the side surface 10Tp3 of the laminated chip 10T and punched out, thereby attaching the side surface covering portion SC. The side surface covering portion SC is attached to the side surface 10Tp4 in the same manner.

[0097] As a result, an unfired laminate chip 10T with a side covering portion SC is formed, as shown in FIG. 14 . Next, this laminate chip 10T is fired to produce the laminate 10. The firing temperature, depending on the materials of the dielectric and internal electrodes, is preferably 900°C or higher and 1400°C or lower. Because the sintering accelerator in the side covering portion SC1 is contained at a higher concentration than the sintering accelerator in the dielectric sheet, the sintering accelerator diffuses from the laminate chip side of the side covering portion SC1 to the dielectric sheet during the firing process, making the side covering portion SC2 side of the side covering portion SC1, which has a higher sintering accelerator concentration, more easily sinter than the dielectric sheet side of the side covering portion SC1. As described above, due to the difference in sinterability during the firing process, the glass component with a relatively high sinterability concentrates on the dielectric sheet side of the side covering portion SC1, which has a relatively low sinterability, and Si segregates, forming the glass region GL.

[0098] Next, the first end surface LS1 of the laminate 10 is immersed in a conductive paste, which is an electrode material for the base electrode layer, using a dipping method, to apply the conductive paste for the base electrode layer 415 to the first end surface LS1. Similarly, the second end surface LS2 of the laminate 10 is immersed in a conductive paste, which is an electrode material for the base electrode layer, using a dipping method, to apply the conductive paste for the base electrode layer 425 to the second end surface LS2. These conductive pastes are then fired to form the fired layers, the base electrode layers 415 and 425. The firing temperature is preferably 600°C or higher and 900°C or lower.

[0099] As described above, the base electrode layer 415 and the base electrode layer 425, which are resin layers, may be formed by applying a conductive paste containing conductive particles and a thermosetting resin by a coating method and then baking the applied paste, or the base electrode layers 415 and 425, which are thin films, may be formed by a thin film formation method such as a sputtering method or a vapor deposition method.

[0100] Thereafter, a plating layer 416 is formed on the surface of the base electrode layer 415 to form the first external electrode 41, and a plating layer 426 is formed on the surface of the base electrode layer 425 to form the second external electrode 42. Through the above steps, the multilayer ceramic capacitor 1 described above is obtained.

[0101] Although the embodiments of the present invention have been described above, the present invention is not limited to the embodiments, and can be embodied in various forms without departing from the gist of the present invention.

[0102] The present invention includes the following combinations:

[0103] <1> A multilayer ceramic capacitor comprising: a laminate including an inner layer portion in which internal electrode layers and dielectric layers are stacked, the laminate having two main surfaces opposing each other in a stacking direction, two side surfaces opposing each other in a width direction intersecting the stacking direction, and two end faces opposing each other in a length direction intersecting the stacking direction and the width direction; and external electrodes arranged on the two end faces, respectively, wherein, when the end faces are viewed from the length direction, the laminate includes: a central region in which internal electrode layers are arranged, the length in the width direction being 95% or more and 105% or less of the length in the width direction of internal electrode layers arranged at the center in the stacking direction of the inner layer portions; and outer regions in which internal electrode layers are arranged, the length in the width direction being 70% or more and less than 95%,

[0104] <2> The multilayer ceramic capacitor according to <1>, wherein the length of the central region in the stacking direction is 40% to 80% of the length of the inner layer portion in the stacking direction, and the length of the outer region in the stacking direction is 10% to 30% of the length of the inner layer portion in the stacking direction.

[0105] <3> The multilayer ceramic capacitor according to <1> or <2>, wherein the internal electrode layers in the outer region include opposing portions where adjacent internal electrode layers in the stacking direction face each other, and lead portions that are drawn out from the opposing portions to end faces and connect to the external electrodes, and the lead portions include minimum width portions, the minimum width portions being located closer to the center in the length direction than the end faces.

[0106] <4> The multilayer ceramic capacitor according to any one of <1> to <3>, wherein the laminate has side margin portions on both sides in the width direction of the inner layer portion and two outer layer portions sandwiching the inner layer portion in the stacking direction, and includes a glass region in which Si segregates inside the side margin portions.

[0107] <5> The multilayer ceramic capacitor according to <4>, further comprising a glass region inside the side margin portion located on both sides of the outer region in the width direction.

[0108] <6> The multilayer ceramic capacitor according to <4> or <5>, which includes a continuous glass region inside the side margin portion located on both sides of the inner layer portion and the two outer layer portions in the width direction.

[0109] <7> The multilayer ceramic capacitor according to any one of <4> to <6>, wherein the dielectric layers in the outer regions and the side margin portions are continuously joined in the stacking direction.

[0110] 1 Multilayer ceramic capacitor 10 Laminate 20 Dielectric layer 20i Dielectric layer 20o Dielectric layer 20z Dielectric layer 30 Internal electrode layer 31 First internal electrode layer 311 Opposing portion 312 Lead portion 32 Second internal electrode layer 321 Opposing portion 322 Lead portion 40 External electrode 41 First external electrode 415 Base electrode layer 416 Plating layer 42 Second external electrode 425 Base electrode layer 426 Plating layer 100 Internal layer portion 200 External layer portion 201 First external layer portion 202 Second external layer portion L30 Electrode opposing portion LG1 First end margin portion LG2 Second end margin portion W30 Electrode opposing portion WG1 First side margin portion WG2 Second side margin portion L Length direction T Stacking direction W Width direction GL Glass region SS Minimum width portion TS Main surface TS1 First main surface TS2 Second main surface WS Side surface WS1 First side surface WS2 Second side surface LS End surface LS1 First end surface LS2 Second end surface

Claims

1. A multilayer ceramic capacitor comprising: an inner layer portion in which internal electrode layers and dielectric layers are laminated, and a laminate having two main surfaces opposing each other in the lamination direction, two side surfaces opposing each other in a width direction intersecting the lamination direction, and two end faces opposing each other in a length direction intersecting the lamination direction and the width direction; and external electrodes arranged on the two end faces, respectively, wherein, when the end faces are viewed from the length direction, the laminate comprises: a central region in which internal electrode layers are arranged whose length in the width direction is 95% or more and 105% or less of the length in the width direction of internal electrode layers arranged in the center of the lamination direction of the inner layer portion; and outer regions in which internal electrode layers are arranged whose length in the width direction is 70% or more and less than 95%, 2. The multilayer ceramic capacitor according to claim 1, wherein the length of said central region in said stacking direction is 40% to 80% of the length of said inner layer portion in said stacking direction, and the length of said outer region in said stacking direction is 10% to 30% of the length of said inner layer portion in said stacking direction.

3. A multilayer ceramic capacitor according to claim 1 or 2, wherein the internal electrode layers in the outer region comprise opposing portions where adjacent internal electrode layers in the stacking direction face each other, and lead-out portions that are drawn out from the opposing portions to the end faces and connect to the external electrodes, and the lead-out portions have minimum width portions, where the length in the width direction is minimum, located closer to the center in the longitudinal direction than the end faces.

4. A multilayer ceramic capacitor according to any one of claims 1 to 3, wherein the laminate has side margins on both sides in the width direction of the inner layer and two outer layer portions sandwiching the inner layer in the stacking direction, and the side margins include glass regions in which Si segregates.

5. The multilayer ceramic capacitor according to claim 4, further comprising glass regions inside the side margin portions located on both sides of the outer region in the width direction.

6. The multilayer ceramic capacitor according to claim 4 or 5, wherein a continuous glass region is included within the side margin portions located on both sides of the inner layer portion and the two outer layer portions in the width direction.

7. The multilayer ceramic capacitor according to claim 4, wherein the dielectric layers in the outer regions and the side margin portions are joined continuously in the lamination direction.

Images