SiC EPITAXIAL WAFER, METHOD FOR EVALUATING SiC EPITAXIAL WAFER, AND METHOD FOR MANUFACTURING SiC DEVICE

Abstract

An SiC epitaxial wafer according to the present embodiment comprises: an SiC substrate which has a micropipe; and an SiC epitaxial layer which is formed on the SiC substrate. The SiC epitaxial layer has a density of stacking faults caused by the micropipe of the SiC substrate of less than 0.067 per cm2.

Description

SiC epitaxial wafer, SiC epitaxial wafer evaluation method, and SiC device manufacturing method

[0001] This disclosure relates to a SiC epitaxial wafer, a method for evaluating the SiC epitaxial wafer, and a method for manufacturing a SiC device. This application claims priority to Japanese Patent Application No. 2024-072787, filed on April 26, 2024, the contents of which are incorporated herein by reference.

[0002] Silicon carbide (SiC) has a breakdown field that is one order of magnitude larger than that of silicon (Si) and a band gap that is three times larger. Silicon carbide (SiC) also has properties such as a thermal conductivity that is about three times higher than that of silicon (Si). Therefore, silicon carbide (SiC) is expected to be applied to power devices, high-frequency devices, and the like. In addition, devices using silicon carbide (SiC) can operate at high temperatures of 150°C or higher. For this reason, SiC epitaxial wafers have recently been used in the above-mentioned semiconductor devices.

[0003] A SiC epitaxial wafer is obtained by stacking a SiC epitaxial layer on the surface of a SiC substrate. Hereinafter, a substrate before stacking a SiC epitaxial layer will be referred to as a SiC substrate, and a substrate after stacking a SiC epitaxial layer will be referred to as a SiC epitaxial wafer. A SiC substrate is produced by slicing a SiC ingot. SiC devices such as power devices and high-frequency devices are obtained by forming devices in the SiC epitaxial layer of a SiC epitaxial wafer and then cutting the SiC epitaxial wafer into chips.

[0004] SiC epitaxial wafers generally contain inherent crystal defects. Some of these defects adversely affect subsequent processes and inhibit the normal operation of SiC devices. These defects are called killer defects.

[0005] Furthermore, Patent Document 1 describes the conversion of threading screw dislocations (TSDs) into flank-type stacking faults, which are said to have little effect on SiC devices.

[0006] International Publication No. 2013 / 150587

[0007] Large pit defects and triangular defects caused by micropipes in SiC substrates are known as killer defects. These defects can be identified by surface inspections such as photoluminescence inspection. When fabricating SiC devices, chips having large pit defects and triangular defects caused by micropipes in SiC substrates are removed as defective chips. However, even when using chips after removing these defective chips, defects may still occur.

[0008] The present disclosure has been made in consideration of the above-described problems, and aims to provide a SiC epitaxial wafer, a method for evaluating a SiC epitaxial wafer, and a method for manufacturing a SiC device, which have few stacking faults caused by micropipes in a SiC substrate.

[0009] (1) A SiC epitaxial wafer according to a first aspect includes a SiC substrate having micropipes and a SiC epitaxial layer formed on the SiC substrate, wherein the SiC epitaxial layer has a stacking fault density of 0.067 / cm due to the micropipes of the SiC substrate. ２ is less than.

[0010] (2) In the SiC epitaxial wafer according to the above aspect, the density of stacking faults caused by the micropipes in the SiC substrate is 0.03 / cm ２ The following is also acceptable.

[0011] (3) In the SiC epitaxial wafer according to the above aspect, the density of stacking faults caused by the micropipes in the SiC substrate is 0.02 / cm ２ The following is also acceptable.

[0012] (4) In the SiC epitaxial wafer according to the above aspect, the density of stacking faults caused by the micropipes in the SiC substrate is 0.01 / cm ２ The following is also acceptable.

[0013] (5) In the SiC epitaxial wafer according to the above aspect, the density of stacking faults caused by the micropipes in the SiC substrate is 0 / cm ２ That's fine too.

[0014] (6) The SiC epitaxial wafer according to the above aspect may have a diameter of 145 mm or more.

[0015] (7) The SiC epitaxial wafer according to the above aspect may have a diameter of 195 mm or more.

[0016] (8) A method for evaluating a SiC epitaxial wafer according to a second aspect includes the steps of: identifying the positions of micropipes in a SiC substrate; identifying the positions of stacking faults in a SiC epitaxial layer formed on the SiC substrate; and comparing the positions of the micropipes with the positions of the stacking faults to identify stacking faults in the SiC substrate that are caused by the micropipes.

[0017] (9) A method for manufacturing a SiC device according to a third aspect includes the steps of: performing the SiC epitaxial wafer evaluation method according to the above aspect; dividing the SiC epitaxial wafer into chips; and removing chips having stacking faults caused by the micropipes in the SiC substrate.

[0018] The SiC epitaxial wafer according to the above aspect has few stacking faults caused by micropipes in the SiC substrate.

[0019] 1A and 1B are cross-sectional and plan views of a SiC substrate according to an embodiment of the present invention;

[0020] The SiC epitaxial wafer and the like according to this embodiment will be described in detail below with reference to the drawings as appropriate. The drawings used in the following description may show characteristic portions enlarged for the sake of clarity, and the dimensional ratios of each component may differ from the actual ones. The materials, dimensions, and the like exemplified in the following description are merely examples, and the present invention is not limited thereto. Appropriate changes can be made within the scope of the present invention.

[0021] In this specification, individual orientations are indicated by [ ] and collective orientations by < >. For negative indices, a "-" (bar) is placed above the number in crystallography, but in this specification, a negative sign is placed before the number.

[0022] Fig. 1 is a cross-sectional view of a SiC epitaxial wafer 1 according to this embodiment. Fig. 2 is a plan view of the SiC epitaxial wafer 1 according to this embodiment.

[0023] The SiC epitaxial wafer 1 includes a SiC substrate 2 and a SiC epitaxial layer 3. The SiC epitaxial wafer 1 has a substantially circular shape in a plan view. The SiC epitaxial wafer 1 may have a notch 4 for determining the direction of the crystal axis. The SiC substrate 10 may have an orientation flat instead of the notch 4.

[0024] The diameter of the SiC epitaxial wafer 1 is, for example, 145 mm or more, preferably 149 mm or more. The diameter of the SiC epitaxial wafer 1 is preferably 155 mm or less, more preferably 151 mm or less. The diameter of the SiC epitaxial wafer 1 may be, for example, 195 mm or more, preferably 199 mm or more. The diameter of the SiC epitaxial wafer 1 may be preferably 205 mm or less, more preferably 201 mm or less. The diameter of the SiC epitaxial wafer 1 may be, for example, 245 mm or more, preferably 249 mm or more. The diameter of the SiC epitaxial wafer 1 may be, for example, 255 mm or less, preferably 251 mm or less. The diameter of the SiC epitaxial wafer 1 may be, for example, 295 mm or more, preferably 299 mm or more. The SiC epitaxial wafer 1 may be, for example, 305 mm or less, and preferably 301 mm or less.

[0025] The SiC substrate 2 is made of, for example, n-type SiC. The conductivity type of the SiC substrate 2 may be p-type or semi-insulating. The polytype of the SiC substrate 2 is not particularly limited and may be any of 2H, 3C, 4H, and 6H. The SiC substrate 2 is, for example, 4H—SiC.

[0026] The SiC substrate 2 has micropipes. The density of the micropipes in the SiC substrate 2 is 1 / cm. ２ It is preferable that the number of particles is 0.003 particles / cm or less. ２ 1 piece / cm ２More preferably, it is 0.003 particles / cm or less. ２ 0.5 pieces / cm or more ２ More preferably, 0.003 particles / cm or less ２ 0.2 pieces / cm or more ２ More preferably, 0.003 particles / cm or less ２ 0.15 pieces / cm or more ２ More preferably, 0.003 particles / cm or less ２ 0.1 pieces / cm or more ２ The following is more preferable: Micropipes are hollow crystal defects with diameters of sub-micrometers to several micrometers that propagate in the c-axis direction of hexagonal silicon carbide. Micropipes are thought to be formed when screw dislocations with large Burgers vectors relax strain energy.

[0027] Since large pit defects and triangular defects caused by micropipes in the SiC substrate after epitaxial growth can become killer defects, it is ideal for the SiC substrate 2 to be free of micropipes. However, it is difficult to consistently fabricate a SiC substrate free of micropipes. In contrast, if the SiC substrate 2 has a micropipe density within a desired range, it can be fabricated relatively stably. That is, if the micropipe density is 0.003 / cm ２ 1 piece / cm ２ The following SiC substrate 2 satisfies the required quality and can be obtained stably. Furthermore, the lower the density of micropipes in the SiC substrate 2, the lower the density of stacking faults caused by the micropipes in the SiC substrate 2 can be.

[0028] Furthermore, if the SiC substrate 2 has a certain number of micropipes, these micropipes can be used as markers for determining the position coordinates of defects, etc. If the SiC substrate 2 has defects that can serve as markers, it becomes easier to investigate the causes of defects that can be confirmed after the SiC epitaxial layer 3 is stacked, based on the defects confirmed after the SiC epitaxial layer 3 is stacked and the position coordinates of these marker defects. Furthermore, by taking advantage of the fact that micropipes are defects that penetrate the SiC ingot, the micropipes can be used as position information markers when matching defects between SiC substrates cut from the same ingot, and this can be utilized in investigating and analyzing defects caused by the SiC substrates formed during epitaxial growth.

[0029] Micropipes are hollow defects with a diameter greater than 100 nm that are exposed on the surface of the SiC substrate 2. Micropipes can be identified using transmission X-ray topography. In X-ray diffraction, regions of lattice disorder in a crystal (crystal defects) exhibit increased diffracted X-ray intensity near the imperfections. X-ray topography utilizes this characteristic. An X-ray topography image is a two-dimensional image obtained by irradiating a sample with X-rays under black conditions and converting the intensity of the diffracted X-rays into contrast. Around crystal defects, the diffracted X-ray intensity increases due to distortion of the crystal lattice, resulting in a darker color density in the XRT image. This contrast pattern can provide information on the shape and distribution of the defects. Micropipes exhibit strong distortion and are identified as dark spots with a contrast difference from other areas. While reflection X-ray topography provides information on defects within the surface layer, typically a few microns to 20 microns, transmission X-ray topography provides information on defects throughout the entire thickness of the sample.

[0030] By using transmission X-ray topography, micropipes can be distinguished by taking advantage of the difference in contrast between them and other defects. For example, when micropipes are confirmed by transmission X-ray topography, the contrast of point-like defects caused by micropipe distortion is three times or more the contrast of point-like defects caused by threading dislocations. After distinguishing micropipes from other defects in the transmission X-ray topography image, the micropipe density and the number of micropipes in the SiC substrate 2 can be determined by counting the number of micropipes. The position coordinates of the micropipes can be calculated from the position coordinates of the full-surface photograph of the transmission X-ray topography image. Furthermore, the micropipe density can be calculated by dividing the number of micropipes by the area of ​​the substrate.

[0031] Micropipes may also be evaluated using optical microscopy and photoluminescence in addition to transmission X-ray topography. Micropipes are identified as irregularities using an optical microscope. Micropipes are also identified as dark spots accompanied by bright spots using photoluminescence. Observing micropipes using multiple evaluation methods can further increase the accuracy of identifying micropipes.

[0032] Furthermore, micropipes in the SiC substrate 2 can be identified using the SiC epitaxial wafer 1 after the SiC epitaxial layer 3 has been formed. By obtaining an X-ray topography image of the surface of the SiC epitaxial wafer 1 facing the SiC substrate 2, the number and positions of micropipes in the SiC substrate 2 can be identified. The X-ray topography measurement of the surface of the SiC epitaxial wafer 1 facing the SiC substrate 2 may be performed by either transmission X-ray topography or reflection X-ray topography, but reflection X-ray topography is preferably used.

[0033] The SiC epitaxial layer 3 is stacked on one surface of the SiC substrate 2. The SiC epitaxial layer 3 has a stacking fault density of 0.067 / cm due to micropipes in the SiC substrate 2. ２ In the SiC epitaxial layer 3, the density of stacking faults due to micropipes in the SiC substrate 2 is less than 0.03 / cm. ２It is preferable that the number of particles is 0.02 particles / cm or less. ２ More preferably, it is 0.01 particles / cm or less. ２ More preferably, it is 0 particles / cm or less. ２ It is more preferable that:

[0034] Stacking faults due to micropipes in SiC substrate 2 can be identified by performing the steps of: identifying the positions of the micropipes in SiC substrate 2; identifying the positions of stacking faults in SiC epitaxial layer 3 formed on SiC substrate 2; and comparing the positions of the micropipes in SiC substrate 2 with the positions of the stacking faults in SiC epitaxial layer 3. This method for identifying stacking faults due to micropipes in SiC substrate 2 can also be used as one of the methods for evaluating SiC epitaxial wafer 1.

[0035] The positions of the micropipes in the SiC substrate 2 can be identified using X-ray topography, as described above.

[0036] The positions of stacking faults in the SiC epitaxial layer 3 can be identified using a photoluminescence method. Photoluminescence can be measured using, for example, a SICA88 manufactured by Lasertec Corporation. For example, excitation light is irradiated onto the surface of the SiC epitaxial wafer using a bandpass filter that transmits ultraviolet wavelengths, and stacking faults are identified using a highpass filter that transmits near-infrared wavelengths (wavelengths of approximately 600 nm or more).

[0037] The position of the micropipe in the SiC substrate 2 and the position of the stacking fault in the SiC epitaxial layer 3 can be matched from the position coordinates of the micropipe in the SiC substrate 2, the thickness of the SiC epitaxial layer 3, and the offset angle of the SiC epitaxial layer 3. The offset angle is the angle between the crystal growth plane and the (0001) plane. The offset angle is the inclination angle between the planes, and can be treated as a first offset angle in the <1-100> direction and a second offset angle in the <11-20> direction. If a stacking fault confirmed after forming the SiC epitaxial layer 3 is located at a predetermined position relative to the micropipe in the SiC substrate 2, this stacking fault can be said to be a defect caused by the micropipe in the SiC substrate 2. For example, if the SiC epitaxial layer 3 does not have an offset angle, the position of the micropipe in the SiC substrate 2 and the position of the stacking fault in the SiC epitaxial layer 3 will coincide. Furthermore, for example, when there is no first offset angle in the <1-100> direction and there is a second offset angle in the <11-20> direction, where d is the thickness of the SiC epitaxial layer 3, there should be stacking faults in the SiC epitaxial layer 3 at positions shifted by d / tan θ in the <11-20> direction from the positions of the micropipes in the SiC substrate 2. The thickness d of the SiC epitaxial layer 3 can be measured using, for example, Fourier transform infrared spectroscopy (FT-IR).

[0038] The conversion rate of micropipes in the SiC substrate 2 to defects other than stacking faults in the SiC epitaxial layer 3 preferably exceeds 60%, for example. The conversion rate to defects other than stacking faults is more preferably 80% or more, and even more preferably 100%. Here, defects other than stacking faults refer to surface defects such as large pit defects and triangular defects. These surface defects are easy to detect and can be classified with high accuracy by automatic defect classification using AI. Converting many of the micropipes in the SiC substrate 2 to surface defects allows the positions of the micropipes to be identified simply by surface inspection after the formation of the SiC epitaxial layer 3. In other words, it is not necessary to compare the defect evaluation results of the SiC substrate 2 with the defect evaluation results of the SiC epitaxial wafer after the formation of the SiC epitaxial layer 3. The conversion rate of micropipes in the SiC substrate 2 to stacking faults in the SiC epitaxial layer 3 is preferably less than 40%, more preferably 20% or less, more preferably 10% or less, more preferably 5% or less, and more preferably 0%.

[0039] Next, a method for manufacturing the SiC epitaxial wafer 1 according to this embodiment will be described.

[0040] First, prepare the SiC substrate 2. The SiC substrate 2 has a micropipe density of, for example, 0.003 pieces / cm ２ 1 piece / cm ２ The following can be used:

[0041] Next, the SiC epitaxial layer 3 is laminated on the SiC substrate 2. The SiC epitaxial layer 3 is formed by, for example, chemical vapor deposition (CVD).

[0042] The SiC epitaxial layer 3 according to this embodiment requires strict control to reduce stacking faults due to micropipes in the SiC substrate. The crystal growth conditions that keep the stacking faults due to micropipes in the SiC substrate within a predetermined range are affected by variations in the characteristics of each film formation apparatus and may differ for each film formation apparatus. Therefore, in order to reduce stacking faults due to micropipes in the SiC substrate, tuning tailored to each film formation apparatus is required.

[0043] First, in the pre-process, the growth conditions for the SiC epitaxial layer 3 are tuned. In the pre-process, the growth conditions for the SiC epitaxial layer 3 are determined to suit a specific film formation apparatus. This pre-process is performed for each film formation apparatus. Furthermore, if the inside of the film formation apparatus is cleaned, the pre-process is performed again. In the pre-process, practice film formation is repeated multiple times until the growth conditions for the SiC epitaxial layer 3 are determined. In the pre-process, the temperature, C / Si ratio, and growth rate parameters are changed in three stages: the initial, middle, and final stages of crystal growth.

[0044] First, a SiC substrate 2 with identified micropipe positions is prepared. The micropipe positions on the SiC substrate 2 are identified using X-ray topography. Next, a practice SiC epitaxial layer 3 is formed on the SiC substrate 2. In the first practice deposition, the SiC epitaxial layer 3 is formed using the temperature, C / Si ratio, and growth rate of each of the three growth stages as first conditions. After the first practice deposition, the SiC epitaxial layer 3 is subjected to photoluminescence measurement to determine the positions of stacking faults in the SiC epitaxial layer 3. Next, the positions of the micropipes on the SiC substrate 2 are compared with the positions of the stacking faults on the SiC epitaxial layer 3 to identify stacking faults due to the micropipes on the SiC substrate 2. Finally, the density of stacking faults due to the micropipes on the SiC substrate 2 is determined when the SiC epitaxial layer 3 is formed under the conditions of the first practice deposition.

[0045] Next, in the second practice deposition, SiC epitaxial layer 3 is deposited under second conditions in which at least one of the temperature, C / Si ratio, and growth rate in each of the three growth stages is changed from the first conditions. Then, the density of stacking faults caused by micropipes in SiC substrate 2 when SiC epitaxial layer 3 is deposited under the conditions of the second practice deposition is determined.

[0046] The results of the first and second practice film depositions are fed back to determine the conditions for the third practice film deposition. In the third practice film deposition, at least one of the temperature, C / Si ratio, and growth rate for each of the three growth stages is changed from the first and second conditions.

[0047] This practice film formation and feedback of the measurement results are repeated to determine the final growth conditions for the SiC epitaxial layer 3. The practice film formation and feedback of the measurement results are repeated by finely changing the growth conditions, and the final growth conditions for the SiC epitaxial layer 3 are precisely determined for each film formation apparatus.

[0048] The temperature conditions for the training film formation are changed in the range of 1500° C. to 1700° C. in each of the three growth stages. The temperature conditions are finally tuned in increments of 1° C.

[0049] The C / Si ratio of the practice film is changed within a range of 0.8 to 1.5 in each of the three growth stages. The C / Si ratio is finally tuned within a range of 0.05. C / Si is the ratio of the C source gas to the Si source gas on the growth surface of the SiC epitaxial layer 3.

[0050] The growth rate of the training film is changed in the range of 5 μm / h to 100 μm / h in each of the three growth stages. The growth rate is finally tuned within a range of 5 μm / h.

[0051] Next, under the deposition conditions determined in the preliminary step, actual deposition of the SiC epitaxial layer 3 is performed. By this procedure, it is possible to fabricate the SiC epitaxial wafer 1 with few stacking faults caused by micropipes in the SiC substrate 2.

[0052] As a result of extensive investigation, the present inventors have identified that stacking faults caused by micropipes in the SiC substrate 2 also act as killer defects. Even when using chips after removing defective chips containing large pit defects, triangular defects, and the like caused by micropipes in the SiC substrate 2, one of the causes of defects in SiC devices is stacking faults caused by micropipes in the SiC substrate 2.

[0053] The SiC epitaxial wafer 1 according to this embodiment has a low density of stacking faults caused by micropipes in the SiC substrate 2, which are likely to become killer defects. Surface defects such as large pit defects and triangular defects caused by micropipes in the SiC substrate 2 are easy to detect. Therefore, the SiC epitaxial wafer 1 according to this embodiment makes it possible to appropriately remove chips that will become defective, and the yield of non-defective products after chipping is high.

[0054] SiC devices are obtained by forming devices in the SiC epitaxial layer 3 of the SiC epitaxial wafer 1 and then chipping the SiC epitaxial wafer 1. The method for manufacturing a SiC device according to this embodiment includes an evaluation step of performing an evaluation method for the SiC epitaxial wafer 1, a chipping step of chipping the SiC epitaxial wafer 1, and a removal step of removing chips having stacking faults caused by micropipes in the SiC substrate 2.

[0055] The evaluation step includes the steps of identifying the positions of micropipes in the SiC substrate 2, identifying the positions of stacking faults in the SiC epitaxial layer 3 formed on the SiC substrate 2, and comparing the positions of the micropipes in the SiC substrate 2 with the positions of the stacking faults in the SiC epitaxial layer 3 to identify stacking faults caused by the micropipes in the SiC substrate 2. The specific procedure for identifying stacking faults caused by the micropipes in the SiC substrate 2 in the evaluation step is as described above.

[0056] In the chipping step, the SiC epitaxial wafer 1 is chipped. The chipping step is preferably performed after devices are formed in the SiC epitaxial layer 3 of the SiC epitaxial wafer 1.

[0057] In the removing step, chips having stacking faults caused by micropipes in the SiC substrate are removed. In the removing step, it is preferable to also remove chips having killer defects other than stacking faults caused by micropipes in the SiC substrate.

[0058] By using the method for manufacturing a SiC device according to this embodiment, it is possible to reduce the probability that chips containing killer defects that hinder normal operation of the SiC device will be mixed into the product.

[0059] Although the preferred embodiments of the present disclosure have been described in detail above, the present disclosure is not limited to specific embodiments, and various modifications and changes are possible within the scope of the gist of the present disclosure as set forth in the claims.

[0060] Example 1 First, a SiC substrate 2 having a diameter of 150 mm was prepared. The SiC substrate 2 had a micropipe density of 0.156 pieces / cm ２ In addition, an X-ray topography image of the SiC substrate 2 was measured, and the positions of the micropipes in the SiC substrate 2 were identified.

[0061] Next, a SiC epitaxial layer 3 was formed on the SiC substrate 2. The growth conditions for the SiC epitaxial layer 3 were set in advance to conditions that would prevent stacking faults due to micropipes in the SiC substrate 2. These conditions differ for each manufacturing device, and conditions specific to the manufacturing device were set by repeating condition determination and evaluation multiple times.

[0062] Next, the positions of stacking faults in the SiC epitaxial layer 3 were identified using a photoluminescence method. The positions of the micropipes in the SiC substrate 2, which had been evaluated in advance, were compared with the positions of the stacking faults in the SiC epitaxial layer 3 to determine the density of stacking faults caused by the micropipes in the SiC substrate 2. The SiC epitaxial wafer 1 in Example 1 had a density of stacking faults caused by the micropipes in the SiC substrate 2 of 0 / cm. ２That is, all of the micropipes contained in the SiC substrate 2 were converted into surface defects such as large pit defects and triangular defects. That is, the conversion rate of the SiC substrate 2 to defects other than stacking faults caused by micropipes was 100%, and the conversion rate of the SiC substrate 2 to stacking faults caused by micropipes was 0%.

[0063] Next, the SiC epitaxial wafer was divided into chips, and chips containing surface defects caused by micropipes in the SiC substrate were removed as defective chips. In Example 1, the conversion rate of micropipes to defects other than stacking faults was 100%. Therefore, in Example 1, when fabricating SiC devices after removing chips having large pit defects and triangular defects caused by micropipes in the SiC substrate as defective chips, no defects caused by micropipes in the SiC substrate 2 occur.

[0064] In Example 1, whether the chip size is assumed to be 7 mm x 7 mm or 10 mm x 10 mm, the yield of SiC devices fabricated from chips excluding defective chips is expected to be 100%.

[0065] Comparative Example 1 As in Example 1, a SiC substrate 2 having a diameter of 150 mm was prepared. The SiC substrate 2 had a micropipe density of 0.156 pieces / cm ２ The following was used.

[0066] Next, a SiC epitaxial layer 3 was formed on the SiC substrate 2. The growth conditions for the SiC epitaxial layer 3 were different from those in Example 1.

[0067] Next, the positions of stacking faults in the SiC epitaxial layer 3 were identified using a photoluminescence method. The positions of the micropipes in the SiC substrate 2, which had been evaluated in advance, were compared with the positions of the stacking faults in the SiC epitaxial layer 3 to determine the density of stacking faults caused by the micropipes in the SiC substrate 2. The SiC epitaxial wafer 1 in Comparative Example 1 had a density of stacking faults caused by the micropipes in the SiC substrate 2 of 0.067 / cm. ２The conversion rate of the SiC substrate 2 to defects other than stacking faults due to micropipes was 60%, and the conversion rate of the SiC substrate 2 to stacking faults due to micropipes was 40%.

[0068] Next, the SiC epitaxial wafer was divided into chips, and chips containing surface defects caused by micropipes in the SiC substrate were removed as defective chips. In Comparative Example 1, even after removing defective chips containing large pit defects, triangular defects, etc. caused by micropipes in the SiC substrate 2, chips that may cause defects in SiC devices were still included in the chips after removing the defective chips.

[0069] In Comparative Example 1, assuming a chip size of 7 mm × 7 mm, the SiC device yield is expected to be 97% or less due to stacking faults caused by micropipes in the SiC substrate. If the chip size is 10 mm × 10 mm, the SiC device yield is expected to be 94% or less.

[0070] Although the results for SiC epitaxial wafers using SiC substrates 2 with a diameter of 150 mm have been shown so far, a similar study was also carried out for SiC epitaxial wafers using SiC substrates 2 with a diameter of 200 mm. When the diameter was 200 mm, the same tendency as when the diameter was 150 mm was confirmed.

[0071] 1 SiC epitaxial wafer 2 SiC substrate 3 SiC epitaxial layer 4 Notch

Claims

1. A method for fabricating a SiC substrate having micropipes and a SiC epitaxial layer formed on the SiC substrate, wherein the SiC epitaxial layer has a stacking fault density of 0.067 / cm due to the micropipes of the SiC substrate. ２ A SiC epitaxial wafer having a thickness of less than 100 nm.

2. The density of stacking faults caused by the micropipes in the SiC substrate is 0.03 / cm ２ 2. The SiC epitaxial wafer of claim 1, wherein:

3. The density of stacking faults caused by the micropipes in the SiC substrate is 0.02 / cm ２ 2. The SiC epitaxial wafer of claim 1, wherein:

4. The density of stacking faults caused by the micropipes in the SiC substrate is 0.01 / cm ２ 2. The SiC epitaxial wafer of claim 1, wherein:

5. The density of stacking faults caused by the micropipes in the SiC substrate is 0 / cm ２ 2. The SiC epitaxial wafer of claim 1, wherein 6. The SiC epitaxial wafer according to any one of claims 1 to 5, having a diameter of 145 mm or more.

7. The SiC epitaxial wafer according to any one of claims 1 to 5, having a diameter of 195 mm or more.

8. A method for evaluating a SiC epitaxial wafer, comprising the steps of: identifying the positions of micropipes in a SiC substrate; identifying the positions of stacking faults in a SiC epitaxial layer formed on the SiC substrate; and comparing the positions of the micropipes with the positions of the stacking faults to identify stacking faults caused by the micropipes in the SiC substrate.

9. A method for manufacturing a SiC device, comprising the steps of: performing the SiC epitaxial wafer evaluation method described in claim 8; dividing the SiC epitaxial wafer into chips; and removing chips having stacking faults caused by the micropipes in the SiC substrate.

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