Light detection device and electronic apparatus

Abstract

The present invention achieves a high saturation charge amount Qs. This light detection device comprises: a semiconductor layer having a first surface part and a second surface part each located on opposite sides in one direction; a shallow separation region provided on the first surface part side of the semiconductor layer; an element formation region demarcated by the shallow separation region on the first surface part side of the semiconductor layer and provided with a pixel transistor; and a photoelectric conversion region demarcated by a deep separation region extending from the second surface part side of the semiconductor layer toward the first surface part side and provided with a photoelectric conversion part. In the deep separation region, a portion overlapping the element formation region in plan view protrudes further toward a first surface side of the semiconductor layer than a bottom part of the shallow separation region.

Description

Photodetector and electronic equipment

[0001] The present technology (technology related to the present disclosure) relates to a photodetector and an electronic device, and in particular to a technology that is effective when applied to a photodetector in which a photoelectric conversion region of a semiconductor layer is partitioned by a recessed isolation region, and to an electronic device equipped with the same.

[0002] 2. Description of the Related Art In image sensors (photodetection devices) such as distance measuring devices and solid-state imaging devices, photoelectric conversion regions and element formation regions of semiconductor layers are partitioned by recessed isolation regions.

[0003] Patent Document 1 discloses an isolation structure in which an element formation region on the first surface side of a semiconductor layer is partitioned by a recessed shallow isolation region, and a photoelectric conversion region of the semiconductor layer is partitioned by a deep isolation region extending from the second surface side of the semiconductor layer toward the first surface side.

[0004] Japanese Patent Application Laid-Open No. 2022-113736

[0005] In the isolation structure of Patent Document 1, the deep isolation region and the element formation region overlap but are spaced apart in a plan view. In this isolation structure, in two photoelectric conversion regions adjacent to each other in a plan view via the deep isolation region, a path connecting one photoelectric conversion region to the other exists on the shallow region side of the deep isolation region. As a result, signal charges photoelectrically converted in one photoelectric conversion region are likely to leak to the other photoelectric conversion region via the path, which determines the upper limit of the saturation charge amount Qs.

[0006] In recent years, there has been a demand in the market for high-resolution image sensors, and the development of image sensors with reduced pixel size is progressing. As pixel size decreases, the saturation charge amount Qs in each pixel (photoelectric conversion area) also decreases. Because the saturation signal amount affects image quality performance, there is room for improvement.

[0007] An object of the present technology is to provide a technology that can obtain a high saturation charge amount Qs.

[0008] (1) A photodetector according to one aspect of the present technology includes: a semiconductor layer having a first surface portion and a second surface portion located opposite to each other in one direction, a shallow isolation region provided on the first surface portion side of the semiconductor layer, an element formation region partitioned by the shallow isolation region on the first surface portion side of the semiconductor layer and having a pixel transistor provided therein, and a photoelectric conversion region partitioned by a deep isolation region extending from the second surface portion side of the semiconductor layer toward the first surface portion side and having a photoelectric conversion unit provided therein, and a portion of the deep isolation region overlapping with the element formation region in a plan view protrudes toward the first surface side of the semiconductor layer beyond a bottom of the shallow isolation region. (2) A photodetector according to another aspect of the present technology includes: a semiconductor layer having a first surface portion and a second surface portion located opposite to each other in one direction, a shallow isolation region provided on the first surface portion side of the semiconductor layer, an element formation region partitioned by the shallow isolation region on the first surface portion side of the semiconductor layer and having a pixel transistor provided therein, and a photoelectric conversion region partitioned by a deep isolation region extending from the second surface portion side of the semiconductor layer toward the first surface portion side and having a photoelectric conversion portion provided therein, wherein the shallow isolation region includes an isolation blocking portion that blocks a bottom side of the element formation region, and a portion of the deep isolation region that overlaps with the element formation region in a plan view is connected to the isolation blocking portion.

[0009] (3) A photodetector according to another aspect of the present technology includes: a semiconductor layer having a first surface portion and a second surface portion located opposite to each other in one direction, a photoelectric conversion region defined by a deep isolation region extending from the second surface portion of the semiconductor layer toward the first surface portion and including a photoelectric conversion portion, and an element formation region defined by a shallow isolation region on the first surface portion side of the semiconductor layer, overlapping the deep isolation region in a plan view, and including a pixel transistor, wherein the shallow isolation region includes: a shallow recessed portion provided in the first surface portion of the semiconductor layer, an isolation insulating film provided inside the shallow recessed portion, and a light reflecting film interposed between the shallow recessed portion and the isolation insulating film and having a higher light reflectance than the isolation insulating film. (4) A photodetector according to another aspect of the present technology includes a semiconductor layer having a first surface portion and a second surface portion located opposite to each other in one direction, a photoelectric conversion region defined by a deep isolation region extending from the second surface portion side of the semiconductor layer toward the first surface portion side and having a photoelectric conversion unit provided therein, and an element formation region defined by a shallow isolation region on the first surface portion side of the semiconductor layer, overlapping the deep isolation region in a plan view, and having a pixel transistor provided therein. The shallow isolation region is inclined with respect to a center line passing through a center of the width of the deep isolation region in a vertical cross section crossing the deep isolation region, and is connected to the deep isolation region.

[0010] (5) An electronic device according to another aspect of the present technology includes the above-mentioned photodetector; an optical lens that focuses image light from a subject on an imaging surface of the semiconductor device; and a signal processing circuit that performs signal processing on a signal output from the above-mentioned photodetector.

[0011] 9A is a chip layout diagram showing a configuration example of a solid-state imaging device according to a first embodiment of the present technology. FIG. 9B is a block diagram showing a configuration example of a solid-state imaging device according to a first embodiment of the present technology. FIG. 9C is an equivalent circuit diagram showing a configuration example of a pixel block and a readout circuit according to a first embodiment of the present technology. FIG. 9D is a plan view schematically showing a configuration example of a pixel block included in the pixel array section of FIG. 1. FIG. 9E is a longitudinal sectional view schematically showing a longitudinal sectional structure along the a4-a4 cutting line of FIG. 4. FIG. 9F is a longitudinal sectional view schematically showing a longitudinal sectional structure along the b4-b4 cutting line of FIG. 4. FIG. 9G is a longitudinal sectional view schematically showing a longitudinal sectional structure along the c4-c4 cutting line of FIG. 4. FIG. 9H is a plan view schematically showing a plan pattern of a shallow isolation region of FIG. 5. FIG. 9H is a plan view schematically showing a plan pattern of a deep isolation region of FIG. 5. FIG. 9A is a plan view of a main part enlarged in part of FIG. 9A. FIG. 9H is a longitudinal sectional view of a main part enlarged in part of FIG. 5. FIG. 9I is a longitudinal sectional view of a main part schematically showing an isolation structure that is a reference example of the prior art. FIG. 9I is a diagram showing a modified example 1-1 according to the first embodiment of the present technology, and is a longitudinal sectional view schematically showing a longitudinal sectional structure at the same position as the longitudinal sectional view of FIG. 5. 5A to 5C are views showing a modified example 1-1 according to the first embodiment of the present technology, and are plan views schematically showing a planar pattern of a deep separation region. FIG. 6A is a view showing a modified example 1-2 according to the first embodiment of the present technology, and are plan views schematically showing a vertical cross-sectional structure at the same position as the vertical cross-sectional structure of FIG. 5A. FIG. 6B is a view showing a modified example 1-3 according to the first embodiment of the present technology, and are plan views schematically showing a vertical cross-sectional structure at the same position as the vertical cross-sectional structure of FIG. 5A. FIG. 6C is a view showing a modified example 1-4 according to the first embodiment of the present technology, and are plan views schematically showing a vertical cross-sectional structure at the same position as the vertical cross-sectional structure of FIG. 5A. FIG. 6D is a view showing a modified example 1-5 according to the first embodiment of the present technology, and are plan views schematically showing a planar pattern of a deep separation region. FIG. 6E is a view showing a modified example 1-6 according to the first embodiment of the present technology, and are plan views schematically showing a planar pattern of a deep separation region. FIG. 6 is a diagram illustrating a modified example 1-7 according to the first embodiment of the present technology, and is a longitudinal cross-sectional view schematically illustrating a longitudinal cross-sectional structure at the same position as the longitudinal cross-sectional view of FIG. 5 .20B is a longitudinal cross-sectional view of a main part in which a part of FIG. 20A is enlarged. FIG. 20C is a longitudinal cross-sectional view showing a modified example 1-8 according to the first embodiment of the present technology, which is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure at the same position as the longitudinal cross-sectional view of FIG. 5. FIG. 20D is a longitudinal cross-sectional view showing a modified example 1-9 according to the first embodiment of the present technology, which is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure at the same position as the longitudinal cross-sectional view of FIG. 5. FIG. 20E is a longitudinal cross-sectional view showing a modified example 1-10 according to the first embodiment of the present technology, which is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure at the same position as the longitudinal cross-sectional view of FIG. 5. FIG. 20F is a longitudinal cross-sectional view showing a modified example 1-11 according to the first embodiment of the present technology, which is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure at the same position as the longitudinal cross-sectional view of FIG. 5. FIG. 20G is a longitudinal cross-sectional view showing a modified example 1-12 according to the first embodiment of the present technology, which is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure at the same position as the longitudinal cross-sectional view of FIG. 5. FIG. 20H is an equivalent circuit diagram showing a configuration example of a pixel block and a readout circuit in a solid-state imaging device according to a second embodiment of the present technology. FIG. 20H is a plan view showing a configuration example of a pixel block included in a pixel array unit in a solid-state imaging device according to a second embodiment of the present technology. 32. It is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the a27-a27 cutting line of FIG. 27. It is an equivalent circuit diagram showing an example configuration of a pixel block and a readout circuit in a solid-state imaging device according to a third embodiment of the present technology. It is a plan view schematically showing an example configuration of a pixel block included in a pixel array section in a solid-state imaging device according to a third embodiment of the present technology. It is a diagram showing an example configuration of a solid-state imaging device according to a fourth embodiment of the present technology, and is a plan view schematically showing an example configuration of a pixel block included in a pixel array section. It is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the a31-a31 cutting line of FIG. 31. It is an enlarged longitudinal cross-sectional view of a main part in which a part of FIG. 32 is enlarged. It is a diagram showing a modification 4-1 according to the fourth embodiment of the present technology, and is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure at the same position as the longitudinal cross-sectional view of FIG. 32. It is a diagram showing a modification 4-2 according to the fourth embodiment of the present technology, and is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure at the same position as the longitudinal cross-sectional view of FIG. Fig. 33 is a diagram showing a modified example 4-3 according to the fourth embodiment of the present technology, which is a longitudinal cross-sectional view schematically showing the longitudinal cross-sectional structure at the same position as the longitudinal cross-sectional view of Fig. 32. Fig. 34 is a diagram showing a modified example 4-4 according to the fourth embodiment of the present technology, which is a longitudinal cross-sectional view schematically showing the longitudinal cross-sectional structure at the same position as the longitudinal cross-sectional view of Fig. 32.41 is a diagram showing a modified example 4-5 according to the fourth embodiment of the present technology, and is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure at the same position as the longitudinal cross-sectional view of FIG. 32 . FIG. 42 is an equivalent circuit diagram schematically showing a configuration example of a pixel block and a readout circuit in a solid-state imaging device according to a fifth embodiment of the present technology. FIG. 43 is a plan view schematically showing a configuration example of a pixel block group included in a pixel array section in a solid-state imaging device according to a fifth embodiment of the present technology. FIG. 44 is a diagram schematically showing a planar pattern of a deep isolation region in FIG. 39 . FIG. 45 is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the a39-a39 cutting line of FIG. 39 . FIG. 46 is an enlarged longitudinal cross-sectional view of a main part, enlarging a part of FIG. 41 . FIG. 47 is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the b39-b39 cutting line of FIG. 39 . FIG. 48 is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the c39-c39 cutting line of FIG. 39 . FIG. 49 is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the d39-d39 cutting line of FIG. 48 . FIG. 49 is a plan view schematically showing a configuration example of a pixel block group included in a pixel array section in a solid-state imaging device according to a sixth embodiment of the present technology. 51. A longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the a47-a47 cutting line of FIG. 47. A longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the b47-b47 cutting line of FIG. 47. A plan view schematically showing a configuration example of a pixel block group included in a pixel array section in a solid-state imaging device according to a seventh embodiment of the present technology. A plan view schematically showing a configuration example of a pixel block group included in a pixel array section in a solid-state imaging device according to an eighth embodiment of the present technology. A longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the a51-a51 cutting line of FIG. 51. A longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the b51-b51 cutting line of FIG. 51. A plan view schematically showing a configuration example of a pixel block group included in a pixel array section in a solid-state imaging device according to a ninth embodiment of the present technology. A longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the a54-a54 cutting line of FIG. 54. A longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the b54-b54 cutting line of FIG. 54. 57. A plan view schematically showing a configuration example of a pixel block group included in a pixel array unit in a solid-state imaging device according to a tenth embodiment of the present technology. A longitudinal sectional view schematically showing a longitudinal sectional structure taken along the a57-a57 cutting line in FIG. 57. A longitudinal sectional view schematically showing a longitudinal sectional structure taken along the b57-b57 cutting line in FIG.61. FIG. 62 is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the c57-c57 cutting line of FIG. 57. FIG. 63 is a plan view schematically showing a configuration example of a pixel block group included in a pixel array section in a solid-state imaging device according to an eleventh embodiment of the present technology. FIG. 64 is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the a61-a61 cutting line of FIG. 61. FIG. 65 is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the b61-b61 cutting line of FIG. 61. FIG. 66 is a plan view schematically showing a configuration example of a pixel block group included in a pixel array section in a solid-state imaging device according to a twelfth embodiment of the present technology. FIG. 67 is a plan view schematically showing a configuration example of a pixel block group included in a pixel array section in a solid-state imaging device according to a thirteenth embodiment of the present technology. FIG. 68 is a plan view schematically showing a configuration example of a pixel block group included in a pixel array section in a solid-state imaging device according to a fourteenth embodiment of the present technology. FIG. 69 is a plan view schematically showing a configuration example of a pixel block group included in a pixel array section in a solid-state imaging device according to a fifteenth embodiment of the present technology. 68. FIG. 68 is a plan view schematically showing a configuration example of a pixel block group included in a pixel array section in a solid-state imaging device according to a sixteenth embodiment of the present technology. FIG. 68 is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure along the a68-a68 cutting line of FIG. 68. FIG. 68 is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure along the b68-b68 cutting line of FIG. 68. FIG. 68 is a plan view schematically showing a configuration example of a pixel block group included in a pixel array section in a solid-state imaging device according to a seventeenth embodiment of the present technology. FIG. 57 is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure along the a57-a57 cutting line of FIG. 57. FIG. 73 is a plan view schematically showing a configuration example of a pixel block group included in a pixel array section in a solid-state imaging device according to an eighteenth embodiment of the present technology. FIG. 73 is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure along the a73-a73 cutting line of FIG. 73. FIG. 73 is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure along the b73-b73 cutting line of FIG. 73. FIG. 73 is a plan view schematically showing a configuration example of a pixel block group included in a pixel array section in a solid-state imaging device according to a nineteenth embodiment of the present technology. Fig. 78 is an enlarged longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the a75-a75 cutting line in Fig. 75. Fig. 79 is a plan view schematically showing an example of the configuration of a pixel block group included in a pixel array unit in a solid-state imaging device according to a twentieth embodiment of the present technology. Fig. 80 is a longitudinal cross-sectional view schematically showing the longitudinal cross-sectional structure taken along the a78-a78 cutting line in Fig. 78.FIG. 26 is a diagram showing a schematic configuration of an electronic device according to a 21st embodiment of the present technology.

[0012] Hereinafter, embodiments of the present technology will be described in detail with reference to the drawings. Note that in the drawings referred to in the following description, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc. may differ from the actual ones. Therefore, specific thicknesses and dimensions should be determined with reference to the following description.

[0013] Furthermore, it goes without saying that the dimensional relationships and ratios may differ between the drawings. Furthermore, the effects described in this specification are merely examples and are not intended to be limiting, and other effects may also be present.

[0014] Furthermore, the following embodiments exemplify devices and methods for embodying the technical idea of ​​the present technology, and do not limit the configuration to the following. In other words, the technical idea of ​​the present technology can be modified in various ways within the technical scope described in the claims.

[0015] Furthermore, the definitions of directions such as up and down in the following description are merely for the sake of convenience and do not limit the technical concept of the present technology. For example, if an object is rotated 90 degrees and observed, up and down are converted to left and right and read as such, and if an object is rotated 180 degrees and observed, up and down are obviously read as reversed.

[0016] In addition, in the following embodiments, an example will be described in which the first conductivity type is p-type and the second conductivity type is n-type as the conductivity type of the semiconductor, but the conductivity types may be selected in the opposite relationship, with the first conductivity type being n-type and the second conductivity type being p-type.

[0017] In the following embodiments, among the three directions orthogonal to each other in space, a first direction and a second direction orthogonal to each other in the same plane are referred to as the X direction and the Y direction, respectively, and a third direction orthogonal to each of the first direction and the second direction is referred to as the Z direction. In the following embodiments, the thickness direction of a semiconductor layer 21 (described later) will be described as the Z direction. In the following embodiments, the Z direction will be described as "one direction" of the present technology.

[0018] In the following embodiments, a plan view refers to a case where the semiconductor layer 21 is viewed from the Z direction (one direction), and a cross-sectional view refers to a case where a cross section along the Z direction (one direction) is viewed from a direction (Z direction) perpendicular to the cross section.

[0019] First Embodiment In this first embodiment, an example in which the present technology is applied to a solid-state imaging device that is a back-illuminated CMOS (Complementary Metal Oxide Semiconductor) image sensor as a photodetector will be described. Also, in this first embodiment, a pixel in which one photoelectric conversion unit is provided in one photoelectric conversion region will be described.

[0020] Fig. 1 is a chip layout diagram showing a configuration example of a solid-state imaging device according to a first embodiment of the present technology. Fig. 2 is a block diagram showing a configuration example of a solid-state imaging device according to the first embodiment of the present technology. Fig. 3 is an equivalent circuit diagram showing a configuration example of a pixel block and a readout circuit according to the first embodiment of the present technology. Fig. 4 is a plan view schematically showing a configuration example of a pixel block included in the pixel array unit of Fig. 1.

[0021] 4, in order to make the drawing easier to understand, a multilayer wiring layer 61, which will be described later, is not shown. Also, while Fig. 1 is a plan view of the semiconductor chip 2 as seen from its light incident surface side, Fig. 4 is a plan view of the semiconductor chip 2 as seen from the opposite side to the light incident surface side (the multilayer wiring layer side).

[0022] <Overall Configuration of Solid-State Imaging Device> First, the overall configuration of the solid-state imaging device 1A will be described with reference to FIGS. 1 to 4. As shown in FIG. 1, the solid-state imaging device 1A according to the first embodiment of the present technology is mainly composed of a semiconductor chip 2 having a rectangular two-dimensional planar shape in a planar view. That is, the solid-state imaging device 1A is mounted on the semiconductor chip 2, and the semiconductor chip 2 can be considered as the solid-state imaging device 1A. As shown in FIG. 80, this solid-state imaging device 1A (101) captures image light (incident light 106) from a subject via an optical lens 102, converts the amount of incident light 106 formed on the imaging surface into an electrical signal on a pixel-by-pixel basis, and outputs the electrical signal as a pixel signal.

[0023] As shown in FIG. 1 , a semiconductor chip 2 on which a solid-state imaging device 1A is mounted includes, in a two-dimensional plane including mutually orthogonal X and Y directions, a rectangular pixel array section 2A provided in the center and a peripheral section 2B provided outside the pixel array section 2A so as to surround the pixel array section 2A. The semiconductor chip 2 is formed in a manufacturing process by dicing a semiconductor wafer including a semiconductor layer 21 (see FIG. 5 ) described below into chip formation regions. Therefore, the configuration of the solid-state imaging device 1A described below is generally the same in the wafer state before the semiconductor wafer is diced. In other words, the present technology can be applied to both the semiconductor chip state and the semiconductor wafer state.

[0024] The solid-state imaging device 1A may be packaged in various types of packages and then mounted on an electronic device, or may be mounted directly on an electronic device in the form of a chip.

[0025] The pixel array section 2A is a light-receiving surface that receives light collected by, for example, an optical lens (optical system) 102 shown in FIG. 80 . The pixel array section 2A includes an effective pixel area and an optical black area (not shown), which is disposed outside the effective pixel area so as to surround the effective pixel area and outputs an optical reference black level. In each of the effective pixel area and the optical black area, a plurality of pixels (sensor pixels) 3 are arranged in a matrix on a two-dimensional plane including the X and Y directions. In other words, the pixels 3 are repeatedly arranged in the X and Y directions, which are orthogonal to each other, on the two-dimensional plane. The optical black area is covered with a light-shielding film.

[0026] 1, a plurality of bonding pads 14 are arranged in the peripheral portion 2B. Each of the plurality of bonding pads 14 is arranged, for example, along each of the four sides in a two-dimensional plane of the semiconductor chip 2. Each of the plurality of bonding pads 14 functions as an input / output terminal that electrically connects the semiconductor chip 2 to an external device. Although not shown, a connecting member such as a bonding wire or a bump electrode is connected to the bonding pad 14.

[0027] <Logic Circuit> The semiconductor chip 2 includes a logic circuit 13 shown in Fig. 2. As shown in Fig. 2, the logic circuit 13 includes a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, and a control circuit 8. The logic circuit 13 is configured of a CMOS (Complementary MOS) circuit having, as field effect transistors, for example, n-channel conductivity type MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and p-channel conductivity type MOSFETs.

[0028] 2 is configured with, for example, a shift register. The vertical drive circuit 4 sequentially selects desired pixel drive lines 10, supplies pulses to the selected pixel drive lines 10 for driving the pixels 3, and drives each pixel 3 row by row. That is, the vertical drive circuit 4 sequentially selects and scans each pixel 3 in the pixel array section 2A row by row in the vertical direction, and supplies pixel signals from the pixels 3 based on signal charges generated by the photoelectric conversion section of each pixel 3 in accordance with the amount of received light to the column signal processing circuit 5 via vertical signal lines 11.

[0029] 2 is arranged for each column of pixels 3, and performs signal processing such as noise removal for each pixel column on signals output from one row of pixels 3. For example, the column signal processing circuit 5 performs signal processing such as CDS (Correlated Double Sampling) and AD (Analog-Digital) conversion to remove fixed pattern noise specific to each pixel.

[0030] 2 is configured by, for example, a shift register. The horizontal drive circuit 6 sequentially outputs horizontal scanning pulses to the column signal processing circuits 5, thereby selecting each of the column signal processing circuits 5 in turn and causing each column signal processing circuit 5 to output a pixel signal that has undergone signal processing to a horizontal signal line 12.

[0031] 2 performs signal processing on pixel signals sequentially supplied from each of the column signal processing circuits 5 via the horizontal signal line 12, and outputs the processed signals. The signal processing may include, for example, buffering, black level adjustment, column variation correction, various types of digital signal processing, etc.

[0032] 2 generates clock signals and control signals that serve as references for the operations of the vertical drive circuit 4, column signal processing circuit 5, horizontal drive circuit 6, etc., based on the vertical synchronization signal, horizontal synchronization signal, and master clock signal. Then, the control circuit 8 outputs the generated clock signals and control signals to the vertical drive circuit 4, column signal processing circuit 5, horizontal drive circuit 6, etc.

[0033] <Pixel Block> The semiconductor chip 2 includes a pixel block 15A and a readout circuit (pixel circuit) 16A shown in FIG.

[0034] As shown in Figures 3 and 4, the pixel block 15A includes a plurality of pixels 3. Although not limited thereto, the pixel block 15A of the first embodiment includes, as a unit, four pixels 3 (3a, 3b, 3c, 3d) arranged in a 2x2 configuration, two adjacent to each other in each of the X and Y directions in a plan view, as shown in Figure 4. Although Figures 3 and 4 mainly illustrate two pixel blocks 15A arranged in the Y direction, the pixel blocks 15A are repeatedly arranged in each of the X and Y directions to form the pixel array unit 2A shown in Figure 1.

[0035] 3, each of the four pixels 3a, 3b, 3c, and 3d included in one pixel block 15A has common components. Specifically, each of the four pixels 3a, 3b, 3c, and 3d included in one pixel block 15A includes a photoelectric conversion unit 25 that photoelectrically converts light into signal charges, a floating diffusion region FD serving as a charge storage unit that stores (accumulates) the signal charges photoelectrically converted by the photoelectric conversion unit 25, and a transfer transistor TR that transfers the signal charges photoelectrically converted by the photoelectric conversion unit 25 to the floating diffusion region FD. Each of the four pixels 3a, 3b, 3c, and 3d included in one pixel block 15A further includes a photoelectric conversion region 22 of a semiconductor layer 21 shown in FIGS. 5 and 6. The photoelectric conversion unit 25, the floating diffusion region FD, and the transfer transistor TR are each provided in the semiconductor layer 21, as shown in Fig. 4 and Fig. 5. Of the four pixels 3a, 3b, 3c, and 3d included in one pixel block 15A, two pixels 3a and 3b are shown. Also, of the four pixels 3a, 3b, 3c, and 3d included in one pixel block 15A, two pixels 3a and 3c are shown for two pixel blocks 15A.

[0036] 3 is configured by, for example, a pn junction photodiode (PD) and generates a signal charge according to the amount of light received. The photoelectric conversion unit 25 also temporarily holds (accumulates) the generated signal charge.

[0037] The photoelectric conversion unit 25 has a cathode side electrically connected to the source region of the transfer transistor TR, and an anode side electrically connected to a reference potential line (for example, ground).

[0038] 3 transfers the signal charges photoelectrically converted by the photoelectric conversion unit 25 to the floating diffusion region FD. The source region of the transfer transistor TR is electrically connected to the cathode side of the photoelectric conversion unit 25, and the drain region is electrically connected to the floating diffusion region FD. The gate electrode of the transfer transistor TR is electrically connected to a transfer transistor drive line of the pixel drive lines 10 shown in FIG.

[0039] (Floating Diffusion Region) The floating diffusion region FD shown in FIG. 3 temporarily accumulates and holds the signal charge transferred from the photoelectric conversion unit 25 via the transfer transistor TR.

[0040] 3 has an input side electrically connected to the floating diffusion region FD of the pixel 3. The readout circuit 16A of the first embodiment is provided, for example, for every two pixel blocks 15 and is shared by the two pixel blocks 15A. The readout circuit 16A of the first embodiment is electrically connected to the floating diffusion region FD of each of the two pixel blocks 15A.

[0041] In the first embodiment, as an example, a circuit configuration is used in which one readout circuit 16A is assigned to two pixel blocks 15A, each unit of which includes four pixels 3. However, the assignment of the readout circuits 16A is not limited to this first embodiment. For example, a circuit configuration may be used in which one readout circuit 16A is assigned to one pixel block 15A, each unit of which includes two or more pixels 3, or a circuit configuration may be used in which one readout circuit 16A is assigned to multiple pixel blocks 15A, each unit of which includes multiple pixels 3. A circuit configuration may also be used in which one readout circuit 16A is assigned to one pixel 3.

[0042] 3 reads out the signal charges held in the floating diffusion regions FD of the pixels 3 and outputs a pixel signal based on the read-out signal charges. In other words, the read-out circuit 16A converts the signal charges photoelectrically converted by the photoelectric conversion unit 25 (photodiode PD) into a pixel signal based on the signal charges and outputs the pixel signal.

[0043] 3, the readout circuit 16A includes, but is not limited to, for example, an amplification transistor AMP, a selection transistor SEL, and a reset transistor RST as pixel transistors Q. These pixel transistors Q (AMP, SEL, RST) and the transfer transistor TR are insulated gate field effect transistors, and the gate insulating film is made of, for example, silicon oxide (SiO ２ The pixel transistor Q and the transfer transistor TR are configured with MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) made of a silicon nitride (Si) film. ３ N ４ Alternatively, a metal insulator semiconductor field effect transistor (MISFET) made of a laminated film of a silicon nitride film, a silicon oxide film, or the like may be used.

[0044] Of the pixel transistors Q (AMP, SEL, RST) included in the readout circuit 16A, the selection transistor SEL and the reset transistor RST mainly function as switching elements, and the remaining amplification transistor AMP mainly functions as an amplification element.

[0045] 3, the source region of the amplifier transistor AMP is electrically connected to the drain region of the select transistor SEL, and the drain region is electrically connected to the power supply line Vdd and the drain region of the reset transistor RST. The gate electrode of the amplifier transistor AMP is electrically connected to each of the floating diffusion regions FD of the eight pixels 3 (3a, 3b, 3c, 3d, 3a, 3b, 3c, 3d) included in the two pixel blocks 15A, and is also electrically connected to the source region of the reset transistor RST.

[0046] 3, the source region of the select transistor SEL is electrically connected to the vertical signal line 11 (VSL), the drain region is electrically connected to the source region of the amplification transistor AMP, and the gate electrode of the select transistor SEL is electrically connected to the select transistor drive line of the pixel drive lines 10 shown in FIG.

[0047] 3, the source region of the reset transistor RST is electrically connected to the gate electrode of the amplification transistor AMP and is also electrically connected to the floating diffusion regions FD of each of the eight pixels 3 (3a, 3b, 3c, 3d, 3a, 3b, 3c, 3d) that share it. The gate electrode of the reset transistor RST is electrically connected to a reset transistor drive line among the pixel drive lines 10 shown in FIG.

[0048] The selection transistor SEL may be omitted if necessary. In the case where the selection transistor SEL is omitted, the source region of the amplification transistor AMP is electrically connected to the vertical signal line 11 (VSL).

[0049] When the transfer transistor TR shown in FIG. 3 is turned on, it transfers the signal charge generated in the photoelectric conversion unit 25 (photodiode PD) to the floating diffusion region FD.

[0050] When the reset transistor RST shown in FIG. 3 is turned on, it resets the potential (signal charge) of the floating diffusion region FD to the potential of the power supply line Vdd.

[0051] The selection transistor SEL shown in FIG. 3 controls the output timing of the pixel signal from the readout circuit 16A.

[0052] 3 generates a pixel signal having a voltage corresponding to the level of the signal charge held in the floating diffusion region FD. The amplifier transistor AMP constitutes a source-follower amplifier and outputs a pixel signal having a voltage corresponding to the level of the signal charge generated in the photoelectric conversion unit 25 (photodiode PD). When the selection transistor SEL is turned on, the amplifier transistor AMP amplifies the potential of the floating diffusion region FD and outputs a voltage corresponding to the potential to the column signal processing circuit 5 via the vertical signal line 11 (VSL).

[0053] During operation of the solid-state imaging device 1A according to the first embodiment, signal charges generated in the photoelectric conversion unit 25 of each pixel 3 (photoelectric conversion region 22) are held (accumulated) in the floating diffusion region FD via the transfer transistor TR of the pixel 3. The signal charges held in the floating diffusion region FD are then read out by the readout circuit 16A and applied to the gate electrode of the amplifier transistor AMP of the readout circuit 16A. A horizontal line selection control signal is applied from the vertical shift register to the gate electrode of the select transistor SEL of the readout circuit 16A. By setting the selection control signal to a high (H) level, the select transistor SEL becomes conductive, and a current corresponding to the potential of the floating diffusion region FD, amplified by the amplifier transistor AMP, flows through the vertical signal line 11. Furthermore, by setting the reset control signal applied to the gate electrode of the reset transistor RST of the readout circuit 16A to a high (H) level, the reset transistor RST becomes conductive, resetting the signal charges accumulated in the floating diffusion region FD.

[0054] The photoelectric conversion unit 25, the transfer transistor TR, and the floating diffusion region FD shown in Fig. 3 are each mounted on a semiconductor layer 21 (see Figs. 4 to 6) described later. In addition, the pixel transistors Q (AMP, SEL, RST) included in the readout circuit 16A in Fig. 3 are also mounted on the semiconductor layer 21 (see Figs. 4 and 7).

[0055] <Specific Configuration of Solid-State Imaging Device> Next, a specific configuration of the solid-state imaging device 1A (semiconductor chip 2) will be described with reference to FIGS. 4 to 9. FIG. 5 is a longitudinal cross-sectional view schematically showing the longitudinal cross-sectional structure taken along the a4-a4 cutting line in FIG. 4. FIG. 6 is a longitudinal cross-sectional view schematically showing the longitudinal cross-sectional structure taken along the b4-b4 cutting line in FIG. 4. FIG. 7 is a longitudinal cross-sectional view schematically showing the longitudinal cross-sectional structure taken along the c4-c4 cutting line in FIG. 4. FIG. 8 is a plan view schematically showing the planar pattern of the shallow isolation region in FIG. 5. FIG. 9A is a plan view schematically showing the planar pattern of the deep isolation region in FIG. 5. FIG. 9B is a plan view of a main portion obtained by enlarging a portion of FIG. 9A. FIG. 10A is a longitudinal cross-sectional view of a main portion obtained by enlarging a portion of FIG. 5.

[0056] 5 does not illustrate layers above the first wiring layer 54 included in the multilayer wiring layer 61. In addition, in FIGS. 5 to 8, the lower side in the figure corresponds to the light incident surface side in FIG. 1, and the upper side in the figure corresponds to the multilayer wiring layer side. In addition, in FIGS. 6 and 7, the lens layer shown in FIG. 5 is not illustrated.

[0057] As shown in Figure 5, the solid-state imaging device 1A of this first embodiment has a semiconductor layer 21 that has a thickness in one direction, the Z direction, and has a first surface portion S1 and a second surface portion S2 that are located opposite each other in the thickness direction (Z direction).

[0058] In addition, the solid-state imaging device 1A according to the first embodiment further includes a shallow isolation region (field isolation region) 31 provided in the surface layer portion on the first surface portion S1 side of the semiconductor layer 21, and element formation regions 21a and 21b partitioned by this shallow isolation region 31 and provided in the surface layer portion on the first surface portion S1 side of the semiconductor layer 21.

[0059] In addition, the solid-state imaging device 1A according to the first embodiment further includes a deep isolation region 41 extending from the second surface portion S2 side of the semiconductor layer 21 toward the first surface portion S1 side, and a photoelectric conversion region 22 partitioned by this deep isolation region 41 and provided in the semiconductor layer 21.

[0060] The solid-state imaging device 1A according to the first embodiment further includes a multilayer wiring layer 61 provided on the first surface S1 side of the semiconductor layer 21. The solid-state imaging device 1A according to the first embodiment further includes a planarization film 71, an optical filter layer 73, and a lens layer 74 provided in this order from the second surface S2 side of the semiconductor layer 21.

[0061] Here, the first surface S1 of the semiconductor layer 21 is sometimes referred to as a main surface or element formation surface, and the second surface S2 is sometimes referred to as a back surface. The solid-state imaging device 1A according to the first embodiment is a back-illuminated image sensor that photoelectrically converts incident light incident from the second surface S2 side of the semiconductor layer 21 using a photoelectric conversion unit 25 (photodiode PD) provided in the photoelectric conversion region 22 of the semiconductor layer 21. Therefore, in the first embodiment, the second surface S2 of the semiconductor layer 21 is sometimes referred to as a light incident surface.

[0062] In addition, the solid-state imaging device 1A of this first embodiment separates the pixels 3 using an isolation structure including a shallow isolation region 31 provided in the surface layer on the first surface S1 side of the semiconductor layer 21 and a deep isolation region 41 extending from the second surface S2 side of the semiconductor layer 21 toward the first surface S1 side.

[0063] 5 , the planarization film 71 is provided on the second surface S2 side of the semiconductor layer 21 so as to cover the second surface S2 of the semiconductor layer 21, and planarizes the second surface S2 side of the semiconductor layer 21. As the planarization film 71, for example, a light-transmitting silicon oxide film can be used.

[0064] 5 , the optical filter layer 73 is provided on the side of the planarization film 71 opposite to the semiconductor layer 21 side. This optical filter layer 73 separates the color of incident light that is incident from the light incident surface side (second surface portion S2 side) of the solid-state imaging device 1A. This optical filter layer 73 includes an optical filter portion 73 a for each pixel 3 (for each photoelectric conversion region 22) that transmits light of a specific wavelength, such as, but not limited to, red (R), green (G), or blue (B).

[0065] 5 , the lens layer 74 is provided on the side of the optical filter layer 73 opposite to the planarization film 71. The lens layer 74 includes a microlens (on-chip lens) 74 a for each pixel 3 (for each photoelectric conversion region 22) that collects irradiated light and allows the collected light to efficiently enter the photoelectric conversion region 22.

[0066] That is, the pixel 3 of this first embodiment includes a photoelectric conversion region 22, a planarization film 71 provided on the second surface portion S2 side of this photoelectric conversion region 22, an optical filter portion 73a, and a microlens 74a.

[0067] Although omitted in this first embodiment, a lattice-shaped light-shielding film having a planar pattern in plan view that opens on the light-receiving surface side of each of the plurality of photoelectric conversion regions 22 may be provided between the planarization film 71 and the optical filter layer 73 so as to prevent light incident on a given photoelectric conversion region 22 from leaking into an adjacent photoelectric conversion region 22. This light-shielding film has the same lattice-shaped planar pattern as the deep isolation region 41 described below, and is positioned so as to overlap the deep isolation region 41 in plan view. As this light-shielding film, for example, a tungsten (W) film having light-shielding properties can be used.

[0068] 5 to 7 , the semiconductor layer 21 includes a deep isolation region 41 extending in the thickness direction (Z direction) of the semiconductor layer 21 and a photoelectric conversion region 22 defined by the deep isolation region 41. The semiconductor layer 21 further includes a shallow isolation region 31 provided in a surface layer portion of the first surface portion S1 of the semiconductor layer 21 and element formation regions 21a and 21b defined by the shallow isolation region 31. As shown in FIG. 5 , the photoelectric conversion region 22 and the element formation regions 21a and 21b are each provided for each pixel 3. The semiconductor layer 21 may be formed of a Si substrate, a SiGe substrate, an InGaAs substrate, or the like. In this first embodiment, although not limited thereto, an n-type semiconductor substrate made of single crystal silicon is used as the semiconductor layer 21.

[0069] 4 to 8 , the shallow isolation region 31 is provided on the first surface S1 of the semiconductor layer 21 across multiple photoelectric conversion regions 22 (multiple pixels 3) in a plan view. The shallow isolation region 31 includes a shallow recessed portion 32 provided on the first surface S1 side of the semiconductor layer 21, and an isolation insulating film 33 provided inside (inside) the shallow recessed portion 32 so as to fill the shallow recessed portion 32. The shallow recessed portion 32 can be formed by selectively etching the first surface S1 of the semiconductor layer 21 using, for example, photolithography and dry etching techniques. The isolation insulating film 33 can be formed by depositing, for example, a silicon oxide film as an insulating film on the first surface S1 side of the semiconductor layer 21 by a CVD method so as to fill the inside of the shallow recessed portion 32, and then selectively removing the silicon oxide film on the first surface S1 side of the semiconductor layer 21 by an etch-back method or a CMP method so that the silicon oxide film inside the shallow recessed portion 32 remains.

[0070] The shallow isolation region 31 separates the element formation regions 21a and 21b and electrically isolates these element formation regions. The shallow isolation region 31 is a trench type that separates and isolates the element formation regions 21a and 21b by forming shallow recesses 32 in the surface layer on the first surface S1 side of the semiconductor layer 21. The inside of the recesses 32 formed in the semiconductor layer 21 is filled with a film, and the recesses 32 are still referred to as recesses 32 even after the film is filled in.

[0071] <Element Formation Region> As shown in FIGS. 4 to 8, each of the element formation regions 21a and 21b is surrounded by a shallow isolation region 31, partitioned into islands, and insulated and isolated from each other.

[0072] 4 to 6, the element formation region 21b overlaps the photoelectric conversion region 22 in a plan view and is provided for each pixel 3 in the surface layer portion of the first surface portion S1 of the semiconductor layer 21. In this element formation region 21b, the above-mentioned transfer transistor TR and floating diffusion region FD are provided, and a power supply contact region WC is also provided.

[0073] As shown in FIGS. 4, 5, 7, and 8, the element formation region 21a is provided in the surface layer portion on the first surface S1 side of the semiconductor layer 21. The element formation region 21a is disposed between two pixel blocks 15A aligned in the X direction in a plan view, for each pixel block 15A. The element formation region 21a extends across two pixel blocks 15A aligned in the Y direction in a plan view, and also extends across four pixels 3 (3a, 3c, 3a, 3c) aligned in the Y direction in the two pixel blocks 15A. FIG. 4 illustrates two element formation regions 21a extending in the Y direction on both sides of the two pixel blocks 15A in the X direction. The element formation region 21a is provided with the above-mentioned amplification transistor AMP, selection transistor SEL, and reset transistor RST as pixel transistors Q included in the readout circuit 16A of FIG. 3. The element formation region 21a also includes a power supply contact region WC. １ is provided.

[0074] 9A , the deep separation region 41 includes a striped first planar extension 41X extending in the X direction in a plan view and a striped second planar extension 41Y extending in the Y direction. The deep separation region 41 further includes an intersection (point of intersection) where the first planar extension 41X and the second planar extension 41Y intersect with each other on the same plane. In this first embodiment, the first planar extension 41X and the second planar extension 41Y are, for example, perpendicular to each other.

[0075] The first planar extensions 41X are repeatedly arranged at predetermined intervals in the Y direction, and the second planar extensions 41Y are repeatedly arranged at predetermined intervals in the X direction. That is, the deep isolation region 41 has a grid-like planar pattern in plan view.

[0076] 9A , the deep isolation region 41 corresponding to one photoelectric conversion region 22 (one pixel 3) has a rectangular annular planar pattern (ring-shaped planar pattern) in a plan view, and surrounds the periphery of one photoelectric conversion region 22. On the other hand, as shown in FIG. 9A , the deep isolation region 41 corresponding to one pixel block 15A has a composite planar pattern having a cross-shaped planar pattern in which a first planar extension portion 41X and a second planar extension portion 41Y are arranged orthogonal to each other within the rectangular annular planar pattern.

[0077] 9A , in the deep isolation region 41 corresponding to one pixel block 15A, the intersection (intersection) 41XY between the first planar extension 41X and the second planar extension 41Y is located in the center of the pixel block 15A. The photoelectric conversion regions 22 of the four pixels 3 (3a, 3b, 3c, 3d) are arranged in a matrix (2×2) around this intersection 41XY. That is, the photoelectric conversion regions 22 of the four pixels 3 (3a, 3b, 3c, 3d) included in one pixel block 15A are adjacent to each other in the X and Y directions via the deep isolation region 41 in a plan view.

[0078] 5, the deep isolation region 41 extends from the second surface S2 side of the semiconductor layer 21 toward the first surface S1 side and terminates at a distance from the first surface S1. The deep isolation region 41 includes, but is not limited to, for example, a deep recessed portion 42 provided on the second surface S2 side of the semiconductor layer 21 and an isolation insulating film 43 provided inside (inside) the deep recessed portion 42 so as to fill the deep recessed portion 42. The deep recessed portion 42 can be formed, for example, by selectively etching the second surface S2 of the semiconductor layer 21 using photolithography and dry etching techniques. The isolation insulating film 43 can be formed by depositing, for example, a silicon oxide film as an isolation insulating film on the second surface S2 side of the semiconductor layer 21 by the ALD method so as to fill the inside of the deep recess 42, and then selectively removing the silicon oxide film on the second surface S2 side of the semiconductor layer 21 by an etch-back method or a CMP method so that the silicon oxide film inside the deep recess 42 remains.

[0079] The deep isolation region 41 separates the photoelectric conversion regions 22 and electrically and optically separates adjacent photoelectric conversion regions 22 in a plan view. That is, the deep isolation region 41 is configured as a trench type that separates and separates the photoelectric conversion regions 22 by forming deep recesses 42 that extend from the second surface S2 side of the semiconductor layer 21 toward the first surface S1 side. Here, the inside of the recesses 42 formed in the semiconductor layer 21 is filled with a film, and the recesses 42 are still referred to as recesses 42 even after the film is filled in.

[0080] <Photoelectric Conversion Region> As shown in FIG. 9B , the photoelectric conversion region 22 is surrounded by a deep isolation region 41 in a plan view and has a rectangular shape including four sides 22a, 22b, 22c, and 22d. Specifically, the photoelectric conversion region 22 includes two sides 22a and 22b located opposite each other in the X direction and two sides 22c and 22d located opposite each other in the Y direction. The photoelectric conversion region 22 is surrounded by two second planar extensions 41Y located outside each of the two sides 22a and 22b and two first planar extensions 41X located outside each of the two sides 22c and 22d. The photoelectric conversion region 22 is partitioned by a first planar extension 31x and a second planar extension 31y and is electrically and optically isolated from adjacent photoelectric conversion regions 22.

[0081] As shown in Figure 5, the photoelectric conversion region 22 has a p-type well region 23 provided in the semiconductor layer 21, an n-type semiconductor region 24 provided in this p-type well region 23, and a photoelectric conversion section 25 including the p-type well region 23 and the n-type semiconductor region 24.

[0082] 5, the p-type well region 23 is provided over a wide area across the first surface S1 side and the second surface S2 side of the semiconductor layer 21. The p-type well region 23 is provided in the photoelectric conversion region 22, and also in each of the element formation regions 21a and 21b. The p-type well region 23 is in contact with each of the shallow isolation region 31 and the deep isolation region 41. The p-type well region 23 is composed of a p-type semiconductor region doped (introduced) with impurities that exhibit p-type conductivity.

[0083] 5, the n-type semiconductor region 24 is provided in the p-type well region 23, spaced apart from the first surface portion S1 and the second surface portion S2 of the semiconductor layer 21, and the shallow isolation region 31 and the deep isolation region 41, for each photoelectric conversion region 22. The n-type semiconductor region 24 has a three-dimensional structure, and six surfaces, including the top surface, bottom surface, and four side surfaces, are surrounded by the p-type well region 23. The n-type semiconductor region 24 forms a pn junction with the p-type well region 23 on these six surfaces.

[0084] 5 , the photoelectric conversion unit 25 is provided in the photoelectric conversion region 22. The photoelectric conversion unit 25 includes a p-type well region 23 and an n-type semiconductor region 24 in the photoelectric conversion region 22. The photoelectric conversion unit 25 is configured as a p-n junction photodiode (PD) including a p-n junction between the p-type well region 23 and the n-type semiconductor region 24.

[0085] The photoelectric conversion unit 25 photoelectrically converts light incident on the n-type semiconductor region 24 from the second surface S2 side (light incident surface side) of the semiconductor layer 21 into signal charges in the n-type semiconductor region 24, and temporarily holds (accumulates) the photoelectrically converted signal charges at the pn junction between the p-type well region 23 and the n-type semiconductor region 24. The photoelectric conversion unit 25 is provided in the semiconductor layer 21, spaced apart from the first surface S1 of the semiconductor layer 21. The photoelectric conversion unit 25 is provided for each photoelectric conversion region 22 (pixel 3).

[0086] In the photoelectric conversion section 25 of the first embodiment, the well region 23 is configured as a p-type and the semiconductor region 24 is configured as an n-type, so that the signal charges photoelectrically converted by the photoelectric conversion section 25 are electrons.

[0087] 4, 6, and 9A, the floating diffusion regions FD of the four pixels 3 (3a, 3b, 3c, and 3d) included in one pixel block 15 are provided adjacent to the intersections 41XY of the deep isolation regions 41, surrounding the intersections 41XY in a plan view, outside the intersections 41XY. As shown in FIG. 6, each floating diffusion region FD is provided in the p-type well region 23 in the surface layer portion on the first surface S1 side of the semiconductor layer 21. Each floating diffusion region FD is composed of an n-type semiconductor region having a higher impurity concentration than the n-type semiconductor region 24.

[0088] 4 and 6, a relay electrode 56 is provided on the first surface S1 side of the semiconductor layer 21. The relay electrode 56 extends across the element formation region 21b and the shallow isolation region 31 in a region that overlaps with the intersection 41XY of the deep isolation region 41 in a plan view. The relay electrode 56 is electrically and mechanically connected to the floating diffusion region FD of each of the four pixels 3 (3a, 3b, 3c, 3d) included in one pixel block 15A. The relay electrode 56 may be, for example, a polycrystalline silicon film doped (introduced) with an impurity that reduces resistance.

[0089] 4 and 5 , the transfer transistor TR is provided in the element formation region 21b on the first surface S1 side of the semiconductor layer 21. The transfer transistor TR has a gate electrode 53 provided on the first surface S1 side of the semiconductor layer 21 and a gate insulating film 52 provided between the gate electrode 53 and the semiconductor layer 21. The transfer transistor TR also has an n-type semiconductor region 24 and an n-type floating diffusion region FD functioning as a source region and a drain region, and a p-type well region 23 functioning as a channel formation region. Although not limited thereto, the transfer transistor TR may have a vertical type configuration in which the gate electrode 53 extends in the thickness direction (Z direction) of the semiconductor layer 21 from inside to outside the semiconductor layer 21.

[0090] 4 and 5, the transfer transistors RT of the four pixels 3 (3a, 3b, 3c, and 3d) included in one pixel block 15A are biased toward the intersection 41XY of the deep isolation region 41 in plan view. The gate electrodes 53 of the transfer transistors TR of the four pixels 3 (3a, 3b, 3c, and 3d) are provided outside the n-type floating diffusion region FD so as to surround the intersection 41XY of the deep isolation region 41 in plan view.

[0091] 5, the gate electrode 53 of the transfer transistor TR has a head 53a provided outside the first surface S1 of the semiconductor layer 21 with the gate insulating film 52 interposed therebetween, and a body 53b that protrudes from the head 53a into the semiconductor layer 21 and is adjacent to the semiconductor layer 21 with the gate insulating film 52 interposed therebetween. The gate electrode 53 of the first embodiment is not limited to this, but for example, the body 53b is narrower than the head 53a.

[0092] The body 53b of the gate electrode 53 is provided in a gate trench (gate excavation portion) 51 of the semiconductor layer 21 with a gate insulating film 52 interposed therebetween. The body 53b of the gate electrode 53 and the gate trench 51 each extend from the first surface S1 side toward the second surface S2 side of the semiconductor layer 21 and reach the n-type semiconductor region 24.

[0093] The gate insulating film 52 is made of, for example, a silicon oxide film, and the gate electrode 53 is made of, for example, a polycrystalline silicon (doped polysilicon) film doped with impurities that reduce the resistance value.

[0094] When a gate voltage is applied to the gate electrode 53 and the transfer transistor TR is turned on, a charge transfer path (channel) electrically connecting the n-type semiconductor region 24 and the n-type floating diffusion region FD is formed in the p-type well region 23. Then, signal charges (electrons) photoelectrically converted in the n-type semiconductor region 24 of the photoelectric conversion unit 25 are transferred from the n-type semiconductor region 24 to the n-type floating diffusion region FD through the charge transfer path.

[0095] 4 and 9A , in each of the four pixels 3 (3 a, 3 b, 3 c, and 3 d) included in one pixel block 15, the p-type power supply contact region WC is provided on the other corner diagonally opposite the corner on the floating diffusion region FD side of the element formation region 21 b in a plan view. Although not shown in detail, the p-type power supply contact region WC is provided in the p-type well region 23 on the first surface S1 side of the semiconductor layer 21, and is electrically connected to this p-type well region 23. The power supply contact region WC is formed of a p-type semiconductor region having a higher impurity concentration than the p-type well region 23.

[0096] A first reference potential (Vss potential) of, for example, 0 V is applied to the p-type power supply contact region WC as a reference potential within the solid-state imaging device 1A (within the semiconductor chip 2) during operation, and the potential is fixed to this first reference potential during operation.

[0097] <Pixel Transistors> As shown in FIGS. 4 and 7, the element formation region 21a has an amplifier transistor AMP, a selection transistor SEL, and a reset transistor RST as pixel transistors Q included in one readout circuit 16A, and also has a p-type power supply contact region WC １ The reset transistor RST, the amplification transistor AMP, and the selection transistor SEL are arranged in this order in the element formation region 21a. １ are arranged next to the select transistor SEL in the Y direction.

[0098] 7, the reset transistor RST has a gate electrode 54r provided outside the first surface S1 of the semiconductor layer 21, and a gate insulating film 52 provided between the gate electrode 54r and the first surface S1 of the semiconductor layer 21. The reset transistor RST also has a pair of main electrode regions 55r and 55a that are provided in the element formation region 21a (semiconductor layer 21) on both sides of the gate electrode 54r in the gate length direction (direction of the gate length Lg) and function as a source region and a drain region. ２ The pair of main electrode regions 55r and 55a ２and a channel forming portion provided between the

[0099] 7, the amplification transistor AMP has a gate electrode 54a provided outside the first surface S1 of the semiconductor layer 21, and a gate insulating film 52 provided between the gate electrode 54a and the first surface S1 of the semiconductor layer 21. The amplification transistor AMP also has a pair of main electrode regions 55a that are provided in the element formation region 21a (semiconductor layer 21) on both sides of the gate electrode 54a in the gate length direction (direction of the gate length Lg) and function as a source region and a drain region. １ and 55a ２ and the pair of main electrode regions 55a １ and 55a ２ and a channel forming portion provided between the

[0100] 7, the select transistor SEL has a gate electrode 54s provided outside the first surface S1 of the semiconductor layer 21, and a gate insulating film 52 provided between the gate electrode 54s and the first surface S1 of the semiconductor layer 21. The select transistor SEL also has a pair of main electrode regions 55a that are provided in the element formation region 21a (semiconductor layer 21) on both sides of the gate electrode 54a in the gate length direction (direction of the gate length Lg) and function as a source region and a drain region. １ and 55s, and the pair of main electrode regions 55a １ and a channel forming portion provided between 55s.

[0101] Main electrode regions 55r, 55a １ , 55a ２ and 55s are each formed of, for example, an n-type semiconductor region provided in the p-type well region 23 of the element formation region 21a. The channel formation portions of the reset transistor RST, the amplification transistor AMP, and the selection transistor SEL are each formed of, for example, the p-type well region 23.

[0102] The gate insulating film 52 of each of the reset transistor RST, the amplifier transistor AMP, and the select transistor SEL is made of, for example, a silicon oxide film. The gate electrodes 45r, 54a, and 54s of each of the reset transistor RST, the amplifier transistor AMP, and the select transistor SEL are made of, for example, a polycrystalline silicon (doped polysilicon) film doped with impurities that reduce the resistance value.

[0103] As shown in FIG. 7, the main electrode region 55a ２ is shared by the reset transistor RST and the amplification transistor AMP. １ is shared by the amplifier transistor AMP and the select transistor SEL. That is, the reset transistor RST, the amplifier transistor AMP, and the select transistor SEL are provided in the element formation region 21 a in a state where they are connected in series in this order.

[0104] As shown in FIG. 7, the p-type power supply contact region WC １ is provided in the p-type well region 23 in the element formation region 21a and is electrically connected to the p-type well region 23. １ Like the power supply contact region WC, the power supply contact region WC is made of a p-type semiconductor region having a higher impurity concentration than the p-type well region 23. １ During operation, a first reference potential (Vss potential) of, for example, 0 V is also applied to the first reference potential (Vss potential).

[0105] <Plane pattern of photoelectric conversion region> As shown in Figure 4, each of the four pixels 3 (3a, 3b, 3c, 3d) included in one pixel block 15A has a different plane pattern, including the arrangement of each of the transfer transistor TR, floating diffusion region FD, power supply contact region WC, and element formation regions 21a, 21b, when viewed in a plan view.

[0106] In the first embodiment, as shown in Fig. 4, the planar patterns of pixels 3a and 3b arranged in the X direction are inverted patterns with the boundary between pixels 3a and 3b as the inversion axis. Furthermore, the planar patterns of pixels 3c and 3d arranged in the X direction are inverted patterns with the boundary between pixels 3c and 3d as the inversion axis. Furthermore, the planar patterns of pixels 3a and 3c arranged in the Y direction are inverted patterns with the boundary between pixels 3a and 3c as the inversion axis. Furthermore, the planar patterns of pixels 3b and 3d arranged in the Y direction are inverted patterns with the boundary between pixels 3b and 3d as the inversion axis.

[0107] 5 to 7, the multilayer wiring layer 61 is provided on the first surface S1 side of the semiconductor layer 21. The multilayer wiring layer 61 includes an interlayer insulating film 62 provided on the first surface S1 side of the semiconductor layer 21 so as to cover the element formation regions 21a, 21b and the shallow isolation region 31, and a first-layer wiring layer 64 provided on the side of the interlayer insulating film 62 opposite to the semiconductor layer 21 side. The multilayer wiring layer 61 also includes a contact electrode 63a provided in the interlayer insulating film 62. ２ , 63f, 63ga, 63gr, 63gs, 63r, 63s, 63t, 63w, etc. The first wiring layer 64 includes wirings 64a ２ , 64f, 64ga, 64gr, 64gs, 64r, 64s, 64t, 64w, etc.

[0108] Contact electrode 63a ２ , 63f, 63ga, 63gr, 63gs, 63r, 63s, 63t, and 63w can be made of, for example, tungsten (W), a high-melting-point metal. The first wiring layer 64 can be made of, for example, a metal material such as aluminum (Al) or copper (Cu), or an alloy material mainly containing Al or Cu. The interlayer insulating film 62 can be made of, for example, a silicon oxide film.

[0109] The gate electrode 53 of the transfer transistor TR, the gate electrodes 54r, 54a, 54s of the pixel transistors Q (RST, AMP, SEL), and the relay electrode 56 (see FIG. 4) are covered with an interlayer insulating film 62.

[0110] 7, the wiring 64r is electrically connected to the main electrode region 55r via a contact electrode 63r provided in the interlayer insulating film 62. ２ The contact electrode 63a provided on the interlayer insulating film 62 ２ via the main electrode region 55a ２ The wiring 64s is electrically connected to the main electrode region 55s via a contact electrode 63s provided in the interlayer insulating film 62. The wiring 64w is electrically connected to the power supply contact region WC via a contact electrode 63w provided in the interlayer insulating film 62.

[0111] 7, the wiring 64gr is electrically connected to the gate electrode 54r of the reset transistor RSG via a contact electrode 63gr provided in the interlayer insulating film 62. The wiring 64ga is electrically connected to the gate electrode 54a of the amplification transistor AMP via a contact electrode 63ga provided in the interlayer insulating film 62. This wiring 64ga is electrically connected to the wiring 64r. The wiring 64gs is electrically connected to the gate electrode 54s of the select transistor SEL via a contact electrode 63gs provided in the interlayer insulating film 62.

[0112] 6, the wiring 64f is electrically connected to the relay electrode 56 via a contact electrode 63f provided in the interlayer insulating film 62. The relay electrode 56 is electrically and mechanically connected to the floating diffusion region FD of each of the four pixels 3 (3a, 3b, 3c, and 3d) included in one pixel block 15A. The wiring 64f is electrically connected to each of the wirings 64r and 64ga.

[0113] As shown in FIG. 5, the wiring 64 t is electrically connected to the gate electrode 53 via a contact electrode 63 t provided in the interlayer insulating film 62 .

[0114] Although not shown, the power supply contact region WC in the element formation region 21b is also electrically connected to wiring provided in the first wiring layer 64 via a contact electrode provided in the interlayer insulating film 62.

[0115] <Specific configuration of shallow isolation region and deep isolation region> As shown in Figures 5 to 7, the shallow isolation region 31 includes a first shallow isolation portion 31a that partitions the element formation region 21a, and a second shallow isolation portion 31b that overlaps with the deep isolation region 41 in a planar view.

[0116] On the other hand, the deep isolation region 41 includes a first deep isolation portion 41a overlapping the element formation region 21a in a plan view and a second deep isolation portion 41b overlapping the second shallow isolation portion 31b in a plan view. The first deep isolation portion 41a has an end 41a located on the first surface S1 side of the semiconductor layer 21, as shown in FIGS. １ The bottom 31a of the first shallow isolation portion 31a １ That is, the deep isolation region 41 of the first embodiment is located (protrudes) closer to the first surface S1 side (the element forming region 21a side) of the semiconductor layer 21 than the bottom 31b of the first shallow isolation portion 31a. １ In other words, the deep isolation region 41 of the first embodiment is located (protrudes) closer to the first surface S1 side of the semiconductor layer 21 than the bottom 31b of the first shallow isolation portion 31a. １ It is located (protrudes) more toward the center of the element forming region 21a than the element forming region 21b.

[0117] The first deep isolation portion 41a is separated from the first shallow isolation portion 31a, but is not limited thereto. On the other hand, the second deep isolation portion 41b is connected to the second shallow isolation portion 31b so as to face each other in the thickness direction (Z direction) of the semiconductor layer 21. As shown in FIGS. 9B and 10A, the width W of the first deep isolation portion 41a in the lateral direction is １ is the width W of the second deep separation portion 41b in the short side direction. ２ is equivalent to the design value.

[0118] Here, the short direction of each of the first deep separation portion 41a and the second deep separation portion 41b is the arrangement direction of the two photoelectric conversion regions 22 arranged on either side of the deep separation region 41 in a planar view, in other words, the width in the direction in which the two photoelectric conversion regions 22 are separated by the deep separation region 41 in a planar view.

[0119] As shown in Figures 9A and 9B, the first deep isolation portion 41a is included in a second planar extension portion 41Y that extends in the Y direction along the boundary between two pixel blocks 15A aligned in the X direction in the grid-like planar pattern of the deep isolation region 41.

[0120] On the other hand, in the lattice-like planar pattern of the deep isolation region 41, the second deep isolation portion 41b is included in the second planar extension portion 41Y that is adjacent to the second planar extension portion 41Y including the first deep isolation portion 41a via the photoelectric conversion region 22, and is also included in each of the two first planar extension portions 41X that extend in the X direction on both sides of the Y direction of the photoelectric conversion region 22.

[0121] That is, in the deep isolation region 41 that annularly surrounds one photoelectric conversion region 22, the first deep isolation portion 41a is provided on the side 22a of the four side portions 22a, 22b, 22c, and 22d of the photoelectric conversion region 22 in a planar view, and the second deep isolation portions 41b are provided on the remaining three side portions 22b, 22c, and 22d. The element formation region 21a is provided on the side 22a of the photoelectric conversion region 22 in a planar view.

[0122] 5, the first deep isolation portion 41a and the second deep isolation portion 41b have different lengths extending from the second surface S2 side toward the first surface S1 side of the semiconductor layer 21, with the first deep isolation portion 41a being longer than the second deep isolation portion 41b. This difference in length can be achieved by first forming the deep dug portions 42 of both the first deep isolation portion 41a and the second deep isolation portion 41b, and then selectively deepening the deep dug portion 42 of the first deep isolation portion 41a. This difference in length can also be achieved by separately forming the deep dug portions 42 of different depths in the first deep isolation portion 41a and the second deep isolation portion 41b.

[0123] <<Main Effects of the First Embodiment>> Next, the main effects of the first embodiment will be described with reference to Fig. 10A and Fig. 10B. Fig. 10B is a longitudinal cross-sectional view of a main part of a conventional separation structure as a reference example. In Fig. 10B, the same reference numerals as in Fig. 10A are used, except for the path routes described below.

[0124] 10A , the solid-state imaging device 1A according to the first embodiment of the present technology includes a shallow isolation region 31 provided in a surface layer portion on the first surface portion S1 side of the semiconductor layer 21, an element formation region 21a partitioned by the shallow isolation region 31 on the first surface portion S1 side of the semiconductor layer 21 and provided with pixel transistors Q (RST, AMP, SEL), and a photoelectric conversion region 22 partitioned by a deep isolation region 41 extending from the second surface portion S2 side toward the first surface portion S1 side of the semiconductor layer 21 and provided with a photoelectric conversion unit 25 (PD). The shallow isolation region 31 includes a first shallow isolation portion 31a partitioning the element formation region 21a and a second shallow isolation portion 31b overlapping the deep isolation region 41 in a plan view. The deep isolation region 41 includes a first deep isolation portion 41a that overlaps the element formation region 21a in a plan view, and a second deep isolation portion 41b that overlaps the second shallow isolation portion 31b of the shallow isolation region 31 in a plan view. The first deep isolation portion 41a and the element formation region 21a are spaced apart.

[0125] In such an isolation structure, a path R connecting two adjacent photoelectric conversion regions 22 via the first deep isolation portion 41a is formed. １ The end 41a of the first deep separation portion 41a １ The first deep isolation portion 41a is located on the first shallow isolation portion 31a side.

[0126] Here, as shown in FIG. 10B, in the isolation structure of the conventional reference example, in the depth direction (Z direction) of the semiconductor layer 21, the end 41a of the first deep isolation portion 41a on the side of the first shallow isolation portion 31a １ and the bottom 31a of the first shallow separation portion 31a １ The first deep separation portion 41a and the first shallow separation portion 31a are at the same height position, or the end 41a of the first deep separation portion 41a on the first shallow separation portion 31a side １ However, the bottom 31a of the first shallow separation portion 31a １The first deep isolation portion 41a is located closer to the second surface S2 of the semiconductor layer 21 than the first deep isolation portion 41a. １ A path route R connecting one photoelectric conversion area 22 and the other photoelectric conversion area 22 on the side ２ is short in length.

[0127] In contrast, as shown in FIG. 10A, in the isolation structure of the first embodiment, the end 41a of the first deep isolation portion 41a overlapping the element formation region 21a in plan view １ The bottom 31a of the first shallow isolation portion 31a １ That is, in the solid-state imaging device 1A according to the first embodiment of the present technology, the end 41a of the first deep isolation portion 41a is protruded (located) toward the first surface portion S1 side (the element formation region 21a side) of the semiconductor layer 21. １ The bottom 31a of the first shallow isolation portion 31a １ The protruding portion 21a is located closer to the first surface S1 of the semiconductor layer 21 (toward the element forming region 21a) than the protruding portion 21b.

[0128] Therefore, the end 41a of the first deep separation portion 41a １ A path route R connecting one photoelectric conversion area 22 and the other photoelectric conversion area 22 on the side １ The length of the path route R shown in FIG. 10B of a conventional reference example is ２ can be made longer compared to the length of the path route R １ , it is possible to suppress leakage of signal charges from one photoelectric conversion region 22 to the other photoelectric conversion region 22. Therefore, according to the solid-state imaging device 1A according to the first embodiment, it is possible to obtain a high saturation charge amount Qs.

[0129] Furthermore, since a high saturation charge amount Qs can be obtained, the pixels 3 can be miniaturized while maintaining image quality performance.

[0130] Furthermore, the solid-state imaging device 1A of the first embodiment has an isolation structure in which the pixels 3 are separated by a shallow isolation region 31 provided on the first surface S1 side of the semiconductor layer 21 and a deep isolation region 41 extending from the second surface S2 side toward the first surface S1 side of the semiconductor layer 21. Therefore, compared to an isolation structure in which the pixels 3 are separated only by a deep isolation region extending across the first surface S1 and second surface S2 of the semiconductor layer 21, the volume of the photoelectric conversion region 22 can be made more efficient and the degree of design freedom for improving characteristics can be increased.

[0131] Furthermore, in the solid-state imaging device 1A of the first embodiment, the element formation region 21a in which the pixel transistors Q are arranged is shared by two pixel blocks 15A, each including four pixels 3 (3a, 3b, 3c, 3d) arranged in a 2x2 configuration. Therefore, compared to a case in which the element formation region 21a in which the pixel transistors Q are arranged is provided for each pixel 3, it is possible to further miniaturize the pixels while maintaining image quality performance.

[0132] In the first embodiment, the case where the element formation region 21a is provided for every two pixel blocks 15A has been described, but the element formation region 21a may be provided for every pixel block 15A, or may be configured to extend continuously across three or more pixel blocks 15A. Also, the first deep isolation portion 41a may be configured to be connected to the first shallow isolation portion 31a.

[0133] <Modifications of First Embodiment> <Modification 1-1> Fig. 11 is a diagram showing Modification 1-1 according to the first embodiment of the present technology, and is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure at the same position as the longitudinal cross-sectional view of Fig. 5. Fig. 12 is a diagram showing Modification 1-1 according to the first embodiment of the present technology, and is a plan view schematically showing a planar pattern of a deep isolation region.

[0134] As shown in FIGS. 11 and 12, in this modification 1-1, the width W １ is the width W of the second deep separation portion 41b in the lateral direction. ２ In this modification 1-1, the end 41a of the first deep isolation portion 41a is wider than the end 41a of the first deep isolation portion 41a. １ The side is the bottom 31a of the first shallow separation portion 31a. １The first deep isolation portion 41a protrudes (is positioned) closer to the first surface portion S1 of the semiconductor layer 21 (toward the element formation region 21a) than the first shallow isolation portion 31a, and the first deep isolation portion 41a is spaced apart from the first shallow isolation portion 31a.

[0135] Width W of the first deep isolation portion 41a １ is the width W of the second deep isolation portion 41b from the first surface portion S1 side to the second surface portion S2 side of the semiconductor layer 21. ２ It is wider than.

[0136] The present technology can also be applied to this modified example 1-1, and the same effects as those of the first embodiment described above can be obtained.

[0137] <Modification 1-2> FIG. 13 is a diagram showing Modification 1-2 according to the first embodiment of the present technology, and is a longitudinal cross-sectional view schematically showing the longitudinal cross-sectional structure at the same position as the longitudinal cross-sectional view of FIG. 5.

[0138] As shown in FIG. 13, in this modified example 1-2, the width W １ However, the bottom side of the element forming region 21a (the bottom 31a of the first shallow isolation portion 31a) １ Width W in the short direction at the side ３ In other words, the width W of the first deep separation portion 41a in the lateral direction is １ is the distance between the two first shallow isolation portions 31a located on both sides of the element forming region 21a in the lateral direction, in other words, the width W of the element forming region 21a in the lateral direction (X direction in FIG. 13) at the bottom side. ３ The end 41a of the first deep separation portion 41a is wider than the end 41a of the first deep separation portion 41a. １ The bottom 31a of the first shallow isolation portion 31a １ The first shallow isolation portion 31a protrudes (is located) closer to the first surface portion S1 of the semiconductor layer 21 (toward the element forming region 21a) than the first shallow isolation portion 31a. １ The first shallow isolation portion 31a is connected to the first shallow isolation portion 31a so as to close the element forming region 21a on the side thereof. That is, in this modification 1-2, the bottom of the element forming region 21a is closed by the first deep isolation portion 41a.

[0139] In this modified example 1-2, the first deep isolation portion 41a is located at the bottom 31a of the first shallow isolation portion 31a. １10A. １ Since there is basically no leakage of signal charges from one photoelectric conversion region 22 to the other photoelectric conversion region 22, it is possible to further suppress leakage of signal charges from one photoelectric conversion region 22 to the other photoelectric conversion region 22 compared to the first embodiment described above.

[0140] The first deep isolation portion 41a is located at the bottom 31a of the first shallow isolation portion 31a. １ The first shallow isolation portion 31a is connected to the first shallow isolation portion 31a so as to cover the element formation region 21a on the side thereof. Therefore, the main electrode regions 55r and 55a of the pixel transistors Q (RST, AMP, SEL) provided in the element formation region 21a are １ , 55a ２ , 55s (main electrode region 55s is exemplified in FIG. 13), the signal charges photoelectrically converted in the photoelectric conversion portion 25 of the photoelectric conversion region 22 can be prevented from leaking.

[0141] The first deep isolation portion 41a of this modification 1-2 is formed by forming the shallow isolation region 31, and then etching the semiconductor layer 21 under conditions where the etching ratio is larger than that of the shallow isolation region 31 to form the deep recessed portion 42. １ The bottom 31a of the first shallow isolation portion 31a １ The first deep isolation portion 41a does not necessarily have to close the bottom side of the element forming region 21a.

[0142] <Modification 1-3> Fig. 14 is a diagram illustrating Modification 1-3 according to the first embodiment of the present technology, and is a longitudinal cross-sectional view schematically illustrating a longitudinal cross-sectional structure at the same position as the longitudinal cross-sectional view of Fig. 5. As shown in Fig. 14, in Modification 1-3, the width in the short side direction of the first deep isolation portion 41a is different between the first surface portion S1 side and the second surface portion S2 side of the semiconductor layer 21.

[0143] That is, as shown in FIG. 14, the first deep isolation portion 41a of this modification 1-3 has a width W １ is the width W in the short direction on the second surface portion S2 side of the semiconductor layer 21. ４The first deep isolation portion 41a has two side surfaces on both sides in the short direction thereof that are inclined at an acute angle with respect to the thickness direction (Z direction) of the semiconductor layer 21. １ The side is the bottom 31a of the first shallow separation portion 31a. １ The first deep isolation portion 41a protrudes (is positioned) closer to the first surface portion S1 of the semiconductor layer 21 (toward the element formation region 21a) than the first shallow isolation portion 31a, and the first deep isolation portion 41a is spaced apart from the first shallow isolation portion 31a.

[0144] The present technology can also be applied to this modified example 1-3, and the same effects as those of the first embodiment described above can be obtained.

[0145] In addition, in the second deep isolation portion 41b of this modification 1-3, the width W ２ is the width W in the short direction on the second surface portion S2 side of the semiconductor layer 21. ５ The second deep isolation portion 41b is wider than the first deep isolation portion 41b, and two side portions located on both sides in the short direction of the second deep isolation portion 41b are inclined at an acute angle with the thickness direction of the semiconductor layer 21 (Z direction).

[0146] 15 is a diagram showing a modification 1-4 according to the first embodiment of the present disclosure, which is a longitudinal cross-sectional view schematically showing the longitudinal cross-sectional structure of the deep isolation region. As shown in FIG. 15, this modification 1-4 is a combination of the above-described modifications 1-2 and 1-3.

[0147] That is, as shown in FIG. 15, in this modified example 1-4, the width W of the first deep isolation portion 41a in the lateral direction is １ However, the bottom side of the element forming region 21a (the bottom 31a of the first shallow isolation portion 31a) １ Width W in the short direction at the side ３ The end 41a of the first deep separation portion 41a is wider than the end 41a of the first deep separation portion 41a. １ The bottom 31a of the first shallow isolation portion 31a １ The first shallow isolation portion 31a protrudes (is located) closer to the first surface portion S1 of the semiconductor layer 21 (toward the element forming region 21a) than the first shallow isolation portion 31a. １The first deep isolation portion 41a of the modified example 1-4 is connected to the first shallow isolation portion 31a so as to cover the element formation region 21a on the side of the first surface portion S1 of the semiconductor layer 21. １ is the width W in the short direction on the second surface portion S2 side of the semiconductor layer 21. ４ The first deep isolation portion 41a is wider than the first deep isolation portion 41b, and two side portions located on both sides in the short direction of the first deep isolation portion 41a are inclined at an acute angle with the thickness direction (Z direction) of the semiconductor layer 21.

[0148] The present technology can also be applied to this modification 1-4, and the same effects as those of the above-described modification 1-2 can be obtained.

[0149] <Modification 1-5> Fig. 16 is a diagram showing Modification 1-5 according to the first embodiment of the present technology, and is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure at the same position as the longitudinal cross-sectional view of Fig. 5. Fig. 17 is a diagram showing Modification 1-5 according to the first embodiment of the present technology, and is a plan view schematically showing a planar pattern of a deep isolation region.

[0150] In this modified example 1-5, the configuration of the first deep isolation portion 41a is different from that of the first embodiment described above. That is, as shown in FIG. 16, the first deep isolation portion 41a in this modified example 1-5 includes a main deep isolation portion 41aa extending from the second surface portion S2 side of the semiconductor layer 21 toward the first surface portion S1 side, and a deep isolation extension portion 41ab that is integrated with the main deep isolation portion 41aa on the element formation region 21a side of the main deep isolation portion 41aa and that extends further toward the photoelectric conversion region 22 than the main deep isolation portion 41aa. The deep isolation extension portion 41ab has a width in the lateral direction that is wider than the width in the lateral direction on the bottom side of the element formation region 21a, and is connected to the first shallow isolation portion 31a so as to close the bottom side of the element formation region 21a. In this modified example 1-5 as well, the end portion 41a of the first deep isolation portion 41a １ The side is the bottom 31a of the first shallow separation portion 31a. １The deep isolation extension 41ab protrudes (is positioned) toward the first surface S1 side (the element formation region 21a side) of the semiconductor layer 21 more than the first surface S1 side. As shown in Fig. 17, the deep isolation extension 41ab extends along the longitudinal direction (Y direction) of the element formation region 21a in a plan view. As shown in Fig. 16, the deep isolation extension 41ab has an elliptical cross section in a longitudinal section along the short side direction of the deep isolation extension 41ab.

[0151] In this modified example 1-5, the bottom side of the element formation region 21a is blocked by the deep isolation extension 41ab of the first deep isolation portion 41a, so that the path route R shown in FIG. 10A is １ The bottom side of the element formation region 21a is isolated from the photoelectric conversion region 22 by the deep isolation extension 41ab of the first deep isolation portion 41a. Therefore, the present technology can also be applied to this modification 1-5, and the same effects as those of the above-described modification 1-2 can be obtained.

[0152] 16, the second deep isolation portion 41b of this modification 1-5, like the first deep isolation portion 41a, includes a main deep isolation portion 41ba extending from the second surface S2 side of the semiconductor layer 21 toward the first surface S1 side, and a deep isolation extension portion 41bb that is integral with the main deep isolation portion 41ba on the second shallow isolation portion 31b side of the main deep isolation portion 41ba and extends further toward the photoelectric conversion region 22 than the main deep isolation portion 41ba. The deep isolation extension portion 41bb is connected to the second shallow isolation portion 31b on the bottom side of the second shallow isolation portion 31b.

[0153] Furthermore, the main deep isolation portions 41aa, 41ba and the deep isolation extension portions 41ab, 41bb can be easily formed by changing the etching conditions to form the deep excavated portion 42 in stages.

[0154] <Modification 1-6> Fig. 18 is a diagram showing Modification 1-6 according to the first embodiment of the present technology, and is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure at the same position as the longitudinal cross-sectional view of Fig. 5. Fig. 19 is a diagram showing Modification 1-6 according to the first embodiment of the present technology, and is a plan view schematically showing a planar pattern of a deep isolation region.

[0155] In this modification 1-6, the configuration of the deep isolation extension 41ab of the first deep isolation portion 41a is different from that of the above-described modification 1-5. That is, as shown in FIG. 18, the deep isolation extension 41ab of this modification 1-6 has a rectangular cross section along the thickness direction (Z direction) of the semiconductor layer 21. The first deep isolation portion 41a of this modification 1-5 has a T-shaped cross section along the short side direction of the first deep isolation portion 41a. As shown in FIG. 19, the deep isolation extension 41ab of this modification 1-6 also extends along the longitudinal direction (Y direction) of the element formation region 21a in a plan view.

[0156] 18, the first deep isolation portion 41a of this modified example 1-6 also includes a main deep isolation portion 41aa extending from the second surface portion S2 side of the semiconductor layer 21 toward the first surface portion S1 side, and a deep isolation extension portion 41ab that is provided integrally with the main deep isolation portion 41aa on the element formation region 21a side of the main deep isolation portion 41aa and that extends further toward the photoelectric conversion region 22 than the main deep isolation portion 41aa. The deep isolation extension portion 41ab has a width in the lateral direction that is wider than the width in the lateral direction on the bottom side of the element formation region 21a, and is connected to the first shallow isolation portion 31a so as to close the bottom side of the element formation region 21a. Also in this modified example 1-6, the end portion 41a of the first deep isolation portion 41a １ The side is the bottom 31a of the first shallow separation portion 31a. １ The protruding portion 21 protrudes (is positioned) toward the first surface portion S1 side (element forming region 21a side) of the semiconductor layer 21 more than the protruding portion 21a side.

[0157] In this modification 1-6, as in the above-described modification 1-2, the path route R shown in FIG. １The bottom side of the element formation region 21a is isolated from the photoelectric conversion region 22 by the deep isolation extension 42ab of the first deep isolation portion 41a. Therefore, the present technology can also be applied to this modification 1-6, and the same effects as those of the above-described modification 1-2 can be obtained.

[0158] In this modified example 1-6, the second deep isolation portion 41b has the same configuration as the second deep isolation portion 41b of the first embodiment described above.

[0159] <Modification 1-7> Fig. 20A is a diagram showing Modification 1-7 according to the first embodiment of the present technology, and is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure at the same position as the longitudinal cross-sectional view of Fig. 5. Fig. 20B is a longitudinal cross-sectional view of a main part in which a part of Fig. 20A is enlarged.

[0160] As shown in FIG. 20A, in this modified example 1-7, the longitudinal cross-sectional shape of the first shallow isolation portion 31a along the short side direction is an inverse tapered shape compared to the first shallow isolation portion 31a of the above-mentioned modified example 1-2 shown in FIG. 13.

[0161] That is, as shown in FIG. 20B, the first shallow isolation portion 31a of this modification 1-7 has a width Wa in the lateral direction on the first surface S1 side of the semiconductor layer 21 in a longitudinal cross section along the lateral direction of the first shallow isolation portion 31a (the X direction in FIG. 20A). １ However, the bottom 31a of the first shallow separation portion 31a １ Width in the short direction at the side Wa ２ The first shallow isolation portion 31a is narrower (has a narrower width) than the first shallow isolation portion 31a, and the two side portions on both sides of the short side of the first shallow isolation portion 31a are inclined at an acute angle with the thickness direction (Z direction) of the semiconductor layer 21, resulting in an inverse tapered shape compared to the first shallow isolation portion 31a of the above-mentioned variant 1-2.

[0162] In this modified example 1-7, the end 41a of the first deep isolation portion 41a １ The bottom 31a of the first shallow isolation portion 31a １ and the first deep isolation portion 41a is located closer to the first surface S1 of the semiconductor layer 21 (toward the element forming region 21a). １ The bottom 31a of the first shallow isolation portion 31a １The first shallow isolation portion 31a is connected to the first shallow isolation portion 31a so as to cover the element formation region 21a on the side.

[0163] In this modification 1-7, as in the above-described modification 1-2, the path route R shown in FIG. １ The bottom side of the element formation region 21a is separated from the photoelectric conversion region 22 by the first deep isolation portion 41a. Therefore, the present technology can also be applied to this modification 1-7, and the same effects as those of the above-described modification 1-2 can be obtained.

[0164] Furthermore, the first shallow isolation portion 31a of this modification 1-7 has a vertical cross-sectional shape along the short side of the first shallow isolation portion 31a that is reverse tapered compared to the first shallow isolation portion 31a of the above-described modification 1-2. Therefore, the bottom side of the element formation region 21a can be blocked by the first deep isolation portion 41a, which has a narrower width in the short side compared to the first shallow isolation portion 31a of the above-described modification 1-2, and the volume of the photoelectric conversion region 22 can be increased compared to the above-described modification 1-2.

[0165] Furthermore, since the width in the short direction (X direction in Figure 20B) at the top side of the element formation region 21a is wider than the width in the short direction at the bottom side of the element formation region 21a, the width in the short direction of the first deep isolation portion 41a can be narrowed from the first surface portion S1 side to the second surface portion S2 side of the semiconductor layer 21 while ensuring the gate width of the pixel transistor Q mounted in this element formation region 21a.

[0166] In this modified example 1-7, the second shallow isolation portion 31b also has a vertical cross section along the short side direction that is inversely tapered, similar to the first shallow isolation portion 31a.

[0167] <Modification 1-8> FIG. 21 is a diagram showing Modification 1-8 according to the first embodiment of the present technology, and is a longitudinal cross-sectional view schematically showing the longitudinal cross-sectional structure at the same position as the longitudinal cross-sectional view of FIG. 5.

[0168] As shown in FIG. 21, in this modified example 1-8, the configuration of the first shallow isolation portion 31a is different from that of the first embodiment described above.

[0169] 21, the first shallow isolation portion 31a of this modified example 1-8 includes a main shallow isolation portion 31aa extending from the first surface portion S1 side of the semiconductor layer 21 toward the second surface portion S2 side, and a shallow isolation extension portion 31ab that is provided integrally with the main shallow isolation portion 31aa on the photoelectric conversion region 22 side of the main shallow isolation portion 31aa and that extends further in the lateral direction of the main shallow isolation portion 31aa (the X direction in FIG. 21) than the main shallow isolation portion 31aa. The shallow isolation extension portion 31ab extends toward the bottom side of the element formation region 21a. The end portion 41a of the first deep isolation portion 41a １ The shallow isolation extension 31ab of the first shallow isolation portion 31a is connected to the shallow isolation extension 31ab of the first shallow isolation portion 31a so as to close the bottom side of the element formation region 21a together with the shallow isolation extension 31ab of the first shallow isolation portion 31a.

[0170] The shallow isolation extension 31ab has, for example, an elliptical cross section along the short-side direction of the first shallow isolation portion 31a (the X direction in FIG. 22). Although not shown in detail, each of the main shallow isolation portion 31aa and the shallow isolation extension 31ab extends along the longitudinal direction (the Y direction) of the element formation region 21a in plan view.

[0171] In this modified example 1-8, the end 41a of the first deep isolation portion 41a １ The bottom 31a of the first shallow isolation portion 31a １ and the first deep isolation portion 41a is located closer to the first surface S1 of the semiconductor layer 21 (toward the element forming region 21a). １ The bottom 31a of the first shallow isolation portion 31a １ The shallow isolation extension 31ab is connected to the first shallow isolation portion 31a so as to block the element formation region 21a together with the shallow isolation extension 31ab of the first shallow isolation portion 31a.

[0172] In this modification 1-8, as in the above-described modification 1-2, the path route R shown in FIG. １ The bottom side of the element formation region 21a is isolated from the photoelectric conversion region 22 by the shallow isolation extension 31ab of the first shallow isolation portion 31a and the first deep isolation portion 41a. Therefore, the present technology can also be applied to this modification 1-8, and the same effects as those of the above-described modification 1-2 can be obtained.

[0173] In this modification 1-8, the bottom side of the element forming region 21a is surrounded by the shallow isolation extension 31ab of the first shallow isolation portion 31a and the end 41a of the first deep isolation portion 41a. １ Since the first deep isolation portion 41a is blocked on the side, the width in the short direction of the first deep isolation portion 41a can be narrower than that of the first deep isolation portion 41a in the above-mentioned variant 1-2, and the volume of the photoelectric conversion region 22 can be increased compared to that of the above-mentioned variant 1-2.

[0174] Furthermore, since the width in the short direction at the top side of the element formation region 21a is wider than the width in the short direction at the bottom side of the element formation region 21a, the bottom side of the element formation region 21a can be separated from the photoelectric conversion region 22 while ensuring the gate width of the pixel transistor Q mounted in this element formation region 21a.

[0175] <Modification 1-9> FIG. 22 is a diagram showing Modification 1-9 according to the first embodiment of the present technology, and is a longitudinal cross-sectional view schematically showing the longitudinal cross-sectional structure at the same position as the longitudinal cross-sectional view of FIG. 5.

[0176] In this modification 1-9, the configurations of the shallow isolation region 31 and the deep isolation region 41 are different from those of the first embodiment.

[0177] 22, the first shallow isolation portion 31a of this modified example 1-9 includes a main shallow isolation portion 31aa provided on each side of the element formation region 21a in the short-side direction (X direction in FIG. 22) and extending from the first surface portion S1 side toward the second surface portion S2 side of the semiconductor layer 21, and an isolation blocking portion 31ac integrated with the main shallow isolation portion 31aa so as to block the element formation region 21a on the first deep isolation portion 41a side of the main shallow isolation portion 31aa. １ The side is connected to the separating and blocking part 31ac.

[0178] That is, in this modified example 1-9, the shallow isolation region 31 including the first shallow isolation portion 31a includes an isolation blocking portion 31ac that blocks the bottom side of the element formation region 21a, and the deep isolation region 41 including the first deep isolation portion 41a has a portion that overlaps with the element formation region 21a in a planar view connected to the isolation blocking portion 31ac of the shallow isolation region 31.

[0179] In this modification 1-9, as in the above-described modification 1-2, the path route R shown in FIG. １ The bottom side of the element formation region 21a is isolated from the photoelectric conversion region 22 by the isolation blocking portion 31ac of the first shallow isolation portion 31a. Therefore, the present technology can also be applied to this modification 1-9, and the same effects as those of the above-described modification 1-2 can be obtained.

[0180] <Modification 1-10> FIG. 23 is a diagram showing Modification 1-10 according to the first embodiment of the present technology, and is a longitudinal cross-sectional view schematically showing the longitudinal cross-sectional structure at the same position as the longitudinal cross-sectional view of FIG. 5.

[0181] As shown in FIG. 23, this modified example 1-10 differs from the first embodiment described above in the longitudinal cross-sectional structure of the deep isolation region 41 including each of the first deep isolation portion 41a and the second deep isolation portion 41b.

[0182] That is, each of the first deep isolation portion 41a and the second deep isolation portion 41b of this modified example 1-10 includes a deep dug portion 42 extending from the second surface portion S2 side toward the first surface portion S1 side of the semiconductor layer 21, an insulating thin film 43a provided along the inner wall surface portion of this deep dug portion 42, and a conductor 45 provided in the deep dug portion 42 via this insulating thin film 43a. The conductor 45 is provided so as to fill the inside of the deep dug portion 42 with the insulating thin film 44a interposed therebetween.

[0183] The insulating thin film 43a may be, for example, a silicon oxide film. The conductor 45 may be, for example, a metal film containing tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), or the like, or a polycrystalline silicon (doped polysilicon) film doped with impurities that reduce resistance. Alternatively, the conductor 45 may be a non-doped polysilicon film that does not contain impurities.

[0184] This modification 1-10 also provides the present technology, and the same effects as those of the first embodiment described above can be obtained.

[0185] <Modification 1-11> FIG. 24 is a diagram showing Modification 1-11 according to the first embodiment of the present technology, and is a longitudinal cross-sectional view schematically showing the longitudinal cross-sectional structure at the same position as the longitudinal cross-sectional view of FIG. 5.

[0186] As shown in FIG. 24, this modified example 1-11 differs from the first embodiment described above in the longitudinal cross-sectional structure of the deep isolation region 41 including each of the first deep isolation portion 41a and the second deep isolation portion 41b.

[0187] That is, each of the first deep isolation portion 41a and the second deep isolation portion 41b of this modification 1-10 is provided between the deep carved portion 42 and the isolation insulating film 43, and further includes a fixed charge film 46 having a fixed charge.

[0188] The fixed charge film 46 is provided along the inner side and bottom surfaces of the deep recess 42, in other words, along the side surfaces of the photoelectric conversion region 22 (side surfaces of the semiconductor layer 21). The fixed charge film 46 is in contact with the p-type well region 23 of the photoelectric conversion region 22 along the thickness direction (Z direction) of the semiconductor layer 21.

[0189] In this modification 1-11, the signal charges photoelectrically converted by the photoelectric conversion unit 25 are electrons, and the well region 23 in contact with the deep isolation region 41 is a p-type semiconductor region. Therefore, the fixed charge film 46 in this modification 1-11 has negative fixed charges.

[0190] The material of the fixed charge film 46 is an insulating material containing at least one of Si, N, Al, Hf, Ta, Ti, O, Ca, Mg, Li, Sr, Sc, Ba, Nb, W, Mo, Zr, La, Gd, and Y. For example, the fixed charge film 46 may be a silicon nitride (SiN) film, an aluminum oxide (Al ２ O ３ ) film, silicon oxide (SiO ２ ) film, silicon oxynitride (SiON) film, aluminum oxynitride (AlON) film, silicon aluminum nitride (SiAlN) film, magnesium oxide (MgO), silicon aluminum oxide (AlSiO) film, hafnium oxide (HfO ２ ) film, hafnium aluminum oxide (HfAlO) film, tantalum oxide (Ta ２ O ３ ) film, titanium oxide (TiO２ ) film, scandium oxide (Sc ２ O ３ ) film, zirconium oxide (ZrO ２ ) film, gadolinium oxide (Gd ２ O ３ ) film, lanthanum oxide (La ２ O ３ ) film or yttrium oxide (Y ２ O ３ ), niobium pentoxide (Nb ２ O ５ ), calcium oxide (CaO), lithium oxide (Li ２ O), strontium oxide (SrO), barium oxide (BaO), tungsten oxide (WO ３ ), or molybdenum oxide (MoO ３ In this modification 1-11, the fixed charge film 46 having a negative fixed charge may be made of, for example, aluminum oxide (Al ２ O ３ ) membrane is used.

[0191] The fixed charge film 46 allows holes (h ＋ ) is induced, and pinning can be ensured at this interface, thereby suppressing the generation of dark current.

[0192] The present technology can also be applied to this modified example 1-11, and the same effects as those of the first embodiment described above can be obtained, while the generation of dark current can be suppressed.

[0193] In addition, when the signal charge photoelectrically converted by the photoelectric conversion unit 25 is a hole, the semiconductor region 24 is p-type, and the well region 23 in contact with the deep isolation region 41 is n-type, a fixed charge film having a positive fixed charge is used instead of the fixed charge film 46 having a negative fixed charge.

[0194] <Modification 1-12> FIG. 25 is a diagram showing Modification 1-11 according to the first embodiment of the present technology, and is a longitudinal cross-sectional view schematically showing the longitudinal cross-sectional structure at the same position as the longitudinal cross-sectional view of FIG. 5.

[0195] 25, this modified example 1-12 further includes a pinning layer 47 that is provided in contact with the well region 23 on the semiconductor layer 21 side of the interface between the deep recess 42 and the semiconductor layer 21, and that has the same conductivity type as the well region 23 but a higher impurity concentration than the well region 23. The pinning layer 47 is electrically connected to wiring to which a potential is applied (supplied), although this is not shown. The potential may be a power supply potential supplied from a power supply generating circuit provided inside the solid-state imaging device 1A or a power supply potential supplied from outside the solid-state imaging device 1A via the bonding pad 14. These power supply potentials may include, for example, a first reference potential V of "0V". １ And this first reference potential V １ a second reference potential V ２ And this first reference potential V １ a third reference potential V ３ etc.

[0196] In this modification 1-12, the signal charges photoelectrically converted by the photoelectric conversion unit 25 are electrons, the semiconductor region 24 is n-type, and the well region is p-type, so a p-type pinning layer 47 is used. When the pinning layer 47 is p-type, a third reference potential that is a negative potential is applied to the pinning layer 47 during operation of the solid-state imaging device 1A.

[0197] On the other hand, when the signal charges photoelectrically converted by the photoelectric conversion unit 25 are holes, the semiconductor region 24 is p-type, and the well region 23 is n-type, an n-type pinning layer 47 is used. When the pinning layer 47 is n-type, the second reference potential V ２ is applied to the pinning layer 47 .

[0198] By providing this pinning layer 47, holes (h ＋ ) is induced, and pinning can be ensured at this interface, thereby suppressing the generation of dark current.

[0199] The present technology can also be applied to this modified example 1-12, and the same effects as those of the first embodiment described above can be obtained, while the generation of dark current can be suppressed.

[0200] When the signal charges photoelectrically converted by the photoelectric conversion portion 25 are holes, the semiconductor region 24 is p-type, and the well region 23 in contact with the deep isolation region 41 is n-type, an n-type pinning layer 47 is used.

[0201] [Second embodiment] Fig. 26 is an equivalent circuit diagram showing a configuration example of a pixel block and a readout circuit in a solid-state imaging device according to a second embodiment of the present technology. Fig. 27 is a plan view schematically showing a configuration example of a pixel block included in a pixel array section in a solid-state imaging device according to the second embodiment of the present technology. Fig. 28 is a longitudinal sectional view schematically showing a longitudinal sectional structure taken along the a27-a27 cutting line in Fig. 27.

[0202] A solid-state imaging device 1B according to the second embodiment of the present technology basically has the same configuration as the solid-state imaging device 1A according to the first embodiment described above, but differs in the following configuration.

[0203] That is, as shown in Fig. 26 , a solid-state imaging device 1B according to the second embodiment of the present technology includes a readout circuit 16B instead of the readout circuit 16A of the first embodiment shown in Fig. 3. The readout circuit 16B includes, as pixel transistors Q, a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL, similar to the readout circuit 16A of the first embodiment, and also includes a new switching transistor FDG.

[0204] In this readout circuit 16B, the source region of the reset transistor RST is electrically connected to the drain region of the switching transistor FDG. The source region of the switching transistor FDG is electrically connected to the gate electrode of the amplifier transistor AMP and is also electrically connected to the floating diffusion regions FD of each of the eight shared pixels 3 (3a, 3b, 3c, 3d, 3a, 3b, 3c, 3d). The gate electrode of the switching transistor FDG is electrically connected to a switching transistor drive line among the pixel drive lines 10 shown in FIG. 2. The switching transistor FDG controls charge retention by the floating diffusion region FD and adjusts the voltage multiplication factor according to the potential amplified by the amplifier transistor AMP.

[0205] As shown in FIGS. 27 and 28, the switching transistor FDG, the reset transistor RST, the amplification transistor AMP, and the selection transistor SEL are provided in the element formation region 21a in a state of being connected in series in this order.

[0206] 28 , the switching transistor FDG has a gate electrode 54fd provided outside the first surface S1 of the semiconductor layer 21, and a gate insulating film 52 provided between the gate electrode 54fd and the first surface S1 of the semiconductor layer 21. The switching transistor FDG also has a pair of main electrode regions 55r and 55fd provided in the element formation region 21a (semiconductor layer 21) on both sides of the gate electrode 54fd in the gate length direction (direction of the gate length Lg) and functioning as a source region and a drain region, and a channel formation portion provided between the pair of main electrode regions 55r and 55fd.

[0207] The main electrode region 55fd of the switching transistor FDG, like the other pixel transistors Q, is made up of, for example, an n-type semiconductor region provided in the p-type well region 23 of the element formation region 21a. The channel formation portion is also made up of, for example, the p-type well region 23. The gate electrode 54fd is also made up of a doped polysilicon film.

[0208] 28 , the main electrode region 55r is shared by the switching transistor FDG and the reset transistor RST. In the second embodiment, the wiring 64r is electrically connected to the main electrode region 55fd via a contact electrode 63r. The gate electrode 54fd of the switching transistor FDG is electrically connected to a wiring 64gf provided in the first wiring layer 64 via a contact electrode 63gf provided in the interlayer insulating film 62.

[0209] The present technology can also be applied to the solid-state imaging device 1B of the second embodiment, and the same effects as those of the solid-state imaging device 1A of the first embodiment described above can be obtained.

[0210] 29 is an equivalent circuit diagram showing a configuration example of a pixel block and a readout circuit in a solid-state imaging device according to a third embodiment of the present technology. Fig. 30 is a plan view schematically showing a configuration example of a pixel block included in a pixel array unit in the solid-state imaging device according to the third embodiment of the present technology.

[0211] A solid-state imaging device 1C according to the third embodiment of the present technology basically has the same configuration as the solid-state imaging device 1A according to the first embodiment described above, but differs in the following configuration.

[0212] That is, as shown in FIG. 3, the solid-state imaging device 1A according to the first embodiment described above has a readout circuit 16A for every two pixel blocks 15A, and has a circuit configuration in which one readout circuit 16A is assigned to each of the two pixel blocks 15A.

[0213] In contrast, as shown in Figure 29, the solid-state imaging device 1C according to the third embodiment of the present technology has one readout circuit 16A for each pixel block 15A, and has a circuit configuration in which one readout circuit 16A is assigned to one pixel block 15A.

[0214] 30 , the solid-state imaging device 1C according to the third embodiment of the present technology includes one element formation region 21 a for each pixel block 15 A. In each element formation region 21 a, a pixel transistor Q (SRT, AMP, SEL) included in one readout circuit 16 A is provided for each readout circuit 16 A.

[0215] The present technology can also be applied to the solid-state imaging device 1C of the third embodiment, and the same effects as those of the solid-state imaging device 1A of the first embodiment described above can be obtained.

[0216] In this third embodiment, the case where an element formation region 21a is provided for each pixel block 15A has been described, but the element formation region 21a may be provided for every two pixel blocks 15A, or may be configured to extend continuously across three or more pixel blocks 15A.

[0217] [Fourth embodiment] Fig. 31 is a diagram showing a configuration example of a solid-state imaging device according to a fourth embodiment of the present technology, and is a plan view schematically showing a configuration example of a pixel block included in a pixel array section. Fig. 32 is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the a31-a31 cutting line in Fig. 31. Fig. 33 is an enlarged longitudinal cross-sectional view of a main part obtained by enlarging a part of Fig. 32.

[0218] 31 and 32 , a solid-state imaging device 1D according to a fourth embodiment of the present technology has a configuration basically similar to that of the solid-state imaging device 1A according to the first embodiment described above, but differs in the configuration of a first shallow isolation portion 31 a included in a shallow isolation region 31. That is, as shown in FIGS. 32 and 33 , the first shallow isolation portion 31 a according to the fourth embodiment includes a shallow recessed portion 32 provided on the first surface portion 21 a side of the semiconductor layer 21, an isolation insulating film 33 provided inside the shallow recessed portion 32 so as to fill the shallow recessed portion 32, and a light reflecting film 35 interposed between the shallow recessed portion 32 and the isolation insulating film 33 and having a higher light reflectivity than the isolation insulating film 33. The light reflecting film 35 has a thickness such that it does not fill the shallow recessed portion 32, and is provided continuously along the semiconductor layer 21 inside the shallow recessed portion 32.

[0219] In the fourth embodiment, for example, a silicon oxide film is used as the isolation insulating film 33, and therefore an insulating film having a higher light reflectance than a silicon oxide film, such as an aluminum oxide (AlO) film, a tantalum oxide (TaO) film, or a silicon nitride (SiN) film, can be used as the light reflecting film 35. Although the expression is different, a light-shielding film having a lower light transmittance than the isolation insulating film 33, or a light-absorbing film having a higher light absorption rate than the isolation insulating film 33 can also be used instead of the light reflecting film 35.

[0220] The light reflecting film 35 is provided in at least the first portion 31a of the first shallow isolation portion 31a and the second shallow isolation portion 31b of the shallow isolation region 31. In this fourth embodiment, the light reflecting film 35 is selectively provided in the first shallow isolation portion 31a of the shallow isolation region 31, but is not provided in the second shallow isolation portion 31b of the shallow isolation region 31. That is, in the shallow isolation region 31 of this fourth embodiment, the first shallow isolation portion 31a is configured to include the light reflecting film 35, while the second shallow isolation portion 31b is configured not to include the light reflecting film 35.

[0221] 31 and 32, the element formation region 21a is mainly defined by a pair of first shallow isolation portions 31a and 31a that are included in the shallow isolation region 31 and are spaced apart from each other in the X direction. On the other hand, the element formation region 21b is mainly defined by the first shallow isolation portion 31a and the second shallow isolation portion 31b that are included in the shallow isolation region 31. The element formation region 21a is shared by two pixels 3 that are straddled by the element formation region 21a in plan view. In FIGS. 31 and 32, the pixel 3a and the pixel 3b to the left of this pixel 3a share the element formation region 21a.

[0222] Color Mixing: Here, color mixing between two pixels 3 sharing an element formation region 21 will be described with reference to FIGS. 32 and 33 . Light incident on the photoelectric conversion region 22 from the second surface S2 side (light incident surface side) of the semiconductor layer 21 is photoelectrically converted and absorbed by the photoelectric conversion unit 25 of the photoelectric conversion region 22. Meanwhile, unabsorbed long-wavelength light is irradiated as oblique light onto the first shallow isolation portion 31a of the shallow isolation region 31 on the first surface S1 side of the semiconductor layer 21. The oblique light irradiated onto the first shallow isolation portion 31a is not only reflected or absorbed by the first shallow isolation portion 31a, but also passes through the first shallow isolation portion 31a and enters the element formation region 21a. The light incident on the element formation region 21a is reflected by the gate electrode 54a of the amplifier transistor AMP provided in the element formation region 21a in the figure, and may enter the photoelectric conversion region 22 of the adjacent pixel 3 sharing this element formation region 21a as unwanted light. This unnecessary light induces color mixing and is a factor that leads to deterioration of image quality, so it is desirable to suppress it as much as possible.

[0223] 32 and 33 , the first shallow isolation portion 31 a in the fourth embodiment has a light-reflecting film 35 between the recessed portion 32 and the isolation insulating film 33, the light-reflecting film 35 having a higher light reflectivity than the isolation insulating film 33. Therefore, compared to a configuration in which the first shallow isolation portion 31 a that partitions the element formation region 21 a does not include the light-reflecting film 35, the reflection of long-wavelength light (oblique light) irradiated onto the first shallow isolation portion 31 can be improved, and the phenomenon in which the long-wavelength light (oblique light) irradiated onto the first shallow isolation portion 31 a passes through the first shallow isolation portion 31 a and enters the element formation region 21 a can be suppressed. In other words, between two pixels 3 that share the element formation region 21 a, it is possible to suppress the incidence of light that passes through the first shallow isolation portion 31 a and travels from the photoelectric conversion region 22 of one pixel 3 to the photoelectric conversion region 22 of the other pixel 3.

[0224] Although the amplification transistor AMP is shown as an example in Figures 32 and 33, reflection of light at the gate electrode provided in the element formation region 21a occurs not only in the gate electrode 54a of the amplification transistor AMP but also in other pixel transistors Q arranged in the element formation region 21a, such as the gate electrode 54s of the selection transistor SET and the gate electrode 54r of the reset transistor RST.

[0225] <<Major Effects of the Fourth Embodiment>> As shown in FIG. 33 , the shallow isolation region 31 according to the fourth embodiment has an end 41 a of the first deep isolation portion 41 a that overlaps in plan view with the element formation region 21 a partitioned by the first shallow isolation portion 31 a of the shallow isolation region 31. １ The bottom 31a of the first shallow isolation portion 31a １ Since the isolation structure is positioned (protrudes) closer to the first surface S1 side (element formation region 21a side) of the semiconductor layer 21 than the first surface S1 side, the same effects as those of the first embodiment can be obtained.

[0226] Furthermore, in the shallow isolation region 31 according to the fourth embodiment, the first shallow isolation portion 31a that partitions the element formation region 21a includes a shallow recess 32, an isolation insulating film 33, and a light reflecting film 35. As a result, between two pixels 3 (pixel 3a and the left-side pixel 3b in FIG. 33 ) that share the element formation region 21a, it is possible to suppress the incidence of light that passes through the first shallow isolation portion 31a from the photoelectric conversion region 22 of one pixel 3 to the photoelectric conversion region 22 of the other pixel 3, thereby suppressing color mixing between these pixels 3. Furthermore, since the amount of return light that is generated by the long-wavelength light (oblique light) irradiated onto the first shallow isolation portion 31a and reflected by the first shallow isolation portion 31a and returns to the photoelectric conversion region 22 increases, it is possible to suppress color mixing and improve the quantum efficiency Qe.

[0227] <Modification of Fourth Embodiment> <Modification 4-1> FIG. 34 is a diagram showing Modification 4-1 according to the fourth embodiment of the present technology, and is a longitudinal cross-sectional view schematically showing the longitudinal cross-sectional structure at the same position as the longitudinal cross-sectional view of FIG. 32 .

[0228] 34, in this modification 4-1, the second shallow isolation portion 31b of the shallow isolation region 31, which overlaps with the second deep isolation portion 41b of the deep isolation region 41 in plan view, is configured to include a light reflecting film 35, similar to the first shallow isolation portion 31a. That is, in the shallow isolation region 31 of this modification 4-1, the first shallow isolation portion 31a and the second shallow isolation portion 31b each include a shallow recessed portion 32, an isolation insulating film 33 provided inside this shallow recessed portion 32, and a light reflecting film 35 interposed between the recessed portion 32 and the isolation insulating film 33 and having a higher light reflectance than the isolation insulating film 33.

[0229] This modification 4-1 also provides the same effects as those of the above-described embodiment 4. Furthermore, in this modification 4-1, between two pixels 3 adjacent to each other via the second deep isolation portion 41b of the deep isolation region 41, it is possible to suppress the incidence of light from the photoelectric conversion region 22 of one pixel 3 to the photoelectric conversion region 22 of the other pixel 3 by transmitting through the second shallow isolation portion 31b, and it is possible to suppress color mixing between the two pixels 3 adjacent to each other via the second deep isolation portion 41b.

[0230] <Modification 4-2> FIG. 35 is a diagram showing Modification 4-2 according to the fourth embodiment of the present technology, and is a longitudinal cross-sectional view schematically showing the longitudinal cross-sectional structure at the same position as the longitudinal cross-sectional view of FIG. 32.

[0231] This modified example 4-2 is a combination of the first deep isolation portion 41a shown in FIG. 13 of the modified example 1-2 of the first embodiment and the shallow isolation portion 31a shown in FIG. 32 of the fourth embodiment.

[0232] That is, as shown in FIG. 35, the first deep isolation portion 41a of the deep isolation region 41 according to this modification 4-2 has a width W １ However, the bottom side of the element forming region 21a (the bottom 31a of the first shallow isolation portion 31a) １ The width W in the short side direction across the element forming region 21a ３ The end 41a of the first deep separation portion 41a is wider than the end 41a of the first deep separation portion 41a. １ The bottom 31a of the first shallow isolation portion 31a １The first shallow isolation portion 31a protrudes (is located) closer to the first surface portion S1 of the semiconductor layer 21 (toward the element forming region 21a) than the first shallow isolation portion 31a. １ The bottom of the element forming region 21a is connected to a pair of first shallow isolation parts 31a so as to close the element forming region 21a on the side thereof. That is, in this modification 4-2, the bottom of the element forming region 21a is closed by a pair of first deep isolation parts 41a that define the element forming region 21a.

[0233] On the other hand, as shown in FIG. 35, the first shallow isolation portion 31a of the shallow isolation region 31 according to this modification 4-2 includes a shallow recess 32, an isolation insulating film 33 provided inside the shallow recess 32, and a light reflecting film 35 interposed between the recess 32 and the isolation insulating film 33 and having a higher light reflectivity than the isolation insulating film 33.

[0234] According to this modification 4-2, the same effects as those of the above-described modification 1-2 can be obtained, and also the same effects as those of the above-described fourth embodiment can be obtained.

[0235] <Modification 4-3> FIG. 36 is a diagram showing Modification 4-3 according to the fourth embodiment of the present technology, and is a longitudinal cross-sectional view schematically showing the longitudinal cross-sectional structure at the same position as the longitudinal cross-sectional view of FIG. 32.

[0236] As shown in Figure 36, this variant 4-3 has basically the same configuration as the above-mentioned variant 4-2, and the second shallow isolation portion 31b of the shallow isolation region 31, which overlaps with the second deep isolation region 41b of the deep isolation region 41 in a planar view, also includes a light-reflecting film 35, similar to the first shallow isolation portion 31a.

[0237] That is, in the shallow isolation region 31 of this modified example 4-3, each of the first shallow isolation portion 31a and the second shallow isolation portion 31b includes a shallow recessed portion 32, an isolation insulating film 33 provided inside this shallow recessed portion 32, and a light reflecting film 35 interposed between the recessed portion 32 and the isolation insulating film 33 and having a higher light reflectivity than the isolation insulating film 33.

[0238] According to Modification 4-3, the same effect as that of Modification 4-2 described above can be obtained. Furthermore, in Modification 4-3, similarly to Modification 4-1 described above, between two pixels 3 adjacent to each other via the second deep isolation portion 41b of the deep isolation region 41, it is possible to suppress the incidence of light that passes through the second shallow isolation portion 31b and goes from the photoelectric conversion region 22 of one pixel 3 to the photoelectric conversion region 22 of the other pixel 3, thereby suppressing color mixing between the two pixels 3 adjacent to each other via the second deep isolation portion 41b.

[0239] <Modification 4-4> FIG. 37 is a diagram showing Modification 4-4 according to the fourth embodiment of the present technology, and is a longitudinal cross-sectional view schematically showing the longitudinal cross-sectional structure at the same position as the longitudinal cross-sectional view of FIG. 32.

[0240] 37, this modified example 4-4 has a configuration basically similar to that of the fourth embodiment, but differs in the configuration of the first deep isolation portion 41a included in the deep isolation region 41. That is, as shown in FIG. 37, the first deep isolation portion 41a of this modified example 4-4 has an end 41a on the element formation region 21a side, as in the conventional configuration. １ The bottom surface 31a of the first shallow isolation portion 31a １ The first shallow isolation portions 31a are located closer to the second surface S2 of the semiconductor layer 21 than the first shallow isolation portions 31a, and are spaced apart from the pair of first shallow isolation portions 31a that define the element forming region 21a.

[0241] In this modification 4-4, between two pixels 3 sharing the element formation region 21a (between pixel 3b and pixel 3a on the left side in FIG. 37 ), it is possible to suppress the incidence of light that passes through the first shallow isolation portion 31a from the photoelectric conversion region 22 of one pixel 3 to the photoelectric conversion region 22 of the other pixel 3, thereby suppressing color mixing. Furthermore, since the amount of return light that is generated when long-wavelength light (oblique light) irradiated onto the first shallow isolation portion 31a is reflected by the first shallow isolation portion 31a and returns to the photoelectric conversion region 22 increases, it is also possible to improve the quantum efficiency Qe.

[0242] <Modification 4-5> FIG. 38 is a diagram showing Modification 4-5 according to the fourth embodiment of the present technology, and is a longitudinal cross-sectional view schematically showing the longitudinal cross-sectional structure at the same position as the longitudinal cross-sectional view of FIG. 32.

[0243] As shown in Figure 38, this variant 4-5 has basically the same configuration as the above-mentioned variant 4-4, and the second shallow isolation portion 31b of the shallow isolation region 31, which overlaps with the second deep isolation region 41b of the deep isolation region 41 in a planar view, also includes a light-reflecting film 35, similar to the first shallow isolation portion 31a.

[0244] That is, in the shallow isolation region 31 of this modified example 4-5, each of the first shallow isolation portion 31a and the second shallow isolation portion 31b includes a shallow recessed portion 32, an isolation insulating film 33 provided inside this shallow recessed portion 32, and a light reflecting film 35 interposed between the recessed portion 32 and the isolation insulating film 33 and having a higher light reflectivity than the isolation insulating film 33.

[0245] According to this variant 4-5, the same effect as that of the variant 4-4 described above can be obtained, and similarly to the variant 4-1 described above, between two adjacent pixels 3 via the second deep isolation portion 41b of the deep isolation region 41, it is possible to suppress the incidence of light from the photoelectric conversion region 22 of one pixel 3 to the photoelectric conversion region 22 of the other pixel 3 by passing through the second shallow isolation portion 31b, thereby suppressing color mixing between two adjacent pixels 3 via the second deep isolation portion 41b.

[0246] <Other Modifications> The first and second shallow isolation portions 31a and 31b including the light reflecting film 35 can also be applied to the above-described modification 1-1, modification 1-3 to modification 1-12 of the first embodiment, and each of the second and third embodiments.

[0247] Fifth Embodiment In the fifth embodiment, as shown in FIG. 43, in a longitudinal section across the deep isolation region 81, the width W １A shallow separation region (71a, 71b) that is inclined with respect to the center line Lc passing through the center will be described. FIG. 39 is an equivalent circuit diagram schematically showing a configuration example of a pixel block and a readout circuit in a solid-state imaging device according to the fifth embodiment of the present technology. FIG. 40 is a plan view schematically showing a configuration example of a pixel block included in a pixel array unit in a solid-state imaging device according to the fifth embodiment of the present technology. FIG. 41 is a plan view schematically showing a planar pattern of a deep separation region in FIG. 40. FIG. 42 is a longitudinal sectional view schematically showing a longitudinal sectional structure along the a40 - a40 cut line in FIG. 40. FIG. 43 is a main part enlarged longitudinal sectional view obtained by enlarging a part of FIG. 42. FIG. 44 is a longitudinal sectional view schematically showing a longitudinal sectional structure along the b40 - b40 cut line in FIG. 40. FIG. 45 is a longitudinal sectional view schematically showing a longitudinal sectional structure along the c40 - c40 cut line in FIG. 40. FIG. 46 is a longitudinal sectional view schematically showing a longitudinal sectional structure along the d40 - d40 cut line in FIG. 40.

[0248] <<Overall Configuration of Solid-State Imaging Device>> The solid-state imaging device 1E according to the fifth embodiment of the present technology basically has the same configuration as that of the first embodiment described above, and the following configurations are different. That is, the solid-state imaging device 1E according to the fifth embodiment of the present technology includes a pixel block group 15EE and a readout circuit (pixel circuit) 16E shown in FIG. 39 instead of the pixel block 15A and the readout circuit (pixel circuit) 16A shown in FIG. 3 of the first embodiment described above.

[0249] Further, the solid-state imaging device 1E according to the fifth embodiment of the present technology includes an element formation region 21c, an element formation region 21d, shallow separation regions 71a, 71b, and a deep separation region 81 shown in FIGS. 40 to 42 instead of the element formation region 21a, the element formation region 21b, the shallow separation region 31, and the deep separation region 41 shown in FIGS. 4 and 5 of the first embodiment described above.

[0250] Further, the solid-state imaging device 1E according to the fifth embodiment of the present technology further includes a diffusion separation layer 85 shown in FIG. 42. Other configurations are generally the same as those of the first embodiment described above.

[0251] <Pixel Block Group> As shown in FIGS. 39 to 41, the pixel block group 15EE is made up of pixel blocks 15E arranged adjacent to each other in the Y direction in plan view. １ and 15E ２ as one unit. １ and 15E ２ Each of the pixel blocks 15EE includes, as a unit, four pixels 3 (3a, 3b, 3c, and 3d) arranged in a 2×2 configuration, two adjacent pixels arranged in each of the X and Y directions in a plan view, similar to the pixel block 15A of the first embodiment described above. While one pixel block group 15EE is illustrated in Figures 39 to 41, pixel block groups 15EE are repeatedly arranged in each of the X and Y directions to form the pixel array unit 2A shown in Figure 1.

[0252] As shown in FIG. 39, pixel block 15E １ and 15E ２ Each of the four pixels 3a, 3b, 3c, and 3d included in each of the four pixels 3 (3a, 3b, 3c, and 3d) has common components. Specifically, each of the four pixels 3 (3a, 3b, 3c, and 3d) includes a photoelectric conversion unit 25 that photoelectrically converts light into signal charges, a floating diffusion region FD that serves as a charge storage unit that stores (accumulates) the signal charges photoelectrically converted by the photoelectric conversion unit 25, and a transfer transistor TRL that transfers the signal charges photoelectrically converted by the photoelectric conversion unit 25 to the floating diffusion region FD. Also, each of the four pixels 3 (3a, 3b, 3c, and 3d) includes a power supply contact region WC ２ 42. The photoelectric conversion region 22 of the semiconductor layer 21 shown in FIG. 42 includes a photoelectric conversion unit 25, a floating diffusion region FD, a transfer transistor TRL, and a power supply contact region WC. ２ are provided in the photoelectric conversion region 22 of the semiconductor layer 21.

[0253] The transfer transistor TRL of this fifth embodiment is configured with a planar structure, unlike the transfer transistor TR of the first embodiment having a bigal structure shown in Fig. 5. Each of the four pixels 3 (3a, 3b, 3c, and 3d) of this fifth embodiment includes a photoelectric conversion unit 25, a floating diffusion region FD, a transfer transistor TRL, and a power supply contact region WC. ２ The element layout pattern of the four pixels 3 (3a, 3b, 3c, and 3d) shown in FIG. 4 in the first embodiment is different from the element layout pattern in plan view.

[0254] 39, the input side of the readout circuit 16E is electrically connected to the floating diffusion region FD of the pixel 3. The readout circuit 16E of the fifth embodiment is, but is not limited to, connected to two pixel blocks 15E １ and 15E ２ and two pixel blocks 15E １ , 15E ２ In other words, it is shared by eight pixels 3 ((3a, 3b, 3c, 3d)×2)) included in one pixel block group 15EE.

[0255] Similar to the readout circuit 16A of the first embodiment described above, the readout circuit 16E reads out the signal charges held in the floating diffusion region FD of the pixel 3 and outputs a pixel signal based on the readout signal charges. In other words, each readout circuit 16E converts the signal charges photoelectrically converted by the photoelectric conversion unit 25 (photodiode PD) into a pixel signal based on this signal charge and outputs the pixel signal.

[0256] The readout circuit 16E has, but is not limited to, a configuration similar to that of the readout circuit 16B of the second embodiment shown in Fig. 26. That is, as shown in Fig. 39, the readout circuit 16E has, as pixel transistors Q, an amplification transistor AMP, a selection transistor SEL, a reset transistor RST, and a switching transistor FDG.

[0257] <Pixel Block Inversion Pattern> As shown in FIG. 40, two pixel blocks 15E included in a pixel block group 15EE １ , 15E２ are arranged adjacent to each other in the Y direction in a plan view. １ and 15E ２ Each element arrangement pattern is １ and the other pixel block 15E ２ It is an inversion pattern with the boundary between them as the inversion axis.

[0258] <<Specific Configuration of Solid-State Imaging Device>> Next, a specific configuration of the solid-state imaging device 1E according to the fifth embodiment will be described with reference to FIGS. 40 to 46. FIG.

[0259] As shown in Figures 40 to 46, the solid-state imaging device 1E of this fifth embodiment comprises a semiconductor layer 21 having a first surface portion S1 and a second surface portion S2 located opposite each other in one direction, and a photoelectric conversion region 22 partitioned by a deep isolation region 81 extending from the second surface portion S2 side of the semiconductor layer 21 toward the first surface portion S1 side, and in which a photoelectric conversion section 25 is provided.

[0260] In addition, the solid-state imaging device 1E according to the fifth embodiment further includes an element formation region 21c that is partitioned by a pair of shallow isolation regions 71a and 71b on the first surface portion S1 side of the semiconductor layer 21, overlaps with the deep isolation region 81 in a planar view, and has a pixel transistor Q provided therein.

[0261] In addition, the solid-state imaging device 1E according to the fifth embodiment further includes an element formation region 21d in which a transfer transistor TRL is provided, and a diffusion isolation layer 85 provided on the first surface portion S1 side of the semiconductor layer 21 so as to overlap the deep isolation region 81 in a planar view.

[0262] Furthermore, although not shown, the solid-state imaging device 1E of this fifth embodiment, as with the solid-state imaging device 1A of the first embodiment described above, further includes a multilayer wiring layer 61 provided on the first surface S1 side of the semiconductor layer 21, and a flattening film 71, an optical filter 73, and a lens layer 74 provided in sequence from the second surface S2 side of the semiconductor layer 21, although this is described with reference to Figure 5 of the first embodiment described above.

[0263] <Semiconductor Layer> As shown in Figures 42 and 44, the semiconductor layer 21 includes a deep isolation region 81 extending in the thickness direction (Z direction) of the semiconductor layer 21 and a photoelectric conversion region 22 defined by the deep isolation region 81. The semiconductor layer 21 further includes a pair of shallow isolation regions 71a and 71b provided in a surface layer portion of the first surface portion S1 of the semiconductor layer 21 and element formation regions 21c and 21d defined by the pair of shallow isolation regions 71a and 71b. As shown in Figures 42 and 44, the photoelectric conversion region 22 is provided for each pixel 3. The semiconductor layer 21 may be formed of a Si substrate, a SiGe substrate, an InGaAs substrate, or the like. In the fifth embodiment, although not limited thereto, an n-type semiconductor substrate made of single crystal silicon, for example, is used as the semiconductor layer 21.

[0264] <Deep Isolation Region> As shown in FIG. 41 , the deep isolation region 81 has a grid-like planar pattern in plan view, similar to the deep isolation region 41 shown in FIG. 9A of the first embodiment described above. That is, although not shown in detail, the deep isolation region 81 includes stripe-shaped first planar extensions extending in the X direction in plan view and repeatedly arranged at predetermined intervals in the Y direction, and stripe-shaped second planar extensions extending in the Y direction in plan view and repeatedly arranged at predetermined intervals in the X direction. The deep isolation region 81 also includes intersections 81XY (intersections) where the first planar extensions and the second planar extensions intersect within the same plane. In this fifth embodiment, for example, the first planar extensions and the second planar extensions are orthogonal to each other. That is, as shown in FIG. 41 , the photoelectric conversion region 22 partitioned by the deep isolation region 81 has a rectangular planar shape in plan view.

[0265] 41, the deep isolation region 81 corresponding to one photoelectric conversion region 22 (one pixel 3) has a rectangular annular planar pattern (ring-shaped planar pattern) in a plan view, and surrounds one photoelectric conversion region 22. On the other hand, as shown in FIG. １ , 15E ２The deep isolation region 81 corresponding to the above has a composite planar pattern having a cross-shaped planar pattern in which a first planar extension portion and a second planar extension portion are arranged orthogonal to each other within a square annular planar pattern.

[0266] As shown in FIG. 41, one pixel block 15E １ , 15E ２ The deep isolation region 81 corresponding to the four pixels 3 is located at the intersection (intersection) 81XY of the first planar extension and the second planar extension in the pixel block 15E. １ , 15E ２ The photoelectric conversion regions 22 of the four pixels 3 (3a, 3b, 3c, 3d) are arranged in a matrix (2x2) so as to surround the intersection 81XY. １ , 15E ２ The photoelectric conversion regions 22 of the four pixels 3 (3a, 3b, 3c, 3d) included in the pixel 3 are adjacent to each other in the X and Y directions in plan view with deep isolation regions 81 interposed therebetween.

[0267] 42 to 44 , the deep isolation region 81 extends from the second surface S2 side of the semiconductor layer 21 toward the first surface S1 side and terminates at a distance (separate) from the first surface S1. The deep isolation region 81 includes, but is not limited to, for example, a deep recessed portion 82 provided on the first surface S1 side of the semiconductor layer 21 and an isolation insulating film 83 provided inside (inside) the deep recessed portion 82 so as to fill the deep recessed portion 82. The deep recessed portion 82 can be formed, for example, by selectively etching the second surface S2 of the semiconductor layer 21 using photolithography and dry etching techniques. The isolation insulating film 83 can be formed by depositing, for example, a silicon oxide film by the ALD method on the second surface S2 side of the semiconductor layer 21 so as to fill the inside of the deep recess 82, and then selectively removing the silicon oxide film on the second surface S2 side of the semiconductor layer 21 by an etch-back method or a CMP method so that the silicon oxide film inside the deep recess 82 remains.

[0268] The deep isolation region 81 defines the photoelectric conversion regions 22 and electrically and optically separates the adjacent photoelectric conversion regions 22 in plan view. That is, the deep isolation region 81 is configured as a trench type that defines and separates the photoelectric conversion regions 22 by forming deep recesses 82 that extend from the second surface S2 side of the semiconductor layer 21 toward the first surface S1 side.

[0269] Unlike the deep isolation region 41 shown in FIG. 5 of the first embodiment described above, the deep isolation region 81 has the same distance from the first surface S1 of the semiconductor layer 21 as the design value, as shown in FIGS. 42 to 44, and there is no difference in height at the end 81z (see FIG. 42) located on the first surface S1 side of the semiconductor layer 21.

[0270] As shown in FIGS. 42 to 44, the deep isolation region 81 has a first region 81a that overlaps the element formation region 21c in plan view, and a second region 81b that excludes the first region 81a.

[0271] 42 and 44 , the diffusion isolation layer 85 is provided on the first surface S1 side of the semiconductor layer 21 in a plan view, overlapping the deep isolation region 81. The diffusion isolation layer 85 is provided to selectively overlap the second region 81b of the deep isolation region 81, excluding the first region 81a that overlaps the element formation region 21c, and defines the photoelectric conversion region 22 together with the deep isolation region 81. The diffusion isolation layer 85 is composed of a p-type semiconductor region having a higher impurity concentration than the p-type well region 23 described below. The diffusion isolation layer 85 basically extends from the first surface S1 of the semiconductor layer 21 to the deep isolation region 81, but as shown in FIG. 44 , a portion of the diffusion isolation layer 85 is spaced apart from the first surface S1 of the semiconductor layer 21.

[0272] <Separation within pixel block> As shown in FIGS. 40 and 41, pixel block 15E １ and 15E ２Each of the semiconductor layers 21 includes four pixels 3 (3 a, 3 b, 3 c, and 3 d). Of these, in two pixels 3 a and 3 b that are adjacent to each other in the X direction, the photoelectric conversion region 22 of one pixel 3 a and the photoelectric conversion region 22 of the other pixel 3 b are electrically and optically separated by a deep isolation region 81 and a diffusion isolation layer 85 that are provided between the photoelectric conversion regions 22 and are aligned in the thickness direction (Z direction) of the semiconductor layer 21, as shown in FIG.

[0273] Although not shown in detail, the pixel block 15E １ and 15E ２ Of the four pixels 3 (3a, 3b, 3c, 3d) included in each of the semiconductor layers 21, the two pixels 3c and 3d that are arranged adjacent to each other in the X direction are electrically and optically separated from the photoelectric conversion region 22 of one pixel 3c by a deep isolation region 81 and a diffusion isolation layer 85 that are arranged in the thickness direction (Z direction) of the semiconductor layer 21, similar to the two pixels 3a and 3b that are arranged in the X direction.

[0274] Also, pixel block 15E １ and 15E ２ Of the four pixels 3 (3a, 3b, 3c, 3d) included in each of the semiconductor layers 21, two pixels 3a and 3c are arranged adjacent to each other in the Y direction. As shown in FIG. 44, the photoelectric conversion region 22 of one pixel 3a and the photoelectric conversion region 22 of the other pixel 3c are electrically and optically separated by a deep isolation region 81 and a diffusion isolation layer 85 which are provided between the respective photoelectric conversion regions 22 and are arranged in the thickness direction (Z direction) of the semiconductor layer 21.

[0275] Although not shown in detail, the pixel block 15E １ and 15E ２Among the four pixels 3 (3a, 3b, 3c, 3d) included in each of the pixel blocks 15E, two pixels 3b and 3d are arranged adjacent to each other in the Y direction, and similarly to the two pixels 3a and 3c arranged in the Y direction, the photoelectric conversion region 22 of one pixel 3b and the photoelectric conversion region 22 of the other pixel 3d are electrically and optically separated by a deep isolation region 81 and a diffusion isolation layer 85 which are provided between the photoelectric conversion regions 22 and are arranged in the thickness direction (Z direction) of the semiconductor layer 21. That is, one pixel block (15E １ , 15E ２ The photoelectric conversion regions 22 of two adjacent pixels 3 arranged in the pixel block (15E) are electrically and optically isolated by the deep isolation region 81 and the diffusion layer 85. １， 15E ２ ) the diffusion isolation layer 85 provided between the photoelectric conversion regions 22 of each of the two pixels 3 reaches the deep isolation region 81 from the first surface portion S1 of the semiconductor layer 21, as shown in Figures 42 and 44.

[0276] <Separation of pixel blocks arranged in the Y direction within a pixel block group> As shown in FIGS. 40 and 41, a pixel block 15E included in one pixel block group 15EE １ and pixel block 15E ２ are arranged adjacent to each other in the Y direction. １ and 15E ２ In this case, as shown in FIG. １ The other pixel block 15E ２ The photoelectric conversion region 22 of the pixel 3 (3c) located on the side and the other pixel block 15E ２ One pixel block 15E １ The photoelectric conversion region 22 of the pixel 3 (3c) located on the side is electrically and optically separated from the photoelectric conversion region 22 of the pixel 3 (3c) located on the side by a deep isolation region 81 and a diffusion isolation layer 85 that are provided between each photoelectric conversion region 22 and are aligned in the thickness direction (Z direction) of the semiconductor layer 21.

[0277] That is, the pixel block 15E included in one pixel block group 15EE １ and pixel block 15E ２The photoelectric conversion regions 22 of the two adjacent pixels 3 arranged between the pixel block 15E and the pixel block 15E are electrically and optically isolated by the deep isolation region 81 and the diffusion layer 85. １ and 15E ２ The diffusion isolation layer 85 provided between the first surface S1 of the semiconductor layer 21 also reaches the deep isolation region 81 from the first surface S1 of the semiconductor layer 21.

[0278] 40 and 41 are repeatedly arranged adjacent to each other in the Y direction. In these two pixel block groups 15EE and 15EE arranged adjacent to each other in the Y direction, as shown in Fig. 44, the photoelectric conversion region 22 of the pixel 3 (3 a) located in one pixel block group 15EE on the side of the other pixel block group 15EE and the photoelectric conversion region 22 of the pixel 3 (3 a) located in the other pixel block group 15EE on the side of the one pixel block group 15EE are electrically and optically separated by deep isolation regions 81 and diffusion isolation layers 85 that are provided between the photoelectric conversion regions 22 and are arranged in the thickness direction (Z direction) of the semiconductor layer 21.

[0279] That is, the photoelectric conversion regions 22 of each of the two pixels 3 arranged adjacent to each other in the Y direction between the two pixel block groups 15EE and 15EE arranged adjacent to each other in the Y direction are electrically and optically separated by the deep isolation region 81 and the diffusion layer 85.

[0280] As shown in FIG. 44 , the diffusion isolation layer 85 provided between the two pixel block groups 15EE and 15EE aligned in the Y direction is spaced apart from the first surface S1 of the semiconductor layer 21 and reaches the deep isolation region 81. An n-type semiconductor region 55 functioning as the source and drain regions of the pixel transistor Q is provided between the diffusion isolation layer 85 and the first surface S1 of the semiconductor layer 21. In the fifth embodiment, as shown in FIG. 40 , a pixel transistor Q is provided between two pixel block groups 15EE and 15EE aligned adjacent to each other in the Y direction. The pixel transistor Q is disposed between the two pixel block groups 15EE and 15EE with the pair of n-type semiconductor regions 55 functioning as the source and drain regions aligned in the Y direction. For example, an amplification transistor AMP is provided as the pixel transistor Q.

[0281] 40 and 41 are repeatedly arranged adjacent to each other in the X direction. In these two pixel block groups 15EE and 15EE arranged adjacent to each other in the X direction, as shown in Fig. 42, the photoelectric conversion region 22 of a pixel 3a located in one pixel block group 15EE on the side of the other pixel block group 15EE and the photoelectric conversion region 22 of a pixel 3b located in the other pixel block group 15EE on the side of the one pixel block group 15EE are electrically and optically separated by a deep isolation region 81 and a pair of shallow isolation regions 71a, 71b that are provided between the photoelectric conversion regions 22 and are arranged in the thickness direction (Z direction) of the semiconductor layer 21.

[0282] 42, the photoelectric conversion region 22 of the fifth embodiment, like the photoelectric conversion region 22 of the first embodiment, further includes a p-type well region 23 provided in the semiconductor layer 21, an n-type semiconductor region 24 provided in the p-type well region 23, a photoelectric conversion unit 25 (PD) including the p-type well region 23 and the n-type semiconductor region 24, an element formation region 21d provided on the first surface portion S1 side of the semiconductor layer 21, and a transfer transistor TRL provided in the element formation region 21d. Also, as shown in FIG. 40, the photoelectric conversion region 22 of the fifth embodiment, like the photoelectric conversion region 22 of the first embodiment, further includes a floating diffusion region FD and a power supply contact region WC. ２ 42 and 43, the photoelectric conversion region 22 of the fifth embodiment further includes element formation regions 21c and 21d.

[0283] <Floating Diffusion Region> As shown in FIG. 42, the floating diffusion region FD of the fifth embodiment is different from the floating diffusion region FD of the first embodiment described above, and is formed in a pixel block 15E in plan view. １ and 15E ２ are arranged at the center (intersection 81XY) of each pixel block 15E １ , 15E ２ Although not shown, this floating diffusion region FD is provided in the p-type well region 23 in the surface layer portion on the first surface S1 side of the semiconductor layer 21, which is an element formation region 21d, similar to the floating diffusion region FD of the first embodiment.

[0284] <Transfer Transistor> As shown in Figures 42 and 43, the transfer transistor TRL is provided on the first surface S1 side of the semiconductor layer 21 in the element formation region 21d. The transfer transistor TRL has a gate electrode 53 provided on the first surface S1 side of the semiconductor layer 21, and a gate insulating film 52 provided between the gate electrode 53 and the semiconductor layer 21. The transfer transistor TRL also has an n-type semiconductor region 24 and an n-type floating diffusion region FD functioning as a source region and a drain region, and a p-type well region 23 functioning as a channel formation region. This transfer transistor TRL is, for example, configured as a planar type in which the gate electrode 53 is provided only outside the first surface of the semiconductor layer 21, although this is not limited thereto. As shown in Figure 40, one pixel block 15E １ , 15E ２ The transfer transistors RTL of the four pixels 3 (3a, 3b, 3c, and 3d) included in the pixel block 15E are located on the crossing portion 81XY side of the deep isolation region 81 in plan view (the pixel block 15E １ , 15E ２ The gate electrodes 53 of the transfer transistors TRL of the four pixels 3 (3 a, 3 b, 3 c, and 3 d) are provided outside the n-type floating diffusion regions FD so as to surround the floating diffusion regions FD arranged at the intersections 81XY of the deep isolation regions 81 in plan view.

[0285] <P-type power supply contact region> As shown in FIG. 40, the power supply contact region WC ２ are two pixel blocks 15E included in one pixel block group 15EE. １ and 15E ２ and one pixel block 15E １ and the other pixel block 15E. ２ The power supply contact region WC is shared by two pixels 3c and 3d included in the power supply contact region WC. ２ is provided across four pixels 3 (3c, 3d, 3c, 3d). ２45, the power supply contact region WC is provided in the p-type well region 23 in the surface layer portion on the first surface portion S1 side of the semiconductor layer 21, which is the element forming region 21d. ２ is made up of a p-type semiconductor region having a higher impurity concentration than the p-type well region 23 and is electrically connected to the p-type well region 23 .

[0286] p-type power supply contact region WC ２ During operation, a first reference potential (Vss potential) of, for example, 0 V is applied to this terminal as a reference potential within the solid-state imaging device 1E (within the semiconductor chip 2), and the potential is fixed to this first reference potential during operation.

[0287] 40 to 42, the element formation region 21c is provided on the first surface S1 side of the semiconductor layer 21, and is partitioned on both sides in the X direction by a pair of shallow isolation regions 71a and 71b that are spaced apart from each other in the X direction on the first surface S1 side of the semiconductor layer 21. Then, as shown in FIGS. １ and 15E ２ The pixel block 15EE extends across the Y direction and across a plurality of pixel block groups 15EE aligned in the Y direction.

[0288] As shown in FIGS. 40 to 42, the element formation region 21c is formed by two pixel blocks 15E arranged adjacent to each other in the X direction. １ and 15E １ (15E ２ and 15E ２ ), one pixel block 15E １ (15E ２ ) the other pixel block 15E １ (15E ２ ) side, and the other pixel block 15E １ (15E ２ ) one pixel block 15E １ (15E ２ ) side, and is shared by these two pixels 3.

[0289] 42 and 44 , one shallow isolation region 71a of the pair of shallow isolation regions 71a and 71b is provided on the photoelectric conversion region 22 side of one of the two pixels 3 that share the element formation region 21c. The other shallow isolation region 71b of the pair of shallow isolation regions 71a and 71b is provided on the photoelectric conversion region 22 side of the other pixel 3 of the two pixels 3 that share the element formation region 21c. The pair of shallow isolation regions 71a and 71b are arranged on both the left and right sides of the element formation region 21c in the X direction in a plan view, and extend in the Y direction.

[0290] 40 , 42 , 43 , and 45 , a p-type well region 23 and pixel transistors Q are provided in the element formation region 21 c. In the fifth embodiment, for example, a selection transistor SEL, a reset transistor RST, and a switching transistor FDG are provided as the pixel transistors Q. These pixel transistors Q have a gate electrode 54 provided on the element formation region 21 c, a gate insulating film 52 provided between the gate electrode 53 and the element formation region 21 c, a pair of semiconductor regions 55 provided in the p-type well region 23 and functioning as a source region and a drain region, and the p-type well region 23 functioning as a channel formation region.

[0291] As shown in FIGS. 40 and 45, the element forming region 21c also has a p-type power supply contact region WC ３ The p-type power supply contact region WC is provided. ３ is provided in the p-type well region 23 in the element formation region 21c and is electrically connected to the p-type well region 23. ３ is the above-mentioned power supply contact area WC ２ Similarly to the p-type well region 23, the p-type power supply contact region WC is made of a p-type semiconductor region having a higher impurity concentration than the p-type well region 23. ３ During operation, a first reference potential (Vss potential) of, for example, 0 V is also applied to the first reference potential (Vss potential).

[0292] 40 to 42, the element formation region 21d is provided on the first surface S1 side of the semiconductor layer 21, and is defined on both sides in the X direction by the shallow isolation region 71a (or 71b) and the diffusion isolation layer 85 that are spaced apart from each other and lined up in the X direction on the first surface S1 side of the semiconductor layer 21. Also, as shown in FIGS. 40 and 44, the element formation region 21d is provided on the first surface S1 side of the semiconductor layer 21, and is defined on both sides in the Y direction by the diffusion isolation regions 85 and 85 that are spaced apart from each other and lined up in the Y direction on the first surface S1 side of the semiconductor layer 21. That is, the element formation region 21d in this fifth embodiment is provided for each pixel 3 (photoelectric conversion region 22).

[0293] 43, the pair of shallow isolation regions 71a, 71b are inclined with respect to the first surface S1 of the semiconductor layer 21 in a vertical cross section across the deep isolation region 81. Specifically, in a vertical cross section across the deep isolation region 81, the pair of shallow isolation regions 71a, 71b are inclined with respect to the first surface S1 of the semiconductor layer 21 in a vertical cross section across the deep isolation region 81. １ The shallow isolation region 71a is inclined to one side of the center line Lc (the right side in FIG. 43 ) with respect to the center line Lc passing through the center of the semiconductor layer 21 and extends from the first surface S1 side of the semiconductor layer 21 toward the deep isolation region 81, while the other shallow isolation region 71b is inclined to the other side of the center line Lc (the left side in FIG. 43 ) with respect to the center line Lc and extends from the first surface S1 side of the semiconductor layer 21 toward the deep isolation region 81. At least one of the shallow isolation region 71a and the other shallow isolation region 71b of the pair of shallow isolation regions 71a, 71b is connected to the deep isolation region 81. In this fifth embodiment, both of the pair of shallow isolation regions 71a, 71b are connected to the deep isolation region 81. In this fifth embodiment, the deep isolation region 81 sides of the pair of shallow isolation regions 71a, 71b are connected to each other.

[0294] That is, in a longitudinal cross section across the deep isolation region 81, the element formation region 21c is divided into a shallow isolation region 71a that extends from the first surface portion S1 side of the semiconductor layer 21 toward the deep isolation region 81 and is connected to the deep isolation region 81, while being inclined to one side of the center line Lc of the deep isolation region 81 (the right side in Figure 43) with respect to the center line Lc of the deep isolation region 81, and a shallow isolation region 71b that extends from the first surface portion S1 side of the semiconductor layer 21 toward the deep isolation region 81 and is connected to the deep isolation region 81, while being inclined to the other side of the center line Lc of the deep isolation region 81 (the left side in Figure 43).

[0295] 43 , one shallow isolation region 71a, in a cross section across the deep isolation region 81, includes a shallowly dug portion 72a that is inclined to one side of the center line Lc of the deep isolation region 81 (to the right in FIG. 43 ) with respect to the center line Lc, and extends from the first face S1 side of the semiconductor layer 21 toward the deep isolation region 81, and an isolation insulating film 73a provided inside the shallowly dug portion 72a to embed the shallowly dug portion 72a. The other shallow isolation region 71b, in a cross section across the deep isolation region 81, includes a shallowly dug portion 72b that is inclined to the other side of the center line Lc of the deep isolation region 81 (to the left in FIG. 43 ) with respect to the center line Lc, and extends from the first face S1 side of the semiconductor layer 21 toward the deep isolation region 81, and an isolation insulating film 73b provided inside the shallowly dug portion 72b to embed the shallowly dug portion 72b. That is, the shallow isolation regions 71a, 71b are provided on the first surface S1 of the semiconductor layer 21 and are configured as trenches including recessed portions 72a, 72b extending obliquely from the first surface S1 of the semiconductor layer 21 to the first surface S1.

[0296] Such a pair of shallow isolation regions 71 a, 71 b can be easily formed, for example, by selectively etching the first surface S1 side of the semiconductor layer 21 while tilting the semiconductor layer 21 with respect to the vertical direction to form shallow recessed portions 72 a, 72 b. Alternatively, for example, the recessed portion 72 a and the isolation insulating film 73 a of one of the pair of shallow isolation regions 71 a, 71 b may be formed first, and then the recessed portion 72 b and the isolation insulating film 73 b of the other shallow isolation region 71 b may be formed, thereby forming the pair of shallow isolation regions 71 a, 71 b without separating the element formation region 21 c from the semiconductor layer 21.

[0297] In other words, the configuration of the pair of shallow isolation regions 71a, 71b is such that, in a vertical cross section across the deep isolation region 81, one shallow isolation region 71a is inclined at an acute angle with the center line Ld to one side (the right side in FIG. 40 ) of the center line Lc of the deep isolation region 81, and extends from the first surface S1 side of the semiconductor layer 21 toward the deep isolation region 81. The other shallow isolation region 71b is inclined at an acute angle with the center line Ld to the other side (the left side in FIG. 40 ) of the center line Lc of the deep isolation region 81, and extends from the first surface S1 side of the semiconductor layer 21 toward the deep isolation region 81. In yet another way, the configuration of the pair of shallow isolation regions 71a, 71b is such that, in a cross section across the deep isolation region 81, one shallow isolation region 71a is inclined clockwise (to the right in FIG. 40 ) from the center line Lc of the deep isolation region 81 and extends from the first surface S1 side of the semiconductor layer 21 toward the deep isolation region 81. The other shallow isolation region 71b is inclined counterclockwise (to the left in FIG. 40 ) from the center line Lc of the deep isolation region 81 and extends from the first surface S1 side of the semiconductor layer 21 toward the deep isolation region 81.

[0298] <<Main Effects of Fifth Embodiment>> As described above, the solid-state imaging device 1E according to the fifth embodiment includes a pair of shallow isolation regions 71a and 71b that partition the element formation region 21c. In a vertical cross section (vertical cross section in FIG. 43) that crosses the deep isolation region 81, the shallow isolation region 71a has a width W of the deep isolation region 81. １ 43 ) with respect to a center line Lc passing through the center of the semiconductor layer 21, and extends from the first surface portion S1 side of the semiconductor layer 21 toward the deep isolation region 81, while the other shallow isolation region 71b is inclined to the other side of the center line Lc (the left side in FIG. 43 ) with respect to the center line Lc and extends from the first surface portion S1 side of the semiconductor layer 21 toward the deep isolation region 81. Both of the pair of shallow isolation regions 71a, 71b are connected to the deep isolation region 81. Therefore, between two pixels 3 (pixels 3a and 3b in FIG. 43 ) that share the element formation region 21c partitioned by the pair of shallow isolation regions 71a, 71b, there basically is no path route R2 as shown in FIG. 10B referred to in the first embodiment described above. Therefore, according to the solid-state imaging device 1E of this fifth embodiment, compared to the first embodiment described above, it is possible to further suppress signal charge leakage, in which signal charge leaks from one photoelectric conversion region 22 to the other photoelectric conversion region 22 between two pixels 3 that are arranged adjacent to each other in the Y direction and share an element formation region 21c.

[0299] Furthermore, in the fifth embodiment, each of the pair of shallow isolation regions 71 a, 71 b is connected to the deep isolation region 81, so that the photoelectric conversion region 22 of each of the two pixels 3 that share the element formation region 21 c can be electrically and optically isolated from the element formation region 21 c. That is, the element formation region 21 c can be set in a floating state with respect to each of the two photoelectric conversion regions 22 and 22.

[0300] Furthermore, since the width of the lower side (deep isolation region 81 side) of the element formation region 21c can be narrowed relative to the width of the upper side (first surface S1 side of the semiconductor layer 21) of the element formation region 21c, it is possible to ensure the channel width (gate width) of the pixel transistor Q provided in the element formation region 21c while suppressing the reduction in volume of the photoelectric conversion region 22 caused by providing a pair of shallow isolation regions 71a, 71b.

[0301] In the above-described fifth embodiment, a configuration has been described in which each of the pair of shallow isolation regions 71a, 71b is connected to the deep isolation region 81, but it is not necessary that both of the pair of shallow isolation regions 71a, 71b are connected to the deep isolation region 81, and it is sufficient that at least one of the pair of shallow isolation regions 71a, 71b is connected to the deep isolation region 81. In addition, in the above-described fifth embodiment, a pair of shallow isolation regions 71a, 71b has been described, but the shallow isolation regions do not necessarily have to be a pair, and it may be either the shallow isolation regions 71a or 71b.

[0302] Sixth Embodiment In this sixth embodiment, a three-dimensional structure will be described. Fig. 47 is a plan view schematically showing a configuration example of a pixel block group included in a pixel array unit in a solid-state imaging device according to a sixth embodiment of the present technology. Fig. 48 is a longitudinal sectional view schematically showing a longitudinal sectional structure taken along the a47-a47 cutting line in Fig. 47. Fig. 49 is a longitudinal sectional view schematically showing a longitudinal sectional structure taken along the b47-b47 cutting line in Fig. 47. Note that in Fig. 47, layers above the pixel transistor Q and the transfer transistor TRL are omitted from the illustration in order to make the drawing easier to understand.

[0303] As shown in Figures 47 to 49 , a solid-state imaging device 1F according to the sixth embodiment of the present technology has a configuration basically similar to that of the solid-state imaging device 1E according to the fifth embodiment, but differs in the following configuration. That is, as shown in Figures 48 and 49 , the solid-state imaging device 1F according to the sixth embodiment further includes a semiconductor layer 92 and an insulating layer 93 provided on the first surface S1 side of the semiconductor layer 21, with an insulating layer 91 interposed therebetween. The semiconductor layer 92 includes a pixel transistor Q included in the pixel circuit 15E (see Figure 39 ). A plurality of semiconductor layers 92 are provided in the same plane, and each semiconductor layer 92 is island-shaped. The insulating layer 9 is provided between the semiconductor layers 92 so as to surround the periphery of the semiconductor layer 92. That is, the solid-state imaging device 1F according to the sixth embodiment has a three-dimensional structure in which the semiconductor layers 21 and 92 are stacked in the thickness direction (Z direction) of each semiconductor layer 21 and 92 with an insulating layer 93 interposed therebetween.

[0304] Furthermore, in the solid-state imaging device 1F according to the sixth embodiment, the element arrangement pattern of the pixel block group 15EE shown in Fig. 47 is different from the element arrangement pattern of the pixel block group 15EE of the fifth embodiment shown in Fig. 40. Specifically, compared to the number of pixel transistors Q provided in the element formation region 21c of the fifth embodiment shown in Fig. 40, in the sixth embodiment, the number of pixel transistors Q provided in the element formation region 21c is smaller, as shown in Fig. 47.

[0305] 40 of the fifth embodiment, the pixel transistor Q is provided in the element formation region 21d, but in this sixth embodiment, as shown in FIG. 47, the pixel transistor Q is omitted. In this sixth embodiment, a p-type power supply contact region WC is provided between two pixel block groups 15EE and 15EE arranged adjacent to each other in the Y direction instead of the pixel transistor Q. ４ is provided.

[0306] This p-type power supply contact region WC ４47 and 49, is disposed between two pixel block groups 15EE and 15EE arranged adjacent to each other in the Y direction, and is shared by two pixels 3a and 3b on the 15EE side of one pixel block group and two pixels 3a and 3b on the 15EE side of the other pixel block group. ４ Although not shown, the power supply contact area WC ２ Similarly, the p-type power supply contact region WC is provided in the p-type well region 23 in the element formation region 21d, in the surface layer portion on the first surface portion S1 side of the semiconductor layer 21. ４ is made up of a p-type semiconductor region having a higher impurity concentration than the p-type well region 23 and is electrically connected to the p-type well region 23 .

[0307] The present technology can also be applied to the solid-state imaging device 1F having a three-dimensional structure according to the sixth embodiment, and the same effects as those of the solid-state imaging device 1E according to the fifth embodiment can be obtained.

[0308] It is preferable that the switching transistor FDG as the pixel transistor Q is provided on the semiconductor layer 21 side where the photoelectric conversion region 22 is provided.

[0309] Seventh Embodiment In this seventh embodiment, an oblique arrangement of pixel block groups will be described. FIG. 50 is a plan view schematically illustrating a configuration example of a pixel block group included in a pixel array section in a solid-state imaging device according to a seventh embodiment of the present technology. As illustrated in FIG. 50, in a solid-state imaging device 1G according to the seventh embodiment of the present technology, pixel block groups 15EE are repeatedly arranged in a +XY direction inclined at, for example, 45° with respect to the X and Y directions in a two-dimensional plane, and in a −YX direction orthogonal to the +XY direction. Each of a pair of shallow isolation regions 71a and 71b extends in the +XY direction. That is, pixels 3 included in the pixel block group 15EE are repeatedly arranged in the +XY direction and the −YX direction, thereby forming the pixel array section 2A shown in FIG. 1 . The other configurations are generally similar to those of the fifth embodiment.

[0310] The present technology can also be applied to the solid-state imaging device 1G according to the seventh embodiment, and the same effects as those of the solid-state imaging device 1E according to the fifth embodiment can be obtained.

[0311] Eighth Embodiment In this eighth embodiment, a configuration will be described in which a shallow isolation region having an oblique trench structure extending in the Y direction, a shallow isolation region having an oblique trench structure extending in the X direction, and a shallow isolation region having a vertical trench structure are mixed. Fig. 51 is a plan view schematically showing an example configuration of a pixel block group included in a pixel array section in a solid-state imaging device according to an eighth embodiment of the present technology. Fig. 52 is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the a51-a51 cutting line in Fig. 51. Fig. 53 is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the b51-b51 cutting line in Fig. 51.

[0312] As shown in Figures 51 to 53, the solid-state imaging device 1H of the eighth embodiment of the present technology is basically configured in the same manner as the solid-state imaging device 1E of the fifth embodiment described above, with the following differences in configuration.

[0313] That is, as shown in FIG. 44, in the fifth embodiment described above, two pixel blocks 15E arranged adjacent to each other in the Y direction in one pixel block group 15EE are １ and 15E ２ In contrast, as shown in FIGS. 51 and 53, in the eighth embodiment, two pixel blocks 15E arranged adjacent to each other in the Y direction in one pixel block group 15EE are provided with a diffusion separation layer 85 therebetween. １ and 15E ２ 44. A shallow isolation region 75 is provided between the first and second electrodes 71 and 72 instead of the diffusion isolation layer 85 shown in FIG.

[0314] 52 , the shallow isolation region 75 extends perpendicular to the first surface S1 of the semiconductor layer 21, as shown in FIG. 53 . The shallow isolation region 75 is not limited to this, but includes, for example, a deep dug portion 75a provided on the first surface S1 side of the semiconductor layer 21 and extending perpendicular to the first surface S1 of the semiconductor layer 21, and an isolation insulating film 75b provided inside (inside) the deep dug portion 75a so as to fill the deep dug portion 75a. That is, the shallow isolation region 75 is configured as a vertical trench type provided on the first surface S1 side of the semiconductor layer 21 and including the deep dug portion 75a extending perpendicularly from the first surface S1 of the semiconductor layer 21 to the first surface S1. Similarly to the diffusion isolation layer 85, the shallow isolation region 75 overlaps with the deep isolation region 81 in plan view, and reaches the deep isolation region 81 from the first surface portion S1 of the semiconductor layer 21. Here, in the eighth embodiment, the shallow isolation regions 71a and 71b correspond to a specific example of a "first shallow isolation region" of the present technology, and the shallow isolation region 75 corresponds to a specific example of a "second shallow isolation region" of the present technology.

[0315] In addition, as shown in FIG. 40, in the fifth embodiment, two pixel blocks 15E included in one pixel block group 15EE １ and 15E ２ A power supply contact area WC is formed between the ３ are arranged, and one pixel block 15E １ and the other pixel block 15E. ２ and the two pixels 3c and 3d included in the power supply contact region WC ３ In contrast, as shown in FIG. 51, in the eighth embodiment, two pixel blocks 15E included in one pixel block group 15EE share １ and 15E ２ The pixel block 15E of the shallow isolation region 75 between １ side and pixel block 15E ２ Power supply contact areas WC on each side ５ are provided adjacent to the shallow isolation region 75. １ side power supply contact area WC ５is pixel block 15E １ Among the four pixels 3 (3a, 3b, 3c, 3d) in the pixel block 15E, the pixel block 15E is shared by two pixels 3c and 3d located on the shallow isolation region 75 side. ２ side power supply contact area WC ５ is pixel block 15E ２ Of the four pixels 3 (3a, 3b, 3c, 3d), the pixel 3c is shared by two pixels 3c and 3d located on the shallow isolation region 75 side.

[0316] This power supply contact area WC ５ Although not shown, the power supply contact area WC ２ Similarly, the power supply contact region WC is provided in the p-type well region 23 in the element forming region 21d, in the surface layer portion on the first surface portion S1 side of the semiconductor layer 21. ５ is made up of a p-type semiconductor region having a higher impurity concentration than the p-type well region 23 and is electrically connected to the p-type well region 23 .

[0317] 44, in the fifth embodiment, a diffusion isolation layer 85 is provided between two pixel block groups 15EE and 15EE that are adjacent to each other in the Y direction. In contrast, in the eighth embodiment, as shown in FIGS. 51 and 53, a pair of shallow isolation regions 71a are provided between two pixel block groups 15EE and 15EE that are adjacent to each other in the Y direction, instead of the diffusion isolation layer 85 shown in FIG. １ and 71b １ The pair of shallow isolation regions 71a １ and 71b １ The pair of shallow isolation regions 71a and 71b are configured as oblique trenches similar to the pair of shallow isolation regions 71a and 71b. １ and 71b １ The element forming region 21c is partitioned by １ The pixel transistor Q is provided in the pair of shallow isolation regions 71a. １ and 71b １In this way, shallow isolation regions 71a and 71b of an oblique trench structure extending in the Y direction and shallow isolation region 71a of an oblique trench structure extending in the X direction are formed. １ , 71b １ The present technology can also be applied to the solid-state imaging device 1H of the eighth embodiment, which mixes a shallow isolation region 75 with a vertical trench structure and a shallow isolation region 75 with a vertical trench structure, and the same effects as those of the solid-state imaging device 1E of the fifth embodiment described above can be obtained.

[0318] Ninth Embodiment In this ninth embodiment, a configuration will be described in which shallow isolation regions with an oblique trench structure extending in the Y direction and shallow isolation regions with a vertical trench structure are mixed. Fig. 54 is a plan view schematically showing an example configuration of a pixel block group included in a pixel array section in a solid-state imaging device according to a ninth embodiment of the present technology. Fig. 55 is a longitudinal sectional view schematically showing a longitudinal sectional structure taken along the a54-a54 cutting line in Fig. 54. Fig. 56 is a longitudinal sectional view schematically showing a longitudinal sectional structure taken along the b54-b54 cutting line in Fig. 54.

[0319] As shown in Figures 54 to 56, the solid-state imaging device 1I of the ninth embodiment of the present technology is basically configured in the same manner as the solid-state imaging device 1E of the fifth embodiment described above, with the following differences in configuration.

[0320] 54 to 56, the solid-state imaging device 1I according to the ninth embodiment, like the sixth embodiment, does not include a pixel transistor Q between two pixel block groups 15EE and 15EE that are adjacent to each other in the Y direction. Furthermore, the solid-state imaging device 1I according to the ninth embodiment includes a vertical shallow isolation region 75 instead of the diffusion isolation layer 85 of the fifth embodiment shown in FIGS. 42 and 44. In the ninth embodiment, except for the area between two pixels 3 that are adjacent to each other in the Y direction and share the element formation region 21c, two adjacent pixels 3 (photoelectric conversion regions 22) are separated by a deep isolation region 81 and a shallow isolation region 75 that are aligned in the thickness direction (Z direction) of the semiconductor layer 21.

[0321] Furthermore, the solid-state imaging device 1I according to the ninth embodiment has two pixel blocks 15E arranged adjacent to each other in the Y direction. １ and 15E ２ and a p-type power supply contact region WC provided individually for each of the four pixels 3 located on the boundary side between the ６ The p-type power supply contact region WC ６ Although not shown, the above-mentioned power supply contact area WC ２ Similarly, the power supply contact region WC is provided in the p-type well region 23 in the element forming region 21d, in the surface layer portion on the first surface portion S1 side of the semiconductor layer 21. ６ The p-type well region 23 is also formed of a p-type semiconductor region having a higher impurity concentration than the p-type well region 23 and is electrically connected to the p-type well region 23 .

[0322] In this way, the present technology can also be applied to the solid-state imaging device 1I of the ninth embodiment, which mixes shallow isolation regions 71a, 71b with an oblique trench structure extending in the Y direction and a shallow isolation region 75 with a vertical trench structure, and the same effects as those of the solid-state imaging device 1E of the fifth embodiment described above can be obtained.

[0323] Tenth Embodiment In this tenth embodiment, a configuration will be described in which a floating diffusion region is individually provided for each of four pixels that are arranged adjacent to one another in a plan view. Fig. 57 is a plan view schematically showing a configuration example of a pixel block group included in a pixel array unit in a solid-state imaging device according to a tenth embodiment of the present technology. Fig. 58 is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the a57-a57 cutting line in Fig. 57. Fig. 59 is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the b57-b57 cutting line in Fig. 57. Fig. 60 is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the c57-c57 cutting line in Fig. 57.

[0324] As shown in Figures 57 to 59, the solid-state imaging device 1J of the tenth embodiment of the present technology is basically configured in the same manner as the solid-state imaging device 1I of the ninth embodiment described above, except for the configuration of the floating diffusion region FD.

[0325] That is, the floating diffusion region FD of the tenth embodiment is １ and 15E ２ 60 , each of the four photoelectric conversion regions FD is provided individually for each of the four pixels 3 (3 a, 3 b, 3 c, 3 d) so as to surround an intersection 75XY where the shallow isolation region 75 extending in the X direction intersects with the shallow isolation region 75 extending in the Y direction. Further, as shown in FIG. 60 , each of the four photoelectric conversion regions FD is electrically and mechanically connected to a relay electrode 89 that straddles the intersection 75XY of the shallow isolation regions 75 and covers the four photoelectric conversion regions FD.

[0326] In this way, the present technology can also be applied to the solid-state imaging device 1J of the 10th embodiment, in which the floating diffusion region FD is individually provided for each of the four pixels 3 (3a, 3b, 3c, 3d) that are arranged adjacent to each other in a planar view, and the same effects as those of the solid-state imaging device 1E of the fifth embodiment described above can be obtained.

[0327] [Eleventh Embodiment] In this eleventh embodiment, a configuration will be described in which a floating diffusion region is provided in an element formation region partitioned on both sides by shallow isolation regions with a diagonal trench structure. Fig. 61 is a plan view schematically showing an example configuration of a pixel block group included in a pixel array section in a solid-state imaging device according to an eleventh embodiment of the present technology. Fig. 62 is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the a61-a61 cutting line in Fig. 61. Fig. 63 is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the b61-b61 cutting line in Fig. 61. Note that in Fig. 61, the relay electrodes shown in Fig. 62 are omitted for ease of viewing.

[0328] As shown in Figure 61, the solid-state imaging device 1K according to the eleventh embodiment of the present technology is basically configured in the same manner as the solid-state imaging device 1J according to the tenth embodiment described above, with the following differences in configuration.

[0329] That is, as shown in Figure 61, the solid-state imaging device 1K of the 11th embodiment includes shallow isolation regions 76a, 76b, 76c, and 76d of an oblique trench structure instead of the shallow isolation region 57 of the vertical trench structure shown in Figure 57 of the above-mentioned 10th embodiment, an element formation region 21k partitioned by these four shallow isolation regions 76a, 76b, 76c, and 76d, and a floating diffusion region FD provided in this element formation region 21k.

[0330] The element formation region 21k is provided across four adjacent pixels 3 (3a, 3b, 3c, 3d) arranged inside each of the pixel blocks 15E1 and 15E2. The element formation region 21k is partitioned on both sides in the X direction by two shallow isolation regions 76a and 76b, as shown in FIG. 62. The element formation region 21k is also partitioned on both sides in the Y direction by two shallow isolation regions 76c and 76d, as shown in FIG. 63.

[0331] 62, the shallow isolation regions 76a and 76b are arranged adjacent to each other in the X direction. Similarly to the diffusion isolation layer 85 described above, each of the shallow isolation regions 76a and 76b overlaps with the deep isolation region 81 in a plan view and extends across the first surface portion S1 (not shown) of the semiconductor layer 21 and the deep isolation region 81.

[0332] As shown in FIG. 62, the shallow isolation region 76a has an inclined surface 76a between it and the element forming region 21k. １ The shallow isolation region 76b has an inclined surface 76b between the shallow isolation region 76b and the element forming region 21k. １ The inclined surface 76a of the shallow isolation region 76a １ The inclined surface 76b of the shallow isolation region 76b extends obliquely from the upper surface of the shallow isolation region 76a toward the shallow isolation region 76b. １ extends obliquely from the upper surface of the shallow isolation region 76b toward the shallow isolation region 76a. The shallow isolation regions 76a and 76b are spaced apart above the element formation region 21k and connected below the element formation region 21k.

[0333] Similar to the above-described shallow isolation regions 71a and 71b, each of the shallow isolation regions 76a and 76b includes shallow recessed portions 77a and 77b extending from the first face S1 side of the semiconductor layer 21 toward the deep isolation region 81, and isolation insulating films 78a and 78b provided inside the shallow recessed portions 77a and 77b to bury the shallow recessed portions 77a and 77b. Similarly to the above-described shallow isolation regions 71a and 71b, each of the shallow isolation regions 76a and 76b can be easily constructed, for example, by selectively etching the first face S1 side of the semiconductor layer 21 while tilting the semiconductor layer 21 with respect to the vertical direction to form a shallow recessed portion.

[0334] 63, the shallow isolation regions 76c and 76d are arranged adjacent to each other in the X direction. Like the diffusion isolation layer 85 described above, each of the shallow isolation regions 76c and 76d overlaps with the deep isolation region 81 in a plan view and extends across the first surface portion S1 (not shown) of the semiconductor layer 21 and the deep isolation region 81.

[0335] As shown in FIG. 63, the shallow isolation region 76c has an inclined surface 76c between it and the element forming region 21k. １ The shallow isolation region 76d has an inclined surface 76d between the element forming region 21k and the shallow isolation region 76d. １ The inclined surface 76c of the shallow isolation region 76c １ The inclined surface 76d of the shallow isolation region 76d extends obliquely from the upper surface of the shallow isolation region 76a toward the shallow isolation region 76d. １ extends obliquely from the upper surface of shallow isolation region 76d toward shallow isolation region 76c. Shallow isolation regions 76c and 76d are spaced apart above element formation region 21k and connected below element formation region 21k.

[0336] Similar to the above-described shallow isolation regions 71a and 71b, each of the shallow isolation regions 76c and 76d includes shallow recessed portions 77c and 77d extending from the first face S1 side of the semiconductor layer 21 toward the deep isolation region 81, and isolation insulating films 78c and 78d provided inside the shallow recessed portions 77c and 77d so as to bury the shallow recessed portions 77c and 77d. Similarly to the above-described shallow isolation regions 71a and 71b, each of the shallow isolation regions 76c and 76d can be easily constructed, for example, by selectively etching the first face S1 side of the semiconductor layer 21 while tilting the semiconductor layer 21 with respect to the vertical direction to form a shallow recessed portion.

[0337] As shown in Figures 61 to 63, the floating diffusion region FD of this 11th embodiment is provided in the element formation region 21k, and is provided across four pixels 3 (3a, 3b, 3c, 3d) within each of the pixel blocks 15E1 and 15E2, and is shared by these four pixels 3 (3a, 3b, 3c, 3d).

[0338] In this way, the present technology can also be applied to the solid-state imaging device 1K of the 11th embodiment, in which a floating diffusion region FD is provided in the element formation region 21k partitioned on all sides by shallow isolation regions 76a, 76b, 76c, and 76d having an oblique trench structure, and the same effects as those of the solid-state imaging device 1E of the fifth embodiment described above can be obtained.

[0339] 64 is a plan view schematically illustrating a configuration example of a pixel block group included in a pixel array unit in a solid-state imaging device according to a twelfth embodiment of the present technology. As shown in Fig. 64, a solid-state imaging device 1L according to the twelfth embodiment of the present technology has a configuration basically similar to that of the solid-state imaging device 1E according to the fifth embodiment described above, except that the configuration of one shallow isolation region 71a of a pair of shallow isolation regions 71a and 71b is different.

[0340] 64, one shallow isolation region 71a of the twelfth embodiment has both ends in the Y direction terminated inside one pixel block 15EE. Specifically, one shallow isolation region 71a of the twelfth embodiment is located between two pixel blocks 15EE in the Y direction inside one pixel block group 15EE. １and 15E ２ In other words, in the twelfth embodiment, one shallow isolation region 71a, unlike the shallow isolation region 71b, does not extend across (span) the two pixel block groups 15EE and 15EE aligned in the Y direction.

[0341] In this way, the present technology can also be applied to the solid-state imaging device 1L of the 12th embodiment in which one of the pair of shallow isolation regions 71a and 71b, 71a, terminates inside the pixel block group 15EE, and the same effect as that of the solid-state imaging device 1E of the fifth embodiment described above can be obtained.

[0342] Thirteenth Embodiment FIG. 65 is a plan view schematically showing an example of the configuration of a pixel block group included in a pixel array unit in a solid-state imaging device according to a thirteenth embodiment of the present technology.

[0343] As shown in Figure 65, the solid-state imaging device 1M of the thirteenth embodiment of the present technology is basically configured in the same manner as the solid-state imaging device 1E of the fifth embodiment described above, except for the configuration of the pair of shallow isolation regions 71a and 71b.

[0344] 65, each of the pair of shallow isolation regions 71a and 71b in the thirteenth embodiment is alternately separated between two pixel block groups 15EE and 15EE aligned in the Y direction. In other words, each of the pair of shallow isolation regions 71a and 71b in the thirteenth embodiment is separated between two pixel block groups 15EE and 15EE aligned in the Y direction by one shallow isolation region 71a, and the other shallow isolation region crosses between the two pixel block groups 15EE and 15EE in the Y direction.

[0345] In this way, the present technology can also be applied to the solid-state imaging device 1M of the 13th embodiment in which a pair of shallow isolation regions 71a and 71b are alternately separated between two pixel block groups 15EE and 15EE arranged in the Y direction, and the same effects as those of the solid-state imaging device 1E of the fifth embodiment described above can be obtained.

[0346] Fourteenth Embodiment FIG. 66 is a plan view schematically showing an example of the configuration of a pixel block group included in a pixel array unit in a solid-state imaging device according to a fourteenth embodiment of the present technology.

[0347] As shown in Figure 66, the solid-state imaging device 1N of the fourteenth embodiment of the present technology is basically configured in the same manner as the solid-state imaging device 1E of the fifth embodiment described above, except for the configuration of the pair of shallow isolation regions 71a and 71b.

[0348] 66, each of the pair of shallow isolation regions 71a and 71b according to the fourteenth embodiment has both ends in the Y direction terminated within one pixel block 15EE. Specifically, each of the pair of shallow isolation regions 71a and 71b according to the fourteenth embodiment extends across two pixel blocks in the Y direction within one pixel block group 15EE, and both ends terminate within the pixel block group 15EE. In other words, in the fourteenth embodiment, neither of the pair of shallow isolation regions 71a and 71b extends across (across) the two pixel block groups 15EE and 15EE aligned in the Y direction.

[0349] In this way, the present technology can also be applied to the solid-state imaging device 1N of the 14th embodiment in which both of the pair of shallow isolation regions 71a and 71b terminate inside the pixel block group 15EE, and the same effects as those of the solid-state imaging device 1E of the fifth embodiment described above can be obtained.

[0350] Fifteenth Embodiment FIG. 75 is a plan view schematically showing an example of the configuration of a pixel block group included in a pixel array unit in a solid-state imaging device according to a fifteenth embodiment of the present technology.

[0351] As shown in Figure 67, the solid-state imaging device 1P of the fourteenth embodiment of the present technology is basically configured in the same manner as the solid-state imaging device 1E of the fifth embodiment described above, except for the configuration of the pair of shallow isolation regions 71a and 71b.

[0352] That is, as shown in FIG. 67, each of the pair of shallow isolation regions 71a and 71b according to the fifteenth embodiment is connected to each other via a shallow isolation region 79 having a vertical trench structure between two pixel block groups 15EE and 15EE that are arranged adjacent to each other in the Y direction.

[0353] In this way, the present technology can also be applied to the solid-state imaging device 1P of the 15th embodiment in which each of a pair of shallow isolation regions 71a and 71b is connected via a shallow isolation region 79 having a vertical trench structure, and the same effects as those of the solid-state imaging device 1E of the fifth embodiment described above can be obtained.

[0354] [16th embodiment] Fig. 68 is a plan view schematically showing a configuration example of a pixel block group included in a pixel array unit in a solid-state imaging device according to a 16th embodiment of the present technology. Fig. 69 is a longitudinal sectional view schematically showing a longitudinal sectional structure taken along the a68-a68 cutting line in Fig. 68. Fig. 70 is a longitudinal sectional view schematically showing a longitudinal sectional structure taken along the b68-b68 cutting line in Fig. 68.

[0355] As shown in Figures 68 to 70, the solid-state imaging device 1Q of the 16th embodiment of the present technology is basically configured in the same manner as the solid-state imaging device 1E of the fifth embodiment described above, with the following differences in configuration.

[0356] 68 and 69, the solid-state imaging device 1Q according to the sixteenth embodiment includes a diffusion isolation region 86 instead of the shallow isolation region 71b of the fifth embodiment shown in Figures 40 and 42. The element formation region 21c according to the sixteenth embodiment is partitioned on both sides in the Y direction by the shallow isolation region 71a and the diffusion isolation layer 86.

[0357] As shown in FIG. 68, the diffusion isolation layer 86 is formed between two pixel blocks 15E included in one pixel block group 15EE in plan view, similar to the shallow isolation region 71a. １ and 15E ２69 , the diffusion isolation layer 86 extends from the first surface S1 of the semiconductor layer 21 in the thickness direction (Z direction) of the semiconductor layer 21. Similar to the diffusion isolation region 85 described above, the diffusion isolation layer 86 is made of a p-type semiconductor region having a higher impurity concentration than the p-type well region 23.

[0358] In this way, the present technology can be applied to the solid-state imaging device 1Q of the 16th embodiment in which both sides of the element formation region 21c in the Y direction are partitioned by a shallow isolation region 71a with an oblique trench structure and a diffusion isolation layer 86, and the same effects as those of the solid-state imaging device 1E of the fifth embodiment described above can be obtained.

[0359] [Seventeenth embodiment] Fig. 71 is a plan view schematically showing a configuration example of a pixel block group included in a pixel array unit in a solid-state imaging device according to a seventeenth embodiment of the present technology. Fig. 72 is a longitudinal sectional view schematically showing a longitudinal sectional structure taken along the a71-a71 cutting line in Fig. 71. Note that in Fig. 71, relay electrodes shown in Fig. 72 are omitted from illustration in order to make the drawing easier to understand.

[0360] As shown in Figure 71, the solid-state imaging device 1R according to the seventeenth embodiment of the present technology is basically configured in the same manner as the solid-state imaging device 1I according to the ninth embodiment described above, with the following differences in configuration.

[0361] That is, as shown in FIGS. 71 and 72, the solid-state imaging device 1R according to the seventeenth embodiment has two pixel blocks 15E located inside a pixel block group 15EE. １ and 15E ２ Four power supply contact regions WC surrounding the intersection 75XY between ６ A relay electrode 90 is electrically and mechanically connected to each of the electrodes 75XY across the intersection 75XY.

[0362] Although not shown, four power supply contact regions WC surrounding the intersection 75XY located between two pixel blocks 15EE and 15EE aligned in the Y direction ６The relay electrode 90 is electrically and mechanically connected to the solid-state imaging device 1R according to the seventeenth embodiment. The present technology can be applied to the solid-state imaging device 1R according to the seventeenth embodiment as well, and the same effects as those of the solid-state imaging device 1E according to the fifth embodiment can be obtained.

[0363] [Eighteenth embodiment] Fig. 73 is a plan view schematically showing a configuration example of a pixel block group included in a pixel array unit in a solid-state imaging device according to an eighteenth embodiment of the present technology. Fig. 74 is a longitudinal sectional view schematically showing a longitudinal sectional structure taken along the a73-a73 cutting line in Fig. 73. Note that in Fig. 73, relay electrodes shown in Fig. 74 are omitted from illustration in order to make the drawing easier to understand.

[0364] As shown in Figure 73, the solid-state imaging device 1S according to the 18th embodiment of the present technology is basically configured in the same manner as the solid-state imaging device 1R according to the 17th embodiment described above, with the following differences in configuration.

[0365] That is, as shown in FIG. 73, the solid-state imaging device 1S according to the 18th embodiment includes shallow isolation regions 76a, 76b, 76c, and 76d having an oblique trench structure instead of the shallow isolation region 57 having a vertical trench structure shown in FIG. 71 of the above-described 17th embodiment, an element forming region 21s partitioned by these four shallow isolation regions 76a, 76b, 76c, and 76d, and a power supply contact region WC provided in this element forming region 21s. ７ It is equipped with the following.

[0366] The element formation region 21s is formed by pixel blocks 15E arranged adjacent to each other in the Y direction within one pixel block group 15EE. １ and 15E ２ 74, the element formation region 21s is partitioned on both sides in the X direction by two shallow isolation regions 76a and 76b. Also, as shown in FIG. 75, the element formation region 21s is partitioned on both sides in the Y direction by two shallow isolation regions 76c and 76d.

[0367] 74, the shallow isolation regions 76a and 76b are arranged adjacent to each other in the X direction. Similarly to the diffusion isolation layer 85 described above, each of the shallow isolation regions 76a and 76b overlaps with the deep isolation region 81 in a plan view and extends across the first surface portion S1 (not shown) of the semiconductor layer 21 and the deep isolation region 81.

[0368] As shown in FIG. 74, the shallow isolation region 76a has an inclined surface 76a between it and the element forming region 21s. ２ The shallow isolation region 76b has an inclined surface 76b between the shallow isolation region 76b and the element formation region 21s. ２ The inclined surface 76a of the shallow isolation region 76a ２ The inclined surface 76b of the shallow isolation region 76b extends obliquely from the upper surface of the shallow isolation region 76a toward the shallow isolation region 76b. ２ extends obliquely from the upper surface of the shallow isolation region 76b toward the shallow isolation region 76a. The shallow isolation regions 76a and 76b are spaced apart above the element formation region 21s and connected below the element formation region 21s.

[0369] Similar to the above-described shallow isolation regions 71a and 71b, each of the shallow isolation regions 76a and 76b includes shallow recessed portions 77a and 77b extending from the first face S1 side of the semiconductor layer 21 toward the deep isolation region 81, and isolation insulating films 78a and 78b provided inside the shallow recessed portions 77a and 77b to bury the shallow recessed portions 77a and 77b. Similarly to the above-described shallow isolation regions 71a and 71b, each of the shallow isolation regions 76a and 76b can be easily constructed, for example, by selectively etching the first face S1 side of the semiconductor layer 21 while tilting the semiconductor layer 21 with respect to the vertical direction to form a shallow recessed portion.

[0370] 75, the shallow isolation regions 76c and 76d are arranged adjacent to each other in the X direction. Like the diffusion isolation layer 85 described above, each of the shallow isolation regions 76c and 76d overlaps with the deep isolation region 81 in a plan view and extends across the first surface portion S1 (not shown) of the semiconductor layer 21 and the deep isolation region 81.

[0371] As shown in FIG. 75, the shallow isolation region 76c has an inclined surface 76c between it and the element forming region 21s. ２ The shallow isolation region 76d has an inclined surface 76d between the shallow isolation region 76d and the element formation region 21s. ２ The inclined surface 76c of the shallow isolation region 76c ２ The inclined surface 76d of the shallow isolation region 76d extends obliquely from the upper surface of the shallow isolation region 76c toward the shallow isolation region 76d. ２ extends obliquely from the upper surface of the shallow isolation region 76d toward the shallow isolation region 76c. The shallow isolation regions 76c and 76d are spaced apart above the element formation region 21s and connected below the element formation region 21s.

[0372] Similar to the above-described shallow isolation regions 71a and 71b, each of the shallow isolation regions 76c and 76d includes shallow recessed portions 77c and 77d extending from the first face S1 side of the semiconductor layer 21 toward the deep isolation region 81, and isolation insulating films 78c and 78d provided inside the shallow recessed portions 77c and 77d so as to bury the shallow recessed portions 77c and 77d. Similarly to the above-described shallow isolation regions 71a and 71b, each of the shallow isolation regions 76c and 76d can be easily constructed, for example, by selectively etching the first face S1 side of the semiconductor layer 21 while tilting the semiconductor layer 21 with respect to the vertical direction to form a shallow recessed portion.

[0373] As shown in FIGS. 74 and 75, the power supply contact region WC of the 18th embodiment ７ is provided in the element formation region 21s, is provided across four pixels 3 (3a, 3b, 3c, 3d) surrounding the center between pixel blocks 15E1 and 15E2 in the pixel block group 15EE, and is shared by these four pixels 3 (3a, 3b, 3c, 3d).

[0374] In this way, the present technology can also be applied to the solid-state imaging device 1S according to the eighteenth embodiment, in which the power supply contact region WC7 is provided in the element formation region 21s partitioned on all sides by shallow isolation regions 76a, 76b, 76c, and 76d having an oblique trench structure, and the same effects as those of the solid-state imaging device 1E according to the fifth embodiment can be obtained. ７ is provided.

[0375] 76 is a plan view schematically showing a configuration example of a pixel block group included in a pixel array unit in a solid-state imaging device according to a 19th embodiment of the present technology. Fig. 77 is an enlarged longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the line a76-a76 in Fig. 76.

[0376] 76 and 77 , a solid-state imaging device 1T according to a 19th embodiment of the present technology has a configuration basically similar to that of the solid-state imaging device 1E according to the above-described fifth embodiment, with the following differences in configuration. That is, as shown in Fig. 76 and 77 , in the solid-state imaging device 1T according to the 19th embodiment, the gate electrode 54 of the pixel transistor Q has a fin structure. The other configurations are generally similar to those of the above-described fifth embodiment.

[0377] In this way, the present technology can also be applied to the solid-state imaging device 1T of the 19th embodiment in which the gate electrode 54 of the pixel transistor Q is configured with a fin structure, and the same effects as those of the solid-state imaging device 1E of the fifth embodiment described above can be obtained.

[0378] 78 is a plan view schematically showing an example of the configuration of a pixel block group included in a pixel array section in a solid-state imaging device according to a twentieth embodiment of the technology. Fig. 79 is a longitudinal sectional view schematically showing the longitudinal sectional structure taken along the a78-a78 cutting line in Fig. 78.

[0379] As shown in Figures 78 and 79, the solid-state imaging device 1U according to the twentieth embodiment of the present technology is basically configured in the same manner as the solid-state imaging device 1E according to the fifth embodiment described above, with the following differences in configuration.

[0380] 78 and 79, the solid-state imaging device 1U according to the twentieth embodiment includes a transfer transistor TR having a vertical structure instead of the transfer transistor TRL having a planar structure of the fifth embodiment shown in Fig. 40 and 42. The other configurations are generally similar to those of the fifth embodiment.

[0381] In this way, the present technology can also be applied to the solid-state imaging device 1U of the 20th embodiment, which has a transfer transistor TR with a vertical structure, and the same effects as those of the solid-state imaging device 1E of the fifth embodiment described above can be obtained.

[0382] Twenty-first embodiment <Application example to electronic devices> The present technology (technology related to the present disclosure) can be applied to various electronic devices, such as imaging devices such as digital still cameras and digital video cameras, mobile phones with imaging functions, or other devices with imaging functions.

[0383] FIG. 80 is a diagram showing a schematic configuration of an electronic device (for example, a camera) according to a fourth embodiment of the present technology.

[0384] 80, the electronic device 100 includes a solid-state imaging device 101, an optical lens 102, a shutter device 103, a drive circuit 104, and a signal processing circuit 105. The electronic device 100 illustrates an embodiment in which the solid-state imaging devices 1A to 1U according to the first to third embodiments of the present technology and the modified example of the first embodiment are used in an electronic device (for example, a camera) as the solid-state imaging device 101.

[0385] The optical lens 102 focuses image light (incident light 106) from the subject on the imaging surface of the solid-state imaging device 101. This causes signal charges to accumulate in the solid-state imaging device 101 for a certain period of time. The shutter device 103 controls the light irradiation period and light blocking period of the solid-state imaging device 101. The drive circuit 104 supplies drive signals that control the transfer operation of the solid-state imaging device 101 and the shutter operation of the shutter device 103. The drive signals (timing signals) supplied from the drive circuit 104 cause charge transfer in the solid-state imaging device 101. The signal processing circuit 105 performs various signal processing on signals (pixel signals (image signals)) output from the solid-state imaging device 101. The processed video signals are stored in a storage medium such as a memory or output to a monitor.

[0386] With this configuration, a high saturation charge amount Qs is obtained in the solid-state imaging device 101, and therefore the image quality performance of the electronic device 100 of the fifth embodiment can be improved.

[0387] The electronic device 100 to which the solid-state imaging device of the above-described embodiment can be applied is not limited to a camera, but can also be applied to other electronic devices. For example, the solid-state imaging device may be applied to an imaging device such as a camera module for a mobile device such as a mobile phone or a tablet terminal.

[0388] Furthermore, the present technology can be applied to not only the solid-state imaging device as the image sensor described above, but also to photodetection devices in general, including distance measurement sensors called ToF (Time of Flight) sensors that measure distance. A distance measurement sensor emits light toward an object, detects the light reflected from the surface of the object, and calculates the distance to the object based on the time of flight between when the light is emitted and when the reflected light is received. The pixel transistor described above can also be used in this distance measurement sensor.

[0389] The present technology may also be configured as follows: (1) A photodetector comprising: a semiconductor layer having a first surface portion and a second surface portion located opposite each other in one direction, a shallow isolation region provided on the first surface portion side of the semiconductor layer, an element formation region partitioned by the shallow isolation region on the first surface portion side of the semiconductor layer and having a pixel transistor provided therein, and a photoelectric conversion region partitioned by a deep isolation region extending from the second surface portion side of the semiconductor layer toward the first surface portion side and having a photoelectric conversion portion provided therein, wherein a portion of the deep isolation region that overlaps with the element formation region in a plan view protrudes toward the first surface side of the semiconductor layer beyond a bottom of the shallow isolation region. (2) The photodetector according to (1) above, wherein the shallow isolation region includes: a first shallow isolation portion that partitions the element formation region; and a second shallow isolation portion that overlaps the deep isolation region in a planar view, and the deep isolation region includes: a first deep isolation portion that overlaps the element formation region in a planar view; and a second deep isolation portion that overlaps the second shallow isolation portion of the shallow isolation region in a planar view. (3) The photodetector according to (2) above, wherein the first deep isolation portion is spaced apart from the first shallow isolation portion. (4) The photodetector according to (2) or (3) above, wherein the width of the first deep isolation portion in the lateral direction is wider than the width of the second deep isolation portion in the lateral direction. (5) The photodetector according to (2) above, wherein the first deep isolation portion is connected to the first shallow isolation portion. (6) The photodetector according to any one of (2) to (5) above, wherein the first deep isolation portion is configured so that its width in the short side direction is wider than the width in the short side direction of the element formation region and is connected to the first shallow isolation portion so as to block the element formation region. (7) The photodetector according to any one of (2) to (6) above, wherein the width in the short side direction of the first deep isolation portion is wider on the first surface side of the semiconductor layer than on the second surface side.(8) The photodetector according to (2) above, wherein the first deep isolation portion includes a main isolation portion extending from the second surface portion side of the semiconductor layer toward the first surface portion side, and an isolation extension portion that is integrated with the main isolation portion on the element formation region side of the main isolation portion and that extends further toward the photoelectric conversion region than the main isolation portion, and the isolation extension portion is connected to the first shallow isolation portion so as to block the bottom side of the element formation region. (9) The photodetector according to any of (2) to (8) above, wherein the width of the first shallow isolation portion in the lateral direction on the first surface portion side of the semiconductor layer is narrower than the width of the first shallow isolation portion in the lateral direction on the bottom side of the first shallow isolation portion, and the deep isolation portion is connected to the first shallow isolation portion so as to block the bottom side of the element formation region. (10) The photodetector according to (2) above, wherein the first shallow isolation portion includes a main shallow isolation portion extending from the first surface portion side of the semiconductor layer toward the second surface portion side, and a shallow isolation extension portion provided integrally with the main shallow isolation portion on the photoelectric conversion region side of the main shallow isolation portion and extending beyond the main shallow isolation portion in a lateral direction of the main isolation portion, and the first deep isolation portion is connected to the shallow isolation extension portion. (11) The photodetector according to any of (2) to (10) above, wherein the deep isolation region includes a deep recessed portion extending from the second surface portion side of the semiconductor layer toward the first surface portion side, and an isolation insulating film provided inside the deep recessed portion. (12) The photodetector according to any one of (2) to (10) above, wherein the deep isolation region includes: a deep carved portion extending from the second surface side of the semiconductor layer toward the first surface side, an insulating thin film provided along an inner wall surface of the deep carved portion, and a conductor provided inside the carved portion with the insulating thin film interposed therebetween. (13) The photodetector according to any one of (2) to (12) above, wherein the photoelectric conversion region has a rectangular planar shape, and the element formation region is provided on a side of the photoelectric conversion region in a planar view.(14) The photodetector according to any one of (2) to (13), further comprising: a first element formation region as the element formation region; a second element formation region partitioned by the shallow isolation region on the first surface portion side of the semiconductor layer and provided so as to overlap the photoelectric conversion region in a planar view; a charge holding portion provided in the second element formation region and holding signal charges photoelectrically converted in the photoelectric conversion portion; and a transfer transistor provided in the second element formation region and transferring the signal charges photoelectrically converted in the photoelectric conversion portion to the charge holding portion. (15) The photodetector according to (14), further comprising: a readout circuit that reads out the signal charges held in the charge holding portion and outputs a pixel signal based on the readout signal charges, the readout circuit including the pixel transistor. (16) A photodetector comprising: a semiconductor layer having a first surface portion and a second surface portion located opposite each other in one direction; a shallow isolation region provided on the first surface portion side of the semiconductor layer; an element formation region partitioned by the shallow isolation region on the first surface portion side of the semiconductor layer and having a pixel transistor provided therein; and a photoelectric conversion region partitioned by a deep isolation region extending from the second surface portion side of the semiconductor layer toward the first surface portion side and having a photoelectric conversion portion provided therein; wherein the shallow isolation region includes an isolation blocking portion that blocks a bottom side of the element formation region, and a portion of the deep isolation region that overlaps with the element formation region in a planar view is connected to the isolation blocking portion. (17) The photodetector according to (16) above, wherein the shallow isolation region includes a first shallow isolation portion that partitions the element formation region and a second shallow isolation portion that overlaps with the deep isolation region in a planar view, the deep isolation region includes a first deep isolation portion that overlaps with the element formation region in a planar view and a second deep isolation portion that overlaps with the second shallow isolation portion of the shallow isolation region in a planar view, the first shallow isolation portion includes main shallow isolation portions provided on both sides of the element formation region in the short direction, and the isolation blocking portion is integrated with the main shallow isolation portion so as to block the element formation region on the first deep isolation portion side of the shallow isolation portion, and the end of the first deep isolation portion on the element formation region side is connected to the isolation blocking portion.(18) The photodetector according to (1), wherein the shallow isolation region includes: a shallow recessed portion provided in a first surface portion of the semiconductor layer, an isolation insulating film provided inside the shallow recessed portion, and a light reflecting film interposed between the shallow recessed portion and the isolation insulating film and having a higher light reflectivity than the isolation insulating film. (19) The photodetector according to (18), wherein the shallow isolation region includes: a first shallow isolation portion that partitions the element formation region, and a second shallow isolation portion that overlaps the deep isolation region in a planar view, and the light reflecting film is provided in at least the first shallow isolation portion of the first and second shallow isolation portions. (20) A photodetector comprising: a semiconductor layer having a first surface portion and a second surface portion located opposite each other in one direction; a photoelectric conversion region defined by a deep isolation region extending from the second surface portion of the semiconductor layer toward the first surface portion, and having a photoelectric conversion portion provided therein; an element formation region defined by a shallow isolation region on the first surface portion side of the semiconductor layer, overlapping the deep isolation region in a planar view, and having a pixel transistor provided therein; wherein the shallow isolation region includes: a shallow recessed portion provided in the first surface portion of the semiconductor layer; an isolation insulating film provided inside the shallow recessed portion; and a light reflecting film interposed between the shallow recessed portion and the isolation insulating film, and having a higher light reflectivity than the isolation insulating film. (21) A photodetector comprising: a semiconductor layer having a first surface portion and a second surface portion located opposite each other in one direction; a photoelectric conversion region partitioned by a deep isolation region extending from the second surface portion side of the semiconductor layer toward the first surface portion side, and having a photoelectric conversion portion provided therein; and an element formation region partitioned by a shallow isolation region on the first surface portion side of the semiconductor layer, overlapping the deep isolation region in a planar view, and having a pixel transistor provided therein; wherein the shallow isolation region is inclined with respect to the first surface portion of the semiconductor layer in a cross section across the deep isolation region, and is connected to the deep isolation region.(22) The photodetector according to (21) above, wherein the element formation region is partitioned by a pair of the shallow isolation regions aligned and spaced apart in a horizontal direction across the deep isolation region, and wherein, in a cross section across the deep isolation region, one of the pair of shallow isolation regions is inclined in a first oblique direction with respect to the first surface portion of the semiconductor layer and the other of the pair of shallow isolation regions is inclined in a second oblique direction intersecting the first oblique direction, and at least one of the shallow isolation regions is connected to the deep isolation region. (23) The photodetector according to (21) or (22) above, wherein the shallow isolation region includes a recessed portion provided on the first surface side of the semiconductor layer at an angle with respect to the first surface portion, and an isolation insulating film provided inside the recessed portion. (24) The photodetector according to (21) or (22), wherein the shallow isolation region is a first shallow isolation region, and further comprising a second shallow isolation region provided on the first surface portion side of the semiconductor layer so as to overlap the deep isolation region in a plan view. (25) The photodetector according to (24), wherein the first shallow isolation region is provided on the first surface portion side of the semiconductor layer and is configured as an oblique trench type including a recessed portion extending obliquely with respect to the first surface portion, and the second shallow isolation region is provided on the first surface portion side of the semiconductor layer and is configured as a vertical trench type including a recessed portion extending perpendicular to the first surface portion, or a diffusion isolation type in which impurities are diffused. (26) An electronic device comprising: the photodetector according to any of (1) to (25), an optical lens that focuses image light from a subject on an imaging surface of the photodetector, and a signal processing circuit that processes signals output from the photodetector.

[0390] The scope of the present technology is not limited to the exemplary embodiments shown and described, but includes all embodiments that achieve equivalent effects to those intended by the present technology. Furthermore, the scope of the present technology is not limited to the combination of the features of the invention defined by the claims, but may be defined by any desired combination of specific features among all the respective disclosed features.

[0391] DESCRIPTION OF SYMBOLS 1A, 1B, 1C...Solid-state imaging device 2...Semiconductor chip 2A...Pixel array section 2B...Peripheral section 3, 3a, 3b, 3c, 3d...Pixels (sensor pixels) 4...Vertical drive circuit 5...Column signal processing circuit 6...Horizontal drive circuit 7...Output circuit 8...Control circuit 10...Pixel drive line 11...Vertical signal line 12...Horizontal signal line 13...Logic circuit 14...Bonding pad 15A...Pixel block 16A...Readout circuit 21...Semiconductor layer 21a, 21b...Element formation region 22...Photoelectric conversion region 23...P-type well region 24...N-type semiconductor region 25...Photoelectric conversion section 31...Shallow isolation region 31a...First shallow isolation portion 31aa...Main shallow isolation portion 31ab...Shallow isolation extension portion 31ac...Isolation blocking portion 31b...Second shallow isolation portion 32...Shallow recessed portion 33...Isolation insulating film 35...Reflective film 41...Deep isolation region 41a...First deep isolation portion 41aa...Main deep isolation portion 41ab...Deep isolation extension portion 41b...Second deep isolation portion 41ba...Main deep isolation portion 41bb...Deep isolation extension portion 41X...First planar extension portion 41Y...Second planar extension portion 42...Deeply carved portion 43...Isolation insulating film 43a...Insulating thin film 45...Conductor 46...Fixed charge film 47...Pinning layer 51...Gate trench portion (gate carved portion) 52...Gate insulating film 53...Gate electrode 53a...Head portion 53b...Body portion 54a, 54fd, 54r, 54s...Gate electrodes 55a １ , 55a ２ , 55fd, 55r, 55s... n-type semiconductor region 61... multi-layer wiring layer 62... interlayer insulating film 63a １ , 63a ２ , 63fd, 63ga, 63gf, 63gr, 63gs, 63r, 63s...contact electrodes 64...wiring layer 64a １ , 64a ２, 64fd, 64ga, 64gf, 64gr, 64gs, 64r, 64s...wiring 71a, 71b...shallow isolation region (diagonal trench structure) 72a, 72b...shallow recessed portion 73a, 73b...isolation insulating film 75...shallow isolation region (vertical trench structure) 76a, 76b, 76c, 76d...shallow isolation region (diagonal trench structure) 77a, 77b, 77c, 77d...recessed portion 78a, 78b, 78c, 78d...isolation insulating film 79...shallow isolation region (vertical trench structure) 81...deep isolation region 82...recessed portion 83...isolation insulating film 85, 86...diffusion isolation layer 89, 90...relay electrode 100...electronic device 101...solid-state imaging device 102...optical lens (optical system) 103...shutter device 104...drive circuit 105...signal processing circuit 106...incident light AMP...amplifying transistor FD...n-type floating diffusion region FDG...switching transistor Q...pixel transistor RST...reset transistor SEL...selection transistor S1...first surface portion S2...second surface portion TR, TRL...transfer transistor WC, WC １ , W.C. ２ , W.C. ３ , W.C. ４ , W.C. ５ , W.C. ６ , W.C. ７ ...Power supply contact area

Claims

1. A photodetector comprising: a semiconductor layer having a first surface portion and a second surface portion located opposite each other in one direction; a shallow isolation region provided on the first surface portion side of the semiconductor layer; an element formation region defined by the shallow isolation region on the first surface portion side of the semiconductor layer and having a pixel transistor provided therein; and a photoelectric conversion region defined by a deep isolation region extending from the second surface portion side of the semiconductor layer toward the first surface portion side and having a photoelectric conversion portion provided therein; wherein a portion of the deep isolation region that overlaps with the element formation region in a planar view protrudes toward the first surface side of the semiconductor layer beyond the bottom of the shallow isolation region.

2. The photodetector device of claim 1, wherein the shallow isolation region includes a first shallow isolation portion that partitions the element formation region and a second shallow isolation portion that overlaps the deep isolation region in a planar view, and the deep isolation region includes a first deep isolation portion that overlaps the element formation region in a planar view and a second deep isolation portion that overlaps the second shallow isolation portion of the shallow isolation region in a planar view.

3. The optical detection device of claim 2, wherein said first deep isolation portion is spaced apart from said first shallow isolation portion.

4. The photodetector according to claim 2, wherein the width of the first deep isolation portion in the lateral direction is greater than the width of the second deep isolation portion in the lateral direction.

5. The photodetector device of claim 2, wherein said first deep isolation portion is connected to said first shallow isolation portion.

6. A photodetector device as described in claim 2, wherein the first deep isolation portion is configured so that its width in the short side direction is wider than the width in the short side direction of the element formation region, and is connected to the first shallow isolation portion so as to block the element formation region.

7. The photodetector according to claim 2, wherein the width of the first deep isolation portion in the lateral direction is wider on the first surface side of the semiconductor layer than on the second surface side.

8. A photodetector device as described in claim 2, wherein the first deep isolation portion includes a main isolation portion extending from the second surface side of the semiconductor layer toward the first surface side, and an isolation extension portion that is integrated with the main isolation portion on the element formation region side of the main isolation portion and that extends further toward the photoelectric conversion region than the main isolation portion, and the isolation extension portion is connected to the first shallow isolation portion so as to block the bottom side of the element formation region.

9. A photodetector device as described in claim 2, wherein the width of the first shallow isolation portion in the short direction on the first surface side of the semiconductor layer is narrower than the width of the first shallow isolation portion in the short direction on the bottom side of the first shallow isolation portion, and the deep isolation portion is connected to the first shallow isolation portion so as to block the bottom side of the element formation region.

10. The photodetector device described in claim 2, wherein the first shallow isolation portion includes a main shallow isolation portion extending from the first surface side of the semiconductor layer toward the second surface side, and a shallow isolation extension portion that is integrated with the main shallow isolation portion on the photoelectric conversion region side of the main shallow isolation portion and that extends further in the short direction of the main isolation portion than the main shallow isolation portion, and the first deep isolation portion is connected to the shallow isolation extension portion.

11. The photodetector device according to claim 1, wherein the deep isolation region includes a deep recess extending from the second surface side of the semiconductor layer toward the first surface side, and an isolation insulating film provided inside the deep recess.

12. The photodetector device of claim 1, wherein the deep isolation region includes: a deep recess extending from the second surface side of the semiconductor layer toward the first surface side; an insulating thin film provided along the inner wall surface of the deep recess; and a conductor provided inside the recess with the insulating thin film interposed therebetween.

13. The photodetector according to claim 1, wherein the photoelectric conversion region has a rectangular planar shape, and the element formation region is provided on a side of the photoelectric conversion region in a planar view.

14. The photodetector according to claim 1, further comprising: a first element formation region, a second element formation region partitioned by the shallow isolation region on the first surface side of the semiconductor layer and overlapping the photoelectric conversion region in a planar view; a charge holding section provided in the second element formation region and holding signal charges photoelectrically converted in the photoelectric conversion section; and a transfer transistor provided in the second element formation region and transferring signal charges photoelectrically converted in the photoelectric conversion section to the charge holding section.

15. The photodetector according to claim 14, further comprising a readout circuit that reads out the signal charge held in the charge holding portion and outputs a pixel signal based on the readout signal charge, wherein the readout circuit includes the pixel transistor.

16. A photodetector comprising: a semiconductor layer having a first surface portion and a second surface portion located opposite each other in one direction; a shallow isolation region provided on the first surface portion side of the semiconductor layer; an element formation region partitioned by the shallow isolation region on the first surface portion side of the semiconductor layer and having a pixel transistor provided therein; and a photoelectric conversion region partitioned by a deep isolation region extending from the second surface portion side of the semiconductor layer toward the first surface portion side and having a photoelectric conversion portion provided therein; wherein the shallow isolation region includes an isolation blocking portion that blocks the bottom side of the element formation region, and a portion of the deep isolation region that overlaps with the element formation region in a planar view is connected to the isolation blocking portion.

17. The photodetector device described in claim 16, wherein the shallow isolation region includes a first shallow isolation portion that partitions the element formation region and a second shallow isolation portion that overlaps with the deep isolation region in a planar view, the deep isolation region includes a first deep isolation portion that overlaps with the element formation region in a planar view and a second deep isolation portion that overlaps with the second shallow isolation portion of the shallow isolation region in a planar view, the first shallow isolation portion includes main shallow isolation portions provided on both sides of the element formation region in the short direction, and the isolation blocking portion is integrated with the main shallow isolation portion so as to block the element formation region on the first deep isolation portion side of the shallow isolation portion, and the end of the first deep isolation portion on the element formation region side is connected to the isolation blocking portion.

18. The photodetector according to claim 1, wherein the shallow isolation region includes: a shallow recessed portion provided in a first surface portion of the semiconductor layer; an isolation insulating film provided inside the shallow recessed portion; and a light reflecting film interposed between the shallow recessed portion and the isolation insulating film and having a higher light reflectivity than the isolation insulating film.

19. The photodetector device described in claim 18, wherein the shallow isolation region includes a first shallow isolation portion that partitions the element formation region and a second shallow isolation portion that overlaps the deep isolation region in a planar view, and the light reflecting film is provided on at least the first shallow isolation portion of the first and second shallow isolation portions.

20. A photodetector comprising: a semiconductor layer having a first surface portion and a second surface portion located opposite each other in one direction; a photoelectric conversion region defined by a deep isolation region extending from the second surface portion of the semiconductor layer toward the first surface portion, and having a photoelectric conversion portion provided therein; an element formation region defined by a shallow isolation region on the first surface portion side of the semiconductor layer, overlapping the deep isolation region in a plan view, and having a pixel transistor provided therein; wherein the shallow isolation region includes: a shallow recessed portion provided in the first surface portion of the semiconductor layer; an isolation insulating film provided inside the shallow recessed portion; and a light reflecting film interposed between the shallow recessed portion and the isolation insulating film, and having a higher light reflectivity than the isolation insulating film.

21. A photodetector comprising: a semiconductor layer having a first surface portion and a second surface portion located opposite each other in one direction; a photoelectric conversion region partitioned by a deep isolation region extending from the second surface portion side of the semiconductor layer toward the first surface portion side, and having a photoelectric conversion portion provided therein; and an element formation region partitioned by a shallow isolation region on the first surface portion side of the semiconductor layer, overlapping the deep isolation region in a planar view, and having a pixel transistor provided therein; wherein the shallow isolation region is inclined with respect to a center line passing through the center of the width of the deep isolation region in a vertical cross section crossing the deep isolation region, and is connected to the deep isolation region.

22. The photodetector device described in claim 21, wherein the element formation region is partitioned by a pair of shallow isolation regions aligned and spaced apart in a horizontal direction across the deep isolation region, and wherein, in a vertical cross section across the deep isolation region, one of the pair of shallow isolation regions is inclined to one side of a center line passing through the center of the width of the deep isolation region, and the other of the pair of shallow isolation regions is inclined to the other side of the center line, and at least one of the one shallow isolation region and the other shallow isolation region is connected to the deep isolation region.

23. A photodetector device according to claim 21 or 22, wherein the shallow isolation region extends from the first surface of the semiconductor layer towards the deep isolation region.

24. A photodetector device as described in claim 21 or 22, wherein the shallow isolation region includes a recessed portion provided on the first surface side of the semiconductor layer at an angle relative to the first surface, and an isolation insulating film provided inside the recessed portion.

25. The photodetector according to claim 21 or 22, wherein the shallow isolation region is a first shallow isolation region, and further comprising a second shallow isolation region provided on the first surface side of the semiconductor layer and overlapping the deep isolation region in a plan view.

26. The photodetector device described in claim 25, wherein the first shallow isolation region is provided on the first surface side of the semiconductor layer and is configured as an oblique trench type including a recessed portion extending obliquely relative to the first surface, and the second shallow isolation region is provided on the first surface side of the semiconductor layer and is configured as a vertical trench type including a recessed portion extending perpendicular to the first surface, or a diffusion isolation type in which impurities are diffused.

27. An electronic device comprising: a photodetector; an optical lens that focuses image light from a subject on an imaging surface of the photodetector; and a signal processing circuit that processes signals output from the photodetector, wherein the photodetector comprises: a semiconductor layer having a first surface portion and a second surface portion located opposite each other in one direction; a shallow isolation region provided on the first surface portion side of the semiconductor layer; an element formation region that is partitioned by the shallow isolation region on the first surface portion side of the semiconductor layer and has a pixel transistor provided therein; and a photoelectric conversion region that is partitioned by a deep isolation region extending from the second surface portion side of the semiconductor layer toward the first surface portion side and has a photoelectric conversion portion provided therein, wherein a portion of the deep isolation region that overlaps with the element formation region in a planar view protrudes toward the first surface side of the semiconductor layer beyond the bottom of the shallow isolation region.

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