Method for manufacturing coating layer and plasma-resistant member manufactured by same
A two-layer coating process using aerosol deposition and EB-PVD/IBAD enhances plasma resistance and bonding strength in semiconductor devices, addressing contamination issues from high-energy etching processes.
Patent Information
- Application Number
- PCT/KR2025/003842
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2024-04-26
- Filing Date
- 2025-03-26
- Publication Date
- 2025-10-30
AI Technical Summary
Semiconductor devices face challenges in plasma resistance due to increased demands for finer line widths and stacked packaging technologies, leading to device failures from contaminants generated during high-energy etching processes, which are exacerbated by surface roughness and chemical changes on internal components.
A method involving a two-layer coating process, where a first layer is formed using aerosol deposition (e.g., Al2O3, Y2O3, YSZ) and a second layer using EB-PVD or IBAD (e.g., Y2O3, YF3) with columnar crystals perpendicular to the surface, enhancing plasma resistance and bonding strength.
The method improves plasma resistance, hardness, and bonding strength of semiconductor device components, reducing contaminant generation and extending their lifespan and production yield.