Monitoring circuit and method for display module, and display apparatus

Abstract

The present disclosure relates to the technical field of display. Disclosed are a monitoring circuit and method for a display module, and a display apparatus. The display module comprises a display panel and a display circuit, the display circuit comprising a main controller, a first controller, a first power manager and a level converter, wherein an output end of the first controller is electrically connected to an input end of the level converter, the first controller is configured to output a display signal, which is required by the display panel, and the first power manager is configured to provide a voltage signal to the first controller. The monitoring circuit comprises a second controller, wherein an input end of the second controller is electrically connected to an output end of the first power manager, and is electrically connected to the output end of the first controller by means of the level converter, the second controller is configured to monitor the display state of the display panel on the basis of the display signal and / or the voltage signal, and an output end of the level converter is electrically connected to an input end of the display panel and the input end of the second controller. By means of the monitoring circuit, the technical difficulty and the cost for a user are reduced.

Description

Monitoring circuit and method for display module, and display device

[0001] Cross-reference to related applications

[0002] The present disclosure claims priority to Chinese Patent Application No. 202410544344.2, filed on April 30, 2024, entitled “Monitoring circuit and method for display module, and display device”, the entire contents of which are incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The present disclosure relates to the technical field of display, in particular, to a monitoring circuit and method for display module, and a display device comprising the monitoring circuit. BACKGROUND

[0004] Currently, whether the display screen is normal or abnormal cannot be found in time, which affects user experience; it may be necessary to directly view by human eyes or to judge by machine vision; directly viewing by human eyes requires staff to monitor at all times, which wastes a lot of human resources; judging by machine vision requires image acquisition and image processing, which requires additional equipment and has a high technical difficulty, increasing user cost.

[0005] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present disclosure, and therefore can include information that does not constitute prior art known to those of ordinary skill in the art. SUMMARY

[0006] The purpose of the present disclosure is to overcome the deficiencies of the prior art, and to provide a monitoring circuit and method for display module, and a display device comprising the monitoring circuit.

[0007] According to one aspect of the present disclosure, a monitoring circuit for a display module is provided, the display module comprising a display panel and a display circuit, the display circuit comprising a main controller, a first controller, a first power manager, and a level converter, an input end of the first controller being electrically connected to an output end of the first power manager and an output end of the main controller, an output end of the first controller being electrically connected to an input end of the level converter, the first controller being configured to output a display signal required by the display panel through the level converter according to an instruction of the main controller, the first power manager being configured to provide a voltage signal to the first controller; the monitoring circuit comprising:

[0008] a second controller, an input terminal of the second controller being electrically connected to an output terminal of the first power manager and electrically connected to an output terminal of the first controller through the level converter, the second controller being configured to monitor a display state of the display panel according to the display signal and / or the voltage signal, wherein an output terminal of the level converter is electrically connected to an input terminal of the display panel and an input terminal of the second controller.

[0009] In an exemplary embodiment of the present disclosure, the display module further comprises a backlight module, and the display circuit further comprises a backlight driving circuit, the backlight driving circuit being configured to provide a backlight signal to the backlight module, an output terminal of the backlight driving circuit being electrically connected to an input terminal of the second controller and an input terminal of the backlight module.

[0010] In an exemplary embodiment of the present disclosure, the monitoring circuit further comprises:

[0011] a signal processing circuit, the signal processing circuit comprising a first signal processing circuit, the first signal processing circuit being configured to process a direct-current digital voltage signal in the voltage signal, the first signal processing circuit comprising:

[0012] a first emitter follower unit, the first emitter follower unit being electrically connected to the output terminal of the first power manager, the first emitter follower unit being configured to collect the direct-current digital voltage signal in the voltage signal and prevent the direct-current digital voltage signal from flowing back to the display circuit;

[0013] a first analog-to-digital conversion unit, the first analog-to-digital conversion unit being electrically connected to an output terminal of the first emitter follower unit, and the second controller being electrically connected to an output terminal of the first analog-to-digital conversion unit, the second controller being configured to output the display state of the display panel as a first abnormal display state, in the first abnormal display state, the direct-current digital voltage signal has a first set value.

[0014] In an exemplary embodiment of the present disclosure, the first set value is less than 3.0V or greater than 3.6V.

[0015] In an exemplary embodiment of the present disclosure, the monitoring circuit further comprises:

[0016] a signal processing circuit, the signal processing circuit comprising a second signal processing circuit, the second signal processing circuit being configured to process a direct-current analog voltage signal in the voltage signal, the second signal processing circuit comprising:

[0017] a second emitter follower unit, the second emitter follower unit being electrically connected to the output terminal of the first power manager, the second emitter follower unit being configured to collect the direct-current analog voltage signal in the voltage signal and prevent the direct-current analog voltage signal from flowing back to the display circuit.

[0018] a second voltage dividing unit electrically connected to an output terminal of the second emitter follower unit, the second voltage dividing unit configured to adjust a value of the direct current analog voltage signal to a fixed voltage;

[0019] a second analog-digital converting unit electrically connected to an output terminal of the second voltage dividing unit;

[0020] the second controller electrically connected to an output terminal of the second analog-digital converting unit, the second controller configured to output a display state of the display panel as a second abnormal display state, in which the direct current analog voltage signal has a second set value.

[0021] In an exemplary embodiment of the present disclosure, the second set value is less than 15V or greater than 17V.

[0022] In an exemplary embodiment of the present disclosure, the monitoring circuit further comprises:

[0023] a signal processing circuit, the signal processing circuit comprising a third signal processing circuit configured to process a frame start signal in the display signal, the third signal processing circuit comprising:

[0024] a third emitter follower unit electrically connected to an output terminal of the level shifter, the third emitter follower unit configured to collect the frame start signal in the display signal and prevent the frame start signal from flowing back to the display circuit;

[0025] a third voltage dividing unit electrically connected to an output terminal of the third emitter follower unit, the third voltage dividing unit configured to adjust a voltage value of the frame start signal to a fixed voltage;

[0026] a first timing unit electrically connected to an output terminal of the third voltage dividing unit;

[0027] the second controller electrically connected to an output terminal of the first timing unit, the second controller configured to output a display state of the display panel as a third abnormal display state, in which a frequency of the frame start signal has a third set value.

[0028] In an exemplary embodiment of the present disclosure, the third set value is less than 58Hz or greater than 62Hz.

[0029] In an exemplary embodiment of the present disclosure, the monitoring circuit further comprises:

[0030] a signal processing circuit, the signal processing circuit comprising a fourth signal processing circuit configured to process a reset signal in the display signal, the fourth signal processing circuit comprising:

[0031] a fourth emitter follower unit electrically connected to an output terminal of the level converter, the fourth emitter follower unit configured to collect the reset signal in the display signal and prevent the reset signal from flowing back to the display circuit;

[0032] a fourth voltage dividing unit electrically connected to an output terminal of the fourth emitter follower unit, the fourth voltage dividing unit configured to adjust a voltage value of the reset signal to a fixed voltage;

[0033] a second timing unit electrically connected to an output terminal of the fourth voltage dividing unit;

[0034] the second controller is electrically connected to an output terminal of the second timing unit, the second controller configured to output a display state of the display panel as a fourth abnormal display state, in which the frequency of the reset signal has a fourth set value.

[0035] In an exemplary embodiment of the present disclosure, the fourth set value is less than 56 Hz or greater than 60 Hz, or the fourth set value is less than 1.5 kHz or greater than 1.9 kHz.

[0036] In an exemplary embodiment of the present disclosure, the monitoring circuit further comprises:

[0037] a signal processing circuit, the signal processing circuit comprising a plurality of fifth signal processing circuits configured to process a clock signal in the display signal, the fifth signal processing circuit comprising:

[0038] a fifth emitter follower unit electrically connected to an output terminal of the level converter, the fifth emitter follower unit configured to collect the clock signal in the display signal and prevent the clock signal from flowing back to the display circuit;

[0039] a fifth voltage dividing unit electrically connected to an output terminal of the fifth emitter follower unit, the fifth voltage dividing unit configured to adjust a voltage value of the clock signal to a fixed voltage;

[0040] a plurality of third timing units electrically connected to output terminals of the plurality of fifth voltage dividing units in a one-to-one correspondence;

[0041] The second controller is electrically connected to the output end of the plurality of third timing units; and the second controller is configured to output the display state of the display panel as a fifth abnormal display state, in which the frequency of the clock signal has a fifth set value.

[0042] In an exemplary embodiment of the present disclosure, the fifth set value is less than 22.5 kHz or greater than 22.9 kHz.

[0043] In an exemplary embodiment of the present disclosure, the monitoring circuit further comprises:

[0044] The signal processing circuit comprises a sixth signal processing circuit configured to process the cathode voltage signal in the backlight signal, and the sixth signal processing circuit comprises:

[0045] A sixth emitter follower unit electrically connected to the backlight driving circuit, configured to collect the cathode voltage signal in the backlight signal and prevent the cathode voltage signal from flowing back to the display circuit;

[0046] A third analog-to-digital conversion unit electrically connected to the output end of the sixth emitter follower unit;

[0047] The second controller is electrically connected to the output end of the third analog-to-digital conversion unit, and the second controller is configured to output the display state of the display panel as a sixth abnormal display state, in which the cathode voltage signal has a sixth preset value.

[0048] In an exemplary embodiment of the present disclosure, the sixth preset value is less than 0.25 V or greater than 0.5 V.

[0049] In an exemplary embodiment of the present disclosure, the monitoring circuit further comprises:

[0050] The signal processing circuit is configured to process the working signal, and the signal processing circuit comprises an emitter follower unit and a voltage dividing unit, the emitter follower unit is electrically connected to the output end of the display circuit, the voltage dividing unit is electrically connected to the output end of the emitter follower unit, the emitter follower unit is configured to collect the working signal and prevent the backflow of the working signal current, and the voltage dividing unit is configured to adjust the voltage of the working signal.

[0051] The working signal at least comprises any one of the voltage signal, the display signal and the backlight signal.

[0052] The second controller is configured to determine whether the voltage signal, the display signal and the backlight signal in the working signal are all normal, and determine that the display state of the display panel is a normal display state if yes.

[0053] In an exemplary embodiment of the present disclosure, the monitoring circuit further comprises:

[0054] A signal processing circuit configured to process the working signal, the signal processing circuit comprising an emitter follower unit and a voltage dividing unit, the emitter follower unit being electrically connected to an output end of the display circuit, the voltage dividing unit being electrically connected to an output end of the emitter follower unit, the emitter follower unit being configured to collect the working signal and prevent backflow of the working signal current, and the voltage dividing unit being configured to adjust the voltage of the working signal.

[0055] The working signal comprises at least any one of a direct current digital voltage signal and a direct current analog voltage signal in the voltage signal, a frame start signal, a reset signal and a clock signal in the display signal, and a cathode voltage signal in the backlight signal.

[0056] The second controller is configured to determine whether the working signal satisfies the following conditions, and determine that the display state of the display panel is a normal display state if yes: the direct current digital voltage signal is greater than or equal to 3.0V and less than or equal to 3.6V; the direct current analog voltage signal is greater than or equal to 15V and less than or equal to 17V; the frame start signal is greater than or equal to 58Hz and less than or equal to 62Hz; the reset signal is greater than or equal to 56Hz and less than or equal to 60Hz, or the reset signal is greater than or equal to 1.5kHz and less than or equal to 1.9kHz; the clock signal is greater than or equal to 22.5kHz and less than or equal to 22.9kHz; and the cathode voltage signal is greater than or equal to 0.25V and less than or equal to 0.5V.

[0057] In an exemplary embodiment of the present disclosure, the monitoring circuit further comprises:

[0058] A second power manager electrically connected to the signal processing circuit and the second controller, the second power manager being configured to supply power to the signal processing circuit and the second controller.

[0059] In an exemplary embodiment of the present disclosure, the monitoring circuit further comprises:

[0060] A second power manager electrically connected to the monitoring circuit, the second power manager being configured to supply power to the monitoring circuit.

[0061] In an exemplary embodiment of the present disclosure, at least part of the monitoring circuit and at least part of the display circuit are arranged on the same circuit board.

[0062] In an exemplary embodiment of the present disclosure, the display circuit further comprises:

[0063] a backlight driving controller, an output end of the backlight driving controller being electrically connected to an input end of the second controller and an input end of the backlight module, the backlight driving controller being configured to output a second error identification signal or a backlight signal according to a working state of the backlight driving controller;

[0064] an input end of the second controller being electrically connected to an output end of the backlight driving controller and electrically connected to an output end of the first controller through the level converter, the second controller being configured to determine the display state of the display panel by judging whether the first error identification signal and / or the second error identification signal is received.

[0065] In an exemplary embodiment of the present disclosure, the display module further comprises a backlight module, and the display circuit further comprises a backlight driving controller, an output end of the backlight driving controller being electrically connected to an input end of the second controller and an input end of the backlight module;

[0066] the backlight driving controller being configured to output a second error identification signal or a backlight signal according to a working state of the backlight driving controller, and the first controller being configured to output a display signal required by the display panel or a first error identification signal according to a working state of the level converter;

[0067] an input end of the second controller being electrically connected to an output end of the backlight driving controller and electrically connected to an output end of the first controller through the level converter, the second controller being configured to determine the display state of the display panel by judging whether the first error identification signal and / or the second error identification signal is received.

[0068] According to still another aspect of the present disclosure, there is provided a monitoring circuit of a display module, the display module comprising a backlight module, a display panel and a display circuit, the display circuit comprising a main controller, a first controller, a backlight driving controller and a level converter, an input end of the first controller being electrically connected to an output end of the main controller, an output end of the first controller being electrically connected to an input end of the level converter, an output end of the backlight driving controller being electrically connected to an input end of the backlight module; the first controller being configured to output a display signal required by the display panel or a first error identification signal according to a working state of the level converter, and the backlight driving controller being configured to output a second error identification signal or a backlight signal according to a working state of the backlight driving controller.

[0069] The monitoring circuit comprises:

[0070] A second controller, an input end of the second controller being electrically connected to an output end of the backlight drive controller and being electrically connected to an output end of the first controller through the level converter, the second controller being configured to determine the display state of the display panel by determining whether the first error identification signal and / or the second error identification signal is received.

[0071] According to another aspect of the present disclosure, a monitoring method of a display module is provided, which is used for the monitoring circuit described in any one of the above, and the monitoring method comprises:

[0072] The display signal and / or the voltage signal of the display circuit are collected, and it is determined whether the display panel displays normally and the abnormal type of abnormal display according to the display signal and / or the voltage signal, and the determination result is outputted.

[0073] In an exemplary embodiment of the present disclosure, the display signal and / or the voltage signal of the display circuit are collected, and it is determined whether the display panel displays normally and the abnormal type of abnormal display according to the display signal and / or the voltage signal, comprising:

[0074] The direct-current digital voltage signal and the direct-current analog voltage signal in the voltage signal are collected;

[0075] If the voltage of the direct-current digital voltage signal satisfies a first preset value, and the voltage of the direct-current analog voltage signal satisfies a second preset value, it is determined that the voltage is normal and outputted;

[0076] If the voltage of the direct-current digital voltage signal does not satisfy the first preset value, and / or, the voltage of the direct-current analog voltage signal does not satisfy the second preset value, it is determined that the voltage is abnormal and outputted.

[0077] In an exemplary embodiment of the present disclosure, the display signal and / or the voltage signal of the display circuit are collected, and it is determined whether the display panel displays normally and the abnormal type of abnormal display according to the display signal and / or the voltage signal, further comprising:

[0078] After it is determined that the voltage is normal, the frame start signal, the reset signal and the plurality of clock signals of the display signal are collected;

[0079] If the frequency of the frame start signal satisfies a third preset value, the frequency of the reset signal satisfies a fourth preset value, and the frequency of the plurality of clock signals satisfies a fifth preset value, it is determined that the driving is normal and outputted;

[0080] If the frequency of the frame start signal does not satisfy a third preset value, and / or the frequency of the reset signal does not satisfy a fourth preset value, and / or the frequency of the plurality of clock signals does not satisfy a fifth preset value, it is determined that the driving is abnormal and output.

[0081] In an exemplary embodiment of the present disclosure, the monitoring method further comprises:

[0082] After determining that the voltage is normal, a first error identification signal of the display circuit is collected; if the first error identification signal is collected, it is determined that the driving is abnormal and output.

[0083] In an exemplary embodiment of the present disclosure, the monitoring method further comprises:

[0084] A backlight signal or a second error identification signal of the display circuit is collected, and whether the display panel is normally displayed and the abnormal type of abnormal display is determined according to the backlight signal or the second error identification signal, and the determination result is output.

[0085] In an exemplary embodiment of the present disclosure, a backlight signal or a second error identification signal of the display circuit is collected, and whether the display panel is normally displayed and the abnormal type of abnormal display is determined according to the backlight signal or the second error identification signal, and the determination result is output.

[0086] The cathode voltage signal in the backlight signal is collected at the same time as the voltage signal is collected;

[0087] If the cathode voltage signal satisfies a sixth preset value, it is determined that the backlight is normal; if the cathode voltage signal does not satisfy the sixth preset value, it is determined that the backlight is abnormal and output;

[0088] Alternatively, the second error identification signal is collected at the same time as the voltage signal is collected;

[0089] If the second error identification signal is collected, it is determined that the backlight is abnormal and output; if the second error identification signal is not collected, it is determined that the backlight is normal.

[0090] In an exemplary embodiment of the present disclosure, the monitoring method further comprises:

[0091] The refresh rate of the built-in self-test display mode is set to a set value different from the refresh rate of normal display, after determining that the voltage is normal, a frame start signal is collected, if the frame start signal is equal to the set value, it is determined that the built-in self-test is abnormal due to the abnormality of the supply signal and output; if the frame start signal is not equal to the set value, it is determined that the built-in self-test is normal.

[0092] In one example embodiment of the present disclosure, when it is determined that the voltage is normal, the built-in self-test is normal, the driving is normal, and the backlight is normal, a display normality is output.

[0093] According to still another aspect of the present disclosure, there is provided a display device, comprising:

[0094] The display module comprises a display panel and a display circuit.

[0095] The monitoring circuit is electrically connected to the display circuit.

[0096] It should be understood that the foregoing general description and the following detailed description are only exemplary and explanatory, and are not limiting to the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0097] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments consistent with the present disclosure and serve to explain the principles of the present disclosure. It is apparent that the accompanying drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0098] FIG. 1 is a structural schematic diagram of an example embodiment of a display module.

[0099] FIG. 2 is a structural schematic diagram of a monitoring circuit and a display module of the present disclosure.

[0100] FIG. 3 is a connection structural schematic diagram of a monitoring circuit and a display circuit of an example embodiment of the present disclosure.

[0101] FIG. 4 is a structural schematic diagram of a signal processing circuit and a processor of an example embodiment of the monitoring circuit of the present disclosure.

[0102] FIG. 5 is a circuit structural schematic diagram of a first signal processing circuit, a second signal processing circuit, and a sixth signal processing circuit in FIG. 4.

[0103] FIG. 6 is a circuit structural schematic diagram of a third signal processing circuit and a fourth signal processing circuit in FIG. 4.

[0104] FIG. 7 is a circuit structural schematic diagram of two fifth signal processing circuits in FIG. 4.

[0105] FIG. 8 is a connection structural schematic diagram of a monitoring circuit and a display circuit of another example embodiment of the present disclosure.

[0106] FIG. 9 is a structural schematic diagram of a signal processing circuit and a processor of another example embodiment of the monitoring circuit of the present disclosure.

[0107] FIG. 10 is a flowchart of a monitoring method of a display module according to an embodiment of the disclosure.

[0108] BRIEF DESCRIPTION OF DRAWINGS 1, display circuit; PMIC1, first power manager; TCON, first controller; LSIC, level shifter; BLU-Con, backlight converter; LED-D, backlight drive controller; 2, signal processing circuit; 21, first signal processing circuit; 211, first emitter follower unit; 22, second signal processing circuit; 221, second emitter follower unit; 222, second voltage dividing unit; 23, third signal processing circuit; 231, third emitter follower unit; 232, third voltage dividing unit; 24, fourth signal processing circuit; 241, fourth emitter follower unit; 242, fourth voltage dividing unit; 25, fifth signal processing circuit; 251, fifth emitter follower unit; 252, fifth voltage dividing unit; 26, sixth signal processing circuit; 261, sixth emitter follower unit; 27, seventh signal processing circuit; 271, seventh emitter follower unit; 272, seventh voltage dividing unit; MCU, processor; ADC1, first analog-digital conversion unit; ADC2, second analog-digital conversion unit; ADC3, third analog-digital conversion unit; Timer1, first timing unit; Timer2, second timing unit; Timer3, third timing unit; CPU, second controller; GPIO1, first input port; GPIO2, second input port; PMIC2, second power manager; 3, display panel; 31, backlight module; 32, array substrate; 33, liquid crystal layer; 34, color filter substrate; 351, first printed circuit board; 352, second printed circuit board. DETAILED DESCRIPTION

[0109] Example embodiments now will be described more fully hereinafter with reference to the accompanying drawings. Example embodiments, however, can be implemented in many different forms and should not be construed as limited to the implementations set forth herein; rather, these implementations are provided so that this disclosure will be thorough and complete, and will fully convey the scope of example embodiments to those skilled in the art. Like reference numerals refer to like elements throughout the figures, and descriptions of the same elements will be omitted from descriptions of subsequent figures. In addition, the drawings are only schematic and the dimensions are not necessarily to scale.

[0110] Although relative terms are used in this description, such as "upper," "lower," to describe one component's relationship to another component, these terms are used herein for convenience only and are not intended to be limiting. It is to be understood that, when a part is referred to as being "on" or "under" another part, it can be directly on or under the other part, or intervening parts can be present. When a part is "on" or "under" another part in an assembly, it can be directly connected to the other part or "indirectly" connected through one or more intervening parts.

[0111] The terms "one," "a," "an," "the" and "at least one" are used interchangeably to mean that "one or more" of the referenced component(s) are present; the terms "comprises," "comprising," "includes," "including," and the like can mean "including without limitation," as the term "comprising," when used in a claim, should not be interpreted as limiting the number or range of components in the claim; and the terms "first," "second," and "third," and the like, merely mean "one," "two," or "three" and the like, respectively, and are not intended to limit one claim over another.

[0112] In the present application, unless specifically stated and limited otherwise, the term "connected" shall be understood broadly, for example, "connected" can be fixed connection, or detachable connection, or integral; can be directly connected, or indirectly connected through intermediate medium. "And / or", is only a description of the relationship between the associated objects, which means that there can be three kinds of relationships, for example, A and / or B, which can represent: A exists alone, A and B exist together, B exists alone. In addition, the character " / " in this paper generally represents that the front and rear associated objects are a "or" relationship.

[0113] The inventors found through experiments and investigations that the main cause of display module failure is that the first power manager PMIC1, the logic board, and the chip on film binding are directly related. Among them, the first power manager PMIC1 and the logic board account for a high proportion, and the main display failure is logic board input signal or receiving related black screen abnormality, first power manager PMIC1 voltage abnormality related black screen abnormality, and gate drive circuit (GOA: Gate Driver On Array) related picture abnormality.

[0114] The display module monitoring circuit provided by the example embodiments of the present disclosure can include a display panel 3 and a display circuit 1, the display circuit 1 can include a main controller, a first controller TCON, a first power manager PMIC1, and a level converter LSIC, an input end of the first controller TCON is electrically connected to an output end of the first power manager PMIC1 and an output end of the main controller, an output end of the first controller TCON is electrically connected to an input end of the level converter LSIC, the first controller TCON is configured to output a display signal required by the display panel 3 through the level converter LSIC according to an instruction of the main controller, the first power manager PMIC1 is configured to provide a voltage signal for the first controller TCON; the monitoring circuit can include a second controller CPU, an input end of the second controller CPU is electrically connected to the output end of the first power manager PMIC1 and the output end of the first controller TCON through the level converter LSIC, the second controller CPU is configured to monitor a display state of the display panel 3 according to the display signal and / or the voltage signal, and an output end of the level converter LSIC is electrically connected to an input end of the display panel 3 and an input end of the second controller CPU.

[0115] The display module monitoring circuit of the present disclosure, the second controller CPU monitors the display state of the display panel 3 according to the display signal and / or the voltage signal, without the need to observe whether the display module displays normally through the human eye, avoiding the waste of human resources, and without the need to determine whether the display is normal through machine vision, avoiding image processing, reducing the technical difficulty and user cost; and the judgment result is output, so that the user can directly know the abnormal type of abnormal display, facilitating subsequent maintenance.

[0116] In the example embodiments, referring to FIG. 1, the display panel 3 can be a liquid crystal display panel 3, the display panel 3 can include an array substrate 32, a color film substrate 34, and a liquid crystal layer 33 disposed between the array substrate 32 and the color film substrate 34. The display module can further include a backlight module 31.

[0117] The backlight module 31 can include a plurality of backlight sources arranged in an array, the backlight source can be an LED (Light-Emitting Diode). The backlight module 31 can be provided as only one partition, that is, the plurality of backlight sources of the backlight module 31 are uniformly controlled, and the voltage input to the plurality of backlight sources is substantially the same, so that the luminous brightness of the plurality of backlight sources of the backlight module 31 is substantially the same.

[0118] For the backlight module 31 of Local Dimming, the backlight source can be adjusted according to the brightness of the image, so that the brightness of the highlighted part of the display image can reach the maximum, while the dark part can reduce the brightness, or even be turned off, to achieve the best contrast. In this way, the reduction of dark area brightness reduces the power consumption of the backlight. Therefore, the backlight module 31 can also be provided as two partitions, three partitions or more partitions, and the multiple backlight sources in the same partition are controlled uniformly, that is, the voltage input to the multiple backlight sources in the same partition is basically the same, so that the luminous brightness of the multiple backlight sources in the same partition is basically the same.

[0119] The display panel 3 has a display area and a non-display area surrounding the periphery of the display area. In the display area, the array substrate 32 can include a plurality of pixel circuits arranged in an array. The pixel circuit can include a transistor and a pixel electrode. The transistor can include a gate, a source and a drain. The gate of the transistor is connected to a corresponding gate line, the source of the transistor is connected to a corresponding data line, and the drain of the transistor is connected to the pixel electrode. A common electrode is also provided in the display area. The common electrode can be located on the array substrate 32 or on the color film substrate 34.

[0120] The signal loaded by the gate line controls the conduction of the transistor, so as to write the data voltage provided by the data line to the corresponding pixel electrode. An electric field can be formed between the pixel electrode and the common electrode to drive the liquid crystal molecules in the corresponding area to deflect, thereby realizing gray scale control. In order to accurately control the gray scale displayed by the sub-pixel, it is necessary to accurately write the data voltage provided by the data line to the pixel electrode of the sub-pixel.

[0121] A gate drive circuit (GOA: Gate Driver On Array) is provided in the non-display area of the array substrate 32. The gate drive circuit can include a plurality of cascaded shift registers. The signal output end of each stage of shift registers is connected to a corresponding gate line to provide a display signal to the corresponding gate line. The display signal provided by the gate drive circuit controls the gate switching of different rows of transistors. The data signal provided by the source drive chip (Source Driver IC) is sent to the source of different columns of transistors. When the scanning line signal turns on the transistor, the signal line charges the liquid crystal and the storage capacitor from the source, and saves the data; when the scanning line signal turns off the transistor, the high impedance ROFF cuts off the loop to prevent the data from being changed.

[0122] Referring to FIG. 2, the display module can be a 1920x360 rail transit strip screen. The display module can further include a first printed circuit board 351 on which a part of a display circuit 1 and are disposed. The display circuit 1 can include a backlight driving circuit, a main controller, a first controller TCON (Timing controller, Tcon), a first power manager PMIC1 (Power Management IC, PMIC), a level shifter LSIC, a capacitor, a resistor element, and the like. The main controller can be a SoC (System on Chip) motherboard, and the first power manager PMIC1 supplies power to other components of the display circuit 1. The first printed circuit board 351 can be a logic board on which the first power manager PMIC1, the first controller TCON, and the level shifter LSIC are disposed.

[0123] The first printed circuit board 351 can be connected to a left X-printed circuit board assembly XPCBA-L (X-printed circuit board assembly) and a right X-printed circuit board assembly XPCBA-R through two flexible printed circuit boards FPCB. The left X-printed circuit board assembly XPCBA-L and the right X-printed circuit board assembly XPCBA-R are coupled to conductive connection terminals on the array substrate 32 in the bonding area through two chip on film COF (a total of four chip on film COF), respectively. The input end of the first printed circuit board 351 is electrically connected to the SoC motherboard. Specifically, the input end of the first controller TCON is electrically connected to the output end of the first power manager PMIC1 and the output end of the main controller, and the first controller TCON is configured to output the display signal required by the display panel 3 through the level shifter LSIC according to the instruction of the main controller. The output end of the first printed circuit board 351 is connected to a source driver IC SDIC (Source Driver IC) and a gate driving circuit, realizing signal input to the pixel circuit. The source driver IC SDIC can be disposed on the chip on film COF, and a total of four source driver ICs SDIC are disposed. The display module can also be other structures, which are not described one by one here.

[0124] Referring to FIG. 2, the display circuit can further include a backlight driving circuit. Specifically, the display module can further include a second printed circuit board 352, which can be a cross-flow board. The backlight driving circuit is disposed on the second printed circuit board 352 and configured to provide a backlight signal to the backlight module 31. The output end of the backlight driving circuit is electrically connected to the input end of the second controller CPU and the backlight module 31. The backlight driving circuit can include a backlight converter BLU-Con. The second printed circuit board 352 can be electrically connected to the first printed circuit board 351 by a wire, so that the backlight driving circuit on the second printed circuit board 352 can be electrically connected to the monitoring circuit. Moreover, the backlight driving circuit is electrically connected to the backlight module 31, and the control of the backlight module 31 is realized by the backlight driving circuit. For example, the backlight driving circuit can be electrically connected to the backlight module 31 through the first printed circuit board 351.

[0125] At least part of the monitoring circuit and at least part of the display circuit 1 are disposed on the same circuit board. Referring to FIG. 2, in the example embodiment, the monitoring circuit is also disposed on the first printed circuit board 351. Specifically, the signal processing circuit 2, the processor MCU, and the second power manager PMIC2 are disposed on the first printed circuit board 351. That is, the signal processing circuit 2, the processor MCU, and the second power manager PMIC2 are disposed on the same first printed circuit board 351 as the first power manager PMIC1, the first controller TCON, and the level converter LSIC. Of course, in some other example embodiments of the disclosure, the signal processing circuit 2, the processor MCU, and the second power manager PMIC2 can also be separately disposed on another monitoring printed circuit board. The monitoring printed circuit board and the first printed circuit board 351 can be electrically connected by binding, or can be electrically connected by a chip on film or a flexible circuit board.

[0126] Referring to FIG. 3, the first controller TCON converts a video signal transmitted from a main controller (SOC mainboard) into a data signal format required by a data driving circuit, for example, converts LVDS (Low Voltage Differential Signaling) into RSDS (Reduced Swing Differential Signaling), or converts into Mini-LVDS (Mini Low Voltage Differential Signaling), and then connects to an array substrate through a Mini-LVDS connector of a left X-printed circuit board assembly XPCBA-L and a right X-printed circuit board assembly XPCBA-R, for data driving of a display module, and also provides a display signal for a gate and a source.

[0127] The main controller (SOC mainboard) provides a 12V power voltage (VDD) for the first power manager PMIC1 and the second power manager PMIC2. Moreover, the processor MCU can output a judgment result to the main controller (SOC mainboard).

[0128] In the example embodiment, the monitoring circuit can further include a signal processing circuit 2 electrically connected between a display circuit 1 of the display module and the processor MCU, the signal processing circuit 2 being configured to process a working signal, the signal processing circuit 2 can include an emitter follower unit and a voltage dividing unit, the emitter follower unit being electrically connected to an output end of the display circuit, the voltage dividing unit being electrically connected to an output end of the emitter follower unit, the emitter follower unit being configured to collect the working signal and prevent backflow of a working signal current, the voltage dividing unit being configured to adjust a voltage of the working signal; the working signal at least including any one of a voltage signal, a display signal, and a backlight signal; so that the signal processing circuit 2 is used to collect any one of the voltage signal, the display signal, and the backlight signal of the display circuit 1.

[0129] The working signal at least includes any one of a direct current digital voltage signal DVDD and a direct current analog voltage signal AVDD in the voltage signal, a frame start signal STV1, a reset signal STV2, and a clock signal CLK in the display signal, and a cathode voltage signal LED- in the backlight signal.

[0130] In the example embodiment, the voltage signals can include direct-current analog voltage signals and direct-current digital voltage signals. For example, generally, the voltage signals can be direct-current voltage signals, and the voltage signals can include direct-current analog voltage signals AVDD, direct-current digital voltage signals DVDD, gate drive high level VGH, gate drive low level VGL, analog working half voltage HAVDD, reference voltage VCOM, correction voltage Gamma, and the like. If all the voltage signals are detected, seven signal processing circuits need to be set, and the processor MCU also needs to select a chip with more interfaces, which can cause a substantial increase in hardware costs and increase the area occupied by the first printed circuit board 351. Since the direct-current analog voltage signals AVDD and the direct-current digital voltage signals DVDD are the basic voltages for generating the gate drive high level VGH, the gate drive low level VGL, the analog working half voltage HAVDD, the reference voltage VCOM, and the correction voltage Gamma, that is, the direct-current analog voltage signals AVDD and the direct-current digital voltage signals DVDD are the sources of other voltages. If the direct-current analog voltage signals AVDD and the direct-current digital voltage signals DVDD are abnormal, the other voltages are also abnormal. If the direct-current analog voltage signals AVDD and the direct-current digital voltage signals DVDD are normal, the other voltages are also normal under normal circumstances. Therefore, monitoring the direct-current analog voltage signals AVDD and the direct-current digital voltage signals DVDD can achieve monitoring of the first power manager PMIC1 of the display module, and the processor MCU does not need to select a chip with more interfaces, the hardware cost will not substantially increase, and the area occupied by the first printed circuit board 351 will not substantially increase.

[0131] Of course, in some other example embodiments of the present disclosure, for example, in the case of high monitoring requirements, the voltage signals can include one, two, or more of the direct-current analog voltage signals AVDD, the direct-current digital voltage signals DVDD, the gate drive high level VGH, the gate drive low level VGL, the analog working half voltage HAVDD, the reference voltage VCOM, and the correction voltage Gamma, which are not described one by one here.

[0132] In this case, as shown in FIG. 3, since the connection lines in the figure intersect, the black dots at the intersection positions are cross connections, and the black dots at the intersection positions are only intersections without connections. The signal processing circuit 2 is electrically connected to the output end of the first power manager PMIC1 for collecting the direct-current analog voltage signals AVDD. The signal processing circuit 2 is also electrically connected to the output end of the first power manager PMIC1 for collecting the direct-current digital voltage signals DVDD.

[0133] Specifically, referring to FIG. 4, the signal processing circuit 2 can include a first signal processing circuit 21 and a second signal processing circuit 22. The first signal processing circuit 21 is configured to process the direct-current digital voltage signal DVDD in the voltage signal. The second signal processing circuit 22 is configured to process the direct-current analog voltage signal AVDD in the voltage signal.

[0134] The first signal processing circuit 21 can include a first emitter follower unit 211 electrically connected to the output end of the first power manager PMIC1, and the first emitter follower unit 211 is configured to collect the direct-current digital voltage signal DVDD output by the first power manager PMIC1, i.e., the first emitter follower unit 211 is configured to collect the direct-current digital voltage signal DVDD and prevent the direct-current digital voltage signal DVDD from flowing back to the display circuit 1. Since the processor MCU can only withstand a voltage of 0-3.3V, and the direct-current digital voltage signal DVDD is about 3.3V, the direct-current digital voltage signal DVDD can be directly connected to the processor MCU, i.e., the output end of the first signal processing circuit 21 is directly electrically connected to the input end of the processor MCU.

[0135] The second signal processing circuit 22 can include a second emitter follower unit 221 and a second voltage dividing unit 222, the second emitter follower unit 221 is electrically connected to the output end of the first power manager PMIC1, and the second emitter follower unit 221 is configured to collect the direct-current analog voltage signal AVDD in the voltage signal, i.e., the second emitter follower unit 221 is configured to collect the direct-current analog voltage signal AVDD in the voltage signal and prevent the direct-current analog voltage signal AVDD from flowing back to the display circuit 1. Since the processor MCU can only withstand a voltage of 0-3.3V, and the direct-current analog voltage signal AVDD is about 16V, the direct-current analog voltage signal AVDD cannot be directly connected to the processor MCU and needs to be connected to the processor MCU after being divided by the second voltage dividing unit 222; therefore, the second voltage dividing unit 222 is electrically connected to the output end of the second emitter follower unit 221, and the second voltage dividing unit 222 is configured to adjust the voltage value of the direct-current analog voltage signal AVDD to be within a first required range, i.e., the second voltage dividing unit 222 is configured to adjust the voltage value of the direct-current analog voltage signal AVDD to be a fixed voltage.

[0136] It should be noted that the adjustment of the second voltage dividing unit 222 to the direct-current analog voltage signal AVDD can be proportional adjustment, and generally the maximum value is less than 3.3V. In the case where the voltage value of the direct-current analog voltage signal AVDD is a certain value, the adjusted value is a fixed voltage. Of course, the voltage value of the direct-current analog voltage signal AVDD is different, and the adjusted voltage value will also change. In the present disclosure, the fixed voltage is a voltage that the processor MCU can accept, for example, the fixed voltage is greater than or equal to 0 and less than or equal to 3.3V.

[0137] In the present example embodiment, the display signals can include a frame start signal STV1, a reset signal STV2, and a plurality of clock signals CLK. Since the gate driving circuit is arranged in the array substrate 32, if the output signals from the output end of the gate driving circuit are led out to the first printed circuit board 351 for detection, the difficulty of arranging the display panel 3 and the manufacturing cost are increased, and the output signals of the gate driving circuit are generated by the input control signals, and the input control signals of the gate driving circuit are generated on the first printed circuit board 351. Therefore, the input control signals of the gate driving circuit, i.e. the frame start signal STV1, the reset signal STV2, and the plurality of clock signals CLK1-6 of the gate driving circuit can be monitored. The frame start signal STV1 and the reset signal STV2 are fixed frequency pulse signals, and the clock signals CLK1-6 are fixed frequency square wave signals, and the monitoring of the frequencies thereof can realize the monitoring of the display signals of the display module, and further realize the monitoring of the display state of the display panel 3.

[0138] Of course, in some other example embodiments of the present disclosure, the output signals of the gate driving circuit can also be detected.

[0139] In this case, referring to FIG. 3, the first controller TCON generates the frame start signal STV1, the reset signal STV2, and the plurality of clock signals CLK1-6 and transmits them to the level shifter LSIC, which inputs them to the gate driving circuit. Therefore, referring to FIG. 4, the signal processing circuit 2 is electrically connected to the output end of the level shifter LSIC for collecting the frame start signal STV1, the reset signal STV2, and the plurality of clock signals CLK1-6; and the second controller CPU is electrically connected to the first controller TCON through the level shifter LSIC to receive the electrical signals (the frame start signal STV1, the reset signal STV2, and the plurality of clock signals CLK1-6) of the first controller TCON.

[0140] Specifically, the signal processing circuit 2 can include a third signal processing circuit 23, a fourth signal processing circuit 24, and a plurality of fifth signal processing circuits 25. The third signal processing circuit 23 is configured to process the frame start signal STV1 in the display signals, the fourth signal processing circuit 24 is configured to process the reset signal STV2 in the display signals, and the fifth signal processing circuit 25 is configured to process the clock signal CLK in the display signals.

[0141] The third signal processing circuit 23 can include a third emitter follower unit 231 and a third voltage dividing unit 232. The third emitter follower unit 231 is electrically connected to the output end of the level shifter LSIC, and is configured to collect the frame start signal STV1 in the display signal and prevent the frame start signal STV1 from flowing back to the display circuit 1. Since the processor MCU can only withstand a voltage of 0-3.3V, although the frame start signal STV1 is a fixed frequency pulse signal, it is realized by voltage jump. Therefore, in the case that the high level of the frame start signal STV1 is high, the processor MCU cannot be directly connected, and the third voltage dividing unit 232 is needed to divide the voltage before connecting to the processor MCU. Therefore, the third voltage dividing unit 232 is electrically connected to the output end of the third emitter follower unit 231, and is configured to adjust the voltage value of the frame start signal STV1 to a second required range, i.e., the third voltage dividing unit 232 is configured to adjust the voltage value of the frame start signal to a fixed voltage. Moreover, the third voltage dividing unit 232 does not affect the frequency of the frame start signal STV1 during the adjustment of the voltage value of the frame start signal STV1.

[0142] It should be noted that the adjustment of the voltage value of the frame start signal STV1 by the third voltage dividing unit 232 can be proportional adjustment. Generally, the maximum value is less than 3.3V. In the case that the voltage value of the frame start signal STV1 is a certain value, the adjusted value is a fixed voltage. Of course, the voltage value of the frame start signal STV1 is different, and the adjusted voltage value will also change.

[0143] The fourth signal processing circuit 24 can include a fourth emitter follower unit 241 and a fourth voltage dividing unit 242. The fourth emitter follower unit 241 is electrically connected to the output end of the level shifter LSIC, and is configured to collect the reset signal STV2 in the display signal and prevent the reset signal STV2 from flowing back to the display circuit 1. Since the processor MCU can only withstand a voltage of 0-3.3V, although the reset signal STV2 is a fixed frequency pulse signal, it is realized by voltage jump. Therefore, in the case that the high level of the reset signal STV2 is high, the processor MCU cannot be directly connected, and the processor MCU needs to be connected after being divided by the fourth voltage dividing unit 242. Therefore, the fourth voltage dividing unit 242 is electrically connected to the output end of the fourth emitter follower unit 241, and is configured to adjust the voltage value of the reset signal STV2 to a third required range, i.e., to a fixed voltage. Moreover, the fourth voltage dividing unit 242 does not affect the frequency of the reset signal STV2 during the adjustment of the voltage value of the reset signal STV2.

[0144] It should be noted that the adjustment of the voltage value of the reset signal STV2 by the fourth voltage dividing unit 242 can be proportional adjustment. Generally, the maximum value is less than 3.3V. In the case that the voltage value of the reset signal STV2 is a certain value, the adjusted value is a fixed voltage. Of course, the voltage value of the reset signal STV2 is different, and the adjusted voltage value will also change.

[0145] The fifth signal processing circuit 25 includes a fifth emitter follower unit 251 and a fifth voltage dividing unit 252. The fifth emitter follower unit 251 is electrically connected to the output end of the level shifter LSIC, and is configured to collect the clock signal CLK in the display signal and prevent the clock signal CLK from flowing back to the display circuit 1. Since the processor MCU can only withstand a voltage of 0-3.3V, and the clock signal CLK is about -4V-32V, the clock signal CLK cannot be directly connected to the processor MCU, and needs to be connected to the processor MCU after being divided by the fifth voltage dividing unit 252. Therefore, the fifth voltage dividing unit 252 is electrically connected to the output end of the fifth emitter follower unit 251, and is configured to adjust the voltage value of the clock signal CLK to a fourth required range, i.e., to a fixed voltage. Moreover, the fifth voltage dividing unit 252 does not affect the frequency of the clock signal CLK during the adjustment of the voltage value of the clock signal CLK.

[0146] It should be noted that the voltage value adjustment of the fifth voltage dividing unit 252 to the clock signal CLK can be proportional adjustment, and generally the minimum value is greater than 0V and the maximum value is less than 3.3V. In the case of a certain voltage value of the clock signal CLK, the adjusted value is a fixed voltage. Of course, the voltage value of the clock signal CLK is different, and the adjusted voltage value will also change.

[0147] The number of the fifth signal processing circuit 25 can be set according to the number of the clock signal CLK. The number of the fifth signal processing circuit 25 is equal to the number of the clock signal CLK, and one fifth signal processing circuit 25 collects one clock signal CLK. For example, in the case of six clock signals CLK, six fifth signal processing circuits 25 can be set. In the case of ten clock signals CLK, ten fifth signal processing circuits 25 can be set. In FIG. 4, only two fifth signal processing circuits 25 are shown, and the middle part is replaced by an ellipsis.

[0148] In the present example embodiment, the backlight signal can include the cathode voltage signal LED- of each sub-region of the backlight module 31. Since the cathode voltage signals LED- in the same sub-region are the same, for example, in the case of the backlight module 31 being set as only one sub-region, the backlight signal can be one cathode voltage signal LED-. In the case of the backlight module 31 being set as two sub-regions, the backlight signal can be two cathode voltage signals LED-. Similarly, in the case of the backlight module 31 being set as three or more sub-regions, the backlight signal can be three or more cathode voltage signals LED-.

[0149] In this case, the signal processing circuit 2 is electrically connected to the backlight driving circuit of the backlight module 31, and is used to collect the cathode voltage signal LED- of each sub-region.

[0150] Specifically, referring to FIG. 4, the signal processing circuit 2 can include a sixth signal processing circuit 26, which is configured to process the cathode voltage signal LED- in the backlight signal.

[0151] The sixth signal processing circuit 26 can include a sixth emitter follower unit 261 electrically connected to the backlight driving circuit of the backlight module 31, specifically, the sixth emitter follower unit 261 is electrically connected to the backlight converter BLU-Con of the backlight driving circuit of the backlight module 31. The sixth emitter follower unit 261 is configured to collect the cathode voltage signal LED- of each sub-zone of the backlight module 31, that is, the sixth emitter follower unit 261 is configured to collect the cathode voltage signal LED- in the backlight signal and prevent the cathode voltage signal LED- from flowing back to the display circuit 1. Since the cathode voltage signal LED- is usually less than 1V, the cathode voltage signal can be directly connected to the processor MCU, that is, the output end of the sixth signal processing circuit 26 is directly electrically connected to the input end of the processor MCU.

[0152] The number of the sixth signal processing circuit 26 can be set according to the number of the cathode voltage signals, that is, the number of the sixth signal processing circuit 26 can be equal to the number of the sub-zones of the backlight module 31. For example, when the backlight module 31 is provided with two sub-zones, two sixth signal processing circuits 26 are needed to correspondingly collect the cathode voltage signals of the two sub-zones; when the backlight module 31 is provided with three or more sub-zones, three or more sixth signal processing circuits 26 are needed to correspondingly collect the cathode voltage signals of the three or more sub-zones.

[0153] The monitoring circuit can further include a first analog-to-digital conversion unit ADC1, a second analog-to-digital conversion unit ADC2, a third analog-to-digital conversion unit ADC3, a first timing unit Timer1, a second timing unit Timer2, a second controller CPU, and a plurality of third timing units Timer3. In the example embodiment, referring to FIG. 4, the first analog-to-digital conversion unit ADC1, the second analog-to-digital conversion unit ADC2, the third analog-to-digital conversion unit ADC3, the first timing unit Timer1, the second timing unit Timer2, the second controller CPU, and the plurality of third timing units Timer3 can be included in the processor MCU. Of course, in some other example embodiments of the present disclosure, the first analog-to-digital conversion unit ADC1, the second analog-to-digital conversion unit ADC2, the third analog-to-digital conversion unit ADC3, the first timing unit Timer1, the second timing unit Timer2, the second controller CPU, and the plurality of third timing units Timer3 can also be separately provided as one component, respectively; and one, two or more of them can be selected according to different signals to be monitored.

[0154] The first analog-to-digital conversion unit ADC1 is electrically connected to the output end of the first emitter follower unit 211, and is configured to convert the direct-current digital voltage signal DVDD into a digital signal. The second controller CPU is electrically connected to the output end of the first analog-to-digital conversion unit ADC1, and is configured to output the display state of the display panel as a first abnormal display state, in which the direct-current digital voltage signal DVDD has a first set value. That is, the second controller CPU is configured to determine whether the voltage of the direct-current digital voltage signal DVDD meets the first set value, and if so, determine that the display state of the display panel 3 is the first abnormal display state. The first set value is less than 3.0 V or greater than 3.6 V.

[0155] The second analog-to-digital conversion unit ADC2 is electrically connected to the output end of the second voltage dividing unit 222, and is configured to convert the direct-current analog voltage signal AVDD into a digital signal. The second controller CPU is electrically connected to the output end of the second analog-to-digital conversion unit ADC2, and is configured to output the display state of the display panel as a second abnormal display state, in which the direct-current analog voltage signal AVDD has a second set value. That is, the second controller CPU is configured to determine whether the voltage of the direct-current analog voltage signal AVDD meets the second set value, and if so, determine that the display state of the display panel 3 is the second abnormal display state. The second set value is less than 15 V or greater than 17 V.

[0156] The third analog-to-digital conversion unit ADC3 is electrically connected to the output end of the sixth emitter follower unit 261, and is configured to convert the cathode voltage signal LED- into a digital signal. The second controller CPU is electrically connected to the output end of the third analog-to-digital conversion unit ADC3, and is configured to output the display state of the display panel as a sixth abnormal display state, in which the cathode voltage signal LED- has a sixth preset value. That is, the second controller CPU is configured to determine whether the cathode voltage signal LED- meets the sixth preset value, and if so, determine that the display state of the display panel 3 is the sixth abnormal display state. The sixth preset value is less than 0.25 V or greater than 0.5 V.

[0157] The first timing unit Timer1 is electrically connected to the output terminal of the third voltage dividing unit 232, and is configured to identify the frequency of the frame start signal STV1. The second controller CPU is electrically connected to the output terminal of the first timing unit Timer1, and is configured to output the display state of the display panel as a third abnormal display state, in which the frequency of the frame start signal STV1 has a third set value. That is, the second controller CPU is configured to determine whether the frequency of the frame start signal STV1 meets the third set value, and if yes, determine that the display state of the display panel 3 is the third abnormal display state. The third set value is less than 58 Hz or greater than 62 Hz.

[0158] The second timing unit Timer2 is electrically connected to the output terminal of the fourth voltage dividing unit 242, and is configured to identify the frequency of the reset signal STV2. The second controller CPU is electrically connected to the output terminal of the second timing unit Timer2, and is configured to output the display state of the display panel as a fourth abnormal display state, in which the frequency of the reset signal STV2 has a fourth set value. That is, the second controller CPU is configured to determine whether the frequency of the reset signal STV2 meets the fourth set value, and if yes, determine that the display state of the display panel 3 is the fourth abnormal display state. The fourth set value is less than 56 Hz or greater than 60 Hz, or the fourth set value is less than 1.5 kHz or greater than 1.9 kHz.

[0159] The third timing unit Timer3 is electrically connected to the output terminal of the fifth voltage dividing unit 252, and is configured to identify the frequency of the clock signal CLK. The second controller CPU is electrically connected to the output terminal of the third timing unit Timer3, and is configured to output the display state of the display panel as a fifth abnormal display state, in which the frequency of the clock signal CLK has a fifth set value. That is, the second controller CPU is configured to determine whether the frequency of the clock signal CLK meets the fifth set value, and if no, determine that the display state of the display panel 3 is the fifth abnormal display state. The fifth set value is less than 22.5 kHz or greater than 22.9 kHz.

[0160] The second controller CPU is configured to determine whether the voltage signal, the display signal and the backlight signal in the working signal are all normal, and if yes, determine that the display state of the display panel 3 is a normal display state; if no, the display state of the display panel 3 is an abnormal display state, which can include a plurality of types, as described above.

[0161] Further, the second controller CPU is configured to judge whether all of the working signals satisfy the following conditions, and if so, determine that the display state of the display panel 3 is a normal display state: the DC digital voltage signal DVDD is greater than or equal to 3.0 V and less than or equal to 3.6 V; the DC analog voltage signal AVDD is greater than or equal to 15 V and less than or equal to 17 V; the frame start signal STV1 is greater than or equal to 58 Hz and less than or equal to 62 Hz; the reset signal STV2 is greater than or equal to 56 Hz and less than or equal to 60 Hz, or the reset signal STV2 is greater than or equal to 1.5 kHz and less than or equal to 1.9 kHz; the clock signal CLK is greater than or equal to 22.5 kHz and less than or equal to 22.9 kHz; and the cathode voltage signal LED- is greater than or equal to 0.25 V and less than or equal to 0.5 V.

[0162] The specific judgment process of the second controller CPU is described in the monitoring method, which will not be repeated here.

[0163] The emitter follower units (the first emitter follower unit 211, the second emitter follower unit 221, the third emitter follower unit 231, the fourth emitter follower unit 241, the fifth emitter follower unit 251, and the sixth emitter follower unit 261) have an isolation effect, i.e., preventing signal backflow to the display circuit 1, and ensuring that the signal does not affect the normal operation of the original display circuit 1 after being connected to the monitoring circuit. The isolation of the two circuits is achieved by using the high input impedance characteristic of the emitter follower unit. In addition, the output voltage of the emitter follower unit is equal to the size of its input voltage, and the signal parameter acquisition can be accurately achieved.

[0164] Of course, in some other example embodiments of the present disclosure, the signal processing circuit 2 can not be provided, so that the processor MCU is directly electrically connected with the display circuit 1.

[0165] Referring to FIG. 5, the first emitter follower unit 211, the second emitter follower unit 221, and the sixth emitter follower unit 261 can be provided on a first chip IC1. VOUTA, VINA-, and VINA+ are three pins of the second emitter follower unit 221, which are used to collect the DC analog voltage signal AVDD. VOUTB, VINB-, and VINB+ are three pins of the first emitter follower unit 211, which are used to collect the DC digital voltage signal DVDD. VOUTC, VINC-, and VINC+ are three pins of the first sixth emitter follower unit 261, which are used to collect the cathode voltage signal LED1- of the first subzone. VOUTD, VIND-, and VIND+ are three pins of the second sixth emitter follower unit 261, which are used to collect the cathode voltage signal LED2- of the second subzone. Further, 0-ohm resistors 0R0 are connected to these input terminals, which can isolate these signals from the display circuit 1, so as to avoid the influence of these signals on the normal operation of the original display circuit 1.

[0166] Wherein, AVDD, DVDD, LED1- and LED2- are signals inputted into the first chip IC1, AVDD_M, DVDD_M, LED1_M and LED2_M are signals outputted from the first chip IC1, and the arrows in Fig. 5 also represent input and output. Similarly, 0 ohm resistors 0R0 are arranged at the output ends of these signals (except AVDD_M), and the 0 ohm resistors 0R0 can isolate the signals from each other, avoiding the influence of the later signals on the former signals.

[0167] The direct current analog voltage signal AVDD needs to be divided, and the second dividing unit 222 is formed by the first resistor R1 and the second resistor R2 to divide the direct current analog voltage signal AVDD.

[0168] Moreover, the first clamping diode D1 is connected at the connection end of AVDD_M, and the first clamping diode D1 limits the size of AVDD_M. The second clamping diode D2 is connected at the connection end of DVDD_M, and the second clamping diode D2 limits the size of DVDD_M.

[0169] VSS+ and VSS- are the positive and negative power supply ends of the first chip IC1, and the AVDD-OP outputted from the second power manager PMIC2 is inputted into the first chip IC1 through VSS+. Moreover, VSS+ is grounded through the capacitor C, and the capacitor C can filter the AVDD-OP to ensure the stability of the AVDD-OP.

[0170] Referring to Fig. 6, the third emitter follower unit 231 and the fourth emitter follower unit 241 can be arranged on one second chip IC2. OUTA, INA- and INA+ are three pins of the third emitter follower unit 231, and are used to collect the frame start signal STV1. OUTB, INB- and INB+ are three pins of the fourth emitter follower unit 241, and are used to collect the reset signal STV2. Moreover, 0 ohm resistors 0R0 are connected at these input ends, and the 0 ohm resistors 0R0 can isolate these signals from the display circuit 1, avoiding the influence of these signals on the normal work of the original display circuit 1.

[0171] Wherein, STV1 and STV2 are signals inputted into the second chip IC2, and STV1_M and STV2_M are signals outputted from the second chip IC2, and the arrows in Fig. 6 also represent input and output.

[0172] The frame start signal STV1 and the reset signal STV2 need to be divided, and the frame start signal STV1 and the reset signal STV2 are both negative and positive voltages, and the negative voltage needs to be adjusted to a positive voltage. The third voltage dividing unit 232 is formed by the third resistor R3 and the fourth resistor R4, and the frame start signal STV1 is divided, and the negative voltage of the frame start signal STV1 is adjusted to a positive voltage by the third clamping diode D3, the fifth resistor R5 and the sixth resistor R6. The fourth voltage dividing unit 242 is formed by the seventh resistor R7 and the eighth resistor R8, and the reset signal STV2 is divided, and the negative voltage of the reset signal STV2 is adjusted to a positive voltage by the fourth clamping diode D4, the ninth resistor R9 and the tenth resistor R10.

[0173] VS+ and VS- are the positive and negative power supply terminals of the second chip IC2, and VGH_OP output by the second power manager PMIC2 is input into the second chip IC2 through VS+. VGL_OP output by the second power manager PMIC2 is input into the second chip IC2 through VS-. Moreover, VS+ and VS- are both grounded through the capacitor C, and the capacitor C can filter VGH_OP and VGL_OP to ensure the stability of VGH_OP and VGL_OP.

[0174] Referring to FIG. 7, two fifth emitter follower units 251 can be arranged on a third chip IC3. OUTA, INA- and INA+ are three pins of a fifth emitter follower unit 251, used to collect a clock signal CLK1. OUTB, INB- and INB+ are three pins of another fifth emitter follower unit 251, used to collect another clock signal CLK. Moreover, a 0 ohm resistor 0R0 is connected to each of the input terminals, and the 0 ohm resistor 0R0 can isolate these signals from the display circuit 1, avoiding the influence of these signals on the normal work of the original display circuit 1.

[0175] Among them, CLK1 and CLK2 are signals input into the third chip IC3, and CLK1_M and CLK2_M are signals output by the third chip IC3, and the arrows in FIG. 7 also represent input and output.

[0176] Both clock signals CLK1 and CLK2 need to be divided, and both clock signals CLK1 and CLK2 are negative and positive, and the negative voltage needs to be adjusted to positive voltage. A fifth voltage dividing unit 252 is formed by the eleventh resistor R11 and the twelfth resistor R12 to divide one clock signal CLK1, and the negative voltage of one clock signal CLK1 is adjusted to positive voltage by the fifth clamping diode D5, the thirteenth resistor R13 and the fourteenth resistor R14. Another fifth voltage dividing unit 252 is formed by the fifteenth resistor R15 and the sixteenth resistor R16 to divide another clock signal CLK2, and the negative voltage of another clock signal CLK2 is adjusted to positive voltage by the sixth clamping diode D6, the seventeenth resistor R17 and the eighteenth resistor R18.

[0177] VS+ and VS- are the positive and negative power supply terminals of the third chip IC3, and VGH_OP output by the second power manager PMIC2 is input to the third chip IC3 through VS+. VGL_OP output by the second power manager PMIC2 is input to the third chip IC3 through VS-. Moreover, both VS+ and VS- are grounded through the capacitor C, and VGH_OP and VGL_OP can be filtered through the capacitor C to ensure the stability of VGH_OP and VGL_OP.

[0178] The circuit connection structure of the fifth signal processing circuit 25 for collecting other clock signals CLK4-CLK6 can be the same as that shown in FIG. 7, and thus will not be described here.

[0179] In some other example embodiments of the present disclosure, the number of clock signals CLK of the gate drive circuit of the display module with super large size and the display module with super high resolution is large, for example, twelve clock signals CLK can be provided, and eighteen clock signals CLK can also be provided. If these clock signals CLK are directly monitored, the number of signal processing circuits used will increase, the interface of the processor MCU also needs to be increased, thereby increasing the hardware cost and the area of the first printed circuit board 351.

[0180] In this case, the specific conditions of the voltage signal and the first signal processing circuit 21 and the second signal processing circuit 22 included in the signal processing circuit 2 are the same as those in the above example embodiments, and thus will not be described here.

[0181] The specific conditions of the frame start signal STV1 and the reset signal STV2 in the display signal and the third signal processing circuit 23 and the fourth signal processing circuit 24 included in the signal processing circuit 2 are the same as those in the above example embodiments, and thus will not be described here.

[0182] The first controller TCON is configured to output a display signal required by the display panel 3 or a first error identification signal LS-F according to the working state of the level shifter LSIC. When over temperature protection (OTP) and over current protection (OCP) of the level shifter LSIC occur, the first error identification signal LS-F can be triggered from a high level in normal working to a low level. When over temperature protection of the level shifter LSIC occurs, the level shifter LSIC is prone to burnout. When a signal short circuit of the gate drive circuit GOA occurs, the level shifter LSIC is prone to over current protection.

[0183] The second controller CPU is configured to determine the display state of the display panel by judging whether the first error identification signal LS-F is received. Specifically, if the first error identification signal LS-F is received, it is determined that the display panel 3 is in the seventh abnormal display state.

[0184] In this case, the signal processing circuit 2 is electrically connected to the output end of the level shifter LSIC.

[0185] Specifically, referring to FIGS. 8 and 9, the signal processing circuit 2 can include a seventh signal processing circuit 27 configured to process the first error identification signal LS-F. The seventh signal processing circuit 27 can include a seventh emitter follower unit 271 and a seventh voltage dividing unit 272; the seventh emitter follower unit 271 is electrically connected to the output end of the level shifter LSIC and is configured to collect the first error identification signal LS-F and prevent the first error identification signal LS-F from flowing back to the display circuit; and the seventh voltage dividing unit 272 is electrically connected to the output end of the seventh emitter follower unit 271 and is configured to adjust the voltage value of the first error identification signal LS-F to a fixed voltage, i.e., the seventh voltage dividing unit 272 is configured to adjust the voltage value of the first error identification signal LS-F to a required range.

[0186] By monitoring one first error identification signal LS-F instead of monitoring a plurality of clock signals CLK, i.e., regardless of how many clock signals CLK are provided, only one first error identification signal LS-F is monitored, so that the number of signal processing circuits used is reduced, the interface of the processor MCU is also reduced, the hardware cost is reduced, and the area of the first printed circuit board 351 can also be set smaller.

[0187] In this case, since the first error identification signal LS-F changes from the normal high level to the low level, the voltage of the first error identification signal LS-F does not need to be accurately obtained, and a timing unit is not needed to accurately collect the frequency of the clock signal CLK. Therefore, the processor MCU can include a first input port GPIO1. The first input port GPIO1 is electrically connected to the output end of the seventh voltage dividing unit 272.

[0188] The second controller CPU is electrically connected to the output end of the seventh voltage dividing unit 272, specifically, the second controller CPU is electrically connected to the first input port GPIO1; the second controller CPU determines the display state of the display panel 3 according to whether the first error identification signal LS-F is received, that is, the second controller CPU is configured to determine whether the first error identification signal LS-F is received, and if so, the display state of the display panel 3 is determined to be abnormal display caused by the abnormality of the level shifter LSIC. The specific process is described in the monitoring method, which will not be described here.

[0189] In some other example embodiments of the present disclosure, the backlight module 31 of the highlight display module has more partitions, for example, the number of partitions of the backlight module 31 of Local Dimming (Local Dimming) is usually dozens of partitions. If the cathode voltage signal LED- of each partition is monitored, the number of signal processing circuits used will increase, the interface of the processor MCU also needs to be increased, thereby increasing the hardware cost, and increasing the area of the first printed circuit board 351.

[0190] In this case, the specific conditions of the voltage signal and the first signal processing circuit 21 and the second signal processing circuit 22 included in the signal processing circuit 2 are the same as those in the above example embodiments, and thus will not be described here.

[0191] In this case, the display circuit can further include a backlight drive controller LED-D (LED Driver), the output end of the backlight drive controller LED-D is electrically connected to the input end of the second controller CPU and the input end of the backlight drive circuit, and the output end of the backlight drive controller LED-D is electrically connected to the backlight converter BLU-Con; the backlight drive controller LED-D is configured to output the second error identification signal LED-DF or the backlight signal according to the working state of the backlight drive controller LED-D.

[0192] The input end of the second controller CPU is electrically connected to the output end of the backlight drive controller LED-D, and is electrically connected to the output end of the first controller TCON through the level shifter LSIC, and the second controller CPU is configured to determine the display state of the display panel by judging whether the second error identification signal LED-DF is received.

[0193] The monitoring circuit further comprises a signal processing circuit 2 electrically connected between the backlight driving controller LED-D and the second controller CPU, for processing the second error identification signal LED-DF.

[0194] Specifically, referring to FIGS. 8 and 9, the signal processing circuit 2 can comprise a sixth signal processing circuit 26, which can comprise a sixth emitter follower unit 261 electrically connected to the output end of the backlight driving controller LED-D, specifically, the sixth emitter follower unit 261 is electrically connected to the backlight converter BLU-Con of the backlight driving circuit of the backlight module 31. The sixth emitter follower unit 261 is used to collect the second error identification signal LED-DF.

[0195] In the case of over temperature protection (OTP) of the backlight driving controller LED-D, open circuit or short circuit of the backlight, the second error identification signal LED-DF can be triggered, and the second error identification signal LED-DF changes from the normal high level to the low level.

[0196] By monitoring one second error identification signal LED-DF instead of monitoring multiple cathode voltage signals LED-, no matter how many partitions the backlight module 31 is provided with and how many backlight driving controllers LED-D are used, the error signals of the respective backlight driving controllers LED-D can be connected together to form one second error identification signal LED-DF. Therefore, only one second error identification signal LED-DF needs to be monitored, which reduces the number of signal processing circuits used and the interface of the processor MCU, reduces the hardware cost, and the area of the first printed circuit board 351 can also be set smaller.

[0197] In this case, since the second error identification signal LED-DF changes from the normal high level to the low level, it is not necessary to accurately obtain the voltage of the second error identification signal LED-DF, and an analog-to-digital conversion unit is not needed to accurately collect the voltage of the second error identification signal LED-DF. Therefore, the processor MCU can comprise a second input port GPIO2 electrically connected to the output end of the sixth emitter follower unit 261.

[0198] The second controller CPU is configured to determine the display state of the display panel 3 by judging whether the second error identification signal LED-DF is received; the second controller CPU is electrically connected to the second input port GPIO2, and the second controller CPU determines whether the backlight is normal or abnormal to cause abnormal display according to whether the second error identification signal is received. The specific process is described in the monitoring method, which will not be repeated here.

[0199] It should be noted that in the example embodiment of monitoring the second error identification signal LED-DF, the clock signal CLK can be monitored; of course, in the example embodiment of monitoring the first error identification signal LS-F, the cathode voltage signal LED- of each sub-zone of the backlight module 31 can be monitored.

[0200] In addition, the output end UART of the processor MCU can be connected to the SoC mainboard, and the monitoring result can be transmitted to the SoC mainboard, so that the SoC mainboard learns of the display state in the first time, and the technical effect of automatically monitoring the display state of the display module in real time is achieved. Moreover, the SoC mainboard can also be connected to a control center, which can be a customer after-sales platform, a railway central control platform, etc. For example, the SoC mainboard can upload the monitoring result to a cloud platform and issue abnormal information to after-sales personnel, so that the display can be repaired and replaced in the first time after an abnormality occurs, avoiding bad use effects on consumers.

[0201] In some example embodiments of the present disclosure, referring to FIGS. 2 and 3, the monitoring circuit can further include a second power manager PMIC2, which is electrically connected to the monitoring circuit and is configured to supply power to the monitoring circuit; for example, the second power manager PMIC2 is electrically connected to the signal processing circuit 2 and the second controller CPU, and is configured to supply power to the signal processing circuit 2 and the second controller CPU; or the second power manager PMIC2 is electrically connected to the signal processing circuit 2 and the processor MCU, and is configured to supply power to the signal processing circuit 2 and the processor MCU, so that the signal processing circuit 2 and the processor MCU are not powered by the same power supply as the first controller TCON and the level shifter LSIC, and in the case of abnormality of the first power manager PMIC1, the normal work of the signal processing circuit 2 and the processor MCU will not be affected.

[0202] The first printed circuit board 351 is also provided with a jumper cap, through which the on-off of the analog signal can be simulated, and the processor MCU can monitor the state of each analog signal in real time.

[0203] Based on the same inventive concept, the example embodiments of the present disclosure provide a display module monitoring circuit. The display module can include a backlight module 31, a display panel 3, and a display circuit 1. The display circuit 1 can include a main controller, a first controller TCON, a backlight driving controller LED-D, and a level shifter LSIC. An input end of the first controller TCON is electrically connected to an output end of the main controller. An output end of the first controller TCON is electrically connected to an input end of the level shifter LSIC. An output end of the backlight driving controller LED-D is electrically connected to an input end of the backlight module 31. The first controller TCON is configured to output a display signal required by the display panel or a first error identification signal LS-F according to a working state of the level shifter LSIC. The backlight driving controller LED-D is configured to output a second error identification signal LED-DF or a backlight signal according to a working state of the backlight driving controller LED-D.

[0204] In this case, the monitoring circuit can include a second controller CPU. An input end of the second controller CPU is electrically connected to an output end of the backlight driving controller LED-D and is electrically connected to an output end of the first controller TCON through the level shifter LSIC. The second controller CPU is configured to determine the display state of the display panel 3 by judging whether the first error identification signal LS-F and / or the second error identification signal LED-DF is received. That is, the display state of the display panel 3 can be determined by the first error identification signal LS-F and the second error identification signal LED-DF together or by any one of the first error identification signal LS-F and the second error identification signal LED-DF. The generation principle and determination criteria of the first error identification signal LS-F and the second error identification signal LED-DF are described in detail above, and thus will not be described again here.

[0205] Based on the same inventive concept, the example embodiments of the present disclosure provide a display module monitoring method. The monitoring method is used in the monitoring circuit described in any one of the above embodiments. The monitoring method can include the following steps: collecting a display signal and / or a voltage signal of the display circuit, determining whether the display panel displays normally and the abnormal type of abnormal display according to the display signal and / or the voltage signal, and outputting the determination result.

[0206] The steps of the monitoring method are described below.

[0207] Referring to FIG. 10, after the system (i.e., the display device) is powered on stably, the voltage signal of the display circuit 1 is collected. Specifically, the voltage signal can include a direct-current analog voltage signal AVDD and a direct-current digital voltage signal DVDD. Therefore, the direct-current analog voltage signal AVDD and the direct-current digital voltage signal DVDD of the display circuit 1 are collected.

[0208] If the voltage signal is within the set range, it is determined that the voltage is normal; that is, if the voltage of the direct-current analog voltage signal AVDD meets the first preset value, and the voltage of the direct-current analog voltage signal AVDD meets the second preset value, it is determined that the voltage is normal and output.

[0209] Specifically, the first preset value of the direct-current analog voltage signal AVDD can be greater than or equal to 15V and less than or equal to 17V. The second preset value of the direct-current digital voltage signal DVDD can be greater than or equal to 3V and less than or equal to 3.6V. That is, the voltage of the collected direct-current analog voltage signal AVDD is greater than or equal to 15V and less than or equal to 17V, and the voltage of the collected direct-current digital voltage signal DVDD is greater than or equal to 3V and less than or equal to 3.6V, it is determined that the voltage is normal. That is, the direct-current analog voltage signal AVDD and the direct-current digital voltage signal DVDD are within the respective set range, and it is determined that the voltage is normal.

[0210] If the voltage signal is not within the set range, it is determined that the voltage is abnormal and output; that is, if the voltage of the direct-current digital voltage signal DVDD does not meet the first preset value, and / or, the voltage of the direct-current analog voltage signal AVDD does not meet the second preset value, it is determined that the voltage is abnormal and output.

[0211] Specifically, the voltage of the collected direct-current analog voltage signal AVDD is less than 15V or greater than 17V, or the value of the collected direct-current digital voltage signal DVDD is less than 3V or greater than 3.6V, it is determined that the voltage is abnormal and output. That is, as long as one of the direct-current analog voltage signal AVDD and the direct-current digital voltage signal DVDD is not within the respective set range, it is determined that the voltage is abnormal and output; of course, if the voltage of the direct-current digital voltage signal DVDD does not meet the first preset value, and the voltage of the direct-current analog voltage signal AVDD does not meet the second preset value, it is also determined that the voltage is abnormal and output; for example, the code 0x01 in hexadecimal can be output as the code of voltage abnormality; of course, it can also be output through binary code, and it can also be directly output in Chinese or English, which is not limited here.

[0212] In addition, in some other example embodiments of the present disclosure, only one of the direct-current analog voltage signal AVDD and the direct-current digital voltage signal DVDD can be monitored.

[0213] It should be noted that, since the voltage value of the direct current analog voltage signal AVDD is adjusted to a fixed voltage by the second voltage dividing unit 222, the fixed voltage is greater than or equal to 0 and less than or equal to 3.3V, and the second preset value can be greater than or equal to 3V and less than or equal to 3.6V, therefore, a mapping table between the adjusted value and the actual value of the direct current analog voltage signal AVDD can be established, and the adjusted value of the direct current analog voltage signal AVDD can be mapped to the actual value before the comparison between the direct current analog voltage signal AVDD and the second preset value is performed.

[0214] Referring to FIG. 10, after determining that the voltage is normal, the display signal of the display circuit 1 is collected; since the voltage is abnormal, the display signal is also abnormal, therefore, it is unnecessary to collect the display signal in the case of determining that the voltage is abnormal, and the collection of the display signal is needed only in the case of determining that the voltage is normal. The display signal can include a frame start signal STV1, a reset signal STV2 and a plurality of clock signals CLK, therefore, the frame start signal STV1, the reset signal STV2 and the plurality of clock signals CLK of the display circuit 1 are collected.

[0215] If the display signal is within the set range, it is determined that the driving is normal; that is, if the frequency of the frame start signal STV1 meets the third preset value, the frequency of the reset signal STV2 meets the fourth preset value, and the frequency of the plurality of clock signals CLK meets the fifth preset value, it is determined that the driving is normal and output.

[0216] Specifically, the third preset value of the frame start signal STV1 can be greater than or equal to 58Hz and less than or equal to 62Hz. The fourth preset value of the reset signal STV2 can be greater than or equal to 56Hz and less than or equal to 60Hz, or the fourth preset value of the reset signal STV2 can be greater than or equal to 1.5kHz and less than or equal to 1.9kHz. The fifth preset value of the clock signal CLK can be greater than or equal to 22.5kHz and less than or equal to 22.9kHz. That is, the value of the collected frame start signal STV1 is greater than or equal to 58Hz and less than or equal to 62Hz, the value of the collected reset signal STV2 is greater than or equal to 56Hz and less than or equal to 60Hz, or greater than or equal to 1.5kHz and less than or equal to 1.9kHz, and the value of the collected clock signal CLK is greater than or equal to 22.5kHz and less than or equal to 22.9kHz, then it is determined that the driving is normal. That is, the frame start signal STV1, the reset signal STV2 and the plurality of clock signals CLK are all within the respective set ranges, and only then it is determined that the driving is normal.

[0217] If the display signal is not within the set range, it is determined that the driving is abnormal and output; that is, if the frequency of the frame start signal STV1 does not meet the third preset value, and / or the frequency of the reset signal STV2 does not meet the fourth preset value, and / or the frequency of the plurality of clock signals CLK does not meet the fifth preset value, it is determined that the driving is abnormal and output.

[0218] Specifically, if the value of the collected frame start signal STV1 is less than 58 Hz or greater than 62 Hz, or the value of the collected reset signal STV2 is less than 56 Hz or greater than 60 Hz, or less than 1.5 kHz or greater than 1.9 kHz, or the value of the collected clock signal CLK is less than 22.5 kHz or greater than 22.9 kHz, it is determined that the driving is abnormal and output. That is, as long as one of the frame start signal STV1, the reset signal STV2, and the plurality of clock signals CLK is not within the respective corresponding set range, it is determined that the driving is abnormal and output; of course, it can also be that two or more of the frame start signal STV1, the reset signal STV2, and the plurality of clock signals CLK are not within the respective corresponding set range, it is determined that the driving is abnormal and output; for example, the hexadecimal code 0x02 can be output as the code of the driving abnormality; of course, it can also be output through a binary code, and can also be directly output in Chinese or English, which is not limited here.

[0219] In addition, in some other example embodiments of the present disclosure, only one, two or more of the frame start signal STV1, the reset signal STV2, and the plurality of clock signals CLK can be monitored.

[0220] In some other example embodiments of the present disclosure, the monitoring method can further include: after determining that the voltage is normal, collecting a first error identification signal LS-F of the display circuit 1; if the first error identification signal LS-F is collected, it is determined that the driving is abnormal and output.

[0221] In this case, the display signal can include the frame start signal STV1 and the reset signal STV2, and the set range and judgment standard of the frame start signal STV1 and the reset signal STV2 have been described in detail above, so they will not be repeated here. The principle of generating the first error identification signal LS-F has also been described in detail above, so it will not be repeated here.

[0222] Specifically, if the frequency of the collected frame start signal STV1 is greater than or equal to 58 Hz and less than or equal to 62 Hz, and the frequency of the collected reset signal STV2 is greater than or equal to 56 Hz and less than or equal to 60 Hz, or greater than or equal to 1.5 kHz and less than or equal to 1.9 kHz, and the first error identification signal LS-F is not collected, it is determined that the driving is normal. That is, only when the frame start signal STV1, the reset signal STV2, and the first error identification signal LS-F all meet the above conditions, it is determined that the driving is normal.

[0223] If the frequency of the collected frame start signal STV1 is less than 58 Hz or greater than 62 Hz, and / or, the frequency of the collected reset signal STV2 is less than 56 Hz or greater than 60 Hz, or less than 1.5 kHz or greater than 1.9 kHz, and / or, the first error identification signal LS-F is collected, it is determined that the driving is abnormal and output. That is, as long as one of the frame start signal STV1, the reset signal STV2, and the first error identification signal LS-F does not meet the above conditions, it is determined that the driving is abnormal and output, for example, the hexadecimal code 0x02 can be output as the code of the driving abnormality; of course, it can also be output by binary code, and can also be directly output by Chinese or English, which is not limited here.

[0224] In addition, in some other example embodiments of the present disclosure, when the first error identification signal LS-F of the display circuit 1 is collected, the display signal can include one of the frame start signal STV1 and the reset signal STV2.

[0225] Referring to FIG. 10, the monitoring method can further include collecting a backlight signal of the display circuit 1, and determining whether the display panel 3 normally displays and an abnormal type of abnormal display according to the backlight signal, and outputting the determination result.

[0226] Specifically, the voltage signal is collected, and at the same time, the backlight signal of the display circuit 1 is collected; the backlight signal can include the cathode voltage signal LED- of each sub-zone of the backlight module 31, and therefore, the cathode voltage signal LED- of each sub-zone of the backlight module 31 of the display circuit 1 is collected.

[0227] If the cathode voltage signal LED- meets the sixth preset value, it is determined that the backlight is normal; the sixth preset value of the backlight signal can be greater than or equal to 0.25 V and less than or equal to 0.5 V. That is, if the values of the collected cathode voltage signals LED- of each sub-zone of the backlight module 31 are all greater than or equal to 0.25 V and less than or equal to 0.5 V, it is determined that the backlight is normal.

[0228] If the cathode voltage signal LED- does not meet the sixth preset value, it is determined that the backlight is abnormal and output; that is, as long as the value of the cathode voltage signal LED- of each sub-area of the backlight module 31 collected is less than 0.25V or greater than 0.5V, it is determined that the backlight is abnormal and output, for example, in the case where the backlight module 31 is provided with three sub-areas, as long as the value of the cathode voltage signal LED- of one sub-area is less than 0.25V or greater than 0.5V, it is determined that the backlight is abnormal and output, for example, the code 0x04 in hexadecimal can be output as the code of the backlight abnormality; of course, it can also be output through a binary code, and can also be directly output in Chinese or English, which is not limited here.

[0229] It should be noted that in the case where the backlight module 31 has only one sub-area, the cathode voltage signal LED- of one sub-area can be determined; in the case where the backlight module 31 has two or more sub-areas, the cathode voltage signals LED- of all sub-areas need to be determined, and as long as the cathode voltage signal LED- of one sub-area does not meet the set range, it is determined that the backlight is abnormal and output.

[0230] In some other example embodiments of the present disclosure, the monitoring method can further include collecting a second error identification signal LED-DF of the display circuit 1, and determining whether the display panel 3 is normally displayed and the abnormal type of abnormal display according to the second error identification signal LED-DF, and outputting the determination result.

[0231] Specifically, the second error identification signal LED-DF is collected at the same time as the voltage signal; if the second error identification signal LED-DF is not collected, it is determined that the backlight is normal; if the second error identification signal LED-DF is collected, it is determined that the backlight is abnormal and output, for example, the code 0x04 in hexadecimal can be output as the code of the backlight abnormality; of course, it can also be output through a binary code, and can also be directly output in Chinese or English, which is not limited here.

[0232] In the case where the backlight module 31 is provided with two or more sub-areas, only one second error identification signal LED-DF needs to be collected.

[0233] When the voltage is determined to be normal, the driving is determined to be normal, and the backlight is determined to be normal, the display is output to be normal, for example, the code 0xFF in hexadecimal can be output as the code of the normal display; of course, it can also be output through a binary code, and can also be directly output in Chinese or English, which is not limited here.

[0234] Of course, in some other example embodiments of the present disclosure, in the case where only one or two of the voltage signal, the display signal, and the backlight signal is monitored, as long as the monitored one or two is normal, the display is output to be normal.

[0235] Referring to FIG. 10, in some example embodiments of the present disclosure, the monitoring method can further include setting the refresh rate of the built-in self-test display mode to a set value different from the refresh rate of normal display, for example, setting the refresh rate (STV1 special frequency) of the built-in self-test display mode to 70 Hz, 65 Hz, 50 Hz, or 48 Hz, etc. when the refresh rate of normal display is 60 Hz.

[0236] The built-in self-test (BIST) display mode can be used for abnormality detection in the use stage of the display module, and automatically detects the running state of a large-area screen. The built-in self-test display mode is generally a black picture or a black-and-white red-green-blue cycle picture.

[0237] After determining that the voltage is normal, the frame start signal STV1 is collected, that is, the refresh rate of the built-in self-test display mode is identified by the frame start signal STV1.

[0238] If the frame start signal (STV1 special frequency) is equal to the set value, it is determined that the built-in self-test is abnormal due to signal abnormality provided by the SoC mainboard and is output; if the frame start signal (STV1 special frequency) is not equal to the set value, it is determined that the built-in self-test is normal.

[0239] Referring to FIG. 10, in the case of built-in self-test determination, when it is determined that the voltage is normal, the built-in self-test is normal, the driving is normal, and the backlight is normal, the display is normal is output, for example, the code 0xFF in hexadecimal can be output as the code of normal display; of course, it can also be output by binary code, and can also be directly output by Chinese or English, which is not limited here.

[0240] The monitoring method can further include adjusting the voltage value of the above-mentioned signals to the required range after collecting the above-mentioned signals of the display circuit 1. Since the processor MCU can only withstand a voltage of 0-3.3V, the voltage value of the collected signals needs to be adjusted to the required range to avoid damage to the processor MCU.

[0241] It should be noted that the continuous collection time of various signals in the above-mentioned signals is about 5 seconds, and the collection and determination are performed simultaneously; after completing a round of collection and determination, the next round of collection and determination is performed, that is, after completing the collection and determination of the voltage signal, the display signal (no collection and determination is required when the voltage signal is abnormal), and the backlight signal, the next round of collection and determination of the voltage signal, the display signal, and the backlight signal is performed. Moreover, the above-mentioned data is only an example and is used to illustrate the logic, and different data can be set according to different display modules, and the specific values are different after being divided by the voltage dividing unit, which will not be described one by one here.

[0242] It should be noted that although the steps of the monitoring method of the display module in the present disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in this specific order, or that all the steps shown must be performed to achieve the desired results. In addition or alternatively, some steps can be omitted, multiple steps can be combined into one step, and / or one step can be divided into multiple steps, etc.

[0243] Based on the same inventive concept, the example embodiments of the present disclosure provide a display device, which can include a display module and a monitoring circuit of the display module as described in any one of the above. The specific structure of the display module and the monitoring circuit has been described in detail above, and thus will not be described here again.

[0244] The specific type of the display device is not particularly limited, and any type of display device commonly used in the art can be used, such as a rail transit display screen, an outdoor advertising machine, a refrigerator display screen, a vehicle-mounted display screen, a mobile device such as a mobile phone, a wearable device such as a watch, a VR device, etc. A person skilled in the art can select a corresponding display device according to the specific use of the display device, and thus will not be described here again.

[0245] For example, the display device of rail transit, the display device at the subway station / station / parking lot, etc. The display device is used to provide vehicle arrival and station guidance information to pedestrians. If a display failure cannot be found and repaired in the first time, it will bring long-term inconvenience to the traveling personnel.

[0246] For example, the outdoor advertising machine has many applications in sparsely populated scenes, and the consumer and the operator cannot timely find the display failure. It is more suitable for the above monitoring method and monitoring circuit.

[0247] It should be noted that the display device can also include other necessary components and compositions. For example, for a display, specific components such as a shell, a circuit board, a power cord, etc. can be added according to the specific use requirements of the display device, and thus will not be described here again.

[0248] Compared with the prior art, the display device provided by the example embodiments of the present disclosure has the same beneficial effects as the monitoring circuit of the display module provided by the above example embodiments, and thus will not be described here again.

[0249] Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the features disclosed herein. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

Claims

1. A monitoring circuit for a display module, wherein, The display module includes a display panel and a display circuit. The display circuit includes a main controller, a first controller, a first power manager, and a level converter. The input terminal of the first controller is electrically connected to the output terminal of the first power manager and the output terminal of the main controller. The output terminal of the first controller is electrically connected to the input terminal of the level converter. The first controller is configured to output the display signal required by the display panel through the level converter according to the instructions of the main controller. The first power manager is configured to provide a voltage signal to the first controller. The monitoring circuit includes: A second controller, the input of which is electrically connected to the output of the first power manager and electrically connected to the output of the first controller via the level converter, is configured to monitor the display status of the display panel based on the display signal and / or the voltage signal, wherein the output of the level converter is electrically connected to the input of the display panel and the input of the second controller.

2. The monitoring circuit of the display module according to claim 1, wherein, The display module further includes a backlight module, and the display circuit further includes a backlight driving circuit. The backlight driving circuit is configured to provide a backlight signal to the backlight module, and the output terminal of the backlight driving circuit is electrically connected to the second controller and the input terminal of the backlight module.

3. The monitoring circuit of the display module according to claim 1, wherein, The monitoring circuit also includes: The signal processing circuit includes a first signal processing circuit configured to process a DC digital voltage signal in the voltage signal. The first signal processing circuit includes: The first emitter follower unit is electrically connected to the output terminal of the first power manager. The first emitter follower unit is configured to acquire the DC digital voltage signal in the voltage signal and prevent the DC digital voltage signal from flowing back to the display circuit. The first analog-to-digital converter is electrically connected to the output terminal of the first emitter follower unit; the second controller is electrically connected to the output terminal of the first analog-to-digital converter, and the second controller is configured to output the display state of the display panel as a first abnormal display state. In the first abnormal display state, the DC digital voltage signal has a first set value.

4. The monitoring circuit of the display module according to claim 3, wherein, The first set value is less than 3.0V or greater than 3.6V.

5. The monitoring circuit of the display module according to claim 1, wherein, The monitoring circuit also includes: The signal processing circuit includes a second signal processing circuit configured to process a DC analog voltage signal in the voltage signal. The second signal processing circuit includes: The second emitter follower unit is electrically connected to the output terminal of the first power manager. The second emitter follower unit is configured to acquire the DC analog voltage signal in the voltage signal and prevent the DC analog voltage signal from flowing back to the display circuit. The second voltage divider unit is electrically connected to the output terminal of the second emitter follower unit, and the second voltage divider unit is configured to adjust the value of the DC analog voltage signal to a fixed voltage. The second analog-to-digital converter is electrically connected to the output terminal of the second voltage divider unit; The second controller is electrically connected to the output terminal of the second analog-to-digital converter. The second controller is configured to output the display state of the display panel as a second abnormal display state. In the second abnormal display state, the DC analog voltage signal has a second set value.

6. The monitoring circuit of the display module according to claim 5, wherein, The second setting value is less than 15V or greater than 17V.

7. The monitoring circuit of the display module according to claim 1, wherein, The monitoring circuit also includes: The signal processing circuit includes a third signal processing circuit configured to process a frame start signal in the display signal, the third signal processing circuit comprising: The third emitter follower unit is electrically connected to the output terminal of the level converter. The third emitter follower unit is configured to acquire the frame start signal in the display signal and prevent the frame start signal from flowing back to the display circuit. The third voltage divider unit is electrically connected to the output terminal of the third emitter follower unit, and the third voltage divider unit is configured to adjust the voltage value of the frame start signal to a fixed voltage. The first timing unit is electrically connected to the output terminal of the third voltage divider unit; The second controller is electrically connected to the output terminal of the first timing unit. The second controller is configured to output the display state of the display panel as a third abnormal display state. In the third abnormal display state, the frequency of the frame start signal has a third set value.

8. The monitoring circuit of the display module according to claim 7, wherein, The third set value is less than 58Hz or greater than 62Hz.

9. The monitoring circuit of the display module according to claim 1, wherein, The monitoring circuit also includes: The signal processing circuit includes a fourth signal processing circuit configured to process a reset signal in the display signal, the fourth signal processing circuit comprising: The fourth emitter follower unit is electrically connected to the output terminal of the level converter. The fourth emitter follower unit is configured to acquire the reset signal in the display signal and prevent the reset signal from flowing back to the display circuit. The fourth voltage divider unit is electrically connected to the output terminal of the fourth emitter follower unit, and the fourth voltage divider unit is configured to adjust the voltage value of the reset signal to a fixed voltage; The second timing unit is electrically connected to the output terminal of the fourth voltage divider unit; The second controller is electrically connected to the output terminal of the second timing unit. The second controller is configured to output the display state of the display panel as a fourth abnormal display state. In the fourth abnormal display state, the frequency of the reset signal has a fourth set value.

10. The monitoring circuit of the display module according to claim 9, wherein, The fourth setting value is less than 56Hz or greater than 60Hz, or the fourth setting value is less than 1.5kHz or greater than 1.9kHz.

11. The monitoring circuit of the display module according to claim 1, wherein, The monitoring circuit also includes: The signal processing circuit includes a plurality of fifth signal processing circuits configured to process the clock signal in the display signal, the fifth signal processing circuit including: The fifth emitter follower unit is electrically connected to the output terminal of the level converter. The fifth emitter follower unit is configured to acquire the clock signal in the display signal and prevent the clock signal from flowing back to the display circuit. The fifth voltage divider unit is electrically connected to the output terminal of the fifth emitter follower unit, and the fifth voltage divider unit is configured to adjust the voltage value of the clock signal to a fixed voltage; Multiple third timing units are electrically connected to the output terminals of multiple fifth voltage divider units in a one-to-one correspondence. The second controller is electrically connected to the output terminals of a plurality of third timing units; the second controller is configured to output the display state of the display panel as a fifth abnormal display state, in which the frequency of the clock signal has a fifth set value.

12. The monitoring circuit of the display module according to claim 11, wherein, The fifth set value is less than 22.5 kHz or greater than 22.9 kHz.

13. The monitoring circuit of the display module according to claim 2, wherein, The monitoring circuit also includes: The signal processing circuit includes a sixth signal processing circuit configured to process the cathode voltage signal in the backlight signal. The sixth signal processing circuit includes: The sixth emitter follower unit is electrically connected to the backlight driving circuit. The sixth emitter follower unit is configured to acquire the cathode voltage signal in the backlight signal and prevent the cathode voltage signal from flowing back to the display circuit. The third analog-to-digital converter is electrically connected to the output terminal of the sixth emitter follower unit; The second controller is electrically connected to the output terminal of the third analog-to-digital conversion unit. The second controller is configured to output the display state of the display panel as the sixth abnormal display state. In the sixth abnormal display state, the cathode voltage signal has a sixth preset value.

14. The monitoring circuit of the display module according to claim 13, wherein, The sixth preset value is less than 0.25V or greater than 0.5V.

15. The monitoring circuit of the display module according to claim 2, wherein, The monitoring circuit also includes: A signal processing circuit is configured to process a working signal. The signal processing circuit includes an emitter follower unit and a voltage divider unit. The emitter follower unit is electrically connected to the output terminal of the display circuit, and the voltage divider unit is electrically connected to the output terminal of the emitter follower unit. The emitter follower unit is configured to acquire the working signal and prevent backflow of the working signal current. The voltage divider unit is configured to adjust the voltage of the working signal. The operating signal includes at least one of the voltage signal, the display signal, and the backlight signal; The second controller is configured to determine whether the voltage signal, the display signal and the backlight signal in the working signal are all normal, and if so, determine that the display panel is in a normal display state.

16. The monitoring circuit of the display module according to claim 2, wherein, The monitoring circuit also includes: A signal processing circuit is configured to process a working signal. The signal processing circuit includes an emitter follower unit and a voltage divider unit. The emitter follower unit is electrically connected to the output terminal of the display circuit, and the voltage divider unit is electrically connected to the output terminal of the emitter follower unit. The emitter follower unit is configured to acquire the working signal and prevent backflow of the working signal current. The voltage divider unit is configured to adjust the voltage of the working signal. The operating signal includes at least one of the following: the DC digital voltage signal and the DC analog voltage signal in the voltage signal; the frame start signal, the reset signal and the clock signal in the display signal; and the cathode voltage signal in the backlight signal. The second controller is configured to determine whether all of the operating signals meet the following conditions, and if so, determine that the display panel is in a normal display state: the DC digital voltage signal is greater than or equal to 3.0V and less than or equal to 3.6V; the DC analog voltage signal is greater than or equal to 15V and less than or equal to 17V; the frame start signal is greater than or equal to 58Hz and less than or equal to 62Hz; the reset signal is greater than or equal to 56Hz and less than or equal to 60Hz, or the reset signal is greater than or equal to 1.5kHz and less than or equal to 1.9kHz; the clock signal is greater than or equal to 22.5kHz and less than or equal to 22.9kHz; and the cathode voltage signal is greater than or equal to 0.25V and less than or equal to 0.5V.

17. The monitoring circuit of the display module according to any one of claims 3 to 16, wherein, The monitoring circuit also includes: A second power manager is electrically connected to the signal processing circuit and the second controller, and the second power manager is configured to supply power to the signal processing circuit and the second controller.

18. The monitoring circuit of the display module according to claim 1, wherein, The monitoring circuit also includes: A second power manager is electrically connected to the monitoring circuit and is configured to supply power to the monitoring circuit.

19. The monitoring circuit of the display module according to claim 1, wherein, At least a portion of the monitoring circuit and at least a portion of the display circuit are disposed on the same circuit board.

20. The monitoring circuit of the display module according to claim 2, wherein, The display circuit also includes: A backlight driver controller, the output of which is electrically connected to the second controller and the input of the backlight driver circuit, the backlight driver controller being configured to output a second error flag signal or a backlight signal according to the operating state of the backlight driver controller; The input terminal of the second controller is electrically connected to the output terminal of the backlight driver controller, and is electrically connected to the output terminal of the first controller through the level converter. The second controller is configured to determine the display status of the display panel by determining whether the second error flag signal is received.

21. The monitoring circuit of the display module according to claim 1, wherein, The display module further includes a backlight module, and the display circuit further includes a backlight driver controller. The output terminal of the backlight driver controller is electrically connected to the second controller and the input terminal of the backlight module. The backlight driver controller is configured to output a second error indicator signal or a backlight signal according to the working state of the backlight driver controller, and the first controller is configured to output a display signal required by the display panel or a first error indicator signal according to the working state of the level converter; The input terminal of the second controller is electrically connected to the output terminal of the backlight driver controller, and is electrically connected to the output terminal of the first controller through the level converter. The second controller is configured to determine the display status of the display panel by determining whether the first error flag signal and / or the second error flag signal are received.

22. A monitoring circuit for a display module, wherein, The display module includes a backlight module, a display panel, and a display circuit. The display circuit includes a main controller, a first controller, a backlight driver controller, and a level converter. The input terminal of the first controller is electrically connected to the output terminal of the main controller, and the output terminal of the first controller is electrically connected to the input terminal of the level converter. The output terminal of the backlight driver controller is electrically connected to the input terminal of the backlight module. The first controller is configured to output a display signal or a first error flag signal required by the display panel according to the operating state of the level converter. The backlight driver controller is configured to output a second error flag signal or a backlight signal according to the operating state of the backlight driver controller. The monitoring circuit includes: The second controller has its input terminal electrically connected to the output terminal of the backlight driver controller and is electrically connected to the output terminal of the first controller via the level converter. The second controller is configured to determine the display state of the display panel by determining whether the first error flag signal and / or the second error flag signal are received.

23. A method for monitoring a display module, used in the monitoring circuit according to any one of claims 1 to 22, wherein, The monitoring method includes: The system acquires display signals and / or voltage signals from the display circuit, determines whether the display panel is displaying normally and the type of abnormal display based on the display signals and / or voltage signals, and outputs the determination results.

24. The monitoring method for a display module according to claim 23, wherein, Acquire display signals and / or voltage signals from the display circuit, and determine whether the display panel is displaying normally and the type of abnormal display based on the display signals and / or voltage signals, including: Acquire the DC digital voltage signal and the DC analog voltage signal from the voltage signal; If the voltage of the DC digital voltage signal meets the first preset value and the voltage of the DC analog voltage signal meets the second preset value, then the voltage is determined to be normal and output. If the voltage of the DC digital voltage signal does not meet the first preset value, and / or the voltage of the DC analog voltage signal does not meet the second preset value, then a voltage abnormality is determined and output.

25. The monitoring method for a display module according to claim 24, wherein, Acquiring display signals and / or voltage signals from the display circuit, and determining whether the display panel is displaying normally and the type of abnormal display based on the values ​​of the display signals and / or voltage signals, further includes: After determining that the voltage is normal, the frame start signal, reset signal, and multiple clock signals of the displayed signal are collected; If the frequency of the frame start signal meets the third preset value, the frequency of the reset signal meets the fourth preset value, and the frequency of the plurality of clock signals meets the fifth preset value, then the drive is determined to be normal and output is performed. If the frequency of the frame start signal does not meet the third preset value, and / or the frequency of the reset signal does not meet the fourth preset value, and / or the frequency of the plurality of clock signals does not meet the fifth preset value, then a drive abnormality is determined and output.

26. The monitoring method for a display module according to claim 24, wherein, The monitoring method also includes: After determining that the voltage is normal, the first error indicator signal of the display circuit is collected; if the first error indicator signal is collected, the drive is determined to be abnormal and output.

27. The monitoring method for a display module according to claim 23, wherein, The monitoring method also includes: The backlight signal or the second error indicator signal of the display circuit is collected, and the display panel is judged as to whether it is displaying normally and the type of abnormal display based on the backlight signal or the second error indicator signal, and the judgment result is output.

28. The monitoring method for a display module according to claim 27, wherein, Acquire the backlight signal or the second error indicator signal of the display circuit, and determine whether the display panel is displaying normally and the type of abnormal display based on the backlight signal or the second error indicator signal, including: Simultaneously with acquiring the voltage signal, the cathode voltage signal in the backlight signal is also acquired; If the cathode voltage signal meets the sixth preset value, the backlight is determined to be normal; if the cathode voltage signal does not meet the sixth preset value, the backlight is determined to be abnormal and an output is made. Alternatively, the second error flag signal can be acquired simultaneously with the voltage signal; If the second error flag signal is detected, the backlight is determined to be abnormal and an error is output; if the second error flag signal is not detected, the backlight is determined to be normal.

29. The monitoring method for a display module according to claim 27, wherein, The monitoring method also includes: Set the refresh rate of the built-in self-test display mode to a value different from the refresh rate of the normal display. After determining that the voltage is normal, collect the frame start signal. If the frame start signal is equal to the set value, it is determined that the signal is abnormal, causing the built-in self-test to be abnormal and output. If the frame start signal is not equal to the set value, it is determined that the built-in self-test is normal.

30. The monitoring method for a display module according to claim 29, wherein, When the voltage, built-in self-test, drive, and backlight are all normal, the output display is normal.

31. A display device, wherein, include: Display module, including display panel and display circuit; The monitoring circuit is the monitoring circuit according to any one of claims 1 to 22, wherein the monitoring circuit is electrically connected to the display circuit.

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