Communication processing method and apparatus, and electronic device and readable storage medium

Abstract

The present application belongs to the technical field of communications. Disclosed are a communication processing method and apparatus, and an electronic device and a readable storage medium. The method comprises: when an electronic device configures a signal path called by a first subscriber identity module and a second subscriber identity module, acquiring a path state of the signal path and a configuration occasion therefor; on the basis of the path state and the configuration occasion, configuring the value of a target control bit in first path control information, so as to obtain second path control information, wherein the target control bit is a control bit, other than a first control bit, among control bits of the first path control information, and the first control bit corresponds to the path state; and on the basis of the first subscriber identity module and the second subscriber identity module, calling a target signal path, which corresponds to the second path control information, for communication processing.

Description

Communication processing method and apparatus, electronic device, and readable storage medium

[0001] Cross-reference to Related Applications

[0002] This application claims priority to Chinese Patent Application No. 202410517599.X, filed on April 28, 2024, the contents of which are incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The present application belongs to the field of communication technology, and specifically relates to a communication processing method and apparatus, an electronic device, and a readable storage medium. BACKGROUND

[0004] With the rapid development of communication technology, two identity recognition modules can be usually deployed in an electronic device to meet the demand of users for dual cards.

[0005] For the dual card capability of the combination of the existing processor and radio frequency chip, the electronic device can support a single receiver-dual SIM dual standby (SR-DSDS) mechanism, as shown in FIG. 1. In the SR-DSDS mode, when card two is paging, card one is allowed to completely disconnect the connection with the base station, that is, when card two is in an active state, card one is in an inactive state.

[0006] For the SR-DSDS, the electronic device can only use one frequency band under a network at the same time, while the dual receiver-dual SIM dual standby (DR-DSDS) mechanism allows the electronic device to use two different frequency bands under a network such as a 5G network at the same time, to realize the switching between different networks such as the 4th Generation (4G) and the 5th Generation (5G), as shown in FIG. 2.

[0007] For the DR-DSDS mechanism, the combination of the processor and the radio frequency chip needs to meet certain rules. For example, when card two is paging, card one needs to reserve the signal path of the main set antenna and give up the signal path of the original diversity antenna to card two for paging use. However, the current combination of the processor and the radio frequency chip cannot meet the rules due to the possible inability of the radio frequency front-end device to meet the rules, resulting in the failure of the DR-DSDS mechanism.

[0008] As shown in FIG. 2, the Subscriber Identity Module (SIM) 1 is defective in the Dynamic Time Allocation (DTA) process, i.e., paging of card 2 is monitored when card 1 is a Time Division Duplexing (TDD) frequency band. Since the paging time of Long Time Evolution (LTE) lasts for 5 ms, and the uplink and downlink switching time of TDD is also about this magnitude, if the switching period of card 1 is encountered during the paging of card 2, the connection of card 1 may be interrupted due to the false calling of a signal path, which leads to the failure of the DR-DSDS mechanism. SUMMARY

[0009] The embodiments of the present application provide a communication processing method and device, an electronic device and a readable storage medium, which can solve the technical problem that the DR-DSDS mechanism cannot be implemented due to the false calling of a signal path interrupting the connection of card 1 during the paging of card 2, so as to accurately implement the DR-DSDS mechanism.

[0010] In a first aspect, the embodiments of the present application provide a communication processing method applied to an electronic device, wherein the electronic device comprises a first Subscriber Identity Module (SIM) and a second SIM, and the method comprises the following steps.

[0011] In the case that the electronic device configures a signal path called by the first SIM and the second SIM, a path state of the signal path is acquired, and a configuration timing of the signal path is acquired.

[0012] Based on the path state and the configuration timing, a value of a target control bit in first path control information is configured to obtain second path control information, the target control bit is a control bit other than a first control bit in the first path control information, the first control bit corresponds to the path state, the value of the first control bit is used to control a first signal path of a main set antenna corresponding to the first SIM, and the value of the target control bit is used to control a signal path of a diversity antenna corresponding to a target SIM, the target SIM is the first SIM or the second SIM.

[0013] Based on the first SIM and the second SIM, a target signal path corresponding to the second path control information is called for communication processing, the target signal path comprises the first signal path and the signal path of the diversity antenna corresponding to the target SIM.

[0014] In a second aspect, an embodiment of the present application provides a communication processing apparatus applied to an electronic device, wherein the electronic device comprises a first identity recognition module and a second identity recognition module, and the apparatus comprises:

[0015] an acquisition module, configured to acquire a channel state of a signal channel and an acquisition time of the signal channel in a case where the electronic device configures the signal channel called by the first identity recognition module and the second identity recognition module;

[0016] a first configuration module, configured to configure a value of a target control bit in first channel control information based on the channel state and the acquisition time, to obtain second channel control information, the target control bit being a control bit other than a first control bit in the first channel control information, the first control bit corresponding to the channel state, the value of the first control bit being used to control a first signal channel of a main diversity antenna corresponding to the first identity recognition module, and the value of the target control bit being used to control a signal channel of a diversity antenna corresponding to a target identity recognition module, the target identity recognition module being the first identity recognition module or the second identity recognition module;

[0017] a communication processing module, configured to perform communication processing on a target signal channel corresponding to the second channel control information based on the first identity recognition module and the second identity recognition module, the target signal channel comprising the first signal channel and the signal channel of the diversity antenna corresponding to the target identity recognition module.

[0018] In a third aspect, an embodiment of the present application provides a communication processing circuit applied to an electronic device, wherein the circuit comprises a switching device, a main diversity antenna corresponding to a first identity recognition module in the electronic device and a diversity antenna corresponding to the first identity recognition module, a diversity antenna corresponding to a second identity recognition module in the electronic device, a first processing module, and a second processing module.

[0019] The switching device is configured to respectively establish a connection between the main diversity antenna corresponding to the first identity recognition module and the first processing module or the second processing module, a connection between the diversity antenna corresponding to the first identity recognition module and the first processing module or the second processing module, and a connection between the diversity antenna corresponding to the second identity recognition module and the first processing module or the second processing module.

[0020] The switching device is configured to control a signal channel called by the first identity recognition module and the second identity recognition module, the first processing module is configured to process a signal of a signal channel of the main diversity antenna, and the second processing module is configured to process a signal of a signal channel of the diversity antenna.

[0021] In a fourth aspect, an electronic device is provided, which includes a processor, a memory, and a program or instructions stored in the memory and executable on the processor, and the program or instructions, when executed by the processor, implement the steps of the communication processing method according to the first aspect.

[0022] In a fifth aspect, a readable storage medium is provided, which stores a program or instructions, and the program or instructions, when executed by a processor, implement the steps of the communication processing method according to the first aspect.

[0023] In a sixth aspect, a chip is provided, which includes a processor and a communication interface, the communication interface being coupled to the processor, and the processor being configured to execute a program or instructions to implement the steps of the communication processing method according to the first aspect.

[0024] In a seventh aspect, a computer program product is provided, which is stored in a storage medium and executed by at least one processor to implement the steps of the communication processing method according to the first aspect.

[0025] In the embodiments of the present application, in the case that the electronic device configures the signal path, the path state and the configuration timing of the signal path are obtained, the value of the target control bit in the first path control information is configured based on the path state and the configuration timing, the second path control information is obtained, and the target signal path corresponding to the second path control information is invoked for communication processing based on the first identity recognition module and the second identity recognition module. In this way, the value of the first path control information in the register of the radio frequency front-end device, i.e., the switch device, can be controlled bit by bit, so that the first signal path of the main set antenna corresponding to the first identity recognition module can be configured according to the path state and the configuration timing in the case that the first signal path is locked, and then the signal path invoked by the first identity recognition module and the second identity recognition module can be accurately configured before and after the card two paging and during the paging, so as to solve the technical problem that the DR-DSDS mechanism cannot be implemented due to the interruption of the card one connection caused by the mis-invocation of the signal path during the card two paging, and then the DR-DSDS mechanism can be accurately implemented. BRIEF DESCRIPTION OF DRAWINGS

[0026] FIG. 1 is a schematic diagram of the principle of the SR-DSDS mechanism;

[0027] FIG. 2 is a schematic diagram of the principle of the DR-DSDS mechanism;

[0028] FIG. 3 is a flowchart of the communication processing method according to some embodiments of the present application;

[0029] FIG. 4 is a structural schematic diagram of a communication processing circuit according to an embodiment of the present application;

[0030] FIG. 5 is a structural schematic diagram of a communication processing circuit according to some embodiments of the present application;

[0031] FIG. 6 is a flowchart of a communication processing method according to an embodiment of the present application;

[0032] FIG. 7 is a structural schematic diagram of a communication processing apparatus according to some embodiments of the present application;

[0033] FIG. 8 is a structural schematic diagram of an electronic device according to some embodiments of the present application;

[0034] FIG. 9 is a hardware structural schematic diagram of an electronic device according to some embodiments of the present application. DETAILED DESCRIPTION

[0035] The technical solutions in the embodiments of the present application will be described clearly below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art belong to the scope of protection of the present application.

[0036] The terms "first", "second", and the like in the specification of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than that illustrated or described herein, and the objects distinguished by "first", "second", and the like are generally of a kind and are not limited in number, for example, the first object can be one or more. In addition, "and / or" in the specification indicates at least one of the connected objects, and the character " / ", generally indicates that the front and rear associated objects are in an "or" relationship.

[0037] The communication processing method provided by the embodiments of the present application will be described in detail below with reference to the drawings, specific embodiments and application scenarios.

[0038] It should be noted that the communication processing method of the present embodiment is applied to an electronic device, and the electronic device comprises a first identity recognition module and a second identity recognition module.

[0039] The first identity recognition module is SIM1, i.e., card 1, and the second identity recognition module is SIM2, i.e., card 2. Card 1 and card 2 can respectively call one frequency band, and the frequency bands called by card 1 and card 2 can be different. For example, card 1 can call a low frequency (LB), and card 2 can call a mid-high frequency (MHB). This dual-card combination is a low frequency + mid-high frequency dual-card combination. For another example, card 1 calls a mid-high frequency, and card 2 calls a low frequency. This dual-card combination is a mid-high frequency + low frequency dual-card combination. Alternatively, card 1 calls a high frequency (HB), and card 2 calls a low frequency.

[0040] The communication modes of card 1 and card 2 can also be different. For example, the communication mode of card 1 can be LTE TDD, and the communication mode of card 2 can be new radio (NR). In some embodiments, the electronic device can deploy a dual-card combination in which the communication mode of card 1 is LTE TDD, the frequency band is HB, and the communication mode of card 2 is NR, and the frequency band is LB.

[0041] FIG. 3 is a flowchart of a communication processing method according to an embodiment of the present application. As shown in FIG. 3, the method includes the following steps:

[0042] In a case where the electronic device configures the signal paths called by the first identity recognition module and the second identity recognition module, the method includes the following steps:

[0043] The signal paths called by the first identity recognition module and the second identity recognition module can be controlled by a switching device. The switching device is used to control the signal paths called by the first identity recognition module and the second identity recognition module when the electronic device uses two types of frequency bands for communication.

[0044] The switching device can include at least three switches, and the switches can be double-pole switches. In some embodiments, the switching device can be a double-pole four-throw switch, such as a DP4T. The switching device can control the signal paths called by card 1 and card 2 through the value of a register to implement a DR-DSDS mechanism. That is, the electronic device configuring the signal paths called by the first identity recognition module and the second identity recognition module is essentially configuring the value of the register of the switching device, so that the switching device switches the signal paths called by the first identity recognition module and the second identity recognition module according to the DR-DSDS mechanism.

[0045] In the DR-DSDS mechanism, card one and card two can simultaneously call their corresponding frequency bands, and card two can periodically perform paging to listen to its messages. According to the rules of the combination of the processor and the radio frequency chip, before and after card two paging, card one can call the signal path of the card one corresponding main set antenna (PRx) and the signal path of the card one corresponding diversity antenna (DRx) to realize the communication processing of card one. When card two is paging, card one needs to reserve the signal path of the card one corresponding main set antenna and give up the signal path of its diversity antenna for card two to use for paging. Wherein, PRx can also be called TRx.

[0046] Table 1 is a configuration table of signal paths in the DR-DSDS mechanism, wherein 1TRx or 1PRx represents the signal path of the card one corresponding main set antenna, which can be simply referred to as TRx path or PRx path, 1DRx represents the signal path of the card one corresponding diversity antenna, which can be simply referred to as the DRx path of card one, and 2DRx represents the signal path of the card two corresponding diversity antenna, which can be simply referred to as the DRx path of card two. Wherein, 2DRx and 1DRx are different signal paths.

[0047] Table 1 is a configuration table of signal paths in the DR-DSDS mechanism

[0048] As shown in Table 1 above, before card two paging, the electronic device will configure the PRx path of card one and the DRx path of card one respectively, and the electronic device can configure through the register of the switching device. Since the design logic of the combination of the processor and the radio frequency chip is that the PRx path and the DRx path are respectively controlled by a separate register, the PRx path and the DRx path are only set when they are set. However, the switching device may not be able to distinguish, so the PRx path is set every time, which is equivalent to setting the TRx+DRx path completely. The DRx path is configured again, resulting in a total of two settings. In the single card state, the two times of writing register configuration should be the same, that is, the switching device is switched to the state of 1TRx+1DRx.

[0049] When card two is paging, the electronic device can configure the signal path, and card one can give up 1DRx and replace it with 2DRx for card two to use for paging.

[0050] After card two paging is completed, if there is no need to switch to the business scenario of card two, the electronic device needs to re-switch the signal path to the state of 1TRx+1DRx by the switching device.

[0051] It can be known that the signal path configuration needs to be performed before, during and after the second card paging, wherein the signal path configuration can be performed before the second card paging, such as when the SIM card is activated. The SIM card needs to be activated and the signal path configuration needs to be performed when the SIM card is inserted into the electronic device, the electronic device is powered on, and the electronic device is switched from the flight mode to the communication mode.

[0052] In the case that the electronic device performs the signal path configuration, the path state and the configuration timing of the signal path can be acquired. Since the value in the register of the switching device reflects the connection state of the switching device, in some embodiments, the path state can be determined by reading the value of all control bits or part of control bits in the register of the switching device, such as in the case that the electronic device determines that the path state does not change.

[0053] In some embodiments, due to the change of the use environment of the electronic device, the path state can need to change from the pass-through state to the cross state, or switch from the cross state to the pass-through state, at this time, the electronic device can detect the change of the environment and determine the path state switched to currently, thereby acquiring the path state of the signal path.

[0054] The configuration timing can be determined by the information sent by the base station or the second card paging period. For example, when the first card or the second card is activated, the base station can send some related information to the electronic device, and the electronic device can perform the signal path configuration and determine that the configuration timing thereof is before the second card paging in the case that the information is received. For another example, when the second card paging period arrives, the configuration timing is during the second card paging, and when the second card paging ends, the configuration timing is after the second card paging.

[0055] The path state can be determined by reading the value of part of control bits in the register of the switching device, and optionally, in the case that the electronic device determines that the path state of the signal path does not change, the step 301 specifically includes:

[0056] In the case that the first target bit in the first path control information is the first preset information, it is determined that the path state is the cross state.

[0057] In the case that the first target bit is not the first preset information and the second target bit in the first path control information is the second preset information, it is determined that the path state is the pass-through state.

[0058] The first target bit refers to a bit for controlling the first signal path of the main set antenna corresponding to the first identity recognition module in the cross state, and the second target bit refers to a bit for controlling the first signal path of the main set antenna corresponding to the first identity recognition module in the straight-through state. The first preset information indicates that the first signal path of the main set antenna corresponding to the first identity recognition module is open in the cross state, and the second preset information indicates that the first signal path of the main set antenna corresponding to the first identity recognition module is open in the straight-through state.

[0059] In some embodiments, FIG. 4 is a structural schematic diagram of a communication processing circuit provided by some embodiments of the present application, the dual-card combination of the electronic device is a middle-high frequency + low frequency dual-card combination, the switching device in the communication processing circuit can be a DP4T, and the purpose of the communication processing method is to control the switching device by configuring the value in the register, so that the signal path in the communication processing circuit called by the first identity recognition module and the second identity recognition module meets the DR-DSDS mechanism.

[0060] DP4T is a double-pole four-throw switch, the conduction relationship of DP4T in the straight-through state is RF OUT2-RF IN2, to open the PRx path of card one, and RF OUT1-RF IN1, to open the DRx path of card one. In the cross state, the roles of the main set antenna and the diversity antenna of card one are interchanged, the conduction relationship of DP4T is RF OUT2-RF IN1, to open the PRx path of card one, and RF OUT1-RF IN2, to open the DRx path of card one.

[0061] When card two performs paging, according to the rules of the processor and the radio frequency chip combination, card one needs to reserve the PRx path and give up the original DRx path for card two to perform paging, the conduction relationship of DP4T can be RF OUT2-RF IN2 and RF OUT1-RF IN3, to disconnect the DRx path of card one and open the DRx path of card two.

[0062] In the communication processing circuit as shown in FIG. 4, the signal path can be set according to the value in the register of the switching device shown in Table 2 or Table 3 below.

[0063] Table 2 DP4T register truth table one

[0064] Table 3 DP4T register truth table two

[0065] In Table 2 and Table 3 above, Isolation indicates that RF OUT is disconnected and does not connect any RF IN. The first path control information can be the value of register_01.

[0066] From the register feature of DP4T, bit5 / 4 of register_00, register_01 can control the flip of RF OUT, as shown in Table 3, it can be seen that register_00 write 1, register_01 write 000010 can refer to the on-off relationship of DP4T is RF OUT1-isolation, while RF OUT2-RF IN2; At the same time, register_00 write 1, register_01 write 000001 can refer to the on-off relationship of DP4T is RF OUT1-isolation, while RF OUT2-RF IN1. Then the pass-through state of TRX only configures bit1 of register_01, and the cross state only configures bit0 of register_01, if this logic is true in all scenarios, then the effect similar to the sub-register control can be achieved.

[0067] Register_01 bit1 set to 1 does not represent RF OUT2-RF IN2, the following possibilities can be sorted out:

[0068] 1、000010, refers to RF OUT1-isolation / RF OUT2-RF IN2;

[0069] 2、010011, refers to RF OUT1-RF IN2 / RF OUT2-RF IN1;

[0070] 3、010110, refers to RF OUT1-RF IN3 / RF OUT2-RF IN2;

[0071] 4、011010, refers to RF OUT1-RF IN4 / RF OUT2-RF IN2;

[0072] 5、100011, refers to RF OUT1-RF IN1 / RF OUT2-RF IN2;

[0073] 6、100110, refers to RF OUT1-RF IN2 / RF OUT2-RF IN3;

[0074] 7、101010, refers to RF OUT1-RF IN2 / RF OUT2-RF IN4;

[0075] 8、110010, refers to RF OUT1-RF IN2 / RF OUT2-isolation.

[0076] The 2nd, 6th, 7th and 8th items cannot represent RF OUT2-RF IN2. After demonstration, as shown in the scenario of FIG. 4, only the 1st, 3rd and 5th items exist, so that bit1 set to 1 can strictly represent RF OUT2-RF IN2, but bit0 set to 1 cannot strictly represent RF OUT2-RF IN1, for example, the 5th item does not conform.

[0077] It can be found through observation that in the cross state scenario, if the bit5 / 4 / 0 of the control register_01 is written as 0 / 1 / 1, for example, according to the truth table, the following scenarios can occur:

[0078] 1, 010011, representing RF OUT1-RF IN2 / RF OUT2-RF IN1;

[0079] 2, 010101, representing RF OUT1-RF IN3 / RF OUT2-RF IN1;

[0080] 3, 011001, representing RF OUT1-RF IN4 / RF OUT2-RF IN1.

[0081] The three scenarios all correspond to RF OUT2-RF IN1, that is, the PRx path in the cross state is locked.

[0082] The BIT 5 / 4 state can be locked in the cross state scenario, and the reasons are as follows:

[0083] As shown in Table 3, when the value of register_01 is 010011, card one is in the cross state, and 010101 / 011001 is the PRx path of card one in the cross state. The DRx path of card one is switched to the DRx path of card two for paging listening of card two.

[0084] The BIT5 / 4 cannot be locked in the straight-through state, and the reasons are as follows:

[0085] As shown in Table 3, when the value of register_01 is 100011, card one is in the straight-through state. If BIT5 / 4 / 1 is locked, in the register value of 10xx1x, that is, BIT5 / 4 does not change, RF OUT1 cannot be switched to communication with RF IN3 / RF IN4 to switch to the DRx path of card two for paging of card two, so the straight-through state cannot control the three bits of the register to achieve.

[0086] In some embodiments, when the value of the register_00 is 1, the first target bit can be BIT5 / 4 / 0, i.e., the first target bit includes the sixth bit, the fifth bit and the first bit of the register_01. The first preset information can be 011, in which case, the path state of the signal path can be determined as the cross state. The second target bit can be BIT1, i.e., the second target bit is the second bit of the register_01, and the second preset information can be 1. In the case where BIT5 / 4 / 0 is not 011 but BIT1 is 1, the path state of the signal path can be determined as the straight-through state.

[0087] It should be noted that the first target bit, the second target bit, the first preset information and the second preset information can be set according to the value of the register_00, the number and value of the control bits of the register_01 and other information. The setting of the first target bit, the second target bit, the first preset information and the second preset information described above is only an example, and the principle is to summarize the value of the truth table to achieve the control logic that the PRx path of card one remains unchanged and another signal path can be switched according to the path state and the configuration timing under the setting.

[0088] Optionally, the first path control information is represented in binary, and the first target bit and the second target bit are any of the following cases:

[0089] The first target bit includes the sixth bit, the fifth bit and the first bit of the first path control information, and the second target bit is the second bit of the first path control information;

[0090] The first target bit is the second bit of the first path control information, and the second target bit includes the sixth bit, the fifth bit and the first bit of the first path control information.

[0091] In some embodiments, when the value of the register_00 is 1, the first target bit is BIT5 / 4 / 0, the first preset information is 011, the second target bit is BIT1, and the second preset information is 1. In some embodiments, when the value of the register_00 is 0, the first target bit is BIT1, the first preset information is 1, the second target bit is BIT5 / 4 / 0, and the second preset information is 011. The value of the register_00 can be determined in advance and written.

[0092] In this embodiment, the path state of the signal path is determined by reading the values of the first target bit and the second target bit in the first path control information, so that the acquisition of the path state can be easily realized. In this case, the value of the first control bit in the first path control information does not need to be reconfigured. Since the value of the first control bit can be used to control the first signal path of the main set antenna corresponding to the first identity recognition module, the PRx path of card one remains unchanged.

[0093] In step 302, based on the channel state and the configuration timing, a value of a target control bit in the first channel control information is configured to obtain second channel control information, the target control bit is a control bit in the first channel control information other than the first control bit, the first control bit corresponds to the channel state, and the value of the first control bit is used to control the first signal channel of the main diversity antenna corresponding to the first identity recognition module to be opened, and the value of the target control bit is used to control the signal channel of the target identity recognition module corresponding to the diversity antenna to be opened, the target identity recognition module being the first identity recognition module or the second identity recognition module.

[0094] In the related art, after the card two paging is ended, the card one will issue an instruction to obtain the control right, that is, the PRx channel is configured to issue a command once, and the switch device realizes the 1TRx+1DRx channel effect. The DRx channel is configured to issue a command once again, and the switch device realizes the 1TRx+1DRx channel effect.

[0095] Essentially, this way establishes a mapping according to the current state of the card one to determine the paging instruction of the card two. However, this way has defects when the card one is a TDD frequency band, because the paging time of the LTE lasts for 5 ms, and the uplink and downlink switching time of the TDD is also about this magnitude. If the card one switching period is encountered during the card two paging, the instruction conflict will occur.

[0096] As shown in Table 4, during the card two paging, the switch device will be set by two instructions, that is, the card one PRx channel configuration will configure the switch device to be in the 1TRx+1DRx state, and the card two paging will configure the switch device to be in the 1TRx+2DRx state. If the PRx channel configuration of the card one finally occupies this paging period, the paging channel of the card two will be interrupted, resulting in paging failure.

[0097] Table 4 is one of the configuration tables of the error signal channel in the DR-DSDS mechanism

[0098] To ensure that the PRx channel configuration instruction of the card one and the DRx channel configuration instruction of the card two are consistent during the card two paging, the switch device can be switched to the 1TRx+2DRx state during the PRx channel configuration of the card one. At this time, the configuration table is shown in Table 5. This instruction will cause the conflict between the PRx channel configuration instruction and the DRx channel configuration instruction of the card one before and after the card two paging, and the card one will directly lose the DRx channel performance.

[0099] Table 5 is the second configuration table of the error signal channel in the DR-DSDS mechanism

[0100] And in the related art, from the above table 2 and table 3, it can be seen that when card two is paged, the truth table needs to be carefully searched to configure a card two DRx channel, and ensure that this signal channel can meet the configuration of 1TRx+2DRx.

[0101] In some embodiments, as shown in table 2, if register_01 jumps to 011100 state, at this time, the conduction relationship of the switching device is RF OUT2-RF IN4 and RF OUT1-RF IN3, and after card two paging is completed, the PRx channel of card one is disconnected, which does not meet the rules of the combination of the processor and the radio frequency chip, and then after card two paging is completed, card one will be dropped due to the disconnection of the signal channel.

[0102] That is, since the two signal channels between the RF IN and RF OUT ports of the DP4T are switched as a whole according to the value of the register_01, they are not realized by bit control or sub-register control, so it is not possible to simply realize the control logic that one signal channel, the PRx channel of card one, remains unchanged, and the other signal channel is switched according to the requirements, which may lead to the failure to meet the rules of the combination of the processor and the radio frequency chip due to the error jump of the register, and the DR-DSDS mechanism cannot be realized.

[0103] In the embodiment, in the case of determining the channel state, the first control bit and the value of the first control bit can be determined, and in the case of determining the value of the first control bit, it can be ensured that the PRx channel of card one remains unchanged. Correspondingly, the target control bit in the first channel control information can be determined based on the channel state, and then the value of the target control bit in the first channel control information is configured according to the channel state and the configuration opportunity. In this way, the configuration of the first channel control information is realized by a similar bit configuration manner, so that the PRx channel of card one can remain unchanged, and the control logic of the other signal channel, such as the DRx channel of card one or the DRx channel of card two, can be switched according to the requirements, so that the rules of the combination of the processor and the radio frequency chip can be broken through, and the DR-DSDS capability can be realized.

[0104] It should be noted that in the case where the electronic device learns that the channel state of the signal channel changes, such as switching from a straight-through state to a cross state. Alternatively, in the case where the electronic device determines that the channel state of the signal channel changes, before the step 301, the method further comprises:

[0105] Based on the channel state, the value of the first control bit in the first channel control information is configured.

[0106] In this case, the value of the first control bit in the first path control information also needs to be reconfigured. In some embodiments, for example, the value of the register_00 is 1, when the path state switches to the cross state, the first control bit is BIT5 / 4 / 0, and its value can be configured as 011 to ensure that the PRx path of card one is opened; when the path state switches to the straight-through state, the first control bit is BIT1, and its value can be configured as 1 to ensure that the PRx path of card one is opened. In some embodiments, for example, the value of the register_00 is 0, when the path state switches to the cross state, the first control bit is BIT1, and its value can be configured as 1 to ensure that the PRx path of card one is opened; when the path state switches to the straight-through state, the first control bit is BIT5 / 4 / 0, and its value can be configured as 011 to ensure that the PRx path of card one is opened.

[0107] In some embodiments, for example, the value of the register_00 is 1, when the path state is the cross state, the target control bit is BIT3 / 2 / 1, and when the path state is the straight-through state, the target control bit is BIT5 / 4 / 3 / 2 / 0.

[0108] For example, the value of the register_00 is 0, when the path state is the cross state, the target control bit is BIT5 / 4 / 3 / 2 / 0, and when the path state is the straight-through state, the target control bit is BIT3 / 2 / 1.

[0109] In some embodiments, the value of the target control bit can be configured as a whole or can be split and configured.

[0110] In some embodiments, for example, the value of the register_00 is 1, and optionally, the step 302 specifically includes:

[0111] In the case where the path state indicates that the signal path is in the cross state, based on the configuration timing, the values of the second control bit and the third control bit in the first path control information are configured respectively to obtain second path control information, and the target control bit includes the second control bit and the third control bit;

[0112] In the case where the path state indicates that the signal path is in the straight-through state, based on the configuration timing, the values of the fourth control bit and the third control bit in the first path control information are configured respectively to obtain second path control information, and the target control bit includes the third control bit and the fourth control bit;

[0113] In some embodiments, for example, the value of the register_00 is 1, when the path state switches to the cross state, the first control bit is BIT5 / 4 / 0, and its value can be configured as 011 to ensure that the PRx path of card one is opened; when the path state switches to the straight-through state, the first control bit is BIT1, and its value can be configured as 1 to ensure that the PRx path of card one is opened. In some embodiments, for example, the value of the register_00 is 0, when the path state switches to the cross state, the first control bit is BIT1, and its value can be configured as 1 to ensure that the PRx path of card one is opened; when the path state switches to the straight-through state, the first control bit is BIT5 / 4 / 0, and its value can be configured as 011 to ensure that the PRx path of card one is opened.

[0114] In the case that the path state indicates that the signal path is in the cross state, the value of the second control bit, BIT1, in the first path control information can be configured as 1 and the value of the third control bit, BIT3 / 2, in the first path control information can be configured as 00 at the configuration timing before and after the paging of the second card, so that the second path control information is 010011, and the signal path of the diversity antenna corresponding to the first identity recognition module can be opened, as shown in Table 3, the conduction relationship of the switching device is RF OUT2-RF IN1 (the PRx path of the first card) and RF OUT1-RF IN2 (the DRx path of the first card).

[0115] In the case that the path state indicates that the signal path is in the cross state, the value of the second control bit, BIT1, in the first path control information can be configured as 0 and the value of the third control bit, BIT3 / 2, in the first path control information can be configured as 01 or 10 at the configuration timing of the paging of the second card, so that the second path control information is 010101 or 011001, and the signal path of the diversity antenna corresponding to the second identity recognition module can be opened, as shown in Table 3, the conduction relationship of the switching device is RF OUT2-RF IN1 (the PRx path of the first card) and RF OUT1-RF IN3 (the DRx path of the second card), or RF OUT2-RF IN1 (the PRx path of the first card) and RF OUT1-RF IN4 (the DRx path of the second card).

[0116] In the case that the path state indicates that the signal path is in the cross state, the value of the second control bit, BIT1, in the first path control information can be configured as 0 and the value of the third control bit, BIT3 / 2, in the first path control information can be configured as 01 or 10 at the configuration timing of the paging of the second card, so that the second path control information is 010101 or 011001, and the signal path of the diversity antenna corresponding to the second identity recognition module can be opened, as shown in Table 3, the conduction relationship of the switching device is RF OUT2-RF IN1 (the PRx path of the first card) and RF OUT1-RF IN3 (the DRx path of the second card), or RF OUT2-RF IN1 (the PRx path of the first card) and RF OUT1-RF IN4 (the DRx path of the second card).

[0117] In the configuration occasion is card two paging, the value of the fourth control bit in the first path control information, that is, the value of BIT5 / 4 / 0, can be configured as 010, and the value of the third control bit in the first path control information, that is, BIT3 / 2, can be configured as 01 or 10, so that the second path control information is 010110 / 011010, so that the signal path of the diversity antenna corresponding to the second identity recognition module can be opened, as shown in Table 3, the conduction relationship of the switching device is RF OUT2-RF IN2 (PRx path of card one) and RF OUT1-RF IN3 (DRx path of card two), or RF OUT2-RF IN2 (PRx path of card one) and RF OUT1-RF IN4 (DRx path of card two).

[0118] In the embodiment, the configuration of the target control bit value can be simplified by splitting the value of the target control bit.

[0119] In the embodiment, the PRx path of card one is kept in the straight-through state by BIT1, and the PRx path of card one is kept in the cross state by BIT5 / 4 / 0, and the logical switching of another signal path before and after card two paging is realized by configuring the value of the target control bit, which can solve the technical problem that DR-DSDS is not supported in the dual-card combination such as card one LTE TDD HB+card two NR LB dual-card combination. For each low frequency+medium-high frequency or medium-high frequency+low frequency dual-card combination scenario, the method of the embodiment can effectively cover and solve. In actual measurement, for low frequency+medium-high frequency or medium-high frequency+low frequency dual-card combination, the on rate of card two and the throughput rate of card one are normal in the traversal stress test of the straight-through state and the cross state of non-signaling and analog network signaling, which can prove the robustness of the scheme. Moreover, the uplink and downlink switching of card one TDD frequency band will not interrupt the paging state of card two.

[0120] In step 303, based on the first identity recognition module and the second identity recognition module, the second path control information corresponding to the target signal path is called for communication processing, and the target signal path includes the first signal path and the signal path of the diversity antenna corresponding to the target identity recognition module.

[0121] In the case of configuring the second path control information, the switching device can switch states based on the second path control information to switch the signal path to the target signal path, and then based on the first identity recognition module and the second identity recognition module, the target signal path can be called for communication processing.

[0122] Optionally, the step 303 specifically includes any one of the following:

[0123] Based on the first identity recognition module, the first signal channel and the second signal channel are called to perform communication processing, and the second signal channel is a signal channel of a diversity antenna corresponding to the first identity recognition module.

[0124] Based on the first identity recognition module, the first signal channel is called to perform communication processing, and based on the second identity recognition module, the third signal channel is called to perform communication processing, and the third signal channel is a signal channel of a diversity antenna corresponding to the second identity recognition module.

[0125] When the configuration timing is before and after card two paging, the second communication control information needs to be configured so that the target signal channel includes the first signal channel and the second signal channel, and the switch device is switched to the state of the target signal channel, and when the configuration timing is card two paging, the second communication control information needs to be configured so that the target signal channel includes the first signal channel and the third signal channel, thereby realizing the DR-DSDS mechanism.

[0126] In the embodiment, when the electronic device performs signal channel configuration, the channel state and the configuration timing of the signal channel are obtained, the value of the target control bit in the first channel control information is configured based on the channel state and the configuration timing to obtain the second channel control information, and based on the first identity recognition module and the second identity recognition module, the target signal channel corresponding to the second channel control information is called to perform communication processing. In this way, the value of the first channel control information in the register of the radio frequency front-end device, i.e., the switch device, can be controlled bit by bit, so that when the first signal channel of the main diversity antenna corresponding to the first identity recognition module is locked, another signal channel can be configured according to the channel state and the configuration timing, and then the signal channel called by the first identity recognition module and the second identity recognition module can be accurately configured before and after card two paging and paging, thereby solving the technical problem that the DR-DSDS mechanism cannot be realized due to the interruption of card one connection caused by the mis-call of the signal channel in the card two paging process, and accurately realizing the DR-DSDS mechanism.

[0127] As shown in FIG. 5, the embodiment further provides a communication processing circuit applied to an electronic device, wherein the electronic device further includes a first identity recognition module and a second identity recognition module, and the circuit includes a switch device 501, a main diversity antenna 502 and a diversity antenna 503 corresponding to the first identity recognition module, a diversity antenna 504 corresponding to the second identity recognition module, a first processing module 505, and a second processing module 506.

[0128] The switch device 501 is used for connecting the main diversity antenna 502 corresponding to the first identity recognition module with the first processing module 505 or the second processing module 506, connecting the diversity antenna 503 corresponding to the first identity recognition module with the first processing module 505 or the second processing module 506, and connecting the diversity antenna 504 corresponding to the second identity recognition module with the first processing module 505 or the second processing module 506.

[0129] The switch device 501 is used for controlling the signal paths called by the first identity recognition module and the second identity recognition module, the first processing module 505 is used for processing the signals of the signal paths of the main diversity antenna, and the second processing module 506 is used for processing the signals of the signal paths of the diversity antenna.

[0130] The antenna corresponding to the first identity recognition module has a different frequency band from the antenna corresponding to the second identity recognition module, the antenna corresponding to the first identity recognition module has a first frequency band, such as an MHB frequency band, and the antenna corresponding to the second identity recognition module has a second frequency band, such as an LB frequency band.

[0131] Optionally, the number of the diversity antenna corresponding to the second identity recognition module is two, or, as shown in FIG. 5, the circuit further includes a main diversity antenna 507 corresponding to the second identity recognition module.

[0132] The switch device is a double-pole four-throw switch, and in the case that the circuit further includes the main diversity antenna corresponding to the second identity recognition module, the switch device is also used for connecting the main diversity antenna corresponding to the second identity recognition module with the first processing module or the second processing module.

[0133] The role of the main diversity antenna 507 corresponding to the second identity recognition module can also be switched to a diversity antenna.

[0134] In this embodiment, the first processing module and the second processing module are connected with the antennas split from the first frequency band, such as an MHB frequency band, and the second frequency band, such as an LB frequency band, through a switch device, such as a DP4T, and the material of the antennas can be die-cast aluminum. This architecture has benefits in architecture loss by using the connection scheme of the DP4T, which is very helpful for improving the communication performance.

[0135] The first processing module can include a frequency selection switch, such as a PH2 TXM, and the second processing module can include a diversity switch single-port device, such as a DRX SP8T. The PH2 TXM and the DRX SP8T can be connected with the antennas split from the first frequency band, such as an MHB frequency band, and the second frequency band, such as an LB frequency band, through the DP4T.

[0136] It should be noted that when the switch device is controlled, the main diversity antenna will not be connected to the second processing module. When the physical antenna is connected to the second processing module, its definition will be changed to diversity antenna. That is, the main / diversity definition of the antenna will change following the change of the processing module to which it is connected. In the logical control of the switch device, the main diversity antenna of card one will only be connected to the first processing module, and the diversity antenna of card one will only be connected to the second processing module. When card two is paged, the diversity antenna of card two is connected to the second processing module, and at this time, the connection of the diversity antenna of card one to the second processing module is disconnected.

[0137] Fig. 4 is a structural schematic diagram of the communication processing circuit of the specific example of the embodiment one. The flow of the communication processing method in the embodiment is described in detail with Fig. 4 and Table 3 as examples. The specific steps are as follows.

[0138] Step 601, in the case that the electronic device determines that the channel state has not changed, the information of BIT5 / 4 / 0 in the first channel control information is read, and it is determined whether the information is 011; if yes, step 602 is executed; if not, step 606 is executed.

[0139] Step 602, it is determined that the channel state is cross state.

[0140] Step 603, it is determined whether the configuration opportunity is card two paging; if yes, step 604 is executed; if not, step 605 is executed.

[0141] Step 604, if paged from ANT1, the value of BIT3 / 2 is configured as 01; if paged from ANT3, the value of BIT3 / 2 is configured as 10; BIT1 is configured as 0.

[0142] Step 605, the value of BIT3 / 2 is configured as 00, and BIT1 is configured as 1.

[0143] Step 606, the information of BIT1 in the first channel control information is read, and it is determined whether the information is 1; if yes, step 607 is executed; if not, step 611 is executed.

[0144] Step 607, it is determined that the channel state is straight-through state.

[0145] Step 608, it is determined whether the configuration opportunity is card two paging; if yes, step 609 is executed; if not, step 610 is executed.

[0146] Step 609, if paged from ANT1, the value of BIT3 / 2 is configured as 01; if paged from ANT3, the value of BIT3 / 2 is configured as 10; BIT5 / 4 / 0 is configured as 010.

[0147] Step 610, if paging from ANT1, configuring the value of BIT3 / 2 as 01; if paging from ANT3, configuring the value of BIT3 / 2 as 10; configuring BIT5 / 4 / 0 as 101;

[0148] Step 611, determining that it is an error logic and not included in the conversion state of the software.

[0149] It should be noted that the communication processing method provided in the embodiments of the present application can be executed by a communication processing device or a control module in the communication processing device for executing the communication processing method. In the embodiments of the present application, the communication processing device is taken as an example to execute the communication processing method, and the communication processing device provided in the embodiments of the present application is described.

[0150] Referring to FIG. 7, FIG. 7 is a structural schematic diagram of a communication processing device provided in the embodiments of the present application. The electronic device includes a first identity recognition module and a second identity recognition module, and the device includes:

[0151] The acquisition module 701 is configured to, in a case where the electronic device configures a signal path called by the first identity recognition module and the second identity recognition module, acquire a path state of the signal path and acquire a configuration timing of the signal path.

[0152] The first configuration module 702 is configured to, based on the path state and the configuration timing, configure a value of a target control bit in first path control information to obtain second path control information, the target control bit being a control bit other than a first control bit in the control bits of the first path control information, the first control bit corresponding to the path state, the value of the first control bit being used to control a first signal path of a main set antenna corresponding to the first identity recognition module to be opened, and the value of the target control bit being used to control a signal path of a diversity antenna corresponding to a target identity recognition module to be opened, the target identity recognition module being the first identity recognition module or the second identity recognition module.

[0153] The communication processing module 703 is configured to, based on the first identity recognition module and the second identity recognition module, invoke a target signal path corresponding to the second path control information to perform communication processing, the target signal path including the first signal path and the signal path of the diversity antenna corresponding to the target identity recognition module.

[0154] Optionally, in a case where the electronic device determines that the path state of the signal path has not changed, the acquisition module 701 is specifically configured to:

[0155] In a case where the first target bit in the first path control information is first preset information, it is determined that the path state is a cross state.

[0156] In a case where the first target bit is not the first preset information and a second target bit in the first path control information is second preset information, it is determined that the path state is a pass-through state.

[0157] Optionally, the first path control information is represented by binary, and the first target bit and the second target bit are any of the following cases:

[0158] The first target bit includes a sixth bit, a fifth bit and a first bit in the first path control information, and the second target bit is a second bit in the first path control information.

[0159] The first target bit is a second bit in the first path control information, and the second target bit includes a sixth bit, a fifth bit and a first bit in the first path control information.

[0160] Optionally, the apparatus further includes:

[0161] A second configuration module, configured to configure values of the first control bits in the first path control information based on the path state.

[0162] Optionally, the first configuration module 702 is specifically configured to:

[0163] In a case where the path state indicates that the signal path is a cross state, values of a second control bit and a third control bit in the first path control information are configured based on the configuration timing to obtain second path control information, and the target control bits include the second control bit and the third control bit.

[0164] In a case where the path state indicates that the signal path is a pass-through state, values of a fourth control bit and the third control bit in the first path control information are configured based on the configuration timing to obtain second path control information, and the target control bits include the third control bit and the fourth control bit.

[0165] The second control bit is a second bit in the first path control information, the third control bit includes a fourth bit and a third bit in the first path control information, and the fourth control bit includes a sixth bit, a fifth bit and a first bit in the first path control information.

[0166] Optionally, the communication processing module 703 is specifically configured to any of the following:

[0167] Based on the first identity recognition module, the first signal path and a second signal path are called for communication processing, and the second signal path is a signal path of a diversity antenna corresponding to the first identity recognition module.

[0168] Based on the first identity recognition module, a third signal path is called for communication processing based on the second identity recognition module, and the third signal path is a signal path of a diversity antenna corresponding to the second identity recognition module.

[0169] In the embodiment, when the electronic device configures the signal path, the path state and the configuration opportunity of the signal path are obtained, the value of the target control bit in the first path control information is configured based on the path state and the configuration opportunity, the second path control information is obtained, and the target signal path corresponding to the second path control information is called for communication processing based on the first identity recognition module and the second identity recognition module. In this way, the value of the first path control information in the register of the radio frequency front-end device, i.e., the switch device, can be controlled bit by bit, so that the first signal path of the main diversity antenna corresponding to the first identity recognition module can be configured according to the path state and the configuration opportunity in the case of being locked, and then the signal path called by the first identity recognition module and the second identity recognition module can be accurately configured before and after the card two paging and during the paging, thereby solving the technical problem that the DR-DSDS mechanism cannot be implemented due to the interruption of the card one connection caused by the mis-calling of the signal path in the card two paging process, and then accurately implementing the DR-DSDS mechanism.

[0170] The communication processing apparatus in the embodiment of the application can be an apparatus, a component, an integrated circuit, or a chip in the communication processing apparatus. The communication processing apparatus can be a mobile electronic device or a non-mobile electronic device. For example, the mobile electronic device can be a mobile phone, a tablet computer, a notebook computer, a palm computer, a vehicle-mounted electronic device, a wearable device, an ultra-mobile personal computer (UMPC), a netbook, or a personal digital assistant (PDA), and the non-mobile electronic device can be a server, a network attached storage (NAS), a personal computer (PC), a television (TV), a teller machine, or a self-service machine. The embodiment of the application is not limited in this regard.

[0171] The communication processing apparatus in the embodiment of the application can be an apparatus with an operating system. The operating system can be an Android operating system, an ios operating system, or another possible operating system. The embodiment of the application is not limited in this regard.

[0172] The communication processing apparatus provided in the embodiments of the present application can realize each process of the method embodiment of FIG. 3, and achieve the same technical effects. To avoid repetition, details are not described herein.

[0173] Optionally, as shown in FIG. 8, the embodiments of the present application further provide an electronic device 800, which includes a processor 801, a memory 802, and a program or instruction stored in the memory 802 and executable on the processor 801. When the program or instruction is executed by the processor 801, each process of the above communication processing method embodiment is realized, and the same technical effects can be achieved. To avoid repetition, details are not described herein.

[0174] It should be noted that the electronic device in the embodiments of the present application includes the mobile electronic device and the non-mobile electronic device described above.

[0175] FIG. 9 is a schematic diagram of a hardware structure of an electronic device for implementing the embodiments of the present application.

[0176] The electronic device 900 includes, but is not limited to, a radio frequency unit 901, a network module 902, an audio output unit 903, an input unit 904, a sensor 905, a display unit 906, a user input unit 907, an interface unit 908, a memory 909, and a processor 910, etc. The electronic device further includes a first identity recognition module and a second identity recognition module.

[0177] Those skilled in the art can understand that the electronic device 900 can further include a power supply (such as a battery) for supplying power to each component. The power supply can be logically connected to the processor 910 through a power management system, so as to realize functions such as management of charging, discharging, and power consumption management through the power management system. The electronic device structure shown in FIG. 9 does not constitute a limitation on the electronic device, and the electronic device can include more or fewer components than shown, or combine certain components, or different component arrangements, which are not described herein.

[0178] The processor 910 is configured to:

[0179] In a case where the electronic device configures a signal path called by the first identity recognition module and the second identity recognition module, a path state of the signal path is acquired, and a configuration timing of the signal path is acquired.

[0180] configure a value of a target control bit in first path control information based on the path state and the configuration timing, to obtain second path control information, the target control bit being a control bit in the first path control information other than a first control bit, the first control bit corresponding to the path state, the value of the first control bit being used to control opening of a first signal path of a main diversity antenna corresponding to the first identity recognition module, the value of the target control bit being used to control opening of a signal path of a diversity antenna corresponding to a target identity recognition module, the target identity recognition module being the first identity recognition module or the second identity recognition module;

[0181] based on the first identity recognition module and the second identity recognition module, invoke a target signal path corresponding to the second path control information for communication processing, the target signal path including the first signal path and the signal path of the diversity antenna corresponding to the target identity recognition module.

[0182] In the embodiment, in the case where the electronic device performs signal path configuration, the path state and the configuration timing of the signal path are obtained, the value of the target control bit in the first path control information is configured based on the path state and the configuration timing, to obtain the second path control information, and the target signal path corresponding to the second path control information is invoked for communication processing based on the first identity recognition module and the second identity recognition module. In this way, the value of the first path control information in the register of the radio frequency front-end device, i.e., the switch device, can be controlled bit by bit, so that in the case where the first signal path of the main diversity antenna corresponding to the first identity recognition module is locked, another signal path can be configured according to the path state and the configuration timing, and then the signal path invoked by the first identity recognition module and the second identity recognition module can be accurately configured before and after card two paging and during paging, to solve the technical problem that the DR-DSDS mechanism cannot be implemented due to the interruption of card one connection caused by the misinvocation of the signal path during card two paging, and then the DR-DSDS mechanism can be accurately implemented.

[0183] Optionally, in the case where the electronic device determines that the path state of the signal path has not changed, the processor 910 is further configured to:

[0184] in the case where the first target bit in the first path control information is first preset information, determine that the path state is a cross state;

[0185] in the case where the first target bit is not the first preset information, and a second target bit in the first path control information is second preset information, determine that the path state is a straight-through state.

[0186] Optionally, the first pass control information is represented by binary, the first target bit and the second target bit are any of the following cases:

[0187] The first target bit includes a sixth bit, a fifth bit and a first bit in the first pass control information, and the second target bit is a second bit in the first pass control information.

[0188] The first target bit is a second bit in the first pass control information, and the second target bit includes a sixth bit, a fifth bit and a first bit in the first pass control information.

[0189] Optionally, in a case where the electronic device determines that the pass state of the signal pass changes, the processor 910 is further configured to:

[0190] Configure a value of the first control bit in the first pass control information based on the pass state.

[0191] Optionally, the processor 910 is further configured to:

[0192] In a case where the pass state indicates that the signal pass is in the cross state, configure a value of a second control bit and a value of a third control bit in the first pass control information based on the configuration timing to obtain second pass control information, and the target control bit includes the second control bit and the third control bit.

[0193] In a case where the pass state indicates that the signal pass is in the straight-through state, configure a value of a fourth control bit and a value of the third control bit in the first pass control information based on the configuration timing to obtain second pass control information, and the target control bit includes the third control bit and the fourth control bit.

[0194] The second control bit is a second bit in the first pass control information, the third control bit includes a fourth bit and a third bit in the first pass control information, and the fourth control bit includes a sixth bit, a fifth bit and a first bit in the first pass control information.

[0195] Optionally, the processor 910 is further configured to:

[0196] Based on the first identity recognition module, call the first signal pass and the second signal pass for communication processing, and the second signal pass is a signal pass of a diversity antenna corresponding to the first identity recognition module.

[0197] Based on the first identity recognition module, a first signal path is called to perform communication processing, and based on the second identity recognition module, a third signal path is called to perform communication processing, the third signal path being a signal path of a diversity antenna corresponding to the second identity recognition module.

[0198] It should be understood that in the embodiments of the present application, the input unit 904 can include a graphics processor (GPU) 9041 and a microphone 9042. The graphics processor 9041 processes image data of a still picture or a video obtained by an image capture device (such as a camera) in a video capture mode or an image capture mode. The display unit 906 can include a display panel 9061, which can be configured in the form of a liquid crystal display, an organic light-emitting diode, etc. The user input unit 907 includes at least one of a touch panel 9071 and other input devices 9072. The touch panel 9071 is also called a touch screen. The touch panel 9071 can include two parts of a touch detection device and a touch controller. The other input devices 9072 can include, but are not limited to, a physical keyboard, function keys (such as volume control keys, on-off keys, etc.), a trackball, a mouse, an operation lever, and the like, which will not be described here.

[0199] The memory 909 can be used to store software programs and various data. The memory 909 can mainly include a first storage area storing programs or instructions and a second storage area storing data, wherein the first storage area can store an operating system, application programs or instructions required by at least one function (such as a sound playing function, an image playing function, etc.), etc. In addition, the memory 909 can include a volatile memory or a non-volatile memory, or the memory 909 can include both volatile and non-volatile memories. The non-volatile memory can be a Read-Only Memory (ROM), a Programmable ROM (PROM), an Erasable PROM (EPROM), an Electrically EPROM (EEPROM), or a flash memory. The volatile memory can be a Random Access Memory (RAM), a Static RAM (SRAM), a Dynamic RAM (DRAM), a Synchronous DRAM (SDRAM), a Double Data Rate SDRAM (DDR SDRAM), an Enhanced SDRAM (ESDRAM), a Synch link DRAM (SLDRAM), and a Direct Rambus RAM (DRRAM). The memory 909 in the embodiments of the present application includes but is not limited to these and any other suitable types of memories.

[0200] The processor 910 can include one or more processing units; in some embodiments, the processor 910 integrates an application processor and a modem processor, wherein the application processor mainly processes operations related to an operating system, a user interface, and an application program, and the modem processor mainly processes wireless communication signals, such as a baseband processor. It can be understood that the above-mentioned modem processor can also not be integrated into the processor 910.

[0201] The embodiments of the present application also provide a readable storage medium, the readable storage medium stores programs or instructions, the programs or instructions are executed by a processor to realize various processes of the above-mentioned communication processing method embodiments, and the same technical effects can be achieved, and details are not repeated here to avoid repetition.

[0202] The processor is the processor in the electronic device described in the above embodiments. The readable storage medium includes a computer readable storage medium, such as a computer readable memory, a random access memory, a magnetic disk or an optical disk, etc.

[0203] The embodiment of the present application further provides a chip, which comprises a processor and a communication interface, the communication interface is coupled with the processor, the processor is used for running programs or instructions to realize the processes of the communication processing method embodiments and achieve the same technical effects. To avoid repetition, details are not described here.

[0204] It should be understood that the chip mentioned in the embodiment of the present application can also be referred to as a system chip, a system chip, a chip system or a system on chip, etc.

[0205] The embodiment of the present application provides a computer program product, which is stored in a storage medium, and the program product is executed by at least one processor to realize the processes of the communication processing method embodiments and achieve the same technical effects. To avoid repetition, details are not described here.

[0206] It should be noted that in this paper, the term "includes", "contains" or any other variant thereof is intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. Without more limitations, the element defined by the statement "includes a" does not exclude the presence of other identical elements in the process, method, article or device including the element. In addition, it should be pointed out that the scope of the method and device in the embodiment of the present application is not limited to the order of the functions shown or discussed, but can also include the functions performed in a substantially simultaneous manner or in the opposite order according to the functions involved, for example, the described method can be performed in an order different from the described order, and various steps can also be added, omitted or combined. In addition, the features described with reference to some examples can be combined in other examples.

[0207] Through the above description of the embodiments, those skilled in the art can clearly understand that the above-mentioned example methods can be realized by means of software and a necessary general hardware platform, and of course, can also be realized by hardware, but in many cases, the former is a better embodiment. Based on such understanding, the technical solutions of the present application can be embodied in the form of a computer software product in essence or in the form of a part that contributes to the prior art, which is stored in a storage medium (such as a ROM / RAM, a magnetic disc, an optical disc), and includes a plurality of instructions for causing an electronic device (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods described in the various embodiments of the present application.

[0208] The embodiments of the present application are described above in combination with the drawings, but the present application is not limited to the above-mentioned specific embodiments, and the above-mentioned specific embodiments are only illustrative and not restrictive. Those skilled in the art can make many forms under the inspiration of the present application without departing from the scope of the present application and the scope protected by the claims.

Claims

1. A communication processing method applied to an electronic device, the electronic device comprising a first identity module and a second identity module, the method comprising: in a case where the electronic device configures a signal path called by the first identity module and the second identity module, obtaining a path state of the signal path and obtaining a configuration timing of the signal path; based on the path state and the configuration timing, configuring a value of a target control bit in first path control information to obtain second path control information, the target control bit being a control bit other than a first control bit in the first path control information, the first control bit corresponding to the path state, the value of the first control bit being used to control a first signal path of a main diversity antenna corresponding to the first identity module to be open, the value of the target control bit being used to control a signal path of a diversity antenna corresponding to a target identity module to be open, the target identity module being the first identity module or the second identity module; based on the first identity module and the second identity module, invoking a target signal path corresponding to the second path control information for communication processing, the target signal path comprising the first signal path and the signal path of the diversity antenna corresponding to the target identity module. in a case where the electronic device determines that the path state of the signal path has not changed, the obtaining the path state of the signal path comprising: in a case where a first target bit in the first path control information is first preset information, determining that the path state is a cross state; in a case where the first target bit is not the first preset information and a second target bit in the first path control information is second preset information, determining that the path state is a straight-through state. the first path control information is represented by binary, and the first target bit and the second target bit are in any of the following cases: the first target bit comprises a sixth bit, a fifth bit and a first bit in the first path control information, and the second target bit is a second bit in the first path control information; the first target bit is a second bit in the first path control information, and the second target bit comprises a sixth bit, a fifth bit and a first bit in the first path control information. in a case where the electronic device determines that the path state of the signal path has changed, before the method further comprising: based on the path state, configuring a value of the first control bit in the first path control information. based on the path state and the configuration timing, configuring a value of a target control bit in first path control information to obtain second path control information, comprising: ​ ​ ​ 2. The method of claim 1, wherein, ​ ​ ​ 3. The method of claim 2, wherein, ​ ​ ​ 4. The method of claim 1, wherein, ​ ​ 5. The method of claim 1, wherein, ​ In a case where the path state indicates that the signal path is in the cross state, values of a second control bit and a third control bit in the first path control information are configured based on the configuration timing to obtain second path control information, and the target control bits include the second control bit and the third control bit. In a case where the path state indicates that the signal path is in the pass-through state, values of a fourth control bit and the third control bit in the first path control information are configured based on the configuration timing to obtain second path control information, and the target control bits include the third control bit and the fourth control bit. The second control bit is a second bit in the first path control information, the third control bit includes a fourth bit and a third bit in the first path control information, and the fourth control bit includes a sixth bit, a fifth bit and a first bit in the first path control information.

6. The method of claim 1, wherein, The communication processing based on the first identity recognition module and the second identity recognition module includes any one of the following: The first signal path and the second signal path are called for communication processing based on the first identity recognition module, and the second signal path is a signal path of a diversity antenna corresponding to the first identity recognition module. The first signal path is called for communication processing based on the first identity recognition module, and a third signal path is called for communication processing based on the second identity recognition module, and the third signal path is a signal path of a diversity antenna corresponding to the second identity recognition module.

7. A communication processing apparatus applied to an electronic device, the electronic device including a first identity recognition module and a second identity recognition module, and the apparatus including: An acquisition module configured to acquire a path state of a signal path called by the electronic device for the first identity recognition module and the second identity recognition module, and acquire a configuration timing of the signal path; A first configuration module configured to configure values of target control bits in first path control information based on the path state and the configuration timing to obtain second path control information, the target control bits being other control bits than a first control bit in the first path control information, the first control bit corresponding to the path state, the value of the first control bit being used to control a first signal path of a main diversity antenna corresponding to the first identity recognition module, and the values of the target control bits being used to control signal paths of diversity antennas corresponding to target identity recognition modules, the target identity recognition modules being the first identity recognition module or the second identity recognition module; A communication processing module configured to call target signal paths corresponding to the second path control information for communication processing based on the first identity recognition module and the second identity recognition module, the target signal paths including the first signal path and the signal paths of the diversity antennas corresponding to the target identity recognition modules.

8. The apparatus of claim 7, wherein, In a case where the electronic device determines that the path state of the signal path does not change, the obtaining module is specifically configured to: In a case where the first target bit in the first path control information is first preset information, it is determined that the path state is a cross state; In a case where the first target bit is not the first preset information, and a second target bit in the first path control information is second preset information, it is determined that the path state is a straight-through state.

9. The apparatus of claim 8, wherein, The first path control information is represented by binary, and the first target bit and the second target bit are in any of the following cases: The first target bit includes a sixth bit, a fifth bit and a first bit in the first path control information, and the second target bit is a second bit in the first path control information; The first target bit is a second bit in the first path control information, and the second target bit includes a sixth bit, a fifth bit and a first bit in the first path control information.

10. The apparatus of claim 7, further comprising: A second configuration module configured to configure a value of the first control bit in the first path control information based on the path state.

11. The apparatus of claim 7, wherein, The first configuration module is specifically configured to: In a case where the path state indicates that the signal path is in a cross state, based on the configuration timing, values of a second control bit and a third control bit in the first path control information are configured respectively to obtain second path control information, and the target control bit includes the second control bit and the third control bit; In a case where the path state indicates that the signal path is in a straight-through state, based on the configuration timing, values of a fourth control bit and the third control bit in the first path control information are configured respectively to obtain second path control information, and the target control bit includes the third control bit and the fourth control bit; Wherein, the second control bit is a second bit in the first path control information, the third control bit includes a fourth bit and a third bit in the first path control information, and the fourth control bit includes a sixth bit, a fifth bit and a first bit in the first path control information.

12. The apparatus of claim 7, wherein, The communication processing module is specifically configured to any of the following: Based on the first identity recognition module, the first signal path and the second signal path are called for communication processing, and the second signal path is a signal path of a diversity antenna corresponding to the first identity recognition module; Based on the first identity recognition module, the first signal path is called for communication processing, and based on the second identity recognition module, the third signal path is called for communication processing, and the third signal path is a signal path of a diversity antenna corresponding to the second identity recognition module.

13. A communication processing circuitry for use in an electronic device, the circuitry comprising: Switching device, main diversity antenna and diversity antenna corresponding to the first identity recognition module in the electronic device, diversity antenna corresponding to the second identity recognition module in the electronic device, first processing module, and second processing module; The switch device respectively establishes a connection between the main diversity antenna corresponding to the first identity recognition module and the first processing module or the second processing module, and establishes a connection between the diversity antenna corresponding to the first identity recognition module and the first processing module or the second processing module, and establishes a connection between the diversity antenna corresponding to the second identity recognition module and the first processing module or the second processing module. The switch device is used for controlling the signal paths called by the first identity recognition module and the second identity recognition module, the first processing module is used for processing signals of the signal path of the main diversity antenna, and the second processing module is used for processing signals of the signal path of the diversity antenna.

14. The circuit of claim 13, wherein, The number of the diversity antenna corresponding to the second identity recognition module is two, or the circuit further comprises a main diversity antenna corresponding to the second identity recognition module. The switch device is a double-pole four-throw switch, and in the case that the circuit further comprises a main diversity antenna corresponding to the second identity recognition module, the switch device also establishes a connection between the main diversity antenna corresponding to the second identity recognition module and the first processing module or the second processing module.

15. A chip comprising a processor and a communication interface, wherein the communication interface and the processor are coupled, and the processor is used for running a program or instructions to realize the steps of the communication processing method according to any one of claims 1-6.

16. An electronic device comprising a processor, a memory, and a program or instructions stored in the memory and executable on the processor, wherein the program or instructions are executed by the processor to realize the steps of the communication processing method according to any one of claims 1-6.

17. A readable storage medium, wherein the readable storage medium stores a program or instructions, and the program or instructions are executed by a processor to realize the steps of the communication processing method according to any one of claims 1-6.

18. A computer program product, wherein the program product is stored in a storage medium, and the program product is executed by at least one processor to realize the steps of the communication processing method according to any one of claims 1-6.

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