Gate drive module, display panel, display screen, and display device

Abstract

A gate drive module (10), comprising a plurality of gate drive circuits. Each gate drive circuit comprises: an initial generation module (100), which is used for receiving a trigger signal (P_in) and clock signals (CK, CKB) from a display drive chip (40), and generating an initial drive signal on the basis of the clock signals (CK, CKB) and the trigger signal (P_in), the trigger signal (P_in) being from the display drive chip (40) or from another gate drive module (10); and an output module (200), which is connected to an output end of the initial generation module (100) and used for amplifying the initial drive signal to generate a gate drive signal, the gate drive signal being used for driving transistors in pixel circuits (20), wherein input ends, used for receiving the clock signals (CK, CKB), of at least some of the gate drive circuits are connected together.

Description

Gate drive module, display panel, display screen and display device

[0001] Cross-references to related applications

[0002] This application claims priority to Chinese Patent Application No. 2024105365053, filed on April 29, 2024, entitled "Gate Driving Module, Display Panel, Display Screen and Display Device", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of display technology, and in particular to a gate driving module, display panel, display screen and display device. Background Technology

[0004] The statements herein are provided only as background information in connection with this application and do not necessarily constitute exemplary technology.

[0005] With the continuous advancement of display technology, the resolution of display devices is also increasing. To accommodate these rising resolutions and increasingly complex display control functions, the number of signal traces in display devices is constantly increasing. Many of these signal traces need to be routed along the edge areas of the display device. Consequently, the width of these edge areas is also increasing, leading to wider black borders on the display device. Summary of the Invention

[0006] According to various embodiments of this application, a gate driving module, a display panel, a display screen, and a display device are provided.

[0007] In a first aspect, this application provides a gate driving module, including a plurality of gate driving circuits, wherein the gate driving circuits include:

[0008] An initial generation module is configured to receive a trigger signal and a clock signal from a display driver chip, and generate an initial drive signal based on the clock signal and the trigger signal; the trigger signal comes from the display driver chip or from another gate drive module.

[0009] An output module, connected to the output of the initial generation module, is used to amplify the initial driving signal to generate a gate driving signal, which is used to drive the transistors in the pixel circuit.

[0010] In this circuit, at least a portion of the input terminals of the gate drive circuit used for receiving clock signals are connected.

[0011] Secondly, this application provides a display panel, including:

[0012] Multiple pixel circuits are arranged in multiple rows, and each pixel circuit includes multiple transistors.

[0013] The gate driving module has multiple stages as described above, and the output terminals of each stage are respectively connected to the multiple pixel circuits located in each row, so as to control the transistors in the connected pixel circuits to turn on and off through the gate driving signal.

[0014] Thirdly, this application provides a display screen, including:

[0015] The display panel as described above;

[0016] A cover plate is disposed on the light-emitting side of the display panel and covers the display panel.

[0017] Fourthly, this application provides a display device, comprising:

[0018] As shown in the above display screen.

[0019] Details of one or more embodiments of this application are set forth in the following drawings and description. Other features, objects, and advantages of this application will become apparent from the specification, drawings, and claims. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments or exemplary technologies of this application, the accompanying drawings used in the description of the embodiments or exemplary technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other embodiments can be obtained based on these drawings without creative effort.

[0021] Figure 1 is a circuit diagram of a pixel circuit according to an embodiment;

[0022] Figure 2 is a schematic diagram of the gate drive module according to an embodiment;

[0023] Figure 3 is a schematic diagram of the gate drive circuit of one embodiment;

[0024] Figure 4 is a circuit diagram of one embodiment of the gate drive circuit;

[0025] Figure 5 is one of the signal timing diagrams of a gate drive circuit according to an embodiment;

[0026] Figure 6 is a second circuit diagram of a gate drive circuit according to an embodiment;

[0027] Figure 7 is a second signal timing diagram of a gate drive circuit according to an embodiment;

[0028] Figure 8 is a circuit diagram of the third embodiment of the gate drive circuit;

[0029] Figure 9 is a fourth circuit diagram of a gate drive circuit according to an embodiment;

[0030] Figure 10 is a schematic diagram of the structure of a display panel according to an embodiment;

[0031] Figure 11 is a driving timing diagram of a pixel circuit according to an embodiment;

[0032] Figure 12 is a schematic diagram of the structure of a display screen according to an embodiment;

[0033] Figure 13 is a schematic diagram of the gate drive circuit configuration according to an embodiment;

[0034] Figure 14 is an internal structural diagram of a display device according to an embodiment.

[0035] Component labeling: Gate drive module: 10; Initial generation module: 100; Flip unit: 110; First inverter: 111; Holding unit: 120; Locking unit: 121; Third inverter: 1211; Fourth inverter: 1212; Output module: 200; Second inverter: 201; Reset module: 300; Pixel circuit: 20; Cover plate: 30; Display driver chip: 40. Detailed Implementation

[0036] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0037] It is understood that the terms "first," "second," etc., used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of this application, a first gate drive circuit may be referred to as a second gate drive circuit, and similarly, a second gate drive circuit may be referred to as a first gate drive circuit.

[0038] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. "Multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. "Several" means at least one, such as one, two, etc., unless otherwise explicitly specified.

[0039] In the display field, the display area (Active Area, AA area) of a display panel includes multiple light-emitting elements and multiple pixel circuits. The pixel circuits include connected storage capacitors and multiple transistors. The non-display area of ​​the display panel has multiple gate driving circuits, each connected to a transistor in one of the pixel circuits located in the same row. The gate driving circuits control the pixel circuits to perform initialization, writing, and light-emitting processes via gate driving signals, thereby driving the light-emitting elements to emit light, thus displaying an image on the display panel. The light-emitting elements can be, but are not limited to, organic light-emitting diodes (OLEDs) or micro light-emitting diodes (Micro-LEDs). The transistors in the pixel circuits can be made using low-temperature polycrystalline silicon (LTPS) or low-temperature polycrystalline oxide (LTPO) technology. LTPO transistors can be IGZO transistors; IGZO transistors have low leakage current, thus effectively reducing the power consumption of the display panel, and are increasingly used in display devices.

[0040] Furthermore, to reduce the size of the gate driving circuit in display devices, current display devices mostly use a GOA (Gate On Array) approach to integrate the gate driving circuit onto the array substrate. LTPS type pixel circuits typically only require two GOAs: P_gate GOA and EM GOA. The P_gate GOA controls the reset and writing of the pixel circuit, while the EM GOA controls the pixel circuit's ability to drive the light-emitting devices. However, because the switching mechanism of IGZO transistors differs from that of LTPS, pixel circuits including IGZO transistors require three or even five GOAs to control all transistors in the pixel circuit. These three GOAs are P_GOA, N_GOA, and EM GOA. Figure 1 is a circuit diagram of a pixel circuit according to an embodiment. Referring to Figure 1, N_GOA is used to control IGZO TFTs (T1 and T2), P_GOA is used to control P_TFTs (T4, T7 and T8) to realize the reset and writing of the pixel circuit, and EM_GOA is used to control P_TFTs (T5 and T6) to drive the light-emitting device to emit light. It should be noted that the 7T1C pixel circuit shown in Figure 1 is only for illustrative purposes. The gate driving circuit of this embodiment can also be applied to other pixel circuits, such as 8T1C, etc.

[0041] Multiple gate drive modules are cascaded and correspond one-to-one with multiple rows of pixel circuits. Multiple pixel circuits in the same row are connected to the same gate drive module. That is, the pixel circuit in the nth row is connected to the nth-level gate drive module. During screen refresh, the gate drive signal is propagated from top to bottom to refresh the pixel circuits row by row. However, since a single gate drive module requires 3 or even 5 sets of gate drive circuits, and each gate drive circuit needs to receive a clock signal, the number of clock signal traces supporting the gate drive circuits in the display device becomes large, resulting in a wider black border. Therefore, this application provides a gate drive module that can narrow the black border width of the display device.

[0042] Figure 2 is a schematic diagram of a gate driving module according to an embodiment. Referring to Figure 2, the gate driving module includes multiple gate driving circuits, all of which are located in the edge region outside the central region A1, and are used to drive multiple transistors in the pixel circuit. The edge region can be further divided into a first edge region A2 and a second edge region A3 located on both sides of the central region A1. For example, the central region A1 can be the display area of ​​a display device, and the edge region can be the non-display area of ​​the display device. For another example, the central region A1 can be a portion of the middle of the display area, and the edge region can be a portion of the edge of the display area. Here, a pixel circuit with a 7T1C architecture is used as an example. Continuing to refer to Figure 1, the pixel circuit includes six transistors in addition to the driving transistor T3. Therefore, six gate driving circuits can be provided in the gate driving module, and each gate driving circuit can be connected to a corresponding transistor so that the gate driving circuit drives the corresponding connected transistor.

[0043] Furthermore, the number of gate drive circuits in the gate drive module can be adjusted according to the actual driving requirements of the pixel circuits. For example, during the operation of the pixel circuit, some transistors need to be synchronously turned on and off, such as the first light-emitting control transistor T5 connected between the driving transistor T3 and the power supply voltage ELVDD, and the second light-emitting control transistor T6 connected between the driving transistor T3 and the light-emitting element. Therefore, multiple transistors that need to be synchronously turned on and off (e.g., T5 and T6) can be connected to the same gate drive circuit, thereby turning on and off under the control of the same gate drive signal, reducing the number of gate drive circuits in the gate drive module. Another example is that a larger number of gate drive circuits can be set in the gate drive module, and some of these gate drive circuits can be connected to pixel circuits in the same row, using the same operating mode. That is, some transistors will be connected to two identical gate drive circuits. It is understood that if there are too many pixel circuits in the same row, the number of pixel circuits connected to the same gate drive circuit will be too large, resulting in an excessive load on the gate drive circuit, making it unable to accurately drive pixel circuits that are far apart, thus causing display abnormalities on the display panel. Therefore, by setting up two gate drive circuits connected to the same row and using the same operating mode but in different positions, any pixel circuit can be within the effective driving range of the gate drive circuit, thereby achieving accurate driving.

[0044] Figure 3 is a schematic diagram of the gate driving circuit of one embodiment. Referring to Figure 3, the gate driving circuit includes an initial generation module 100 and an output module 200.

[0045] The initial generation module 100 receives a clock signal and a trigger signal P-in, and generates an initial drive signal based on the clock signal and the trigger signal P-in. The clock signal comes from the display driver chip, and the trigger signal P-in comes from the display driver chip or from another gate drive module.

[0046] Specifically, if the gate driving circuit is connected to the first row of pixel circuits on the display panel, then there is necessarily no previous-level gate driving module. The trigger signal P-in it receives is, for example, the start vertical (STV) signal output by the display driver chip 40. Alternatively, if the gate driving circuit is a stage other than the first stage, it can receive signals from the previous-level gate driving module and also receive the start vertical (STV) signal output by the display driver chip 40. Therefore, the gate driving circuit can select one as the trigger signal P-in according to the refresh scenario to generate the gate driving signal. It should be noted that the signal received by the gate driving circuit from the previous-level gate driving module can be the gate driving signal output by the previous stage, or it can be the signal generated by the previous-level gate driving circuit after flipping the received trigger signal P-in, or it can be other process signals between the flipped signal and the final output gate driving signal. This embodiment does not limit this; as long as the trigger signal P-in enables different-level gate driving circuits to sequentially output gate driving signals, it falls within the protection scope of this embodiment.

[0047] The output module 200 is connected to the output terminal of the initial generation module 100 and is used to amplify the initial driving signal to generate a gate driving signal, which is used to drive the transistors in the pixel circuit. Specifically, the output module 200 is used to increase the output current through amplification to improve the load-carrying capacity of the gate driving circuit. It should be noted that this embodiment does not limit the specific structure of the output module 200; as long as the output current of the output module 200 is greater than the input current, it falls within the protection scope of this embodiment.

[0048] In this embodiment, by setting the output module 200, the initial drive signal generated by the initial generation module 100 can be amplified, thereby providing a larger drive current to drive a larger load. That is, the output module 200 greatly improves the load-carrying capacity of the gate drive circuit. Moreover, since the clock signals of some gate drive circuits in the gate drive module have the same timing, the input terminals of the multiple gate drive circuits used to receive clock signals can be connected, and the clock signal from the display driver chip can be accessed through the connected nodes, without having to connect the input terminals of each gate drive circuit used to receive clock signals to the display driver chip independently. This reduces the number of clock signal traces required for the display device, thereby narrowing the black border width of the display device. Combined with the strong load-carrying capacity of the gate drive circuit, even if the input terminals of multiple gate drive circuits used to receive clock signals are connected, it will not cause excessive load pressure on the clock signal from the input terminals used to receive clock signals. Correspondingly, it is not easy to cause waveform distortion of the clock signal, thereby ensuring the reliability of the output gate drive signal. Therefore, this application provides a gate drive module with strong load capacity and few traces.

[0049] In one embodiment, the plurality of gate driving circuits includes a first gate driving circuit and a second gate driving circuit. The number of first and second gate driving circuits is not limited here. For example, the plurality of gate driving circuits may include one first gate driving circuit and multiple second gate driving circuits. The first gate driving circuit drives transistors in multiple pixel circuits located in the same row, and the second gate driving circuits drive transistors in multiple pixel circuits located in multiple rows. It is understood that continuous level switching of the gate driving signal can lead to high power consumption of the gate driving module. Therefore, multiple pixel circuits in adjacent rows can be driven by the same second gate driving signal. For example, multiple pixel circuits in two adjacent rows can be driven by the same second gate driving signal, thereby reducing the power consumption of the gate driving module. For simplicity, the first gate driving circuit in the nth-level gate driving module is referred to as the first gate driving circuit of the nth level, and the second gate driving circuit in the nth-level gate driving module is referred to as the second gate driving circuit of the nth level.

[0050] Specifically, the second gate driving circuits of odd-numbered levels can be cascaded sequentially, and the second gate driving circuits of even-numbered levels can be cascaded sequentially as well. Each pair of adjacent second gate driving circuits forms a gate driving circuit group, and each gate driving circuit group corresponds to two adjacent rows of pixel circuits. Both stages of the second gate driving circuits within the same group are electrically connected to the gate lines of the corresponding two rows of pixel circuits. During operation, the second gate driving circuits of odd-numbered and even-numbered levels operate alternately according to a preset switching cycle. When the second gate driving circuit of an odd-numbered level is operating, it receives a clock signal and uses it to generate a gate driving signal to drive the transistors in the two connected rows of pixel circuits. When the second gate driving circuit of an even-numbered level is operating, it receives a clock signal and uses it to generate a gate driving signal to drive the transistors in the two connected rows of pixel circuits. However, some transistors in the pixel circuits require continuous high-frequency switching on and off, making the aforementioned one-to-two driving architecture unsuitable. Therefore, the transistors can be driven one-to-one by the first gate driving circuit to enable the pixel circuit to operate correctly. It should be noted that the number of first gate driving circuits in a gate driving module can be one or more; this is not limited here.

[0051] In this design, since multiple second gate drive circuits employ a one-to-two driving architecture, they can use the same clock signal, and at least some of the clock signal receiving inputs of the second gate drive circuits are connected to reduce the number of clock signal traces. However, the clock signals of the first and second gate drive circuits are different. Therefore, the clock signal receiving inputs of the first and second gate drive circuits need to be disconnected to avoid clock signal interference between different gate drive circuits, thus ensuring stable and reliable operation of the gate drive module. It is understandable that, if power consumption is not a concern, all gate drive circuits can adopt a one-to-one driving architecture. In this case, all gate drive circuits can share the same clock signal. Accordingly, the clock signal receiving inputs of all gate drive circuits can be connected.

[0052] Specifically, continuing to refer to Figure 1, in one embodiment, the pixel circuit includes a driving transistor T3 and a data writing transistor T4. The first terminal of the data writing transistor T4 is connected to the first terminal of the driving transistor T3, and the second terminal of the data writing transistor T4 is used to receive a data signal. The pixel circuit also includes a gate reset transistor T1, a threshold compensation transistor T2, an anode reset transistor T7, a first light-emitting control transistor T5, and a second light-emitting control transistor T6. The first terminal of the gate reset transistor T1 is used to receive a first reset signal Vinit1, and the second terminal of the gate reset transistor T1 is connected to the control terminal of the driving transistor T3. The first terminal of the threshold compensation transistor T2 is connected to the control terminal of the driving transistor T3, and the second terminal of the threshold compensation transistor T2 is connected to the second terminal of the driving transistor T3. The first terminal of the anode reset transistor T7 is connected to the anode of the light-emitting element, and the second terminal of the anode reset transistor T7 is used to receive a second reset signal Vinit2. The first terminal of the first light-emitting control transistor T5 is used to receive the power supply voltage ELVDD, and the first terminal of the first light-emitting control transistor T5 is connected to the first terminal of the driving transistor T3. The first terminal of the second light-emitting control transistor T6 is connected to the second terminal of the driving transistor T3, and the second terminal of the second light-emitting control transistor T6 is connected to the anode of the light-emitting element.

[0053] The first gate driving circuit is connected to the gate of the data writing transistor T4 in the pixel circuit, and multiple second gate driving circuits are respectively connected to the gate reset transistor T1, threshold compensation transistor T2, anode reset transistor T7, and first light-emitting control transistor T5 (second light-emitting control transistor T6). It is understood that the data writing transistor T4 needs to continuously write data signals at high frequency, therefore a one-to-one driving architecture is required, connecting each row of pixel circuits one-to-one to the first gate driving circuit in each level of the gate driving module to ensure correct display of the display panel. The gate reset transistor T1, threshold compensation transistor T2, anode reset transistor T7, and first light-emitting control transistor T5 in the pixel circuit can all adopt a one-to-two driving architecture. Therefore, four second gate driving circuits can be correspondingly set in the gate driving module, connecting the four transistors one-to-one to the four second gate driving circuits, and connecting at least some of the input terminals of the four second gate driving circuits used for receiving clock signals to reduce the number of clock signal traces. In this embodiment, by defining the connection relationship between the first gate driving circuit and the second gate driving circuit and each transistor in the pixel circuit, the power consumption of the gate driving module can be reduced and the number of clock signal traces can be reduced while ensuring the correct display of the display device, thereby narrowing the bezel of the display device.

[0054] Referring again to Figure 3, in one embodiment, the initial generation module 100 includes a toggle unit 110 and a holding unit 120. The toggle unit 110 toggles the level of the received trigger signal P-in when the received clock signal switches from a first level state to a second level state. It is understood that the clock signal is directly powered by the chip, resulting in a very fast transition speed during level state switching. Consequently, the rise and fall times are short, resulting in a steeper edge for the clock signal and higher signal quality compared to the signal output by the preceding gate drive circuit. The holding unit 120 is connected to the output of the toggle unit 110 and maintains the level of the output of the toggle unit 110 when the clock signal is in the first level state, generating an initial drive signal. The initial drive signal has the opposite level to the signal output by the toggle unit 110, and the gate drive signal has the same waveform as the initial drive signal. That is, the gate drive signal and the initial drive signal have the same duty cycle, but their voltage amplitude and phase may not be exactly the same. By inverting the input signal using the internal structure of the holding unit 120, minute fluctuations in the input signal can be filtered out, thereby making the stability of the output initial drive signal higher than that of the output of the flip unit 110. Optionally, the initial drive signal can be used directly as the gate drive signal, or the gate drive signal can be generated by adjusting the amplitude and / or delay of the initial drive signal. However, regardless of which method is used, the reliability of the gate drive signal can be greatly improved while ensuring that the information carried by the signal remains unchanged.

[0055] Figure 4 is a circuit diagram of one embodiment of the gate drive circuit. Referring to Figure 4, in one embodiment, the output module 200 includes multiple fourth inverters 201 connected in series. Specifically, the fourth inverters 201 can effectively filter out small fluctuations in the input signal through analog amplification, thereby making the output signal more stable and improving the reliability of the gate drive circuit. Further, the fourth inverters 201 include a thirteenth switch and a fourteenth switch. The thirteenth switch is a first type of switch, which is used to conduct when the signal received at the control terminal is a low-level signal. The fourteenth switch is a second type of switch, which is used to conduct when the signal received at the control terminal is a high-level signal. That is, the thirteenth switch can be a seventh PMOS transistor QP7, and the fourteenth switch can be a seventh NMOS transistor QN7. It should be noted that, for ease of explanation, in the following embodiments, the first type of switch is a PMOS transistor and the second type of switch is an NMOS transistor, but the switches in each embodiment can also be other types of voltage-controlled transistors, which is not limited in this application.

[0056] The first terminal of the thirteenth switch QP7 is connected to the high-level voltage source VHG, and the second terminal of the thirteenth switch QP7 serves as the output terminal of the fourth inverter 201. The first terminal of the fourteenth switch QN7 is connected to the low-level voltage source VGL, and the second terminal of the fourteenth switch QN7 is connected to the second terminal of the thirteenth switch QP7. The input terminal of the first fourth inverter 201 is connected to the output terminal of the holding unit 120, and the input terminals of the remaining fourth inverters 201 are respectively connected to the output terminals of the preceding fourth inverter 201. The output terminal of the last fourth inverter 201 serves as the output terminal of the output module 400, used to output the gate drive signal. Specifically, the amplification factor of the output module 400 can be adjusted by adjusting the dimensions of the thirteenth switch QP7 and the fourteenth switch QN7 in each fourth inverter 201. The larger the dimensions of the thirteenth switch QP7 and the fourteenth switch QN7, the greater the amplification factor of the output module 400 and the stronger its load-carrying capacity. It should be noted that Figure 4 shows two second inverters 201 in the output module 200, but in reality, the number of second inverters 201 in the output module 200 can be adjusted according to requirements. This embodiment does not limit the number of second inverters 201. For example, if the gate drive signal needs to be opposite to the level of the initial drive signal, an odd number of second inverters 201 can be set. If the gate drive signal needs to be the same as the level of the initial drive signal, an even number of second inverters 201 can be set. Moreover, since there is a certain delay in the signal transmission process of the second inverters 201, the number of second inverters 201 can be determined according to the required delay time between the gate drive signal and the initial drive signal.

[0057] Referring again to Figure 4, in one embodiment, the clock signal includes a first clock signal CKB and a second clock signal CK, with the level of the second clock signal CK being the opposite of that of the first clock signal CKB. The flip-flop unit 110 includes a first switch, a second switch, and a first inverter 111. The first switch is a first type of switch, and the second switch is a second type of switch. That is, the first switch can be a first PMOS transistor QP1, and the second switch can be a first NMOS transistor QN1.

[0058] The first terminal of the first switch QP1 is connected to a high-level voltage source VHG, and the control terminal of the first switch QP1 is used to receive the first clock signal CKB. Therefore, the first switch QP1 is turned on when the first clock signal CKB is low and turned off when the first clock signal CKB is high. The first terminal of the second switch QN1 is connected to a low-level voltage source VGL, and the control terminal of the second switch QN1 is used to receive the second clock signal CK. Therefore, the first switch QP1 is turned on when the second clock signal CK is high and turned off when the second clock signal CK is low. The level of the second clock signal CK is opposite to that of the first clock signal CKB, causing the first switch QP1 and the second switch QN1 to turn on synchronously. Therefore, at the falling edge of the first clock signal CKB, the high-level voltage VHG is transmitted to the first inverter 111, and simultaneously, at the rising edge of the second clock signal CK, the low-level voltage VGL is also transmitted to the first inverter 111. Understandably, the clock signals are directly powered by the chip, resulting in very fast transitions when the clock signals switch levels. Consequently, the rise and fall times are both short, leading to steeper edges for both the first clock signal CKB and the second clock signal CK, resulting in higher signal quality compared to the signal output from the preceding gate drive circuit.

[0059] The first inverter 111 is connected to the second terminals of the first switch QP1 and the second switch QN1, respectively. When the first switch QP1 and the second switch QN1 are turned on, the first inverter 111 flips the level of the trigger signal P-in input to the first inverter 111 to generate a gate drive signal. Optionally, the gate drive circuit can directly output the signal flipped by the first inverter 111 as the gate drive signal. Alternatively, the gate drive circuit can be connected to other circuit modules after the first inverter 111 and process the signal flipped by the first inverter 111 to generate the gate drive signal. That is, this embodiment only limits the signal output by the first inverter 111 to be associated with the gate drive signal, but does not limit the signal output by the first inverter 111 to be the gate drive signal.

[0060] Furthermore, the level of the trigger signal P-in received by the first inverter 111 is switched when the first clock signal CKB is high. That is, the level of the trigger signal P-in is switched when both the first switch QP1 and the second switch QN1 are off, so that the output of the first inverter 111 remains unchanged when the first switch QP1 and the second switch QN1 are on, thereby avoiding timing conflicts that could cause abnormal gate drive signals output by the gate drive circuit.

[0061] In related technologies, insufficient driving capability of the gate driving module leads to excessively long rise time (TR) and / or fall time (TF) of the gate driving signal transmitted in stages. That is, the switching speed of the gate driving signal's level state is slow, resulting in slow switching speed of transistors in the pixel circuit, and consequently, insufficient charging of the storage capacitor. Furthermore, since the subsequent gate driving module completely depends on the gate driving signal output by the previous gate driving module, errors in the gate driving signal accumulate line by line, ultimately leading to display abnormalities on the display panel. In this embodiment, because the first terminal of the first switch QP1 is connected to a high-level voltage source VHG, the first switch QP1 will conduct when the first clock signal CKB is low. Similarly, the second switch QN1 will conduct when the second clock signal CK is low. Because the first clock signal CKB and the second clock signal CK have opposite voltage levels, the first switch QP1 and the second switch QN1 will conduct synchronously. This allows the first inverter 111 to flip the trigger signal P-in under the combined action of the high-level voltage VHG and the low-level voltage VGL, thereby generating the gate drive signal. Therefore, the timing of the gate drive signal's voltage level switching is only determined by the clock signal and is independent of the trigger signal P-in. The trigger signal P-in is only used to determine the voltage level of the gate drive signal. Thus, even if the trigger signal P-in has an excessively long rise or fall time, it will not affect the timing or speed of the gate drive signal's voltage level switching, thereby improving the quality of the output gate drive signal and ultimately enhancing the display effect and reliability of the display panel.

[0062] Referring again to Figure 4, in one embodiment, the first inverter 111 includes a ninth switch and a tenth switch. The ninth switch is a fifth PMOS transistor QP5 of a first type, and the tenth switch is a fifth NMOS transistor QN5 of a second type. The first terminal of the ninth switch QP5 is connected to the second terminal of the first switch QP1, and the second terminal of the ninth switch QP5 serves as the output terminal of the first inverter 111. The control terminal of the ninth switch QP5 is used to receive the trigger signal P-in. The first terminal of the tenth switch QN5 is connected to the second terminal of the second switch QN1, and the second terminal of the tenth switch QN5 is connected to the second terminal of the ninth switch QP5. The control terminal of the tenth switch QN5 is used to receive the trigger signal P-in. Therefore, when the first switch QP1 is turned on, the first terminal of the ninth switch QP5 receives a high-level voltage VHG. Simultaneously, the second switch QN1 is turned on so that the first terminal of the tenth switch QN5 receives a low-level voltage VGL, thus forming the structure of the first inverter 111. Figure 5 is one of the signal timing diagrams of a gate drive circuit according to an embodiment. Referring to Figures 4 and 5, the explanation will focus on the example where the trigger signal P-in is the start vertical (STV) signal output by the display driver chip. At time T1, when the trigger signal P-in is low, the signal at point P, the output of the first inverter 111, is high. At time T2, when the trigger signal P-in is high, the signal at point P, the output of the first inverter 111, is low. In this embodiment, the first inverter 111 is formed using the ninth switch QP5 and the tenth switch QN5, resulting in fewer circuit components and simpler connections, thus providing a small-sized gate drive circuit.

[0063] Referring again to Figure 4, in one embodiment, the holding unit 120 includes a third switch, a fourth switch, and a locking unit 121. The third switch is a first-type second PMOS transistor QP2, and the fourth switch is a second-type second NMOS transistor QN2.

[0064] It is understandable that the pixel circuit of the display panel needs to be refreshed line by line. Correspondingly, the first switch QP1 and the second switch QN1 in the gate drive circuit corresponding to the non-refreshed line will not always be on. Therefore, the first inverter 111 will not receive the high-level voltage VHG and the low-level voltage VGL during certain periods, thus preventing the first inverter 111 from flipping the input trigger signal P-in, resulting in no signal output from the gate drive circuit during those periods. Therefore, this embodiment introduces a holding unit 120, which can maintain the level state of the output terminal of the flipping unit 110, thereby improving the stability of the gate drive signal received by the downstream pixel circuit. The second terminal of the third switch QP2 is connected to the high-level voltage source VHG, and the control terminal of the third switch QP2 is used to receive the second clock signal CK. Therefore, the third switch QP2 is used to be on when the second clock signal CK is low and off when the second clock signal CK is high. The second terminal of the fourth switch QN2 is connected to the low-level voltage source VGL, and the control terminal of the fourth switch QN2 is used to receive the first clock signal CKB. Therefore, the fourth switch QN2 is turned on when the first clock signal CKB is high and turned off when the first clock signal CKB is low. The locking unit 121 is connected to the output of the first inverter 111, the first terminal of the third switch QP2, and the first terminal of the fourth switch QN2. The locking unit 121 maintains the output level of the first inverter 111 unchanged and generates the initial drive signal when the third switch QP2 and the fourth switch QN2 are on. Specifically, the locking unit 121 can be understood as a 1-bit latch used to latch the input signal. It is understandable that although the output capacitor can maintain the stability of the output signal to a certain extent, as the output capacitor continuously discharges, the signal at the output terminal Q of the gate drive circuit will also drift, which may lead to control errors in the pixel circuit. In this embodiment, the latching unit 121, which adopts a latch structure, is directly powered by a high-level voltage VHG and a low-level voltage VGL when the third switch QP2 and the fourth switch QN2 are turned on. This can provide a stable initial drive signal, thereby improving the stability and reliability of the gate drive signal output by the gate drive circuit.

[0065] Figure 6 is a second circuit diagram of a gate drive circuit according to an embodiment. Referring to Figure 6, in one embodiment, the locking unit 121 includes a second inverter 1211 and a third inverter 1212.

[0066] The second inverter 1211 is connected to the first terminals of the third switch QP2 and the fourth switch QN2, respectively. The second inverter 1211 is used to flip the level state of the input signal when the third switch QP2 and the fourth switch QN2 are turned on. The input terminal of the fourth inverter 1212 is connected to the output terminal of the flipping unit 110 and the output terminal of the third inverter 1211, respectively. The output terminal of the fourth inverter 1212 is connected to the input terminal of the third inverter 1211. The fourth inverter 1212 is used to flip the level state of the input signal. Specifically, Figure 7 is a signal timing diagram of a gate drive circuit according to one embodiment. Referring to Figures 6 and 7, taking point P as a high-level state as an example, the fourth inverter 1212 will output a low-level signal to the input terminal of the third inverter 1211 under the influence of the high-level state at point P. The third inverter 1211 will then output a high-level signal to point P under the influence of the low-level state at its input terminal. Through this cyclical action, the initial drive signal level at point Q is stabilized at a low level. Similarly, when point P is at a low level, point Q can also be stabilized at a high level under the combined action of the third inverter 1211 and the fourth inverter 1212. That is, this embodiment provides a strong-point interlocking locking unit 121 structure, where the outputs of the two inverters are each other's inputs, forming a bistable structure. This structure can maintain a constant level until a new state is written. Therefore, it can effectively resist interference factors such as temperature, making the initial drive signal output by the locking unit 121 more stable, thereby improving the stability of the gate drive signal output by the gate drive circuit. Moreover, the latch structure is relatively simple, occupying less space and able to quickly respond to changes in the input signal, achieving fast signal processing.

[0067] Referring again to Figure 6, in one embodiment, the second inverter 1211 includes a fifth switch and a sixth switch. The fifth switch is a first-type third PMOS transistor QP3, and the sixth switch is a second-type third NMOS transistor QN3. The second terminal of the fifth switch QP3 is connected to the first terminal of the third switch QP2, and the first terminal of the fifth switch QP3 is connected to the output terminal of the first inverter 1211. The control terminal of the fifth switch QP3 is connected to the output terminal of the third inverter 1212. The second terminal of the sixth switch QN3 is connected to the first terminal of the fourth switch QN2, and the first terminal of the sixth switch QN3 is connected to the first terminal of the fifth switch QP3. The control terminal of the sixth switch QN3 is connected to the output terminal of the third inverter 1212. Therefore, when the third switch QP2 is turned on, the second terminal of the fifth switch QP3 receives a high-level voltage VHG. Simultaneously, the fourth switch QN2 is turned on, causing the second terminal of the sixth switch QN3 to receive a low-level voltage VGL, thus forming the structure of the second inverter 1211. In this embodiment, the fifth switch QP3 and the sixth switch QN3 are used to form the second inverter 1211. The circuit components are few and the connection relationship is simple, thereby providing a small-sized gate drive circuit.

[0068] Referring again to Figure 6, in one embodiment, the third inverter 1212 includes a seventh switch and an eighth switch. The seventh switch is a first-type fourth PMOS transistor QP4, and the eighth switch is a second-type fourth NMOS transistor QN4. The first terminal of the seventh switch QP4 is connected to a high-level voltage source VHG, the second terminal of the seventh switch QP4 is connected to the input terminal of the second inverter 1211, and the control terminal of the seventh switch QP4 is connected to the output terminal of the second inverter 1211. The first terminal of the eighth switch QN4 is connected to a low-level voltage source VGL, the second terminal of the eighth switch QN4 is connected to the second terminal of the seventh switch QP4, and the control terminal of the eighth switch QN4 is connected to the output terminal of the third inverter 1212. In this embodiment, the third inverter 1212 is formed using the seventh switch QP4 and the eighth switch QN4, resulting in fewer circuit components and simpler connections, thus providing a small-sized gate drive circuit.

[0069] Figure 8 is a circuit diagram of a third embodiment of the gate driving circuit. Referring to Figure 8, in one embodiment, the gate driving circuit further includes a reset module 300. The reset module 300 is connected to the output terminal of the holding unit 120 and is used to receive a reset control signal RST. In response to the rising or falling edge of the reset control signal RST, the reset module 300 switches the level state of the output terminal of the holding unit 120 to a target level state. Specifically, the target level state is one of a low level state and a high level state, and the target level state is determined according to the transistor type in the pixel circuit connected to the gate driving circuit. In this embodiment, the reset module 300 can release the charge of the Q point by switching the level state of the output terminal of the holding unit 120, thereby reducing the distortion of the gate driving signal and improving the reliability of the gate driving signal. It is understood that resetting the Q point during display may cause the display panel to flicker. Therefore, the display driver chip 40 can provide the aforementioned edge that controls the reset module 300 to reset when the display panel is not displaying an image. For example, when the display panel is powered on or off, this reduces the problem of display panel flicker and improves the user's viewing experience.

[0070] Referring again to Figure 8, in one embodiment, the reset module 300 includes an eleventh switch. The eleventh switch is a sixth PMOS transistor QP6 of the first type. The first terminal of the eleventh switch QP6 is connected to a high-level voltage source VHG, the second terminal of the eleventh switch QP6 is connected to the output of the holding unit 120, and the control terminal of the eleventh switch QP6 is used to receive a reset control signal RST. The eleventh switch QP6 is used to switch the level state of the output of the holding unit 120 to a high level when it is turned on. That is, the eleventh switch QP6 turns on in response to the falling edge of the reset control signal RST to switch the level state of the output of the holding unit 120 to a high level. Specifically, the gate drive circuit can use the eleventh switch QP6 when driving P-type transistors (e.g., T4-T7 shown in Figure 1) in the pixel circuit. Figure 9 is a fourth circuit diagram of a gate drive circuit according to one embodiment. Referring to Figure 9, in one embodiment, the reset module 300 includes a twelfth switch. In this embodiment, the twelfth switch is a sixth NMOS transistor of the second type, QN6. The first terminal of the twelfth switch QN6 is connected to a low-level voltage source VGL, and the second terminal is connected to the output of the holding unit 120. The control terminal of the twelfth switch QN6 receives the reset control signal RST. When turned on, the twelfth switch QN6 switches the output of the holding unit 120 to a low level. That is, the twelfth switch QN6 turns on in response to the rising edge of the reset control signal RST to switch the output of the holding unit 120 to a low level. Specifically, the gate drive circuit can use the twelfth switch QN6 when driving N-type transistors (e.g., T1 and T2 shown in Figure 1) in the pixel circuit. In this embodiment, different reset modules 300 can be adaptively selected for different types of transistors in the pixel circuit, thereby achieving accurate release of charge at the target node (Q point) and improving the reliability of the output gate drive signal.

[0071] This application also provides a display panel. FIG10 is a schematic diagram of the structure of a display panel according to an embodiment. Referring to FIG10, the display panel includes multiple pixel circuits 20 and multiple levels of gate driving modules 10 as described above. The multiple pixel circuits 20 are arranged in multiple rows, and each pixel circuit 20 includes multiple transistors. The output terminals of each level of the gate driving module 10 are respectively connected to the multiple pixel circuits 20 located in each row, so as to control the transistors in the connected pixel circuits 20 to turn on and off through gate driving signals. Based on the aforementioned gate driving module 10, the display panel of this embodiment can display images stably and accurately, and requires fewer clock signal traces, thereby narrowing the black border width of the display device.

[0072] Referring again to Figure 10, in one embodiment, multiple gate driving modules 10 are connected in stages. The trigger signal of a first-stage gate driving module 10 comes from the display driver chip or another connected gate driving module 10. That is, the first-stage gate driving module 10 is connected to both the display driver chip and another gate driving module 10, so that the gate driving module 10 can receive two signals respectively and select one of the two signals as the trigger signal. Specifically, if the display panel is in a global refresh scenario, each row of pixel circuits 20 needs to be refreshed row by row. The gate driving signal of each row of pixel circuits 20 can be generated by triggering the nth-stage gate driving module 10 by the (n-1)th-stage gate driving module 10, which is simple and convenient for control logic. If the display panel is in a local high refresh scenario, only some rows of pixel circuits 20 need to be refreshed during certain periods. Therefore, the gate driving module 10 corresponding to the first row pixel circuit 20 in the high refresh rate region can receive the frame start signal from the display driver chip, and the gate driving modules 10 corresponding to other row pixel circuits 20 in the high refresh rate region can generate gate driving signals under the triggering of the corresponding previous stage gate driving module 10, thereby realizing flexible and high-frequency refresh of some row pixel circuits 20.

[0073] Referring again to Figure 1, in one embodiment, the pixel circuit 20 drives the transistor T3 and the data writing transistor T4. The first terminal of the data writing transistor T4 is connected to the first terminal of the driving transistor T3, and the second terminal of the data writing transistor T4 is used to receive data signals. The control terminal of the data writing transistor T4 is connected to the first gate driving circuit in the gate driving module 10. In this embodiment, because the data writing transistor needs to continuously write data signals at high frequency, a one-to-one driving architecture is required, connecting each row of pixel circuits 20 to the first gate driving circuit in each level of the gate driving module 10 to ensure correct display of the display panel.

[0074] Referring again to Figure 1, in one embodiment, the pixel circuit 20 further includes a gate reset transistor T1, a threshold compensation transistor T2, an anode reset transistor T7, a first light-emitting control transistor T5, and a second light-emitting control transistor T6. The first terminal of the gate reset transistor T1 receives a first reset signal Vinit1, and the second terminal of the gate reset transistor T1 is connected to the control terminal of the driving transistor T3. The first terminal of the threshold compensation transistor T2 is connected to the control terminal of the driving transistor T3, and the second terminal of the threshold compensation transistor T2 is connected to the second terminal of the driving transistor T3. The first terminal of the anode reset transistor T7 is connected to the anode of the light-emitting element, and the second terminal of the anode reset transistor T7 receives a second reset signal Vinit2. The first terminal of the first light-emitting control transistor T5 receives the power supply voltage ELVDD, and the first terminal of the first light-emitting control transistor T5 is connected to the first terminal of the driving transistor T3. The first terminal of the second light-emitting control transistor T6 is connected to the second terminal of the driving transistor T3, and the second terminal of the second light-emitting control transistor T6 is connected to the anode of the light-emitting element. In this embodiment, the gate reset transistor T1, threshold compensation transistor T2, anode reset transistor T7, and first light-emitting control transistor T5 are respectively connected to each of the second gate driving circuits in the gate driving module 10, and the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are connected to the same second gate driving circuit. In this embodiment, the turn-on and turn-off frequencies of the gate reset transistor T1, threshold compensation transistor T2, anode reset transistor T7, and first light-emitting control transistor T5 in the pixel circuit 20 are relatively low, so a one-to-two driving architecture can be used. Specifically, four second gate driving circuits can be correspondingly set in the gate driving module 10, and the above four transistors can be connected one-to-one to the four second gate driving circuits. At least some of the input terminals of the four second gate driving circuits used for receiving clock signals can be connected to reduce the number of clock signal traces. In this embodiment, by defining the connection relationship between the first gate driving circuit, the second gate driving circuit, and each transistor in the pixel circuit 20, the power consumption of the gate driving module 10 can be reduced while ensuring correct display of the display device, and the number of clock signal traces can be reduced, thereby narrowing the bezel of the display device.

[0075] This application embodiment also provides a driving timing diagram for the above-mentioned pixel circuit. Referring to Figures 1 and 11, in this embodiment, EM_GOA, N_Gate_GOA, H_Reset_GOA, and N_Reset_GOA share the first set of clock signals CK1 and CK1B, while P_Gate_GOA uses CK2 and CK2B. The display process of one frame of the display panel includes three stages: initialization stage, writing stage, and light emission stage. In the initialization stage, the high level state of N_Reset turns on the gate reset transistor T1, the high level state of N_Gate turns on the threshold compensation transistor T2, and the low level state of H_Reset turns on the anode reset transistor T7. Therefore, after the initialization stage, N1, N3, and N4 of the pixel circuit are reset. During the writing phase, the high level of N_Gate keeps the threshold compensation transistor T2 on, and the low level of P_Gate turns on the data writing transistor T4. When the driving transistor T3 operates in the critical saturation region, its gate voltage is set to Vdata-Vth and turned off, and this voltage is stored in the storage capacitor Cst. After the data writing is complete, H_Reset can be pulled low to turn on the anode reset transistor T7, thereby resetting the anode of the light-emitting element. During the light-emitting phase, the low level of EM turns on the first light-emitting control transistor T5 and the second light-emitting control transistor T6, thereby driving the light-emitting element to emit light.

[0076] In one embodiment, the pixel circuit 20 further includes a data reset transistor T8. The first terminal of the data reset transistor T8 is connected to the first terminal of the driving transistor T3, and the second terminal of the data reset transistor T8 is used to receive a third reset signal Vinit3. The data reset transistor T8 and the anode reset transistor T7 are connected to the same second gate driving circuit. Specifically, the data reset transistor T8 can release the charge of the data writing node before the data signal is written, so that the data signal is written correctly, thereby ensuring that the brightness of the corresponding light-emitting element meets the display requirements.

[0077] This application also provides a display screen. FIG12 is a schematic diagram of the structure of a display screen according to an embodiment. Referring to FIG12, the display screen includes a cover plate 30 and a display panel as described above. The cover plate 30 is disposed on the light-emitting side of the display panel and covers the display panel. In this embodiment, by providing the cover plate 30, the display panel can be protected, reducing damage to the display panel from external forces, thereby improving the reliability of the display panel.

[0078] In one embodiment, continuing to refer to FIG12, the display screen further includes a display driver chip 40, which is connected to the display panel and is used to output a clock signal and a frame start signal to the display panel. The input terminals of multiple gate drive circuits in the display panel for receiving clock signals are connected to the same clock signal output terminal of the display driver chip. Further, the clock signal includes a first clock signal CKB and a second clock signal CK. The display driver chip 40 is used to switch the level state of the frame start signal when the first clock signal CKB is high. In this embodiment, by controlling the switching timing of the level state of the frame start signal output by the display driver chip 40, timing conflicts between the frame start signal and the clock signal can be effectively avoided, thereby preventing abnormalities in the gate drive circuit caused by timing conflicts and improving the operational reliability of the gate drive circuit.

[0079] This application also provides a display device, including the display screen described above. In this embodiment, based on the aforementioned display screen, a display screen with stable and reliable image display and narrow black borders is provided.

[0080] In one embodiment, a plurality of pixel circuits 20 are disposed in the central region A1 of the display device, a portion of the gate driving circuits are disposed in a first edge region A2 on one side of the central region A1, and another portion of the gate driving circuits are disposed in a second edge region A3 on the other side of the central region A1. In this embodiment, by distributing the gate driving circuits on both sides of the central region A1, the excessive number of gate driving circuits on one side can be effectively reduced, thereby reducing potential problems such as wide black borders.

[0081] Figure 13 is a schematic diagram of the gate driving circuit configuration according to one embodiment. Referring to Figure 13, in one embodiment, the first edge region A2 is provided with gate driving circuits for H_Reset, N_Reset, and P_Gate, and the second edge region A3 is provided with gate driving circuits for EM, N_Gate, and P_Gate. The clock signal output by the display driver chip 30 is transmitted to the gate driving circuit via traces. The number of traces for the clock signal in the first edge region A2 is the same as the number of traces for the clock signal in the second edge region A3.

[0082] Specifically, Table 1 shows the routing table between the gate driving module 10 and the display driving chip 30 when using the connection method of this embodiment. Referring to Table 1, after adopting the connection method of this embodiment, on one side of the central region A1, only one set of clock signals CK1 and CK1B corresponding to P_gate needs to be set, and a set of clock signals CK2 and CK12 shared by N_gate, N_Reset, H_Reset and EM needs to be set. That is, in this application, only 10 clock signal traces need to be set on each side, and a total of 10 clock signal traces need to be set on the first edge region A2 and the second edge region A3.

[0083] Table 1 shows the wiring diagram between the gate driving module and the display driving chip when using the connection method of this embodiment.

[0084] In comparison, Table 2 shows the routing table between the gate driving module 10 and the display driving chip 30 when the connection method of this embodiment is not adopted. Referring to Table 2, if the connection method of this embodiment is not adopted, N_gate, N_Reset, H_Reset, and EM need to be set with corresponding clock signals, specifically NCK and NCB for N_gate, RCK and RCB for N_Reset, EMCK and EMCB for EM, and HCK and HCB for H_Reset. Moreover, in related technologies, due to the use of gate driving circuits with architectures such as 13T3C and 16T3C, on the one hand, two sets of VGH and VGL need to be set on each side of the central region A1, and on the other hand, independent reset control signals RSTNCX, RCX, EMCX, and HCX need to be configured for each gate driving circuit, which further increases the number of routing lines. That is, in related technologies, 15 clock signal routing lines need to be set on each side, and a total of 30 clock signal routing lines need to be set on the first edge region A2 and the second edge region A3.

[0085] Table 2 shows the wiring diagram between the gate driving module and the display driving chip when the connection method of this embodiment is not used.

[0086] In one embodiment, a display device is provided, which can be a terminal. The terminal can be, but is not limited to, various personal computers, laptops, smartphones, tablets, IoT devices, and portable wearable devices. IoT devices can be smart speakers, smart TVs, smart air conditioners, smart in-vehicle devices, etc. Portable wearable devices can be smartwatches, smart bracelets, head-mounted devices, etc. Figure 14 is an internal structural diagram of a display device according to an embodiment. The display device includes a processor, memory, communication interface, display panel, and input device connected via a system bus. The processor of the display device provides computing and control capabilities. The memory of the display device includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores an operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The communication interface of the display device is used for wired or wireless communication with external terminals. Wireless communication can be achieved through Wi-Fi, mobile cellular networks, NFC (Near Field Communication), or other technologies. The input device of the display device can be a touch layer covering the display panel, or a button, trackball, or touchpad set on the casing of the display device, or an external keyboard, touchpad, or mouse, etc.

[0087] Those skilled in the art will understand that the structure shown in FIG14 is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the display device to which the present application is applied. A specific display device may include more or fewer components than those shown in FIG14, or combine certain components, or have different component arrangements.

[0088] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0089] The above embodiments merely illustrate several implementation methods of the embodiments of this application, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the embodiments of this application, and these all fall within the protection scope of the embodiments of this application. Therefore, the protection scope of the patent for the embodiments of this application should be determined by the appended claims.

Claims

1. A gate driving module, comprising a plurality of gate driving circuits, each of the gate driving circuits comprising: an initial generating module, configured to receive a trigger signal and a clock signal from a display driving chip, and generate an initial driving signal according to the clock signal and the trigger signal; the trigger signal being from the display driving chip or from another gate driving module; and an output module, connected to an output terminal of the initial generating module, configured to amplify the initial driving signal to generate a gate driving signal, the gate driving signal being used to drive a transistor in a pixel circuit; wherein input terminals of at least some of the gate driving circuits for receiving the clock signal are connected in communication. 2.The gate driving module of claim 1, wherein if the gate driving circuit is connected to a first row of pixel circuits of a display panel, the received trigger signal is a frame start signal output by the display driving chip. 3.The gate driving module of claim 1, wherein if the gate driving circuit is connected to other rows of pixel circuits of the display panel, the received trigger signal is one of a signal of a previous stage gate driving module and a frame start signal output by the display driving chip. 4.The gate driving module of claim 3, wherein if the received trigger signal is the signal of the previous stage gate driving module, the trigger signal received by the gate driving circuit is the gate driving signal output by the previous stage gate driving module or a signal generated by inverting the trigger signal received by the previous stage gate driving module. 5.The gate driving module of claim 1, wherein the plurality of gate driving circuits comprises a first gate driving circuit and a plurality of second gate driving circuits; the first gate driving circuit is used to drive transistors in a plurality of pixel circuits located in the same row, and the second gate driving circuit is used to drive transistors in a plurality of pixel circuits located in multiple rows; input terminals of at least some of the second gate driving circuits for receiving the clock signal are connected in communication, and input terminals of the first gate driving circuit and the second gate driving circuit for receiving the clock signal are disconnected. 6.The gate driving module of claim 5, wherein the second gate driving circuits of each odd stage are sequentially cascaded, and the second gate driving circuits of each even stage are sequentially cascaded; each two adjacent stages of the second gate driving circuits form a gate driving circuit group, each gate driving circuit group corresponds to two adjacent rows of pixel circuits, and the two stages of second gate driving circuits in the same gate driving circuit group are electrically connected to gate lines of the corresponding two rows of pixel circuits. 7.The gate driving module of claim 5, wherein the first gate driving circuit is used to be connected to a gate of a data writing transistor in a pixel circuit; and the plurality of second gate driving circuits are used to be connected to gates of a plurality of transistors in a pixel circuit except the data writing transistor. 8.The gate driving module of claim 1, wherein the initial generating module comprises: ​ ​ wherein, ​ ​ ​ ​ ​ ​ a flip unit, configured to flip a level state of a received trigger signal when a received clock signal is switched from a first level state to a second level state; a holding unit, connected to an output terminal of the flip unit, configured to maintain the level state of the output terminal of the flip unit when the clock signal is in the first level state, and generate an initial driving signal; wherein the initial driving signal is opposite to the level state of the signal output by the flip unit, and the gate driving signal has a same waveform as the initial driving signal.

9. The gate driving module of claim 8, wherein the clock signal comprises a first clock signal and a second clock signal, the second clock signal having an opposite level state to the first clock signal; and the flip unit comprises: a first switch tube, a first terminal of the first switch tube being configured to be connected to a high-level voltage source, a control terminal of the first switch tube being configured to receive the first clock signal, the first switch tube being a first type of switch tube configured to be turned on when a signal received by the control terminal is in a low-level state; a second switch tube, a first terminal of the second switch tube being configured to be connected to a low-level voltage source, a control terminal of the second switch tube being configured to receive the second clock signal, the second clock signal having an opposite level state to the first clock signal, the second switch tube being a second type of switch tube configured to be turned on when a signal received by the control terminal is in a high-level state; a first inverter, respectively connected to a second terminal of the first switch tube and a second terminal of the second switch tube, the first inverter being configured to flip a level state of a trigger signal input to the first inverter to generate a gate driving signal when the first switch tube and the second switch tube are turned on.

10. The gate driving module of claim 8, wherein the holding unit comprises: a third switch tube, a second terminal of the third switch tube being configured to be connected to the high-level voltage source, a control terminal of the third switch tube being configured to receive the second clock signal, the third switch tube being configured to be turned on when the second clock signal is in a low-level state and turned off when the second clock signal is in a high-level state; a fourth switch tube, a second terminal of the fourth switch tube being configured to be connected to the low-level voltage source, a control terminal of the fourth switch tube being configured to receive the first clock signal, the fourth switch tube being configured to be turned on when the first clock signal is in a high-level state and turned off when the first clock signal is in a low-level state; a locking unit, respectively connected to an output terminal of the first inverter, a first terminal of the third switch tube and a first terminal of the fourth switch tube, the locking unit being configured to maintain the level state of the output terminal of the first inverter unchanged and generate an initial driving signal when the third switch tube and the fourth switch tube are turned on.

11. The gate driving module of claim 1, wherein the output module comprises a plurality of second inverters connected in series.

12. A display panel, comprising: a plurality of pixel circuits arranged in a plurality of rows, each of the pixel circuits comprising a plurality of transistors. The multi-stage gate drive module of any one of claims 1 to 11, wherein the output terminal of each stage of the gate drive module is connected to a plurality of pixel circuits in each row, respectively, to control the on and off of transistors in the connected pixel circuits by gate drive signals.

13. The display panel of claim 12, wherein the plurality of gate drive modules are connected stage by stage, and the trigger signal of a stage of the gate drive modules is from a display driving chip or another stage of the gate drive modules connected thereto.

14. The display panel of claim 12, wherein the pixel circuit comprises: a driving transistor; a data writing transistor, a first terminal of the data writing transistor being connected to a first terminal of the driving transistor, and a second terminal of the data writing transistor being configured to receive a data signal; wherein a control terminal of the data writing transistor is connected to a first gate drive circuit in the gate drive module.

15. The display panel of claim 14, wherein the pixel circuit further comprises: a gate reset transistor, a first terminal of the gate reset transistor being configured to receive a first reset signal, and a second terminal of the gate reset transistor being connected to a control terminal of the driving transistor; a threshold compensation transistor, a first terminal of the threshold compensation transistor being connected to the control terminal of the driving transistor, and a second terminal of the threshold compensation transistor being connected to a second terminal of the driving transistor; an anode reset transistor, a first terminal of the anode reset transistor being connected to an anode of a light emitting element, and a second terminal of the anode reset transistor being configured to receive a second reset signal; a first light emitting control transistor, a first terminal of the first light emitting control transistor being configured to receive a power voltage, and a first terminal of the first light emitting control transistor being connected to the first terminal of the driving transistor; a second light emitting control transistor, a first terminal of the second light emitting control transistor being connected to the second terminal of the driving transistor, and a second terminal of the second light emitting control transistor being connected to the anode of the light emitting element; wherein the gate reset transistor, the threshold compensation transistor, the anode reset transistor, and the first light emitting control transistor are connected to respective second gate drive circuits in the gate drive module, and the first light emitting control transistor and the second light emitting control transistor are connected to the same second gate drive circuit.

16. A display screen, comprising: the display panel of any one of claims 12 to 15; and a cover plate disposed on a light exit side of the display panel and covering the display panel.

17. The display screen of claim 16, further comprising: a display driving chip connected to the display panel and configured to output a clock signal and a frame start signal to the display panel; wherein the input terminals of the plurality of gate drive circuits in the display panel for receiving the clock signal are connected to the same clock signal output terminal of the display driving chip.

18. A display device, comprising: the display screen of any one of claims 16 to 17. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ 19.The display device of claim 18, wherein a plurality of the pixel circuits are disposed in a middle region of the display device, a portion of the gate driving circuits are disposed in a first edge region on one side of the middle region, and another portion of the gate driving circuits are disposed in a second edge region on another side of the middle region. 20.The display device of claim 19, wherein the clock signals output by the display driving chip are transmitted to the gate driving circuits through wirings, and a number of wirings of the clock signals disposed in the first edge region is the same as a number of wirings of the clock signals disposed in the second edge region.

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