Display substrate, manufacturing method therefor, and display apparatus

Abstract

A display substrate, a manufacturing method therefor, and a display apparatus. The display substrate comprises a plurality of repeating units (100); at least one repeating unit (100) comprises a display area (110) and a light-transmitting area (120); the display area (100) comprises a plurality of sub-pixels; at least one sub-pixel comprises a pixel driving circuit and a light-emitting device connected to the pixel driving circuit; the pixel driving circuit is separately connected to a first power line (71), data signal lines (61-64) and a compensation signal line (73); the light-emitting device is connected to a second power line (72); the display area comprises a first area (110-1) and a second area (110-2); the pixel driving circuits of the plurality of sub-pixels are arranged in the first area (110-1), and the first power line (71), the second power line (72), the compensation signal line (73) and the data signal lines (61-64) are arranged in the second area (110-2).

Description

Display substrate and its preparation method, display device Technical Field

[0001] This disclosure relates to, but is not limited to, the field of display technology, and particularly to a display substrate, a method for preparing the same, and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) are active-matrix display devices with advantages such as active emission, ultra-thinness, wide viewing angle, high brightness, high contrast, low power consumption, extremely high response speed, lightweight design, customizability, and flexible display capabilities. They have gradually become a promising next-generation display technology. Among them, active matrix (AM) OLEDs are current-driven devices that use independent thin-film transistors (TFTs) to control each sub-pixel, allowing each sub-pixel to emit light continuously and independently.

[0003] With the continuous development of display technology, OLED technology is increasingly being applied to transparent displays. Transparent displays are an important area of ​​personalized display technology, referring to image display in a transparent state. Viewers can see not only the images on the display device but also the scene behind it, enabling virtual reality (VR), augmented reality (AR), and 3D display functions. Transparent display devices using OLED technology typically divide each sub-pixel into a display area and a light-transmitting area. The display area houses the pixel driving circuitry and light-emitting devices to display the image, while the light-transmitting area allows light to pass through.

[0004] Summary of the Invention

[0005] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0006] On one hand, this disclosure provides a display substrate including a plurality of repeating units arranged in a regular pattern. At least one repeating unit includes a display area and a light-transmitting area disposed on one side of a first direction or the opposite side of the first direction of the display area. The display area is configured to display an image, and the light-transmitting area is configured to transmit light. The display area includes a plurality of sub-pixels arranged sequentially along a second direction, wherein the first direction and the second direction intersect. At least one sub-pixel includes a pixel driving circuit and a light-emitting device connected to the pixel driving circuit. The pixel driving circuit is connected to a first power line, a data signal line, and a compensation signal line, respectively. The light-emitting device is connected to a second power line. The display area includes a first area and a second area disposed on the side of the first area away from the light-transmitting area. The pixel driving circuit of the plurality of sub-pixels is disposed in the first area, and the first power line, the second power line, the data signal line, and the compensation signal line are disposed in the second area.

[0007] In an exemplary embodiment, in the first direction, the compensation signal line is disposed between the data signal line and the first power line, and the first power line is disposed between the compensation signal line and the second power line.

[0008] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate includes a plurality of conductive layers disposed on the substrate, wherein the first power line and the data signal line are disposed in the same conductive layer, the compensation signal line and the second power line are disposed in the same conductive layer, and the first power line and the second power line are disposed in different conductive layers.

[0009] In an exemplary embodiment, the data signal line includes a first data signal line, a second data signal line, a third data signal line, and a fourth data signal line arranged sequentially along the first direction; adjacent data signal lines have a first spacing, the fourth data signal line and the compensation signal line have a second spacing, the first power line and the compensation signal line have a third spacing, and the first power line and the second power line have a fourth spacing, wherein the second spacing is smaller than the first spacing, the third spacing is smaller than the first spacing, and the fourth spacing is smaller than the first spacing.

[0010] In an exemplary embodiment, the pixel driving circuit includes at least a first transistor, a second transistor, a third transistor, and a storage capacitor. The first electrode of the first transistor is connected to the data signal line, the second electrode of the first transistor is connected to the gate electrode of the second transistor and the first terminal of the storage capacitor, the first electrode of the second transistor is connected to the first power line, the second electrode of the second transistor is connected to the second electrode of the third transistor and the second terminal of the storage capacitor, and the first electrode of the third transistor is connected to the compensation signal line. In the plurality of sub-pixels of at least one repeating unit, the gate electrodes of the plurality of first transistors and the gate electrodes of the plurality of third transistors are connected to the same scan signal line.

[0011] In an exemplary embodiment, in at least one repeating unit, the scanning signal line includes a scanning transmission line disposed in the light-transmitting area and a first ring structure and a second ring structure disposed in the display area. The first end of the scanning transmission line is connected to the second ring structure in the repeating unit, and the second end of the scanning transmission line is connected to the second ring structure in the repeating unit adjacent in the first direction.

[0012] In an exemplary embodiment, in at least one repeating unit and a repeating unit adjacent to the first direction, the scan transmission lines in the two repeating units are not on the same straight line extending along the first direction.

[0013] In an exemplary embodiment, the display area includes a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel arranged sequentially along the second direction. The first ring structure is disposed in the first sub-pixel and the second sub-pixel, and the second ring structure is disposed in the third sub-pixel and the fourth sub-pixel. The first ring structure and the second ring structure are connected to each other by a ring connecting line.

[0014] In an exemplary embodiment, in at least one repeating unit, the first ring structure, the second ring structure, and the ring connecting line are an integral structure that is interconnected.

[0015] In an exemplary embodiment, the first ring structure or the second ring structure includes at least two gate electrode lines, a first scan connection line, and a second scan connection line. The gate electrode lines are in the shape of a straight line or a broken line extending along the first direction. The two gate electrode lines are respectively disposed in two sub-pixels. The first scan connection line and the second scan connection line are in the shape of a straight line or a broken line extending along the second direction. The first scan connection line is connected to the ends of the two gate electrode lines in the opposite direction of the first direction, and the second scan connection line is connected to the ends of the two gate electrode lines in the first direction, thus forming the first ring structure or the second ring structure.

[0016] In an exemplary embodiment, in at least one repeating unit, the two gate electrode lines, one first scan connection line, and one second scan connection line in the first ring structure or the second ring structure are an integral structure that is interconnected.

[0017] In an exemplary embodiment, the orthographic projections of the first ring structure and the second ring structure on the display substrate plane at least partially overlap with the orthographic projections of the first power line, the second power line, the data signal line, and the compensation signal line on the display substrate plane.

[0018] In an exemplary embodiment, the first annular structure is provided with a first protruding structure, the first protruding structure protruding toward the light-transmitting area, and the orthographic projection of the first protruding structure on the display substrate plane at least partially overlaps with the orthographic projection of the light-transmitting area on the display substrate plane; and / or, the second annular structure is provided with a second protruding structure, the second protruding structure protruding toward the light-transmitting area, and the orthographic projection of the second protruding structure on the display substrate plane at least partially overlaps with the orthographic projection of the light-transmitting area on the display substrate plane.

[0019] In an exemplary embodiment, in at least one repeating unit, the first protruding structure and the second protruding structure have different protrusion lengths, wherein the protrusion length is the dimension in the first direction.

[0020] In an exemplary embodiment, in at least one repeating unit, the first protrusion width and the second protrusion width in the first protrusion structure are different, wherein the first protrusion width is the dimension of the first protrusion structure located on the side of the gate electrode line away from the ring connection line, and the second protrusion width is the dimension of the first protrusion structure located on the side of the gate electrode line close to the ring connection line; and / or, the third protrusion width and the fourth protrusion width in the second protrusion structure are different, wherein the third protrusion width is the dimension of the second protrusion structure located on the side of the gate electrode line close to the ring connection line, and the fourth protrusion width is the dimension of the second protrusion structure located on the side of the gate electrode line away from the ring connection line.

[0021] In an exemplary embodiment, at least one repeating unit further includes a third protruding structure, the third protruding structure being disposed on the side of the pixel driving circuit away from the first protruding structure or the second protruding structure, the third protruding structure protruding toward the light-transmitting area, and the orthographic projection of the third protruding structure on the display substrate plane at least partially overlapping the orthographic projection of the light-transmitting area on the display substrate plane; the electrode connecting electrode includes an electrode connecting strip and an electrode connecting block, the first end of the electrode connecting strip being connected to the fifth electrode of the storage capacitor, and the second end of the electrode connecting strip extending to the light-transmitting area and then being connected to the electrode connecting block; the anode connecting electrode includes a first sub-connecting electrode, a second sub-connecting electrode, and a third sub-connecting electrode, the first sub-connecting electrode... The first end of the electrode is connected to the first sub-anode of the light-emitting device, the first end of the second sub-connecting electrode is connected to the second sub-anode of the light-emitting device, the second ends of the first and second sub-connecting electrodes extend to the light-transmitting area and are respectively connected to the first and second ends of the third sub-connecting electrode, and the third sub-connecting electrode is connected to the electrode plate connecting block through a through hole; there is a fifth protrusion width between the first sub-connecting electrode and the electrode plate connecting strip or between the second sub-connecting electrode and the electrode plate connecting strip, the first protrusion width is greater than the fifth protrusion width, the second protrusion width is greater than the fifth protrusion width, the third protrusion width is greater than the fifth protrusion width, and the fourth protrusion width is greater than the fifth protrusion width.

[0022] In an exemplary embodiment, the storage capacitor includes a first capacitor and a second capacitor connected in parallel. The first capacitor includes a first electrode and a second electrode stacked on top of each other. The orthographic projection of the first electrode on the display substrate plane overlaps with the orthographic projection of the second electrode on the display substrate plane. The second capacitor includes a third electrode, a fourth electrode, and a fifth electrode stacked on top of each other. The orthographic projections of the third electrode, the fourth electrode, and the fifth electrode on the display substrate plane overlap with each other. The first electrode and the third electrode are connected, the third electrode and the fifth electrode are connected, and the second electrode and the fourth electrode are connected.

[0023] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate includes at least a first transparent conductive layer disposed on a substrate, a first conductive layer disposed on a side of the first transparent conductive layer away from the substrate, and a semiconductor layer disposed on a side of the first conductive layer away from the substrate; a first electrode plate is disposed in the first transparent conductive layer, and a second electrode plate is disposed in the semiconductor layer, forming a transparent first capacitor.

[0024] In an exemplary embodiment, the orthographic projections of the first electrode plate and the second electrode plate onto the substrate at least partially overlap with the orthographic projection of the light-transmitting region onto the substrate.

[0025] In an exemplary embodiment, the display substrate further includes a second conductive layer disposed on the side of the semiconductor layer away from the substrate, and a third conductive layer disposed on the side of the second conductive layer away from the substrate; the third electrode plate is disposed in the first conductive layer, the fourth electrode plate is disposed in the second conductive layer, and the fifth electrode plate is disposed in the third conductive layer.

[0026] In an exemplary embodiment, the display substrate further includes a second conductive layer disposed on the side of the semiconductor layer away from the substrate, and a third conductive layer disposed on the side of the second conductive layer away from the substrate; the third electrode plate is disposed in the first conductive layer, the fourth electrode plate is disposed in the semiconductor layer, and the fifth electrode plate is disposed in the third conductive layer.

[0027] On the other hand, this disclosure also provides a display device including the aforementioned display substrate.

[0028] In another aspect, this disclosure also provides a method for fabricating a display substrate, the display substrate comprising a plurality of repeating units arranged in a regular pattern, at least one repeating unit comprising a display area and a light-transmitting area disposed on one side of a first direction or on the opposite side of the first direction of the display area, the display area being configured to display an image, the light-transmitting area being configured to transmit light, the display area comprising a plurality of sub-pixels sequentially disposed along a second direction, the first direction and the second direction intersecting; the fabrication method comprising:

[0029] A pixel driving circuit and a light-emitting device connected to the pixel driving circuit are formed in at least one sub-pixel. The pixel driving circuit is connected to a first power line, a data signal line, and a compensation signal line, respectively. The light-emitting device is connected to a second power line. The display area includes a first area and a second area disposed on the side of the first area away from the light-transmitting area. The pixel driving circuits of multiple sub-pixels are disposed in the first area, and the first power line, the second power line, the data signal line, and the compensation signal line are disposed in the second area.

[0030] After reading and understanding the accompanying diagrams and detailed descriptions, other aspects can be understood. Attached Figure Description

[0031] The accompanying drawings are provided to further illustrate the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure. The shapes and sizes of the components in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure.

[0032] Figure 1 is a schematic diagram of a display device;

[0033] Figure 2 is a schematic diagram of a planar structure of a display substrate;

[0034] Figure 3 is a schematic diagram of the arrangement of sub-pixels in a repeating unit according to an exemplary embodiment of the present disclosure;

[0035] Figure 4 shows an equivalent circuit diagram of a pixel driving circuit according to an exemplary embodiment of this disclosure;

[0036] Figure 5 is a schematic diagram of the structure of a display substrate according to an exemplary embodiment of the present disclosure;

[0037] Figure 6 is a schematic diagram of the structure of a storage capacitor according to an exemplary embodiment of the present disclosure;

[0038] Figure 7 is a schematic diagram of a display substrate after the formation of a first transparent conductive layer pattern according to the present disclosure;

[0039] Figures 8A and 8B are schematic diagrams of a display substrate after the formation of the first conductive layer pattern according to the present disclosure;

[0040] Figures 9A and 9B are schematic diagrams of a display substrate after a semiconductor layer pattern has been formed.

[0041] Figures 10A and 10B are schematic diagrams of a display substrate after the formation of a second conductive layer pattern according to the present disclosure;

[0042] Figure 10C is a schematic diagram of a short-circuit fault repair method for a display substrate disclosed herein;

[0043] Figure 11 is a schematic diagram of a display substrate after the formation of a third insulating layer pattern according to the present disclosure;

[0044] Figures 12A and 12B are schematic diagrams of a display substrate after the formation of a third conductive layer pattern according to the present disclosure;

[0045] Figure 13 is a schematic diagram of a display substrate after the formation of a fourth insulating layer and a first planarization layer pattern according to the present disclosure;

[0046] Figures 14A and 14B are schematic diagrams of a display substrate after the formation of a second transparent conductive layer pattern according to the present disclosure.

[0047] Figure 15 is a schematic diagram of a display substrate after forming a pixel definition layer pattern according to the present disclosure;

[0048] Figure 16 is a schematic diagram of the structure of another display substrate according to an exemplary embodiment of the present disclosure;

[0049] Figure 17 is a schematic diagram of the structure of another storage capacitor according to an exemplary embodiment of the present disclosure;

[0050] Figures 18A and 18B are schematic diagrams of another display substrate after a semiconductor layer pattern has been formed;

[0051] Figures 19A and 19B are schematic diagrams of another display substrate after the formation of the second conductive layer pattern in this disclosure;

[0052] Figure 20 is a schematic diagram of another display substrate after the formation of the third insulating layer pattern according to the present disclosure;

[0053] Figures 21A and 21B are schematic diagrams of another display substrate after the formation of the third conductive layer pattern according to this disclosure.

[0054] Explanation of reference numerals in the attached figures: 10-1—First capacitor; 10-2—Second capacitor; 11—First electrode; 12—Second electrode; 13—Third electrode; 14—Fourth electrode; 15—Fifth electrode; 21—First active layer; 22—Second active layer; 23—Third active layer; 30—Scan signal line; 30A—First ring structure; 30B—Second ring structure; 31—Gate electrode line; 32—Second gate electrode; 33—First scan connection line; 34—Second scan connection line; 35—Ring connection line; 36—Scan transmission line; 37—First protruding structure; 38—Second protruding structure; 41—First connecting electrode; 42—Second connecting electrode; 43—Third connecting electrode; 44—Fourth connecting electrode; 45—Fifth connecting electrode; 46—Sixth connecting electrode; 47—Seventh connecting electrode; 48—Eighth connecting electrode; 49—Ninth connecting electrode; 50—Tenth connecting electrode; 51—Eleventh connecting electrode; 52—Twelfth connecting electrode; 53—Thirteenth connecting electrode; 54—Fourteenth connecting electrode; 55—Fifteenth connecting electrode; 56—Sixteenth connecting electrode; 61—First data signal line; 62—Second data signal line; 63—Third data signal line; 64—Fourth data signal line; 71—First power line; 72—Second power line; 73—Compensation signal line; 81—Electrode plate connecting electrode; 82—Auxiliary connecting electrode; 91—Anode; 92—Anode connecting electrode; 93—Auxiliary cathode; 100—Repetition unit; 110—Display area; 110-1—First area; 110-2—Second area; 120—Transparent area; 300—Substrate; 301—First insulating layer; 302—Second insulating layer; 303—Third insulating layer. Detailed Implementation

[0055] To make the objectives, technical solutions, and advantages of this disclosure clearer, embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be varied in various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0056] The scale of the figures in this disclosure can be used as a reference in actual manufacturing processes, but is not limited thereto. For example, the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The figures described in this disclosure are only schematic diagrams of the structure, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0057] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0058] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0059] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0060] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0061] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged, and the "source terminal" and "drain terminal" can be interchanged.

[0062] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0063] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0064] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0065] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.

[0066] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0067] Figure 1 is a schematic diagram of a display device. As shown in Figure 1, the OLED display device may include a timing controller, a data driver, a scan driver, and a pixel array. The timing controller is connected to both the data driver and the scan driver. The data driver is connected to multiple data signal lines (D1 to Dn), and the scan driver is connected to multiple scan signal lines (S1 to Sm). The pixel array may include multiple sub-pixels Pxij, each sub-pixel Pxij being connected to a corresponding data signal line and a corresponding scan signal line, where i and j can be natural numbers. At least one sub-pixel Pxij may include at least a circuit unit and a display unit. The circuit unit may include at least a pixel driving circuit, which is connected to both the scan signal line and the data signal line. The display unit may include at least a light-emitting device, which is connected to the pixel driving circuit of the circuit unit. The sub-pixel Pxij may refer to a sub-pixel whose pixel driving circuit is connected to the i-th scan signal line and connected to the j-th data signal line. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals of specifications suitable for the data driver to the data driver, and may provide clock signals, scan start signals, etc., of specifications suitable for the scan driver to the scan driver. The data driver can use grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to data signal lines D1, D2, D3, ..., Dn, where n can be a natural number. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn on a pixel-row basis. The scan driver can generate scan signals to be provided to scan signal lines S1, S2, S3, ..., Sm by receiving clock signals, scan start signals, etc., from the timing controller. For example, the scan driver can sequentially provide scan signals with on-level pulses to scan signal lines S1 to Sm, where m can be a natural number. The scan driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals, provided in the form of on-level pulses, to the next stage circuit under the control of a clock signal. In an exemplary embodiment, a pixel array can be disposed on a display substrate.

[0068] Figure 2 is a schematic diagram of a planar structure of a display substrate. As shown in Figure 2, in an exemplary embodiment, the display substrate may include a plurality of repeating units 100 arranged in a regular pattern. At least one repeating unit 100 may include a display area 110 and a light-transmitting area 120. The display area 110 may include a plurality of sub-pixels. At least one sub-pixel may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit, and the light-emitting unit may include at least a light-emitting device. The light-emitting device of the light-emitting unit is connected to the pixel driving circuit of the corresponding circuit unit. The display area 110 is configured to display an image. The light-transmitting area 120 may be located on at least one side of the display area 110 in the repeating unit 100. The light-transmitting area 120 is configured to transmit light, so that the repeating unit 100 can achieve image display in a transparent state, i.e., transparent display. In the exemplary embodiment, the repeating unit is the basic unit constituting the display substrate. The display substrate is formed by repeating and continuously arranging the repeating units along at least one direction. That is, the display substrate is composed of a plurality of repeating units spliced ​​together.

[0069] An exemplary embodiment of this disclosure provides a display substrate including a plurality of repeating units arranged in a regular pattern. At least one repeating unit includes a display area and a light-transmitting area disposed on one side of a first direction or the opposite side of the first direction of the display area. The display area is configured to display an image, and the light-transmitting area is configured to transmit light. The display area includes a plurality of sub-pixels arranged sequentially along a second direction, wherein the first direction and the second direction intersect. At least one sub-pixel includes a pixel driving circuit and a light-emitting device connected to the pixel driving circuit. The pixel driving circuit is connected to a first power line, a data signal line, and a compensation signal line, respectively, and the light-emitting device is connected to a second power line. The display area includes a first area and a second area disposed on the side of the first area away from the light-transmitting area. The pixel driving circuit of the plurality of sub-pixels is disposed in the first area, and the first power line, the second power line, the data signal line, and the compensation signal line are disposed in the second area.

[0070] In an exemplary embodiment, in the first direction, the compensation signal line is disposed between the data signal line and the first power line, and the first power line is disposed between the compensation signal line and the second power line.

[0071] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate includes a plurality of conductive layers disposed on the substrate, wherein the first power line and the data signal line are disposed in the same conductive layer, the compensation signal line and the second power line are disposed in the same conductive layer, and the first power line and the second power line are disposed in different conductive layers.

[0072] In an exemplary embodiment, the storage capacitor includes a first capacitor and a second capacitor connected in parallel. The first capacitor includes a first electrode and a second electrode stacked on top of each other. The orthographic projection of the first electrode on the display substrate plane overlaps with the orthographic projection of the second electrode on the display substrate plane. The second capacitor includes a third electrode, a fourth electrode, and a fifth electrode stacked on top of each other. The orthographic projections of the third electrode, the fourth electrode, and the fifth electrode on the display substrate plane overlap with each other. The first electrode and the third electrode are connected, the third electrode and the fifth electrode are connected, and the second electrode and the fourth electrode are connected.

[0073] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate includes at least a first transparent conductive layer disposed on a substrate, a first conductive layer disposed on a side of the first transparent conductive layer away from the substrate, and a semiconductor layer disposed on a side of the first conductive layer away from the substrate; a first electrode plate is disposed in the first transparent conductive layer, and a second electrode plate is disposed in the semiconductor layer, forming a transparent first capacitor.

[0074] In an exemplary embodiment, the display substrate further includes a second conductive layer disposed on the side of the semiconductor layer away from the substrate, and a third conductive layer disposed on the side of the second conductive layer away from the substrate; the third electrode plate is disposed in the first conductive layer, the fourth electrode plate is disposed in the second conductive layer, and the fifth electrode plate is disposed in the third conductive layer.

[0075] In an exemplary embodiment, the display substrate further includes a second conductive layer disposed on the side of the semiconductor layer away from the substrate, and a third conductive layer disposed on the side of the second conductive layer away from the substrate; the third electrode plate is disposed in the first conductive layer, the fourth electrode plate is disposed in the semiconductor layer, and the fifth electrode plate is disposed in the third conductive layer.

[0076] The display substrate of this disclosure will be illustrated by some exemplary embodiments below.

[0077] An exemplary embodiment of this disclosure provides a display substrate. On a plane parallel to the display substrate, the display substrate may include a plurality of regularly arranged repeating units. At least one repeating unit may include a display area and a light-transmitting area. The display area is configured to display an image, and the light-transmitting area is configured to allow light to pass through, thereby achieving a transparent display. In a direction perpendicular to the display substrate, the display substrate may include at least a driving circuit layer disposed on a substrate and a light-emitting structure layer disposed on the side of the driving circuit layer away from the substrate. In at least one repeating unit, the driving circuit layer of the display area may include a plurality of circuit units, and the light-emitting structure layer of the display area may include a plurality of light-emitting units. Each circuit unit may include at least a pixel driving circuit, and each light-emitting unit may include at least a light-emitting device. The light-emitting device is connected to the pixel driving circuit of the corresponding circuit unit.

[0078] In exemplary embodiments, the circuit unit referred to in this disclosure refers to a region divided according to the pixel driving circuit, and the light-emitting unit referred to in this disclosure refers to a region divided according to the light-emitting device. In exemplary embodiments, the position of the orthographic projection of the light-emitting unit on the substrate may correspond to the position of the orthographic projection of the circuit unit on the substrate, or the position of the orthographic projection of the light-emitting unit on the substrate may not correspond to the position of the orthographic projection of the circuit unit on the substrate.

[0079] In the exemplary embodiments of this disclosure, the position of the circuit unit projected onto the substrate corresponds one-to-one with the position of the light-emitting unit projected onto the substrate. The circuit unit and the light-emitting unit constitute a sub-pixel. Therefore, in the following content, sub-pixel is used to refer to the circuit unit and the light-emitting unit.

[0080] Figure 3 is a schematic diagram of the arrangement of sub-pixels in a repeating unit according to an exemplary embodiment of the present disclosure, illustrating the structure of a repeating unit. As shown in Figure 3, the repeating unit may include a display area 110 and a light-transmitting area 120, and the light-transmitting area 120 may be located on one side of the display area 110 in the first direction X or on the opposite side of the first direction X.

[0081] In an exemplary embodiment, the display area 110 may include four sub-pixels, namely a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3, and a fourth sub-pixel P4. The four sub-pixels are arranged vertically along the second direction Y. Compared with horizontal and square arrangements, the vertical arrangement of sub-pixels in this disclosure can effectively increase the area of ​​the light-transmitting region and improve the transmittance.

[0082] In an exemplary embodiment, the second sub-pixel P2 can be disposed on one side of the first sub-pixel P1 in the second direction Y, the third sub-pixel P3 can be disposed on one side of the second sub-pixel P2 in the second direction Y, and the fourth sub-pixel P4 can be disposed on one side of the third sub-pixel P3 in the second direction Y.

[0083] In an exemplary embodiment, the first direction X intersects with the second direction Y.

[0084] In an exemplary embodiment, the first sub-pixel P1 may be a red sub-pixel (R) that emits red light, the second sub-pixel P2 may be a green sub-pixel (G) that emits green light, the third sub-pixel P3 may be a blue sub-pixel (B) that emits blue light, and the fourth sub-pixel P4 may be a white sub-pixel (W) that emits white light.

[0085] In some possible implementations, the arrangement of the four sub-pixels can be adjusted according to actual needs, and this disclosure does not limit it.

[0086] In some possible implementations, the display area 110 may include three sub-pixels arranged vertically, which is not limited herein.

[0087] Figure 4 shows an equivalent circuit diagram of a pixel driving circuit according to an exemplary embodiment of this disclosure. As shown in Figure 4, the pixel driving circuit of this disclosure can be a 3T1C structure. The pixel driving circuit can include three transistors (first transistor T1, second transistor T2, and third transistor T3) and a storage capacitor C. The pixel driving circuit is connected to the scan signal line S, the first power supply line VDD, the data signal line D, and the compensation signal line B, respectively.

[0088] In an exemplary embodiment, the pixel driving circuit may include at least a first node N1 and a second node N2. The first node N1 is connected to the second electrode of the first transistor T1, the gate electrode of the second transistor T2, and the first terminal of the storage capacitor C, respectively. The second node N2 is connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the second terminal of the storage capacitor C, respectively.

[0089] In an exemplary embodiment, the first end of the storage capacitor C is connected to the first node N1, and the second end of the storage capacitor C is connected to the second node N2. The storage capacitor C is used to store the potential of the gate electrode of the second transistor T2.

[0090] In an exemplary embodiment, the gate electrode of the first transistor T1 is connected to the scan signal line S, the first terminal of the first transistor T1 is connected to the data signal line D, and the second terminal of the first transistor T1 is connected to the first node N1. The gate electrode of the second transistor T2 is connected to the first node N1, the first terminal of the second transistor T2 is connected to the first power supply line VDD, and the second terminal of the second transistor T2 is connected to the second node N2. The gate electrode of the third transistor T3 is connected to the scan signal line S, the first terminal of the third transistor T3 is connected to the compensation signal line B, and the second terminal of the third transistor T3 is connected to the second node N2.

[0091] In an exemplary embodiment, in the pixel driving circuit of at least one sub-pixel, the gate electrode of the first transistor T1 and the gate electrode of the third transistor T3 are connected to the same scan signal line S.

[0092] In an exemplary embodiment, the first electrode of the light-emitting device EL is connected to the second node N2, and the second electrode of the light-emitting device EL is connected to the second power line VSS. The light-emitting device EL can be an OLED, including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode), or it can be a QLED, including a stacked first electrode (anode), a quantum dot light-emitting layer, and a second electrode (cathode).

[0093] In an exemplary embodiment, the signal of the first power line VDD is a continuously provided high-level signal, and the signal of the second power line VSS is a continuously provided low-level signal.

[0094] In an exemplary embodiment, the first transistor T1 to the third transistor T3 can be either P-type transistors or N-type transistors. Using the same type of transistor in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield.

[0095] In an exemplary embodiment, the first transistor T1 to the third transistor T3 can be low-temperature polysilicon (LTPS) transistors, or oxide transistors, or a combination of both. The active layer of the LTPS transistor is made of low-temperature polysilicon (LTPS), while the active layer of the oxide transistor is made of oxide semiconductor. LTPS transistors have advantages such as high mobility and fast charging, while oxide transistors have advantages such as low leakage current. Integrating LTPS transistors and oxide transistors onto a single display substrate, i.e., an LTPS+Oxide (LTPO) display substrate, leverages the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0096] Figure 5 is a schematic diagram of the structure of a display substrate according to an exemplary embodiment of the present disclosure, illustrating the structure of a repeating unit. As shown in Figure 5, the repeating unit may include a display area 110 and a light-transmitting area 120. The light-transmitting area 120 may be located on the opposite side of the first direction X of the display area 110. The display area 110 may include a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3, and a fourth sub-pixel P4 arranged vertically. At least one sub-pixel may include a pixel driving circuit and a light-emitting device.

[0097] In an exemplary embodiment, the pixel driving circuit of at least one sub-pixel can be connected to a first power line 71, a compensation signal line 73, and a corresponding data signal line, respectively. The first power line 71 is configured to provide a first power signal to the connected pixel driving circuit, the compensation signal line 73 is configured to provide a compensation signal to the connected pixel driving circuit, and the data signal line is configured to provide a data signal to the connected pixel driving circuit. The light-emitting device of at least one sub-pixel can be connected to a second power line 72, which is configured to provide a second power signal to the connected light-emitting device.

[0098] In an exemplary embodiment, at least one repeating unit may include a first power line 71, a compensation signal line 73, and four data signal lines. The first power line 71 simultaneously provides a first power signal to the pixel driving circuits in the first sub-pixel P1 to the fourth sub-pixel P4, forming a one-to-four structure of the first power line 71. The compensation signal line 73 simultaneously provides a compensation signal to the pixel driving circuits in the first sub-pixel P1 to the fourth sub-pixel P4, forming a one-to-four structure of the compensation signal line 73. The four data signal lines respectively provide data signals to the pixel driving circuits in the first sub-pixel P1 to the fourth sub-pixel P4.

[0099] In an exemplary embodiment, the four data signal lines in at least one repeating unit can be a first data signal line 61, a second data signal line 62, a third data signal line 63, and a fourth data signal line 64, respectively. The first data signal line 61 is configured to provide a data signal to the pixel driving circuit in the fourth sub-pixel P4, the second data signal line 62 is configured to provide a data signal to the pixel driving circuit in the third sub-pixel P3, the third data signal line 63 is configured to provide a data signal to the pixel driving circuit in the second sub-pixel P2, and the fourth data signal line 64 is configured to provide a data signal to the pixel driving circuit in the first sub-pixel P1.

[0100] In an exemplary embodiment, at least one display area 110 can be divided into a first area 110-1 and a second area 110-2. The second area 110-2 can be located on the side of the first area 110-1 away from the light-transmitting area 120. The first area 110-1 is configured to accommodate a pixel driving circuit for multiple sub-pixels. The second area 110-2 is configured to accommodate a first data signal line 61 to a fourth data signal line 64, a first power line 71, a second power line 72, and a compensation signal line 73. That is, multiple pixel driving circuits can be located on the side of the display area 110 close to the light-transmitting area 120, and multiple signal lines can be located on the side of the display area 110 away from the light-transmitting area 120.

[0101] In an exemplary embodiment, the shapes of the first data signal line 61 to the fourth data signal line 64, the first power line 71, the second power line 72, and the compensation signal line 73 can be straight lines or broken lines extending along the second direction Y of the main body. The first data signal line 61 can be located on the side of the second region 110-2 close to the first region 110-1. The second data signal line 62 can be located on the side of the first data signal line 61 away from the first region 110-1. The third data signal line 63 can be located on the side of the second data signal line 62 away from the first region 110-1. The fourth data signal line 64 can be located on the side of the third data signal line 63 away from the first region 110-1. The compensation signal line 73 can be located on the side of the fourth data signal line 64 away from the first region 110-1. The first power line 71 can be located on the side of the compensation signal line 73 away from the first region 110-1. The second power line 72 can be located on the side of the first power line 71 away from the first region 110-1. On one side, namely the first data signal line 61, the second data signal line 62, the third data signal line 63, the fourth data signal line 64, the compensation signal line 73, the first power line 71 and the second power line 72 can be arranged sequentially along the first direction X.

[0102] In an exemplary embodiment, in the first direction X, the compensation signal line 73 may be disposed between the fourth data signal line 64 and the first power line 71, and the first power line 71 may be disposed between the compensation signal line 73 and the second power line 72.

[0103] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate may include a plurality of conductive layers disposed on the substrate. The first data signal line 61 to the fourth data signal line 64 and the first power line 71 may be disposed in the same conductive layer, the second power line 72 and the compensation signal line 73 may be disposed in the same conductive layer, and the first power line 71 and the second power line 72 may be disposed in different conductive layers.

[0104] In an exemplary embodiment, at least one pixel driving circuit may include at least a first transistor T1 as a data writing transistor, a second transistor T2 as a driving transistor, and a third transistor T3 as a sensing transistor. The first terminal of the first transistor T1 is connected to the corresponding data signal line, the second terminal of the first transistor T1 is connected to the gate electrode of the second transistor T2, the first terminal of the second transistor T2 is connected to the first power supply line 71, the second terminal of the second transistor is connected to the second terminal of the third transistor T3, and the first terminal of the third transistor T3 is connected to the compensation signal line 73.

[0105] In an exemplary embodiment, in at least one repeating unit, the positions of transistors in adjacent sub-pixels can be arranged symmetrically in pairs. For example, the positions of the first transistor T1, the second transistor T2, and the third transistor T3 in the first sub-pixel P1 and the second sub-pixel P2 can be substantially symmetrically arranged with respect to the sub-pixel center line. Similarly, the positions of the first transistor T1, the second transistor T2, and the third transistor T3 in the third sub-pixel P3 and the fourth sub-pixel P4 can be substantially symmetrically arranged with respect to the sub-pixel center line. Furthermore, the positions of the first transistor T1, the second transistor T2, and the third transistor T3 in the second sub-pixel P2 and the third sub-pixel P3 can be substantially symmetrically arranged with respect to the sub-pixel center line. The sub-pixel center line can be a straight line located between adjacent sub-pixels and extending along a first direction X.

[0106] In an exemplary embodiment, in at least one sub-pixel, the gate electrode of the first transistor T1 and the gate electrode of the third transistor T3 are connected to the same scan signal line 30.

[0107] In an exemplary embodiment, in at least one repeating unit, the gate electrodes of four first transistors T1 and the gate electrodes of four third transistors T3 are connected to the same scan signal line 30.

[0108] In an exemplary embodiment, in at least one repeating unit, the scanning signal line 30 may include at least a first ring structure 30A, a second ring structure 30B, a ring connecting line 35, and a scanning transmission line 36. The first ring structure 30A, the second ring structure 30B, and the ring connecting line 35 may be disposed in the display area 110, and the scanning transmission line 36 may be disposed in the light-transmitting area 120.

[0109] In an exemplary embodiment, the first ring structure 30A can be disposed in the first sub-pixel P1 and the second sub-pixel P2, and the second ring structure 30B can be disposed in the third sub-pixel P3 and the fourth sub-pixel P4. The shape of the ring connecting line 35 can be a straight line or a broken line extending along the second direction Y of the main body, and it can be disposed between the first ring structure 30A and the second ring structure 30B. The first end of the ring connecting line 35 is connected to the first ring structure 30A, and the second end of the ring connecting line 35 is connected to the second ring structure 30B, so that the first ring structure 30A and the second ring structure 30B are connected to each other through the ring connecting line 35.

[0110] In an exemplary embodiment, in at least one repeating unit, the first ring structure 30A, the second ring structure 30B, and the ring connecting line 35 can be an integral structure that is interconnected.

[0111] In an exemplary embodiment, the shape of the scanning transmission line 36 can be a straight line or a broken line extending along the first direction X of the main body. The first end of the scanning transmission line 36 is connected to the second ring structure 30B in the repeating unit, and the second end of the scanning transmission line 36 is connected to the second ring structure 30B in the adjacent repeating unit in the first direction X.

[0112] In an exemplary embodiment, in two adjacent repeating units in the first direction X, the scanning transmission lines 36 in the two light-transmitting areas 120 can be staggered, that is, the scanning transmission lines 36 in the two light-transmitting areas 120 are not on the same straight line extending along the first direction X.

[0113] In an exemplary embodiment, in at least one repeating unit, the first ring structure 30A, the second ring structure 30B, the ring connecting line 35, and the scanning transmission line 36 can be an integral structure that is interconnected.

[0114] In an exemplary embodiment, the first annular structure 30A may include at least two gate electrode lines 31, a first scan connection line 33, and a second scan connection line 34. The gate electrode lines 31 are straight or broken lines extending along the first direction X. The two gate electrode lines are respectively disposed in the first sub-pixel P1 and the second sub-pixel P2. The first scan connection line 33 and the second scan connection line 34 are straight or broken lines extending along the second direction Y. They are both disposed across the first sub-pixel P1 and the second sub-pixel P2. The first scan connection line 34 is connected to the ends of the two gate electrode lines in the opposite direction of the first direction X. The second scan connection line 34 is connected to the ends of the two gate electrode lines in the first direction X, thus forming the first annular structure 30A.

[0115] In an exemplary embodiment, the second annular structure 30B may include at least two gate electrode lines 31, a first scan connection line 33, and a second scan connection line 34. The gate electrode lines 31 are straight or broken lines extending along the first direction X. The two gate electrode lines are respectively disposed in the third sub-pixel P3 and the fourth sub-pixel P4. The first scan connection line 33 and the second scan connection line 34 are straight or broken lines extending along the second direction Y, and are both disposed across the third sub-pixel P3 and the fourth sub-pixel P4. The first scan connection line 34 is connected to the ends of the two gate electrode lines in the opposite direction of the first direction X, and the second scan connection line 34 is connected to the ends of the two gate electrode lines in the first direction X, thus forming the second annular structure 30B.

[0116] In an exemplary embodiment, in at least one repeating unit, all longitudinal signal lines are located between the first scan connection line 33 and the second scan connection line 34. The orthographic projections of the first ring structure 30A and the second ring structure 30B on the display substrate plane at least partially overlap with the orthographic projections of the first data signal line 61, the second data signal line 62, the third data signal line 63, the fourth data signal line 64, the compensation signal line 73, the first power line 71, and the second power line 72 on the display substrate plane, that is, all longitudinal signal lines are located within the first ring structure 30A and the second ring structure 30B.

[0117] In an exemplary embodiment, a first protruding structure 37 may be provided on the first annular structure 30A. The first protruding structure 37 may be provided on one side of the first annular structure 30A in the first direction X and protrude toward the light-transmitting area 120 in the adjacent repeating unit in the first direction X. The orthographic projection of the first protruding structure 37 on the display substrate plane and the orthographic projection of the light-transmitting area 120 on the display substrate plane at least partially overlap.

[0118] In an exemplary embodiment, a second protruding structure 38 may be provided on the second annular structure 30B. The second protruding structure 38 may be provided on one side of the second annular structure 30B in the first direction X and protrude toward the light-transmitting area 120 in the adjacent repeating unit in the first direction X. The orthographic projection of the second protruding structure 38 on the display substrate plane and the orthographic projection of the light-transmitting area 120 on the display substrate plane at least partially overlap.

[0119] In an exemplary embodiment, in at least one repeating unit, the first protruding structure 37 and the second protruding structure 38 have different protrusion lengths, and the protrusion length can be the dimension in the first direction X.

[0120] Figure 6 is a schematic diagram of the structure of a storage capacitor according to an exemplary embodiment of the present disclosure, and is a cross-sectional view along line AA in Figure 5. As shown in Figures 5 and 6, at least one pixel driving circuit may further include a first capacitor 10-1 and a second capacitor 10-2, wherein the first capacitor 10-1 and the second capacitor 10-2 are connected in parallel, and together they constitute the storage capacitor of the pixel driving circuit.

[0121] In an exemplary embodiment, the first capacitor 10-1 may include a first electrode 11 and a second electrode 12 stacked together, with an overlapping area between the orthographic projection of the first electrode 11 onto the display substrate plane and the orthographic projection of the second electrode 12 onto the display substrate plane. The second capacitor 10-2 may include a third electrode 13, a fourth electrode 14, and a fifth electrode 15 stacked together, with an overlapping area between the orthographic projections of the third electrode 13, the fourth electrode 14, and the fifth electrode 15 onto the display substrate plane.

[0122] In an exemplary embodiment, the first electrode 11 and the third electrode 13 are connected, the third electrode 13 and the fifth electrode 15 are connected, and the second electrode 12 and the fourth electrode 14 are connected. Therefore, the first electrode 11, the third electrode 13 and the fifth electrode 15 have the same potential, and the second electrode 12 and the fourth electrode 14 have the same potential. The first capacitor 10-1 and the second capacitor 10-2 in parallel structure form a complete storage capacitor.

[0123] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate may include at least: a substrate 300, a first transparent conductive layer disposed on the substrate 300, a first conductive layer disposed on the side of the first transparent conductive layer away from the substrate 300, a first insulating layer 301 disposed on the side of the first conductive layer away from the substrate 300, a semiconductor layer disposed on the side of the first insulating layer 301 away from the substrate 300, a second insulating layer 302 disposed on the side of the semiconductor layer away from the substrate 300, a second conductive layer disposed on the side of the second insulating layer 302 away from the substrate 300, a third insulating layer 303 disposed on the side of the second conductive layer away from the substrate 300, and a third conductive layer disposed on the side of the third insulating layer 303 away from the substrate 300.

[0124] In an exemplary embodiment, the first transparent conductive layer may include at least a first electrode 11, which may be disposed in the display area 110 and the light-transmitting area 120. The first electrode 11 may serve as the transparent lower electrode of the first capacitor 10-1.

[0125] In an exemplary embodiment, the first conductive layer may include at least a third electrode plate 13, which can serve as the lower electrode plate of the second capacitor 10-2. The third electrode plate 13 is connected to the first electrode plate 11, thereby enabling the first electrode plate 11 and the third electrode plate 13 to have the same potential.

[0126] In an exemplary embodiment, the semiconductor layer may include at least a second electrode 12, a second active layer 22 and a third active layer 23. The second electrode 12 may serve as the transparent upper electrode of the first capacitor 10-1. The first electrode 11 and the second electrode 12 constitute the first capacitor 10-1.

[0127] In an exemplary embodiment, the orthographic projections of the first electrode plate 11 and the second electrode plate 12 onto the substrate at least partially overlap with the orthographic projection of the light-transmitting region 120 onto the substrate.

[0128] In an exemplary embodiment, the second conductive layer may include at least a fourth electrode plate 14 and a second gate electrode 32. The fourth electrode plate 14 may serve as the intermediate electrode plate of the second capacitor 10-2, and the fourth electrode plate 14 and the second gate electrode 32 may be an integral structure that is interconnected.

[0129] In an exemplary embodiment, the third conductive layer may include at least a fifth electrode 15 and an eighth connecting electrode 48. The fifth electrode 15 can serve as the upper electrode of the second capacitor 10-2. The fifth electrode 15 is connected to both the third active layer 23 and the third electrode 13 through a sixth via V6, enabling the third electrode 13 and the fifth electrode 15 to have the same potential. The third electrode 13, the fourth electrode 14, and the fifth electrode 15 constitute the second capacitor 10-2. The eighth connecting electrode 48 is connected to both the second electrode 12 and the second gate electrode 32 through a seventh via V7. Since the second gate electrode 32 is connected to the fourth electrode 14, the second electrode 12 and the fourth electrode 14 have the same potential.

[0130] In an exemplary embodiment, the first data signal line 61 to the fourth data signal line 64 and the first power line 71 may be disposed in the first conductive layer, the scan signal line 30 may be disposed in the second conductive layer, and the second power line 72 and the compensation signal line 73 may be disposed in the third conductive layer.

[0131] The following description uses the fabrication process of a display substrate as an example. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film made of a certain material on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0132] In an exemplary embodiment, taking four sub-pixels (first sub-pixel P1, second sub-pixel P2, third sub-pixel P3 and fourth sub-pixel P4) of a repeating unit as an example, the fabrication process of the display substrate in this embodiment may include the following operations.

[0133] (11) Forming a first transparent conductive layer pattern. In an exemplary embodiment, forming a first transparent conductive layer pattern may include: depositing a first transparent conductive film on a substrate, patterning the first transparent conductive film using a patterning process, and forming a first transparent conductive layer pattern on the substrate, as shown in FIG7. In an exemplary embodiment, the first transparent conductive layer may be referred to as the 1st ITO layer.

[0134] In an exemplary embodiment, the first transparent conductive layer pattern of each sub-pixel in the display substrate may include at least the first electrode 11 of the storage capacitor.

[0135] In an exemplary embodiment, the shape of the first electrode plate 11 can be a strip (such as a rectangle) extending along the first direction X. The corners of the strip shape can be chamfered or grooved, and the edge of the strip shape can be a broken line. It can be set in the display area 110 and the light-transmitting area 120. The first electrode plate 11 can serve as the transparent lower electrode plate of the first capacitor. The first electrode plate 11 and the second electrode plate formed subsequently form the first capacitor of the storage capacitor.

[0136] In an exemplary embodiment, in the first direction X, the first electrode 11 can extend from the display area 110 to the light-transmitting area 120, or the first electrode 11 can extend from the light-transmitting area 120 to the display area 110. In the second direction Y, the first electrode 11 can be disposed on one side of each sub-pixel in the second direction Y. For example, the first electrode 11 in the first sub-pixel P1 can be located on the side away from the second sub-pixel P2, and the first electrode 11 in the second sub-pixel P2 can be located on the side away from the first sub-pixel P1. As another example, the first electrode 11 in the third sub-pixel P3 can be located on the side away from the fourth sub-pixel P4, and the first electrode 11 in the fourth sub-pixel P4 can be located on the side away from the third sub-pixel P3.

[0137] In an exemplary embodiment, the first electrode plate 11 in the first sub-pixel P1 and the second sub-pixel P2 can be arranged substantially symmetrically with respect to the sub-pixel center line, the first electrode plate 11 in the second sub-pixel P2 and the third sub-pixel P3 can be arranged substantially symmetrically with respect to the sub-pixel center line, and the first electrode plate 11 in the third sub-pixel P3 and the fourth sub-pixel P4 can be arranged substantially symmetrically with respect to the sub-pixel center line. The sub-pixel center line can be a straight line located between adjacent sub-pixels and extending along the first direction X.

[0138] In an exemplary embodiment, the material of the first transparent conductive layer can be a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0139] (12) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern includes: depositing a first conductive thin film on a substrate on which the aforementioned pattern is formed, patterning the first conductive thin film using a patterning process, and forming the first conductive layer pattern on a first transparent conductive layer, as shown in Figures 8A and 8B. In an exemplary embodiment, the first conductive layer may be referred to as a shielding metal (SHL) layer.

[0140] In an exemplary embodiment, the first conductive layer of each sub-pixel in the display substrate may include at least a third electrode 13 for storing capacitors, a first connecting electrode 41, and a second connecting electrode 42.

[0141] In an exemplary embodiment, the third electrode plate 13 may be rectangular in shape, and the corners of the rectangle may be chamfered or grooved. The third electrode plate 13 may serve as the lower electrode plate of the second capacitor, and the third electrode plate 13 may be configured to form the first sub-capacitor of the second capacitor together with the subsequently formed fourth electrode plate.

[0142] In an exemplary embodiment, the third electrode 13 may be disposed in the display area 110 in the first direction X. In the second direction Y, the third electrode 13 may be disposed on the side of each sub-pixel closest to the first electrode 11.

[0143] In an exemplary embodiment, the third electrode plate 13 in the first sub-pixel P1 may be located in a region away from the second sub-pixel P2 and overlap with the first electrode plate 11 in the first sub-pixel P1. Similarly, the third electrode plate 13 in the second sub-pixel P2 may be located in a region away from the first sub-pixel P1 and overlap with the first electrode plate 11 in the second sub-pixel P2. The third electrode plate 13 in the third sub-pixel P3 may be located in a region away from the fourth sub-pixel P4 and overlap with the first electrode plate 11 in the third sub-pixel P3. Finally, the third electrode plate 13 in the fourth sub-pixel P4 may be located in a region away from the third sub-pixel P3 and overlap with the first electrode plate 11 in the fourth sub-pixel P4.

[0144] In an exemplary embodiment, since the first electrode plate 11 and the third electrode plate 13 in each sub-pixel are connected together, the first electrode plate 11 and the third electrode plate 13 in each sub-pixel have the same potential.

[0145] In an exemplary embodiment, the third plate 13 in each sub-pixel is further configured to block light from the second transistor T2 in the sub-pixel, thereby reducing the light intensity illuminating the second transistor T2, reducing the leakage current of the second transistor T2, and thus reducing the impact of light on the characteristics of the second transistor T2.

[0146] In an exemplary embodiment, the first connecting electrode 41 may be block-shaped (e.g., rectangular) and may be disposed on the side of the third electrode plate 13 away from the first electrode plate 11.

[0147] In an exemplary embodiment, the second connecting electrode 42 may be block-shaped (e.g., rectangular) and may be disposed on the side of the third electrode plate 13 away from the first electrode plate 11.

[0148] In an exemplary embodiment, in the first direction X, the first connecting electrode 41 may be disposed on one side of the second connecting electrode 42 in the first direction X, and in the second direction Y, the first connecting electrode 41 and the second connecting electrode 42 may be substantially flush.

[0149] In an exemplary embodiment, the first conductive layer of each repeating unit in the display substrate may further include a first data signal line 61, a second data signal line 62, a third data signal line 63, a fourth data signal line 64, and a first power supply line 71.

[0150] In an exemplary embodiment, the shape of the first data signal line 61 can be a straight line or a broken line extending along the second direction Y of the main body, and can be disposed on one side of the third electrode plate 13 in the first direction X.

[0151] In an exemplary embodiment, a first data connection block 61-1 may be provided on the first data signal line 61. The shape of the first data connection block 61-1 may be block-shaped (such as rectangular), and it may be provided in the fourth sub-pixel P4. The first end of the first data connection block 61-1 is connected to the first data signal line 61, and the second end of the first data connection block 61-1 is connected to the first connection electrode 41 in the fourth sub-pixel P4.

[0152] In an exemplary embodiment, in at least one repeating unit, the first data signal line 61, the first data connection block 61-1, and the first connection electrode 41 in the fourth sub-pixel P4 can be an integral structure that is interconnected.

[0153] In an exemplary embodiment, the shape of the second data signal line 62 can be a straight line or a broken line extending along the second direction Y of the main body, and can be disposed on one side of the first data signal line 61 in the first direction X.

[0154] In an exemplary embodiment, a second data connection block 62-1 may be provided on the second data signal line 62. The second data connection block 62-1 may be block-shaped (e.g., rectangular), may be disposed in the third sub-pixel P3, and may be connected to the second data signal line 62. The second data connection block 62-1 is configured to be connected to the first connection electrode 41 in the third sub-pixel P3 through a subsequently formed connection electrode.

[0155] In an exemplary embodiment, in at least one repeating unit, the second data signal line 62 and the second data connection block 62-1 can be an integral structure that is interconnected.

[0156] In an exemplary embodiment, the shape of the third data signal line 63 can be a straight line or a broken line extending along the second direction Y of the main body, and can be disposed on one side of the second data signal line 62 in the first direction X.

[0157] In an exemplary embodiment, a third data connection block 63-1 may be provided on the third data signal line 63. The third data connection block 63-1 may be block-shaped (e.g., rectangular), may be disposed in the second sub-pixel P2, and may be connected to the third data signal line 63. The third data connection block 63-1 is configured to be connected to the first connection electrode 41 in the second sub-pixel P2 through a subsequently formed connection electrode.

[0158] In an exemplary embodiment, in at least one repeating unit, the third data signal line 63 and the third data connection block 63-1 can be an integral structure that is interconnected.

[0159] In an exemplary embodiment, the shape of the fourth data signal line 64 can be a straight line or a broken line extending along the second direction Y of the main body, and it can be disposed on one side of the third data signal line 63 in the first direction X.

[0160] In an exemplary embodiment, a fourth data connection block 64-1 may be provided on the fourth data signal line 64. The fourth data connection block 64-1 may be block-shaped (e.g., rectangular), may be disposed in the first sub-pixel P1, and may be connected to the fourth data signal line 64. The fourth data signal line 64 is configured to be connected to the first connection electrode 41 in the first sub-pixel P1 through a subsequently formed connection electrode.

[0161] In an exemplary embodiment, in at least one repeating unit, the fourth data signal line 64 and the fourth data connection block 64-1 can be an integral structure that is interconnected.

[0162] In an exemplary embodiment, in at least one repeating unit, the first data signal line 61 and the second data signal line 62, the second data signal line 62 and the third data signal line 63, and the third data signal line 63 and the fourth data signal line 64 may have substantially the same first spacing S1, which may be the dimension of the first direction X.

[0163] In an exemplary embodiment, the first spacing S1 may be the minimum spacing between adjacent data signal lines. For example, the first spacing S1 may be the minimum spacing between the edge of the first data signal line 61 near the second data signal line 62 and the edge of the second data signal line 62 near the first data signal line 61.

[0164] In an exemplary embodiment, the shape of the first power line 71 can be a straight line or a broken line extending along the second direction Y of the main body, and it can be disposed on one side of the fourth data signal line 64 in the first direction X.

[0165] In an exemplary embodiment, the first data signal line 61, the second data signal line 62, the third data signal line 63, the fourth data signal line 64, and the first power line 71 are all disposed on one side of the third electrode plate 13 in the first direction X. The overall layout of the repeating unit of this disclosure is that all longitudinal lines are arranged on the same side, which can maximize the area of ​​the light-transmitting region and improve the transmittance.

[0166] In an exemplary embodiment, in at least one repeating unit, the display area may include a circuit area (first area) and a trace area (second area) disposed on one side of the circuit area in a first direction X. The circuit area may contain a storage capacitor and multiple transistors, and the trace area may contain multiple signal lines. Thus, in the first direction X, the repeating unit may only include three areas: a light-transmitting area, an area containing the storage capacitor and multiple transistors, and an area containing the signal lines, which can effectively reduce the area occupied by the display area and maximize the area of ​​the light-transmitting area.

[0167] In an exemplary embodiment, the third electrode plate 13, the first connecting electrode 41, and the second connecting electrode 42 in the first sub-pixel P1 and the second sub-pixel P2 can be arranged substantially symmetrically with respect to the center line of the sub-pixel. The third electrode plate 13, the first connecting electrode 41, and the second connecting electrode 42 in the third sub-pixel P3 and the fourth sub-pixel P4 can be arranged substantially symmetrically with respect to the center line of the sub-pixel. The third electrode plate 13, the first connecting electrode 41, and the second connecting electrode 42 in the second sub-pixel P2 and the third sub-pixel P3 can be arranged substantially symmetrically with respect to the center line of the sub-pixel.

[0168] (13) Forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern may include: depositing a first insulating film and a semiconductor film sequentially on a substrate on which the aforementioned pattern is formed, patterning the semiconductor film by a patterning process to form a first insulating layer covering a first conductive layer, and a semiconductor layer disposed on the first insulating layer, as shown in FIG9A and FIG9B, FIG9B being a schematic diagram of the semiconductor layer in FIG9A.

[0169] In an exemplary embodiment, the semiconductor layer of each sub-pixel in the display substrate may include at least a first active layer 21, a second active layer 22, a third active layer 23, and a second electrode plate 12 of a storage capacitor. The first active layer 21 may serve as the active layer of the first transistor T1, the second active layer 22 may serve as the active layer of the second transistor T2, and the third active layer 23 may serve as the active layer of the third transistor T3.

[0170] In an exemplary embodiment, the shape of the second electrode plate 12 can be a strip (such as a rectangle) extending along the first direction X. The corners of the strip shape can be chamfered or grooved, and the edge of the strip shape can be a broken line. It can be set in the display area 110 and the light-transmitting area 120. The orthographic projection of the second electrode plate 12 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate 11 on the substrate. The second electrode plate 12 can serve as the transparent upper electrode plate of the first capacitor. The first electrode plate 11 and the second electrode plate 12 form the first capacitor of the storage capacitor.

[0171] In an exemplary embodiment, in the first direction X, the second electrode 12 can extend from the display area 110 to the light-transmitting area 120, or the second electrode 12 can extend from the light-transmitting area 120 to the display area 110. In the second direction Y, the second electrode 12 can be disposed on one side of each sub-pixel in the second direction Y. For example, the second electrode 12 in the first sub-pixel P1 can be located on the side away from the second sub-pixel P2, and the second electrode 12 in the second sub-pixel P2 can be located on the side away from the first sub-pixel P1. Similarly, the second electrode 12 in the third sub-pixel P3 can be located on the side away from the fourth sub-pixel P4, and the second electrode 12 in the fourth sub-pixel P4 can be located on the side away from the third sub-pixel P3. By disposing a portion of the transparent first electrode 11 and the second electrode 12 in the light-transmitting area 120, this disclosure can effectively increase the capacitance of the first capacitor with minimal impact on transmittance.

[0172] In an exemplary embodiment, the first active layer 21 and the third active layer 23 can be strip-shaped extending along the second direction Y, and the first active layer 21 and the third active layer 23 can be disposed on the side of the sub-pixel away from the second electrode plate 12. The second active layer 22 can be rectangular or "T"-shaped, and the second active layer 22 can be disposed on the side of the sub-pixel closer to the second electrode plate 12.

[0173] In an exemplary embodiment, the active layer of each transistor may include a first region, a second region, and a channel region located between the first region and the second region.

[0174] In an exemplary embodiment, in the first direction X, the first active layer 21 may be disposed on the side of the third active layer 23 near the first data signal line 61. In the second direction Y, the first region 21-1 of the first active layer may be located on the side of the channel region of the first active layer away from the third electrode plate 13, and the second region 21-2 of the first active layer may be located on the side of the channel region of the first active layer near the third electrode plate 13. The orthographic projection of the first region 21-1 of the first active layer on the substrate at least partially overlaps with the orthographic projection of the first connecting electrode 41 on the substrate, and the orthographic projections of the channel region of the first active layer and the second region 21-2 of the first active layer on the substrate do not overlap with the orthographic projection of the third electrode plate 13 on the substrate.

[0175] In an exemplary embodiment, in the first direction X, the first region 22-1 of the second active layer may be located on the side of the channel region of the second active layer close to the first data signal line 61, and the second region 22-2 of the second active layer may be located on the side of the channel region of the second active layer away from the first data signal line 61. The orthographic projection of the channel region of the second active layer and the second region 22-2 of the second active layer on the substrate at least partially overlaps with the orthographic projection of the third electrode plate 13 on the substrate, so that the third electrode plate 13, as a shielding layer, can shield the channel region of the second transistor T2, avoid light from affecting the channel, and ensure the electrical performance of the second transistor T2.

[0176] In an exemplary embodiment, in the first direction X, the third active layer 23 may be disposed on the side of the first active layer 21 away from the first data signal line 61. In the second direction Y, the first region 23-1 of the third active layer may be located on the side of the channel region of the third active layer away from the third electrode plate 13, and the second region 23-2 of the third active layer may be located on the side of the channel region of the third active layer close to the third electrode plate 13. The orthographic projection of the first region 23-1 of the third active layer on the substrate at least partially overlaps with the orthographic projection of the second connecting electrode 42 on the substrate, and the orthographic projection of the second region 23-2 of the third active layer on the substrate at least partially overlaps with the orthographic projection of the third electrode plate 13 on the substrate.

[0177] In an exemplary embodiment, the shapes of the first active layer 21 in the first sub-pixel P1 to the fourth sub-pixel P4 can be substantially the same, the shapes of the third active layer 23 in the first sub-pixel P1 to the fourth sub-pixel P4 can be substantially the same, and the shapes of the second active layer 22 in the first sub-pixel P1 to the fourth sub-pixel P4 can be different.

[0178] In an exemplary embodiment, the shape of the second active layer 22 in the first sub-pixel P1 can be rectangular, and the shape of the second active layer 22 in the second sub-pixels P2 to P4 can be "T" shaped. The active width of the second active layer 22 in the first sub-pixel P1 can be greater than the active width of the second active layer 22 in the second sub-pixels P2 to P4. When the active lengths are substantially the same, the aspect ratio of the second transistor T2 in the first sub-pixel P1 can be greater than the aspect ratio of the second transistor T2 in the second sub-pixels P2 to P4. The active width can be the dimension of the active layer channel region in the second direction Y, and the active length can be the dimension of the active layer channel region in the first direction X.

[0179] In an exemplary embodiment, the first active layer 21, the third active layer 23, and the second electrode plate 12 in the first sub-pixel P1 and the second sub-pixel P2 can be arranged substantially symmetrically with respect to the center line of the sub-pixel, the semiconductor layers in the third sub-pixel P3 and the fourth sub-pixel P4 can be arranged substantially symmetrically with respect to the center line of the sub-pixel, and the semiconductor layers in the second sub-pixel P2 and the third sub-pixel P3 can be arranged substantially symmetrically with respect to the center line of the sub-pixel.

[0180] In an exemplary embodiment, the semiconductor layer may be a metal oxide, such as an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium, and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium, and tin, an oxide containing indium and zinc, an oxide containing silicon, indium, and tin, an oxide containing indium, gallium, and zinc, etc. The semiconductor layer may be a single layer, a double layer, or a multilayer.

[0181] (14) Forming a second conductive layer pattern. In an exemplary embodiment, forming a second conductive layer pattern may include: depositing a second insulating film and a second conductive film sequentially on a substrate on which the aforementioned pattern is formed, patterning the second conductive film by a patterning process to form a second insulating layer covering a semiconductor layer, and a second conductive layer pattern disposed on the second insulating layer, as shown in Figures 10A and 10B, where Figure 10B is a schematic diagram of the second conductive layer in Figure 10A.

[0182] In an exemplary embodiment, the second conductive layer of each sub-pixel in the display substrate may include at least a fourth electrode plate 14 for storing capacitors, a gate electrode line 31, a second gate electrode 32, a third connection electrode 43, and a fourth connection electrode 44.

[0183] In an exemplary embodiment, the fourth electrode plate 14 may be rectangular in shape, and the corners of the rectangle may be chamfered or grooved. It may be located in the area where the third electrode plate 13 is located. The orthographic projection of the fourth electrode plate 14 on the substrate and the orthographic projection of the third electrode plate 13 on the substrate at least partially overlap. The fourth electrode plate 14 may serve as an intermediate electrode plate for the second capacitor. The fourth electrode plate 14 is configured as a first sub-capacitor that forms the second capacitor with the third electrode plate 13, and is also configured as a second sub-capacitor that forms the second capacitor with the subsequently formed fifth electrode plate.

[0184] In an exemplary embodiment, the shape of the gate electrode line 31 can be a straight line or a broken line extending along the first direction X of the main body. The orthographic projection of the gate electrode line 31 on the substrate at least partially overlaps with the orthographic projection of the first active layer 21 on the substrate. The overlapping area serves as the gate electrode of the first transistor T1. The orthographic projection of the gate electrode line 31 on the substrate at least partially overlaps with the orthographic projection of the third active layer 23 on the substrate. The overlapping area serves as the gate electrode of the third transistor T3. The gate electrode line 31 that transmits the same scanning signal can simultaneously control the conduction or disconnection of the first transistor T1 and the third transistor T3 in the sub-pixel.

[0185] In an exemplary embodiment, the second gate electrode 32 may be a strip shape extending along the second direction Y, and may be located on the side of the fourth electrode plate 14 away from the gate electrode line 31. The first end of the second gate electrode 32 is connected to the fourth electrode plate 14, and the second end of the second gate electrode 32 extends in a direction away from the gate electrode line 31. The orthographic projection of the second gate electrode 32 on the substrate at least partially overlaps with the orthographic projection of the second active layer 22 on the substrate. The second gate electrode 32 serves as the gate electrode of the second transistor T2.

[0186] In an exemplary embodiment, the orthographic projection of the second end of the second gate electrode 32 onto the substrate at least partially overlaps with the orthographic projection of the second electrode plate 12 onto the substrate.

[0187] In an exemplary embodiment, in at least one sub-pixel, the fourth electrode plate 14 and the second gate electrode 32 can be an integral structure that is interconnected.

[0188] In an exemplary embodiment, the third connecting electrode 43 may be a strip shape extending along the second direction Y, and may be located on the side of the fourth electrode plate 14 near the gate electrode line 31. The first end of the third connecting electrode 43 is connected to the fourth electrode plate 14, and the second end of the third connecting electrode 43 extends in the direction near the gate electrode line 31. The orthographic projection of the second end of the third connecting electrode 43 on the substrate at least partially overlaps with the orthographic projection of the second region of the first active layer on the substrate.

[0189] In an exemplary embodiment, in at least one sub-pixel, the fourth electrode plate 14, the second gate electrode 32, and the third connecting electrode 43 can be an integral structure that is interconnected.

[0190] In an exemplary embodiment, the fourth connecting electrode 44 may be a strip extending along the first direction X, and may span between the second active layer 22 and the first power line 71. The orthographic projection of the first end of the fourth connecting electrode 44 on the substrate at least partially overlaps with the orthographic projection of the second active layer 22 on the substrate, and the orthographic projection of the second end of the fourth connecting electrode 44 on the substrate at least partially overlaps with the orthographic projection of the first power line 71 on the substrate.

[0191] In an exemplary embodiment, the second conductive layer of each repeating unit in the display substrate may further include two first scan connection lines 33, two second scan connection lines 34, a loop connection line 35, and a scan transmission line 36.

[0192] In an exemplary embodiment, the shape of the first scanning connection line 33 can be a straight line or a broken line extending along the second direction Y of the main body. In the first direction X, the first scanning connection line 33 can be disposed at the boundary region between the display area 110 and the light-transmitting area 120 in this repeating unit. In the second direction Y, one first scanning connection line 33 can be disposed between the gate electrode line 31 of the first sub-pixel P1 and the gate electrode line 31 of the second sub-pixel P2, and connected to the ends of the gate electrode lines 31 of the two sub-pixels in the opposite direction of the first direction X, respectively. Another first scanning connection line 33 can be disposed between the gate electrode line 31 of the third sub-pixel P3 and the gate electrode line 31 of the fourth sub-pixel P4, and connected to the ends of the gate electrode lines 31 of the two sub-pixels in the opposite direction of the first direction X, respectively.

[0193] In an exemplary embodiment, the shape of the second scanning connection line 34 can be a straight line or a broken line extending along the second direction Y of the main body portion. In the first direction X, the second scanning connection line 34 can be disposed at the boundary between the display area 110 of this repeating unit and the light-transmitting area 120 of an adjacent repeating unit in the first direction X. In the second direction Y, one second scanning connection line 34 can be disposed between the gate electrode line 31 of the first sub-pixel P1 and the gate electrode line 31 of the second sub-pixel P2, and connected to the ends of the gate electrode lines 31 of the two sub-pixels in the first direction X, respectively. Another second scanning connection line 34 can be disposed between the gate electrode line 31 of the third sub-pixel P3 and the gate electrode line 31 of the fourth sub-pixel P4, and connected to the ends of the gate electrode lines 31 of the two sub-pixels in the first direction X, respectively.

[0194] In an exemplary embodiment, in the first sub-pixel P1 and the second sub-pixel P2, two gate electrode lines 31 extending along the first direction X (gate electrode lines 31 of the first sub-pixel P1 and the second sub-pixel P2) and two scan connection lines extending along the second direction Y (first scan connection line 33 and second scan connection line 34) are sequentially connected to form a first ring structure 30A. In an exemplary embodiment, the first ring structure 30A disposed in the first sub-pixel P1 and the second sub-pixel P2 can be a rectangular ring structure or a polygonal ring structure.

[0195] In an exemplary embodiment, in at least one repeating unit, the gate electrode line 31 of the first sub-pixel P1, the gate electrode line 31 of the second sub-pixel P2, the first scan connection line 33, and the second scan connection line 34 in the first annular structure 30A can be an integral structure that is interconnected.

[0196] In an exemplary embodiment, in the third sub-pixel P3 and the fourth sub-pixel P4, two gate electrode lines 31 extending along the first direction X (the gate electrode lines 31 of the third sub-pixel P3 and the fourth sub-pixel P4) and two scan connection lines extending along the second direction Y (the first scan connection line 33 and the second scan connection line 34) are sequentially connected to form a second ring structure 30B. In an exemplary embodiment, the second ring structure 30B disposed in the third sub-pixel P3 and the fourth sub-pixel P4 can be a rectangular ring structure or a polygonal ring structure.

[0197] In an exemplary embodiment, in at least one repeating unit, the gate electrode line 31 of the third sub-pixel P3, the gate electrode line 31 of the fourth sub-pixel P4, the first scan connection line 33, and the second scan connection line 34 in the second ring structure 30B can be an integral structure that is interconnected.

[0198] In an exemplary embodiment, the ring connecting line 35 can be a straight line or a broken line extending along the second direction Y of the main body. In the first direction X, the ring connecting line 35 can be disposed at the boundary between the display area 110 of this repeating unit and the light-transmitting area 120 of an adjacent repeating unit in the first direction X. In the second direction Y, the ring connecting line 35 can be disposed between the first ring structure 30A and the second ring structure 30B, and connected to both ring structures respectively, thus connecting the first ring structure 30A and the second ring structure 30B.

[0199] In an exemplary embodiment, in at least one repeating unit, the first ring structure 30A, the second ring structure 30B, and the ring connecting line 35 can be an integral structure that is interconnected.

[0200] In an exemplary embodiment, the shape of the scanning transmission line 36 can be a straight line or a broken line extending along the first direction X of the main body, and it can be disposed in the light-transmitting area 120. The first end of the scanning transmission line 36 is connected to the second ring structure 30B in the repeating unit, and the second end of the scanning transmission line 36 is connected to the second ring structure 30B in the repeating unit adjacent to the first direction X.

[0201] In an exemplary embodiment, in two adjacent repeating units in the first direction X, the scanning transmission lines 36 in the light-transmitting areas 120 of the two repeating units can be staggered, that is, the scanning transmission lines 36 in the light-transmitting areas 120 of the two repeating units are not on the same straight line extending along the first direction X, which can effectively weaken the diffraction effect, avoid the blurring of objects behind the screen, and improve the transparent display effect.

[0202] In an exemplary embodiment, in at least one repeating unit, the first ring structure 30A, the second ring structure 30B, the scan transmission line 36, and the ring connection line 35 can be an integral structure that is interconnected.

[0203] In an exemplary embodiment, the display area 110 is provided with two interconnected annular structures, and the light-transmitting area 120 is provided with only one signal line. The two annular structures of the display area 110 and the single signal line of the light-transmitting area 120 constitute a continuous scanning signal line.

[0204] In an exemplary embodiment, the scan signal line transmitting the same scan signal can simultaneously control the on or off of all first transistors T1 and all third transistors T3 in the four sub-pixels of the repeating unit.

[0205] In an exemplary embodiment, for a plurality of repeating units arranged sequentially in the first direction X, the scanning signal lines in the plurality of repeating units can be an integral structure that is interconnected.

[0206] In an exemplary embodiment, in at least one repeating unit, the orthographic projections of the first region of the first active layer, the first region of the third active layer, the first connecting electrode 41, and the second connecting electrode 42 in the first sub-pixel P1 and the second sub-pixel P2 onto the substrate can be located within the range of the orthographic projections of the region enclosed by the first annular structure onto the substrate. Similarly, the orthographic projections of the first region of the first active layer, the first region of the third active layer, the first connecting electrode 41, and the second connecting electrode 42 in the third sub-pixel P3 and the fourth sub-pixel P4 onto the substrate can be located within the range of the orthographic projections of the region enclosed by the second annular structure onto the substrate.

[0207] In an exemplary embodiment, in at least one repeating unit, the orthographic projections of the third data connection block 63-1 and the fourth data connection block 64-1 on the substrate may be located within the range of the orthographic projections of the area enclosed by the first annular structure on the substrate, and the orthographic projections of the first data connection block 61-1 and the second data connection block 62-1 on the substrate may be located within the range of the orthographic projections of the area enclosed by the second annular structure on the substrate.

[0208] In an exemplary embodiment, in at least one repeating unit, all longitudinal signal lines are located between the first scan connection line 33 and the second scan connection line 34. The orthographic projections of the first ring structure 30A and the second ring structure 30B on the substrate at least partially overlap with the orthographic projections of the first data signal line 61, the second data signal line 62, the third data signal line 63, the fourth data signal line 64 and the first power line 71 on the substrate, that is, all longitudinal signal lines are located within the first ring structure 30A and the second ring structure 30B.

[0209] In an exemplary embodiment, in at least one repeating unit, a first protruding structure 37 may be provided at the position where the first annular structure 30A and the ring connecting line 35 are connected. The first protruding structure 37 protrudes toward the light-transmitting area 120 of the adjacent repeating unit in the first direction X, and the orthographic projection of the first protruding structure 37 on the substrate at least partially overlaps with the orthographic projection of the light-transmitting area 120 on the substrate. In at least one repeating unit, a second protruding structure 38 may be provided at the position where the second annular structure 30B and the ring connecting line 35 are connected. The second protruding structure 38 protrudes toward the light-transmitting area 120 of the adjacent repeating unit in the first direction X, and the orthographic projection of the second protruding structure 38 on the substrate at least partially overlaps with the orthographic projection of the light-transmitting area 120 on the substrate. The first protruding structure 37 and the second protruding structure 38 can change the light-transmitting area into an irregular shape. When light passes through the irregularly shaped light-transmitting area, the diffraction fringes are generated in different positions and directions. Therefore, the light will not spread in one direction but in multiple directions, which greatly weakens the diffraction effect, avoids the blurring of objects behind the screen, and improves the transparent display effect.

[0210] In an exemplary embodiment, the end of the second scanning connection line 34 near the ring connection line 35 in the first ring structure can be configured as a first fold line 37-1 protruding in a direction away from the first scanning connection line 33, and the end of the ring connection line 35 near the first ring structure can be configured as a second fold line 37-2 protruding in a direction away from the first scanning connection line 33. The first fold line 37-1 and the second fold line 37-2 form a first protruding structure 37.

[0211] In an exemplary embodiment, the first fold line 37-1 may include at least a first sub-line and a second sub-line. The first end of the first sub-line is connected to the second scan connection line 34. The second end of the first sub-line extends along the first direction X and is connected to the first end of the second sub-line. The second end of the second sub-line extends along the second direction Y and is connected to the gate electrode line 31 in the second sub-pixel P2.

[0212] In an exemplary embodiment, the edge of the first sub-line near the gate electrode line 31 has a first protrusion width D1 between the edge of the gate electrode line 31 near the first sub-line.

[0213] In an exemplary embodiment, the second fold line 37-2 may include a third sub-line and a fourth sub-line. The first end of the third sub-line is connected to the loop connection line 35. The second end of the third sub-line extends along the first direction X and is connected to the first end of the fourth sub-line. The second end of the fourth sub-line extends along the opposite direction of the second direction Y and is connected to the gate electrode line 31 in the second sub-pixel P2.

[0214] In an exemplary embodiment, the edge of the third sub-line near the gate electrode line 31 has a second protrusion width D2 between the edge of the gate electrode line 31 near the third sub-line.

[0215] In an exemplary embodiment, the first protrusion width D1 and the second protrusion width D2 can be different, which helps to weaken the diffraction effect and improve the transparent display effect.

[0216] In an exemplary embodiment, the end of the second scanning connection line 34 near the ring connection line 35 in the second ring structure can be configured as a third fold line 38-3 protruding in a direction away from the first scanning connection line 33, and the end of the ring connection line 35 near the second ring structure can be configured as a fourth fold line 38-4 protruding in a direction away from the first scanning connection line 33. The third fold line 38-3 and the fourth fold line 38-4 form the second protruding structure 38.

[0217] In an exemplary embodiment, the third fold line 38-3 may include at least a fifth sub-line and a sixth sub-line. The first end of the fifth sub-line is connected to the loop connection line 35. The second end of the fifth sub-line extends along the first direction X and is connected to the first end of the sixth sub-line. The second end of the sixth sub-line extends along the second direction Y and is connected to the gate electrode line 31 in the third sub-pixel P3.

[0218] In an exemplary embodiment, the edge of the fifth sub-line near the gate electrode line 31 has a third protrusion width D3 between the edge of the gate electrode line 31 near the fifth sub-line.

[0219] In an exemplary embodiment, the fourth fold line 38-4 may include a seventh sub-line and an eighth sub-line. The first end of the seventh sub-line is connected to the second scan connection line 34. The second end of the seventh sub-line extends along the first direction X and is connected to the first end of the eighth sub-line. The second end of the eighth sub-line extends along the opposite direction of the second direction Y and is connected to the gate electrode line 31 in the third sub-pixel P3.

[0220] In an exemplary embodiment, the edge of the seventh sub-line near the gate electrode line 31 has a fourth protrusion width D4 between the edge of the gate electrode line 31 near the seventh sub-line.

[0221] In an exemplary embodiment, the third protrusion width D3 and the fourth protrusion width D4 can be different, which helps to weaken the diffraction effect and improve the transparent display effect.

[0222] In an exemplary embodiment, the shapes of the first protrusion 37 and the second protrusion 38 in a plane parallel to the base may include any one or more of the following: circle, ellipse, rectangle, trapezoid, pentagon, and hexagon, without limitation herein.

[0223] In an exemplary embodiment, in at least one repeating unit, the shapes of the first protrusion structure 37 and the second protrusion structure 38 may be substantially the same, but their protrusion lengths may be different, and the protrusion length may be the dimension in the first direction X.

[0224] In an exemplary embodiment, the first protruding structure 37 may have a first protruding length L1, and the second protruding structure 38 may have a second protruding length L2. The first protruding length L1 may be greater than the second protruding length L2, which is beneficial to weaken the diffraction effect and improve the transparent display effect.

[0225] In exemplary embodiments, because the scan signal lines overlap with multiple signal lines, various defects are prone to occur during the manufacturing process of the display substrate, such as short circuits in the overlapping areas. This disclosure, by setting two interconnected ring structures, not only ensures that the scan signal lines drive all pixel driving circuits in the overlapping area, but also allows for the repair of defects at all locations, achieving full-signal defect repair, avoiding product scrapping, and effectively improving product yield.

[0226] Figure 10C is a schematic diagram of short-circuit repair of a display substrate according to this disclosure. As shown in Figure 10C, when a short circuit 200 occurs between the gate electrode line 31 of the first sub-pixel P1 and the third data signal line 63, the gate electrode lines 31 on both sides of the short circuit 200 can be cut off by laser cutting, forming two cut-off points 210 on both sides of the short circuit 200, thus isolating the short circuit 200. Since the gate electrode lines 31 of the first sub-pixel P1 and the second sub-pixel P2 are dual-line structures with dual-channel functions, the cut-off points can ensure isolation of the short circuit points, regardless of whether a short circuit occurs on the gate electrode line 31 of the first sub-pixel P1 or the gate electrode line 31 of the second sub-pixel P2, and will not affect the normal operation of the pixel driving circuits in the first sub-pixel P1 and the second sub-pixel P2.

[0227] In the exemplary embodiment, since the gate electrode lines 31 of the third sub-pixel P3 and the fourth sub-pixel P4 are dual-line structures with dual-channel functions, the cut-off point can ensure that the short circuit point is isolated regardless of whether a short circuit point appears on the gate electrode line 31 of the third sub-pixel P3 or the gate electrode line 31 of the fourth sub-pixel P4, and will not affect the normal operation of the pixel driving circuit in the third sub-pixel P3 and the fourth sub-pixel P4.

[0228] In an exemplary embodiment, repairs can be performed at four locations: two first scan connection lines 33 and two second scan connection lines 34, depending on the actual defect situation. This achieves full signal defect repair, avoids product scrapping, and effectively improves product yield.

[0229] In an exemplary embodiment, this process can simultaneously pattern the second conductive film and the second insulating film, such that the pattern of the second insulating layer is the same as the pattern of the second conductive layer.

[0230] In an exemplary embodiment, after the second conductive layer pattern is formed, the second conductive layer can be used as a shield to conduct the semiconductor layer. The semiconductor layer in the region shielded by the second conductive layer forms the channel region of the first transistor T1 to the third transistor T3, and the semiconductor layer in the region not shielded by the first conductive layer is conducted.

[0231] (15) Forming a third insulating layer pattern. In an exemplary embodiment, forming a third insulating layer pattern may include: depositing a third insulating film on a substrate on which the aforementioned pattern is formed, and patterning the third insulating film by a patterning process to form a third insulating layer pattern covering the second conductive layer, wherein a plurality of vias are provided on the third insulating layer, as shown in FIG11.

[0232] In an exemplary embodiment, the plurality of vias for each sub-pixel in the display substrate includes at least: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, and a ninth via V9.

[0233] In an exemplary embodiment, the orthographic projection of the first via V1 onto the substrate at least partially overlaps with the orthographic projections of the first region of the first active layer and the first connecting electrode 41 onto the substrate. The third insulating layer, the second insulating layer, and the first insulating layer within the first via V1 are etched away, simultaneously exposing the surface of the first region of the first active layer and the surface of the first connecting electrode 41. The first via V1 is a transition via, consisting of two half-holes; one half-hole exposes the surface of the first region of the first active layer, and the other half-hole exposes the surface of the first connecting electrode 41. In an exemplary embodiment, the first via V1 is configured to allow a subsequently formed connecting electrode to simultaneously connect to the first region of the first active layer and the first connecting electrode 41 through this via.

[0234] In an exemplary embodiment, the orthographic projection of the first via V1 in the first sub-pixel P1 and the second sub-pixel P2 onto the substrate can be located within the range of the orthographic projection of the area enclosed by the first annular structure onto the substrate, and the orthographic projection of the first via V1 in the third sub-pixel P3 and the fourth sub-pixel P4 onto the substrate can be located within the range of the orthographic projection of the area enclosed by the second annular structure onto the substrate.

[0235] In an exemplary embodiment, the orthographic projection of the second via V2 onto the substrate at least partially overlaps with the orthographic projections of the second region of the first active layer and the third connecting electrode 43 onto the substrate. The third and second insulating layers within the second via V2 are etched away, simultaneously exposing the surfaces of the second region of the first active layer and the third connecting electrode 43. The second via V2 is a transition via consisting of two half-holes, one half-hole exposing the surface of the second region of the first active layer, and the other half-hole exposing the surface of the third connecting electrode 43. In an exemplary embodiment, the second via V2 is configured to allow a subsequently formed fifth connecting electrode to simultaneously connect to the second region of the first active layer and the third connecting electrode 43 through this via.

[0236] In an exemplary embodiment, the orthographic projection of the third via V3 onto the substrate at least partially overlaps with the orthographic projections of the first region of the second active layer and the fourth connecting electrode 44 onto the substrate. The third and second insulating layers within the third via V3 are etched away, simultaneously exposing the surfaces of the first region of the second active layer and the fourth connecting electrode 44. The third via V3 is a transition via, consisting of two half-holes; one half-hole exposes the surface of the first region of the second active layer, and the other half-hole exposes the surface of the fourth connecting electrode 44. In an exemplary embodiment, the third via V3 is configured to allow a subsequently formed seventh connecting electrode to simultaneously connect to both the first region of the second active layer and the fourth connecting electrode 44 through this via. In an exemplary embodiment, there can be multiple third vias V3, which can be sequentially arranged along the second direction Y to increase connection reliability.

[0237] In an exemplary embodiment, the orthographic projection of the fourth via V4 onto the substrate at least partially overlaps with the orthographic projections of the second region of the second active layer and the third electrode plate 13 onto the substrate. The third insulating layer, the second insulating layer, and the first insulating layer within the fourth via V4 are etched away, simultaneously exposing the surface of the second region of the second active layer and the surface of the third electrode plate 13. The fourth via V4 is a transition via, consisting of two half-holes; one half-hole exposes the surface of the second region of the second active layer, and the other half-hole exposes the surface of the third electrode plate 13. In an exemplary embodiment, the fourth via V4 is configured to allow a subsequently formed fifth electrode plate to connect simultaneously to the second region of the second active layer and the third electrode plate 13 through this via. In an exemplary embodiment, there can be multiple fourth vias V4, which can be sequentially arranged along the second direction Y to increase connection reliability.

[0238] In an exemplary embodiment, the orthographic projection of the fifth via V5 onto the substrate at least partially overlaps with the orthographic projections of the first region of the third active layer and the second connecting electrode 42 onto the substrate. The third, second, and first insulating layers within the fifth via V5 are etched away, simultaneously exposing the surface of the first region of the third active layer and the surface of the second connecting electrode 42. The fifth via V5 is a transition via consisting of two half-holes, one half-hole exposing the surface of the first region of the third active layer, and the other half-hole exposing the surface of the second connecting electrode 42. In an exemplary embodiment, the fifth via V5 is configured to connect to both the first region of the third active layer and the second connecting electrode 42 simultaneously through this via, along with a subsequently formed ninth connecting electrode.

[0239] In an exemplary embodiment, the orthographic projection of the fifth via V5 in the first sub-pixel P1 and the second sub-pixel P2 onto the substrate can be located within the range of the orthographic projection of the area enclosed by the first annular structure onto the substrate, and the orthographic projection of the fifth via V5 in the third sub-pixel P3 and the fourth sub-pixel P4 onto the substrate can be located within the range of the orthographic projection of the area enclosed by the second annular structure onto the substrate.

[0240] In an exemplary embodiment, the orthographic projection of the sixth via V6 onto the substrate at least partially overlaps with the orthographic projections of the second region of the third active layer and the third electrode plate 13 onto the substrate. The third insulating layer, the second insulating layer, and the first insulating layer within the sixth via V6 are etched away, simultaneously exposing the surface of the second region of the third active layer and the surface of the third electrode plate 13. The sixth via V6 is a transition via consisting of two half-holes; one half-hole exposes the surface of the second region of the third active layer, and the other half-hole exposes the surface of the third electrode plate 13. In an exemplary embodiment, the sixth via V6 is configured to allow a subsequently formed fifth electrode plate to connect simultaneously to the second region of the third active layer and the third electrode plate 13 through this via.

[0241] In an exemplary embodiment, the orthographic projection of the seventh via V7 onto the substrate at least partially overlaps with the orthographic projections of the second electrode 12 and the second gate electrode 32 onto the substrate. The third and second insulating layers within the seventh via V7 are etched away, simultaneously exposing the surfaces of the second electrode 12 and the second gate electrode 32. The seventh via V7 is a transition via consisting of two half-holes, one exposing the surface of the second electrode 12 and the other exposing the surface of the second gate electrode 32. In an exemplary embodiment, the seventh via V7 is configured to allow a subsequently formed eighth connection electrode to be connected to both the second electrode 12 and the second gate electrode 32 simultaneously through this via.

[0242] In an exemplary embodiment, the orthographic projection of the eighth via V8 on the substrate is within the range of the orthographic projection of the first power line 71 on the substrate. The third insulating layer, the second insulating layer, and the first insulating layer within the eighth via V8 are etched away, exposing the surface of the first power line 71. The eighth via V8 is configured to allow the subsequently formed sixth connection electrode to be connected to the first power line 71 through the via.

[0243] In an exemplary embodiment, the orthographic projection of the ninth via V9 on the substrate is within the range of the orthographic projection of the fourth connection electrode 44 on the substrate. The third and second insulating layers within the ninth via V9 are etched away, exposing the surface of the fourth connection electrode 44. The ninth via V9 is configured to allow the subsequently formed sixth connection electrode to be connected to the fourth connection electrode 44 through the via.

[0244] In an exemplary embodiment, at least one repeating unit may further include a tenth via V10 disposed in the first sub-pixel P1, an eleventh via V11 disposed in the second sub-pixel P2, and a twelfth via V12 disposed in the third sub-pixel P3.

[0245] In an exemplary embodiment, the orthographic projection of the tenth via V10 on the substrate is within the range of the orthographic projection of the fourth data connection block 64-1 on the substrate. The third insulating layer, the second insulating layer, and the first insulating layer within the tenth via V10 are etched away, exposing the surface of the fourth data connection block 64-1. The tenth via V10 is configured to allow the subsequently formed eleventh connection electrode to be connected to the fourth data connection block 64-1 through the via.

[0246] In an exemplary embodiment, the orthographic projection of the eleventh via V11 onto the substrate is within the range of the orthographic projection of the third data connection block 63-1 onto the substrate. The third insulating layer, the second insulating layer, and the first insulating layer within the eleventh via V11 are etched away, exposing the surface of the third data connection block 63-1. The eleventh via V11 is configured to allow the subsequently formed twelfth connection electrode to be connected to the third data connection block 63-1 through the via.

[0247] In an exemplary embodiment, the orthographic projection of the twelfth via V12 on the substrate is within the range of the orthographic projection of the second data connection block 62-1 on the substrate. The third insulating layer, the second insulating layer, and the first insulating layer within the twelfth via V12 are etched away, exposing the surface of the second data connection block 62-1. The twelfth via V12 is configured to allow the subsequently formed thirteenth connection electrode to be connected to the second data connection block 62-1 through the via.

[0248] In an exemplary embodiment, the patterning process may employ a half-tone mask process.

[0249] (16) Forming a third conductive layer pattern. In an exemplary embodiment, forming a third conductive layer pattern may include: depositing a third conductive film on a substrate on which the aforementioned pattern is formed, patterning the third conductive film by a patterning process, and forming a third conductive layer pattern on a third insulating layer, as shown in Figures 12A and 12B, where Figure 12B is a schematic diagram of the third conductive layer in Figure 12A.

[0250] In an exemplary embodiment, the third conductive layer of each sub-pixel in the display substrate may include at least a fifth electrode 15 for storing capacitors, a fifth connecting electrode 45, a sixth connecting electrode 46, a seventh connecting electrode 47, an eighth connecting electrode 48, a ninth connecting electrode 49, a second power line 72, a compensation signal line 73, and an electrode connecting electrode 81.

[0251] In an exemplary embodiment, the shape of the second power line 72 may be a straight line or a broken line extending along the second direction Y of the main body portion, and may be located on the side of the first power line 71 away from the fourth data signal line 64. The second power line 72 is configured to provide a second power signal to the light-emitting device of each sub-pixel.

[0252] In an exemplary embodiment, considering the voltage drop (IR Drop) problem in large-size transparent displays, this disclosure embodiment specifically provides a second power line for transmitting a low-voltage signal in each repeating unit. The second power line is connected to the cathode of the subsequently formed light-emitting device, which can effectively reduce the voltage drop of the second power signal, effectively solve the voltage drop problem in large-size transparent displays, and ensure display uniformity.

[0253] In an exemplary embodiment, the shape of the compensation signal line 73 may be a straight line or a broken line extending along the second direction Y of the main body portion, and may be located between the fourth data signal line 64 and the first power supply line 71. The compensation signal line 73 is configured to provide a compensation signal to the pixel driving circuit of each sub-pixel.

[0254] In an exemplary embodiment, in at least one repeating unit, the orthographic projections of the second power line 72 and the compensation signal line 73 on the substrate at least partially overlap with the orthographic projections of the first ring structure and the second ring structure on the substrate.

[0255] In an exemplary embodiment, in at least one repeating unit, there may be a second spacing S2 between the fourth data signal line 64 and the compensation signal line 73. The second spacing S2 may be the minimum spacing between the edge of the fourth data signal line 64 near the compensation signal line 73 and the edge of the compensation signal line 73 near the fourth data signal line 64, which is the dimension of the first direction X.

[0256] In an exemplary embodiment, the second spacing S2 may be smaller than the first spacing S1.

[0257] In an exemplary embodiment, in at least one repeating unit, there may be a third spacing S3 between the first power line 71 and the compensation signal line 73. The third spacing S3 may be the minimum spacing between the edge of the first power line 71 near the compensation signal line 73 and the compensation signal line 73 near the first power line 71, and is the dimension in the first direction X.

[0258] In an exemplary embodiment, the third spacing S3 may be smaller than the first spacing S1.

[0259] In an exemplary embodiment, in at least one repeating unit, there may be a fourth spacing S4 between the first power line 71 and the second power line 72. The fourth spacing S4 may be the minimum spacing between the edge of the first power line 71 near the second power line 72 and the edge of the second power line 72 near the first power line 71, and is the dimension in the first direction X.

[0260] In an exemplary embodiment, the fourth spacing S4 may be smaller than the first spacing S1.

[0261] In an exemplary embodiment, a first power line 71 and first data signal lines 61 to fourth data signal lines 64 are disposed in a first conductive layer, and a second power line 72 and a compensation signal line 73 are disposed in a third conductive layer. The compensation signal line 73 is disposed between the first power line 71 and the fourth data signal line 64, and the first power line 71 is disposed between the compensation signal line 73 and the second power line 72. Since the spacing between signal lines in different conductive layers can be smaller than the spacing between signal lines in the same conductive layer (i.e., the second, third, and fourth spacings can all be smaller than the first spacing), the spacing between the fourth data signal line 64 and the compensation signal line 73, the spacing between the first power line 71 and the compensation signal line 73, and the spacing between the first power line 71 and the second power line 72 can be effectively reduced, thereby reducing the area occupied by the display area and increasing the area of ​​the light-transmitting area.

[0262] In an exemplary embodiment, the fifth electrode plate 15 may be rectangular in shape, and the corners of the rectangle may be chamfered or grooved. It may be located in the area where the third electrode plate 13 is located. The orthographic projection of the fifth electrode plate 15 on the substrate and the orthographic projection of the fourth electrode plate 14 on the substrate at least partially overlap. The fifth electrode plate 15 may serve as the upper electrode plate of the second capacitor. The fifth electrode plate 15 is configured to form a second sub-capacitor with the fourth electrode plate 14 to form the second capacitor.

[0263] In an exemplary embodiment, the fifth electrode plate 15 is connected to the second region of the second active layer and the third electrode plate 13 simultaneously through the fourth via V4, and to the second region of the third active layer and the third electrode plate 13 simultaneously through the sixth via V6. This not only realizes the interconnection between the second electrode of the second transistor T2, the second electrode of the third transistor T3, the third electrode plate 13 and the fifth electrode plate 15 to form the second node N2 of the pixel driving circuit, but also ensures that the third electrode plate 13 and the fifth electrode plate 15 of the second capacitor have the same potential of the second node N2.

[0264] In an exemplary embodiment, the electrode plate connecting electrode 81 is T-shaped and protrudes towards the light-transmitting area 120 of the repeating unit. The orthographic projection of the electrode plate connecting electrode 81 on the substrate at least partially overlaps with the orthographic projection of the light-transmitting area 120 on the substrate. The electrode plate connecting electrode 81 may include an electrode plate connecting strip 81-1 and an electrode plate connecting block 81-2. The electrode plate connecting strip 81-1 may be a strip shape extending along a first direction X. The first end of the electrode plate connecting strip 81-1 is connected to the fifth electrode plate 15, and the second end of the electrode plate connecting strip 81-1 extends away from the fifth electrode plate 15 to the adjacent light-transmitting area 120 and then connects to the electrode plate connecting block 81-2. The electrode plate connecting block 81-2 may be block-shaped (e.g., rectangular) and is disposed in the light-transmitting area 120. The electrode plate connecting block 81-2 is configured to connect to the subsequently formed anode connecting electrode.

[0265] In an exemplary embodiment, in at least one sub-pixel, the electrode connecting strip 81-1 and the electrode connecting block 81-2 can be an integral structure that is interconnected.

[0266] In an exemplary embodiment, in at least one sub-pixel, the fifth electrode plate 15 and the electrode plate connecting electrode 81 can be an integral structure that is interconnected.

[0267] In an exemplary embodiment, the fifth connecting electrode 45 can be block-shaped (e.g., rectangular). The fifth connecting electrode 45 is connected to both the second region of the first active layer and the third connecting electrode 43 via the second via V2. Since the third connecting electrode 43 is connected to the fourth electrode plate 14, and the fourth electrode plate 14 is connected to the second gate electrode 32, the fifth connecting electrode 45 achieves interconnection between the second electrode of the first transistor T1, the gate electrode of the second transistor T2, and the fourth electrode plate 14 in each sub-pixel, forming the first node N1 of the pixel driving circuit.

[0268] In an exemplary embodiment, the sixth connecting electrode 46 may be block-shaped (e.g., rectangular). The sixth connecting electrode 46 is connected to the first power line 71 through the eighth via V8 on one hand, and to the fourth connecting electrode 44 through the ninth via V9 on the other hand.

[0269] In an exemplary embodiment, the seventh connection electrode 47 can be block-shaped (e.g., rectangular), and it is connected to both the first region of the second active layer and the fourth connection electrode 44 via the third via V3. Since the fourth connection electrode 44 is connected to the first power line 71, the first power line 71 writes the first power signal into the first electrode of the second transistor T2.

[0270] In an exemplary embodiment, since the first electrode of the second transistor T2 in each sub-pixel is connected to the first power line 71 through the fourth connection electrode 44, the sixth connection electrode 46, and the seventh connection electrode 47, the four pixel driving circuits in a display area 110 can share a single first power line 71, i.e., the first power line 71 in a repeating unit is a one-to-four structure. By designing the first power line 71 as a one-to-four structure, the display substrate of this disclosure saves the number of signal lines, reduces the space occupied, has a simple structure, a reasonable layout, makes full use of the layout space, improves space utilization, and is beneficial for improving resolution and transparency.

[0271] In an exemplary embodiment, the eighth connecting electrode 48 can be block-shaped (e.g., rectangular), and is connected to both the second electrode plate 12 and the second gate electrode 32 via the seventh via V7. Since the second gate electrode 32 is connected to the fourth electrode plate 14, the eighth connecting electrode 48 enables the second electrode plate 12 of the first capacitor and the fourth electrode plate 14 of the second capacitor to have the same potential at the first node N1.

[0272] In an exemplary embodiment, the ninth connecting electrode 49 may be block-shaped (e.g., rectangular), and the ninth connecting electrode 49 is connected to the first region of the third active layer and the second connecting electrode 42 simultaneously through the fifth via V5.

[0273] In an exemplary embodiment, the ninth connecting electrode 49 in the first sub-pixel P1 and the second sub-pixel P2 can be an integral structure that is interconnected with each other, and the ninth connecting electrode 49 in the third sub-pixel P3 and the fourth sub-pixel P4 can be an integral structure that is interconnected with each other.

[0274] In an exemplary embodiment, the third conductive layer of each repeating unit in the display substrate may further include an eleventh connecting electrode 51, a twelfth connecting electrode 52, a thirteenth connecting electrode 53, and a fourteenth connecting electrode 54.

[0275] In an exemplary embodiment, the eleventh connection electrode 51 can be a strip extending along the first direction X, and can be disposed in the first sub-pixel P1. The first end of the eleventh connection electrode 51 is connected to both the first region of the first active layer and the first connection electrode 41 in the first sub-pixel P1 through the first via V1, and the second end of the eleventh connection electrode 51 is connected to the fourth data connection block 64-1 through the tenth via V10. Since the fourth data connection block 64-1 is connected to the fourth data signal line 64, the fourth data signal line 64 writes the fourth data signal into the first electrode of the first transistor T1 in the first sub-pixel P1.

[0276] In an exemplary embodiment, the twelfth connecting electrode 52 can be a strip extending along the first direction X, and can be disposed in the second sub-pixel P2. The first end of the twelfth connecting electrode 52 is connected to both the first region of the first active layer and the first connecting electrode 41 in the second sub-pixel P2 through the first via V1, and the second end of the twelfth connecting electrode 52 is connected to the third data connecting block 63-1 through the eleventh via V11. Since the third data connecting block 63-1 is connected to the third data signal line 63, the third data signal line 63 writes the third data signal into the first electrode of the first transistor T1 in the second sub-pixel P2.

[0277] In an exemplary embodiment, the thirteenth connecting electrode 53 can be a strip extending along the first direction X, and can be disposed in the third sub-pixel P3. The first end of the thirteenth connecting electrode 53 is connected to both the first region of the first active layer and the first connecting electrode 41 in the third sub-pixel P3 through the first via V1, and the second end of the thirteenth connecting electrode 53 is connected to the second data connecting block 62-1 through the twelfth via V12. Since the second data connecting block 62-1 is connected to the second data signal line 62, the second data signal line 62 writes the second data signal into the first electrode of the first transistor T1 in the third sub-pixel P3.

[0278] In an exemplary embodiment, the fourteenth connection electrode 54 can be block-shaped (e.g., rectangular) and can be disposed in the fourth sub-pixel P4. The fourteenth connection electrode 54 is connected to both the first region of the first active layer and the first connection electrode 41 in the fourth sub-pixel P4 through the first via V1. Since the first connection electrode 41 in the fourth sub-pixel P4 is connected to the first data signal line 61 through the first data connection block, the first data signal line 61 writes the first data signal into the first electrode of the first transistor T1 in the fourth sub-pixel P4.

[0279] In an exemplary embodiment, the third conductive layer of each repeating unit in the display substrate may further include a fifteenth connecting electrode 55 and a sixteenth connecting electrode 56.

[0280] In an exemplary embodiment, the fifteenth connecting electrode 55 can be a strip extending along the first direction X, and can be disposed in the region between the first sub-pixel P1 and the second sub-pixel P2. The first end of the fifteenth connecting electrode 55 is connected to the compensation signal line 73, and the second end of the fifteenth connecting electrode 55 is connected to the ninth connecting electrode 49 in the first sub-pixel P1 and the ninth connecting electrode 49 in the second sub-pixel P2, respectively. Since the ninth connecting electrode 49 is simultaneously connected to the first region of the third active layer and the second connecting electrode 42, the compensation signal line 73 is able to write the compensation signal into the first electrode of the third transistor T3 in the first sub-pixel P1 and the first electrode of the third transistor T3 in the second sub-pixel P2.

[0281] In an exemplary embodiment, since the third transistors T3 in the first sub-pixel P1 and the second sub-pixel P2 are adjacent to each other, the third transistors T3 of the two sub-pixels can share the same fifteenth connection electrode 55 as a lateral compensation connection line, which can reduce the number of lateral compensation connection lines, save layout space, and improve yield.

[0282] In an exemplary embodiment, in at least one repeating unit, the ninth connecting electrode 49, the fifteenth connecting electrode 55, and the compensation signal line 73, which are integral structures in the first sub-pixel P1 and the second sub-pixel P2, can be integral structures that are interconnected.

[0283] In an exemplary embodiment, the sixteenth connecting electrode 56 can be a strip extending along the first direction X, and can be disposed in the region between the third sub-pixel P3 and the fourth sub-pixel P4. The first end of the sixteenth connecting electrode 56 is connected to the compensation signal line 73, and the second end of the sixteenth connecting electrode 56 is connected to the ninth connecting electrode 49 in the third sub-pixel P3 and the ninth connecting electrode 49 in the fourth sub-pixel P4, respectively. Since the ninth connecting electrode 49 is simultaneously connected to the first region and the second connecting electrode 42 of the third active layer, the compensation signal line 73 is able to write the compensation signal into the first electrode of the third transistor T3 in the third sub-pixel P3 and the first electrode of the third transistor T3 in the fourth sub-pixel P4.

[0284] In an exemplary embodiment, since the third transistors T3 in the third sub-pixel P3 and the fourth sub-pixel P4 are adjacent to each other, the third transistors T3 of the two sub-pixels can share the same sixteenth connection electrode 56 as a lateral compensation connection line, which can reduce the number of lateral compensation connection lines, save layout space, and improve yield.

[0285] In an exemplary embodiment, in at least one repeating unit, the ninth connecting electrode 49, the fifteenth connecting electrode 55, and the compensation signal line 73, which are integral structures in the third sub-pixel P3 and the fourth sub-pixel P4, can be integral structures that are interconnected.

[0286] In an exemplary embodiment, the fifteenth connecting electrode 55, the sixteenth connecting electrode 56, and the compensation signal line 73 can be an integral structure that is interconnected. Compared with the structure in which the lateral compensation connecting line and the compensation signal line are connected by vias, the embodiments of this disclosure reduce the number of vias, reduce the space occupied, simplify the connection structure, and help improve resolution and transparency.

[0287] In an exemplary embodiment, the orthographic projections of the fifteenth connecting electrode 55 and the sixteenth connecting electrode 56 on the substrate at least partially overlap with the orthographic projections of the first data signal lines 61 to the fourth data signal lines 64 on the substrate. Since the first data signal lines 61 to the fourth data signal lines 64 are disposed in the first conductive layer, and the fifteenth connecting electrode 55 and the sixteenth connecting electrode 56 are disposed in the third conductive layer, with a first insulating layer, a second insulating layer, and a third insulating layer spaced between the first conductive layer and the third conductive layer, the occurrence of cross-line defects can be effectively reduced.

[0288] In an exemplary embodiment, since both the fifteenth connecting electrode 55 and the sixteenth connecting electrode 56 are connected to the compensation signal line 73, the compensation signal line 73 can provide compensation signals to the pixel driving circuit in each sub-pixel through the fifteenth connecting electrode 55 and the sixteenth connecting electrode 56. Therefore, the four pixel driving circuits in a display area 110 can share a single compensation connection line 73, i.e., the compensation connection line in a repeating unit is a one-to-four structure. By designing the compensation signal line as a one-to-four structure, the display substrate of this disclosure saves the number of signal lines, reduces the space occupied, has a simple structure, a reasonable layout, makes full use of the layout space, improves space utilization, and is conducive to improving resolution and transparency.

[0289] In an exemplary embodiment, since the fourth data signal line 64 and the first power line 71 are disposed in one conductive layer, and the second power line 72 and the compensation signal line 73 are disposed in another conductive layer, the structure in which the compensation signal line 73 is disposed between the fourth data signal line 64 and the first power line 71, and the structure in which the first power line 71 is disposed between the compensation signal line 73 and the second power line 72, can effectively reduce the spacing between the fourth data signal line 64 and the compensation signal line 73, reduce the spacing between the first power line 71 and the compensation signal line 73, reduce the spacing between the first power line 71 and the second power line 72, reduce the area occupied by multiple signal lines, reduce the area of ​​the display area, and increase the area of ​​the light-transmitting area.

[0290] In an exemplary embodiment, in at least one repeating unit, the ninth connecting electrode 49, an integral structure in the first sub-pixel P1 and the second sub-pixel P2, and the ninth connecting electrode 49, an integral structure in the third sub-pixel P3 and the fourth sub-pixel P4, can be substantially symmetrically arranged with respect to the sub-pixel center line between the second sub-pixel P2 and the third sub-pixel P3. Similarly, the fifteenth connecting electrode 55 and the sixteenth connecting electrode 56 can be substantially symmetrically arranged with respect to the sub-pixel center line between the second sub-pixel P2 and the third sub-pixel P3. This disclosure, through the symmetrical structure of the third transistor T3 connected to the compensation connecting line, ensures that the RC delay of the compensation signal written to the third transistor T3 is substantially the same, guaranteeing display uniformity.

[0291] In an exemplary embodiment, since the first electrode 11 is connected to the third electrode 13, the first electrode 11 has a potential at the second node N2. Since the second electrode 12 and the fourth electrode 14 are connected via the eighth connecting electrode 48, the second electrode 12 has a potential at the first node N1. Thus, the first electrode 11 with the potential at the second node N2 and the second electrode 12 with the potential at the first node N1 constitute a first capacitor.

[0292] In an exemplary embodiment, since the third electrode 13, serving as the lower electrode, has a potential at the second node N2, and the fourth electrode 14, serving as the middle electrode, has a potential at the first node N1, the third electrode 13 with the potential at the second node N2 and the fourth electrode 14 with the potential at the first node N1 constitute the first sub-capacitor of the second capacitor. Since the fourth electrode 14, serving as the middle electrode, has a potential at the first node N1, and the fifth electrode 15, serving as the upper electrode, has a potential at the second node N2, the fourth electrode 14 with the potential at the first node N1 and the fifth electrode 15 with the potential at the second node N2 constitute the second sub-capacitor of the second capacitor.

[0293] In an exemplary embodiment, the first sub-capacitor and the second sub-capacitor are connected in parallel. This disclosure utilizes a first conductive layer, a second conductive layer, and a third conductive layer to form a first sub-capacitor and a second sub-capacitor connected in parallel. The first sub-capacitor and the second sub-capacitor in parallel constitute the second capacitor. On the one hand, this can effectively increase the capacitance value of the second capacitor. On the other hand, it can reduce the plate area while ensuring the capacitance value of the second capacitor, thus effectively reducing the occupied area.

[0294] In an exemplary embodiment, the first capacitor and the second capacitor are connected in parallel. This disclosure, by setting the first and second capacitors in a parallel structure, constitutes the complete storage capacitor of the pixel driving circuit. This effectively increases the capacitance value of the storage capacitor and reduces the electrode area while maintaining the storage capacitance, thus effectively reducing the occupied area. Furthermore, the first capacitor is a transparent capacitor, and a portion of the transparent capacitor is disposed in the light-transmitting area, which effectively increases the capacity of the storage capacitor with minimal impact on transmittance.

[0295] In an exemplary embodiment, the first capacitor may have a first capacitance value Cst1, the second capacitor may have a second capacitance value Cst2, and the storage capacitance value Cst of the storage capacitor is Cst = Cst1 + Cst2. Since the first capacitor is located in the light-transmitting area, the first capacitance value Cst1 can be determined by the magnitudes of the storage capacitance value Cst and the second capacitance value Cst2. The area of ​​the two transparent plates of the first capacitor can be adjusted in the light-transmitting area according to actual conditions. Since the second capacitor is located in the display area, the magnitude of the second capacitance value Cst2 is actually determined by the sub-pixel layout space. When there is sufficient horizontal space in the sub-pixel, the area of ​​the three plates of the second capacitor can be appropriately increased in the first direction X. When there is sufficient vertical space in the sub-pixel, the area of ​​the three plates of the second capacitor can be appropriately increased in the second direction Y. In this way, the area of ​​the three plates of the second capacitor can be minimized to maximize the area of ​​the light-transmitting area.

[0296] In an exemplary embodiment, the third conductive layer of each repeating unit in the display substrate may further include at least one auxiliary connection electrode 82.

[0297] In an exemplary embodiment, the auxiliary connection electrode 82 is generally T-shaped and may include an auxiliary connection strip 82-1 and an auxiliary connection block 82-2. The auxiliary connection strip 82-1 may be a strip extending along a first direction X. The first end of the auxiliary connection strip 82-1 is connected to the second power line 72, and the second end of the auxiliary connection strip 82-1 extends away from the second power line 72 into the adjacent light-transmitting area 120, where it connects to the auxiliary connection block 82-2. The auxiliary connection block 82-2 may be block-shaped (e.g., rectangular) and is disposed in the light-transmitting area 120. The auxiliary connection block 82-2 is configured to connect to a subsequently formed auxiliary cathode.

[0298] In an exemplary embodiment, at least one repeating unit may have five auxiliary connection electrodes 82. For example, two auxiliary connection electrodes 82 may be provided in the first sub-pixel P1, two auxiliary connection electrodes 82 may be provided in the fourth sub-pixel P4, and one auxiliary connection electrode 82 may be provided between the second sub-pixel P2 and the third sub-pixel P3.

[0299] In an exemplary embodiment, in at least one sub-pixel, the auxiliary connecting strip 82-1 and the auxiliary connecting block 82-2 can be an integral structure that is interconnected.

[0300] In an exemplary embodiment, in at least one repeating unit, the second power line 72 and the auxiliary connection electrode 82 can be an integral structure that is interconnected.

[0301] (17) Forming a fourth insulating layer and a first planarization layer pattern. In an exemplary embodiment, forming a fourth insulating layer and a first planarization layer pattern may include: depositing a fourth insulating film on a substrate on which the aforementioned pattern is formed, then coating a first planarization film, and patterning the fourth insulating film and the first planarization film by a patterning process to form a fourth insulating layer covering a third conductive layer and a first planarization layer pattern disposed on the fourth insulating layer. A plurality of vias are provided on the fourth insulating layer and the first planarization layer, as shown in FIG13.

[0302] In an exemplary embodiment, at least one repeating unit may include four twenty-first vias V21 and five twenty-second vias V22.

[0303] In an exemplary embodiment, the orthographic projection of each 21-th via V21 onto the substrate is within the range of the orthographic projection of the electrode connecting block 81-2 of the electrode connecting electrode 81 onto the substrate. The fourth insulating layer and the first planarization layer within the 21-th via V21 are removed, exposing the surface of the electrode connecting block 81-2. The 21-th via V21 is configured to allow the subsequently formed anode connecting electrode to be connected to the electrode connecting block 81-2 through the via.

[0304] In an exemplary embodiment, the orthographic projection of each 22nd via V22 onto the substrate is within the range of the orthographic projection of the auxiliary connection block 82-2 of the auxiliary connection electrode 82 onto the substrate. The fourth insulating layer and the first planarization layer within the 22nd via V22 are removed, exposing the surface of the auxiliary connection block 82-2. The 22nd via V22 is configured to allow the subsequently formed auxiliary cathode to be connected to the auxiliary connection block 82-2 through the via.

[0305] In an exemplary embodiment, the patterning process may employ a half-tone mask process.

[0306] In an exemplary embodiment, the display substrate may further include a color filter layer. On a substrate with the aforementioned pattern, a fourth insulating layer is first formed, and then a color filter layer is formed on the fourth insulating layer by a patterning process. The color filter layer may include at least a red filter, a blue filter, and a green filter. Subsequently, a planarization film is coated, and the planarization film and the fourth insulating film are patterned using a patterning process to form a fourth insulating layer covering the third conductive layer, a color filter layer disposed on the fourth insulating layer, and a planarization layer pattern covering the color filter layer. Multiple vias are formed on the planarization layer and the fourth insulating layer.

[0307] In an exemplary embodiment, the first planarization layer and the color filter layer may be provided only in the display area 110, and the first planarization layer and the color filter layer located in the light-transmitting area 120 are completely removed, including the area where the electrode plate connecting electrode 81 and the auxiliary connecting electrode 82 are located.

[0308] (18) Forming a second transparent conductive layer pattern. In an exemplary embodiment, forming a second transparent conductive layer pattern may include: depositing a second transparent conductive film on a substrate on which the aforementioned pattern is formed, and patterning the second transparent conductive film using a patterning process to form a second transparent conductive layer pattern, as shown in Figures 14A and 14B, where Figure 14B is a schematic diagram of the second transparent conductive layer in Figure 14A. In an exemplary embodiment, the second transparent conductive layer may be referred to as a 2nd ITO layer.

[0309] In an exemplary embodiment, the second transparent conductive layer of each sub-pixel in the display substrate may include at least an anode 91 and an anode connection electrode 92.

[0310] In an exemplary embodiment, the anode 91 in at least one sub-pixel may include a first sub-anode 91-1 and a second sub-anode 91-2 that are isolated from each other. The first sub-anode 91-1 and the second sub-anode 91-2 may be rectangular in shape, located in the display area 110, and disposed on the first flat layer. The first sub-anode 91-1 and the second sub-anode 91-2 may be disposed sequentially along the second direction Y.

[0311] In an exemplary embodiment, the anode connection electrode 92 may be C-shaped, disposed on the fourth insulating layer, and protrude toward the light-transmitting area 120 of the repeating unit. The orthographic projection of the anode connection electrode 92 on the substrate at least partially overlaps with the orthographic projection of the light-transmitting area 120 on the substrate. The anode connection electrode 92 may include a first sub-connection electrode 92-1, a second sub-connection electrode 92-2, and a third sub-connection electrode 92-3. The first sub-connection electrode 92-1 and the second sub-connection electrode 92-2 may be strip-shaped extending along a first direction X, and the third sub-connection electrode 92-3 may be strip-shaped extending along a second direction Y. The first end of the first sub-connecting electrode 92-1 is connected to the first sub-anode 91-1, and the first end of the second sub-connecting electrode 92-2 is connected to the second sub-anode 91-2. The second ends of both the first and second sub-connecting electrodes 92-1 and 92-2 extend into the light-transmitting area 120 of this repeating unit and are then connected to the first and second ends of the third sub-connecting electrode 92-3, respectively. The third sub-connecting electrode 92-3 is connected to the electrode plate connecting block 81-2 through the twenty-first through-hole V21. In an exemplary embodiment, the anode connecting electrode 92 enables the interconnection between the first sub-anode 91-1 and the second sub-anode 91-2. Since the electrode plate connecting block 81-2 is connected to the fifth electrode plate 15 through the electrode plate connecting strip 81-1, and the anode connecting electrode 92 is connected to the anode 91, the connection between the anode 91 and the fifth electrode plate 15 of the storage capacitor is achieved.

[0312] In an exemplary embodiment, the electrode plate connecting electrode 81 and the anode connecting electrode 92 can serve as the third protruding structure of this disclosure. That is, the third protruding structure may include the electrode plate connecting electrode 81 and the anode connecting electrode 92 located in different conductive layers. The third protruding structure protrudes toward the light-transmitting region 120 of this repeating unit, and the orthographic projection of the third protruding structure on the substrate at least partially overlaps with the orthographic projection of the light-transmitting region 120 on the substrate, so as to weaken the diffraction effect and improve the transparent display effect.

[0313] In an exemplary embodiment, the edge of the first sub-connecting electrode 92-1 near the electrode connecting strip 81-1 may have a fifth protrusion width D5 between the edge of the electrode connecting strip 81-1 near the first sub-connecting electrode 92-1, or the edge of the second sub-connecting electrode 92-2 near the electrode connecting strip 81-1 may have a fifth protrusion width D5 between the edge of the second sub-connecting electrode 92-2 near the electrode connecting strip 81-1 and the edge of the electrode connecting strip 81-1 near the second sub-connecting electrode 92-2.

[0314] In an exemplary embodiment, the first protrusion width D1 can be greater than the fifth protrusion width D5, the second protrusion width D2 can be greater than the fifth protrusion width D5, the third protrusion width D3 can be greater than the fifth protrusion width D5, and the fourth protrusion width D4 can be greater than the fifth protrusion width D5. This not only helps to weaken the diffraction effect and improve the transparent display effect, but also facilitates the repair of the scanning signal lines.

[0315] In an exemplary embodiment, when a bright spot defect occurs on the display substrate, the anode connection electrode 92 can be cut off by laser cutting, so that one of the first sub-anode 91-1 and the second sub-anode 91-2 is connected to the fifth electrode plate 15, while the other is floating, thereby repairing the bright spot defect.

[0316] In an exemplary embodiment, the twenty-first via V21 can be referred to as an anode via. The orthographic projection of the anode via on the substrate does not overlap with the orthographic projections of the first sub-anode 91-1 and the second sub-anode 91-2 on the substrate. This not only improves the success rate of repairing defective bright spots and avoids the impact of repair on the pixel driving circuit, but also ensures the flatness of the anode, improves the light output quality of the light-emitting device, and enhances the display effect.

[0317] In an exemplary embodiment, the four anodes 91 in the repeating unit are arranged vertically. The anode 91 in the first sub-pixel P1 is connected to the pixel driving circuit in that sub-pixel, the anode 91 in the second sub-pixel P2 is connected to the pixel driving circuit in that sub-pixel, the anode 91 in the third sub-pixel P3 is connected to the pixel driving circuit in that sub-pixel, and the anode 91 in the fourth sub-pixel P4 is connected to the pixel driving circuit in that sub-pixel. In some possible implementations, the arrangement of the anodes can be adjusted according to actual needs, and this disclosure does not specifically limit it.

[0318] In an exemplary embodiment, the first sub-anode 91-1, the second sub-anode 91-2, and the anode connection electrode 92 in each sub-pixel can be an integral structure that is interconnected.

[0319] In an exemplary embodiment, the second transparent conductive layer of at least one repeating unit may further include an auxiliary cathode 93. The auxiliary cathode 93 may be block-shaped (e.g., rectangular), and the orthographic projection of the auxiliary cathode 93 on the substrate at least partially overlaps with the orthographic projection of the auxiliary connecting block 82-2 on the substrate. The auxiliary cathode 93 may be connected to the auxiliary connecting block 82-2 through the 22nd via V22, and the auxiliary cathode 93 is configured to be connected to the subsequently formed cathode.

[0320] In an exemplary embodiment, the auxiliary cathode 93 can adopt an isolation pillar (RIB) structure. The cross-sectional shape of the auxiliary cathode 93 can be an inverted trapezoid, so that the organic light-emitting layer formed subsequently can be broken at the side edge of the auxiliary cathode 93 to form an isolated and isolated organic light-emitting block. This effectively avoids the interference of the organic light-emitting block on the emitted light, improves the quality of the emitted light, and is beneficial to improving the display quality.

[0321] In an exemplary embodiment, the auxiliary cathode is also configured to reduce the diffraction effect in the transparent area. By setting the auxiliary cathode in the transparent area, the transparent area is changed from a regular rectangle to an irregular shape, and different positions in the transparent area have different slit widths. When light passes through the irregularly shaped transparent area, because the positions and directions of the diffraction fringes are different, the light does not diffuse in one direction but in multiple directions, greatly weakening the diffraction effect, avoiding the blurring of objects behind the screen, and improving the transparent display effect.

[0322] In an exemplary embodiment, the shape of the auxiliary cathode on a plane parallel to the substrate may include any one or more of the following: circular, elliptical, rectangular, trapezoidal, pentagonal, and hexagonal.

[0323] In an exemplary embodiment, the material of the second transparent conductive layer can be a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0324] (19) Forming a pixel definition layer. In an exemplary embodiment, forming a pixel definition layer pattern may include: coating a pixel definition film on a substrate on which the aforementioned pattern is formed, and patterning the pixel definition film using a patterning process to form a pixel definition layer, as shown in FIG15.

[0325] In an exemplary embodiment, a first pixel opening K1 and a second pixel opening K2 are provided on the pixel definition layer of each sub-pixel in the display substrate. The pixel definition film in the first pixel opening K1 is removed to expose a portion of the surface of the first sub-anode 91-1 in the anode 91. The pixel definition film in the second pixel opening K2 is removed to expose a portion of the surface of the second sub-anode 91-2 in the anode 91.

[0326] In an exemplary embodiment, the orthographic projection of the first pixel opening K1 onto the substrate is within the range of the orthographic projection of the first sub-anode 91-1 onto the substrate, and the orthographic projection of the second pixel opening K2 onto the substrate is within the range of the orthographic projection of the second sub-anode 91-2 onto the substrate.

[0327] In an exemplary embodiment, in a plane parallel to the substrate, the shapes of the first pixel opening K1 and the second pixel opening K2 can be similar to the shape of the sub-anode, and in a direction perpendicular to the substrate, the cross-sectional shapes of the first pixel opening K1 and the second pixel opening K2 can be rectangular or trapezoidal, etc.

[0328] In an exemplary embodiment, the pixel definition layer of the light-transmitting region 120 is essentially removed, forming a plurality of light-transmitting openings T.

[0329] In an exemplary embodiment, at least one light-transmitting opening T may be provided with a groove on the side near the display area 110. The groove is recessed in a direction away from the display area 110. The orthogonal projection of the groove on the substrate includes the orthogonal projection of the anode connection electrode 92, the first protrusion structure and the second protrusion structure on the substrate. That is, the area where the anode connection electrode 92, the first protrusion structure and the second protrusion structure are located in the light-transmitting area 120 is covered by the pixel definition layer.

[0330] In an exemplary embodiment, the orthographic projection of the light-transmitting opening T on the substrate does not overlap with the orthographic projection of the scan transmission line 36 on the substrate, that is, the area where the scan transmission line 36 is located in the light-transmitting area 120 is covered by the pixel definition layer.

[0331] In an exemplary embodiment, the orthographic projection of the light-transmitting opening T in the light-transmitting region 120 onto the substrate includes the orthographic projection of the auxiliary cathode 93 onto the substrate, that is, the light-transmitting opening T exposes the surfaces of the plurality of auxiliary cathodes 93.

[0332] In an exemplary embodiment, the pixel definition layer may be made of polyimide, acrylic, or polyethylene terephthalate, etc.

[0333] Subsequently, an organic light-emitting layer pattern and a cathode pattern are formed. In an exemplary embodiment, forming the organic light-emitting layer and cathode pattern may include: first, forming the organic light-emitting layer pattern in the display area, wherein the organic light-emitting layer is connected to a first sub-anode and a second sub-anode through a first pixel opening and a second pixel opening, respectively. Then, a cathode is formed; in the display area, the cathode is connected to the organic light-emitting layer, and in the light-transmitting area, the cathode is connected to a plurality of auxiliary cathodes. Since the auxiliary cathodes are connected to auxiliary connection electrodes, and the auxiliary connection electrodes are connected to a second power line, the connection between the cathode and the second power line is achieved.

[0334] In an exemplary embodiment, the organic light-emitting layer may include an emissive layer (EML), and any one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, the organic light-emitting layer may be formed by vapor deposition using a fine metal mask (FMM) or an open mask, or by inkjet printing.

[0335] In an exemplary embodiment, the fabrication process of the display substrate may further include forming an encapsulation structure layer pattern. Forming the encapsulation structure layer pattern may include: firstly, depositing a first inorganic thin film using an open mask to form a first encapsulation layer; subsequently, using an inkjet printing process to print an organic material onto the first encapsulation layer, and after curing, forming a second encapsulation layer; subsequently, depositing a second inorganic thin film using an open mask to form a third encapsulation layer, wherein the first, second, and third encapsulation layers constitute the encapsulation structure layer. The first and third encapsulation layers may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), silicon carbide (SiC), silicon carbonitride (SiCN), and silicon oxynitride (SiON), and may be single-layer, multi-layer, or composite layers. The second encapsulation layer may be made of a resin material, forming an inorganic / organic / inorganic material stacked structure. The organic material layer is disposed between the two inorganic material layers to ensure that external moisture cannot enter the light-emitting device.

[0336] This completes the fabrication of the display substrate for this embodiment.

[0337] In an exemplary embodiment, the display substrate may include at least: a substrate, a first transparent conductive layer disposed on the substrate, a first conductive layer disposed on the side of the first transparent conductive layer away from the substrate, a first insulating layer disposed on the side of the first conductive layer away from the substrate, a semiconductor layer disposed on the side of the first insulating layer away from the substrate, a second insulating layer disposed on the side of the semiconductor layer away from the substrate, a second conductive layer disposed on the side of the second insulating layer away from the substrate, a third insulating layer disposed on the side of the second conductive layer away from the substrate, a third conductive layer disposed on the side of the third insulating layer away from the substrate, a fourth insulating layer disposed on the side of the third conductive layer away from the substrate, a first planarization layer disposed on the side of the fourth insulating layer away from the substrate, and a second transparent conductive layer disposed on the side of the first planarization layer away from the substrate.

[0338] In an exemplary embodiment, the first transparent conductive layer may include at least a first electrode 11, the first conductive layer may include at least a third electrode 13, a first data signal line 61 to a fourth data signal line 64, and a first power line 71, the semiconductor layer may include at least a second electrode 12, a first active layer 21, a second active layer 22, and a third active layer 23, the second conductive layer may include at least a fourth electrode 14, a second gate electrode 32, and a scan signal line 30, the third conductive layer may include at least a fifth electrode 15, a second power line 72, a compensation signal line 73, and a plurality of connection electrodes, and the second transparent conductive layer may include at least an anode 91 and an anode connection electrode 92.

[0339] In an exemplary embodiment, the substrate can be a flexible substrate or a rigid substrate. The rigid substrate can be, but is not limited to, one or more of glass and quartz, while the flexible substrate can be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In an exemplary embodiment, the flexible substrate can include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first and second flexible material layers can be polyimide (PI), polyethylene terephthalate (PET), or surface-treated polymer films, etc. The materials of the first and second inorganic material layers can be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The material of the semiconductor layer can be amorphous silicon (a-Si).

[0340] In an exemplary embodiment, the first conductive layer, the second conductive layer, and the third conductive layer can be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). They can be single-layer structures or multi-layer composite structures, such as Mo / Cu / Mo. The first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON). They can be single-layer, multi-layer, or composite layers. The first planarization layer can be made of organic materials, such as resin.

[0341] This exemplary embodiment provides a top-emitting display substrate. By arranging all pixel driving circuits on one side and all vertical traces on the other side through the overall layout of repeating units, the area of ​​the light-transmitting region can be maximized, thereby improving transmittance. This disclosure divides the repeating units into a light-transmitting region, a first region, and a second region arranged sequentially along a first direction. The first region houses a storage capacitor and multiple transistors, while the second region houses multiple vertical signal lines. The structure is simple and the layout is reasonable, making full use of the layout space and improving space utilization. This effectively reduces the space occupied by the display area, maximizing the area of ​​the light-transmitting region and contributing to improved resolution and transparency.

[0342] This disclosure displays a pixel driving circuit with a single scan signal line. This scan signal line is connected to the first and third transistors in the pixel driving circuit. By reducing the number of scan signal lines, not only can the structure of the pixel driving circuit be simplified and its occupied area reduced, which is beneficial for achieving high-resolution displays, but the light-transmitting area of ​​the light-transmitting region can also be effectively increased, improving the space ratio of the light-transmitting region and facilitating high-transparency displays. Furthermore, since only one scan signal line is needed to drive a repeating unit, the number of its corresponding gate driving circuit (GOA) and clock signal line (CLK) can be reduced significantly, effectively reducing the occupied area of ​​the gate driving circuit and clock signal line, which is beneficial for achieving narrow bezels and enhancing product advantages.

[0343] This disclosed display substrate, by setting a single-line structure for the scanning transmission line in the light-transmitting area and a double-ring structure with a first ring structure and a second ring structure in the display area, not only ensures that the scanning signal line drives all pixel driving circuits in the repeating area, but also realizes multi-channel function, which can repair signal lines at all positions, realize full signal defect repair, and effectively improve product yield.

[0344] The display substrate of this disclosure utilizes a first capacitor and a second capacitor to form a storage capacitor, and the first capacitor is a transparent capacitor. A portion of the transparent capacitor is disposed in the light-transmitting area, which can effectively increase the capacity of the storage capacitor with minimal impact on the transmittance.

[0345] The present disclosure displays a second capacitor formed by a three-layer metal sandwich structure using a first conductive layer, a second conductive layer, and a third conductive layer. The second capacitor consists of a first sub-capacitor and a second sub-capacitor connected in parallel. On the one hand, this can effectively increase the capacitance value of the second capacitor, and on the other hand, it can reduce the plate area while ensuring the capacitance value of the second capacitor, thereby effectively reducing the area occupied by the pixel driving circuit and facilitating the realization of high-resolution display.

[0346] The display substrate of this disclosure saves the number of signal lines and reduces the space occupied by setting a one-to-four structure for the first power line and a one-to-four structure for the compensation signal line. The structure is simple, the layout is reasonable, and the layout space is fully utilized, which improves the space utilization rate and helps to improve the resolution.

[0347] The display substrate disclosed herein connects the first sub-anode and the second sub-anode respectively by setting an anode connecting electrode. This not only improves the success rate of repairing bright spots and avoids the impact of repair on the pixel driving circuit, but also avoids causing other defects. The repair success rate is high, and the flatness of the anode can be guaranteed, improving the light output quality of the light-emitting device and enhancing the display effect.

[0348] The display substrate disclosed herein, by providing a second power line and an auxiliary cathode, with the second power line connected to the cathode via the auxiliary cathode, can effectively reduce the voltage drop of the second power supply and ensure display uniformity.

[0349] The display substrate disclosed herein transforms the light-transmitting area into an irregular shape by placing an anode connecting electrode, an auxiliary cathode, a first protruding structure, and a second protruding structure in the light-transmitting area. When light passes through the irregularly shaped light-transmitting area, the diffraction fringes are generated at different positions and in different directions. Therefore, the light does not diffuse in one direction but diffuses in multiple directions, thus greatly weakening the diffraction effect, avoiding the blurring of objects behind the screen, and improving the transparent display effect.

[0350] The preparation process of the exemplary embodiments disclosed herein is well compatible with existing preparation processes, is simple to implement, easy to carry out, has high production efficiency, low production cost, and high yield.

[0351] Figure 16 is a schematic diagram of another display substrate structure according to an exemplary embodiment of the present disclosure, illustrating the structure of a repeating unit. As shown in Figure 16, the main structure of the display substrate in this embodiment is basically the same as that in the embodiment shown in Figure 5. The difference is that the second capacitor in this embodiment is formed by a first conductive layer, a semiconductor layer, and a third conductive layer.

[0352] Figure 17 is a schematic diagram of another storage capacitor structure in an exemplary embodiment of the present disclosure, and is a cross-sectional view along the BB direction in Figure 16. As shown in Figures 16 and 17, at least one pixel driving circuit may include a first capacitor 10-1 and a second capacitor 10-2, wherein the first capacitor 10-1 and the second capacitor 10-2 are connected in parallel, and together they constitute the storage capacitor of the pixel driving circuit.

[0353] In an exemplary embodiment, the first capacitor 10-1 may include a first electrode 11 and a second electrode 12 stacked together, and the second capacitor 10-2 may include a third electrode 13, a fourth electrode 14 and a fifth electrode 15 stacked together. The first electrode 11 and the third electrode 13 are connected, the third electrode 13 and the fifth electrode 15 are connected, and the second electrode 12 and the fourth electrode 14 are connected. Therefore, the first electrode 11, the third electrode 13 and the fifth electrode 15 have the same potential, and the second electrode 12 and the fourth electrode 14 have the same potential. The first capacitor 10-1 and the second capacitor 10-2 in parallel structure form a complete storage capacitor.

[0354] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate may include at least: a substrate 300, a first transparent conductive layer, a first conductive layer, a first insulating layer 301, a semiconductor layer, a second insulating layer 302, a second conductive layer, a third insulating layer 303, and a third conductive layer.

[0355] In an exemplary embodiment, the first transparent conductive layer may include at least a first electrode 11, and the first conductive layer may include at least a third electrode 13, with the third electrode 13 overlapping the first electrode 11.

[0356] In an exemplary embodiment, the semiconductor layer may include at least a second electrode 12, a fourth electrode 14, a second active layer 22, and a third active layer 23. The second conductive layer may include at least a second gate electrode 32. The third conductive layer may include at least a fifth electrode 15, an eighth connection electrode 48, and a tenth connection electrode. The fifth electrode 15 is connected to both the third active layer 23 and the third electrode 13 through a sixth via V6. The eighth connection electrode 48 is connected to both the second electrode 12 and the second gate electrode 32 through a seventh via V7. The tenth connection electrode is connected to both the fourth electrode 14 and the second gate electrode 32 through a via. Thus, the third electrode 13 and the fifth electrode 15 have the same potential, and the second electrode 12 and the fourth electrode 14 have the same potential.

[0357] In an exemplary embodiment, the fabrication process of the display substrate may include the following operations.

[0358] (21) Forming a first transparent conductive layer pattern. In the exemplary embodiment, the process of forming the first transparent conductive layer and the formed first transparent conductive layer pattern are basically the same as those in the embodiment shown in FIG5, and will not be described again here.

[0359] (22) Forming a first conductive layer pattern. In the exemplary embodiment, the process of forming the first conductive layer and the formed first conductive layer pattern are basically the same as those in the embodiment shown in FIG5, and will not be described again here.

[0360] (23) Forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern may include: depositing a first insulating film and a semiconductor film sequentially on a substrate on which the aforementioned pattern is formed, patterning the semiconductor film by a patterning process to form a first insulating layer covering a first conductive layer, and a semiconductor layer disposed on the first insulating layer, as shown in Figures 18A and 18B, where Figure 18B is a schematic diagram of the semiconductor layer in Figure 18A.

[0361] In an exemplary embodiment, the semiconductor layer of each sub-pixel in the display substrate may include at least a first active layer 21, a second active layer 22, a third active layer 23, a second electrode plate 12 of the storage capacitor, and a fourth electrode plate 14 of the storage capacitor. The structures of the first active layer 21, the second active layer 22, the third active layer 23, and the second electrode plate 12 are substantially the same as those in the embodiment shown in FIG. 5.

[0362] In an exemplary embodiment, the first active layer 21 and the third active layer 23 may be strip-shaped extending along the second direction Y, and the second active layer 22 may be strip-shaped extending along the first direction X or rectangular.

[0363] In an exemplary embodiment, the fourth electrode plate 14 may be rectangular in shape, and the corners of the rectangle may be chamfered or grooved. The orthographic projection of the fourth electrode plate 14 on the substrate at least partially overlaps with the orthographic projection of the third electrode plate 13 on the substrate. The fourth electrode plate 14 may serve as an intermediate electrode plate for the second capacitor. The fourth electrode plate 14 is configured to form a first sub-capacitor of the second capacitor together with the third electrode plate 13, and is also configured to form a second sub-capacitor of the second capacitor together with the subsequently formed fifth electrode plate.

[0364] In an exemplary embodiment, in at least one sub-pixel, the second region of the first active layer may be connected to the fourth electrode plate 14.

[0365] In an exemplary embodiment, in at least one sub-pixel, the fourth electrode plate 14 and the first active layer 21 can be an integral structure that is interconnected.

[0366] (24) Forming a second conductive layer pattern. In an exemplary embodiment, forming a second conductive layer pattern may include: depositing a second insulating film and a second conductive film sequentially on a substrate on which the aforementioned pattern is formed, patterning the second conductive film by a patterning process to form a second insulating layer covering the semiconductor layer, and a second conductive layer pattern disposed on the second insulating layer, as shown in Figures 19A and 19B, where Figure 19B is a schematic diagram of the second conductive layer in Figure 19A.

[0367] In an exemplary embodiment, the second conductive layer of each sub-pixel in the display substrate may include at least a gate electrode line 31, a second gate electrode 32, and a fourth connecting electrode 44. The structure and connection relationship of the gate electrode line 31 and the fourth connecting electrode 44 are basically the same as those in the embodiment shown in FIG. 5. Unlike the embodiment shown in FIG. 5, since the fourth electrode plate is disposed in the semiconductor layer, and the fourth electrode plate and the first active layer are an integral structure interconnected, the second conductive layer of this embodiment does not contain a fourth electrode plate and a third connecting electrode.

[0368] In an exemplary embodiment, the shape of the second gate electrode 32 can be an "L" shape extending along the second direction Y. The orthographic projection of the first end of the second gate electrode 32 on the substrate at least partially overlaps with the orthographic projection of the fourth electrode plate 14 on the substrate. The orthographic projection of the second end of the second gate electrode 32 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate 12 on the substrate. The orthographic projection of the region between the first end and the second end of the second gate electrode 32 on the substrate at least partially overlaps with the orthographic projection of the second active layer 22 on the substrate. The second gate electrode 32 serves as the gate electrode of the second transistor T2.

[0369] In an exemplary embodiment, the second conductive layer of each repeating unit in the display substrate may further include two first scan connection lines 33, two second scan connection lines 34, a ring connection line 35, and a scan transmission line 36. The above structure and its connection relationship are basically the same as those in the embodiment shown in FIG5. In the first sub-pixel P1 and the second sub-pixel P2, the two gate electrode lines 31, the first scan connection lines 33, and the second scan connection lines 34 constitute a first ring structure 30A. In the third sub-pixel P3 and the fourth sub-pixel P4, the two gate electrode lines 31, the first scan connection lines 33, and the second scan connection lines 34 constitute a second ring structure 30B.

[0370] In an exemplary embodiment, each repeating unit in the display substrate may further include a first protrusion structure 37 and a second protrusion structure 38, and the above structures and their connection relationships are basically the same as those in the embodiment shown in FIG5.

[0371] (25) Forming a third insulating layer pattern. In an exemplary embodiment, forming a third insulating layer pattern may include: depositing a third insulating film on a substrate on which the aforementioned pattern is formed, and patterning the third insulating film by a patterning process to form a third insulating layer pattern covering the second conductive layer, wherein a plurality of vias are provided on the third insulating layer, as shown in FIG20.

[0372] In an exemplary embodiment, the plurality of vias for each sub-pixel in the display substrate includes at least: a first via V1, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, and a thirteenth via V13. The structure and connection relationship of the first via V1, the third via V3 to the ninth via V9 are substantially the same as those in the embodiment shown in FIG. 5; that is, this embodiment does not have a second via V2, but it does have a thirteenth via V13.

[0373] In an exemplary embodiment, the orthographic projection of the thirteenth via V13 onto the substrate at least partially overlaps with the orthographic projections of the first end of the second gate electrode 32 and the fourth electrode plate 14 onto the substrate. The third and second insulating layers within the thirteenth via V13 are etched away, simultaneously exposing the first end of the second gate electrode 32 and the surface of the fourth electrode plate 14. The thirteenth via V13 is a transition via consisting of two half-holes, one exposing the surface of the second gate electrode 32 and the other exposing the surface of the fourth electrode plate 14. In an exemplary embodiment, the thirteenth via V13 is configured to allow a subsequently formed tenth connection electrode to connect simultaneously to the fourth electrode plate 14 and the second gate electrode 32 through this via.

[0374] In an exemplary embodiment, at least one repeating unit may further include a tenth via V10 disposed in the first sub-pixel P1, an eleventh via V11 disposed in the second sub-pixel P2, and a twelfth via V12 disposed in the third sub-pixel P3. The structure and connection relationship of the above vias are basically the same as those in the embodiment shown in FIG5.

[0375] (26) Forming a third conductive layer pattern. In an exemplary embodiment, forming a third conductive layer pattern may include: depositing a third conductive film on a substrate on which the aforementioned pattern is formed, patterning the third conductive film by a patterning process, and forming a third conductive layer pattern on a third insulating layer, as shown in Figures 21A and 21B, where Figure 21B is a schematic diagram of the third conductive layer in Figure 21A.

[0376] In an exemplary embodiment, the third conductive layer of each sub-pixel in the display substrate may include at least a fifth electrode 15 for storing capacitors, a sixth connecting electrode 46, a seventh connecting electrode 47, an eighth connecting electrode 48, a ninth connecting electrode 49, a tenth connecting electrode 50, a second power line 72, a compensation signal line 73, and an electrode connecting electrode 81. Except for the structure and connection relationship of the tenth connecting electrode 50, which is essentially the same as in the embodiment shown in FIG. 5, the third conductive layer in this embodiment does not have a fifth connecting electrode, but does have a tenth connecting electrode 50, because the fourth electrode is disposed in the semiconductor layer and the fourth electrode and the first active layer are an integral structure interconnected.

[0377] In an exemplary embodiment, the tenth connecting electrode 50 can be block-shaped (e.g., rectangular). The tenth connecting electrode 50 is connected to the fourth electrode plate 14 and the second gate electrode 32 simultaneously through the thirteenth via V13. Since the second gate electrode 32 is connected to the second electrode plate 12, and the fourth electrode plate 14 and the first active layer are interconnected as an integral structure, the interconnection between the second electrode of the first transistor T1, the gate electrode of the second transistor T2, the second electrode plate 12, and the fourth electrode plate 14 in each sub-pixel is realized, forming the first node N1 of the pixel driving circuit.

[0378] In an exemplary embodiment, the third conductive layer of each repeating unit in the display substrate may further include an eleventh connecting electrode 51, a twelfth connecting electrode 52, a thirteenth connecting electrode 53, a fourteenth connecting electrode 54, a fifteenth connecting electrode 55, a sixteenth connecting electrode 56, and an auxiliary connecting electrode 82. The above structure and its connection relationship are basically the same as those in the embodiment shown in FIG5.

[0379] In an exemplary embodiment, since the first electrode 11 is connected to the third electrode 13, the first electrode 11 has a potential at the second node N2. Since the second electrode 12 and the fourth electrode 14 are connected via the eighth connecting electrode 48 and the tenth connecting electrode 50, the second electrode 12 has a potential at the first node N1. Thus, the first electrode 11 with the potential at the second node N2 and the second electrode 12 with the potential at the first node N1 constitute a first capacitor.

[0380] In an exemplary embodiment, since the third electrode 13, serving as the lower electrode, has a potential at the second node N2, and the fourth electrode 14, serving as the middle electrode, has a potential at the first node N1, the third electrode 13 with the potential at the second node N2 and the fourth electrode 14 with the potential at the first node N1 constitute the first sub-capacitor of the second capacitor. Since the fourth electrode 14, serving as the middle electrode, has a potential at the first node N1, and the fifth electrode 15, serving as the upper electrode, has a potential at the second node N2, the fourth electrode 14 with the potential at the first node N1 and the fifth electrode 15 with the potential at the second node N2 constitute the second sub-capacitor of the second capacitor.

[0381] In an exemplary embodiment, the first sub-capacitor and the second sub-capacitor are connected in parallel.

[0382] In the exemplary embodiment, compared to the structure formed by stacked first conductive layer, second conductive layer and third conductive layer in the embodiment shown in FIG5, a first insulating layer and then a second insulating layer are spaced between the first conductive layer and the second conductive layer forming the first sub-capacitor. In this embodiment, the second capacitor is formed by stacked first conductive layer, semiconductor layer and third conductive layer, with only a first insulating layer separating the first conductive layer and the semiconductor layer forming the first sub-capacitor. Therefore, the structure of this embodiment can effectively increase the capacitance of the first sub-capacitor, effectively increase the capacitance of the second capacitor, and thus increase the capacitance of the storage capacitor. Furthermore, it can reduce the electrode area while maintaining the capacitance value of the storage capacitor, effectively reducing the area occupied by the pixel driving circuit, which is beneficial for achieving high-resolution display.

[0383] In an exemplary embodiment, subsequent fabrication processes may include forming a fourth insulating layer and a first planarization layer pattern, forming a second transparent conductive layer, forming a pixel definition layer, forming an organic light-emitting layer, forming a cathode, and forming an encapsulation structure layer, etc. The formation process is basically the same as that shown in the embodiment of FIG5, and will not be described again here.

[0384] This completes the fabrication of the display substrate for this embodiment. In this exemplary embodiment, the structure of the display substrate is essentially the same as that shown in FIG. 5. The difference is that the fourth electrode plate in this embodiment is disposed in the semiconductor layer.

[0385] The exemplary embodiments disclosed herein provide a top-emitting display substrate that not only has the technical effects of the embodiment shown in FIG5, but also effectively increases the capacity of the storage capacitor by forming a second capacitor with a sandwich structure through a first conductive layer, a semiconductor layer and a third conductive layer.

[0386] The structure and its preparation process described above in this disclosure are merely illustrative examples. In the exemplary embodiments, the corresponding structure and the patterning process can be changed or added or reduced according to actual needs, and this disclosure does not limit them.

[0387] In exemplary embodiments, the display substrate of this disclosure can be applied to display devices with pixel driving circuits, such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED) or quantum dot light-emitting diode display (QDLED), etc., and this disclosure does not limit it.

[0388] This disclosure also provides a method for fabricating a display substrate to prepare the display substrate provided in the above embodiments. In an exemplary embodiment, the display substrate includes a plurality of repeating units arranged in a regular pattern. At least one repeating unit includes a display area and a light-transmitting area disposed on one side of a first direction or on the opposite side of the first direction of the display area. The display area is configured to display an image, and the light-transmitting area is configured to transmit light. The display area includes a plurality of sub-pixels arranged sequentially along a second direction, wherein the first direction and the second direction intersect. The fabrication method may include:

[0389] A pixel driving circuit and a light-emitting device connected to the pixel driving circuit are formed in at least one sub-pixel. The pixel driving circuit is connected to a first power line, a data signal line, and a compensation signal line, respectively. The light-emitting device is connected to a second power line. The display area includes a first area and a second area disposed on the side of the first area away from the light-transmitting area. The pixel driving circuits of multiple sub-pixels are disposed in the first area, and the first power line, the second power line, the data signal line, and the compensation signal line are disposed in the second area.

[0390] This disclosure also provides a display device, which includes the aforementioned display substrate. The display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator, and the embodiments of the present invention are not limited thereto.

[0391] While the embodiments disclosed herein are as described above, it should be noted that these embodiments are merely exemplary and not restrictive. Therefore, this disclosure is not limited to the specific content shown and described herein. Various modifications, substitutions, or omissions can be made to the form and details of the embodiments without departing from the scope of this disclosure.

Claims

1. A display substrate comprising a plurality of repeating units arranged in a regular pattern, at least one repeating unit comprising a display area and a light-transmitting area disposed on one side of the display area in a first direction or on the opposite side of the first direction, the display area being configured to display an image, the light-transmitting area being configured to transmit light, the display area comprising a plurality of sub-pixels arranged sequentially along a second direction, the first direction and the second direction intersecting; at least one sub-pixel comprising a pixel driving circuit and a light-emitting device connected to the pixel driving circuit, the pixel driving circuit being connected to a first power line, a data signal line and a compensation signal line respectively, the light-emitting device being connected to a second power line; the display area comprising a first area and a second area disposed on the side of the first area away from the light-transmitting area, the pixel driving circuit of the plurality of sub-pixels being disposed in the first area, the first power line, the second power line, the data signal line and the compensation signal line being disposed in the second area.

2. The display substrate according to claim 1, wherein, In the first direction, the compensation signal line is disposed between the data signal line and the first power line, and the first power line is disposed between the compensation signal line and the second power line.

3. The display substrate according to claim 2, wherein, In a direction perpendicular to the display substrate, the display substrate includes a plurality of conductive layers disposed on the substrate, wherein the first power line and the data signal line are disposed in the same conductive layer, the compensation signal line and the second power line are disposed in the same conductive layer, and the first power line and the second power line are disposed in different conductive layers.

4. The display substrate according to claim 2, wherein, The data signal lines include a first data signal line, a second data signal line, a third data signal line, and a fourth data signal line arranged sequentially along the first direction; adjacent data signal lines have a first spacing, the fourth data signal line and the compensation signal line have a second spacing, the first power line and the compensation signal line have a third spacing, and the first power line and the second power line have a fourth spacing, wherein the second spacing is smaller than the first spacing, the third spacing is smaller than the first spacing, and the fourth spacing is smaller than the first spacing.

5. The display substrate according to claim 1, wherein, The pixel driving circuit includes at least a first transistor, a second transistor, a third transistor, and a storage capacitor. The first electrode of the first transistor is connected to the data signal line, the second electrode of the first transistor is connected to the gate electrode of the second transistor and the first terminal of the storage capacitor, the first electrode of the second transistor is connected to the first power line, the second electrode of the second transistor is connected to the second electrode of the third transistor and the second terminal of the storage capacitor, and the first electrode of the third transistor is connected to the compensation signal line. In the plurality of sub-pixels of at least one repeating unit, the gate electrodes of the plurality of first transistors and the gate electrodes of the plurality of third transistors are connected to the same scan signal line.

6. The display substrate according to claim 5, wherein, In at least one repeating unit, the scanning signal line includes a scanning transmission line disposed in the light-transmitting area and a first ring structure and a second ring structure disposed in the display area. The first end of the scanning transmission line is connected to the second ring structure in the repeating unit, and the second end of the scanning transmission line is connected to the second ring structure in the repeating unit adjacent in the first direction.

7. The display substrate according to claim 6, wherein, In at least one repeating unit and a repeating unit adjacent to the first direction, the scan transmission lines in the two repeating units are not on the same straight line extending along the first direction.

8. The display substrate according to claim 6, wherein, The display area includes a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel arranged sequentially along the second direction. The first ring structure is disposed in the first sub-pixel and the second sub-pixel, and the second ring structure is disposed in the third sub-pixel and the fourth sub-pixel. The first ring structure and the second ring structure are connected to each other by a ring connecting line.

9. The display substrate according to claim 8, wherein, In at least one repeating unit, the first ring structure, the second ring structure, and the ring connecting line are an integral structure that is interconnected.

10. The display substrate according to claim 8, wherein, The first ring structure or the second ring structure includes at least two gate electrode lines, a first scan connection line, and a second scan connection line. The gate electrode lines are straight or broken lines extending along the first direction. The two gate electrode lines are respectively disposed in two sub-pixels. The first scan connection line and the second scan connection line are straight or broken lines extending along the second direction. The first scan connection line is connected to the ends of the two gate electrode lines in the opposite direction of the first direction, and the second scan connection line is connected to the ends of the two gate electrode lines in the first direction, thus forming the first ring structure or the second ring structure.

11. The display substrate according to claim 10, wherein, In at least one repeating unit, the two gate electrode lines, one first scan connection line, and one second scan connection line in the first ring structure or the second ring structure are an integral structure that is interconnected.

12. The display substrate according to claim 10, wherein, The orthographic projections of the first ring structure and the second ring structure onto the display substrate plane at least partially overlap with the orthographic projections of the first power line, the second power line, the data signal line, and the compensation signal line onto the display substrate plane.

13. The display substrate according to claim 10, wherein, The first annular structure is provided with a first protruding structure, which protrudes toward the light-transmitting area. The orthographic projection of the first protruding structure on the display substrate plane overlaps at least partially with the orthographic projection of the light-transmitting area on the display substrate plane. And / or, a second protruding structure is provided on the second annular structure, the second protruding structure protrudes toward the light-transmitting area, and the orthographic projection of the second protruding structure on the display substrate plane at least partially overlaps with the orthographic projection of the light-transmitting area on the display substrate plane.

14. The display substrate according to claim 13, wherein, In at least one repeating unit, the protrusion lengths of the first protrusion structure and the second protrusion structure are different, and the protrusion length is the dimension in the first direction.

15. The display substrate according to claim 13, wherein, In at least one repeating unit, the first protrusion width and the second protrusion width in the first protrusion structure are different, wherein the first protrusion width is the dimension of the first protrusion structure located on the side of the gate electrode line away from the ring connection line, and the second protrusion width is the dimension of the first protrusion structure located on the side of the gate electrode line close to the ring connection line; and / or, the third protrusion width and the fourth protrusion width in the second protrusion structure are different, wherein the third protrusion width is the dimension of the second protrusion structure located on the side of the gate electrode line close to the ring connection line, and the fourth protrusion width is the dimension of the second protrusion structure located on the side of the gate electrode line away from the ring connection line.

16. The display substrate according to claim 15, wherein, At least one repeating unit further includes a third protruding structure, which is disposed on the side of the pixel driving circuit away from the first or second protruding structure. The third protruding structure protrudes toward the light-transmitting area, and its orthographic projection on the display substrate plane at least partially overlaps with the orthographic projection of the light-transmitting area on the display substrate plane. The electrode connecting electrode includes an electrode connecting strip and an electrode connecting block. The first end of the electrode connecting strip is connected to the fifth electrode of the storage capacitor, and the second end of the electrode connecting strip extends to the light-transmitting area and is connected to the electrode connecting block. The anode connecting electrode includes a first sub-connecting electrode, a second sub-connecting electrode, and a third sub-connecting electrode. The first end of the first sub-connecting electrode... The first sub-anode of the light-emitting device is connected to the first sub-anode of the light-emitting device, and the first end of the second sub-connecting electrode is connected to the second sub-anode of the light-emitting device. The second ends of the first and second sub-connecting electrodes extend to the light-transmitting area and are respectively connected to the first and second ends of the third sub-connecting electrode. The third sub-connecting electrode is connected to the electrode plate connecting block through a through hole. There is a fifth protrusion width between the first sub-connecting electrode and the electrode plate connecting strip or between the second sub-connecting electrode and the electrode plate connecting strip. The first protrusion width is greater than the fifth protrusion width, the second protrusion width is greater than the fifth protrusion width, the third protrusion width is greater than the fifth protrusion width, and the fourth protrusion width is greater than the fifth protrusion width.

17. The display substrate according to any one of claims 1 to 16, wherein, The storage capacitor includes a first capacitor and a second capacitor connected in parallel. The first capacitor includes a first electrode and a second electrode stacked on top of each other. The orthographic projections of the first electrode and the second electrode on the display substrate plane overlap. The second capacitor includes a third electrode, a fourth electrode, and a fifth electrode stacked on top of each other. The orthographic projections of the third electrode, the fourth electrode, and the fifth electrode on the display substrate plane overlap. The first electrode and the third electrode are connected, the third electrode and the fifth electrode are connected, and the second electrode and the fourth electrode are connected.

18. The display substrate according to claim 17, wherein, In a direction perpendicular to the display substrate, the display substrate includes at least a first transparent conductive layer disposed on a substrate, a first conductive layer disposed on a side of the first transparent conductive layer away from the substrate, and a semiconductor layer disposed on a side of the first conductive layer away from the substrate; a first electrode plate is disposed in the first transparent conductive layer, and a second electrode plate is disposed in the semiconductor layer, forming a transparent first capacitor.

19. The display substrate according to claim 18, wherein, The orthographic projections of the first electrode plate and the second electrode plate onto the substrate at least partially overlap with the orthographic projection of the light-transmitting region onto the substrate.

20. The display substrate according to claim 18, wherein, The display substrate further includes a second conductive layer disposed on the side of the semiconductor layer away from the substrate, and a third conductive layer disposed on the side of the second conductive layer away from the substrate; the third electrode plate is disposed in the first conductive layer, the fourth electrode plate is disposed in the second conductive layer, and the fifth electrode plate is disposed in the third conductive layer.

21. The display substrate according to claim 18, wherein, The display substrate further includes a second conductive layer disposed on the side of the semiconductor layer away from the substrate, and a third conductive layer disposed on the side of the second conductive layer away from the substrate; the third electrode plate is disposed in the first conductive layer, the fourth electrode plate is disposed in the semiconductor layer, and the fifth electrode plate is disposed in the third conductive layer.

22. A display device, wherein, Includes the display substrate as described in any one of claims 1 to 21.

23. A method for fabricating a display substrate, the display substrate comprising a plurality of repeating units arranged in a regular pattern, at least one repeating unit comprising a display area and a light-transmitting area disposed on one side of a first direction or on the opposite side of the first direction of the display area, the display area being configured to display an image, the light-transmitting area being configured to transmit light, the display area comprising a plurality of sub-pixels sequentially disposed along a second direction, the first direction and the second direction intersecting; the fabrication method comprising: A pixel driving circuit and a light-emitting device connected to the pixel driving circuit are formed in at least one sub-pixel. The pixel driving circuit is connected to a first power line, a data signal line, and a compensation signal line, respectively. The light-emitting device is connected to a second power line. The display area includes a first area and a second area disposed on the side of the first area away from the light-transmitting area. The pixel driving circuits of multiple sub-pixels are disposed in the first area, and the first power line, the second power line, the data signal line, and the compensation signal line are disposed in the second area.

Images